Patched in Tegra support.

58 files changed, 3014 insertions, 15462 deletions

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d4c12180c65..2e3b3d38c46 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -53,7 +53,6 @@ config AMBA_PL08X
         bool "ARM PrimeCell PL080 or PL081 support"
         depends on ARM_AMBA && EXPERIMENTAL
         select DMA_ENGINE
-        select DMA_VIRTUAL_CHANNELS
         help
           Platform has a PL08x DMAC device
           which can provide DMA engine support
@@ -90,23 +89,13 @@ config DW_DMAC
           Support the Synopsys DesignWare AHB DMA controller.  This
           can be integrated in chips such as the Atmel AT32ap7000.
 
-config DW_DMAC_BIG_ENDIAN_IO
-        bool "Use big endian I/O register access"
-        default y if AVR32
-        depends on DW_DMAC
-        help
-          Say yes here to use big endian I/O access when reading and writing
-          to the DMA controller registers. This is needed on some platforms,
-          like the Atmel AVR32 architecture.
-
-          If unsure, use the default setting.
-
 config AT_HDMAC
         tristate "Atmel AHB DMA support"
-        depends on ARCH_AT91
+        depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
         select DMA_ENGINE
         help
-          Support the Atmel AHB DMA controller.
+          Support the Atmel AHB DMA controller.  This can be integrated in
+          chips such as the Atmel AT91SAM9RL.
 
 config FSL_DMA
         tristate "Freescale Elo and Elo Plus DMA support"
@@ -135,7 +124,7 @@ config MV_XOR
 
 config MX3_IPU
         bool "MX3x Image Processing Unit support"
-        depends on ARCH_MXC
+        depends on ARCH_MX3
         select DMA_ENGINE
         default y
         help
@@ -160,20 +149,6 @@ config TXX9_DMAC
           Support the TXx9 SoC internal DMA controller.  This can be
           integrated in chips such as the Toshiba TX4927/38/39.
 
-config TEGRA20_APB_DMA
-        bool "NVIDIA Tegra20 APB DMA support"
-        depends on ARCH_TEGRA
-        select DMA_ENGINE
-        help
-          Support for the NVIDIA Tegra20 APB DMA controller driver. The
-          DMA controller is having multiple DMA channel which can be
-          configured for different peripherals like audio, UART, SPI,
-          I2C etc which is in APB bus.
-          This DMA controller transfers data from memory to peripheral fifo
-          or vice versa. It does not support memory to memory data transfer.
-
-
-
 config SH_DMAE
         tristate "Renesas SuperH DMAC support"
         depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
@@ -212,60 +187,43 @@ config TIMB_DMA
         help
           Enable support for the Timberdale FPGA DMA engine.
 
-config SIRF_DMA
-        tristate "CSR SiRFprimaII DMA support"
-        depends on ARCH_PRIMA2
-        select DMA_ENGINE
-        help
-          Enable support for the CSR SiRFprimaII DMA engine.
-
-config TI_EDMA
-        tristate "TI EDMA support"
-        depends on ARCH_DAVINCI
-        select DMA_ENGINE
-        select DMA_VIRTUAL_CHANNELS
-        default n
-        help
-          Enable support for the TI EDMA controller. This DMA
-          engine is found on TI DaVinci and AM33xx parts.
-
 config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
         bool
 
 config PL330_DMA
         tristate "DMA API Driver for PL330"
         select DMA_ENGINE
-        depends on ARM_AMBA
+        depends on PL330
         help
           Select if your platform has one or more PL330 DMACs.
           You need to provide platform specific settings via
           platform_data for a dma-pl330 device.
 
 config PCH_DMA
-        tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
+        tristate "Intel EG20T PCH / OKI Semi IOH(ML7213/ML7223) DMA support"
         depends on PCI && X86
         select DMA_ENGINE
         help
           Enable support for Intel EG20T PCH DMA engine.
 
-          This driver also can be used for LAPIS Semiconductor IOH(Input/
-          Output Hub), ML7213, ML7223 and ML7831.
-          ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
-          for MP(Media Phone) use and ML7831 IOH is for general purpose use.
-          ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
-          ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
+          This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
+          Output Hub), ML7213 and ML7223.
+          ML7213 IOH is for IVI(In-Vehicle Infotainment) use and ML7223 IOH is
+          for MP(Media Phone) use.
+          ML7213/ML7223 is companion chip for Intel Atom E6xx series.
+          ML7213/ML7223 is completely compatible for Intel EG20T PCH.
 
 config IMX_SDMA
         tristate "i.MX SDMA support"
-        depends on ARCH_MXC
+        depends on ARCH_MX25 || ARCH_MX3 || ARCH_MX5
         select DMA_ENGINE
         help
           Support the i.MX SDMA engine. This engine is integrated into
-          Freescale i.MX25/31/35/51/53 chips.
+          Freescale i.MX25/31/35/51 chips.
 
 config IMX_DMA
         tristate "i.MX DMA support"
-        depends on ARCH_MXC
+        depends on IMX_HAVE_DMA_V1
         select DMA_ENGINE
         help
           Support the i.MX DMA engine. This engine is integrated into
@@ -273,8 +231,7 @@ config IMX_DMA
 
 config MXS_DMA
         bool "MXS DMA support"
-        depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q
-        select STMP_DEVICE
+        depends on SOC_IMX23 || SOC_IMX28
         select DMA_ENGINE
         help
           Support the MXS DMA engine. This engine including APBH-DMA
@@ -287,45 +244,9 @@ config EP93XX_DMA
         help
           Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
 
-config DMA_SA11X0
-        tristate "SA-11x0 DMA support"
-        depends on ARCH_SA1100
-        select DMA_ENGINE
-        select DMA_VIRTUAL_CHANNELS
-        help
-          Support the DMA engine found on Intel StrongARM SA-1100 and
-          SA-1110 SoCs.  This DMA engine can only be used with on-chip
-          devices.
-
-config MMP_TDMA
-        bool "MMP Two-Channel DMA support"
-        depends on ARCH_MMP
-        select DMA_ENGINE
-        help
-          Support the MMP Two-Channel DMA engine.
-          This engine used for MMP Audio DMA and pxa910 SQU.
-
-          Say Y here if you enabled MMP ADMA, otherwise say N.
-
-config DMA_OMAP
-        tristate "OMAP DMA support"
-        depends on ARCH_OMAP
-        select DMA_ENGINE
-        select DMA_VIRTUAL_CHANNELS
-
-config MMP_PDMA
-        bool "MMP PDMA support"
-        depends on (ARCH_MMP || ARCH_PXA)
-        select DMA_ENGINE
-        help
-          Support the MMP PDMA engine for PXA and MMP platfrom.
-
 config DMA_ENGINE
         bool
 
-config DMA_VIRTUAL_CHANNELS
-        tristate
-
 comment "DMA Clients"
         depends on DMA_ENGINE
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7428feaa870..30cf3b1f0c5 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -2,7 +2,6 @@ ccflags-$(CONFIG_DMADEVICES_DEBUG)  := -DDEBUG
 ccflags-$(CONFIG_DMADEVICES_VDEBUG) += -DVERBOSE_DEBUG
 
 obj-$(CONFIG_DMA_ENGINE) += dmaengine.o
-obj-$(CONFIG_DMA_VIRTUAL_CHANNELS) += virt-dma.o
 obj-$(CONFIG_NET_DMA) += iovlock.o
 obj-$(CONFIG_INTEL_MID_DMAC) += intel_mid_dma.o
 obj-$(CONFIG_DMATEST) += dmatest.o
@@ -15,22 +14,15 @@ obj-$(CONFIG_DW_DMAC) += dw_dmac.o
 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
 obj-$(CONFIG_MX3_IPU) += ipu/
 obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
-obj-$(CONFIG_SH_DMAE) += sh/
+obj-$(CONFIG_SH_DMAE) += shdma.o
 obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
 obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
 obj-$(CONFIG_IMX_DMA) += imx-dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
-obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
-obj-$(CONFIG_TI_EDMA) += edma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
-obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
 obj-$(CONFIG_PCH_DMA) += pch_dma.o
 obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
 obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
-obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
-obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
-obj-$(CONFIG_DMA_OMAP) += omap-dma.o
-obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index d1cc5791476..be21e3f138a 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -66,45 +66,40 @@
  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  *    will then move to the next LLI entry.
  *
+ * Only the former works sanely with scatter lists, so we only implement
+ * the DMAC flow control method.  However, peripherals which use the LBREQ
+ * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
+ * these hardware restrictions prevents them from using scatter DMA.
+ *
  * Global TODO:
  * - Break out common code from arch/arm/mach-s3c64xx and share
  */
-#include <linux/amba/bus.h>
-#include <linux/amba/pl08x.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
 #include <linux/device.h>
-#include <linux/dmaengine.h>
-#include <linux/dmapool.h>
-#include <linux/dma-mapping.h>
 #include <linux/init.h>
-#include <linux/interrupt.h>
 #include <linux/module.h>
-#include <linux/pm_runtime.h>
-#include <linux/seq_file.h>
+#include <linux/interrupt.h>
 #include <linux/slab.h>
-#include <asm/hardware/pl080.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/dmaengine.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl08x.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
 
-#include "dmaengine.h"
-#include "virt-dma.h"
+#include <asm/hardware/pl080.h>
 
 #define DRIVER_NAME     "pl08xdmac"
 
-static struct amba_driver pl08x_amba_driver;
-struct pl08x_driver_data;
-
 /**
  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
  * @channels: the number of channels available in this variant
  * @dualmaster: whether this version supports dual AHB masters or not.
- * @nomadik: whether the channels have Nomadik security extension bits
- *      that need to be checked for permission before use and some registers are
- *      missing
  */
 struct vendor_data {
         u8 channels;
         bool dualmaster;
-        bool nomadik;
 };
 
 /*
@@ -121,123 +116,6 @@ struct pl08x_lli {
 };
 
 /**
- * struct pl08x_bus_data - information of source or destination
- * busses for a transfer
- * @addr: current address
- * @maxwidth: the maximum width of a transfer on this bus
- * @buswidth: the width of this bus in bytes: 1, 2 or 4
- */
-struct pl08x_bus_data {
-        dma_addr_t addr;
-        u8 maxwidth;
-        u8 buswidth;
-};
-
-/**
- * struct pl08x_phy_chan - holder for the physical channels
- * @id: physical index to this channel
- * @lock: a lock to use when altering an instance of this struct
- * @serving: the virtual channel currently being served by this physical
- * channel
- * @locked: channel unavailable for the system, e.g. dedicated to secure
- * world
- */
-struct pl08x_phy_chan {
-        unsigned int id;
-        void __iomem *base;
-        spinlock_t lock;
-        struct pl08x_dma_chan *serving;
-        bool locked;
-};
-
-/**
- * struct pl08x_sg - structure containing data per sg
- * @src_addr: src address of sg
- * @dst_addr: dst address of sg
- * @len: transfer len in bytes
- * @node: node for txd's dsg_list
- */
-struct pl08x_sg {
-        dma_addr_t src_addr;
-        dma_addr_t dst_addr;
-        size_t len;
-        struct list_head node;
-};
-
-/**
- * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
- * @vd: virtual DMA descriptor
- * @dsg_list: list of children sg's
- * @llis_bus: DMA memory address (physical) start for the LLIs
- * @llis_va: virtual memory address start for the LLIs
- * @cctl: control reg values for current txd
- * @ccfg: config reg values for current txd
- * @done: this marks completed descriptors, which should not have their
- *   mux released.
- */
-struct pl08x_txd {
-        struct virt_dma_desc vd;
-        struct list_head dsg_list;
-        dma_addr_t llis_bus;
-        struct pl08x_lli *llis_va;
-        /* Default cctl value for LLIs */
-        u32 cctl;
-        /*
-         * Settings to be put into the physical channel when we
-         * trigger this txd.  Other registers are in llis_va[0].
-         */
-        u32 ccfg;
-        bool done;
-};
-
-/**
- * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
- * states
- * @PL08X_CHAN_IDLE: the channel is idle
- * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
- * channel and is running a transfer on it
- * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
- * channel, but the transfer is currently paused
- * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
- * channel to become available (only pertains to memcpy channels)
- */
-enum pl08x_dma_chan_state {
-        PL08X_CHAN_IDLE,
-        PL08X_CHAN_RUNNING,
-        PL08X_CHAN_PAUSED,
-        PL08X_CHAN_WAITING,
-};
-
-/**
- * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
- * @vc: wrappped virtual channel
- * @phychan: the physical channel utilized by this channel, if there is one
- * @name: name of channel
- * @cd: channel platform data
- * @runtime_addr: address for RX/TX according to the runtime config
- * @at: active transaction on this channel
- * @lock: a lock for this channel data
- * @host: a pointer to the host (internal use)
- * @state: whether the channel is idle, paused, running etc
- * @slave: whether this channel is a device (slave) or for memcpy
- * @signal: the physical DMA request signal which this channel is using
- * @mux_use: count of descriptors using this DMA request signal setting
- */
-struct pl08x_dma_chan {
-        struct virt_dma_chan vc;
-        struct pl08x_phy_chan *phychan;
-        const char *name;
-        const struct pl08x_channel_data *cd;
-        struct dma_slave_config cfg;
-        struct pl08x_txd *at;
-        struct pl08x_driver_data *host;
-        enum pl08x_dma_chan_state state;
-        bool slave;
-        int signal;
-        unsigned mux_use;
-};
-
-/**
  * struct pl08x_driver_data - the local state holder for the PL08x
  * @slave: slave engine for this instance
  * @memcpy: memcpy engine for this instance
@@ -247,8 +125,8 @@ struct pl08x_dma_chan {
  * @pd: platform data passed in from the platform/machine
  * @phy_chans: array of data for the physical channels
  * @pool: a pool for the LLI descriptors
- * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
- * fetches
+ * @pool_ctr: counter of LLIs in the pool
+ * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
  * @mem_buses: set to indicate memory transfers on AHB2.
  * @lock: a spinlock for this struct
  */
@@ -261,14 +139,24 @@ struct pl08x_driver_data {
         struct pl08x_platform_data *pd;
         struct pl08x_phy_chan *phy_chans;
         struct dma_pool *pool;
+        int pool_ctr;
         u8 lli_buses;
         u8 mem_buses;
+        spinlock_t lock;
 };
 
 /*
  * PL08X specific defines
  */
 
+/*
+ * Memory boundaries: the manual for PL08x says that the controller
+ * cannot read past a 1KiB boundary, so these defines are used to
+ * create transfer LLIs that do not cross such boundaries.
+ */
+#define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
+#define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
+
 /* Size (bytes) of each LLI buffer allocated for one transfer */
 # define PL08X_LLI_TSFR_SIZE    0x2000
 
@@ -278,51 +166,12 @@ struct pl08x_driver_data {
 
 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 {
-        return container_of(chan, struct pl08x_dma_chan, vc.chan);
+        return container_of(chan, struct pl08x_dma_chan, chan);
 }
 
 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
 {
-        return container_of(tx, struct pl08x_txd, vd.tx);
-}
-
-/*
- * Mux handling.
- *
- * This gives us the DMA request input to the PL08x primecell which the
- * peripheral described by the channel data will be routed to, possibly
- * via a board/SoC specific external MUX.  One important point to note
- * here is that this does not depend on the physical channel.
- */
-static int pl08x_request_mux(struct pl08x_dma_chan *plchan)
-{
-        const struct pl08x_platform_data *pd = plchan->host->pd;
-        int ret;
-
-        if (plchan->mux_use++ == 0 && pd->get_signal) {
-                ret = pd->get_signal(plchan->cd);
-                if (ret < 0) {
-                        plchan->mux_use = 0;
-                        return ret;
-                }
-
-                plchan->signal = ret;
-        }
-        return 0;
-}
-
-static void pl08x_release_mux(struct pl08x_dma_chan *plchan)
-{
-        const struct pl08x_platform_data *pd = plchan->host->pd;
-
-        if (plchan->signal >= 0) {
-                WARN_ON(plchan->mux_use == 0);
-
-                if (--plchan->mux_use == 0 && pd->put_signal) {
-                        pd->put_signal(plchan->cd, plchan->signal);
-                        plchan->signal = -1;
-                }
-        }
+        return container_of(tx, struct pl08x_txd, tx);
 }
 
 /*
@@ -344,25 +193,20 @@ static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
  * been set when the LLIs were constructed.  Poke them into the hardware
  * and start the transfer.
  */
-static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
+static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
+        struct pl08x_txd *txd)
 {
         struct pl08x_driver_data *pl08x = plchan->host;
         struct pl08x_phy_chan *phychan = plchan->phychan;
-        struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc);
-        struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
-        struct pl08x_lli *lli;
+        struct pl08x_lli *lli = &txd->llis_va[0];
         u32 val;
 
-        list_del(&txd->vd.node);
-
         plchan->at = txd;
 
         /* Wait for channel inactive */
         while (pl08x_phy_channel_busy(phychan))
                 cpu_relax();
 
-        lli = &txd->llis_va[0];
-
         dev_vdbg(&pl08x->adev->dev,
                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
                 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
@@ -428,6 +272,7 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
         writel(val, ch->base + PL080_CH_CONFIG);
 }
 
+
 /*
  * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
  * clears any pending interrupt status.  This should not be used for
@@ -471,8 +316,10 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 {
         struct pl08x_phy_chan *ch;
         struct pl08x_txd *txd;
+        unsigned long flags;
         size_t bytes = 0;
 
+        spin_lock_irqsave(&plchan->lock, flags);
         ch = plchan->phychan;
         txd = plchan->at;
 
@@ -512,6 +359,16 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
                 }
         }
 
+        /* Sum up all queued transactions */
+        if (!list_empty(&plchan->pend_list)) {
+                struct pl08x_txd *txdi;
+                list_for_each_entry(txdi, &plchan->pend_list, node) {
+                        bytes += txdi->len;
+                }
+        }
+
+        spin_unlock_irqrestore(&plchan->lock, flags);
+
         return bytes;
 }
 
@@ -535,8 +392,9 @@ pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 
                 spin_lock_irqsave(&ch->lock, flags);
 
-                if (!ch->locked && !ch->serving) {
+                if (!ch->serving) {
                         ch->serving = virt_chan;
+                        ch->signal = -1;
                         spin_unlock_irqrestore(&ch->lock, flags);
                         break;
                 }
@@ -552,111 +410,19 @@ pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
         return ch;
 }
 
-/* Mark the physical channel as free.  Note, this write is atomic. */
 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
                                          struct pl08x_phy_chan *ch)
 {
-        ch->serving = NULL;
-}
-
-/*
- * Try to allocate a physical channel.  When successful, assign it to
- * this virtual channel, and initiate the next descriptor.  The
- * virtual channel lock must be held at this point.
- */
-static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan)
-{
-        struct pl08x_driver_data *pl08x = plchan->host;
-        struct pl08x_phy_chan *ch;
-
-        ch = pl08x_get_phy_channel(pl08x, plchan);
-        if (!ch) {
-                dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
-                plchan->state = PL08X_CHAN_WAITING;
-                return;
-        }
-
-        dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n",
-                ch->id, plchan->name);
-
-        plchan->phychan = ch;
-        plchan->state = PL08X_CHAN_RUNNING;
-        pl08x_start_next_txd(plchan);
-}
-
-static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch,
-        struct pl08x_dma_chan *plchan)
-{
-        struct pl08x_driver_data *pl08x = plchan->host;
-
-        dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n",
-                ch->id, plchan->name);
-
-        /*
-         * We do this without taking the lock; we're really only concerned
-         * about whether this pointer is NULL or not, and we're guaranteed
-         * that this will only be called when it _already_ is non-NULL.
-         */
-        ch->serving = plchan;
-        plchan->phychan = ch;
-        plchan->state = PL08X_CHAN_RUNNING;
-        pl08x_start_next_txd(plchan);
-}
-
-/*
- * Free a physical DMA channel, potentially reallocating it to another
- * virtual channel if we have any pending.
- */
-static void pl08x_phy_free(struct pl08x_dma_chan *plchan)
-{
-        struct pl08x_driver_data *pl08x = plchan->host;
-        struct pl08x_dma_chan *p, *next;
-
- retry:
-        next = NULL;
-
-        /* Find a waiting virtual channel for the next transfer. */
-        list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node)
-                if (p->state == PL08X_CHAN_WAITING) {
-                        next = p;
-                        break;
-                }
-
-        if (!next) {
-                list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node)
-                        if (p->state == PL08X_CHAN_WAITING) {
-                                next = p;
-                                break;
-                        }
-        }
-
-        /* Ensure that the physical channel is stopped */
-        pl08x_terminate_phy_chan(pl08x, plchan->phychan);
+        unsigned long flags;
 
-        if (next) {
-                bool success;
+        spin_lock_irqsave(&ch->lock, flags);
 
-                /*
-                 * Eww.  We know this isn't going to deadlock
-                 * but lockdep probably doesn't.
-                 */
-                spin_lock(&next->vc.lock);
-                /* Re-check the state now that we have the lock */
-                success = next->state == PL08X_CHAN_WAITING;
-                if (success)
-                        pl08x_phy_reassign_start(plchan->phychan, next);
-                spin_unlock(&next->vc.lock);
-
-                /* If the state changed, try to find another channel */
-                if (!success)
-                        goto retry;
-        } else {
-                /* No more jobs, so free up the physical channel */
-                pl08x_put_phy_channel(pl08x, plchan->phychan);
-        }
+        /* Stop the channel and clear its interrupts */
+        pl08x_terminate_phy_chan(pl08x, ch);
 
-        plchan->phychan = NULL;
-        plchan->state = PL08X_CHAN_IDLE;
+        /* Mark it as free */
+        ch->serving = NULL;
+        spin_unlock_irqrestore(&ch->lock, flags);
 }
 
 /*
@@ -733,30 +499,36 @@ struct pl08x_lli_build_data {
 };
 
 /*
- * Autoselect a master bus to use for the transfer. Slave will be the chosen as
- * victim in case src & dest are not similarly aligned. i.e. If after aligning
- * masters address with width requirements of transfer (by sending few byte by
- * byte data), slave is still not aligned, then its width will be reduced to
- * BYTE.
- * - prefers the destination bus if both available
- * - prefers bus with fixed address (i.e. peripheral)
+ * Autoselect a master bus to use for the transfer this prefers the
+ * destination bus if both available if fixed address on one bus the
+ * other will be chosen
  */
 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
         struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
 {
         if (!(cctl & PL080_CONTROL_DST_INCR)) {
-                *mbus = &bd->dstbus;
-                *sbus = &bd->srcbus;
-        } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
                 *mbus = &bd->srcbus;
                 *sbus = &bd->dstbus;
+        } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
+                *mbus = &bd->dstbus;
+                *sbus = &bd->srcbus;
         } else {
-                if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
+                if (bd->dstbus.buswidth == 4) {
                         *mbus = &bd->dstbus;
                         *sbus = &bd->srcbus;
-                } else {
+                } else if (bd->srcbus.buswidth == 4) {
+                        *mbus = &bd->srcbus;
+                        *sbus = &bd->dstbus;
+                } else if (bd->dstbus.buswidth == 2) {
+                        *mbus = &bd->dstbus;
+                        *sbus = &bd->srcbus;
+                } else if (bd->srcbus.buswidth == 2) {
                         *mbus = &bd->srcbus;
                         *sbus = &bd->dstbus;
+                } else {
+                        /* bd->srcbus.buswidth == 1 */
+                        *mbus = &bd->dstbus;
+                        *sbus = &bd->srcbus;
                 }
         }
 }
@@ -775,8 +547,7 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
         llis_va[num_llis].cctl = cctl;
         llis_va[num_llis].src = bd->srcbus.addr;
         llis_va[num_llis].dst = bd->dstbus.addr;
-        llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
-                sizeof(struct pl08x_lli);
+        llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
         llis_va[num_llis].lli |= bd->lli_bus;
 
         if (cctl & PL080_CONTROL_SRC_INCR)
@@ -789,12 +560,16 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
         bd->remainder -= len;
 }
 
-static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
-                u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
+/*
+ * Return number of bytes to fill to boundary, or len.
+ * This calculation works for any value of addr.
+ */
+static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
 {
-        *cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
-        pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
-        (*total_bytes) += len;
+        size_t boundary_len = PL08X_BOUNDARY_SIZE -
+                        (addr & (PL08X_BOUNDARY_SIZE - 1));
+
+        return min(boundary_len, len);
 }
 
 /*
@@ -808,20 +583,27 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
         struct pl08x_bus_data *mbus, *sbus;
         struct pl08x_lli_build_data bd;
         int num_llis = 0;
-        u32 cctl, early_bytes = 0;
-        size_t max_bytes_per_lli, total_bytes;
+        u32 cctl;
+        size_t max_bytes_per_lli;
+        size_t total_bytes = 0;
         struct pl08x_lli *llis_va;
-        struct pl08x_sg *dsg;
 
-        txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
+        txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
+                                      &txd->llis_bus);
         if (!txd->llis_va) {
                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
                 return 0;
         }
 
+        pl08x->pool_ctr++;
+
+        /* Get the default CCTL */
+        cctl = txd->cctl;
+
         bd.txd = txd;
+        bd.srcbus.addr = txd->src_addr;
+        bd.dstbus.addr = txd->dst_addr;
         bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
-        cctl = txd->cctl;
 
         /* Find maximum width of the source bus */
         bd.srcbus.maxwidth =
@@ -833,179 +615,215 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
                                        PL080_CONTROL_DWIDTH_SHIFT);
 
-        list_for_each_entry(dsg, &txd->dsg_list, node) {
-                total_bytes = 0;
-                cctl = txd->cctl;
+        /* Set up the bus widths to the maximum */
+        bd.srcbus.buswidth = bd.srcbus.maxwidth;
+        bd.dstbus.buswidth = bd.dstbus.maxwidth;
 
-                bd.srcbus.addr = dsg->src_addr;
-                bd.dstbus.addr = dsg->dst_addr;
-                bd.remainder = dsg->len;
-                bd.srcbus.buswidth = bd.srcbus.maxwidth;
-                bd.dstbus.buswidth = bd.dstbus.maxwidth;
+        /*
+         * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
+         */
+        max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
+                PL080_CONTROL_TRANSFER_SIZE_MASK;
 
-                pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
+        /* We need to count this down to zero */
+        bd.remainder = txd->len;
 
-                dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
-                        bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
-                        bd.srcbus.buswidth,
-                        bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
-                        bd.dstbus.buswidth,
-                        bd.remainder);
-                dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
-                        mbus == &bd.srcbus ? "src" : "dst",
-                        sbus == &bd.srcbus ? "src" : "dst");
+        /*
+         * Choose bus to align to
+         * - prefers destination bus if both available
+         * - if fixed address on one bus chooses other
+         */
+        pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
+
+        dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu llimax=%zu\n",
+                 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
+                 bd.srcbus.buswidth,
+                 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
+                 bd.dstbus.buswidth,
+                 bd.remainder, max_bytes_per_lli);
+        dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
+                 mbus == &bd.srcbus ? "src" : "dst",
+                 sbus == &bd.srcbus ? "src" : "dst");
+
+        if (txd->len < mbus->buswidth) {
+                /* Less than a bus width available - send as single bytes */
+                while (bd.remainder) {
+                        dev_vdbg(&pl08x->adev->dev,
+                                 "%s single byte LLIs for a transfer of "
+                                 "less than a bus width (remain 0x%08x)\n",
+                                 __func__, bd.remainder);
+                        cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+                        pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
+                        total_bytes++;
+                }
+        } else {
+                /* Make one byte LLIs until master bus is aligned */
+                while ((mbus->addr) % (mbus->buswidth)) {
+                        dev_vdbg(&pl08x->adev->dev,
+                                "%s adjustment lli for less than bus width "
+                                 "(remain 0x%08x)\n",
+                                 __func__, bd.remainder);
+                        cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+                        pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
+                        total_bytes++;
+                }
 
                 /*
-                 * Zero length is only allowed if all these requirements are
-                 * met:
-                 * - flow controller is peripheral.
-                 * - src.addr is aligned to src.width
-                 * - dst.addr is aligned to dst.width
-                 *
-                 * sg_len == 1 should be true, as there can be two cases here:
-                 *
-                 * - Memory addresses are contiguous and are not scattered.
-                 *   Here, Only one sg will be passed by user driver, with
-                 *   memory address and zero length. We pass this to controller
-                 *   and after the transfer it will receive the last burst
-                 *   request from peripheral and so transfer finishes.
-                 *
-                 * - Memory addresses are scattered and are not contiguous.
-                 *   Here, Obviously as DMA controller doesn't know when a lli's
-                 *   transfer gets over, it can't load next lli. So in this
-                 *   case, there has to be an assumption that only one lli is
-                 *   supported. Thus, we can't have scattered addresses.
+                 * Master now aligned
+                 * - if slave is not then we must set its width down
                  */
-                if (!bd.remainder) {
-                        u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
-                                PL080_CONFIG_FLOW_CONTROL_SHIFT;
-                        if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
-                                        (fc <= PL080_FLOW_SRC2DST_SRC))) {
-                                dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
-                                        __func__);
-                                return 0;
-                        }
-
-                        if ((bd.srcbus.addr % bd.srcbus.buswidth) ||
-                                        (bd.dstbus.addr % bd.dstbus.buswidth)) {
-                                dev_err(&pl08x->adev->dev,
-                                        "%s src & dst address must be aligned to src"
-                                        " & dst width if peripheral is flow controller",
-                                        __func__);
-                                return 0;
-                        }
+                if (sbus->addr % sbus->buswidth) {
+                        dev_dbg(&pl08x->adev->dev,
+                                "%s set down bus width to one byte\n",
+                                 __func__);
 
-                        cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
-                                        bd.dstbus.buswidth, 0);
-                        pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
-                        break;
+                        sbus->buswidth = 1;
                 }
 
                 /*
-                 * Send byte by byte for following cases
-                 * - Less than a bus width available
-                 * - until master bus is aligned
+                 * Make largest possible LLIs until less than one bus
+                 * width left
                  */
-                if (bd.remainder < mbus->buswidth)
-                        early_bytes = bd.remainder;
-                else if ((mbus->addr) % (mbus->buswidth)) {
-                        early_bytes = mbus->buswidth - (mbus->addr) %
-                                (mbus->buswidth);
-                        if ((bd.remainder - early_bytes) < mbus->buswidth)
-                                early_bytes = bd.remainder;
-                }
+                while (bd.remainder > (mbus->buswidth - 1)) {
+                        size_t lli_len, target_len, tsize, odd_bytes;
 
-                if (early_bytes) {
-                        dev_vdbg(&pl08x->adev->dev,
-                                "%s byte width LLIs (remain 0x%08x)\n",
-                                __func__, bd.remainder);
-                        prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
-                                &total_bytes);
-                }
-
-                if (bd.remainder) {
                         /*
-                         * Master now aligned
-                         * - if slave is not then we must set its width down
+                         * If enough left try to send max possible,
+                         * otherwise try to send the remainder
                          */
-                        if (sbus->addr % sbus->buswidth) {
-                                dev_dbg(&pl08x->adev->dev,
-                                        "%s set down bus width to one byte\n",
-                                        __func__);
-
-                                sbus->buswidth = 1;
-                        }
+                        target_len = min(bd.remainder, max_bytes_per_lli);
 
                         /*
-                         * Bytes transferred = tsize * src width, not
-                         * MIN(buswidths)
+                         * Set bus lengths for incrementing buses to the
+                         * number of bytes which fill to next memory boundary,
+                         * limiting on the target length calculated above.
                          */
-                        max_bytes_per_lli = bd.srcbus.buswidth *
-                                PL080_CONTROL_TRANSFER_SIZE_MASK;
-                        dev_vdbg(&pl08x->adev->dev,
-                                "%s max bytes per lli = %zu\n",
-                                __func__, max_bytes_per_lli);
-
-                        /*
-                         * Make largest possible LLIs until less than one bus
-                         * width left
-                         */
-                        while (bd.remainder > (mbus->buswidth - 1)) {
-                                size_t lli_len, tsize, width;
+                        if (cctl & PL080_CONTROL_SRC_INCR)
+                                bd.srcbus.fill_bytes =
+                                        pl08x_pre_boundary(bd.srcbus.addr,
+                                                target_len);
+                        else
+                                bd.srcbus.fill_bytes = target_len;
+
+                        if (cctl & PL080_CONTROL_DST_INCR)
+                                bd.dstbus.fill_bytes =
+                                        pl08x_pre_boundary(bd.dstbus.addr,
+                                                target_len);
+                        else
+                                bd.dstbus.fill_bytes = target_len;
+
+                        /* Find the nearest */
+                        lli_len = min(bd.srcbus.fill_bytes,
+                                      bd.dstbus.fill_bytes);
+
+                        BUG_ON(lli_len > bd.remainder);
+
+                        if (lli_len <= 0) {
+                                dev_err(&pl08x->adev->dev,
+                                        "%s lli_len is %zu, <= 0\n",
+                                                __func__, lli_len);
+                                return 0;
+                        }
 
+                        if (lli_len == target_len) {
+                                /*
+                                 * Can send what we wanted.
+                                 * Maintain alignment
+                                 */
+                                lli_len = (lli_len/mbus->buswidth) *
+                                                        mbus->buswidth;
+                                odd_bytes = 0;
+                        } else {
                                 /*
-                                 * If enough left try to send max possible,
-                                 * otherwise try to send the remainder
+                                 * So now we know how many bytes to transfer
+                                 * to get to the nearest boundary.  The next
+                                 * LLI will past the boundary.  However, we
+                                 * may be working to a boundary on the slave
+                                 * bus.  We need to ensure the master stays
+                                 * aligned, and that we are working in
+                                 * multiples of the bus widths.
                                  */
-                                lli_len = min(bd.remainder, max_bytes_per_lli);
+                                odd_bytes = lli_len % mbus->buswidth;
+                                lli_len -= odd_bytes;
 
+                        }
+
+                        if (lli_len) {
                                 /*
-                                 * Check against maximum bus alignment:
-                                 * Calculate actual transfer size in relation to
-                                 * bus width an get a maximum remainder of the
-                                 * highest bus width - 1
+                                 * Check against minimum bus alignment:
+                                 * Calculate actual transfer size in relation
+                                 * to bus width an get a maximum remainder of
+                                 * the smallest bus width - 1
                                  */
-                                width = max(mbus->buswidth, sbus->buswidth);
-                                lli_len = (lli_len / width) * width;
-                                tsize = lli_len / bd.srcbus.buswidth;
+                                /* FIXME: use round_down()? */
+                                tsize = lli_len / min(mbus->buswidth,
+                                                      sbus->buswidth);
+                                lli_len = tsize * min(mbus->buswidth,
+                                                      sbus->buswidth);
+
+                                if (target_len != lli_len) {
+                                        dev_vdbg(&pl08x->adev->dev,
+                                        "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
+                                        __func__, target_len, lli_len, txd->len);
+                                }
+
+                                cctl = pl08x_cctl_bits(cctl,
+                                                       bd.srcbus.buswidth,
+                                                       bd.dstbus.buswidth,
+                                                       tsize);
 
                                 dev_vdbg(&pl08x->adev->dev,
-                                        "%s fill lli with single lli chunk of "
-                                        "size 0x%08zx (remainder 0x%08zx)\n",
+                                        "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
                                         __func__, lli_len, bd.remainder);
-
-                                cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
-                                        bd.dstbus.buswidth, tsize);
                                 pl08x_fill_lli_for_desc(&bd, num_llis++,
-                                                lli_len, cctl);
+                                        lli_len, cctl);
                                 total_bytes += lli_len;
                         }
 
-                        /*
-                         * Send any odd bytes
-                         */
-                        if (bd.remainder) {
-                                dev_vdbg(&pl08x->adev->dev,
-                                        "%s align with boundary, send odd bytes (remain %zu)\n",
-                                        __func__, bd.remainder);
-                                prep_byte_width_lli(&bd, &cctl, bd.remainder,
-                                                num_llis++, &total_bytes);
+
+                        if (odd_bytes) {
+                                /*
+                                 * Creep past the boundary, maintaining
+                                 * master alignment
+                                 */
+                                int j;
+                                for (j = 0; (j < mbus->buswidth)
+                                                && (bd.remainder); j++) {
+                                        cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+                                        dev_vdbg(&pl08x->adev->dev,
+                                                "%s align with boundary, single byte (remain 0x%08zx)\n",
+                                                __func__, bd.remainder);
+                                        pl08x_fill_lli_for_desc(&bd,
+                                                num_llis++, 1, cctl);
+                                        total_bytes++;
+                                }
                         }
                 }
 
-                if (total_bytes != dsg->len) {
-                        dev_err(&pl08x->adev->dev,
-                                "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
-                                __func__, total_bytes, dsg->len);
-                        return 0;
+                /*
+                 * Send any odd bytes
+                 */
+                while (bd.remainder) {
+                        cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+                        dev_vdbg(&pl08x->adev->dev,
+                                "%s align with boundary, single odd byte (remain %zu)\n",
+                                __func__, bd.remainder);
+                        pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
+                        total_bytes++;
                 }
+        }
+        if (total_bytes != txd->len) {
+                dev_err(&pl08x->adev->dev,
+                        "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
+                        __func__, total_bytes, txd->len);
+                return 0;
+        }
 
-                if (num_llis >= MAX_NUM_TSFR_LLIS) {
-                        dev_err(&pl08x->adev->dev,
-                                "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
-                                __func__, (u32) MAX_NUM_TSFR_LLIS);
-                        return 0;
-                }
+        if (num_llis >= MAX_NUM_TSFR_LLIS) {
+                dev_err(&pl08x->adev->dev,
+                        "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
+                        __func__, (u32) MAX_NUM_TSFR_LLIS);
+                return 0;
         }
 
         llis_va = txd->llis_va;
@@ -1034,91 +852,147 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
         return num_llis;
 }
 
+/* You should call this with the struct pl08x lock held */
 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
                            struct pl08x_txd *txd)
 {
-        struct pl08x_sg *dsg, *_dsg;
+        /* Free the LLI */
+        dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
 
-        if (txd->llis_va)
-                dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
-
-        list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
-                list_del(&dsg->node);
-                kfree(dsg);
-        }
+        pl08x->pool_ctr--;
 
         kfree(txd);
 }
 
-static void pl08x_unmap_buffers(struct pl08x_txd *txd)
+static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
+                                struct pl08x_dma_chan *plchan)
 {
-        struct device *dev = txd->vd.tx.chan->device->dev;
-        struct pl08x_sg *dsg;
-
-        if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
-                if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
-                        list_for_each_entry(dsg, &txd->dsg_list, node)
-                                dma_unmap_single(dev, dsg->src_addr, dsg->len,
-                                                DMA_TO_DEVICE);
-                else {
-                        list_for_each_entry(dsg, &txd->dsg_list, node)
-                                dma_unmap_page(dev, dsg->src_addr, dsg->len,
-                                                DMA_TO_DEVICE);
+        struct pl08x_txd *txdi = NULL;
+        struct pl08x_txd *next;
+
+        if (!list_empty(&plchan->pend_list)) {
+                list_for_each_entry_safe(txdi,
+                                         next, &plchan->pend_list, node) {
+                        list_del(&txdi->node);
+                        pl08x_free_txd(pl08x, txdi);
                 }
         }
-        if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
-                if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
-                        list_for_each_entry(dsg, &txd->dsg_list, node)
-                                dma_unmap_single(dev, dsg->dst_addr, dsg->len,
-                                                DMA_FROM_DEVICE);
-                else
-                        list_for_each_entry(dsg, &txd->dsg_list, node)
-                                dma_unmap_page(dev, dsg->dst_addr, dsg->len,
-                                                DMA_FROM_DEVICE);
-        }
 }
 
-static void pl08x_desc_free(struct virt_dma_desc *vd)
+/*
+ * The DMA ENGINE API
+ */
+static int pl08x_alloc_chan_resources(struct dma_chan *chan)
 {
-        struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
-        struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan);
-
-        if (!plchan->slave)
-                pl08x_unmap_buffers(txd);
-
-        if (!txd->done)
-                pl08x_release_mux(plchan);
+        return 0;
+}
 
-        pl08x_free_txd(plchan->host, txd);
+static void pl08x_free_chan_resources(struct dma_chan *chan)
+{
 }
 
-static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
-                                struct pl08x_dma_chan *plchan)
+/*
+ * This should be called with the channel plchan->lock held
+ */
+static int prep_phy_channel(struct pl08x_dma_chan *plchan,
+                            struct pl08x_txd *txd)
 {
-        LIST_HEAD(head);
-        struct pl08x_txd *txd;
+        struct pl08x_driver_data *pl08x = plchan->host;
+        struct pl08x_phy_chan *ch;
+        int ret;
+
+        /* Check if we already have a channel */
+        if (plchan->phychan)
+                return 0;
+
+        ch = pl08x_get_phy_channel(pl08x, plchan);
+        if (!ch) {
+                /* No physical channel available, cope with it */
+                dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
+                return -EBUSY;
+        }
 
-        vchan_get_all_descriptors(&plchan->vc, &head);
+        /*
+         * OK we have a physical channel: for memcpy() this is all we
+         * need, but for slaves the physical signals may be muxed!
+         * Can the platform allow us to use this channel?
+         */
+        if (plchan->slave &&
+            ch->signal < 0 &&
+            pl08x->pd->get_signal) {
+                ret = pl08x->pd->get_signal(plchan);
+                if (ret < 0) {
+                        dev_dbg(&pl08x->adev->dev,
+                                "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
+                                ch->id, plchan->name);
+                        /* Release physical channel & return */
+                        pl08x_put_phy_channel(pl08x, ch);
+                        return -EBUSY;
+                }
+                ch->signal = ret;
 
-        while (!list_empty(&head)) {
-                txd = list_first_entry(&head, struct pl08x_txd, vd.node);
-                list_del(&txd->vd.node);
-                pl08x_desc_free(&txd->vd);
+                /* Assign the flow control signal to this channel */
+                if (txd->direction == DMA_TO_DEVICE)
+                        txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
+                else if (txd->direction == DMA_FROM_DEVICE)
+                        txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
         }
+
+        dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
+                 ch->id,
+                 ch->signal,
+                 plchan->name);
+
+        plchan->phychan_hold++;
+        plchan->phychan = ch;
+
+        return 0;
 }
 
-/*
- * The DMA ENGINE API
- */
-static int pl08x_alloc_chan_resources(struct dma_chan *chan)
+static void release_phy_channel(struct pl08x_dma_chan *plchan)
 {
-        return 0;
+        struct pl08x_driver_data *pl08x = plchan->host;
+
+        if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
+                pl08x->pd->put_signal(plchan);
+                plchan->phychan->signal = -1;
+        }
+        pl08x_put_phy_channel(pl08x, plchan->phychan);
+        plchan->phychan = NULL;
 }
 
-static void pl08x_free_chan_resources(struct dma_chan *chan)
+static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
 {
-        /* Ensure all queued descriptors are freed */
-        vchan_free_chan_resources(to_virt_chan(chan));
+        struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
+        struct pl08x_txd *txd = to_pl08x_txd(tx);
+        unsigned long flags;
+
+        spin_lock_irqsave(&plchan->lock, flags);
+
+        plchan->chan.cookie += 1;
+        if (plchan->chan.cookie < 0)
+                plchan->chan.cookie = 1;
+        tx->cookie = plchan->chan.cookie;
+
+        /* Put this onto the pending list */
+        list_add_tail(&txd->node, &plchan->pend_list);
+
+        /*
+         * If there was no physical channel available for this memcpy,
+         * stack the request up and indicate that the channel is waiting
+         * for a free physical channel.
+         */
+        if (!plchan->slave && !plchan->phychan) {
+                /* Do this memcpy whenever there is a channel ready */
+                plchan->state = PL08X_CHAN_WAITING;
+                plchan->waiting = txd;
+        } else {
+                plchan->phychan_hold--;
+        }
+
+        spin_unlock_irqrestore(&plchan->lock, flags);
+
+        return tx->cookie;
 }
 
 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
@@ -1134,57 +1008,43 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
  * If slaves are relying on interrupts to signal completion this function
  * must not be called with interrupts disabled.
  */
-static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
-                dma_cookie_t cookie, struct dma_tx_state *txstate)
+static enum dma_status
+pl08x_dma_tx_status(struct dma_chan *chan,
+                    dma_cookie_t cookie,
+                    struct dma_tx_state *txstate)
 {
         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
-        struct virt_dma_desc *vd;
-        unsigned long flags;
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
         enum dma_status ret;
-        size_t bytes = 0;
+        u32 bytesleft = 0;
 
-        ret = dma_cookie_status(chan, cookie, txstate);
-        if (ret == DMA_SUCCESS)
-                return ret;
+        last_used = plchan->chan.cookie;
+        last_complete = plchan->lc;
 
-        /*
-         * There's no point calculating the residue if there's
-         * no txstate to store the value.
-         */
-        if (!txstate) {
-                if (plchan->state == PL08X_CHAN_PAUSED)
-                        ret = DMA_PAUSED;
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
+        if (ret == DMA_SUCCESS) {
+                dma_set_tx_state(txstate, last_complete, last_used, 0);
                 return ret;
         }
 
-        spin_lock_irqsave(&plchan->vc.lock, flags);
-        ret = dma_cookie_status(chan, cookie, txstate);
-        if (ret != DMA_SUCCESS) {
-                vd = vchan_find_desc(&plchan->vc, cookie);
-                if (vd) {
-                        /* On the issued list, so hasn't been processed yet */
-                        struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
-                        struct pl08x_sg *dsg;
-
-                        list_for_each_entry(dsg, &txd->dsg_list, node)
-                                bytes += dsg->len;
-                } else {
-                        bytes = pl08x_getbytes_chan(plchan);
-                }
-        }
-        spin_unlock_irqrestore(&plchan->vc.lock, flags);
-
         /*
          * This cookie not complete yet
-         * Get number of bytes left in the active transactions and queue
          */
-        dma_set_residue(txstate, bytes);
+        last_used = plchan->chan.cookie;
+        last_complete = plchan->lc;
+
+        /* Get number of bytes left in the active transactions and queue */
+        bytesleft = pl08x_getbytes_chan(plchan);
+
+        dma_set_tx_state(txstate, last_complete, last_used,
+                         bytesleft);
 
-        if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS)
-                ret = DMA_PAUSED;
+        if (plchan->state == PL08X_CHAN_PAUSED)
+                return DMA_PAUSED;
 
         /* Whether waiting or running, we're in progress */
-        return ret;
+        return DMA_IN_PROGRESS;
 }
 
 /* PrimeCell DMA extension */
@@ -1280,14 +1140,38 @@ static u32 pl08x_burst(u32 maxburst)
         return burst_sizes[i].reg;
 }
 
-static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan,
-        enum dma_slave_buswidth addr_width, u32 maxburst)
+static int dma_set_runtime_config(struct dma_chan *chan,
+                                  struct dma_slave_config *config)
 {
-        u32 width, burst, cctl = 0;
+        struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+        struct pl08x_driver_data *pl08x = plchan->host;
+        enum dma_slave_buswidth addr_width;
+        u32 width, burst, maxburst;
+        u32 cctl = 0;
+
+        if (!plchan->slave)
+                return -EINVAL;
+
+        /* Transfer direction */
+        plchan->runtime_direction = config->direction;
+        if (config->direction == DMA_TO_DEVICE) {
+                addr_width = config->dst_addr_width;
+                maxburst = config->dst_maxburst;
+        } else if (config->direction == DMA_FROM_DEVICE) {
+                addr_width = config->src_addr_width;
+                maxburst = config->src_maxburst;
+        } else {
+                dev_err(&pl08x->adev->dev,
+                        "bad runtime_config: alien transfer direction\n");
+                return -EINVAL;
+        }
 
         width = pl08x_width(addr_width);
-        if (width == ~0)
-                return ~0;
+        if (width == ~0) {
+                dev_err(&pl08x->adev->dev,
+                        "bad runtime_config: alien address width\n");
+                return -EINVAL;
+        }
 
         cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
         cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
@@ -1304,23 +1188,26 @@ static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan,
         cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
         cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
 
-        return pl08x_cctl(cctl);
-}
-
-static int dma_set_runtime_config(struct dma_chan *chan,
-                                  struct dma_slave_config *config)
-{
-        struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
-
-        if (!plchan->slave)
-                return -EINVAL;
-
-        /* Reject definitely invalid configurations */
-        if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
-            config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
-                return -EINVAL;
+        if (plchan->runtime_direction == DMA_FROM_DEVICE) {
+                plchan->src_addr = config->src_addr;
+                plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
+                        pl08x_select_bus(plchan->cd->periph_buses,
+                                         pl08x->mem_buses);
+        } else {
+                plchan->dst_addr = config->dst_addr;
+                plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
+                        pl08x_select_bus(pl08x->mem_buses,
+                                         plchan->cd->periph_buses);
+        }
 
-        plchan->cfg = *config;
+        dev_dbg(&pl08x->adev->dev,
+                "configured channel %s (%s) for %s, data width %d, "
+                "maxburst %d words, LE, CCTL=0x%08x\n",
+                dma_chan_name(chan), plchan->name,
+                (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
+                addr_width,
+                maxburst,
+                cctl);
 
         return 0;
 }
@@ -1334,20 +1221,93 @@ static void pl08x_issue_pending(struct dma_chan *chan)
         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
         unsigned long flags;
 
-        spin_lock_irqsave(&plchan->vc.lock, flags);
-        if (vchan_issue_pending(&plchan->vc)) {
-                if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING)
-                        pl08x_phy_alloc_and_start(plchan);
+        spin_lock_irqsave(&plchan->lock, flags);
+        /* Something is already active, or we're waiting for a channel... */
+        if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
+                spin_unlock_irqrestore(&plchan->lock, flags);
+                return;
+        }
+
+        /* Take the first element in the queue and execute it */
+        if (!list_empty(&plchan->pend_list)) {
+                struct pl08x_txd *next;
+
+                next = list_first_entry(&plchan->pend_list,
+                                        struct pl08x_txd,
+                                        node);
+                list_del(&next->node);
+                plchan->state = PL08X_CHAN_RUNNING;
+
+                pl08x_start_txd(plchan, next);
+        }
+
+        spin_unlock_irqrestore(&plchan->lock, flags);
+}
+
+static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
+                                        struct pl08x_txd *txd)
+{
+        struct pl08x_driver_data *pl08x = plchan->host;
+        unsigned long flags;
+        int num_llis, ret;
+
+        num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
+        if (!num_llis) {
+                kfree(txd);
+                return -EINVAL;
         }
-        spin_unlock_irqrestore(&plchan->vc.lock, flags);
+
+        spin_lock_irqsave(&plchan->lock, flags);
+
+        /*
+         * See if we already have a physical channel allocated,
+         * else this is the time to try to get one.
+         */
+        ret = prep_phy_channel(plchan, txd);
+        if (ret) {
+                /*
+                 * No physical channel was available.
+                 *
+                 * memcpy transfers can be sorted out at submission time.
+                 *
+                 * Slave transfers may have been denied due to platform
+                 * channel muxing restrictions.  Since there is no guarantee
+                 * that this will ever be resolved, and the signal must be
+                 * acquired AFTER acquiring the physical channel, we will let
+                 * them be NACK:ed with -EBUSY here. The drivers can retry
+                 * the prep() call if they are eager on doing this using DMA.
+                 */
+                if (plchan->slave) {
+                        pl08x_free_txd_list(pl08x, plchan);
+                        pl08x_free_txd(pl08x, txd);
+                        spin_unlock_irqrestore(&plchan->lock, flags);
+                        return -EBUSY;
+                }
+        } else
+                /*
+                 * Else we're all set, paused and ready to roll, status
+                 * will switch to PL08X_CHAN_RUNNING when we call
+                 * issue_pending(). If there is something running on the
+                 * channel already we don't change its state.
+                 */
+                if (plchan->state == PL08X_CHAN_IDLE)
+                        plchan->state = PL08X_CHAN_PAUSED;
+
+        spin_unlock_irqrestore(&plchan->lock, flags);
+
+        return 0;
 }
 
-static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
+static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
+        unsigned long flags)
 {
-        struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
+        struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
 
         if (txd) {
-                INIT_LIST_HEAD(&txd->dsg_list);
+                dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
+                txd->tx.flags = flags;
+                txd->tx.tx_submit = pl08x_tx_submit;
+                INIT_LIST_HEAD(&txd->node);
 
                 /* Always enable error and terminal interrupts */
                 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
@@ -1366,32 +1326,23 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
         struct pl08x_driver_data *pl08x = plchan->host;
         struct pl08x_txd *txd;
-        struct pl08x_sg *dsg;
         int ret;
 
-        txd = pl08x_get_txd(plchan);
+        txd = pl08x_get_txd(plchan, flags);
         if (!txd) {
                 dev_err(&pl08x->adev->dev,
                         "%s no memory for descriptor\n", __func__);
                 return NULL;
         }
 
-        dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
-        if (!dsg) {
-                pl08x_free_txd(pl08x, txd);
-                dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n",
-                                __func__);
-                return NULL;
-        }
-        list_add_tail(&dsg->node, &txd->dsg_list);
-
-        dsg->src_addr = src;
-        dsg->dst_addr = dest;
-        dsg->len = len;
+        txd->direction = DMA_NONE;
+        txd->src_addr = src;
+        txd->dst_addr = dest;
+        txd->len = len;
 
         /* Set platform data for m2m */
         txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
-        txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy &
+        txd->cctl = pl08x->pd->memcpy_channel.cctl &
                         ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
 
         /* Both to be incremented or the code will break */
@@ -1401,132 +1352,75 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
                 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
                                               pl08x->mem_buses);
 
-        ret = pl08x_fill_llis_for_desc(plchan->host, txd);
-        if (!ret) {
-                pl08x_free_txd(pl08x, txd);
+        ret = pl08x_prep_channel_resources(plchan, txd);
+        if (ret)
                 return NULL;
-        }
 
-        return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
+        return &txd->tx;
 }
 
 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
                 struct dma_chan *chan, struct scatterlist *sgl,
-                unsigned int sg_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags)
 {
         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
         struct pl08x_driver_data *pl08x = plchan->host;
         struct pl08x_txd *txd;
-        struct pl08x_sg *dsg;
-        struct scatterlist *sg;
-        enum dma_slave_buswidth addr_width;
-        dma_addr_t slave_addr;
-        int ret, tmp;
-        u8 src_buses, dst_buses;
-        u32 maxburst, cctl;
+        int ret;
+
+        /*
+         * Current implementation ASSUMES only one sg
+         */
+        if (sg_len != 1) {
+                dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
+                        __func__);
+                BUG();
+        }
 
         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
-                        __func__, sg_dma_len(sgl), plchan->name);
+                __func__, sgl->length, plchan->name);
 
-        txd = pl08x_get_txd(plchan);
+        txd = pl08x_get_txd(plchan, flags);
         if (!txd) {
                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
                 return NULL;
         }
 
+        if (direction != plchan->runtime_direction)
+                dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
+                        "the direction configured for the PrimeCell\n",
+                        __func__);
+
         /*
          * Set up addresses, the PrimeCell configured address
          * will take precedence since this may configure the
          * channel target address dynamically at runtime.
          */
-        if (direction == DMA_MEM_TO_DEV) {
-                cctl = PL080_CONTROL_SRC_INCR;
-                slave_addr = plchan->cfg.dst_addr;
-                addr_width = plchan->cfg.dst_addr_width;
-                maxburst = plchan->cfg.dst_maxburst;
-                src_buses = pl08x->mem_buses;
-                dst_buses = plchan->cd->periph_buses;
-        } else if (direction == DMA_DEV_TO_MEM) {
-                cctl = PL080_CONTROL_DST_INCR;
-                slave_addr = plchan->cfg.src_addr;
-                addr_width = plchan->cfg.src_addr_width;
-                maxburst = plchan->cfg.src_maxburst;
-                src_buses = plchan->cd->periph_buses;
-                dst_buses = pl08x->mem_buses;
+        txd->direction = direction;
+        txd->len = sgl->length;
+
+        if (direction == DMA_TO_DEVICE) {
+                txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+                txd->cctl = plchan->dst_cctl;
+                txd->src_addr = sgl->dma_address;
+                txd->dst_addr = plchan->dst_addr;
+        } else if (direction == DMA_FROM_DEVICE) {
+                txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+                txd->cctl = plchan->src_cctl;
+                txd->src_addr = plchan->src_addr;
+                txd->dst_addr = sgl->dma_address;
         } else {
-                pl08x_free_txd(pl08x, txd);
                 dev_err(&pl08x->adev->dev,
                         "%s direction unsupported\n", __func__);
                 return NULL;
         }
 
-        cctl |= pl08x_get_cctl(plchan, addr_width, maxburst);
-        if (cctl == ~0) {
-                pl08x_free_txd(pl08x, txd);
-                dev_err(&pl08x->adev->dev,
-                        "DMA slave configuration botched?\n");
-                return NULL;
-        }
-
-        txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses);
-
-        if (plchan->cfg.device_fc)
-                tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
-                        PL080_FLOW_PER2MEM_PER;
-        else
-                tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
-                        PL080_FLOW_PER2MEM;
-
-        txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
-
-        ret = pl08x_request_mux(plchan);
-        if (ret < 0) {
-                pl08x_free_txd(pl08x, txd);
-                dev_dbg(&pl08x->adev->dev,
-                        "unable to mux for transfer on %s due to platform restrictions\n",
-                        plchan->name);
-                return NULL;
-        }
-
-        dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n",
-                 plchan->signal, plchan->name);
-
-        /* Assign the flow control signal to this channel */
-        if (direction == DMA_MEM_TO_DEV)
-                txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT;
-        else
-                txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
-
-        for_each_sg(sgl, sg, sg_len, tmp) {
-                dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
-                if (!dsg) {
-                        pl08x_release_mux(plchan);
-                        pl08x_free_txd(pl08x, txd);
-                        dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
-                                        __func__);
-                        return NULL;
-                }
-                list_add_tail(&dsg->node, &txd->dsg_list);
-
-                dsg->len = sg_dma_len(sg);
-                if (direction == DMA_MEM_TO_DEV) {
-                        dsg->src_addr = sg_dma_address(sg);
-                        dsg->dst_addr = slave_addr;
-                } else {
-                        dsg->src_addr = slave_addr;
-                        dsg->dst_addr = sg_dma_address(sg);
-                }
-        }
-
-        ret = pl08x_fill_llis_for_desc(plchan->host, txd);
-        if (!ret) {
-                pl08x_release_mux(plchan);
-                pl08x_free_txd(pl08x, txd);
+        ret = pl08x_prep_channel_resources(plchan, txd);
+        if (ret)
                 return NULL;
-        }
 
-        return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
+        return &txd->tx;
 }
 
 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
@@ -1547,9 +1441,9 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
          * Anything succeeds on channels with no physical allocation and
          * no queued transfers.
          */
-        spin_lock_irqsave(&plchan->vc.lock, flags);
+        spin_lock_irqsave(&plchan->lock, flags);
         if (!plchan->phychan && !plchan->at) {
-                spin_unlock_irqrestore(&plchan->vc.lock, flags);
+                spin_unlock_irqrestore(&plchan->lock, flags);
                 return 0;
         }
 
@@ -1558,15 +1452,17 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                 plchan->state = PL08X_CHAN_IDLE;
 
                 if (plchan->phychan) {
+                        pl08x_terminate_phy_chan(pl08x, plchan->phychan);
+
                         /*
                          * Mark physical channel as free and free any slave
                          * signal
                          */
-                        pl08x_phy_free(plchan);
+                        release_phy_channel(plchan);
                 }
                 /* Dequeue jobs and free LLIs */
                 if (plchan->at) {
-                        pl08x_desc_free(&plchan->at->vd);
+                        pl08x_free_txd(pl08x, plchan->at);
                         plchan->at = NULL;
                 }
                 /* Dequeue jobs not yet fired as well */
@@ -1586,22 +1482,16 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                 break;
         }
 
-        spin_unlock_irqrestore(&plchan->vc.lock, flags);
+        spin_unlock_irqrestore(&plchan->lock, flags);
 
         return ret;
 }
 
 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 {
-        struct pl08x_dma_chan *plchan;
+        struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
         char *name = chan_id;
 
-        /* Reject channels for devices not bound to this driver */
-        if (chan->device->dev->driver != &pl08x_amba_driver.drv)
-                return false;
-
-        plchan = to_pl08x_chan(chan);
-
         /* Check that the channel is not taken! */
         if (!strcmp(plchan->name, name))
                 return true;
@@ -1617,81 +1507,177 @@ bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
  */
 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
 {
-        /* The Nomadik variant does not have the config register */
-        if (pl08x->vd->nomadik)
-                return;
-        writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
+        u32 val;
+
+        val = readl(pl08x->base + PL080_CONFIG);
+        val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
+        /* We implicitly clear bit 1 and that means little-endian mode */
+        val |= PL080_CONFIG_ENABLE;
+        writel(val, pl08x->base + PL080_CONFIG);
 }
 
-static irqreturn_t pl08x_irq(int irq, void *dev)
+static void pl08x_unmap_buffers(struct pl08x_txd *txd)
 {
-        struct pl08x_driver_data *pl08x = dev;
-        u32 mask = 0, err, tc, i;
-
-        /* check & clear - ERR & TC interrupts */
-        err = readl(pl08x->base + PL080_ERR_STATUS);
-        if (err) {
-                dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
-                        __func__, err);
-                writel(err, pl08x->base + PL080_ERR_CLEAR);
+        struct device *dev = txd->tx.chan->device->dev;
+
+        if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
+                if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
+                        dma_unmap_single(dev, txd->src_addr, txd->len,
+                                DMA_TO_DEVICE);
+                else
+                        dma_unmap_page(dev, txd->src_addr, txd->len,
+                                DMA_TO_DEVICE);
+        }
+        if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
+                if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
+                        dma_unmap_single(dev, txd->dst_addr, txd->len,
+                                DMA_FROM_DEVICE);
+                else
+                        dma_unmap_page(dev, txd->dst_addr, txd->len,
+                                DMA_FROM_DEVICE);
+        }
+}
+
+static void pl08x_tasklet(unsigned long data)
+{
+        struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
+        struct pl08x_driver_data *pl08x = plchan->host;
+        struct pl08x_txd *txd;
+        unsigned long flags;
+
+        spin_lock_irqsave(&plchan->lock, flags);
+
+        txd = plchan->at;
+        plchan->at = NULL;
+
+        if (txd) {
+                /* Update last completed */
+                plchan->lc = txd->tx.cookie;
         }
-        tc = readl(pl08x->base + PL080_TC_STATUS);
-        if (tc)
-                writel(tc, pl08x->base + PL080_TC_CLEAR);
 
-        if (!err && !tc)
-                return IRQ_NONE;
+        /* If a new descriptor is queued, set it up plchan->at is NULL here */
+        if (!list_empty(&plchan->pend_list)) {
+                struct pl08x_txd *next;
+
+                next = list_first_entry(&plchan->pend_list,
+                                        struct pl08x_txd,
+                                        node);
+                list_del(&next->node);
+
+                pl08x_start_txd(plchan, next);
+        } else if (plchan->phychan_hold) {
+                /*
+                 * This channel is still in use - we have a new txd being
+                 * prepared and will soon be queued.  Don't give up the
+                 * physical channel.
+                 */
+        } else {
+                struct pl08x_dma_chan *waiting = NULL;
 
+                /*
+                 * No more jobs, so free up the physical channel
+                 * Free any allocated signal on slave transfers too
+                 */
+                release_phy_channel(plchan);
+                plchan->state = PL08X_CHAN_IDLE;
+
+                /*
+                 * And NOW before anyone else can grab that free:d up
+                 * physical channel, see if there is some memcpy pending
+                 * that seriously needs to start because of being stacked
+                 * up while we were choking the physical channels with data.
+                 */
+                list_for_each_entry(waiting, &pl08x->memcpy.channels,
+                                    chan.device_node) {
+                  if (waiting->state == PL08X_CHAN_WAITING &&
+                            waiting->waiting != NULL) {
+                                int ret;
+
+                                /* This should REALLY not fail now */
+                                ret = prep_phy_channel(waiting,
+                                                       waiting->waiting);
+                                BUG_ON(ret);
+                                waiting->phychan_hold--;
+                                waiting->state = PL08X_CHAN_RUNNING;
+                                waiting->waiting = NULL;
+                                pl08x_issue_pending(&waiting->chan);
+                                break;
+                        }
+                }
+        }
+
+        spin_unlock_irqrestore(&plchan->lock, flags);
+
+        if (txd) {
+                dma_async_tx_callback callback = txd->tx.callback;
+                void *callback_param = txd->tx.callback_param;
+
+                /* Don't try to unmap buffers on slave channels */
+                if (!plchan->slave)
+                        pl08x_unmap_buffers(txd);
+
+                /* Free the descriptor */
+                spin_lock_irqsave(&plchan->lock, flags);
+                pl08x_free_txd(pl08x, txd);
+                spin_unlock_irqrestore(&plchan->lock, flags);
+
+                /* Callback to signal completion */
+                if (callback)
+                        callback(callback_param);
+        }
+}
+
+static irqreturn_t pl08x_irq(int irq, void *dev)
+{
+        struct pl08x_driver_data *pl08x = dev;
+        u32 mask = 0;
+        u32 val;
+        int i;
+
+        val = readl(pl08x->base + PL080_ERR_STATUS);
+        if (val) {
+                /* An error interrupt (on one or more channels) */
+                dev_err(&pl08x->adev->dev,
+                        "%s error interrupt, register value 0x%08x\n",
+                                __func__, val);
+                /*
+                 * Simply clear ALL PL08X error interrupts,
+                 * regardless of channel and cause
+                 * FIXME: should be 0x00000003 on PL081 really.
+                 */
+                writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
+        }
+        val = readl(pl08x->base + PL080_INT_STATUS);
         for (i = 0; i < pl08x->vd->channels; i++) {
-                if (((1 << i) & err) || ((1 << i) & tc)) {
+                if ((1 << i) & val) {
                         /* Locate physical channel */
                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
                         struct pl08x_dma_chan *plchan = phychan->serving;
-                        struct pl08x_txd *tx;
 
-                        if (!plchan) {
-                                dev_err(&pl08x->adev->dev,
-                                        "%s Error TC interrupt on unused channel: 0x%08x\n",
-                                        __func__, i);
-                                continue;
-                        }
-
-                        spin_lock(&plchan->vc.lock);
-                        tx = plchan->at;
-                        if (tx) {
-                                plchan->at = NULL;
-                                /*
-                                 * This descriptor is done, release its mux
-                                 * reservation.
-                                 */
-                                pl08x_release_mux(plchan);
-                                tx->done = true;
-                                vchan_cookie_complete(&tx->vd);
-
-                                /*
-                                 * And start the next descriptor (if any),
-                                 * otherwise free this channel.
-                                 */
-                                if (vchan_next_desc(&plchan->vc))
-                                        pl08x_start_next_txd(plchan);
-                                else
-                                        pl08x_phy_free(plchan);
-                        }
-                        spin_unlock(&plchan->vc.lock);
+                        /* Schedule tasklet on this channel */
+                        tasklet_schedule(&plchan->tasklet);
 
                         mask |= (1 << i);
                 }
         }
+        /* Clear only the terminal interrupts on channels we processed */
+        writel(mask, pl08x->base + PL080_TC_CLEAR);
 
         return mask ? IRQ_HANDLED : IRQ_NONE;
 }
 
 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
 {
+        u32 cctl = pl08x_cctl(chan->cd->cctl);
+
         chan->slave = true;
         chan->name = chan->cd->bus_id;
-        chan->cfg.src_addr = chan->cd->addr;
-        chan->cfg.dst_addr = chan->cd->addr;
+        chan->src_addr = chan->cd->addr;
+        chan->dst_addr = chan->cd->addr;
+        chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
+                pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
+        chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
+                pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
 }
 
 /*
@@ -1699,7 +1685,9 @@ static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
  * Make a local wrapper to hold required data
  */
 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
-                struct dma_device *dmadev, unsigned int channels, bool slave)
+                                           struct dma_device *dmadev,
+                                           unsigned int channels,
+                                           bool slave)
 {
         struct pl08x_dma_chan *chan;
         int i;
@@ -1712,7 +1700,7 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
          * to cope with that situation.
          */
         for (i = 0; i < channels; i++) {
-                chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+                chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
                 if (!chan) {
                         dev_err(&pl08x->adev->dev,
                                 "%s no memory for channel\n", __func__);
@@ -1721,7 +1709,6 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
 
                 chan->host = pl08x;
                 chan->state = PL08X_CHAN_IDLE;
-                chan->signal = -1;
 
                 if (slave) {
                         chan->cd = &pl08x->pd->slave_channels[i];
@@ -1734,12 +1721,27 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
                                 return -ENOMEM;
                         }
                 }
-                dev_dbg(&pl08x->adev->dev,
+                if (chan->cd->circular_buffer) {
+                        dev_err(&pl08x->adev->dev,
+                                "channel %s: circular buffers not supported\n",
+                                chan->name);
+                        kfree(chan);
+                        continue;
+                }
+                dev_info(&pl08x->adev->dev,
                          "initialize virtual channel \"%s\"\n",
                          chan->name);
 
-                chan->vc.desc_free = pl08x_desc_free;
-                vchan_init(&chan->vc, dmadev);
+                chan->chan.device = dmadev;
+                chan->chan.cookie = 0;
+                chan->lc = 0;
+
+                spin_lock_init(&chan->lock);
+                INIT_LIST_HEAD(&chan->pend_list);
+                tasklet_init(&chan->tasklet, pl08x_tasklet,
+                             (unsigned long) chan);
+
+                list_add_tail(&chan->chan.device_node, &dmadev->channels);
         }
         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
                  i, slave ? "slave" : "memcpy");
@@ -1752,8 +1754,8 @@ static void pl08x_free_virtual_channels(struct dma_device *dmadev)
         struct pl08x_dma_chan *next;
 
         list_for_each_entry_safe(chan,
-                                 next, &dmadev->channels, vc.chan.device_node) {
-                list_del(&chan->vc.chan.device_node);
+                                 next, &dmadev->channels, chan.device_node) {
+                list_del(&chan->chan.device_node);
                 kfree(chan);
         }
 }
@@ -1795,10 +1797,8 @@ static int pl08x_debugfs_show(struct seq_file *s, void *data)
                 spin_lock_irqsave(&ch->lock, flags);
                 virt_chan = ch->serving;
 
-                seq_printf(s, "%d\t\t%s%s\n",
-                           ch->id,
-                           virt_chan ? virt_chan->name : "(none)",
-                           ch->locked ? " LOCKED" : "");
+                seq_printf(s, "%d\t\t%s\n",
+                           ch->id, virt_chan ? virt_chan->name : "(none)");
 
                 spin_unlock_irqrestore(&ch->lock, flags);
         }
@@ -1806,7 +1806,7 @@ static int pl08x_debugfs_show(struct seq_file *s, void *data)
         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
         seq_printf(s, "CHANNEL:\tSTATE:\n");
         seq_printf(s, "--------\t------\n");
-        list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) {
+        list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
                 seq_printf(s, "%s\t\t%s\n", chan->name,
                            pl08x_state_str(chan->state));
         }
@@ -1814,7 +1814,7 @@ static int pl08x_debugfs_show(struct seq_file *s, void *data)
         seq_printf(s, "\nPL08x virtual slave channels:\n");
         seq_printf(s, "CHANNEL:\tSTATE:\n");
         seq_printf(s, "--------\t------\n");
-        list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) {
+        list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
                 seq_printf(s, "%s\t\t%s\n", chan->name,
                            pl08x_state_str(chan->state));
         }
@@ -1837,9 +1837,9 @@ static const struct file_operations pl08x_debugfs_operations = {
 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
 {
         /* Expose a simple debugfs interface to view all clocks */
-        (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
-                        S_IFREG | S_IRUGO, NULL, pl08x,
-                        &pl08x_debugfs_operations);
+        (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
+                                   NULL, pl08x,
+                                   &pl08x_debugfs_operations);
 }
 
 #else
@@ -1860,7 +1860,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
                 return ret;
 
         /* Create the driver state holder */
-        pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
+        pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
         if (!pl08x) {
                 ret = -ENOMEM;
                 goto out_no_pl08x;
@@ -1892,7 +1892,6 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
         pl08x->pd = dev_get_platdata(&adev->dev);
         if (!pl08x->pd) {
                 dev_err(&adev->dev, "no platform data supplied\n");
-                ret = -EINVAL;
                 goto out_no_platdata;
         }
 
@@ -1916,6 +1915,8 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
                 goto out_no_lli_pool;
         }
 
+        spin_lock_init(&pl08x->lock);
+
         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
         if (!pl08x->base) {
                 ret = -ENOMEM;
@@ -1938,13 +1939,12 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
         }
 
         /* Initialize physical channels */
-        pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
+        pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
                         GFP_KERNEL);
         if (!pl08x->phy_chans) {
                 dev_err(&adev->dev, "%s failed to allocate "
                         "physical channel holders\n",
                         __func__);
-                ret = -ENOMEM;
                 goto out_no_phychans;
         }
 
@@ -1954,24 +1954,11 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
                 ch->id = i;
                 ch->base = pl08x->base + PL080_Cx_BASE(i);
                 spin_lock_init(&ch->lock);
-
-                /*
-                 * Nomadik variants can have channels that are locked
-                 * down for the secure world only. Lock up these channels
-                 * by perpetually serving a dummy virtual channel.
-                 */
-                if (vd->nomadik) {
-                        u32 val;
-
-                        val = readl(ch->base + PL080_CH_CONFIG);
-                        if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
-                                dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
-                                ch->locked = true;
-                        }
-                }
-
-                dev_dbg(&adev->dev, "physical channel %d is %s\n",
-                        i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
+                ch->serving = NULL;
+                ch->signal = -1;
+                dev_info(&adev->dev,
+                         "physical channel %d is %s\n", i,
+                         pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
         }
 
         /* Register as many memcpy channels as there are physical channels */
@@ -1987,7 +1974,8 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 
         /* Register slave channels */
         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
-                        pl08x->pd->num_slave_channels, true);
+                                              pl08x->pd->num_slave_channels,
+                                              true);
         if (ret <= 0) {
                 dev_warn(&pl08x->adev->dev,
                         "%s failed to enumerate slave channels - %d\n",
@@ -2017,7 +2005,6 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
                  amba_part(adev), amba_rev(adev),
                  (unsigned long long)adev->res.start, adev->irq[0]);
-
         return 0;
 
 out_no_slave_reg:
@@ -2048,12 +2035,6 @@ static struct vendor_data vendor_pl080 = {
         .dualmaster = true,
 };
 
-static struct vendor_data vendor_nomadik = {
-        .channels = 8,
-        .dualmaster = true,
-        .nomadik = true,
-};
-
 static struct vendor_data vendor_pl081 = {
         .channels = 2,
         .dualmaster = false,
@@ -2074,15 +2055,13 @@ static struct amba_id pl08x_ids[] = {
         },
         /* Nomadik 8815 PL080 variant */
         {
-                .id     = 0x00280080,
+                .id     = 0x00280880,
                 .mask   = 0x00ffffff,
-                .data   = &vendor_nomadik,
+                .data   = &vendor_pl080,
         },
         { 0, 0 },
 };
 
-MODULE_DEVICE_TABLE(amba, pl08x_ids);
-
 static struct amba_driver pl08x_amba_driver = {
         .drv.name       = DRIVER_NAME,
         .id_table       = pl08x_ids,
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 13a02f4425b..6a483eac7b3 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -9,9 +9,10 @@
  * (at your option) any later version.
  *
  *
- * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
- * The only Atmel DMA Controller that is not covered by this driver is the one
- * found on AT91SAM9263.
+ * This supports the Atmel AHB DMA Controller,
+ *
+ * The driver has currently been tested with the Atmel AT91SAM9RL
+ * and AT91SAM9G45 series.
  */
 
 #include <linux/clk.h>
@@ -22,11 +23,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
 
 #include "at_hdmac_regs.h"
-#include "dmaengine.h"
 
 /*
  * Glossary
@@ -38,6 +36,7 @@
  */
 
 #define ATC_DEFAULT_CFG         (ATC_FIFOCFG_HALFFIFO)
+#define ATC_DEFAULT_CTRLA       (0)
 #define ATC_DEFAULT_CTRLB       (ATC_SIF(AT_DMA_MEM_IF) \
                                 |ATC_DIF(AT_DMA_MEM_IF))
 
@@ -108,11 +107,10 @@ static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
 {
         struct at_desc *desc, *_desc;
         struct at_desc *ret = NULL;
-        unsigned long flags;
         unsigned int i = 0;
         LIST_HEAD(tmp_list);
 
-        spin_lock_irqsave(&atchan->lock, flags);
+        spin_lock_bh(&atchan->lock);
         list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
                 i++;
                 if (async_tx_test_ack(&desc->txd)) {
@@ -123,7 +121,7 @@ static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
                 dev_dbg(chan2dev(&atchan->chan_common),
                                 "desc %p not ACKed\n", desc);
         }
-        spin_unlock_irqrestore(&atchan->lock, flags);
+        spin_unlock_bh(&atchan->lock);
         dev_vdbg(chan2dev(&atchan->chan_common),
                 "scanned %u descriptors on freelist\n", i);
 
@@ -131,9 +129,9 @@ static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
         if (!ret) {
                 ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
                 if (ret) {
-                        spin_lock_irqsave(&atchan->lock, flags);
+                        spin_lock_bh(&atchan->lock);
                         atchan->descs_allocated++;
-                        spin_unlock_irqrestore(&atchan->lock, flags);
+                        spin_unlock_bh(&atchan->lock);
                 } else {
                         dev_err(chan2dev(&atchan->chan_common),
                                         "not enough descriptors available\n");
@@ -152,9 +150,8 @@ static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
 {
         if (desc) {
                 struct at_desc *child;
-                unsigned long flags;
 
-                spin_lock_irqsave(&atchan->lock, flags);
+                spin_lock_bh(&atchan->lock);
                 list_for_each_entry(child, &desc->tx_list, desc_node)
                         dev_vdbg(chan2dev(&atchan->chan_common),
                                         "moving child desc %p to freelist\n",
@@ -163,14 +160,14 @@ static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
                 dev_vdbg(chan2dev(&atchan->chan_common),
                          "moving desc %p to freelist\n", desc);
                 list_add(&desc->desc_node, &atchan->free_list);
-                spin_unlock_irqrestore(&atchan->lock, flags);
+                spin_unlock_bh(&atchan->lock);
         }
 }
 
 /**
- * atc_desc_chain - build chain adding a descriptor
- * @first: address of first descriptor of the chain
- * @prev: address of previous descriptor of the chain
+ * atc_desc_chain - build chain adding a descripor
+ * @first: address of first descripor of the chain
+ * @prev: address of previous descripor of the chain
  * @desc: descriptor to queue
  *
  * Called from prep_* functions
@@ -191,6 +188,27 @@ static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
 }
 
 /**
+ * atc_assign_cookie - compute and assign new cookie
+ * @atchan: channel we work on
+ * @desc: descriptor to assign cookie for
+ *
+ * Called with atchan->lock held and bh disabled
+ */
+static dma_cookie_t
+atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc)
+{
+        dma_cookie_t cookie = atchan->chan_common.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        atchan->chan_common.cookie = cookie;
+        desc->txd.cookie = cookie;
+
+        return cookie;
+}
+
+/**
  * atc_dostart - starts the DMA engine for real
  * @atchan: the channel we want to start
  * @first: first descriptor in the list we want to begin with
@@ -219,6 +237,10 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
 
         vdbg_dump_regs(atchan);
 
+        /* clear any pending interrupt */
+        while (dma_readl(atdma, EBCISR))
+                cpu_relax();
+
         channel_writel(atchan, SADDR, 0);
         channel_writel(atchan, DADDR, 0);
         channel_writel(atchan, CTRLA, 0);
@@ -243,9 +265,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
         dev_vdbg(chan2dev(&atchan->chan_common),
                 "descriptor %u complete\n", txd->cookie);
 
-        /* mark the descriptor as complete for non cyclic cases only */
-        if (!atc_chan_is_cyclic(atchan))
-                dma_cookie_complete(txd);
+        atchan->completed_cookie = txd->cookie;
 
         /* move children to free_list */
         list_splice_init(&desc->tx_list, &atchan->free_list);
@@ -279,7 +299,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
 
         /* for cyclic transfers,
          * no need to replay callback function while stopping */
-        if (!atc_chan_is_cyclic(atchan)) {
+        if (!test_bit(ATC_IS_CYCLIC, &atchan->status)) {
                 dma_async_tx_callback   callback = txd->callback;
                 void                    *param = txd->callback_param;
 
@@ -451,17 +471,16 @@ static void atc_handle_cyclic(struct at_dma_chan *atchan)
 static void atc_tasklet(unsigned long data)
 {
         struct at_dma_chan *atchan = (struct at_dma_chan *)data;
-        unsigned long flags;
 
-        spin_lock_irqsave(&atchan->lock, flags);
+        spin_lock(&atchan->lock);
         if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
                 atc_handle_error(atchan);
-        else if (atc_chan_is_cyclic(atchan))
+        else if (test_bit(ATC_IS_CYCLIC, &atchan->status))
                 atc_handle_cyclic(atchan);
         else
                 atc_advance_work(atchan);
 
-        spin_unlock_irqrestore(&atchan->lock, flags);
+        spin_unlock(&atchan->lock);
 }
 
 static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
@@ -520,10 +539,9 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
         struct at_desc          *desc = txd_to_at_desc(tx);
         struct at_dma_chan      *atchan = to_at_dma_chan(tx->chan);
         dma_cookie_t            cookie;
-        unsigned long           flags;
 
-        spin_lock_irqsave(&atchan->lock, flags);
-        cookie = dma_cookie_assign(tx);
+        spin_lock_bh(&atchan->lock);
+        cookie = atc_assign_cookie(atchan, desc);
 
         if (list_empty(&atchan->active_list)) {
                 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
@@ -536,7 +554,7 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
                 list_add_tail(&desc->desc_node, &atchan->queue);
         }
 
-        spin_unlock_irqrestore(&atchan->lock, flags);
+        spin_unlock_bh(&atchan->lock);
 
         return cookie;
 }
@@ -572,6 +590,7 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
                 return NULL;
         }
 
+        ctrla =   ATC_DEFAULT_CTRLA;
         ctrlb =   ATC_DEFAULT_CTRLB | ATC_IEN
                 | ATC_SRC_ADDR_MODE_INCR
                 | ATC_DST_ADDR_MODE_INCR
@@ -582,13 +601,13 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
          * of the most common optimization.
          */
         if (!((src | dest  | len) & 3)) {
-                ctrla = ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD;
+                ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD;
                 src_width = dst_width = 2;
         } else if (!((src | dest | len) & 1)) {
-                ctrla = ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD;
+                ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD;
                 src_width = dst_width = 1;
         } else {
-                ctrla = ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE;
+                ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE;
                 src_width = dst_width = 0;
         }
 
@@ -634,16 +653,14 @@ err_desc_get:
  * @sg_len: number of entries in @scatterlist
  * @direction: DMA direction
  * @flags: tx descriptor status flags
- * @context: transaction context (ignored)
  */
 static struct dma_async_tx_descriptor *
 atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-                unsigned int sg_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags)
 {
         struct at_dma_chan      *atchan = to_at_dma_chan(chan);
         struct at_dma_slave     *atslave = chan->private;
-        struct dma_slave_config *sconfig = &atchan->dma_sconfig;
         struct at_desc          *first = NULL;
         struct at_desc          *prev = NULL;
         u32                     ctrla;
@@ -657,27 +674,27 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 
         dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
                         sg_len,
-                        direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
+                        direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE",
                         flags);
 
         if (unlikely(!atslave || !sg_len)) {
-                dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n");
+                dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
                 return NULL;
         }
 
-        ctrla =   ATC_SCSIZE(sconfig->src_maxburst)
-                | ATC_DCSIZE(sconfig->dst_maxburst);
+        reg_width = atslave->reg_width;
+
+        ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla;
         ctrlb = ATC_IEN;
 
         switch (direction) {
-        case DMA_MEM_TO_DEV:
-                reg_width = convert_buswidth(sconfig->dst_addr_width);
+        case DMA_TO_DEVICE:
                 ctrla |=  ATC_DST_WIDTH(reg_width);
                 ctrlb |=  ATC_DST_ADDR_MODE_FIXED
                         | ATC_SRC_ADDR_MODE_INCR
                         | ATC_FC_MEM2PER
                         | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF);
-                reg = sconfig->dst_addr;
+                reg = atslave->tx_reg;
                 for_each_sg(sgl, sg, sg_len, i) {
                         struct at_desc  *desc;
                         u32             len;
@@ -689,11 +706,6 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 
                         mem = sg_dma_address(sg);
                         len = sg_dma_len(sg);
-                        if (unlikely(!len)) {
-                                dev_dbg(chan2dev(chan),
-                                        "prep_slave_sg: sg(%d) data length is zero\n", i);
-                                goto err;
-                        }
                         mem_width = 2;
                         if (unlikely(mem & 3 || len & 3))
                                 mem_width = 0;
@@ -709,15 +721,14 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                         total_len += len;
                 }
                 break;
-        case DMA_DEV_TO_MEM:
-                reg_width = convert_buswidth(sconfig->src_addr_width);
+        case DMA_FROM_DEVICE:
                 ctrla |=  ATC_SRC_WIDTH(reg_width);
                 ctrlb |=  ATC_DST_ADDR_MODE_INCR
                         | ATC_SRC_ADDR_MODE_FIXED
                         | ATC_FC_PER2MEM
                         | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF);
 
-                reg = sconfig->src_addr;
+                reg = atslave->rx_reg;
                 for_each_sg(sgl, sg, sg_len, i) {
                         struct at_desc  *desc;
                         u32             len;
@@ -729,11 +740,6 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 
                         mem = sg_dma_address(sg);
                         len = sg_dma_len(sg);
-                        if (unlikely(!len)) {
-                                dev_dbg(chan2dev(chan),
-                                        "prep_slave_sg: sg(%d) data length is zero\n", i);
-                                goto err;
-                        }
                         mem_width = 2;
                         if (unlikely(mem & 3 || len & 3))
                                 mem_width = 0;
@@ -767,7 +773,6 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 
 err_desc_get:
         dev_err(chan2dev(chan), "not enough descriptors available\n");
-err:
         atc_desc_put(atchan, first);
         return NULL;
 }
@@ -778,7 +783,7 @@ err:
  */
 static int
 atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
-                size_t period_len, enum dma_transfer_direction direction)
+                size_t period_len, enum dma_data_direction direction)
 {
         if (period_len > (ATC_BTSIZE_MAX << reg_width))
                 goto err_out;
@@ -786,7 +791,7 @@ atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
                 goto err_out;
         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
                 goto err_out;
-        if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV))))
+        if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
                 goto err_out;
 
         return 0;
@@ -796,29 +801,26 @@ err_out:
 }
 
 /**
- * atc_dma_cyclic_fill_desc - Fill one period descriptor
+ * atc_dma_cyclic_fill_desc - Fill one period decriptor
  */
 static int
-atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
+atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
                 unsigned int period_index, dma_addr_t buf_addr,
-                unsigned int reg_width, size_t period_len,
-                enum dma_transfer_direction direction)
+                size_t period_len, enum dma_data_direction direction)
 {
-        struct at_dma_chan      *atchan = to_at_dma_chan(chan);
-        struct dma_slave_config *sconfig = &atchan->dma_sconfig;
-        u32                     ctrla;
+        u32             ctrla;
+        unsigned int    reg_width = atslave->reg_width;
 
         /* prepare common CRTLA value */
-        ctrla =   ATC_SCSIZE(sconfig->src_maxburst)
-                | ATC_DCSIZE(sconfig->dst_maxburst)
+        ctrla =   ATC_DEFAULT_CTRLA | atslave->ctrla
                 | ATC_DST_WIDTH(reg_width)
                 | ATC_SRC_WIDTH(reg_width)
                 | period_len >> reg_width;
 
         switch (direction) {
-        case DMA_MEM_TO_DEV:
+        case DMA_TO_DEVICE:
                 desc->lli.saddr = buf_addr + (period_len * period_index);
-                desc->lli.daddr = sconfig->dst_addr;
+                desc->lli.daddr = atslave->tx_reg;
                 desc->lli.ctrla = ctrla;
                 desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
                                 | ATC_SRC_ADDR_MODE_INCR
@@ -827,8 +829,8 @@ atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
                                 | ATC_DIF(AT_DMA_PER_IF);
                 break;
 
-        case DMA_DEV_TO_MEM:
-                desc->lli.saddr = sconfig->src_addr;
+        case DMA_FROM_DEVICE:
+                desc->lli.saddr = atslave->rx_reg;
                 desc->lli.daddr = buf_addr + (period_len * period_index);
                 desc->lli.ctrla = ctrla;
                 desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
@@ -852,26 +854,21 @@ atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
  * @buf_len: total number of bytes for the entire buffer
  * @period_len: number of bytes for each period
  * @direction: transfer direction, to or from device
- * @flags: tx descriptor status flags
- * @context: transfer context (ignored)
  */
 static struct dma_async_tx_descriptor *
 atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
-                size_t period_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                size_t period_len, enum dma_data_direction direction)
 {
         struct at_dma_chan      *atchan = to_at_dma_chan(chan);
         struct at_dma_slave     *atslave = chan->private;
-        struct dma_slave_config *sconfig = &atchan->dma_sconfig;
         struct at_desc          *first = NULL;
         struct at_desc          *prev = NULL;
         unsigned long           was_cyclic;
-        unsigned int            reg_width;
         unsigned int            periods = buf_len / period_len;
         unsigned int            i;
 
         dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
-                        direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
+                        direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE",
                         buf_addr,
                         periods, buf_len, period_len);
 
@@ -886,13 +883,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
                 return NULL;
         }
 
-        if (sconfig->direction == DMA_MEM_TO_DEV)
-                reg_width = convert_buswidth(sconfig->dst_addr_width);
-        else
-                reg_width = convert_buswidth(sconfig->src_addr_width);
-
         /* Check for too big/unaligned periods and unaligned DMA buffer */
-        if (atc_dma_cyclic_check_values(reg_width, buf_addr,
+        if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr,
                                         period_len, direction))
                 goto err_out;
 
@@ -904,8 +896,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
                 if (!desc)
                         goto err_desc_get;
 
-                if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
-                                             reg_width, period_len, direction))
+                if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr,
+                                                period_len, direction))
                         goto err_desc_get;
 
                 atc_desc_chain(&first, &prev, desc);
@@ -928,23 +920,6 @@ err_out:
         return NULL;
 }
 
-static int set_runtime_config(struct dma_chan *chan,
-                              struct dma_slave_config *sconfig)
-{
-        struct at_dma_chan      *atchan = to_at_dma_chan(chan);
-
-        /* Check if it is chan is configured for slave transfers */
-        if (!chan->private)
-                return -EINVAL;
-
-        memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
-
-        convert_burst(&atchan->dma_sconfig.src_maxburst);
-        convert_burst(&atchan->dma_sconfig.dst_maxburst);
-
-        return 0;
-}
-
 
 static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                        unsigned long arg)
@@ -952,29 +927,28 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
         struct at_dma_chan      *atchan = to_at_dma_chan(chan);
         struct at_dma           *atdma = to_at_dma(chan->device);
         int                     chan_id = atchan->chan_common.chan_id;
-        unsigned long           flags;
 
         LIST_HEAD(list);
 
         dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd);
 
         if (cmd == DMA_PAUSE) {
-                spin_lock_irqsave(&atchan->lock, flags);
+                spin_lock_bh(&atchan->lock);
 
                 dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
                 set_bit(ATC_IS_PAUSED, &atchan->status);
 
-                spin_unlock_irqrestore(&atchan->lock, flags);
+                spin_unlock_bh(&atchan->lock);
         } else if (cmd == DMA_RESUME) {
-                if (!atc_chan_is_paused(atchan))
+                if (!test_bit(ATC_IS_PAUSED, &atchan->status))
                         return 0;
 
-                spin_lock_irqsave(&atchan->lock, flags);
+                spin_lock_bh(&atchan->lock);
 
                 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
                 clear_bit(ATC_IS_PAUSED, &atchan->status);
 
-                spin_unlock_irqrestore(&atchan->lock, flags);
+                spin_unlock_bh(&atchan->lock);
         } else if (cmd == DMA_TERMINATE_ALL) {
                 struct at_desc  *desc, *_desc;
                 /*
@@ -983,7 +957,7 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                  * channel. We still have to poll the channel enable bit due
                  * to AHB/HSB limitations.
                  */
-                spin_lock_irqsave(&atchan->lock, flags);
+                spin_lock_bh(&atchan->lock);
 
                 /* disabling channel: must also remove suspend state */
                 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
@@ -1004,9 +978,7 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                 /* if channel dedicated to cyclic operations, free it */
                 clear_bit(ATC_IS_CYCLIC, &atchan->status);
 
-                spin_unlock_irqrestore(&atchan->lock, flags);
-        } else if (cmd == DMA_SLAVE_CONFIG) {
-                return set_runtime_config(chan, (struct dma_slave_config *)arg);
+                spin_unlock_bh(&atchan->lock);
         } else {
                 return -ENXIO;
         }
@@ -1032,27 +1004,32 @@ atc_tx_status(struct dma_chan *chan,
         struct at_dma_chan      *atchan = to_at_dma_chan(chan);
         dma_cookie_t            last_used;
         dma_cookie_t            last_complete;
-        unsigned long           flags;
         enum dma_status         ret;
 
-        spin_lock_irqsave(&atchan->lock, flags);
+        spin_lock_bh(&atchan->lock);
 
-        ret = dma_cookie_status(chan, cookie, txstate);
+        last_complete = atchan->completed_cookie;
+        last_used = chan->cookie;
+
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
         if (ret != DMA_SUCCESS) {
                 atc_cleanup_descriptors(atchan);
 
-                ret = dma_cookie_status(chan, cookie, txstate);
-        }
+                last_complete = atchan->completed_cookie;
+                last_used = chan->cookie;
 
-        last_complete = chan->completed_cookie;
-        last_used = chan->cookie;
+                ret = dma_async_is_complete(cookie, last_complete, last_used);
+        }
 
-        spin_unlock_irqrestore(&atchan->lock, flags);
+        spin_unlock_bh(&atchan->lock);
 
         if (ret != DMA_SUCCESS)
-                dma_set_residue(txstate, atc_first_active(atchan)->len);
+                dma_set_tx_state(txstate, last_complete, last_used,
+                        atc_first_active(atchan)->len);
+        else
+                dma_set_tx_state(txstate, last_complete, last_used, 0);
 
-        if (atc_chan_is_paused(atchan))
+        if (test_bit(ATC_IS_PAUSED, &atchan->status))
                 ret = DMA_PAUSED;
 
         dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n",
@@ -1069,19 +1046,18 @@ atc_tx_status(struct dma_chan *chan,
 static void atc_issue_pending(struct dma_chan *chan)
 {
         struct at_dma_chan      *atchan = to_at_dma_chan(chan);
-        unsigned long           flags;
 
         dev_vdbg(chan2dev(chan), "issue_pending\n");
 
         /* Not needed for cyclic transfers */
-        if (atc_chan_is_cyclic(atchan))
+        if (test_bit(ATC_IS_CYCLIC, &atchan->status))
                 return;
 
-        spin_lock_irqsave(&atchan->lock, flags);
+        spin_lock_bh(&atchan->lock);
         if (!atc_chan_is_enabled(atchan)) {
                 atc_advance_work(atchan);
         }
-        spin_unlock_irqrestore(&atchan->lock, flags);
+        spin_unlock_bh(&atchan->lock);
 }
 
 /**
@@ -1097,7 +1073,6 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
         struct at_dma           *atdma = to_at_dma(chan->device);
         struct at_desc          *desc;
         struct at_dma_slave     *atslave;
-        unsigned long           flags;
         int                     i;
         u32                     cfg;
         LIST_HEAD(tmp_list);
@@ -1141,11 +1116,11 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
                 list_add_tail(&desc->desc_node, &tmp_list);
         }
 
-        spin_lock_irqsave(&atchan->lock, flags);
+        spin_lock_bh(&atchan->lock);
         atchan->descs_allocated = i;
         list_splice(&tmp_list, &atchan->free_list);
-        dma_cookie_init(chan);
-        spin_unlock_irqrestore(&atchan->lock, flags);
+        atchan->completed_cookie = chan->cookie = 1;
+        spin_unlock_bh(&atchan->lock);
 
         /* channel parameters */
         channel_writel(atchan, CFG, cfg);
@@ -1192,56 +1167,6 @@ static void atc_free_chan_resources(struct dma_chan *chan)
 
 /*--  Module Management  -----------------------------------------------*/
 
-/* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
-static struct at_dma_platform_data at91sam9rl_config = {
-        .nr_channels = 2,
-};
-static struct at_dma_platform_data at91sam9g45_config = {
-        .nr_channels = 8,
-};
-
-#if defined(CONFIG_OF)
-static const struct of_device_id atmel_dma_dt_ids[] = {
-        {
-                .compatible = "atmel,at91sam9rl-dma",
-                .data = &at91sam9rl_config,
-        }, {
-                .compatible = "atmel,at91sam9g45-dma",
-                .data = &at91sam9g45_config,
-        }, {
-                /* sentinel */
-        }
-};
-
-MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids);
-#endif
-
-static const struct platform_device_id atdma_devtypes[] = {
-        {
-                .name = "at91sam9rl_dma",
-                .driver_data = (unsigned long) &at91sam9rl_config,
-        }, {
-                .name = "at91sam9g45_dma",
-                .driver_data = (unsigned long) &at91sam9g45_config,
-        }, {
-                /* sentinel */
-        }
-};
-
-static inline const struct at_dma_platform_data * __init at_dma_get_driver_data(
-                                                struct platform_device *pdev)
-{
-        if (pdev->dev.of_node) {
-                const struct of_device_id *match;
-                match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
-                if (match == NULL)
-                        return NULL;
-                return match->data;
-        }
-        return (struct at_dma_platform_data *)
-                        platform_get_device_id(pdev)->driver_data;
-}
-
 /**
  * at_dma_off - disable DMA controller
  * @atdma: the Atmel HDAMC device
@@ -1260,23 +1185,18 @@ static void at_dma_off(struct at_dma *atdma)
 
 static int __init at_dma_probe(struct platform_device *pdev)
 {
+        struct at_dma_platform_data *pdata;
         struct resource         *io;
         struct at_dma           *atdma;
         size_t                  size;
         int                     irq;
         int                     err;
         int                     i;
-        const struct at_dma_platform_data *plat_dat;
 
-        /* setup platform data for each SoC */
-        dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
-        dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
-        dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
-
-        /* get DMA parameters from controller type */
-        plat_dat = at_dma_get_driver_data(pdev);
-        if (!plat_dat)
-                return -ENODEV;
+        /* get DMA Controller parameters from platform */
+        pdata = pdev->dev.platform_data;
+        if (!pdata || pdata->nr_channels > AT_DMA_MAX_NR_CHANNELS)
+                return -EINVAL;
 
         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!io)
@@ -1287,14 +1207,14 @@ static int __init at_dma_probe(struct platform_device *pdev)
                 return irq;
 
         size = sizeof(struct at_dma);
-        size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
+        size += pdata->nr_channels * sizeof(struct at_dma_chan);
         atdma = kzalloc(size, GFP_KERNEL);
         if (!atdma)
                 return -ENOMEM;
 
-        /* discover transaction capabilities */
-        atdma->dma_common.cap_mask = plat_dat->cap_mask;
-        atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
+        /* discover transaction capabilites from the platform data */
+        atdma->dma_common.cap_mask = pdata->cap_mask;
+        atdma->all_chan_mask = (1 << pdata->nr_channels) - 1;
 
         size = resource_size(io);
         if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
@@ -1340,11 +1260,12 @@ static int __init at_dma_probe(struct platform_device *pdev)
 
         /* initialize channels related values */
         INIT_LIST_HEAD(&atdma->dma_common.channels);
-        for (i = 0; i < plat_dat->nr_channels; i++) {
+        for (i = 0; i < pdata->nr_channels; i++, atdma->dma_common.chancnt++) {
                 struct at_dma_chan      *atchan = &atdma->chan[i];
 
                 atchan->chan_common.device = &atdma->dma_common;
-                dma_cookie_init(&atchan->chan_common);
+                atchan->chan_common.cookie = atchan->completed_cookie = 1;
+                atchan->chan_common.chan_id = i;
                 list_add_tail(&atchan->chan_common.device_node,
                                 &atdma->dma_common.channels);
 
@@ -1358,7 +1279,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
 
                 tasklet_init(&atchan->tasklet, atc_tasklet,
                                 (unsigned long)atchan);
-                atc_enable_chan_irq(atdma, i);
+                atc_enable_irq(atchan);
         }
 
         /* set base routines */
@@ -1372,20 +1293,22 @@ static int __init at_dma_probe(struct platform_device *pdev)
         if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
                 atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
 
-        if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
+        if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask))
                 atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
-                /* controller can do slave DMA: can trigger cyclic transfers */
-                dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask);
+
+        if (dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask))
                 atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
+
+        if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ||
+            dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask))
                 atdma->dma_common.device_control = atc_control;
-        }
 
         dma_writel(atdma, EN, AT_DMA_ENABLE);
 
         dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
           dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
           dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)  ? "slave " : "",
-          plat_dat->nr_channels);
+          atdma->dma_common.chancnt);
 
         dma_async_device_register(&atdma->dma_common);
 
@@ -1425,7 +1348,7 @@ static int __exit at_dma_remove(struct platform_device *pdev)
                 struct at_dma_chan      *atchan = to_at_dma_chan(chan);
 
                 /* Disable interrupts */
-                atc_disable_chan_irq(atdma, chan->chan_id);
+                atc_disable_irq(atchan);
                 tasklet_disable(&atchan->tasklet);
 
                 tasklet_kill(&atchan->tasklet);
@@ -1454,112 +1377,27 @@ static void at_dma_shutdown(struct platform_device *pdev)
         clk_disable(atdma->clk);
 }
 
-static int at_dma_prepare(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct at_dma *atdma = platform_get_drvdata(pdev);
-        struct dma_chan *chan, *_chan;
-
-        list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
-                        device_node) {
-                struct at_dma_chan *atchan = to_at_dma_chan(chan);
-                /* wait for transaction completion (except in cyclic case) */
-                if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan))
-                        return -EAGAIN;
-        }
-        return 0;
-}
-
-static void atc_suspend_cyclic(struct at_dma_chan *atchan)
-{
-        struct dma_chan *chan = &atchan->chan_common;
-
-        /* Channel should be paused by user
-         * do it anyway even if it is not done already */
-        if (!atc_chan_is_paused(atchan)) {
-                dev_warn(chan2dev(chan),
-                "cyclic channel not paused, should be done by channel user\n");
-                atc_control(chan, DMA_PAUSE, 0);
-        }
-
-        /* now preserve additional data for cyclic operations */
-        /* next descriptor address in the cyclic list */
-        atchan->save_dscr = channel_readl(atchan, DSCR);
-
-        vdbg_dump_regs(atchan);
-}
-
 static int at_dma_suspend_noirq(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         struct at_dma *atdma = platform_get_drvdata(pdev);
-        struct dma_chan *chan, *_chan;
-
-        /* preserve data */
-        list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
-                        device_node) {
-                struct at_dma_chan *atchan = to_at_dma_chan(chan);
 
-                if (atc_chan_is_cyclic(atchan))
-                        atc_suspend_cyclic(atchan);
-                atchan->save_cfg = channel_readl(atchan, CFG);
-        }
-        atdma->save_imr = dma_readl(atdma, EBCIMR);
-
-        /* disable DMA controller */
-        at_dma_off(atdma);
+        at_dma_off(platform_get_drvdata(pdev));
         clk_disable(atdma->clk);
         return 0;
 }
 
-static void atc_resume_cyclic(struct at_dma_chan *atchan)
-{
-        struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
-
-        /* restore channel status for cyclic descriptors list:
-         * next descriptor in the cyclic list at the time of suspend */
-        channel_writel(atchan, SADDR, 0);
-        channel_writel(atchan, DADDR, 0);
-        channel_writel(atchan, CTRLA, 0);
-        channel_writel(atchan, CTRLB, 0);
-        channel_writel(atchan, DSCR, atchan->save_dscr);
-        dma_writel(atdma, CHER, atchan->mask);
-
-        /* channel pause status should be removed by channel user
-         * We cannot take the initiative to do it here */
-
-        vdbg_dump_regs(atchan);
-}
-
 static int at_dma_resume_noirq(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         struct at_dma *atdma = platform_get_drvdata(pdev);
-        struct dma_chan *chan, *_chan;
 
-        /* bring back DMA controller */
         clk_enable(atdma->clk);
         dma_writel(atdma, EN, AT_DMA_ENABLE);
-
-        /* clear any pending interrupt */
-        while (dma_readl(atdma, EBCISR))
-                cpu_relax();
-
-        /* restore saved data */
-        dma_writel(atdma, EBCIER, atdma->save_imr);
-        list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
-                        device_node) {
-                struct at_dma_chan *atchan = to_at_dma_chan(chan);
-
-                channel_writel(atchan, CFG, atchan->save_cfg);
-                if (atc_chan_is_cyclic(atchan))
-                        atc_resume_cyclic(atchan);
-        }
         return 0;
 }
 
 static const struct dev_pm_ops at_dma_dev_pm_ops = {
-        .prepare = at_dma_prepare,
         .suspend_noirq = at_dma_suspend_noirq,
         .resume_noirq = at_dma_resume_noirq,
 };
@@ -1567,11 +1405,9 @@ static const struct dev_pm_ops at_dma_dev_pm_ops = {
 static struct platform_driver at_dma_driver = {
         .remove         = __exit_p(at_dma_remove),
         .shutdown       = at_dma_shutdown,
-        .id_table       = atdma_devtypes,
         .driver = {
                 .name   = "at_hdmac",
                 .pm     = &at_dma_dev_pm_ops,
-                .of_match_table = of_match_ptr(atmel_dma_dt_ids),
         },
 };
 
diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
index 116e4adffb0..087dbf1dd39 100644
--- a/drivers/dma/at_hdmac_regs.h
+++ b/drivers/dma/at_hdmac_regs.h
@@ -11,7 +11,7 @@
 #ifndef AT_HDMAC_REGS_H
 #define AT_HDMAC_REGS_H
 
-#include <linux/platform_data/dma-atmel.h>
+#include <mach/at_hdmac.h>
 
 #define AT_DMA_MAX_NR_CHANNELS  8
 
@@ -87,26 +87,7 @@
 /* Bitfields in CTRLA */
 #define ATC_BTSIZE_MAX          0xFFFFUL        /* Maximum Buffer Transfer Size */
 #define ATC_BTSIZE(x)           (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
-#define ATC_SCSIZE_MASK         (0x7 << 16)     /* Source Chunk Transfer Size */
-#define         ATC_SCSIZE(x)           (ATC_SCSIZE_MASK & ((x) << 16))
-#define         ATC_SCSIZE_1            (0x0 << 16)
-#define         ATC_SCSIZE_4            (0x1 << 16)
-#define         ATC_SCSIZE_8            (0x2 << 16)
-#define         ATC_SCSIZE_16           (0x3 << 16)
-#define         ATC_SCSIZE_32           (0x4 << 16)
-#define         ATC_SCSIZE_64           (0x5 << 16)
-#define         ATC_SCSIZE_128          (0x6 << 16)
-#define         ATC_SCSIZE_256          (0x7 << 16)
-#define ATC_DCSIZE_MASK         (0x7 << 20)     /* Destination Chunk Transfer Size */
-#define         ATC_DCSIZE(x)           (ATC_DCSIZE_MASK & ((x) << 20))
-#define         ATC_DCSIZE_1            (0x0 << 20)
-#define         ATC_DCSIZE_4            (0x1 << 20)
-#define         ATC_DCSIZE_8            (0x2 << 20)
-#define         ATC_DCSIZE_16           (0x3 << 20)
-#define         ATC_DCSIZE_32           (0x4 << 20)
-#define         ATC_DCSIZE_64           (0x5 << 20)
-#define         ATC_DCSIZE_128          (0x6 << 20)
-#define         ATC_DCSIZE_256          (0x7 << 20)
+/* Chunck Tranfer size definitions are in at_hdmac.h */
 #define ATC_SRC_WIDTH_MASK      (0x3 << 24)     /* Source Single Transfer Size */
 #define         ATC_SRC_WIDTH(x)        ((x) << 24)
 #define         ATC_SRC_WIDTH_BYTE      (0x0 << 24)
@@ -223,11 +204,8 @@ enum atc_status {
  * @status: transmit status information from irq/prep* functions
  *                to tasklet (use atomic operations)
  * @tasklet: bottom half to finish transaction work
- * @save_cfg: configuration register that is saved on suspend/resume cycle
- * @save_dscr: for cyclic operations, preserve next descriptor address in
- *             the cyclic list on suspend/resume cycle
- * @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG
  * @lock: serializes enqueue/dequeue operations to descriptors lists
+ * @completed_cookie: identifier for the most recently completed operation
  * @active_list: list of descriptors dmaengine is being running on
  * @queue: list of descriptors ready to be submitted to engine
  * @free_list: list of descriptors usable by the channel
@@ -240,13 +218,11 @@ struct at_dma_chan {
         u8                      mask;
         unsigned long           status;
         struct tasklet_struct   tasklet;
-        u32                     save_cfg;
-        u32                     save_dscr;
-        struct dma_slave_config dma_sconfig;
 
         spinlock_t              lock;
 
         /* these other elements are all protected by lock */
+        dma_cookie_t            completed_cookie;
         struct list_head        active_list;
         struct list_head        queue;
         struct list_head        free_list;
@@ -264,46 +240,14 @@ static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
         return container_of(dchan, struct at_dma_chan, chan_common);
 }
 
-/*
- * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
- * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
- *
- * This can be done by finding most significant bit set.
- */
-static inline void convert_burst(u32 *maxburst)
-{
-        if (*maxburst > 1)
-                *maxburst = fls(*maxburst) - 2;
-        else
-                *maxburst = 0;
-}
-
-/*
- * Fix sconfig's bus width according to at_hdmac.
- * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
- */
-static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
-{
-        switch (addr_width) {
-        case DMA_SLAVE_BUSWIDTH_2_BYTES:
-                return 1;
-        case DMA_SLAVE_BUSWIDTH_4_BYTES:
-                return 2;
-        default:
-                /* For 1 byte width or fallback */
-                return 0;
-        }
-}
 
 /*--  Controller  ------------------------------------------------------*/
 
 /**
  * struct at_dma - internal representation of an Atmel HDMA Controller
  * @chan_common: common dmaengine dma_device object members
- * @atdma_devtype: identifier of DMA controller compatibility
  * @ch_regs: memory mapped register base
  * @clk: dma controller clock
- * @save_imr: interrupt mask register that is saved on suspend/resume cycle
  * @all_chan_mask: all channels availlable in a mask
  * @dma_desc_pool: base of DMA descriptor region (DMA address)
  * @chan: channels table to store at_dma_chan structures
@@ -312,7 +256,6 @@ struct at_dma {
         struct dma_device       dma_common;
         void __iomem            *regs;
         struct clk              *clk;
-        u32                     save_imr;
 
         u8                      all_chan_mask;
 
@@ -376,27 +319,28 @@ static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
 }
 
 
-static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
+static void atc_setup_irq(struct at_dma_chan *atchan, int on)
 {
-        u32 ebci;
+        struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
+        u32             ebci;
 
         /* enable interrupts on buffer transfer completion & error */
-        ebci =    AT_DMA_BTC(chan_id)
-                | AT_DMA_ERR(chan_id);
+        ebci =    AT_DMA_BTC(atchan->chan_common.chan_id)
+                | AT_DMA_ERR(atchan->chan_common.chan_id);
         if (on)
                 dma_writel(atdma, EBCIER, ebci);
         else
                 dma_writel(atdma, EBCIDR, ebci);
 }
 
-static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
+static inline void atc_enable_irq(struct at_dma_chan *atchan)
 {
-        atc_setup_irq(atdma, chan_id, 1);
+        atc_setup_irq(atchan, 1);
 }
 
-static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
+static inline void atc_disable_irq(struct at_dma_chan *atchan)
 {
-        atc_setup_irq(atdma, chan_id, 0);
+        atc_setup_irq(atchan, 0);
 }
 
 
@@ -411,23 +355,6 @@ static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
         return !!(dma_readl(atdma, CHSR) & atchan->mask);
 }
 
-/**
- * atc_chan_is_paused - test channel pause/resume status
- * @atchan: channel we want to test status
- */
-static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
-{
-        return test_bit(ATC_IS_PAUSED, &atchan->status);
-}
-
-/**
- * atc_chan_is_cyclic - test if given channel has cyclic property set
- * @atchan: channel we want to test status
- */
-static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
-{
-        return test_bit(ATC_IS_CYCLIC, &atchan->status);
-}
 
 /**
  * set_desc_eol - set end-of-link to descriptor so it will end transfer
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index aa384e53b7a..4234f416ef1 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -24,7 +24,6 @@
 #include <mach/coh901318.h>
 
 #include "coh901318_lli.h"
-#include "dmaengine.h"
 
 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
 
@@ -40,7 +39,7 @@ struct coh901318_desc {
         struct scatterlist *sg;
         unsigned int sg_len;
         struct coh901318_lli *lli;
-        enum dma_transfer_direction dir;
+        enum dma_data_direction dir;
         unsigned long flags;
         u32 head_config;
         u32 head_ctrl;
@@ -60,6 +59,7 @@ struct coh901318_base {
 struct coh901318_chan {
         spinlock_t lock;
         int allocated;
+        int completed;
         int id;
         int stopped;
 
@@ -104,6 +104,13 @@ static void coh901318_list_print(struct coh901318_chan *cohc,
 static struct coh901318_base *debugfs_dma_base;
 static struct dentry *dma_dentry;
 
+static int coh901318_debugfs_open(struct inode *inode, struct file *file)
+{
+
+        file->private_data = inode->i_private;
+        return 0;
+}
+
 static int coh901318_debugfs_read(struct file *file, char __user *buf,
                                   size_t count, loff_t *f_pos)
 {
@@ -151,7 +158,7 @@ static int coh901318_debugfs_read(struct file *file, char __user *buf,
 
 static const struct file_operations coh901318_debugfs_status_operations = {
         .owner          = THIS_MODULE,
-        .open           = simple_open,
+        .open           = coh901318_debugfs_open,
         .read           = coh901318_debugfs_read,
         .llseek         = default_llseek,
 };
@@ -311,6 +318,20 @@ static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
 
         return 0;
 }
+static dma_cookie_t
+coh901318_assign_cookie(struct coh901318_chan *cohc,
+                        struct coh901318_desc *cohd)
+{
+        dma_cookie_t cookie = cohc->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        cohc->chan.cookie = cookie;
+        cohd->desc.cookie = cookie;
+
+        return cookie;
+}
 
 static struct coh901318_desc *
 coh901318_desc_get(struct coh901318_chan *cohc)
@@ -684,7 +705,7 @@ static void dma_tasklet(unsigned long data)
         callback_param = cohd_fin->desc.callback_param;
 
         /* sign this job as completed on the channel */
-        dma_cookie_complete(&cohd_fin->desc);
+        cohc->completed = cohd_fin->desc.cookie;
 
         /* release the lli allocation and remove the descriptor */
         coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
@@ -908,7 +929,7 @@ static int coh901318_alloc_chan_resources(struct dma_chan *chan)
         coh901318_config(cohc, NULL);
 
         cohc->allocated = 1;
-        dma_cookie_init(chan);
+        cohc->completed = chan->cookie = 1;
 
         spin_unlock_irqrestore(&cohc->lock, flags);
 
@@ -945,16 +966,16 @@ coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
                                                    desc);
         struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
         unsigned long flags;
-        dma_cookie_t cookie;
 
         spin_lock_irqsave(&cohc->lock, flags);
-        cookie = dma_cookie_assign(tx);
+
+        tx->cookie = coh901318_assign_cookie(cohc, cohd);
 
         coh901318_desc_queue(cohc, cohd);
 
         spin_unlock_irqrestore(&cohc->lock, flags);
 
-        return cookie;
+        return tx->cookie;
 }
 
 static struct dma_async_tx_descriptor *
@@ -1013,8 +1034,8 @@ coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 
 static struct dma_async_tx_descriptor *
 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-                        unsigned int sg_len, enum dma_transfer_direction direction,
-                        unsigned long flags, void *context)
+                        unsigned int sg_len, enum dma_data_direction direction,
+                        unsigned long flags)
 {
         struct coh901318_chan *cohc = to_coh901318_chan(chan);
         struct coh901318_lli *lli;
@@ -1033,7 +1054,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 
         if (!sgl)
                 goto out;
-        if (sg_dma_len(sgl) == 0)
+        if (sgl->length == 0)
                 goto out;
 
         spin_lock_irqsave(&cohc->lock, flg);
@@ -1056,7 +1077,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
         ctrl_last |= cohc->runtime_ctrl;
         ctrl |= cohc->runtime_ctrl;
 
-        if (direction == DMA_MEM_TO_DEV) {
+        if (direction == DMA_TO_DEVICE) {
                 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
 
@@ -1064,7 +1085,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                 ctrl_chained |= tx_flags;
                 ctrl_last |= tx_flags;
                 ctrl |= tx_flags;
-        } else if (direction == DMA_DEV_TO_MEM) {
+        } else if (direction == DMA_FROM_DEVICE) {
                 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
 
@@ -1144,12 +1165,17 @@ coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
                  struct dma_tx_state *txstate)
 {
         struct coh901318_chan *cohc = to_coh901318_chan(chan);
-        enum dma_status ret;
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
+        int ret;
 
-        ret = dma_cookie_status(chan, cookie, txstate);
-        /* FIXME: should be conditional on ret != DMA_SUCCESS? */
-        dma_set_residue(txstate, coh901318_get_bytes_left(chan));
+        last_complete = cohc->completed;
+        last_used = chan->cookie;
 
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
+
+        dma_set_tx_state(txstate, last_complete, last_used,
+                         coh901318_get_bytes_left(chan));
         if (ret == DMA_IN_PROGRESS && cohc->stopped)
                 ret = DMA_PAUSED;
 
@@ -1248,11 +1274,11 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
         int i = 0;
 
         /* We only support mem to per or per to mem transfers */
-        if (config->direction == DMA_DEV_TO_MEM) {
+        if (config->direction == DMA_FROM_DEVICE) {
                 addr = config->src_addr;
                 addr_width = config->src_addr_width;
                 maxburst = config->src_maxburst;
-        } else if (config->direction == DMA_MEM_TO_DEV) {
+        } else if (config->direction == DMA_TO_DEVICE) {
                 addr = config->dst_addr;
                 addr_width = config->dst_addr_width;
                 maxburst = config->dst_maxburst;
@@ -1438,32 +1464,34 @@ static int __init coh901318_probe(struct platform_device *pdev)
 
         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!io)
-                return -ENODEV;
+                goto err_get_resource;
 
         /* Map DMA controller registers to virtual memory */
-        if (devm_request_mem_region(&pdev->dev,
-                                    io->start,
-                                    resource_size(io),
-                                    pdev->dev.driver->name) == NULL)
-                return -ENOMEM;
+        if (request_mem_region(io->start,
+                               resource_size(io),
+                               pdev->dev.driver->name) == NULL) {
+                err = -EBUSY;
+                goto err_request_mem;
+        }
 
         pdata = pdev->dev.platform_data;
         if (!pdata)
-                return -ENODEV;
+                goto err_no_platformdata;
 
-        base = devm_kzalloc(&pdev->dev,
-                            ALIGN(sizeof(struct coh901318_base), 4) +
-                            pdata->max_channels *
-                            sizeof(struct coh901318_chan),
-                            GFP_KERNEL);
+        base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
+                       pdata->max_channels *
+                       sizeof(struct coh901318_chan),
+                       GFP_KERNEL);
         if (!base)
-                return -ENOMEM;
+                goto err_alloc_coh_dma_channels;
 
         base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
 
-        base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
-        if (!base->virtbase)
-                return -ENOMEM;
+        base->virtbase = ioremap(io->start, resource_size(io));
+        if (!base->virtbase) {
+                err = -ENOMEM;
+                goto err_no_ioremap;
+        }
 
         base->dev = &pdev->dev;
         base->platform = pdata;
@@ -1472,20 +1500,25 @@ static int __init coh901318_probe(struct platform_device *pdev)
 
         COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
 
+        platform_set_drvdata(pdev, base);
+
         irq = platform_get_irq(pdev, 0);
         if (irq < 0)
-                return irq;
-
-        err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, IRQF_DISABLED,
-                               "coh901318", base);
-        if (err)
-                return err;
+                goto err_no_irq;
+
+        err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
+                          "coh901318", base);
+        if (err) {
+                dev_crit(&pdev->dev,
+                         "Cannot allocate IRQ for DMA controller!\n");
+                goto err_request_irq;
+        }
 
         err = coh901318_pool_create(&base->pool, &pdev->dev,
                                     sizeof(struct coh901318_lli),
                                     32);
         if (err)
-                return err;
+                goto err_pool_create;
 
         /* init channels for device transfers */
         coh901318_base_init(&base->dma_slave,  base->platform->chans_slave,
@@ -1531,7 +1564,6 @@ static int __init coh901318_probe(struct platform_device *pdev)
         if (err)
                 goto err_register_memcpy;
 
-        platform_set_drvdata(pdev, base);
         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
                 (u32) base->virtbase);
 
@@ -1541,6 +1573,19 @@ static int __init coh901318_probe(struct platform_device *pdev)
         dma_async_device_unregister(&base->dma_slave);
  err_register_slave:
         coh901318_pool_destroy(&base->pool);
+ err_pool_create:
+        free_irq(platform_get_irq(pdev, 0), base);
+ err_request_irq:
+ err_no_irq:
+        iounmap(base->virtbase);
+ err_no_ioremap:
+        kfree(base);
+ err_alloc_coh_dma_channels:
+ err_no_platformdata:
+        release_mem_region(pdev->resource->start,
+                           resource_size(pdev->resource));
+ err_request_mem:
+ err_get_resource:
         return err;
 }
 
@@ -1551,6 +1596,11 @@ static int __exit coh901318_remove(struct platform_device *pdev)
         dma_async_device_unregister(&base->dma_memcpy);
         dma_async_device_unregister(&base->dma_slave);
         coh901318_pool_destroy(&base->pool);
+        free_irq(platform_get_irq(pdev, 0), base);
+        iounmap(base->virtbase);
+        kfree(base);
+        release_mem_region(pdev->resource->start,
+                           resource_size(pdev->resource));
         return 0;
 }
 
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c
index 780e0429b38..9f7e0e6a7ee 100644
--- a/drivers/dma/coh901318_lli.c
+++ b/drivers/dma/coh901318_lli.c
@@ -7,10 +7,11 @@
  * Author: Per Friden <per.friden@stericsson.com>
  */
 
+#include <linux/dma-mapping.h>
 #include <linux/spinlock.h>
+#include <linux/dmapool.h>
 #include <linux/memory.h>
 #include <linux/gfp.h>
-#include <linux/dmapool.h>
 #include <mach/coh901318.h>
 
 #include "coh901318_lli.h"
@@ -176,18 +177,18 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
                           struct coh901318_lli *lli,
                           dma_addr_t buf, unsigned int size,
                           dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
-                          enum dma_transfer_direction dir)
+                          enum dma_data_direction dir)
 {
         int s = size;
         dma_addr_t src;
         dma_addr_t dst;
 
 
-        if (dir == DMA_MEM_TO_DEV) {
+        if (dir == DMA_TO_DEVICE) {
                 src = buf;
                 dst = dev_addr;
 
-        } else if (dir == DMA_DEV_TO_MEM) {
+        } else if (dir == DMA_FROM_DEVICE) {
 
                 src = dev_addr;
                 dst = buf;
@@ -214,9 +215,9 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
 
                 lli = coh901318_lli_next(lli);
 
-                if (dir == DMA_MEM_TO_DEV)
+                if (dir == DMA_TO_DEVICE)
                         src += block_size;
-                else if (dir == DMA_DEV_TO_MEM)
+                else if (dir == DMA_FROM_DEVICE)
                         dst += block_size;
         }
 
@@ -233,7 +234,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
                       struct scatterlist *sgl, unsigned int nents,
                       dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
                       u32 ctrl_last,
-                      enum dma_transfer_direction dir, u32 ctrl_irq_mask)
+                      enum dma_data_direction dir, u32 ctrl_irq_mask)
 {
         int i;
         struct scatterlist *sg;
@@ -248,9 +249,9 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
 
         spin_lock(&pool->lock);
 
-        if (dir == DMA_MEM_TO_DEV)
+        if (dir == DMA_TO_DEVICE)
                 dst = dev_addr;
-        else if (dir == DMA_DEV_TO_MEM)
+        else if (dir == DMA_FROM_DEVICE)
                 src = dev_addr;
         else
                 goto err;
@@ -268,12 +269,12 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
                         ctrl_sg = ctrl ? ctrl : ctrl_last;
 
 
-                if (dir == DMA_MEM_TO_DEV)
+                if (dir == DMA_TO_DEVICE)
                         /* increment source address */
-                        src = sg_dma_address(sg);
+                        src = sg_phys(sg);
                 else
                         /* increment destination address */
-                        dst = sg_dma_address(sg);
+                        dst =  sg_phys(sg);
 
                 bytes_to_transfer = sg_dma_len(sg);
 
@@ -292,7 +293,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
                         lli->src_addr = src;
                         lli->dst_addr = dst;
 
-                        if (dir == DMA_DEV_TO_MEM)
+                        if (dir == DMA_FROM_DEVICE)
                                 dst += elem_size;
                         else
                                 src += elem_size;
diff --git a/drivers/dma/coh901318_lli.h b/drivers/dma/coh901318_lli.h
index abff3714fdd..7a5c80990e9 100644
--- a/drivers/dma/coh901318_lli.h
+++ b/drivers/dma/coh901318_lli.h
@@ -97,7 +97,7 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
                           struct coh901318_lli *lli,
                           dma_addr_t buf, unsigned int size,
                           dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last,
-                          enum dma_transfer_direction dir);
+                          enum dma_data_direction dir);
 
 /**
  * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
@@ -119,6 +119,6 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
                       struct scatterlist *sg, unsigned int nents,
                       dma_addr_t dev_addr, u32 ctrl_chained,
                       u32 ctrl, u32 ctrl_last,
-                      enum dma_transfer_direction dir, u32 ctrl_irq_mask);
+                      enum dma_data_direction dir, u32 ctrl_irq_mask);
 
 #endif /* COH901318_LLI_H */
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index a815d44c70a..b48967b499d 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -45,8 +45,6 @@
  * See Documentation/dmaengine.txt for more details
  */
 
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/module.h>
@@ -263,7 +261,7 @@ enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
         do {
                 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
                 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
-                        pr_err("%s: timeout!\n", __func__);
+                        printk(KERN_ERR "dma_sync_wait_timeout!\n");
                         return DMA_ERROR;
                 }
         } while (status == DMA_IN_PROGRESS);
@@ -314,7 +312,7 @@ static int __init dma_channel_table_init(void)
         }
 
         if (err) {
-                pr_err("initialization failure\n");
+                pr_err("dmaengine: initialization failure\n");
                 for_each_dma_cap_mask(cap, dma_cap_mask_all)
                         if (channel_table[cap])
                                 free_percpu(channel_table[cap]);
@@ -334,20 +332,6 @@ struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
 }
 EXPORT_SYMBOL(dma_find_channel);
 
-/*
- * net_dma_find_channel - find a channel for net_dma
- * net_dma has alignment requirements
- */
-struct dma_chan *net_dma_find_channel(void)
-{
-        struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
-        if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
-                return NULL;
-
-        return chan;
-}
-EXPORT_SYMBOL(net_dma_find_channel);
-
 /**
  * dma_issue_pending_all - flush all pending operations across all channels
  */
@@ -522,12 +506,12 @@ struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, v
                         err = dma_chan_get(chan);
 
                         if (err == -ENODEV) {
-                                pr_debug("%s: %s module removed\n",
-                                         __func__, dma_chan_name(chan));
+                                pr_debug("%s: %s module removed\n", __func__,
+                                         dma_chan_name(chan));
                                 list_del_rcu(&device->global_node);
                         } else if (err)
-                                pr_debug("%s: failed to get %s: (%d)\n",
-                                         __func__, dma_chan_name(chan), err);
+                                pr_debug("dmaengine: failed to get %s: (%d)\n",
+                                         dma_chan_name(chan), err);
                         else
                                 break;
                         if (--device->privatecnt == 0)
@@ -537,9 +521,7 @@ struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, v
         }
         mutex_unlock(&dma_list_mutex);
 
-        pr_debug("%s: %s (%s)\n",
-                 __func__,
-                 chan ? "success" : "fail",
+        pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
                  chan ? dma_chan_name(chan) : NULL);
 
         return chan;
@@ -582,8 +564,8 @@ void dmaengine_get(void)
                                 list_del_rcu(&device->global_node);
                                 break;
                         } else if (err)
-                                pr_debug("%s: failed to get %s: (%d)\n",
-                                       __func__, dma_chan_name(chan), err);
+                                pr_err("dmaengine: failed to get %s: (%d)\n",
+                                       dma_chan_name(chan), err);
                 }
         }
 
@@ -711,12 +693,12 @@ int dma_async_device_register(struct dma_device *device)
                 !device->device_prep_dma_interrupt);
         BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
                 !device->device_prep_dma_sg);
+        BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
+                !device->device_prep_slave_sg);
         BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
                 !device->device_prep_dma_cyclic);
         BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
                 !device->device_control);
-        BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
-                !device->device_prep_interleaved_dma);
 
         BUG_ON(!device->device_alloc_chan_resources);
         BUG_ON(!device->device_free_chan_resources);
@@ -1019,7 +1001,7 @@ dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
         while (tx->cookie == -EBUSY) {
                 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
                         pr_err("%s timeout waiting for descriptor submission\n",
-                               __func__);
+                                __func__);
                         return DMA_ERROR;
                 }
                 cpu_relax();
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
deleted file mode 100644
index 17f983a4e9b..00000000000
--- a/drivers/dma/dmaengine.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * The contents of this file are private to DMA engine drivers, and is not
- * part of the API to be used by DMA engine users.
- */
-#ifndef DMAENGINE_H
-#define DMAENGINE_H
-
-#include <linux/bug.h>
-#include <linux/dmaengine.h>
-
-/**
- * dma_cookie_init - initialize the cookies for a DMA channel
- * @chan: dma channel to initialize
- */
-static inline void dma_cookie_init(struct dma_chan *chan)
-{
-        chan->cookie = DMA_MIN_COOKIE;
-        chan->completed_cookie = DMA_MIN_COOKIE;
-}
-
-/**
- * dma_cookie_assign - assign a DMA engine cookie to the descriptor
- * @tx: descriptor needing cookie
- *
- * Assign a unique non-zero per-channel cookie to the descriptor.
- * Note: caller is expected to hold a lock to prevent concurrency.
- */
-static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
-{
-        struct dma_chan *chan = tx->chan;
-        dma_cookie_t cookie;
-
-        cookie = chan->cookie + 1;
-        if (cookie < DMA_MIN_COOKIE)
-                cookie = DMA_MIN_COOKIE;
-        tx->cookie = chan->cookie = cookie;
-
-        return cookie;
-}
-
-/**
- * dma_cookie_complete - complete a descriptor
- * @tx: descriptor to complete
- *
- * Mark this descriptor complete by updating the channels completed
- * cookie marker.  Zero the descriptors cookie to prevent accidental
- * repeated completions.
- *
- * Note: caller is expected to hold a lock to prevent concurrency.
- */
-static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
-{
-        BUG_ON(tx->cookie < DMA_MIN_COOKIE);
-        tx->chan->completed_cookie = tx->cookie;
-        tx->cookie = 0;
-}
-
-/**
- * dma_cookie_status - report cookie status
- * @chan: dma channel
- * @cookie: cookie we are interested in
- * @state: dma_tx_state structure to return last/used cookies
- *
- * Report the status of the cookie, filling in the state structure if
- * non-NULL.  No locking is required.
- */
-static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
-        dma_cookie_t cookie, struct dma_tx_state *state)
-{
-        dma_cookie_t used, complete;
-
-        used = chan->cookie;
-        complete = chan->completed_cookie;
-        barrier();
-        if (state) {
-                state->last = complete;
-                state->used = used;
-                state->residue = 0;
-        }
-        return dma_async_is_complete(cookie, complete, used);
-}
-
-static inline void dma_set_residue(struct dma_tx_state *state, u32 residue)
-{
-        if (state)
-                state->residue = residue;
-}
-
-#endif
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index 64b048d7fba..765f5ff2230 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -10,7 +10,6 @@
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
-#include <linux/freezer.h>
 #include <linux/init.h>
 #include <linux/kthread.h>
 #include <linux/module.h>
@@ -214,32 +213,9 @@ static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
         return error_count;
 }
 
-/* poor man's completion - we want to use wait_event_freezable() on it */
-struct dmatest_done {
-        bool                    done;
-        wait_queue_head_t       *wait;
-};
-
-static void dmatest_callback(void *arg)
-{
-        struct dmatest_done *done = arg;
-
-        done->done = true;
-        wake_up_all(done->wait);
-}
-
-static inline void unmap_src(struct device *dev, dma_addr_t *addr, size_t len,
-                             unsigned int count)
-{
-        while (count--)
-                dma_unmap_single(dev, addr[count], len, DMA_TO_DEVICE);
-}
-
-static inline void unmap_dst(struct device *dev, dma_addr_t *addr, size_t len,
-                             unsigned int count)
+static void dmatest_callback(void *completion)
 {
-        while (count--)
-                dma_unmap_single(dev, addr[count], len, DMA_BIDIRECTIONAL);
+        complete(completion);
 }
 
 /*
@@ -258,9 +234,7 @@ static inline void unmap_dst(struct device *dev, dma_addr_t *addr, size_t len,
  */
 static int dmatest_func(void *data)
 {
-        DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
         struct dmatest_thread   *thread = data;
-        struct dmatest_done     done = { .wait = &done_wait };
         struct dma_chan         *chan;
         const char              *thread_name;
         unsigned int            src_off, dst_off, len;
@@ -277,7 +251,6 @@ static int dmatest_func(void *data)
         int                     i;
 
         thread_name = current->comm;
-        set_freezable();
 
         ret = -ENOMEM;
 
@@ -331,6 +304,8 @@ static int dmatest_func(void *data)
                 struct dma_async_tx_descriptor *tx = NULL;
                 dma_addr_t dma_srcs[src_cnt];
                 dma_addr_t dma_dsts[dst_cnt];
+                struct completion cmp;
+                unsigned long tmo = msecs_to_jiffies(timeout);
                 u8 align = 0;
 
                 total_tests++;
@@ -367,35 +342,15 @@ static int dmatest_func(void *data)
 
                         dma_srcs[i] = dma_map_single(dev->dev, buf, len,
                                                      DMA_TO_DEVICE);
-                        ret = dma_mapping_error(dev->dev, dma_srcs[i]);
-                        if (ret) {
-                                unmap_src(dev->dev, dma_srcs, len, i);
-                                pr_warn("%s: #%u: mapping error %d with "
-                                        "src_off=0x%x len=0x%x\n",
-                                        thread_name, total_tests - 1, ret,
-                                        src_off, len);
-                                failed_tests++;
-                                continue;
-                        }
                 }
                 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
                 for (i = 0; i < dst_cnt; i++) {
                         dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
                                                      test_buf_size,
                                                      DMA_BIDIRECTIONAL);
-                        ret = dma_mapping_error(dev->dev, dma_dsts[i]);
-                        if (ret) {
-                                unmap_src(dev->dev, dma_srcs, len, src_cnt);
-                                unmap_dst(dev->dev, dma_dsts, test_buf_size, i);
-                                pr_warn("%s: #%u: mapping error %d with "
-                                        "dst_off=0x%x len=0x%x\n",
-                                        thread_name, total_tests - 1, ret,
-                                        dst_off, test_buf_size);
-                                failed_tests++;
-                                continue;
-                        }
                 }
 
+
                 if (thread->type == DMA_MEMCPY)
                         tx = dev->device_prep_dma_memcpy(chan,
                                                          dma_dsts[0] + dst_off,
@@ -417,8 +372,13 @@ static int dmatest_func(void *data)
                 }
 
                 if (!tx) {
-                        unmap_src(dev->dev, dma_srcs, len, src_cnt);
-                        unmap_dst(dev->dev, dma_dsts, test_buf_size, dst_cnt);
+                        for (i = 0; i < src_cnt; i++)
+                                dma_unmap_single(dev->dev, dma_srcs[i], len,
+                                                 DMA_TO_DEVICE);
+                        for (i = 0; i < dst_cnt; i++)
+                                dma_unmap_single(dev->dev, dma_dsts[i],
+                                                 test_buf_size,
+                                                 DMA_BIDIRECTIONAL);
                         pr_warning("%s: #%u: prep error with src_off=0x%x "
                                         "dst_off=0x%x len=0x%x\n",
                                         thread_name, total_tests - 1,
@@ -428,9 +388,9 @@ static int dmatest_func(void *data)
                         continue;
                 }
 
-                done.done = false;
+                init_completion(&cmp);
                 tx->callback = dmatest_callback;
-                tx->callback_param = &done;
+                tx->callback_param = &cmp;
                 cookie = tx->tx_submit(tx);
 
                 if (dma_submit_error(cookie)) {
@@ -444,20 +404,10 @@ static int dmatest_func(void *data)
                 }
                 dma_async_issue_pending(chan);
 
-                wait_event_freezable_timeout(done_wait, done.done,
-                                             msecs_to_jiffies(timeout));
-
+                tmo = wait_for_completion_timeout(&cmp, tmo);
                 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
 
-                if (!done.done) {
-                        /*
-                         * We're leaving the timed out dma operation with
-                         * dangling pointer to done_wait.  To make this
-                         * correct, we'll need to allocate wait_done for
-                         * each test iteration and perform "who's gonna
-                         * free it this time?" dancing.  For now, just
-                         * leave it dangling.
-                         */
+                if (tmo == 0) {
                         pr_warning("%s: #%u: test timed out\n",
                                    thread_name, total_tests - 1);
                         failed_tests++;
@@ -472,7 +422,9 @@ static int dmatest_func(void *data)
                 }
 
                 /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
-                unmap_dst(dev->dev, dma_dsts, test_buf_size, dst_cnt);
+                for (i = 0; i < dst_cnt; i++)
+                        dma_unmap_single(dev->dev, dma_dsts[i], test_buf_size,
+                                         DMA_BIDIRECTIONAL);
 
                 error_count = 0;
 
@@ -525,8 +477,6 @@ err_srcs:
         pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
                         thread_name, total_tests, failed_tests, ret);
 
-        /* terminate all transfers on specified channels */
-        chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
         if (iterations > 0)
                 while (!kthread_should_stop()) {
                         DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit);
@@ -549,10 +499,6 @@ static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
                 list_del(&thread->node);
                 kfree(thread);
         }
-
-        /* terminate all transfers on specified channels */
-        dtc->chan->device->device_control(dtc->chan, DMA_TERMINATE_ALL, 0);
-
         kfree(dtc);
 }
 
@@ -626,7 +572,7 @@ static int dmatest_add_channel(struct dma_chan *chan)
         }
         if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
                 cnt = dmatest_add_threads(dtc, DMA_PQ);
-                thread_count += cnt > 0 ? cnt : 0;
+                thread_count += cnt > 0 ?: 0;
         }
 
         pr_info("dmatest: Started %u threads using %s\n",
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 3e8ba02ba29..4d180ca9a1d 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -9,7 +9,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/dmaengine.h>
@@ -17,14 +16,12 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <linux/of.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
 #include "dw_dmac_regs.h"
-#include "dmaengine.h"
 
 /*
  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
@@ -36,36 +33,32 @@
  * which does not support descriptor writeback.
  */
 
-static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
-{
-        return slave ? slave->dst_master : 0;
-}
-
-static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
-{
-        return slave ? slave->src_master : 1;
-}
-
-#define DWC_DEFAULT_CTLLO(_chan) ({                             \
-                struct dw_dma_slave *__slave = (_chan->private);        \
-                struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
-                struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
-                int _dms = dwc_get_dms(__slave);                \
-                int _sms = dwc_get_sms(__slave);                \
-                u8 _smsize = __slave ? _sconfig->src_maxburst : \
-                        DW_DMA_MSIZE_16;                        \
-                u8 _dmsize = __slave ? _sconfig->dst_maxburst : \
-                        DW_DMA_MSIZE_16;                        \
+#define DWC_DEFAULT_CTLLO(private) ({                           \
+                struct dw_dma_slave *__slave = (private);       \
+                int dms = __slave ? __slave->dst_master : 0;    \
+                int sms = __slave ? __slave->src_master : 1;    \
+                u8 smsize = __slave ? __slave->src_msize : DW_DMA_MSIZE_16; \
+                u8 dmsize = __slave ? __slave->dst_msize : DW_DMA_MSIZE_16; \
                                                                 \
-                (DWC_CTLL_DST_MSIZE(_dmsize)                    \
-                 | DWC_CTLL_SRC_MSIZE(_smsize)                  \
+                (DWC_CTLL_DST_MSIZE(dmsize)                     \
+                 | DWC_CTLL_SRC_MSIZE(smsize)                   \
                  | DWC_CTLL_LLP_D_EN                            \
                  | DWC_CTLL_LLP_S_EN                            \
-                 | DWC_CTLL_DMS(_dms)                           \
-                 | DWC_CTLL_SMS(_sms));                         \
+                 | DWC_CTLL_DMS(dms)                            \
+                 | DWC_CTLL_SMS(sms));                          \
         })
 
 /*
+ * This is configuration-dependent and usually a funny size like 4095.
+ *
+ * Note that this is a transfer count, i.e. if we transfer 32-bit
+ * words, we can do 16380 bytes per descriptor.
+ *
+ * This parameter is also system-specific.
+ */
+#define DWC_MAX_COUNT   4095U
+
+/*
  * Number of descriptors to allocate for each channel. This should be
  * made configurable somehow; preferably, the clients (at least the
  * ones using slave transfers) should be able to give us a hint.
@@ -105,13 +98,13 @@ static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
 
         spin_lock_irqsave(&dwc->lock, flags);
         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
-                i++;
                 if (async_tx_test_ack(&desc->txd)) {
                         list_del(&desc->desc_node);
                         ret = desc;
                         break;
                 }
                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
+                i++;
         }
         spin_unlock_irqrestore(&dwc->lock, flags);
 
@@ -158,136 +151,44 @@ static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
         }
 }
 
-static void dwc_initialize(struct dw_dma_chan *dwc)
-{
-        struct dw_dma *dw = to_dw_dma(dwc->chan.device);
-        struct dw_dma_slave *dws = dwc->chan.private;
-        u32 cfghi = DWC_CFGH_FIFO_MODE;
-        u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
-
-        if (dwc->initialized == true)
-                return;
-
-        if (dws) {
-                /*
-                 * We need controller-specific data to set up slave
-                 * transfers.
-                 */
-                BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
-
-                cfghi = dws->cfg_hi;
-                cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
-        } else {
-                if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
-                        cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
-                else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
-                        cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
-        }
-
-        channel_writel(dwc, CFG_LO, cfglo);
-        channel_writel(dwc, CFG_HI, cfghi);
-
-        /* Enable interrupts */
-        channel_set_bit(dw, MASK.XFER, dwc->mask);
-        channel_set_bit(dw, MASK.ERROR, dwc->mask);
-
-        dwc->initialized = true;
-}
-
-/*----------------------------------------------------------------------*/
-
-static inline unsigned int dwc_fast_fls(unsigned long long v)
+/* Called with dwc->lock held and bh disabled */
+static dma_cookie_t
+dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc)
 {
-        /*
-         * We can be a lot more clever here, but this should take care
-         * of the most common optimization.
-         */
-        if (!(v & 7))
-                return 3;
-        else if (!(v & 3))
-                return 2;
-        else if (!(v & 1))
-                return 1;
-        return 0;
-}
+        dma_cookie_t cookie = dwc->chan.cookie;
 
-static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
-{
-        dev_err(chan2dev(&dwc->chan),
-                "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
-                channel_readl(dwc, SAR),
-                channel_readl(dwc, DAR),
-                channel_readl(dwc, LLP),
-                channel_readl(dwc, CTL_HI),
-                channel_readl(dwc, CTL_LO));
-}
+        if (++cookie < 0)
+                cookie = 1;
 
+        dwc->chan.cookie = cookie;
+        desc->txd.cookie = cookie;
 
-static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
-{
-        channel_clear_bit(dw, CH_EN, dwc->mask);
-        while (dma_readl(dw, CH_EN) & dwc->mask)
-                cpu_relax();
+        return cookie;
 }
 
 /*----------------------------------------------------------------------*/
 
-/* Perform single block transfer */
-static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
-                                       struct dw_desc *desc)
-{
-        struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
-        u32             ctllo;
-
-        /* Software emulation of LLP mode relies on interrupts to continue
-         * multi block transfer. */
-        ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
-
-        channel_writel(dwc, SAR, desc->lli.sar);
-        channel_writel(dwc, DAR, desc->lli.dar);
-        channel_writel(dwc, CTL_LO, ctllo);
-        channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
-        channel_set_bit(dw, CH_EN, dwc->mask);
-}
-
 /* Called with dwc->lock held and bh disabled */
 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 {
         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
-        unsigned long   was_soft_llp;
 
         /* ASSERT:  channel is idle */
         if (dma_readl(dw, CH_EN) & dwc->mask) {
                 dev_err(chan2dev(&dwc->chan),
                         "BUG: Attempted to start non-idle channel\n");
-                dwc_dump_chan_regs(dwc);
+                dev_err(chan2dev(&dwc->chan),
+                        "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
+                        channel_readl(dwc, SAR),
+                        channel_readl(dwc, DAR),
+                        channel_readl(dwc, LLP),
+                        channel_readl(dwc, CTL_HI),
+                        channel_readl(dwc, CTL_LO));
 
                 /* The tasklet will hopefully advance the queue... */
                 return;
         }
 
-        if (dwc->nollp) {
-                was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
-                                                &dwc->flags);
-                if (was_soft_llp) {
-                        dev_err(chan2dev(&dwc->chan),
-                                "BUG: Attempted to start new LLP transfer "
-                                "inside ongoing one\n");
-                        return;
-                }
-
-                dwc_initialize(dwc);
-
-                dwc->tx_list = &first->tx_list;
-                dwc->tx_node_active = first->tx_list.next;
-
-                dwc_do_single_block(dwc, first);
-
-                return;
-        }
-
-        dwc_initialize(dwc);
-
         channel_writel(dwc, LLP, first->txd.phys);
         channel_writel(dwc, CTL_LO,
                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
@@ -310,7 +211,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 
         spin_lock_irqsave(&dwc->lock, flags);
-        dma_cookie_complete(txd);
+        dwc->completed = txd->cookie;
         if (callback_required) {
                 callback = txd->callback;
                 param = txd->callback_param;
@@ -364,7 +265,9 @@ static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
                         "BUG: XFER bit set, but channel not idle!\n");
 
                 /* Try to continue after resetting the channel... */
-                dwc_chan_disable(dw, dwc);
+                channel_clear_bit(dw, CH_EN, dwc->mask);
+                while (dma_readl(dw, CH_EN) & dwc->mask)
+                        cpu_relax();
         }
 
         /*
@@ -392,6 +295,12 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
         unsigned long flags;
 
         spin_lock_irqsave(&dwc->lock, flags);
+        /*
+         * Clear block interrupt flag before scanning so that we don't
+         * miss any, and read LLP before RAW_XFER to ensure it is
+         * valid if we decide to scan the list.
+         */
+        dma_writel(dw, CLEAR.BLOCK, dwc->mask);
         llp = channel_readl(dwc, LLP);
         status_xfer = dma_readl(dw, RAW.XFER);
 
@@ -409,8 +318,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
                 return;
         }
 
-        dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
-                        (unsigned long long)llp);
+        dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp);
 
         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
                 /* check first descriptors addr */
@@ -446,7 +354,9 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
                 "BUG: All descriptors done, but channel not idle!\n");
 
         /* Try to continue after resetting the channel... */
-        dwc_chan_disable(dw, dwc);
+        channel_clear_bit(dw, CH_EN, dwc->mask);
+        while (dma_readl(dw, CH_EN) & dwc->mask)
+                cpu_relax();
 
         if (!list_empty(&dwc->queue)) {
                 list_move(dwc->queue.next, &dwc->active_list);
@@ -455,11 +365,12 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
         spin_unlock_irqrestore(&dwc->lock, flags);
 }
 
-static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
+static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 {
         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
                         "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
-                        lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
+                        lli->sar, lli->dar, lli->llp,
+                        lli->ctlhi, lli->ctllo);
 }
 
 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
@@ -525,16 +436,17 @@ EXPORT_SYMBOL(dw_dma_get_dst_addr);
 
 /* called with dwc->lock held and all DMAC interrupts disabled */
 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
-                u32 status_err, u32 status_xfer)
+                u32 status_block, u32 status_err, u32 status_xfer)
 {
         unsigned long flags;
 
-        if (dwc->mask) {
+        if (status_block & dwc->mask) {
                 void (*callback)(void *param);
                 void *callback_param;
 
                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
                                 channel_readl(dwc, LLP));
+                dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 
                 callback = dwc->cdesc->period_callback;
                 callback_param = dwc->cdesc->period_callback_param;
@@ -557,15 +469,24 @@ static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 
                 spin_lock_irqsave(&dwc->lock, flags);
 
-                dwc_dump_chan_regs(dwc);
+                dev_err(chan2dev(&dwc->chan),
+                        "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
+                        channel_readl(dwc, SAR),
+                        channel_readl(dwc, DAR),
+                        channel_readl(dwc, LLP),
+                        channel_readl(dwc, CTL_HI),
+                        channel_readl(dwc, CTL_LO));
 
-                dwc_chan_disable(dw, dwc);
+                channel_clear_bit(dw, CH_EN, dwc->mask);
+                while (dma_readl(dw, CH_EN) & dwc->mask)
+                        cpu_relax();
 
                 /* make sure DMA does not restart by loading a new list */
                 channel_writel(dwc, LLP, 0);
                 channel_writel(dwc, CTL_LO, 0);
                 channel_writel(dwc, CTL_HI, 0);
 
+                dma_writel(dw, CLEAR.BLOCK, dwc->mask);
                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 
@@ -582,57 +503,36 @@ static void dw_dma_tasklet(unsigned long data)
 {
         struct dw_dma *dw = (struct dw_dma *)data;
         struct dw_dma_chan *dwc;
+        u32 status_block;
         u32 status_xfer;
         u32 status_err;
         int i;
 
+        status_block = dma_readl(dw, RAW.BLOCK);
         status_xfer = dma_readl(dw, RAW.XFER);
         status_err = dma_readl(dw, RAW.ERROR);
 
-        dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
+        dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n",
+                        status_block, status_err);
 
         for (i = 0; i < dw->dma.chancnt; i++) {
                 dwc = &dw->chan[i];
                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
-                        dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
+                        dwc_handle_cyclic(dw, dwc, status_block, status_err,
+                                        status_xfer);
                 else if (status_err & (1 << i))
                         dwc_handle_error(dw, dwc);
-                else if (status_xfer & (1 << i)) {
-                        unsigned long flags;
-
-                        spin_lock_irqsave(&dwc->lock, flags);
-                        if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
-                                if (dwc->tx_node_active != dwc->tx_list) {
-                                        struct dw_desc *desc =
-                                                list_entry(dwc->tx_node_active,
-                                                           struct dw_desc,
-                                                           desc_node);
-
-                                        dma_writel(dw, CLEAR.XFER, dwc->mask);
-
-                                        /* move pointer to next descriptor */
-                                        dwc->tx_node_active =
-                                                dwc->tx_node_active->next;
-
-                                        dwc_do_single_block(dwc, desc);
-
-                                        spin_unlock_irqrestore(&dwc->lock, flags);
-                                        continue;
-                                } else {
-                                        /* we are done here */
-                                        clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
-                                }
-                        }
-                        spin_unlock_irqrestore(&dwc->lock, flags);
-
+                else if ((status_block | status_xfer) & (1 << i))
                         dwc_scan_descriptors(dw, dwc);
-                }
         }
 
         /*
-         * Re-enable interrupts.
+         * Re-enable interrupts. Block Complete interrupts are only
+         * enabled if the INT_EN bit in the descriptor is set. This
+         * will trigger a scan before the whole list is done.
          */
         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
+        channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 }
 
@@ -641,7 +541,7 @@ static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
         struct dw_dma *dw = dev_id;
         u32 status;
 
-        dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
+        dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n",
                         dma_readl(dw, STATUS_INT));
 
         /*
@@ -649,6 +549,7 @@ static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
          * softirq handler.
          */
         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
+        channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 
         status = dma_readl(dw, STATUS_INT);
@@ -659,6 +560,7 @@ static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 
                 /* Try to recover */
                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
+                channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
@@ -679,7 +581,7 @@ static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
         unsigned long           flags;
 
         spin_lock_irqsave(&dwc->lock, flags);
-        cookie = dma_cookie_assign(tx);
+        cookie = dwc_assign_cookie(dwc, desc);
 
         /*
          * REVISIT: We should attempt to chain as many descriptors as
@@ -687,12 +589,12 @@ static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
          * for DMA. But this is hard to do in a race-free manner.
          */
         if (list_empty(&dwc->active_list)) {
-                dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
+                dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
                                 desc->txd.cookie);
                 list_add_tail(&desc->desc_node, &dwc->active_list);
                 dwc_dostart(dwc, dwc_first_active(dwc));
         } else {
-                dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
+                dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
                                 desc->txd.cookie);
 
                 list_add_tail(&desc->desc_node, &dwc->queue);
@@ -708,7 +610,6 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
                 size_t len, unsigned long flags)
 {
         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
-        struct dw_dma_slave     *dws = chan->private;
         struct dw_desc          *desc;
         struct dw_desc          *first;
         struct dw_desc          *prev;
@@ -716,26 +617,30 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
         size_t                  offset;
         unsigned int            src_width;
         unsigned int            dst_width;
-        unsigned int            data_width;
         u32                     ctllo;
 
-        dev_vdbg(chan2dev(chan),
-                        "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
-                        (unsigned long long)dest, (unsigned long long)src,
-                        len, flags);
+        dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n",
+                        dest, src, len, flags);
 
         if (unlikely(!len)) {
-                dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
+                dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
                 return NULL;
         }
 
-        data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)],
-                                         dwc->dw->data_width[dwc_get_dms(dws)]);
-
-        src_width = dst_width = min_t(unsigned int, data_width,
-                                      dwc_fast_fls(src | dest | len));
+        /*
+         * We can be a lot more clever here, but this should take care
+         * of the most common optimization.
+         */
+        if (!((src | dest  | len) & 7))
+                src_width = dst_width = 3;
+        else if (!((src | dest  | len) & 3))
+                src_width = dst_width = 2;
+        else if (!((src | dest | len) & 1))
+                src_width = dst_width = 1;
+        else
+                src_width = dst_width = 0;
 
-        ctllo = DWC_DEFAULT_CTLLO(chan)
+        ctllo = DWC_DEFAULT_CTLLO(chan->private)
                         | DWC_CTLL_DST_WIDTH(dst_width)
                         | DWC_CTLL_SRC_WIDTH(src_width)
                         | DWC_CTLL_DST_INC
@@ -745,7 +650,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 
         for (offset = 0; offset < len; offset += xfer_count << src_width) {
                 xfer_count = min_t(size_t, (len - offset) >> src_width,
-                                           dwc->block_size);
+                                DWC_MAX_COUNT);
 
                 desc = dwc_desc_get(dwc);
                 if (!desc)
@@ -791,53 +696,46 @@ err_desc_get:
 
 static struct dma_async_tx_descriptor *
 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-                unsigned int sg_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags)
 {
         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
         struct dw_dma_slave     *dws = chan->private;
-        struct dma_slave_config *sconfig = &dwc->dma_sconfig;
         struct dw_desc          *prev;
         struct dw_desc          *first;
         u32                     ctllo;
         dma_addr_t              reg;
         unsigned int            reg_width;
         unsigned int            mem_width;
-        unsigned int            data_width;
         unsigned int            i;
         struct scatterlist      *sg;
         size_t                  total_len = 0;
 
-        dev_vdbg(chan2dev(chan), "%s\n", __func__);
+        dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
 
         if (unlikely(!dws || !sg_len))
                 return NULL;
 
+        reg_width = dws->reg_width;
         prev = first = NULL;
 
         switch (direction) {
-        case DMA_MEM_TO_DEV:
-                reg_width = __fls(sconfig->dst_addr_width);
-                reg = sconfig->dst_addr;
-                ctllo = (DWC_DEFAULT_CTLLO(chan)
+        case DMA_TO_DEVICE:
+                ctllo = (DWC_DEFAULT_CTLLO(chan->private)
                                 | DWC_CTLL_DST_WIDTH(reg_width)
                                 | DWC_CTLL_DST_FIX
-                                | DWC_CTLL_SRC_INC);
-
-                ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
-                        DWC_CTLL_FC(DW_DMA_FC_D_M2P);
-
-                data_width = dwc->dw->data_width[dwc_get_sms(dws)];
-
+                                | DWC_CTLL_SRC_INC
+                                | DWC_CTLL_FC(dws->fc));
+                reg = dws->tx_reg;
                 for_each_sg(sgl, sg, sg_len, i) {
                         struct dw_desc  *desc;
                         u32             len, dlen, mem;
 
-                        mem = sg_dma_address(sg);
+                        mem = sg_phys(sg);
                         len = sg_dma_len(sg);
-
-                        mem_width = min_t(unsigned int,
-                                          data_width, dwc_fast_fls(mem | len));
+                        mem_width = 2;
+                        if (unlikely(mem & 3 || len & 3))
+                                mem_width = 0;
 
 slave_sg_todev_fill_desc:
                         desc = dwc_desc_get(dwc);
@@ -850,8 +748,8 @@ slave_sg_todev_fill_desc:
                         desc->lli.sar = mem;
                         desc->lli.dar = reg;
                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
-                        if ((len >> mem_width) > dwc->block_size) {
-                                dlen = dwc->block_size << mem_width;
+                        if ((len >> mem_width) > DWC_MAX_COUNT) {
+                                dlen = DWC_MAX_COUNT << mem_width;
                                 mem += dlen;
                                 len -= dlen;
                         } else {
@@ -879,28 +777,23 @@ slave_sg_todev_fill_desc:
                                 goto slave_sg_todev_fill_desc;
                 }
                 break;
-        case DMA_DEV_TO_MEM:
-                reg_width = __fls(sconfig->src_addr_width);
-                reg = sconfig->src_addr;
-                ctllo = (DWC_DEFAULT_CTLLO(chan)
+        case DMA_FROM_DEVICE:
+                ctllo = (DWC_DEFAULT_CTLLO(chan->private)
                                 | DWC_CTLL_SRC_WIDTH(reg_width)
                                 | DWC_CTLL_DST_INC
-                                | DWC_CTLL_SRC_FIX);
-
-                ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
-                        DWC_CTLL_FC(DW_DMA_FC_D_P2M);
-
-                data_width = dwc->dw->data_width[dwc_get_dms(dws)];
+                                | DWC_CTLL_SRC_FIX
+                                | DWC_CTLL_FC(dws->fc));
 
+                reg = dws->rx_reg;
                 for_each_sg(sgl, sg, sg_len, i) {
                         struct dw_desc  *desc;
                         u32             len, dlen, mem;
 
-                        mem = sg_dma_address(sg);
+                        mem = sg_phys(sg);
                         len = sg_dma_len(sg);
-
-                        mem_width = min_t(unsigned int,
-                                          data_width, dwc_fast_fls(mem | len));
+                        mem_width = 2;
+                        if (unlikely(mem & 3 || len & 3))
+                                mem_width = 0;
 
 slave_sg_fromdev_fill_desc:
                         desc = dwc_desc_get(dwc);
@@ -913,8 +806,8 @@ slave_sg_fromdev_fill_desc:
                         desc->lli.sar = reg;
                         desc->lli.dar = mem;
                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
-                        if ((len >> reg_width) > dwc->block_size) {
-                                dlen = dwc->block_size << reg_width;
+                        if ((len >> reg_width) > DWC_MAX_COUNT) {
+                                dlen = DWC_MAX_COUNT << reg_width;
                                 mem += dlen;
                                 len -= dlen;
                         } else {
@@ -963,39 +856,6 @@ err_desc_get:
         return NULL;
 }
 
-/*
- * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
- * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
- *
- * NOTE: burst size 2 is not supported by controller.
- *
- * This can be done by finding least significant bit set: n & (n - 1)
- */
-static inline void convert_burst(u32 *maxburst)
-{
-        if (*maxburst > 1)
-                *maxburst = fls(*maxburst) - 2;
-        else
-                *maxburst = 0;
-}
-
-static int
-set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
-{
-        struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
-
-        /* Check if it is chan is configured for slave transfers */
-        if (!chan->private)
-                return -EINVAL;
-
-        memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
-
-        convert_burst(&dwc->dma_sconfig.src_maxburst);
-        convert_burst(&dwc->dma_sconfig.dst_maxburst);
-
-        return 0;
-}
-
 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                        unsigned long arg)
 {
@@ -1030,9 +890,9 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
         } else if (cmd == DMA_TERMINATE_ALL) {
                 spin_lock_irqsave(&dwc->lock, flags);
 
-                clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
-
-                dwc_chan_disable(dw, dwc);
+                channel_clear_bit(dw, CH_EN, dwc->mask);
+                while (dma_readl(dw, CH_EN) & dwc->mask)
+                        cpu_relax();
 
                 dwc->paused = false;
 
@@ -1045,11 +905,8 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                 /* Flush all pending and queued descriptors */
                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
                         dwc_descriptor_complete(dwc, desc, false);
-        } else if (cmd == DMA_SLAVE_CONFIG) {
-                return set_runtime_config(chan, (struct dma_slave_config *)arg);
-        } else {
+        } else
                 return -ENXIO;
-        }
 
         return 0;
 }
@@ -1060,17 +917,28 @@ dwc_tx_status(struct dma_chan *chan,
               struct dma_tx_state *txstate)
 {
         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
-        enum dma_status         ret;
+        dma_cookie_t            last_used;
+        dma_cookie_t            last_complete;
+        int                     ret;
+
+        last_complete = dwc->completed;
+        last_used = chan->cookie;
 
-        ret = dma_cookie_status(chan, cookie, txstate);
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
         if (ret != DMA_SUCCESS) {
                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 
-                ret = dma_cookie_status(chan, cookie, txstate);
+                last_complete = dwc->completed;
+                last_used = chan->cookie;
+
+                ret = dma_async_is_complete(cookie, last_complete, last_used);
         }
 
         if (ret != DMA_SUCCESS)
-                dma_set_residue(txstate, dwc_first_active(dwc)->len);
+                dma_set_tx_state(txstate, last_complete, last_used,
+                                dwc_first_active(dwc)->len);
+        else
+                dma_set_tx_state(txstate, last_complete, last_used, 0);
 
         if (dwc->paused)
                 return DMA_PAUSED;
@@ -1091,10 +959,13 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
         struct dw_dma           *dw = to_dw_dma(chan->device);
         struct dw_desc          *desc;
+        struct dw_dma_slave     *dws;
         int                     i;
+        u32                     cfghi;
+        u32                     cfglo;
         unsigned long           flags;
 
-        dev_vdbg(chan2dev(chan), "%s\n", __func__);
+        dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
 
         /* ASSERT:  channel is idle */
         if (dma_readl(dw, CH_EN) & dwc->mask) {
@@ -1102,7 +973,27 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
                 return -EIO;
         }
 
-        dma_cookie_init(chan);
+        dwc->completed = chan->cookie = 1;
+
+        cfghi = DWC_CFGH_FIFO_MODE;
+        cfglo = 0;
+
+        dws = chan->private;
+        if (dws) {
+                /*
+                 * We need controller-specific data to set up slave
+                 * transfers.
+                 */
+                BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
+
+                cfghi = dws->cfg_hi;
+                cfglo = dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
+        }
+
+        cfglo |= DWC_CFGL_CH_PRIOR(dwc->priority);
+
+        channel_writel(dwc, CFG_LO, cfglo);
+        channel_writel(dwc, CFG_HI, cfghi);
 
         /*
          * NOTE: some controllers may have additional features that we
@@ -1135,9 +1026,15 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
                 i = ++dwc->descs_allocated;
         }
 
+        /* Enable interrupts */
+        channel_set_bit(dw, MASK.XFER, dwc->mask);
+        channel_set_bit(dw, MASK.BLOCK, dwc->mask);
+        channel_set_bit(dw, MASK.ERROR, dwc->mask);
+
         spin_unlock_irqrestore(&dwc->lock, flags);
 
-        dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
+        dev_dbg(chan2dev(chan),
+                "alloc_chan_resources allocated %d descriptors\n", i);
 
         return i;
 }
@@ -1150,7 +1047,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
         unsigned long           flags;
         LIST_HEAD(list);
 
-        dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
+        dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
                         dwc->descs_allocated);
 
         /* ASSERT:  channel is idle */
@@ -1161,10 +1058,10 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
         spin_lock_irqsave(&dwc->lock, flags);
         list_splice_init(&dwc->free_list, &list);
         dwc->descs_allocated = 0;
-        dwc->initialized = false;
 
         /* Disable interrupts */
         channel_clear_bit(dw, MASK.XFER, dwc->mask);
+        channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
 
         spin_unlock_irqrestore(&dwc->lock, flags);
@@ -1176,7 +1073,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
                 kfree(desc);
         }
 
-        dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
+        dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
 }
 
 /* --------------------- Cyclic DMA API extensions -------------------- */
@@ -1205,11 +1102,18 @@ int dw_dma_cyclic_start(struct dma_chan *chan)
         if (dma_readl(dw, CH_EN) & dwc->mask) {
                 dev_err(chan2dev(&dwc->chan),
                         "BUG: Attempted to start non-idle channel\n");
-                dwc_dump_chan_regs(dwc);
+                dev_err(chan2dev(&dwc->chan),
+                        "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
+                        channel_readl(dwc, SAR),
+                        channel_readl(dwc, DAR),
+                        channel_readl(dwc, LLP),
+                        channel_readl(dwc, CTL_HI),
+                        channel_readl(dwc, CTL_LO));
                 spin_unlock_irqrestore(&dwc->lock, flags);
                 return -EBUSY;
         }
 
+        dma_writel(dw, CLEAR.BLOCK, dwc->mask);
         dma_writel(dw, CLEAR.ERROR, dwc->mask);
         dma_writel(dw, CLEAR.XFER, dwc->mask);
 
@@ -1240,7 +1144,9 @@ void dw_dma_cyclic_stop(struct dma_chan *chan)
 
         spin_lock_irqsave(&dwc->lock, flags);
 
-        dwc_chan_disable(dw, dwc);
+        channel_clear_bit(dw, CH_EN, dwc->mask);
+        while (dma_readl(dw, CH_EN) & dwc->mask)
+                cpu_relax();
 
         spin_unlock_irqrestore(&dwc->lock, flags);
 }
@@ -1259,14 +1165,14 @@ EXPORT_SYMBOL(dw_dma_cyclic_stop);
  */
 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
-                enum dma_transfer_direction direction)
+                enum dma_data_direction direction)
 {
         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
-        struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
         struct dw_cyclic_desc           *cdesc;
         struct dw_cyclic_desc           *retval = NULL;
         struct dw_desc                  *desc;
         struct dw_desc                  *last = NULL;
+        struct dw_dma_slave             *dws = chan->private;
         unsigned long                   was_cyclic;
         unsigned int                    reg_width;
         unsigned int                    periods;
@@ -1274,13 +1180,6 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
         unsigned long                   flags;
 
         spin_lock_irqsave(&dwc->lock, flags);
-        if (dwc->nollp) {
-                spin_unlock_irqrestore(&dwc->lock, flags);
-                dev_dbg(chan2dev(&dwc->chan),
-                                "channel doesn't support LLP transfers\n");
-                return ERR_PTR(-EINVAL);
-        }
-
         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
                 spin_unlock_irqrestore(&dwc->lock, flags);
                 dev_dbg(chan2dev(&dwc->chan),
@@ -1297,22 +1196,17 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
         }
 
         retval = ERR_PTR(-EINVAL);
-
-        if (direction == DMA_MEM_TO_DEV)
-                reg_width = __ffs(sconfig->dst_addr_width);
-        else
-                reg_width = __ffs(sconfig->src_addr_width);
-
+        reg_width = dws->reg_width;
         periods = buf_len / period_len;
 
         /* Check for too big/unaligned periods and unaligned DMA buffer. */
-        if (period_len > (dwc->block_size << reg_width))
+        if (period_len > (DWC_MAX_COUNT << reg_width))
                 goto out_err;
         if (unlikely(period_len & ((1 << reg_width) - 1)))
                 goto out_err;
         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
                 goto out_err;
-        if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
+        if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
                 goto out_err;
 
         retval = ERR_PTR(-ENOMEM);
@@ -1334,35 +1228,27 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
                         goto out_err_desc_get;
 
                 switch (direction) {
-                case DMA_MEM_TO_DEV:
-                        desc->lli.dar = sconfig->dst_addr;
+                case DMA_TO_DEVICE:
+                        desc->lli.dar = dws->tx_reg;
                         desc->lli.sar = buf_addr + (period_len * i);
-                        desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
+                        desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
                                         | DWC_CTLL_DST_WIDTH(reg_width)
                                         | DWC_CTLL_SRC_WIDTH(reg_width)
                                         | DWC_CTLL_DST_FIX
                                         | DWC_CTLL_SRC_INC
+                                        | DWC_CTLL_FC(dws->fc)
                                         | DWC_CTLL_INT_EN);
-
-                        desc->lli.ctllo |= sconfig->device_fc ?
-                                DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
-                                DWC_CTLL_FC(DW_DMA_FC_D_M2P);
-
                         break;
-                case DMA_DEV_TO_MEM:
+                case DMA_FROM_DEVICE:
                         desc->lli.dar = buf_addr + (period_len * i);
-                        desc->lli.sar = sconfig->src_addr;
-                        desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
+                        desc->lli.sar = dws->rx_reg;
+                        desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
                                         | DWC_CTLL_SRC_WIDTH(reg_width)
                                         | DWC_CTLL_DST_WIDTH(reg_width)
                                         | DWC_CTLL_DST_INC
                                         | DWC_CTLL_SRC_FIX
+                                        | DWC_CTLL_FC(dws->fc)
                                         | DWC_CTLL_INT_EN);
-
-                        desc->lli.ctllo |= sconfig->device_fc ?
-                                DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
-                                DWC_CTLL_FC(DW_DMA_FC_D_P2M);
-
                         break;
                 default:
                         break;
@@ -1386,9 +1272,9 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
         dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
                         sizeof(last->lli), DMA_TO_DEVICE);
 
-        dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
-                        "period %zu periods %d\n", (unsigned long long)buf_addr,
-                        buf_len, period_len, periods);
+        dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
+                        "period %zu periods %d\n", buf_addr, buf_len,
+                        period_len, periods);
 
         cdesc->periods = periods;
         dwc->cdesc = cdesc;
@@ -1418,15 +1304,18 @@ void dw_dma_cyclic_free(struct dma_chan *chan)
         int                     i;
         unsigned long           flags;
 
-        dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
+        dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
 
         if (!cdesc)
                 return;
 
         spin_lock_irqsave(&dwc->lock, flags);
 
-        dwc_chan_disable(dw, dwc);
+        channel_clear_bit(dw, CH_EN, dwc->mask);
+        while (dma_readl(dw, CH_EN) & dwc->mask)
+                cpu_relax();
 
+        dma_writel(dw, CLEAR.BLOCK, dwc->mask);
         dma_writel(dw, CLEAR.ERROR, dwc->mask);
         dma_writel(dw, CLEAR.XFER, dwc->mask);
 
@@ -1446,38 +1335,29 @@ EXPORT_SYMBOL(dw_dma_cyclic_free);
 
 static void dw_dma_off(struct dw_dma *dw)
 {
-        int i;
-
         dma_writel(dw, CFG, 0);
 
         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
+        channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 
         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
                 cpu_relax();
-
-        for (i = 0; i < dw->dma.chancnt; i++)
-                dw->chan[i].initialized = false;
 }
 
-static int dw_probe(struct platform_device *pdev)
+static int __init dw_probe(struct platform_device *pdev)
 {
         struct dw_dma_platform_data *pdata;
         struct resource         *io;
         struct dw_dma           *dw;
         size_t                  size;
-        void __iomem            *regs;
-        bool                    autocfg;
-        unsigned int            dw_params;
-        unsigned int            nr_channels;
-        unsigned int            max_blk_size = 0;
         int                     irq;
         int                     err;
         int                     i;
 
-        pdata = dev_get_platdata(&pdev->dev);
+        pdata = pdev->dev.platform_data;
         if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
                 return -EINVAL;
 
@@ -1489,69 +1369,50 @@ static int dw_probe(struct platform_device *pdev)
         if (irq < 0)
                 return irq;
 
-        regs = devm_request_and_ioremap(&pdev->dev, io);
-        if (!regs)
-                return -EBUSY;
-
-        dw_params = dma_read_byaddr(regs, DW_PARAMS);
-        autocfg = dw_params >> DW_PARAMS_EN & 0x1;
-
-        if (autocfg)
-                nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
-        else
-                nr_channels = pdata->nr_channels;
-
-        size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
-        dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
+        size = sizeof(struct dw_dma);
+        size += pdata->nr_channels * sizeof(struct dw_dma_chan);
+        dw = kzalloc(size, GFP_KERNEL);
         if (!dw)
                 return -ENOMEM;
 
-        dw->clk = devm_clk_get(&pdev->dev, "hclk");
-        if (IS_ERR(dw->clk))
-                return PTR_ERR(dw->clk);
-        clk_prepare_enable(dw->clk);
-
-        dw->regs = regs;
-
-        /* get hardware configuration parameters */
-        if (autocfg) {
-                max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
+        if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) {
+                err = -EBUSY;
+                goto err_kfree;
+        }
 
-                dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
-                for (i = 0; i < dw->nr_masters; i++) {
-                        dw->data_width[i] =
-                                (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
-                }
-        } else {
-                dw->nr_masters = pdata->nr_masters;
-                memcpy(dw->data_width, pdata->data_width, 4);
+        dw->regs = ioremap(io->start, DW_REGLEN);
+        if (!dw->regs) {
+                err = -ENOMEM;
+                goto err_release_r;
         }
 
-        /* Calculate all channel mask before DMA setup */
-        dw->all_chan_mask = (1 << nr_channels) - 1;
+        dw->clk = clk_get(&pdev->dev, "hclk");
+        if (IS_ERR(dw->clk)) {
+                err = PTR_ERR(dw->clk);
+                goto err_clk;
+        }
+        clk_enable(dw->clk);
 
         /* force dma off, just in case */
         dw_dma_off(dw);
 
-        /* disable BLOCK interrupts as well */
-        channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
-
-        err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
-                               "dw_dmac", dw);
+        err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw);
         if (err)
-                return err;
+                goto err_irq;
 
         platform_set_drvdata(pdev, dw);
 
         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
 
+        dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
+
         INIT_LIST_HEAD(&dw->dma.channels);
-        for (i = 0; i < nr_channels; i++) {
+        for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) {
                 struct dw_dma_chan      *dwc = &dw->chan[i];
-                int                     r = nr_channels - i - 1;
 
                 dwc->chan.device = &dw->dma;
-                dma_cookie_init(&dwc->chan);
+                dwc->chan.cookie = dwc->completed = 1;
+                dwc->chan.chan_id = i;
                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
                         list_add_tail(&dwc->chan.device_node,
                                         &dw->dma.channels);
@@ -1560,7 +1421,7 @@ static int dw_probe(struct platform_device *pdev)
 
                 /* 7 is highest priority & 0 is lowest. */
                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
-                        dwc->priority = r;
+                        dwc->priority = 7 - i;
                 else
                         dwc->priority = i;
 
@@ -1573,41 +1434,21 @@ static int dw_probe(struct platform_device *pdev)
                 INIT_LIST_HEAD(&dwc->free_list);
 
                 channel_clear_bit(dw, CH_EN, dwc->mask);
-
-                dwc->dw = dw;
-
-                /* hardware configuration */
-                if (autocfg) {
-                        unsigned int dwc_params;
-
-                        dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
-                                                     DWC_PARAMS);
-
-                        /* Decode maximum block size for given channel. The
-                         * stored 4 bit value represents blocks from 0x00 for 3
-                         * up to 0x0a for 4095. */
-                        dwc->block_size =
-                                (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
-                        dwc->nollp =
-                                (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
-                } else {
-                        dwc->block_size = pdata->block_size;
-
-                        /* Check if channel supports multi block transfer */
-                        channel_writel(dwc, LLP, 0xfffffffc);
-                        dwc->nollp =
-                                (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
-                        channel_writel(dwc, LLP, 0);
-                }
         }
 
-        /* Clear all interrupts on all channels. */
+        /* Clear/disable all interrupts on all channels. */
         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
 
+        channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
+        channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
+        channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
+        channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
+        channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
+
         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
         if (pdata->is_private)
@@ -1627,21 +1468,35 @@ static int dw_probe(struct platform_device *pdev)
         dma_writel(dw, CFG, DW_CFG_DMA_EN);
 
         printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n",
-                        dev_name(&pdev->dev), nr_channels);
+                        dev_name(&pdev->dev), dw->dma.chancnt);
 
         dma_async_device_register(&dw->dma);
 
         return 0;
+
+err_irq:
+        clk_disable(dw->clk);
+        clk_put(dw->clk);
+err_clk:
+        iounmap(dw->regs);
+        dw->regs = NULL;
+err_release_r:
+        release_resource(io);
+err_kfree:
+        kfree(dw);
+        return err;
 }
 
-static int dw_remove(struct platform_device *pdev)
+static int __exit dw_remove(struct platform_device *pdev)
 {
         struct dw_dma           *dw = platform_get_drvdata(pdev);
         struct dw_dma_chan      *dwc, *_dwc;
+        struct resource         *io;
 
         dw_dma_off(dw);
         dma_async_device_unregister(&dw->dma);
 
+        free_irq(platform_get_irq(pdev, 0), dw);
         tasklet_kill(&dw->tasklet);
 
         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
@@ -1650,6 +1505,17 @@ static int dw_remove(struct platform_device *pdev)
                 channel_clear_bit(dw, CH_EN, dwc->mask);
         }
 
+        clk_disable(dw->clk);
+        clk_put(dw->clk);
+
+        iounmap(dw->regs);
+        dw->regs = NULL;
+
+        io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(io->start, DW_REGLEN);
+
+        kfree(dw);
+
         return 0;
 }
 
@@ -1658,7 +1524,7 @@ static void dw_shutdown(struct platform_device *pdev)
         struct dw_dma   *dw = platform_get_drvdata(pdev);
 
         dw_dma_off(platform_get_drvdata(pdev));
-        clk_disable_unprepare(dw->clk);
+        clk_disable(dw->clk);
 }
 
 static int dw_suspend_noirq(struct device *dev)
@@ -1667,8 +1533,7 @@ static int dw_suspend_noirq(struct device *dev)
         struct dw_dma   *dw = platform_get_drvdata(pdev);
 
         dw_dma_off(platform_get_drvdata(pdev));
-        clk_disable_unprepare(dw->clk);
-
+        clk_disable(dw->clk);
         return 0;
 }
 
@@ -1677,7 +1542,7 @@ static int dw_resume_noirq(struct device *dev)
         struct platform_device *pdev = to_platform_device(dev);
         struct dw_dma   *dw = platform_get_drvdata(pdev);
 
-        clk_prepare_enable(dw->clk);
+        clk_enable(dw->clk);
         dma_writel(dw, CFG, DW_CFG_DMA_EN);
         return 0;
 }
@@ -1685,27 +1550,14 @@ static int dw_resume_noirq(struct device *dev)
 static const struct dev_pm_ops dw_dev_pm_ops = {
         .suspend_noirq = dw_suspend_noirq,
         .resume_noirq = dw_resume_noirq,
-        .freeze_noirq = dw_suspend_noirq,
-        .thaw_noirq = dw_resume_noirq,
-        .restore_noirq = dw_resume_noirq,
-        .poweroff_noirq = dw_suspend_noirq,
-};
-
-#ifdef CONFIG_OF
-static const struct of_device_id dw_dma_id_table[] = {
-        { .compatible = "snps,dma-spear1340" },
-        {}
 };
-MODULE_DEVICE_TABLE(of, dw_dma_id_table);
-#endif
 
 static struct platform_driver dw_driver = {
-        .remove         = dw_remove,
+        .remove         = __exit_p(dw_remove),
         .shutdown       = dw_shutdown,
         .driver = {
                 .name   = "dw_dmac",
                 .pm     = &dw_dev_pm_ops,
-                .of_match_table = of_match_ptr(dw_dma_id_table),
         },
 };
 
@@ -1724,4 +1576,4 @@ module_exit(dw_exit);
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
-MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index 88965597b7d..c3419518d70 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -13,18 +13,6 @@
 
 #define DW_DMA_MAX_NR_CHANNELS  8
 
-/* flow controller */
-enum dw_dma_fc {
-        DW_DMA_FC_D_M2M,
-        DW_DMA_FC_D_M2P,
-        DW_DMA_FC_D_P2M,
-        DW_DMA_FC_D_P2P,
-        DW_DMA_FC_P_P2M,
-        DW_DMA_FC_SP_P2P,
-        DW_DMA_FC_P_M2P,
-        DW_DMA_FC_DP_P2P,
-};
-
 /*
  * Redefine this macro to handle differences between 32- and 64-bit
  * addressing, big vs. little endian, etc.
@@ -82,47 +70,9 @@ struct dw_dma_regs {
         DW_REG(ID);
         DW_REG(TEST);
 
-        /* reserved */
-        DW_REG(__reserved0);
-        DW_REG(__reserved1);
-
-        /* optional encoded params, 0x3c8..0x3f7 */
-        u32     __reserved;
-
-        /* per-channel configuration registers */
-        u32     DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
-        u32     MULTI_BLK_TYPE;
-        u32     MAX_BLK_SIZE;
-
-        /* top-level parameters */
-        u32     DW_PARAMS;
+        /* optional encoded params, 0x3c8..0x3 */
 };
 
-#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
-#define dma_readl_native ioread32be
-#define dma_writel_native iowrite32be
-#else
-#define dma_readl_native readl
-#define dma_writel_native writel
-#endif
-
-/* To access the registers in early stage of probe */
-#define dma_read_byaddr(addr, name) \
-        dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
-
-/* Bitfields in DW_PARAMS */
-#define DW_PARAMS_NR_CHAN       8               /* number of channels */
-#define DW_PARAMS_NR_MASTER     11              /* number of AHB masters */
-#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
-#define DW_PARAMS_DATA_WIDTH1   15              /* master 1 data width */
-#define DW_PARAMS_DATA_WIDTH2   17              /* master 2 data width */
-#define DW_PARAMS_DATA_WIDTH3   19              /* master 3 data width */
-#define DW_PARAMS_DATA_WIDTH4   21              /* master 4 data width */
-#define DW_PARAMS_EN            28              /* encoded parameters */
-
-/* Bitfields in DWC_PARAMS */
-#define DWC_PARAMS_MBLK_EN      11              /* multi block transfer */
-
 /* Bitfields in CTL_LO */
 #define DWC_CTLL_INT_EN         (1 << 0)        /* irqs enabled? */
 #define DWC_CTLL_DST_WIDTH(n)   ((n)<<1)        /* bytes per element */
@@ -178,9 +128,10 @@ struct dw_dma_regs {
 /* Bitfields in CFG */
 #define DW_CFG_DMA_EN           (1 << 0)
 
+#define DW_REGLEN               0x400
+
 enum dw_dmac_flags {
         DW_DMA_IS_CYCLIC = 0,
-        DW_DMA_IS_SOFT_LLP = 1,
 };
 
 struct dw_dma_chan {
@@ -189,32 +140,18 @@ struct dw_dma_chan {
         u8                      mask;
         u8                      priority;
         bool                    paused;
-        bool                    initialized;
-
-        /* software emulation of the LLP transfers */
-        struct list_head        *tx_list;
-        struct list_head        *tx_node_active;
 
         spinlock_t              lock;
 
         /* these other elements are all protected by lock */
         unsigned long           flags;
+        dma_cookie_t            completed;
         struct list_head        active_list;
         struct list_head        queue;
         struct list_head        free_list;
         struct dw_cyclic_desc   *cdesc;
 
         unsigned int            descs_allocated;
-
-        /* hardware configuration */
-        unsigned int            block_size;
-        bool                    nollp;
-
-        /* configuration passed via DMA_SLAVE_CONFIG */
-        struct dma_slave_config dma_sconfig;
-
-        /* backlink to dw_dma */
-        struct dw_dma           *dw;
 };
 
 static inline struct dw_dma_chan_regs __iomem *
@@ -224,9 +161,9 @@ __dwc_regs(struct dw_dma_chan *dwc)
 }
 
 #define channel_readl(dwc, name) \
-        dma_readl_native(&(__dwc_regs(dwc)->name))
+        readl(&(__dwc_regs(dwc)->name))
 #define channel_writel(dwc, name, val) \
-        dma_writel_native((val), &(__dwc_regs(dwc)->name))
+        writel((val), &(__dwc_regs(dwc)->name))
 
 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
 {
@@ -241,10 +178,6 @@ struct dw_dma {
 
         u8                      all_chan_mask;
 
-        /* hardware configuration */
-        unsigned char           nr_masters;
-        unsigned char           data_width[4];
-
         struct dw_dma_chan      chan[0];
 };
 
@@ -254,9 +187,9 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
 }
 
 #define dma_readl(dw, name) \
-        dma_readl_native(&(__dw_regs(dw)->name))
+        readl(&(__dw_regs(dw)->name))
 #define dma_writel(dw, name, val) \
-        dma_writel_native((val), &(__dw_regs(dw)->name))
+        writel((val), &(__dw_regs(dw)->name))
 
 #define channel_set_bit(dw, reg, mask) \
         dma_writel(dw, reg, ((mask) << 8) | (mask))
@@ -271,9 +204,9 @@ static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
 /* LLI == Linked List Item; a.k.a. DMA block descriptor */
 struct dw_lli {
         /* values that are not changed by hardware */
-        u32             sar;
-        u32             dar;
-        u32             llp;            /* chain to next lli */
+        dma_addr_t      sar;
+        dma_addr_t      dar;
+        dma_addr_t      llp;            /* chain to next lli */
         u32             ctllo;
         /* values that may get written back: */
         u32             ctlhi;
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
deleted file mode 100644
index f424298f1ac..00000000000
--- a/drivers/dma/edma.c
+++ /dev/null
@@ -1,671 +0,0 @@
-/*
- * TI EDMA DMA engine driver
- *
- * Copyright 2012 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/dmaengine.h>
-#include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-#include <mach/edma.h>
-
-#include "dmaengine.h"
-#include "virt-dma.h"
-
-/*
- * This will go away when the private EDMA API is folded
- * into this driver and the platform device(s) are
- * instantiated in the arch code. We can only get away
- * with this simplification because DA8XX may not be built
- * in the same kernel image with other DaVinci parts. This
- * avoids having to sprinkle dmaengine driver platform devices
- * and data throughout all the existing board files.
- */
-#ifdef CONFIG_ARCH_DAVINCI_DA8XX
-#define EDMA_CTLRS      2
-#define EDMA_CHANS      32
-#else
-#define EDMA_CTLRS      1
-#define EDMA_CHANS      64
-#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
-
-/* Max of 16 segments per channel to conserve PaRAM slots */
-#define MAX_NR_SG               16
-#define EDMA_MAX_SLOTS          MAX_NR_SG
-#define EDMA_DESCRIPTORS        16
-
-struct edma_desc {
-        struct virt_dma_desc            vdesc;
-        struct list_head                node;
-        int                             absync;
-        int                             pset_nr;
-        struct edmacc_param             pset[0];
-};
-
-struct edma_cc;
-
-struct edma_chan {
-        struct virt_dma_chan            vchan;
-        struct list_head                node;
-        struct edma_desc                *edesc;
-        struct edma_cc                  *ecc;
-        int                             ch_num;
-        bool                            alloced;
-        int                             slot[EDMA_MAX_SLOTS];
-        dma_addr_t                      addr;
-        int                             addr_width;
-        int                             maxburst;
-};
-
-struct edma_cc {
-        int                             ctlr;
-        struct dma_device               dma_slave;
-        struct edma_chan                slave_chans[EDMA_CHANS];
-        int                             num_slave_chans;
-        int                             dummy_slot;
-};
-
-static inline struct edma_cc *to_edma_cc(struct dma_device *d)
-{
-        return container_of(d, struct edma_cc, dma_slave);
-}
-
-static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
-{
-        return container_of(c, struct edma_chan, vchan.chan);
-}
-
-static inline struct edma_desc
-*to_edma_desc(struct dma_async_tx_descriptor *tx)
-{
-        return container_of(tx, struct edma_desc, vdesc.tx);
-}
-
-static void edma_desc_free(struct virt_dma_desc *vdesc)
-{
-        kfree(container_of(vdesc, struct edma_desc, vdesc));
-}
-
-/* Dispatch a queued descriptor to the controller (caller holds lock) */
-static void edma_execute(struct edma_chan *echan)
-{
-        struct virt_dma_desc *vdesc = vchan_next_desc(&echan->vchan);
-        struct edma_desc *edesc;
-        int i;
-
-        if (!vdesc) {
-                echan->edesc = NULL;
-                return;
-        }
-
-        list_del(&vdesc->node);
-
-        echan->edesc = edesc = to_edma_desc(&vdesc->tx);
-
-        /* Write descriptor PaRAM set(s) */
-        for (i = 0; i < edesc->pset_nr; i++) {
-                edma_write_slot(echan->slot[i], &edesc->pset[i]);
-                dev_dbg(echan->vchan.chan.device->dev,
-                        "\n pset[%d]:\n"
-                        "  chnum\t%d\n"
-                        "  slot\t%d\n"
-                        "  opt\t%08x\n"
-                        "  src\t%08x\n"
-                        "  dst\t%08x\n"
-                        "  abcnt\t%08x\n"
-                        "  ccnt\t%08x\n"
-                        "  bidx\t%08x\n"
-                        "  cidx\t%08x\n"
-                        "  lkrld\t%08x\n",
-                        i, echan->ch_num, echan->slot[i],
-                        edesc->pset[i].opt,
-                        edesc->pset[i].src,
-                        edesc->pset[i].dst,
-                        edesc->pset[i].a_b_cnt,
-                        edesc->pset[i].ccnt,
-                        edesc->pset[i].src_dst_bidx,
-                        edesc->pset[i].src_dst_cidx,
-                        edesc->pset[i].link_bcntrld);
-                /* Link to the previous slot if not the last set */
-                if (i != (edesc->pset_nr - 1))
-                        edma_link(echan->slot[i], echan->slot[i+1]);
-                /* Final pset links to the dummy pset */
-                else
-                        edma_link(echan->slot[i], echan->ecc->dummy_slot);
-        }
-
-        edma_start(echan->ch_num);
-}
-
-static int edma_terminate_all(struct edma_chan *echan)
-{
-        unsigned long flags;
-        LIST_HEAD(head);
-
-        spin_lock_irqsave(&echan->vchan.lock, flags);
-
-        /*
-         * Stop DMA activity: we assume the callback will not be called
-         * after edma_dma() returns (even if it does, it will see
-         * echan->edesc is NULL and exit.)
-         */
-        if (echan->edesc) {
-                echan->edesc = NULL;
-                edma_stop(echan->ch_num);
-        }
-
-        vchan_get_all_descriptors(&echan->vchan, &head);
-        spin_unlock_irqrestore(&echan->vchan.lock, flags);
-        vchan_dma_desc_free_list(&echan->vchan, &head);
-
-        return 0;
-}
-
-
-static int edma_slave_config(struct edma_chan *echan,
-        struct dma_slave_config *config)
-{
-        if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
-            (config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
-                return -EINVAL;
-
-        if (config->direction == DMA_MEM_TO_DEV) {
-                if (config->dst_addr)
-                        echan->addr = config->dst_addr;
-                if (config->dst_addr_width)
-                        echan->addr_width = config->dst_addr_width;
-                if (config->dst_maxburst)
-                        echan->maxburst = config->dst_maxburst;
-        } else if (config->direction == DMA_DEV_TO_MEM) {
-                if (config->src_addr)
-                        echan->addr = config->src_addr;
-                if (config->src_addr_width)
-                        echan->addr_width = config->src_addr_width;
-                if (config->src_maxburst)
-                        echan->maxburst = config->src_maxburst;
-        }
-
-        return 0;
-}
-
-static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-                        unsigned long arg)
-{
-        int ret = 0;
-        struct dma_slave_config *config;
-        struct edma_chan *echan = to_edma_chan(chan);
-
-        switch (cmd) {
-        case DMA_TERMINATE_ALL:
-                edma_terminate_all(echan);
-                break;
-        case DMA_SLAVE_CONFIG:
-                config = (struct dma_slave_config *)arg;
-                ret = edma_slave_config(echan, config);
-                break;
-        default:
-                ret = -ENOSYS;
-        }
-
-        return ret;
-}
-
-static struct dma_async_tx_descriptor *edma_prep_slave_sg(
-        struct dma_chan *chan, struct scatterlist *sgl,
-        unsigned int sg_len, enum dma_transfer_direction direction,
-        unsigned long tx_flags, void *context)
-{
-        struct edma_chan *echan = to_edma_chan(chan);
-        struct device *dev = chan->device->dev;
-        struct edma_desc *edesc;
-        struct scatterlist *sg;
-        int i;
-        int acnt, bcnt, ccnt, src, dst, cidx;
-        int src_bidx, dst_bidx, src_cidx, dst_cidx;
-
-        if (unlikely(!echan || !sgl || !sg_len))
-                return NULL;
-
-        if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
-                dev_err(dev, "Undefined slave buswidth\n");
-                return NULL;
-        }
-
-        if (sg_len > MAX_NR_SG) {
-                dev_err(dev, "Exceeded max SG segments %d > %d\n",
-                        sg_len, MAX_NR_SG);
-                return NULL;
-        }
-
-        edesc = kzalloc(sizeof(*edesc) + sg_len *
-                sizeof(edesc->pset[0]), GFP_ATOMIC);
-        if (!edesc) {
-                dev_dbg(dev, "Failed to allocate a descriptor\n");
-                return NULL;
-        }
-
-        edesc->pset_nr = sg_len;
-
-        for_each_sg(sgl, sg, sg_len, i) {
-                /* Allocate a PaRAM slot, if needed */
-                if (echan->slot[i] < 0) {
-                        echan->slot[i] =
-                                edma_alloc_slot(EDMA_CTLR(echan->ch_num),
-                                                EDMA_SLOT_ANY);
-                        if (echan->slot[i] < 0) {
-                                dev_err(dev, "Failed to allocate slot\n");
-                                return NULL;
-                        }
-                }
-
-                acnt = echan->addr_width;
-
-                /*
-                 * If the maxburst is equal to the fifo width, use
-                 * A-synced transfers. This allows for large contiguous
-                 * buffer transfers using only one PaRAM set.
-                 */
-                if (echan->maxburst == 1) {
-                        edesc->absync = false;
-                        ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
-                        bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
-                        if (bcnt)
-                                ccnt++;
-                        else
-                                bcnt = SZ_64K - 1;
-                        cidx = acnt;
-                /*
-                 * If maxburst is greater than the fifo address_width,
-                 * use AB-synced transfers where A count is the fifo
-                 * address_width and B count is the maxburst. In this
-                 * case, we are limited to transfers of C count frames
-                 * of (address_width * maxburst) where C count is limited
-                 * to SZ_64K-1. This places an upper bound on the length
-                 * of an SG segment that can be handled.
-                 */
-                } else {
-                        edesc->absync = true;
-                        bcnt = echan->maxburst;
-                        ccnt = sg_dma_len(sg) / (acnt * bcnt);
-                        if (ccnt > (SZ_64K - 1)) {
-                                dev_err(dev, "Exceeded max SG segment size\n");
-                                return NULL;
-                        }
-                        cidx = acnt * bcnt;
-                }
-
-                if (direction == DMA_MEM_TO_DEV) {
-                        src = sg_dma_address(sg);
-                        dst = echan->addr;
-                        src_bidx = acnt;
-                        src_cidx = cidx;
-                        dst_bidx = 0;
-                        dst_cidx = 0;
-                } else {
-                        src = echan->addr;
-                        dst = sg_dma_address(sg);
-                        src_bidx = 0;
-                        src_cidx = 0;
-                        dst_bidx = acnt;
-                        dst_cidx = cidx;
-                }
-
-                edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
-                /* Configure A or AB synchronized transfers */
-                if (edesc->absync)
-                        edesc->pset[i].opt |= SYNCDIM;
-                /* If this is the last set, enable completion interrupt flag */
-                if (i == sg_len - 1)
-                        edesc->pset[i].opt |= TCINTEN;
-
-                edesc->pset[i].src = src;
-                edesc->pset[i].dst = dst;
-
-                edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
-                edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
-
-                edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
-                edesc->pset[i].ccnt = ccnt;
-                edesc->pset[i].link_bcntrld = 0xffffffff;
-
-        }
-
-        return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
-}
-
-static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
-{
-        struct edma_chan *echan = data;
-        struct device *dev = echan->vchan.chan.device->dev;
-        struct edma_desc *edesc;
-        unsigned long flags;
-
-        /* Stop the channel */
-        edma_stop(echan->ch_num);
-
-        switch (ch_status) {
-        case DMA_COMPLETE:
-                dev_dbg(dev, "transfer complete on channel %d\n", ch_num);
-
-                spin_lock_irqsave(&echan->vchan.lock, flags);
-
-                edesc = echan->edesc;
-                if (edesc) {
-                        edma_execute(echan);
-                        vchan_cookie_complete(&edesc->vdesc);
-                }
-
-                spin_unlock_irqrestore(&echan->vchan.lock, flags);
-
-                break;
-        case DMA_CC_ERROR:
-                dev_dbg(dev, "transfer error on channel %d\n", ch_num);
-                break;
-        default:
-                break;
-        }
-}
-
-/* Alloc channel resources */
-static int edma_alloc_chan_resources(struct dma_chan *chan)
-{
-        struct edma_chan *echan = to_edma_chan(chan);
-        struct device *dev = chan->device->dev;
-        int ret;
-        int a_ch_num;
-        LIST_HEAD(descs);
-
-        a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
-                                        chan, EVENTQ_DEFAULT);
-
-        if (a_ch_num < 0) {
-                ret = -ENODEV;
-                goto err_no_chan;
-        }
-
-        if (a_ch_num != echan->ch_num) {
-                dev_err(dev, "failed to allocate requested channel %u:%u\n",
-                        EDMA_CTLR(echan->ch_num),
-                        EDMA_CHAN_SLOT(echan->ch_num));
-                ret = -ENODEV;
-                goto err_wrong_chan;
-        }
-
-        echan->alloced = true;
-        echan->slot[0] = echan->ch_num;
-
-        dev_info(dev, "allocated channel for %u:%u\n",
-                 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
-
-        return 0;
-
-err_wrong_chan:
-        edma_free_channel(a_ch_num);
-err_no_chan:
-        return ret;
-}
-
-/* Free channel resources */
-static void edma_free_chan_resources(struct dma_chan *chan)
-{
-        struct edma_chan *echan = to_edma_chan(chan);
-        struct device *dev = chan->device->dev;
-        int i;
-
-        /* Terminate transfers */
-        edma_stop(echan->ch_num);
-
-        vchan_free_chan_resources(&echan->vchan);
-
-        /* Free EDMA PaRAM slots */
-        for (i = 1; i < EDMA_MAX_SLOTS; i++) {
-                if (echan->slot[i] >= 0) {
-                        edma_free_slot(echan->slot[i]);
-                        echan->slot[i] = -1;
-                }
-        }
-
-        /* Free EDMA channel */
-        if (echan->alloced) {
-                edma_free_channel(echan->ch_num);
-                echan->alloced = false;
-        }
-
-        dev_info(dev, "freeing channel for %u\n", echan->ch_num);
-}
-
-/* Send pending descriptor to hardware */
-static void edma_issue_pending(struct dma_chan *chan)
-{
-        struct edma_chan *echan = to_edma_chan(chan);
-        unsigned long flags;
-
-        spin_lock_irqsave(&echan->vchan.lock, flags);
-        if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
-                edma_execute(echan);
-        spin_unlock_irqrestore(&echan->vchan.lock, flags);
-}
-
-static size_t edma_desc_size(struct edma_desc *edesc)
-{
-        int i;
-        size_t size;
-
-        if (edesc->absync)
-                for (size = i = 0; i < edesc->pset_nr; i++)
-                        size += (edesc->pset[i].a_b_cnt & 0xffff) *
-                                (edesc->pset[i].a_b_cnt >> 16) *
-                                 edesc->pset[i].ccnt;
-        else
-                size = (edesc->pset[0].a_b_cnt & 0xffff) *
-                        (edesc->pset[0].a_b_cnt >> 16) +
-                        (edesc->pset[0].a_b_cnt & 0xffff) *
-                        (SZ_64K - 1) * edesc->pset[0].ccnt;
-
-        return size;
-}
-
-/* Check request completion status */
-static enum dma_status edma_tx_status(struct dma_chan *chan,
-                                      dma_cookie_t cookie,
-                                      struct dma_tx_state *txstate)
-{
-        struct edma_chan *echan = to_edma_chan(chan);
-        struct virt_dma_desc *vdesc;
-        enum dma_status ret;
-        unsigned long flags;
-
-        ret = dma_cookie_status(chan, cookie, txstate);
-        if (ret == DMA_SUCCESS || !txstate)
-                return ret;
-
-        spin_lock_irqsave(&echan->vchan.lock, flags);
-        vdesc = vchan_find_desc(&echan->vchan, cookie);
-        if (vdesc) {
-                txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
-        } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
-                struct edma_desc *edesc = echan->edesc;
-                txstate->residue = edma_desc_size(edesc);
-        } else {
-                txstate->residue = 0;
-        }
-        spin_unlock_irqrestore(&echan->vchan.lock, flags);
-
-        return ret;
-}
-
-static void __init edma_chan_init(struct edma_cc *ecc,
-                                  struct dma_device *dma,
-                                  struct edma_chan *echans)
-{
-        int i, j;
-
-        for (i = 0; i < EDMA_CHANS; i++) {
-                struct edma_chan *echan = &echans[i];
-                echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
-                echan->ecc = ecc;
-                echan->vchan.desc_free = edma_desc_free;
-
-                vchan_init(&echan->vchan, dma);
-
-                INIT_LIST_HEAD(&echan->node);
-                for (j = 0; j < EDMA_MAX_SLOTS; j++)
-                        echan->slot[j] = -1;
-        }
-}
-
-static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
-                          struct device *dev)
-{
-        dma->device_prep_slave_sg = edma_prep_slave_sg;
-        dma->device_alloc_chan_resources = edma_alloc_chan_resources;
-        dma->device_free_chan_resources = edma_free_chan_resources;
-        dma->device_issue_pending = edma_issue_pending;
-        dma->device_tx_status = edma_tx_status;
-        dma->device_control = edma_control;
-        dma->dev = dev;
-
-        INIT_LIST_HEAD(&dma->channels);
-}
-
-static int edma_probe(struct platform_device *pdev)
-{
-        struct edma_cc *ecc;
-        int ret;
-
-        ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
-        if (!ecc) {
-                dev_err(&pdev->dev, "Can't allocate controller\n");
-                return -ENOMEM;
-        }
-
-        ecc->ctlr = pdev->id;
-        ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
-        if (ecc->dummy_slot < 0) {
-                dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
-                return -EIO;
-        }
-
-        dma_cap_zero(ecc->dma_slave.cap_mask);
-        dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
-
-        edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
-
-        edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
-
-        ret = dma_async_device_register(&ecc->dma_slave);
-        if (ret)
-                goto err_reg1;
-
-        platform_set_drvdata(pdev, ecc);
-
-        dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
-
-        return 0;
-
-err_reg1:
-        edma_free_slot(ecc->dummy_slot);
-        return ret;
-}
-
-static int edma_remove(struct platform_device *pdev)
-{
-        struct device *dev = &pdev->dev;
-        struct edma_cc *ecc = dev_get_drvdata(dev);
-
-        dma_async_device_unregister(&ecc->dma_slave);
-        edma_free_slot(ecc->dummy_slot);
-
-        return 0;
-}
-
-static struct platform_driver edma_driver = {
-        .probe          = edma_probe,
-        .remove         = edma_remove,
-        .driver = {
-                .name = "edma-dma-engine",
-                .owner = THIS_MODULE,
-        },
-};
-
-bool edma_filter_fn(struct dma_chan *chan, void *param)
-{
-        if (chan->device->dev->driver == &edma_driver.driver) {
-                struct edma_chan *echan = to_edma_chan(chan);
-                unsigned ch_req = *(unsigned *)param;
-                return ch_req == echan->ch_num;
-        }
-        return false;
-}
-EXPORT_SYMBOL(edma_filter_fn);
-
-static struct platform_device *pdev0, *pdev1;
-
-static const struct platform_device_info edma_dev_info0 = {
-        .name = "edma-dma-engine",
-        .id = 0,
-        .dma_mask = DMA_BIT_MASK(32),
-};
-
-static const struct platform_device_info edma_dev_info1 = {
-        .name = "edma-dma-engine",
-        .id = 1,
-        .dma_mask = DMA_BIT_MASK(32),
-};
-
-static int edma_init(void)
-{
-        int ret = platform_driver_register(&edma_driver);
-
-        if (ret == 0) {
-                pdev0 = platform_device_register_full(&edma_dev_info0);
-                if (IS_ERR(pdev0)) {
-                        platform_driver_unregister(&edma_driver);
-                        ret = PTR_ERR(pdev0);
-                        goto out;
-                }
-        }
-
-        if (EDMA_CTLRS == 2) {
-                pdev1 = platform_device_register_full(&edma_dev_info1);
-                if (IS_ERR(pdev1)) {
-                        platform_driver_unregister(&edma_driver);
-                        platform_device_unregister(pdev0);
-                        ret = PTR_ERR(pdev1);
-                }
-        }
-
-out:
-        return ret;
-}
-subsys_initcall(edma_init);
-
-static void __exit edma_exit(void)
-{
-        platform_device_unregister(pdev0);
-        if (pdev1)
-                platform_device_unregister(pdev1);
-        platform_driver_unregister(&edma_driver);
-}
-module_exit(edma_exit);
-
-MODULE_AUTHOR("Matt Porter <mporter@ti.com>");
-MODULE_DESCRIPTION("TI EDMA DMA engine driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index bcfde400904..5d7a49bd7c2 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -22,13 +22,10 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/dmaengine.h>
-#include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <linux/platform_data/dma-ep93xx.h>
-
-#include "dmaengine.h"
+#include <mach/dma.h>
 
 /* M2P registers */
 #define M2P_CONTROL                     0x0000
@@ -71,7 +68,6 @@
 #define M2M_CONTROL_TM_SHIFT            13
 #define M2M_CONTROL_TM_TX               (1 << M2M_CONTROL_TM_SHIFT)
 #define M2M_CONTROL_TM_RX               (2 << M2M_CONTROL_TM_SHIFT)
-#define M2M_CONTROL_NFBINT              BIT(21)
 #define M2M_CONTROL_RSS_SHIFT           22
 #define M2M_CONTROL_RSS_SSPRX           (1 << M2M_CONTROL_RSS_SHIFT)
 #define M2M_CONTROL_RSS_SSPTX           (2 << M2M_CONTROL_RSS_SHIFT)
@@ -80,22 +76,7 @@
 #define M2M_CONTROL_PWSC_SHIFT          25
 
 #define M2M_INTERRUPT                   0x0004
-#define M2M_INTERRUPT_MASK              6
-
-#define M2M_STATUS                      0x000c
-#define M2M_STATUS_CTL_SHIFT            1
-#define M2M_STATUS_CTL_IDLE             (0 << M2M_STATUS_CTL_SHIFT)
-#define M2M_STATUS_CTL_STALL            (1 << M2M_STATUS_CTL_SHIFT)
-#define M2M_STATUS_CTL_MEMRD            (2 << M2M_STATUS_CTL_SHIFT)
-#define M2M_STATUS_CTL_MEMWR            (3 << M2M_STATUS_CTL_SHIFT)
-#define M2M_STATUS_CTL_BWCWAIT          (4 << M2M_STATUS_CTL_SHIFT)
-#define M2M_STATUS_CTL_MASK             (7 << M2M_STATUS_CTL_SHIFT)
-#define M2M_STATUS_BUF_SHIFT            4
-#define M2M_STATUS_BUF_NO               (0 << M2M_STATUS_BUF_SHIFT)
-#define M2M_STATUS_BUF_ON               (1 << M2M_STATUS_BUF_SHIFT)
-#define M2M_STATUS_BUF_NEXT             (2 << M2M_STATUS_BUF_SHIFT)
-#define M2M_STATUS_BUF_MASK             (3 << M2M_STATUS_BUF_SHIFT)
-#define M2M_STATUS_DONE                 BIT(6)
+#define M2M_INTERRUPT_DONEINT           BIT(1)
 
 #define M2M_BCR0                        0x0010
 #define M2M_BCR1                        0x0014
@@ -140,6 +121,7 @@ struct ep93xx_dma_desc {
  * @lock: lock protecting the fields following
  * @flags: flags for the channel
  * @buffer: which buffer to use next (0/1)
+ * @last_completed: last completed cookie value
  * @active: flattened chain of descriptors currently being processed
  * @queue: pending descriptors which are handled next
  * @free_list: list of free descriptors which can be used
@@ -174,6 +156,7 @@ struct ep93xx_dma_chan {
 #define EP93XX_DMA_IS_CYCLIC            0
 
         int                             buffer;
+        dma_cookie_t                    last_completed;
         struct list_head                active;
         struct list_head                queue;
         struct list_head                free_list;
@@ -262,9 +245,6 @@ static void ep93xx_dma_set_active(struct ep93xx_dma_chan *edmac,
 static struct ep93xx_dma_desc *
 ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)
 {
-        if (list_empty(&edmac->active))
-                return NULL;
-
         return list_first_entry(&edmac->active, struct ep93xx_dma_desc, node);
 }
 
@@ -282,22 +262,16 @@ ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)
  */
 static bool ep93xx_dma_advance_active(struct ep93xx_dma_chan *edmac)
 {
-        struct ep93xx_dma_desc *desc;
-
         list_rotate_left(&edmac->active);
 
         if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
                 return true;
 
-        desc = ep93xx_dma_get_active(edmac);
-        if (!desc)
-                return false;
-
         /*
          * If txd.cookie is set it means that we are back in the first
          * descriptor in the chain and hence done with it.
          */
-        return !desc->txd.cookie;
+        return !ep93xx_dma_get_active(edmac)->txd.cookie;
 }
 
 /*
@@ -352,16 +326,10 @@ static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)
 
 static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)
 {
-        struct ep93xx_dma_desc *desc;
+        struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
         u32 bus_addr;
 
-        desc = ep93xx_dma_get_active(edmac);
-        if (!desc) {
-                dev_warn(chan2dev(edmac), "M2P: empty descriptor list\n");
-                return;
-        }
-
-        if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_MEM_TO_DEV)
+        if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_TO_DEVICE)
                 bus_addr = desc->src_addr;
         else
                 bus_addr = desc->dst_addr;
@@ -442,6 +410,15 @@ static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac)
 
 /*
  * M2M DMA implementation
+ *
+ * For the M2M transfers we don't use NFB at all. This is because it simply
+ * doesn't work well with memcpy transfers. When you submit both buffers it is
+ * extremely unlikely that you get an NFB interrupt, but it instead reports
+ * DONE interrupt and both buffers are already transferred which means that we
+ * weren't able to update the next buffer.
+ *
+ * So for now we "simulate" NFB by just submitting buffer after buffer
+ * without double buffering.
  */
 
 static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
@@ -465,7 +442,7 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
                 control = (5 << M2M_CONTROL_PWSC_SHIFT);
                 control |= M2M_CONTROL_NO_HDSK;
 
-                if (data->direction == DMA_MEM_TO_DEV) {
+                if (data->direction == DMA_TO_DEVICE) {
                         control |= M2M_CONTROL_DAH;
                         control |= M2M_CONTROL_TM_TX;
                         control |= M2M_CONTROL_RSS_SSPTX;
@@ -481,7 +458,11 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
                  * This IDE part is totally untested. Values below are taken
                  * from the EP93xx Users's Guide and might not be correct.
                  */
-                if (data->direction == DMA_MEM_TO_DEV) {
+                control |= M2M_CONTROL_NO_HDSK;
+                control |= M2M_CONTROL_RSS_IDE;
+                control |= M2M_CONTROL_PW_16;
+
+                if (data->direction == DMA_TO_DEVICE) {
                         /* Worst case from the UG */
                         control = (3 << M2M_CONTROL_PWSC_SHIFT);
                         control |= M2M_CONTROL_DAH;
@@ -491,10 +472,6 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
                         control |= M2M_CONTROL_SAH;
                         control |= M2M_CONTROL_TM_RX;
                 }
-
-                control |= M2M_CONTROL_NO_HDSK;
-                control |= M2M_CONTROL_RSS_IDE;
-                control |= M2M_CONTROL_PW_16;
                 break;
 
         default:
@@ -513,13 +490,7 @@ static void m2m_hw_shutdown(struct ep93xx_dma_chan *edmac)
 
 static void m2m_fill_desc(struct ep93xx_dma_chan *edmac)
 {
-        struct ep93xx_dma_desc *desc;
-
-        desc = ep93xx_dma_get_active(edmac);
-        if (!desc) {
-                dev_warn(chan2dev(edmac), "M2M: empty descriptor list\n");
-                return;
-        }
+        struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
 
         if (edmac->buffer == 0) {
                 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE0);
@@ -550,11 +521,6 @@ static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)
         m2m_fill_desc(edmac);
         control |= M2M_CONTROL_DONEINT;
 
-        if (ep93xx_dma_advance_active(edmac)) {
-                m2m_fill_desc(edmac);
-                control |= M2M_CONTROL_NFBINT;
-        }
-
         /*
          * Now we can finally enable the channel. For M2M channel this must be
          * done _after_ the BCRx registers are programmed.
@@ -572,89 +538,32 @@ static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)
         }
 }
 
-/*
- * According to EP93xx User's Guide, we should receive DONE interrupt when all
- * M2M DMA controller transactions complete normally. This is not always the
- * case - sometimes EP93xx M2M DMA asserts DONE interrupt when the DMA channel
- * is still running (channel Buffer FSM in DMA_BUF_ON state, and channel
- * Control FSM in DMA_MEM_RD state, observed at least in IDE-DMA operation).
- * In effect, disabling the channel when only DONE bit is set could stop
- * currently running DMA transfer. To avoid this, we use Buffer FSM and
- * Control FSM to check current state of DMA channel.
- */
 static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)
 {
-        u32 status = readl(edmac->regs + M2M_STATUS);
-        u32 ctl_fsm = status & M2M_STATUS_CTL_MASK;
-        u32 buf_fsm = status & M2M_STATUS_BUF_MASK;
-        bool done = status & M2M_STATUS_DONE;
-        bool last_done;
         u32 control;
-        struct ep93xx_dma_desc *desc;
 
-        /* Accept only DONE and NFB interrupts */
-        if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_MASK))
+        if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_DONEINT))
                 return INTERRUPT_UNKNOWN;
 
-        if (done) {
-                /* Clear the DONE bit */
-                writel(0, edmac->regs + M2M_INTERRUPT);
-        }
-
-        /*
-         * Check whether we are done with descriptors or not. This, together
-         * with DMA channel state, determines action to take in interrupt.
-         */
-        desc = ep93xx_dma_get_active(edmac);
-        last_done = !desc || desc->txd.cookie;
+        /* Clear the DONE bit */
+        writel(0, edmac->regs + M2M_INTERRUPT);
 
-        /*
-         * Use M2M DMA Buffer FSM and Control FSM to check current state of
-         * DMA channel. Using DONE and NFB bits from channel status register
-         * or bits from channel interrupt register is not reliable.
-         */
-        if (!last_done &&
-            (buf_fsm == M2M_STATUS_BUF_NO ||
-             buf_fsm == M2M_STATUS_BUF_ON)) {
-                /*
-                 * Two buffers are ready for update when Buffer FSM is in
-                 * DMA_NO_BUF state. Only one buffer can be prepared without
-                 * disabling the channel or polling the DONE bit.
-                 * To simplify things, always prepare only one buffer.
-                 */
-                if (ep93xx_dma_advance_active(edmac)) {
-                        m2m_fill_desc(edmac);
-                        if (done && !edmac->chan.private) {
-                                /* Software trigger for memcpy channel */
-                                control = readl(edmac->regs + M2M_CONTROL);
-                                control |= M2M_CONTROL_START;
-                                writel(control, edmac->regs + M2M_CONTROL);
-                        }
-                        return INTERRUPT_NEXT_BUFFER;
-                } else {
-                        last_done = true;
-                }
-        }
+        /* Disable interrupts and the channel */
+        control = readl(edmac->regs + M2M_CONTROL);
+        control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_ENABLE);
+        writel(control, edmac->regs + M2M_CONTROL);
 
         /*
-         * Disable the channel only when Buffer FSM is in DMA_NO_BUF state
-         * and Control FSM is in DMA_STALL state.
+         * Since we only get DONE interrupt we have to find out ourselves
+         * whether there still is something to process. So we try to advance
+         * the chain an see whether it succeeds.
          */
-        if (last_done &&
-            buf_fsm == M2M_STATUS_BUF_NO &&
-            ctl_fsm == M2M_STATUS_CTL_STALL) {
-                /* Disable interrupts and the channel */
-                control = readl(edmac->regs + M2M_CONTROL);
-                control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_NFBINT
-                            | M2M_CONTROL_ENABLE);
-                writel(control, edmac->regs + M2M_CONTROL);
-                return INTERRUPT_DONE;
+        if (ep93xx_dma_advance_active(edmac)) {
+                edmac->edma->hw_submit(edmac);
+                return INTERRUPT_NEXT_BUFFER;
         }
 
-        /*
-         * Nothing to do this time.
-         */
-        return INTERRUPT_NEXT_BUFFER;
+        return INTERRUPT_DONE;
 }
 
 /*
@@ -759,32 +668,24 @@ static void ep93xx_dma_tasklet(unsigned long data)
 {
         struct ep93xx_dma_chan *edmac = (struct ep93xx_dma_chan *)data;
         struct ep93xx_dma_desc *desc, *d;
-        dma_async_tx_callback callback = NULL;
-        void *callback_param = NULL;
+        dma_async_tx_callback callback;
+        void *callback_param;
         LIST_HEAD(list);
 
         spin_lock_irq(&edmac->lock);
-        /*
-         * If dma_terminate_all() was called before we get to run, the active
-         * list has become empty. If that happens we aren't supposed to do
-         * anything more than call ep93xx_dma_advance_work().
-         */
         desc = ep93xx_dma_get_active(edmac);
-        if (desc) {
-                if (desc->complete) {
-                        /* mark descriptor complete for non cyclic case only */
-                        if (!test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
-                                dma_cookie_complete(&desc->txd);
-                        list_splice_init(&edmac->active, &list);
-                }
-                callback = desc->txd.callback;
-                callback_param = desc->txd.callback_param;
+        if (desc->complete) {
+                edmac->last_completed = desc->txd.cookie;
+                list_splice_init(&edmac->active, &list);
         }
         spin_unlock_irq(&edmac->lock);
 
         /* Pick up the next descriptor from the queue */
         ep93xx_dma_advance_work(edmac);
 
+        callback = desc->txd.callback;
+        callback_param = desc->txd.callback_param;
+
         /* Now we can release all the chained descriptors */
         list_for_each_entry_safe(desc, d, &list, node) {
                 /*
@@ -804,22 +705,13 @@ static void ep93xx_dma_tasklet(unsigned long data)
 static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id)
 {
         struct ep93xx_dma_chan *edmac = dev_id;
-        struct ep93xx_dma_desc *desc;
         irqreturn_t ret = IRQ_HANDLED;
 
         spin_lock(&edmac->lock);
 
-        desc = ep93xx_dma_get_active(edmac);
-        if (!desc) {
-                dev_warn(chan2dev(edmac),
-                         "got interrupt while active list is empty\n");
-                spin_unlock(&edmac->lock);
-                return IRQ_NONE;
-        }
-
         switch (edmac->edma->hw_interrupt(edmac)) {
         case INTERRUPT_DONE:
-                desc->complete = true;
+                ep93xx_dma_get_active(edmac)->complete = true;
                 tasklet_schedule(&edmac->tasklet);
                 break;
 
@@ -854,10 +746,17 @@ static dma_cookie_t ep93xx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
         unsigned long flags;
 
         spin_lock_irqsave(&edmac->lock, flags);
-        cookie = dma_cookie_assign(tx);
+
+        cookie = edmac->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
 
         desc = container_of(tx, struct ep93xx_dma_desc, txd);
 
+        edmac->chan.cookie = cookie;
+        desc->txd.cookie = cookie;
+
         /*
          * If nothing is currently prosessed, we push this descriptor
          * directly to the hardware. Otherwise we put the descriptor
@@ -903,8 +802,8 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
                         switch (data->port) {
                         case EP93XX_DMA_SSP:
                         case EP93XX_DMA_IDE:
-                                if (data->direction != DMA_MEM_TO_DEV &&
-                                    data->direction != DMA_DEV_TO_MEM)
+                                if (data->direction != DMA_TO_DEVICE &&
+                                    data->direction != DMA_FROM_DEVICE)
                                         return -EINVAL;
                                 break;
                         default:
@@ -925,7 +824,8 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
                 goto fail_clk_disable;
 
         spin_lock_irq(&edmac->lock);
-        dma_cookie_init(&edmac->chan);
+        edmac->last_completed = 1;
+        edmac->chan.cookie = 1;
         ret = edmac->edma->hw_setup(edmac);
         spin_unlock_irq(&edmac->lock);
 
@@ -1046,14 +946,13 @@ fail:
  * @sg_len: number of entries in @sgl
  * @dir: direction of tha DMA transfer
  * @flags: flags for the descriptor
- * @context: operation context (ignored)
  *
  * Returns a valid DMA descriptor or %NULL in case of failure.
  */
 static struct dma_async_tx_descriptor *
 ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-                         unsigned int sg_len, enum dma_transfer_direction dir,
-                         unsigned long flags, void *context)
+                         unsigned int sg_len, enum dma_data_direction dir,
+                         unsigned long flags)
 {
         struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
         struct ep93xx_dma_desc *desc, *first;
@@ -1088,7 +987,7 @@ ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                         goto fail;
                 }
 
-                if (dir == DMA_MEM_TO_DEV) {
+                if (dir == DMA_TO_DEVICE) {
                         desc->src_addr = sg_dma_address(sg);
                         desc->dst_addr = edmac->runtime_addr;
                 } else {
@@ -1118,10 +1017,8 @@ fail:
  * @chan: channel
  * @dma_addr: DMA mapped address of the buffer
  * @buf_len: length of the buffer (in bytes)
- * @period_len: length of a single period
+ * @period_len: lenght of a single period
  * @dir: direction of the operation
- * @flags: tx descriptor status flags
- * @context: operation context (ignored)
  *
  * Prepares a descriptor for cyclic DMA operation. This means that once the
  * descriptor is submitted, we will be submitting in a @period_len sized
@@ -1134,8 +1031,7 @@ fail:
 static struct dma_async_tx_descriptor *
 ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
                            size_t buf_len, size_t period_len,
-                           enum dma_transfer_direction dir, unsigned long flags,
-                           void *context)
+                           enum dma_data_direction dir)
 {
         struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
         struct ep93xx_dma_desc *desc, *first;
@@ -1168,7 +1064,7 @@ ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
                         goto fail;
                 }
 
-                if (dir == DMA_MEM_TO_DEV) {
+                if (dir == DMA_TO_DEVICE) {
                         desc->src_addr = dma_addr + offset;
                         desc->dst_addr = edmac->runtime_addr;
                 } else {
@@ -1236,12 +1132,12 @@ static int ep93xx_dma_slave_config(struct ep93xx_dma_chan *edmac,
                 return -EINVAL;
 
         switch (config->direction) {
-        case DMA_DEV_TO_MEM:
+        case DMA_FROM_DEVICE:
                 width = config->src_addr_width;
                 addr = config->src_addr;
                 break;
 
-        case DMA_MEM_TO_DEV:
+        case DMA_TO_DEVICE:
                 width = config->dst_addr_width;
                 addr = config->dst_addr;
                 break;
@@ -1315,13 +1211,18 @@ static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
                                             struct dma_tx_state *state)
 {
         struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
+        dma_cookie_t last_used, last_completed;
         enum dma_status ret;
         unsigned long flags;
 
         spin_lock_irqsave(&edmac->lock, flags);
-        ret = dma_cookie_status(chan, cookie, state);
+        last_used = chan->cookie;
+        last_completed = edmac->last_completed;
         spin_unlock_irqrestore(&edmac->lock, flags);
 
+        ret = dma_async_is_complete(cookie, last_completed, last_used);
+        dma_set_tx_state(state, last_completed, last_used, 0);
+
         return ret;
 }
 
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 4fc2980556a..8a781540590 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -35,7 +35,6 @@
 #include <linux/dmapool.h>
 #include <linux/of_platform.h>
 
-#include "dmaengine.h"
 #include "fsldma.h"
 
 #define chan_dbg(chan, fmt, arg...)                                     \
@@ -414,10 +413,17 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
          * assign cookies to all of the software descriptors
          * that make up this transaction
          */
+        cookie = chan->common.cookie;
         list_for_each_entry(child, &desc->tx_list, node) {
-                cookie = dma_cookie_assign(&child->async_tx);
+                cookie++;
+                if (cookie < DMA_MIN_COOKIE)
+                        cookie = DMA_MIN_COOKIE;
+
+                child->async_tx.cookie = cookie;
         }
 
+        chan->common.cookie = cookie;
+
         /* put this transaction onto the tail of the pending queue */
         append_ld_queue(chan, desc);
 
@@ -759,7 +765,6 @@ fail:
  * @sg_len: number of entries in @scatterlist
  * @direction: DMA direction
  * @flags: DMAEngine flags
- * @context: transaction context (ignored)
  *
  * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
  * DMA_SLAVE API, this gets the device-specific information from the
@@ -767,8 +772,7 @@ fail:
  */
 static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
         struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
-        enum dma_transfer_direction direction, unsigned long flags,
-        void *context)
+        enum dma_data_direction direction, unsigned long flags)
 {
         /*
          * This operation is not supported on the Freescale DMA controller
@@ -815,7 +819,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
                         return -ENXIO;
 
                 /* we set the controller burst size depending on direction */
-                if (config->direction == DMA_MEM_TO_DEV)
+                if (config->direction == DMA_TO_DEVICE)
                         size = config->dst_addr_width * config->dst_maxburst;
                 else
                         size = config->src_addr_width * config->src_maxburst;
@@ -980,14 +984,19 @@ static enum dma_status fsl_tx_status(struct dma_chan *dchan,
                                         struct dma_tx_state *txstate)
 {
         struct fsldma_chan *chan = to_fsl_chan(dchan);
-        enum dma_status ret;
+        dma_cookie_t last_complete;
+        dma_cookie_t last_used;
         unsigned long flags;
 
         spin_lock_irqsave(&chan->desc_lock, flags);
-        ret = dma_cookie_status(dchan, cookie, txstate);
+
+        last_complete = chan->completed_cookie;
+        last_used = dchan->cookie;
+
         spin_unlock_irqrestore(&chan->desc_lock, flags);
 
-        return ret;
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+        return dma_async_is_complete(cookie, last_complete, last_used);
 }
 
 /*----------------------------------------------------------------------------*/
@@ -1015,7 +1024,7 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
         /*
          * Programming Error
          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
-         * trigger a PE interrupt.
+         * triger a PE interrupt.
          */
         if (stat & FSL_DMA_SR_PE) {
                 chan_dbg(chan, "irq: Programming Error INT\n");
@@ -1078,8 +1087,8 @@ static void dma_do_tasklet(unsigned long data)
 
                 desc = to_fsl_desc(chan->ld_running.prev);
                 cookie = desc->async_tx.cookie;
-                dma_cookie_complete(&desc->async_tx);
 
+                chan->completed_cookie = cookie;
                 chan_dbg(chan, "completed_cookie=%d\n", cookie);
         }
 
@@ -1221,7 +1230,7 @@ out_unwind:
 /* OpenFirmware Subsystem                                                     */
 /*----------------------------------------------------------------------------*/
 
-static int fsl_dma_chan_probe(struct fsldma_device *fdev,
+static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
         struct device_node *node, u32 feature, const char *compatible)
 {
         struct fsldma_chan *chan;
@@ -1294,7 +1303,6 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev,
         chan->idle = true;
 
         chan->common.device = &fdev->common;
-        dma_cookie_init(&chan->common);
 
         /* find the IRQ line, if it exists in the device tree */
         chan->irq = irq_of_parse_and_map(node, 0);
@@ -1324,7 +1332,7 @@ static void fsl_dma_chan_remove(struct fsldma_chan *chan)
         kfree(chan);
 }
 
-static int fsldma_of_probe(struct platform_device *op)
+static int __devinit fsldma_of_probe(struct platform_device *op)
 {
         struct fsldma_device *fdev;
         struct device_node *child;
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index f5c38791fc7..9cb5aa57c67 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -137,6 +137,7 @@ struct fsldma_device {
 struct fsldma_chan {
         char name[8];                   /* Channel name */
         struct fsldma_chan_regs __iomem *regs;
+        dma_cookie_t completed_cookie;  /* The maximum cookie completed */
         spinlock_t desc_lock;           /* Descriptor operation lock */
         struct list_head ld_pending;    /* Link descriptors queue */
         struct list_head ld_running;    /* Link descriptors queue */
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index dbf0e6f8de8..d99f71c356b 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -5,7 +5,6 @@
  * found on i.MX1/21/27
  *
  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -23,623 +22,73 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
-#include <linux/clk.h>
 #include <linux/dmaengine.h>
-#include <linux/module.h>
 
 #include <asm/irq.h>
-#include <linux/platform_data/dma-imx.h>
-
-#include "dmaengine.h"
-#define IMXDMA_MAX_CHAN_DESCRIPTORS     16
-#define IMX_DMA_CHANNELS  16
-
-#define IMX_DMA_2D_SLOTS        2
-#define IMX_DMA_2D_SLOT_A       0
-#define IMX_DMA_2D_SLOT_B       1
-
-#define IMX_DMA_LENGTH_LOOP     ((unsigned int)-1)
-#define IMX_DMA_MEMSIZE_32      (0 << 4)
-#define IMX_DMA_MEMSIZE_8       (1 << 4)
-#define IMX_DMA_MEMSIZE_16      (2 << 4)
-#define IMX_DMA_TYPE_LINEAR     (0 << 10)
-#define IMX_DMA_TYPE_2D         (1 << 10)
-#define IMX_DMA_TYPE_FIFO       (2 << 10)
-
-#define IMX_DMA_ERR_BURST     (1 << 0)
-#define IMX_DMA_ERR_REQUEST   (1 << 1)
-#define IMX_DMA_ERR_TRANSFER  (1 << 2)
-#define IMX_DMA_ERR_BUFFER    (1 << 3)
-#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
-
-#define DMA_DCR     0x00                /* Control Register */
-#define DMA_DISR    0x04                /* Interrupt status Register */
-#define DMA_DIMR    0x08                /* Interrupt mask Register */
-#define DMA_DBTOSR  0x0c                /* Burst timeout status Register */
-#define DMA_DRTOSR  0x10                /* Request timeout Register */
-#define DMA_DSESR   0x14                /* Transfer Error Status Register */
-#define DMA_DBOSR   0x18                /* Buffer overflow status Register */
-#define DMA_DBTOCR  0x1c                /* Burst timeout control Register */
-#define DMA_WSRA    0x40                /* W-Size Register A */
-#define DMA_XSRA    0x44                /* X-Size Register A */
-#define DMA_YSRA    0x48                /* Y-Size Register A */
-#define DMA_WSRB    0x4c                /* W-Size Register B */
-#define DMA_XSRB    0x50                /* X-Size Register B */
-#define DMA_YSRB    0x54                /* Y-Size Register B */
-#define DMA_SAR(x)  (0x80 + ((x) << 6)) /* Source Address Registers */
-#define DMA_DAR(x)  (0x84 + ((x) << 6)) /* Destination Address Registers */
-#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
-#define DMA_CCR(x)  (0x8c + ((x) << 6)) /* Control Registers */
-#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
-#define DMA_BLR(x)  (0x94 + ((x) << 6)) /* Burst length Registers */
-#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
-#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
-#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
-
-#define DCR_DRST           (1<<1)
-#define DCR_DEN            (1<<0)
-#define DBTOCR_EN          (1<<15)
-#define DBTOCR_CNT(x)      ((x) & 0x7fff)
-#define CNTR_CNT(x)        ((x) & 0xffffff)
-#define CCR_ACRPT          (1<<14)
-#define CCR_DMOD_LINEAR    (0x0 << 12)
-#define CCR_DMOD_2D        (0x1 << 12)
-#define CCR_DMOD_FIFO      (0x2 << 12)
-#define CCR_DMOD_EOBFIFO   (0x3 << 12)
-#define CCR_SMOD_LINEAR    (0x0 << 10)
-#define CCR_SMOD_2D        (0x1 << 10)
-#define CCR_SMOD_FIFO      (0x2 << 10)
-#define CCR_SMOD_EOBFIFO   (0x3 << 10)
-#define CCR_MDIR_DEC       (1<<9)
-#define CCR_MSEL_B         (1<<8)
-#define CCR_DSIZ_32        (0x0 << 6)
-#define CCR_DSIZ_8         (0x1 << 6)
-#define CCR_DSIZ_16        (0x2 << 6)
-#define CCR_SSIZ_32        (0x0 << 4)
-#define CCR_SSIZ_8         (0x1 << 4)
-#define CCR_SSIZ_16        (0x2 << 4)
-#define CCR_REN            (1<<3)
-#define CCR_RPT            (1<<2)
-#define CCR_FRC            (1<<1)
-#define CCR_CEN            (1<<0)
-#define RTOR_EN            (1<<15)
-#define RTOR_CLK           (1<<14)
-#define RTOR_PSC           (1<<13)
-
-enum  imxdma_prep_type {
-        IMXDMA_DESC_MEMCPY,
-        IMXDMA_DESC_INTERLEAVED,
-        IMXDMA_DESC_SLAVE_SG,
-        IMXDMA_DESC_CYCLIC,
-};
-
-struct imx_dma_2d_config {
-        u16             xsr;
-        u16             ysr;
-        u16             wsr;
-        int             count;
-};
-
-struct imxdma_desc {
-        struct list_head                node;
-        struct dma_async_tx_descriptor  desc;
-        enum dma_status                 status;
-        dma_addr_t                      src;
-        dma_addr_t                      dest;
-        size_t                          len;
-        enum dma_transfer_direction     direction;
-        enum imxdma_prep_type           type;
-        /* For memcpy and interleaved */
-        unsigned int                    config_port;
-        unsigned int                    config_mem;
-        /* For interleaved transfers */
-        unsigned int                    x;
-        unsigned int                    y;
-        unsigned int                    w;
-        /* For slave sg and cyclic */
-        struct scatterlist              *sg;
-        unsigned int                    sgcount;
-};
+#include <mach/dma-v1.h>
+#include <mach/hardware.h>
 
 struct imxdma_channel {
-        int                             hw_chaining;
-        struct timer_list               watchdog;
         struct imxdma_engine            *imxdma;
         unsigned int                    channel;
+        unsigned int                    imxdma_channel;
 
-        struct tasklet_struct           dma_tasklet;
-        struct list_head                ld_free;
-        struct list_head                ld_queue;
-        struct list_head                ld_active;
-        int                             descs_allocated;
         enum dma_slave_buswidth         word_size;
         dma_addr_t                      per_address;
         u32                             watermark_level;
         struct dma_chan                 chan;
+        spinlock_t                      lock;
         struct dma_async_tx_descriptor  desc;
+        dma_cookie_t                    last_completed;
         enum dma_status                 status;
         int                             dma_request;
         struct scatterlist              *sg_list;
-        u32                             ccr_from_device;
-        u32                             ccr_to_device;
-        bool                            enabled_2d;
-        int                             slot_2d;
 };
 
-enum imx_dma_type {
-        IMX1_DMA,
-        IMX21_DMA,
-        IMX27_DMA,
-};
+#define MAX_DMA_CHANNELS 8
 
 struct imxdma_engine {
         struct device                   *dev;
         struct device_dma_parameters    dma_parms;
         struct dma_device               dma_device;
-        void __iomem                    *base;
-        struct clk                      *dma_ahb;
-        struct clk                      *dma_ipg;
-        spinlock_t                      lock;
-        struct imx_dma_2d_config        slots_2d[IMX_DMA_2D_SLOTS];
-        struct imxdma_channel           channel[IMX_DMA_CHANNELS];
-        enum imx_dma_type               devtype;
+        struct imxdma_channel           channel[MAX_DMA_CHANNELS];
 };
 
-static struct platform_device_id imx_dma_devtype[] = {
-        {
-                .name = "imx1-dma",
-                .driver_data = IMX1_DMA,
-        }, {
-                .name = "imx21-dma",
-                .driver_data = IMX21_DMA,
-        }, {
-                .name = "imx27-dma",
-                .driver_data = IMX27_DMA,
-        }, {
-                /* sentinel */
-        }
-};
-MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
-
-static inline int is_imx1_dma(struct imxdma_engine *imxdma)
-{
-        return imxdma->devtype == IMX1_DMA;
-}
-
-static inline int is_imx21_dma(struct imxdma_engine *imxdma)
-{
-        return imxdma->devtype == IMX21_DMA;
-}
-
-static inline int is_imx27_dma(struct imxdma_engine *imxdma)
-{
-        return imxdma->devtype == IMX27_DMA;
-}
-
 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
 {
         return container_of(chan, struct imxdma_channel, chan);
 }
 
-static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
-{
-        struct imxdma_desc *desc;
-
-        if (!list_empty(&imxdmac->ld_active)) {
-                desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
-                                        node);
-                if (desc->type == IMXDMA_DESC_CYCLIC)
-                        return true;
-        }
-        return false;
-}
-
-
-
-static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
-                             unsigned offset)
-{
-        __raw_writel(val, imxdma->base + offset);
-}
-
-static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
-{
-        return __raw_readl(imxdma->base + offset);
-}
-
-static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
-{
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-
-        if (is_imx27_dma(imxdma))
-                return imxdmac->hw_chaining;
-        else
-                return 0;
-}
-
-/*
- * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
- */
-static inline int imxdma_sg_next(struct imxdma_desc *d)
-{
-        struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        struct scatterlist *sg = d->sg;
-        unsigned long now;
-
-        now = min(d->len, sg_dma_len(sg));
-        if (d->len != IMX_DMA_LENGTH_LOOP)
-                d->len -= now;
-
-        if (d->direction == DMA_DEV_TO_MEM)
-                imx_dmav1_writel(imxdma, sg->dma_address,
-                                 DMA_DAR(imxdmac->channel));
-        else
-                imx_dmav1_writel(imxdma, sg->dma_address,
-                                 DMA_SAR(imxdmac->channel));
-
-        imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
-
-        dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
-                "size 0x%08x\n", __func__, imxdmac->channel,
-                 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
-                 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
-                 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
-
-        return now;
-}
-
-static void imxdma_enable_hw(struct imxdma_desc *d)
-{
-        struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        int channel = imxdmac->channel;
-        unsigned long flags;
-
-        dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
-
-        local_irq_save(flags);
-
-        imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
-        imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
-                         ~(1 << channel), DMA_DIMR);
-        imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
-                         CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
-
-        if (!is_imx1_dma(imxdma) &&
-                        d->sg && imxdma_hw_chain(imxdmac)) {
-                d->sg = sg_next(d->sg);
-                if (d->sg) {
-                        u32 tmp;
-                        imxdma_sg_next(d);
-                        tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
-                        imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
-                                         DMA_CCR(channel));
-                }
-        }
-
-        local_irq_restore(flags);
-}
-
-static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
+static void imxdma_handle(struct imxdma_channel *imxdmac)
 {
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        int channel = imxdmac->channel;
-        unsigned long flags;
-
-        dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
-
-        if (imxdma_hw_chain(imxdmac))
-                del_timer(&imxdmac->watchdog);
-
-        local_irq_save(flags);
-        imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
-                         (1 << channel), DMA_DIMR);
-        imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
-                         ~CCR_CEN, DMA_CCR(channel));
-        imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
-        local_irq_restore(flags);
+        if (imxdmac->desc.callback)
+                imxdmac->desc.callback(imxdmac->desc.callback_param);
+        imxdmac->last_completed = imxdmac->desc.cookie;
 }
 
-static void imxdma_watchdog(unsigned long data)
+static void imxdma_irq_handler(int channel, void *data)
 {
-        struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        int channel = imxdmac->channel;
-
-        imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
+        struct imxdma_channel *imxdmac = data;
 
-        /* Tasklet watchdog error handler */
-        tasklet_schedule(&imxdmac->dma_tasklet);
-        dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
-                imxdmac->channel);
+        imxdmac->status = DMA_SUCCESS;
+        imxdma_handle(imxdmac);
 }
 
-static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
+static void imxdma_err_handler(int channel, void *data, int error)
 {
-        struct imxdma_engine *imxdma = dev_id;
-        unsigned int err_mask;
-        int i, disr;
-        int errcode;
+        struct imxdma_channel *imxdmac = data;
 
-        disr = imx_dmav1_readl(imxdma, DMA_DISR);
-
-        err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
-                   imx_dmav1_readl(imxdma, DMA_DRTOSR) |
-                   imx_dmav1_readl(imxdma, DMA_DSESR)  |
-                   imx_dmav1_readl(imxdma, DMA_DBOSR);
-
-        if (!err_mask)
-                return IRQ_HANDLED;
-
-        imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
-
-        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-                if (!(err_mask & (1 << i)))
-                        continue;
-                errcode = 0;
-
-                if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
-                        imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
-                        errcode |= IMX_DMA_ERR_BURST;
-                }
-                if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
-                        imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
-                        errcode |= IMX_DMA_ERR_REQUEST;
-                }
-                if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
-                        imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
-                        errcode |= IMX_DMA_ERR_TRANSFER;
-                }
-                if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
-                        imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
-                        errcode |= IMX_DMA_ERR_BUFFER;
-                }
-                /* Tasklet error handler */
-                tasklet_schedule(&imxdma->channel[i].dma_tasklet);
-
-                printk(KERN_WARNING
-                       "DMA timeout on channel %d -%s%s%s%s\n", i,
-                       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
-                       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
-                       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
-                       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
-        }
-        return IRQ_HANDLED;
+        imxdmac->status = DMA_ERROR;
+        imxdma_handle(imxdmac);
 }
 
-static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
+static void imxdma_progression(int channel, void *data,
+                struct scatterlist *sg)
 {
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        int chno = imxdmac->channel;
-        struct imxdma_desc *desc;
-
-        spin_lock(&imxdma->lock);
-        if (list_empty(&imxdmac->ld_active)) {
-                spin_unlock(&imxdma->lock);
-                goto out;
-        }
-
-        desc = list_first_entry(&imxdmac->ld_active,
-                                struct imxdma_desc,
-                                node);
-        spin_unlock(&imxdma->lock);
-
-        if (desc->sg) {
-                u32 tmp;
-                desc->sg = sg_next(desc->sg);
+        struct imxdma_channel *imxdmac = data;
 
-                if (desc->sg) {
-                        imxdma_sg_next(desc);
-
-                        tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
-
-                        if (imxdma_hw_chain(imxdmac)) {
-                                /* FIXME: The timeout should probably be
-                                 * configurable
-                                 */
-                                mod_timer(&imxdmac->watchdog,
-                                        jiffies + msecs_to_jiffies(500));
-
-                                tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-                                imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
-                        } else {
-                                imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
-                                                 DMA_CCR(chno));
-                                tmp |= CCR_CEN;
-                        }
-
-                        imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
-
-                        if (imxdma_chan_is_doing_cyclic(imxdmac))
-                                /* Tasklet progression */
-                                tasklet_schedule(&imxdmac->dma_tasklet);
-
-                        return;
-                }
-
-                if (imxdma_hw_chain(imxdmac)) {
-                        del_timer(&imxdmac->watchdog);
-                        return;
-                }
-        }
-
-out:
-        imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
-        /* Tasklet irq */
-        tasklet_schedule(&imxdmac->dma_tasklet);
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-        struct imxdma_engine *imxdma = dev_id;
-        int i, disr;
-
-        if (!is_imx1_dma(imxdma))
-                imxdma_err_handler(irq, dev_id);
-
-        disr = imx_dmav1_readl(imxdma, DMA_DISR);
-
-        dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
-
-        imx_dmav1_writel(imxdma, disr, DMA_DISR);
-        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-                if (disr & (1 << i))
-                        dma_irq_handle_channel(&imxdma->channel[i]);
-        }
-
-        return IRQ_HANDLED;
-}
-
-static int imxdma_xfer_desc(struct imxdma_desc *d)
-{
-        struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        unsigned long flags;
-        int slot = -1;
-        int i;
-
-        /* Configure and enable */
-        switch (d->type) {
-        case IMXDMA_DESC_INTERLEAVED:
-                /* Try to get a free 2D slot */
-                spin_lock_irqsave(&imxdma->lock, flags);
-                for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
-                        if ((imxdma->slots_2d[i].count > 0) &&
-                        ((imxdma->slots_2d[i].xsr != d->x) ||
-                        (imxdma->slots_2d[i].ysr != d->y) ||
-                        (imxdma->slots_2d[i].wsr != d->w)))
-                                continue;
-                        slot = i;
-                        break;
-                }
-                if (slot < 0) {
-                        spin_unlock_irqrestore(&imxdma->lock, flags);
-                        return -EBUSY;
-                }
-
-                imxdma->slots_2d[slot].xsr = d->x;
-                imxdma->slots_2d[slot].ysr = d->y;
-                imxdma->slots_2d[slot].wsr = d->w;
-                imxdma->slots_2d[slot].count++;
-
-                imxdmac->slot_2d = slot;
-                imxdmac->enabled_2d = true;
-                spin_unlock_irqrestore(&imxdma->lock, flags);
-
-                if (slot == IMX_DMA_2D_SLOT_A) {
-                        d->config_mem &= ~CCR_MSEL_B;
-                        d->config_port &= ~CCR_MSEL_B;
-                        imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
-                        imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
-                        imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
-                } else {
-                        d->config_mem |= CCR_MSEL_B;
-                        d->config_port |= CCR_MSEL_B;
-                        imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
-                        imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
-                        imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
-                }
-                /*
-                 * We fall-through here intentionally, since a 2D transfer is
-                 * similar to MEMCPY just adding the 2D slot configuration.
-                 */
-        case IMXDMA_DESC_MEMCPY:
-                imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
-                imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
-                imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
-                         DMA_CCR(imxdmac->channel));
-
-                imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
-
-                dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
-                        "dma_length=%d\n", __func__, imxdmac->channel,
-                        d->dest, d->src, d->len);
-
-                break;
-        /* Cyclic transfer is the same as slave_sg with special sg configuration. */
-        case IMXDMA_DESC_CYCLIC:
-        case IMXDMA_DESC_SLAVE_SG:
-                if (d->direction == DMA_DEV_TO_MEM) {
-                        imx_dmav1_writel(imxdma, imxdmac->per_address,
-                                         DMA_SAR(imxdmac->channel));
-                        imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
-                                         DMA_CCR(imxdmac->channel));
-
-                        dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
-                                "total length=%d dev_addr=0x%08x (dev2mem)\n",
-                                __func__, imxdmac->channel, d->sg, d->sgcount,
-                                d->len, imxdmac->per_address);
-                } else if (d->direction == DMA_MEM_TO_DEV) {
-                        imx_dmav1_writel(imxdma, imxdmac->per_address,
-                                         DMA_DAR(imxdmac->channel));
-                        imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
-                                         DMA_CCR(imxdmac->channel));
-
-                        dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
-                                "total length=%d dev_addr=0x%08x (mem2dev)\n",
-                                __func__, imxdmac->channel, d->sg, d->sgcount,
-                                d->len, imxdmac->per_address);
-                } else {
-                        dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
-                                __func__, imxdmac->channel);
-                        return -EINVAL;
-                }
-
-                imxdma_sg_next(d);
-
-                break;
-        default:
-                return -EINVAL;
-        }
-        imxdma_enable_hw(d);
-        return 0;
-}
-
-static void imxdma_tasklet(unsigned long data)
-{
-        struct imxdma_channel *imxdmac = (void *)data;
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        struct imxdma_desc *desc;
-
-        spin_lock(&imxdma->lock);
-
-        if (list_empty(&imxdmac->ld_active)) {
-                /* Someone might have called terminate all */
-                goto out;
-        }
-        desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
-
-        if (desc->desc.callback)
-                desc->desc.callback(desc->desc.callback_param);
-
-        /* If we are dealing with a cyclic descriptor, keep it on ld_active
-         * and dont mark the descriptor as complete.
-         * Only in non-cyclic cases it would be marked as complete
-         */
-        if (imxdma_chan_is_doing_cyclic(imxdmac))
-                goto out;
-        else
-                dma_cookie_complete(&desc->desc);
-
-        /* Free 2D slot if it was an interleaved transfer */
-        if (imxdmac->enabled_2d) {
-                imxdma->slots_2d[imxdmac->slot_2d].count--;
-                imxdmac->enabled_2d = false;
-        }
-
-        list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
-
-        if (!list_empty(&imxdmac->ld_queue)) {
-                desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
-                                        node);
-                list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
-                if (imxdma_xfer_desc(desc) < 0)
-                        dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
-                                 __func__, imxdmac->channel);
-        }
-out:
-        spin_unlock(&imxdma->lock);
+        imxdmac->status = DMA_SUCCESS;
+        imxdma_handle(imxdmac);
 }
 
 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
@@ -647,21 +96,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
         struct dma_slave_config *dmaengine_cfg = (void *)arg;
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        unsigned long flags;
+        int ret;
         unsigned int mode = 0;
 
         switch (cmd) {
         case DMA_TERMINATE_ALL:
-                imxdma_disable_hw(imxdmac);
-
-                spin_lock_irqsave(&imxdma->lock, flags);
-                list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
-                list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
-                spin_unlock_irqrestore(&imxdma->lock, flags);
+                imxdmac->status = DMA_ERROR;
+                imx_dma_disable(imxdmac->imxdma_channel);
                 return 0;
         case DMA_SLAVE_CONFIG:
-                if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
+                if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
                         imxdmac->per_address = dmaengine_cfg->src_addr;
                         imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
                         imxdmac->word_size = dmaengine_cfg->src_addr_width;
@@ -683,22 +127,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                         mode = IMX_DMA_MEMSIZE_32;
                         break;
                 }
+                ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+                                mode | IMX_DMA_TYPE_FIFO,
+                                IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
+                                imxdmac->dma_request, 1);
+
+                if (ret)
+                        return ret;
 
-                imxdmac->hw_chaining = 1;
-                if (!imxdma_hw_chain(imxdmac))
-                        return -EINVAL;
-                imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
-                        ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
-                        CCR_REN;
-                imxdmac->ccr_to_device =
-                        (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
-                        ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
-                imx_dmav1_writel(imxdma, imxdmac->dma_request,
-                                 DMA_RSSR(imxdmac->channel));
-
-                /* Set burst length */
-                imx_dmav1_writel(imxdma, imxdmac->watermark_level *
-                                imxdmac->word_size, DMA_BLR(imxdmac->channel));
+                imx_dma_config_burstlen(imxdmac->imxdma_channel,
+                                imxdmac->watermark_level * imxdmac->word_size);
 
                 return 0;
         default:
@@ -712,20 +150,43 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
                                             dma_cookie_t cookie,
                                             struct dma_tx_state *txstate)
 {
-        return dma_cookie_status(chan, cookie, txstate);
+        struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
+        dma_cookie_t last_used;
+        enum dma_status ret;
+
+        last_used = chan->cookie;
+
+        ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
+        dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
+
+        return ret;
+}
+
+static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
+{
+        dma_cookie_t cookie = imxdma->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        imxdma->chan.cookie = cookie;
+        imxdma->desc.cookie = cookie;
+
+        return cookie;
 }
 
 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
         struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
         dma_cookie_t cookie;
-        unsigned long flags;
 
-        spin_lock_irqsave(&imxdma->lock, flags);
-        list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
-        cookie = dma_cookie_assign(tx);
-        spin_unlock_irqrestore(&imxdma->lock, flags);
+        spin_lock_irq(&imxdmac->lock);
+
+        cookie = imxdma_assign_cookie(imxdmac);
+
+        imx_dma_enable(imxdmac->imxdma_channel);
+
+        spin_unlock_irq(&imxdmac->lock);
 
         return cookie;
 }
@@ -735,52 +196,23 @@ static int imxdma_alloc_chan_resources(struct dma_chan *chan)
         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
         struct imx_dma_data *data = chan->private;
 
-        if (data != NULL)
-                imxdmac->dma_request = data->dma_request;
+        imxdmac->dma_request = data->dma_request;
 
-        while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
-                struct imxdma_desc *desc;
+        dma_async_tx_descriptor_init(&imxdmac->desc, chan);
+        imxdmac->desc.tx_submit = imxdma_tx_submit;
+        /* txd.flags will be overwritten in prep funcs */
+        imxdmac->desc.flags = DMA_CTRL_ACK;
 
-                desc = kzalloc(sizeof(*desc), GFP_KERNEL);
-                if (!desc)
-                        break;
-                __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
-                dma_async_tx_descriptor_init(&desc->desc, chan);
-                desc->desc.tx_submit = imxdma_tx_submit;
-                /* txd.flags will be overwritten in prep funcs */
-                desc->desc.flags = DMA_CTRL_ACK;
-                desc->status = DMA_SUCCESS;
-
-                list_add_tail(&desc->node, &imxdmac->ld_free);
-                imxdmac->descs_allocated++;
-        }
-
-        if (!imxdmac->descs_allocated)
-                return -ENOMEM;
+        imxdmac->status = DMA_SUCCESS;
 
-        return imxdmac->descs_allocated;
+        return 0;
 }
 
 static void imxdma_free_chan_resources(struct dma_chan *chan)
 {
         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        struct imxdma_desc *desc, *_desc;
-        unsigned long flags;
-
-        spin_lock_irqsave(&imxdma->lock, flags);
-
-        imxdma_disable_hw(imxdmac);
-        list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
-        list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 
-        spin_unlock_irqrestore(&imxdma->lock, flags);
-
-        list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
-                kfree(desc);
-                imxdmac->descs_allocated--;
-        }
-        INIT_LIST_HEAD(&imxdmac->ld_free);
+        imx_dma_disable(imxdmac->imxdma_channel);
 
         if (imxdmac->sg_list) {
                 kfree(imxdmac->sg_list);
@@ -790,31 +222,35 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
 
 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
                 struct dma_chan *chan, struct scatterlist *sgl,
-                unsigned int sg_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags)
 {
         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
         struct scatterlist *sg;
-        int i, dma_length = 0;
-        struct imxdma_desc *desc;
+        int i, ret, dma_length = 0;
+        unsigned int dmamode;
 
-        if (list_empty(&imxdmac->ld_free) ||
-            imxdma_chan_is_doing_cyclic(imxdmac))
+        if (imxdmac->status == DMA_IN_PROGRESS)
                 return NULL;
 
-        desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
+        imxdmac->status = DMA_IN_PROGRESS;
 
         for_each_sg(sgl, sg, sg_len, i) {
-                dma_length += sg_dma_len(sg);
+                dma_length += sg->length;
         }
 
+        if (direction == DMA_FROM_DEVICE)
+                dmamode = DMA_MODE_READ;
+        else
+                dmamode = DMA_MODE_WRITE;
+
         switch (imxdmac->word_size) {
         case DMA_SLAVE_BUSWIDTH_4_BYTES:
-                if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
+                if (sgl->length & 3 || sgl->dma_address & 3)
                         return NULL;
                 break;
         case DMA_SLAVE_BUSWIDTH_2_BYTES:
-                if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
+                if (sgl->length & 1 || sgl->dma_address & 1)
                         return NULL;
                 break;
         case DMA_SLAVE_BUSWIDTH_1_BYTE:
@@ -823,41 +259,37 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
                 return NULL;
         }
 
-        desc->type = IMXDMA_DESC_SLAVE_SG;
-        desc->sg = sgl;
-        desc->sgcount = sg_len;
-        desc->len = dma_length;
-        desc->direction = direction;
-        if (direction == DMA_DEV_TO_MEM) {
-                desc->src = imxdmac->per_address;
-        } else {
-                desc->dest = imxdmac->per_address;
-        }
-        desc->desc.callback = NULL;
-        desc->desc.callback_param = NULL;
+        ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
+                 dma_length, imxdmac->per_address, dmamode);
+        if (ret)
+                return NULL;
 
-        return &desc->desc;
+        return &imxdmac->desc;
 }
 
 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
-                size_t period_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                size_t period_len, enum dma_data_direction direction)
 {
         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
         struct imxdma_engine *imxdma = imxdmac->imxdma;
-        struct imxdma_desc *desc;
-        int i;
+        int i, ret;
         unsigned int periods = buf_len / period_len;
+        unsigned int dmamode;
 
         dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
                         __func__, imxdmac->channel, buf_len, period_len);
 
-        if (list_empty(&imxdmac->ld_free) ||
-            imxdma_chan_is_doing_cyclic(imxdmac))
+        if (imxdmac->status == DMA_IN_PROGRESS)
                 return NULL;
+        imxdmac->status = DMA_IN_PROGRESS;
 
-        desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
+        ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
+                        imxdma_progression);
+        if (ret) {
+                dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
+                return NULL;
+        }
 
         if (imxdmac->sg_list)
                 kfree(imxdmac->sg_list);
@@ -873,243 +305,72 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
                 imxdmac->sg_list[i].page_link = 0;
                 imxdmac->sg_list[i].offset = 0;
                 imxdmac->sg_list[i].dma_address = dma_addr;
-                sg_dma_len(&imxdmac->sg_list[i]) = period_len;
+                imxdmac->sg_list[i].length = period_len;
                 dma_addr += period_len;
         }
 
         /* close the loop */
         imxdmac->sg_list[periods].offset = 0;
-        sg_dma_len(&imxdmac->sg_list[periods]) = 0;
+        imxdmac->sg_list[periods].length = 0;
         imxdmac->sg_list[periods].page_link =
                 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
 
-        desc->type = IMXDMA_DESC_CYCLIC;
-        desc->sg = imxdmac->sg_list;
-        desc->sgcount = periods;
-        desc->len = IMX_DMA_LENGTH_LOOP;
-        desc->direction = direction;
-        if (direction == DMA_DEV_TO_MEM) {
-                desc->src = imxdmac->per_address;
-        } else {
-                desc->dest = imxdmac->per_address;
-        }
-        desc->desc.callback = NULL;
-        desc->desc.callback_param = NULL;
-
-        return &desc->desc;
-}
-
-static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
-        struct dma_chan *chan, dma_addr_t dest,
-        dma_addr_t src, size_t len, unsigned long flags)
-{
-        struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        struct imxdma_desc *desc;
-
-        dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
-                        __func__, imxdmac->channel, src, dest, len);
-
-        if (list_empty(&imxdmac->ld_free) ||
-            imxdma_chan_is_doing_cyclic(imxdmac))
-                return NULL;
-
-        desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
-
-        desc->type = IMXDMA_DESC_MEMCPY;
-        desc->src = src;
-        desc->dest = dest;
-        desc->len = len;
-        desc->direction = DMA_MEM_TO_MEM;
-        desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
-        desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
-        desc->desc.callback = NULL;
-        desc->desc.callback_param = NULL;
-
-        return &desc->desc;
-}
-
-static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
-        struct dma_chan *chan, struct dma_interleaved_template *xt,
-        unsigned long flags)
-{
-        struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        struct imxdma_desc *desc;
-
-        dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
-                "   src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
-                imxdmac->channel, xt->src_start, xt->dst_start,
-                xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
-                xt->numf, xt->frame_size);
-
-        if (list_empty(&imxdmac->ld_free) ||
-            imxdma_chan_is_doing_cyclic(imxdmac))
-                return NULL;
+        if (direction == DMA_FROM_DEVICE)
+                dmamode = DMA_MODE_READ;
+        else
+                dmamode = DMA_MODE_WRITE;
 
-        if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
+        ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
+                 IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
+        if (ret)
                 return NULL;
 
-        desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
-
-        desc->type = IMXDMA_DESC_INTERLEAVED;
-        desc->src = xt->src_start;
-        desc->dest = xt->dst_start;
-        desc->x = xt->sgl[0].size;
-        desc->y = xt->numf;
-        desc->w = xt->sgl[0].icg + desc->x;
-        desc->len = desc->x * desc->y;
-        desc->direction = DMA_MEM_TO_MEM;
-        desc->config_port = IMX_DMA_MEMSIZE_32;
-        desc->config_mem = IMX_DMA_MEMSIZE_32;
-        if (xt->src_sgl)
-                desc->config_mem |= IMX_DMA_TYPE_2D;
-        if (xt->dst_sgl)
-                desc->config_port |= IMX_DMA_TYPE_2D;
-        desc->desc.callback = NULL;
-        desc->desc.callback_param = NULL;
-
-        return &desc->desc;
+        return &imxdmac->desc;
 }
 
 static void imxdma_issue_pending(struct dma_chan *chan)
 {
-        struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
-        struct imxdma_engine *imxdma = imxdmac->imxdma;
-        struct imxdma_desc *desc;
-        unsigned long flags;
-
-        spin_lock_irqsave(&imxdma->lock, flags);
-        if (list_empty(&imxdmac->ld_active) &&
-            !list_empty(&imxdmac->ld_queue)) {
-                desc = list_first_entry(&imxdmac->ld_queue,
-                                        struct imxdma_desc, node);
-
-                if (imxdma_xfer_desc(desc) < 0) {
-                        dev_warn(imxdma->dev,
-                                 "%s: channel: %d couldn't issue DMA xfer\n",
-                                 __func__, imxdmac->channel);
-                } else {
-                        list_move_tail(imxdmac->ld_queue.next,
-                                       &imxdmac->ld_active);
-                }
-        }
-        spin_unlock_irqrestore(&imxdma->lock, flags);
+        /*
+         * Nothing to do. We only have a single descriptor
+         */
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
-        {
+{
         struct imxdma_engine *imxdma;
-        struct resource *res;
         int ret, i;
-        int irq, irq_err;
 
-        imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
+        imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
         if (!imxdma)
                 return -ENOMEM;
 
-        imxdma->devtype = pdev->id_entry->driver_data;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        imxdma->base = devm_request_and_ioremap(&pdev->dev, res);
-        if (!imxdma->base)
-                return -EADDRNOTAVAIL;
-
-        irq = platform_get_irq(pdev, 0);
-        if (irq < 0)
-                return irq;
-
-        imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
-        if (IS_ERR(imxdma->dma_ipg))
-                return PTR_ERR(imxdma->dma_ipg);
-
-        imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
-        if (IS_ERR(imxdma->dma_ahb))
-                return PTR_ERR(imxdma->dma_ahb);
-
-        clk_prepare_enable(imxdma->dma_ipg);
-        clk_prepare_enable(imxdma->dma_ahb);
-
-        /* reset DMA module */
-        imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
-
-        if (is_imx1_dma(imxdma)) {
-                ret = devm_request_irq(&pdev->dev, irq,
-                                       dma_irq_handler, 0, "DMA", imxdma);
-                if (ret) {
-                        dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
-                        goto err;
-                }
-
-                irq_err = platform_get_irq(pdev, 1);
-                if (irq_err < 0) {
-                        ret = irq_err;
-                        goto err;
-                }
-
-                ret = devm_request_irq(&pdev->dev, irq_err,
-                                       imxdma_err_handler, 0, "DMA", imxdma);
-                if (ret) {
-                        dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
-                        goto err;
-                }
-        }
-
-        /* enable DMA module */
-        imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
-
-        /* clear all interrupts */
-        imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
-
-        /* disable interrupts */
-        imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
         INIT_LIST_HEAD(&imxdma->dma_device.channels);
 
         dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
         dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
-        dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
-        dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
-
-        /* Initialize 2D global parameters */
-        for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
-                imxdma->slots_2d[i].count = 0;
-
-        spin_lock_init(&imxdma->lock);
 
         /* Initialize channel parameters */
-        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+        for (i = 0; i < MAX_DMA_CHANNELS; i++) {
                 struct imxdma_channel *imxdmac = &imxdma->channel[i];
 
-                if (!is_imx1_dma(imxdma)) {
-                        ret = devm_request_irq(&pdev->dev, irq + i,
-                                        dma_irq_handler, 0, "DMA", imxdma);
-                        if (ret) {
-                                dev_warn(imxdma->dev, "Can't register IRQ %d "
-                                         "for DMA channel %d\n",
-                                         irq + i, i);
-                                goto err;
-                        }
-                        init_timer(&imxdmac->watchdog);
-                        imxdmac->watchdog.function = &imxdma_watchdog;
-                        imxdmac->watchdog.data = (unsigned long)imxdmac;
+                imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
+                                DMA_PRIO_MEDIUM);
+                if ((int)imxdmac->channel < 0) {
+                        ret = -ENODEV;
+                        goto err_init;
                 }
 
-                imxdmac->imxdma = imxdma;
+                imx_dma_setup_handlers(imxdmac->imxdma_channel,
+                       imxdma_irq_handler, imxdma_err_handler, imxdmac);
 
-                INIT_LIST_HEAD(&imxdmac->ld_queue);
-                INIT_LIST_HEAD(&imxdmac->ld_free);
-                INIT_LIST_HEAD(&imxdmac->ld_active);
+                imxdmac->imxdma = imxdma;
+                spin_lock_init(&imxdmac->lock);
 
-                tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
-                             (unsigned long)imxdmac);
                 imxdmac->chan.device = &imxdma->dma_device;
-                dma_cookie_init(&imxdmac->chan);
                 imxdmac->channel = i;
 
                 /* Add the channel to the DMAC list */
-                list_add_tail(&imxdmac->chan.device_node,
-                              &imxdma->dma_device.channels);
+                list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
         }
 
         imxdma->dev = &pdev->dev;
@@ -1120,39 +381,46 @@ static int __init imxdma_probe(struct platform_device *pdev)
         imxdma->dma_device.device_tx_status = imxdma_tx_status;
         imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
         imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
-        imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
-        imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
         imxdma->dma_device.device_control = imxdma_control;
         imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
 
         platform_set_drvdata(pdev, imxdma);
 
-        imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
         imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
         dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
 
         ret = dma_async_device_register(&imxdma->dma_device);
         if (ret) {
                 dev_err(&pdev->dev, "unable to register\n");
-                goto err;
+                goto err_init;
         }
 
         return 0;
 
-err:
-        clk_disable_unprepare(imxdma->dma_ipg);
-        clk_disable_unprepare(imxdma->dma_ahb);
+err_init:
+        while (--i >= 0) {
+                struct imxdma_channel *imxdmac = &imxdma->channel[i];
+                imx_dma_free(imxdmac->imxdma_channel);
+        }
+
+        kfree(imxdma);
         return ret;
 }
 
 static int __exit imxdma_remove(struct platform_device *pdev)
 {
         struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
+        int i;
 
         dma_async_device_unregister(&imxdma->dma_device);
 
-        clk_disable_unprepare(imxdma->dma_ipg);
-        clk_disable_unprepare(imxdma->dma_ahb);
+        for (i = 0; i < MAX_DMA_CHANNELS; i++) {
+                struct imxdma_channel *imxdmac = &imxdma->channel[i];
+
+                 imx_dma_free(imxdmac->imxdma_channel);
+        }
+
+        kfree(imxdma);
 
         return 0;
 }
@@ -1161,7 +429,6 @@ static struct platform_driver imxdma_driver = {
         .driver         = {
                 .name   = "imx-dma",
         },
-        .id_table       = imx_dma_devtype,
         .remove         = __exit_p(imxdma_remove),
 };
 
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index f082aa3a918..7bd7e98548c 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -18,13 +18,11 @@
  */
 
 #include <linux/init.h>
-#include <linux/module.h>
 #include <linux/types.h>
-#include <linux/bitops.h>
 #include <linux/mm.h>
 #include <linux/interrupt.h>
 #include <linux/clk.h>
-#include <linux/delay.h>
+#include <linux/wait.h>
 #include <linux/sched.h>
 #include <linux/semaphore.h>
 #include <linux/spinlock.h>
@@ -38,10 +36,9 @@
 #include <linux/of_device.h>
 
 #include <asm/irq.h>
-#include <linux/platform_data/dma-imx-sdma.h>
-#include <linux/platform_data/dma-imx.h>
-
-#include "dmaengine.h"
+#include <mach/sdma.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
 
 /* SDMA registers */
 #define SDMA_H_C0PTR            0x000
@@ -248,7 +245,7 @@ struct sdma_engine;
 struct sdma_channel {
         struct sdma_engine              *sdma;
         unsigned int                    channel;
-        enum dma_transfer_direction             direction;
+        enum dma_data_direction         direction;
         enum sdma_peripheral_type       peripheral_type;
         unsigned int                    event_id0;
         unsigned int                    event_id1;
@@ -261,19 +258,17 @@ struct sdma_channel {
         unsigned int                    pc_from_device, pc_to_device;
         unsigned long                   flags;
         dma_addr_t                      per_address;
-        unsigned long                   event_mask[2];
-        unsigned long                   watermark_level;
+        u32                             event_mask0, event_mask1;
+        u32                             watermark_level;
         u32                             shp_addr, per_addr;
         struct dma_chan                 chan;
         spinlock_t                      lock;
         struct dma_async_tx_descriptor  desc;
+        dma_cookie_t                    last_completed;
         enum dma_status                 status;
-        unsigned int                    chn_count;
-        unsigned int                    chn_real_count;
-        struct tasklet_struct           tasklet;
 };
 
-#define IMX_DMA_SG_LOOP         BIT(0)
+#define IMX_DMA_SG_LOOP         (1 << 0)
 
 #define MAX_DMA_CHANNELS 32
 #define MXC_SDMA_DEFAULT_PRIORITY 1
@@ -322,9 +317,7 @@ struct sdma_engine {
         struct sdma_context_data        *context;
         dma_addr_t                      context_phys;
         struct dma_device               dma_device;
-        struct clk                      *clk_ipg;
-        struct clk                      *clk_ahb;
-        spinlock_t                      channel_0_lock;
+        struct clk                      *clk;
         struct sdma_script_start_addrs  *script_addrs;
 };
 
@@ -348,9 +341,9 @@ static const struct of_device_id sdma_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 
-#define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
-#define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
-#define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
+#define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
+#define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
+#define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 
 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
@@ -365,64 +358,51 @@ static int sdma_config_ownership(struct sdma_channel *sdmac,
 {
         struct sdma_engine *sdma = sdmac->sdma;
         int channel = sdmac->channel;
-        unsigned long evt, mcu, dsp;
+        u32 evt, mcu, dsp;
 
         if (event_override && mcu_override && dsp_override)
                 return -EINVAL;
 
-        evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
-        mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
-        dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
+        evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
+        mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
+        dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
 
         if (dsp_override)
-                __clear_bit(channel, &dsp);
+                dsp &= ~(1 << channel);
         else
-                __set_bit(channel, &dsp);
+                dsp |= (1 << channel);
 
         if (event_override)
-                __clear_bit(channel, &evt);
+                evt &= ~(1 << channel);
         else
-                __set_bit(channel, &evt);
+                evt |= (1 << channel);
 
         if (mcu_override)
-                __clear_bit(channel, &mcu);
+                mcu &= ~(1 << channel);
         else
-                __set_bit(channel, &mcu);
+                mcu |= (1 << channel);
 
-        writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
-        writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
-        writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
+        __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
+        __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
+        __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
 
         return 0;
 }
 
-static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
-{
-        writel(BIT(channel), sdma->regs + SDMA_H_START);
-}
-
 /*
- * sdma_run_channel0 - run a channel and wait till it's done
+ * sdma_run_channel - run a channel and wait till it's done
  */
-static int sdma_run_channel0(struct sdma_engine *sdma)
+static int sdma_run_channel(struct sdma_channel *sdmac)
 {
+        struct sdma_engine *sdma = sdmac->sdma;
+        int channel = sdmac->channel;
         int ret;
-        unsigned long timeout = 500;
 
-        sdma_enable_channel(sdma, 0);
+        init_completion(&sdmac->done);
 
-        while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
-                if (timeout-- <= 0)
-                        break;
-                udelay(1);
-        }
+        __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 
-        if (ret) {
-                /* Clear the interrupt status */
-                writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
-        } else {
-                dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
-        }
+        ret = wait_for_completion_timeout(&sdmac->done, HZ);
 
         return ret ? 0 : -ETIMEDOUT;
 }
@@ -434,16 +414,12 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
         void *buf_virt;
         dma_addr_t buf_phys;
         int ret;
-        unsigned long flags;
 
         buf_virt = dma_alloc_coherent(NULL,
                         size,
                         &buf_phys, GFP_KERNEL);
-        if (!buf_virt) {
+        if (!buf_virt)
                 return -ENOMEM;
-        }
-
-        spin_lock_irqsave(&sdma->channel_0_lock, flags);
 
         bd0->mode.command = C0_SETPM;
         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
@@ -453,9 +429,7 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 
         memcpy(buf_virt, buf, size);
 
-        ret = sdma_run_channel0(sdma);
-
-        spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
+        ret = sdma_run_channel(&sdma->channel[0]);
 
         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 
@@ -466,12 +440,12 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 {
         struct sdma_engine *sdma = sdmac->sdma;
         int channel = sdmac->channel;
-        unsigned long val;
+        u32 val;
         u32 chnenbl = chnenbl_ofs(sdma, event);
 
-        val = readl_relaxed(sdma->regs + chnenbl);
-        __set_bit(channel, &val);
-        writel_relaxed(val, sdma->regs + chnenbl);
+        val = __raw_readl(sdma->regs + chnenbl);
+        val |= (1 << channel);
+        __raw_writel(val, sdma->regs + chnenbl);
 }
 
 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
@@ -479,11 +453,11 @@ static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
         struct sdma_engine *sdma = sdmac->sdma;
         int channel = sdmac->channel;
         u32 chnenbl = chnenbl_ofs(sdma, event);
-        unsigned long val;
+        u32 val;
 
-        val = readl_relaxed(sdma->regs + chnenbl);
-        __clear_bit(channel, &val);
-        writel_relaxed(val, sdma->regs + chnenbl);
+        val = __raw_readl(sdma->regs + chnenbl);
+        val &= ~(1 << channel);
+        __raw_writel(val, sdma->regs + chnenbl);
 }
 
 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
@@ -519,7 +493,6 @@ static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
         struct sdma_buffer_descriptor *bd;
         int i, error = 0;
 
-        sdmac->chn_real_count = 0;
         /*
          * non loop mode. Iterate over all descriptors, collect
          * errors and call callback function
@@ -529,7 +502,6 @@ static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 
                  if (bd->mode.status & (BD_DONE | BD_RROR))
                         error = -EIO;
-                 sdmac->chn_real_count += bd->mode.count;
         }
 
         if (error)
@@ -537,17 +509,19 @@ static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
         else
                 sdmac->status = DMA_SUCCESS;
 
-        dma_cookie_complete(&sdmac->desc);
         if (sdmac->desc.callback)
                 sdmac->desc.callback(sdmac->desc.callback_param);
+        sdmac->last_completed = sdmac->desc.cookie;
 }
 
-static void sdma_tasklet(unsigned long data)
+static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
 {
-        struct sdma_channel *sdmac = (struct sdma_channel *) data;
-
         complete(&sdmac->done);
 
+        /* not interested in channel 0 interrupts */
+        if (sdmac->channel == 0)
+                return;
+
         if (sdmac->flags & IMX_DMA_SG_LOOP)
                 sdma_handle_channel_loop(sdmac);
         else
@@ -557,20 +531,18 @@ static void sdma_tasklet(unsigned long data)
 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 {
         struct sdma_engine *sdma = dev_id;
-        unsigned long stat;
+        u32 stat;
 
-        stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
-        /* not interested in channel 0 interrupts */
-        stat &= ~1;
-        writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
+        stat = __raw_readl(sdma->regs + SDMA_H_INTR);
+        __raw_writel(stat, sdma->regs + SDMA_H_INTR);
 
         while (stat) {
                 int channel = fls(stat) - 1;
                 struct sdma_channel *sdmac = &sdma->channel[channel];
 
-                tasklet_schedule(&sdmac->tasklet);
+                mxc_sdma_handle_channel(sdmac);
 
-                __clear_bit(channel, &stat);
+                stat &= ~(1 << channel);
         }
 
         return IRQ_HANDLED;
@@ -667,9 +639,8 @@ static int sdma_load_context(struct sdma_channel *sdmac)
         struct sdma_context_data *context = sdma->context;
         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
         int ret;
-        unsigned long flags;
 
-        if (sdmac->direction == DMA_DEV_TO_MEM) {
+        if (sdmac->direction == DMA_FROM_DEVICE) {
                 load_address = sdmac->pc_from_device;
         } else {
                 load_address = sdmac->pc_to_device;
@@ -679,13 +650,11 @@ static int sdma_load_context(struct sdma_channel *sdmac)
                 return load_address;
 
         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
-        dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
+        dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
-        dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
-        dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
-
-        spin_lock_irqsave(&sdma->channel_0_lock, flags);
+        dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
+        dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
 
         memset(context, 0, sizeof(*context));
         context->channel_state.pc = load_address;
@@ -693,8 +662,8 @@ static int sdma_load_context(struct sdma_channel *sdmac)
         /* Send by context the event mask,base address for peripheral
          * and watermark level
          */
-        context->gReg[0] = sdmac->event_mask[1];
-        context->gReg[1] = sdmac->event_mask[0];
+        context->gReg[0] = sdmac->event_mask1;
+        context->gReg[1] = sdmac->event_mask0;
         context->gReg[2] = sdmac->per_addr;
         context->gReg[6] = sdmac->shp_addr;
         context->gReg[7] = sdmac->watermark_level;
@@ -704,9 +673,8 @@ static int sdma_load_context(struct sdma_channel *sdmac)
         bd0->mode.count = sizeof(*context) / 4;
         bd0->buffer_addr = sdma->context_phys;
         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
-        ret = sdma_run_channel0(sdma);
 
-        spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
+        ret = sdma_run_channel(&sdma->channel[0]);
 
         return ret;
 }
@@ -716,7 +684,7 @@ static void sdma_disable_channel(struct sdma_channel *sdmac)
         struct sdma_engine *sdma = sdmac->sdma;
         int channel = sdmac->channel;
 
-        writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
+        __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
         sdmac->status = DMA_ERROR;
 }
 
@@ -726,13 +694,13 @@ static int sdma_config_channel(struct sdma_channel *sdmac)
 
         sdma_disable_channel(sdmac);
 
-        sdmac->event_mask[0] = 0;
-        sdmac->event_mask[1] = 0;
+        sdmac->event_mask0 = 0;
+        sdmac->event_mask1 = 0;
         sdmac->shp_addr = 0;
         sdmac->per_addr = 0;
 
         if (sdmac->event_id0) {
-                if (sdmac->event_id0 >= sdmac->sdma->num_events)
+                if (sdmac->event_id0 > 32)
                         return -EINVAL;
                 sdma_event_enable(sdmac, sdmac->event_id0);
         }
@@ -755,14 +723,15 @@ static int sdma_config_channel(struct sdma_channel *sdmac)
                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
                 /* Handle multiple event channels differently */
                 if (sdmac->event_id1) {
-                        sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
+                        sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
                         if (sdmac->event_id1 > 31)
-                                __set_bit(31, &sdmac->watermark_level);
-                        sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
+                                sdmac->watermark_level |= 1 << 31;
+                        sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
                         if (sdmac->event_id0 > 31)
-                                __set_bit(30, &sdmac->watermark_level);
+                                sdmac->watermark_level |= 1 << 30;
                 } else {
-                        __set_bit(sdmac->event_id0, sdmac->event_mask);
+                        sdmac->event_mask0 = 1 << sdmac->event_id0;
+                        sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
                 }
                 /* Watermark Level */
                 sdmac->watermark_level |= sdmac->watermark_level;
@@ -788,7 +757,7 @@ static int sdma_set_channel_priority(struct sdma_channel *sdmac,
                 return -EINVAL;
         }
 
-        writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
+        __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 
         return 0;
 }
@@ -810,16 +779,38 @@ static int sdma_request_channel(struct sdma_channel *sdmac)
         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 
+        clk_enable(sdma->clk);
+
         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 
         init_completion(&sdmac->done);
 
+        sdmac->buf_tail = 0;
+
         return 0;
 out:
 
         return ret;
 }
 
+static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
+{
+        __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
+}
+
+static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
+{
+        dma_cookie_t cookie = sdmac->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        sdmac->chan.cookie = cookie;
+        sdmac->desc.cookie = cookie;
+
+        return cookie;
+}
+
 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 {
         return container_of(chan, struct sdma_channel, chan);
@@ -827,15 +818,17 @@ static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 
 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
-        unsigned long flags;
         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
+        struct sdma_engine *sdma = sdmac->sdma;
         dma_cookie_t cookie;
 
-        spin_lock_irqsave(&sdmac->lock, flags);
+        spin_lock_irq(&sdmac->lock);
 
-        cookie = dma_cookie_assign(tx);
+        cookie = sdma_assign_cookie(sdmac);
 
-        spin_unlock_irqrestore(&sdmac->lock, flags);
+        sdma_enable_channel(sdma, sdmac->channel);
+
+        spin_unlock_irq(&sdmac->lock);
 
         return cookie;
 }
@@ -864,15 +857,11 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
 
         sdmac->peripheral_type = data->peripheral_type;
         sdmac->event_id0 = data->dma_request;
-
-        clk_enable(sdmac->sdma->clk_ipg);
-        clk_enable(sdmac->sdma->clk_ahb);
-
-        ret = sdma_request_channel(sdmac);
+        ret = sdma_set_channel_priority(sdmac, prio);
         if (ret)
                 return ret;
 
-        ret = sdma_set_channel_priority(sdmac, prio);
+        ret = sdma_request_channel(sdmac);
         if (ret)
                 return ret;
 
@@ -903,14 +892,13 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
 
         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
 
-        clk_disable(sdma->clk_ipg);
-        clk_disable(sdma->clk_ahb);
+        clk_disable(sdma->clk);
 }
 
 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
                 struct dma_chan *chan, struct scatterlist *sgl,
-                unsigned int sg_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags)
 {
         struct sdma_channel *sdmac = to_sdma_chan(chan);
         struct sdma_engine *sdma = sdmac->sdma;
@@ -924,8 +912,6 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
 
         sdmac->flags = 0;
 
-        sdmac->buf_tail = 0;
-
         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
                         sg_len, channel);
 
@@ -941,14 +927,13 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
                 goto err_out;
         }
 
-        sdmac->chn_count = 0;
         for_each_sg(sgl, sg, sg_len, i) {
                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
                 int param;
 
                 bd->buffer_addr = sg->dma_address;
 
-                count = sg_dma_len(sg);
+                count = sg->length;
 
                 if (count > 0xffff) {
                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
@@ -958,7 +943,6 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
                 }
 
                 bd->mode.count = count;
-                sdmac->chn_count += count;
 
                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
                         ret =  -EINVAL;
@@ -1010,8 +994,7 @@ err_out:
 
 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
-                size_t period_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                size_t period_len, enum dma_data_direction direction)
 {
         struct sdma_channel *sdmac = to_sdma_chan(chan);
         struct sdma_engine *sdma = sdmac->sdma;
@@ -1026,8 +1009,6 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
 
         sdmac->status = DMA_IN_PROGRESS;
 
-        sdmac->buf_tail = 0;
-
         sdmac->flags |= IMX_DMA_SG_LOOP;
         sdmac->direction = direction;
         ret = sdma_load_context(sdmac);
@@ -1098,18 +1079,15 @@ static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                 sdma_disable_channel(sdmac);
                 return 0;
         case DMA_SLAVE_CONFIG:
-                if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
+                if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
                         sdmac->per_address = dmaengine_cfg->src_addr;
-                        sdmac->watermark_level = dmaengine_cfg->src_maxburst *
-                                                dmaengine_cfg->src_addr_width;
+                        sdmac->watermark_level = dmaengine_cfg->src_maxburst;
                         sdmac->word_size = dmaengine_cfg->src_addr_width;
                 } else {
                         sdmac->per_address = dmaengine_cfg->dst_addr;
-                        sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
-                                                dmaengine_cfg->dst_addr_width;
+                        sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
                 }
-                sdmac->direction = dmaengine_cfg->direction;
                 return sdma_config_channel(sdmac);
         default:
                 return -ENOSYS;
@@ -1127,19 +1105,16 @@ static enum dma_status sdma_tx_status(struct dma_chan *chan,
 
         last_used = chan->cookie;
 
-        dma_set_tx_state(txstate, chan->completed_cookie, last_used,
-                        sdmac->chn_count - sdmac->chn_real_count);
+        dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0);
 
         return sdmac->status;
 }
 
 static void sdma_issue_pending(struct dma_chan *chan)
 {
-        struct sdma_channel *sdmac = to_sdma_chan(chan);
-        struct sdma_engine *sdma = sdmac->sdma;
-
-        if (sdmac->status == DMA_IN_PROGRESS)
-                sdma_enable_channel(sdma, sdmac->channel);
+        /*
+         * Nothing to do. We only have a single descriptor
+         */
 }
 
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
@@ -1156,17 +1131,18 @@ static void sdma_add_scripts(struct sdma_engine *sdma,
                         saddr_arr[i] = addr_arr[i];
 }
 
-static void sdma_load_firmware(const struct firmware *fw, void *context)
+static int __init sdma_get_firmware(struct sdma_engine *sdma,
+                const char *fw_name)
 {
-        struct sdma_engine *sdma = context;
+        const struct firmware *fw;
         const struct sdma_firmware_header *header;
+        int ret;
         const struct sdma_script_start_addrs *addr;
         unsigned short *ram_code;
 
-        if (!fw) {
-                dev_err(sdma->dev, "firmware not found\n");
-                return;
-        }
+        ret = request_firmware(&fw, fw_name, sdma->dev);
+        if (ret)
+                return ret;
 
         if (fw->size < sizeof(*header))
                 goto err_firmware;
@@ -1181,14 +1157,12 @@ static void sdma_load_firmware(const struct firmware *fw, void *context)
         addr = (void *)header + header->script_addrs_start;
         ram_code = (void *)header + header->ram_code_start;
 
-        clk_enable(sdma->clk_ipg);
-        clk_enable(sdma->clk_ahb);
+        clk_enable(sdma->clk);
         /* download the RAM image for SDMA */
         sdma_load_script(sdma, ram_code,
                         header->ram_code_size,
                         addr->ram_code_start_addr);
-        clk_disable(sdma->clk_ipg);
-        clk_disable(sdma->clk_ahb);
+        clk_disable(sdma->clk);
 
         sdma_add_scripts(sdma, addr);
 
@@ -1198,16 +1172,6 @@ static void sdma_load_firmware(const struct firmware *fw, void *context)
 
 err_firmware:
         release_firmware(fw);
-}
-
-static int __init sdma_get_firmware(struct sdma_engine *sdma,
-                const char *fw_name)
-{
-        int ret;
-
-        ret = request_firmware_nowait(THIS_MODULE,
-                        FW_ACTION_HOTPLUG, fw_name, sdma->dev,
-                        GFP_KERNEL, sdma, sdma_load_firmware);
 
         return ret;
 }
@@ -1230,11 +1194,10 @@ static int __init sdma_init(struct sdma_engine *sdma)
                 return -ENODEV;
         }
 
-        clk_enable(sdma->clk_ipg);
-        clk_enable(sdma->clk_ahb);
+        clk_enable(sdma->clk);
 
         /* Be sure SDMA has not started yet */
-        writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
+        __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
 
         sdma->channel_control = dma_alloc_coherent(NULL,
                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
@@ -1257,11 +1220,11 @@ static int __init sdma_init(struct sdma_engine *sdma)
 
         /* disable all channels */
         for (i = 0; i < sdma->num_events; i++)
-                writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
+                __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
 
         /* All channels have priority 0 */
         for (i = 0; i < MAX_DMA_CHANNELS; i++)
-                writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
+                __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
 
         ret = sdma_request_channel(&sdma->channel[0]);
         if (ret)
@@ -1270,28 +1233,26 @@ static int __init sdma_init(struct sdma_engine *sdma)
         sdma_config_ownership(&sdma->channel[0], false, true, false);
 
         /* Set Command Channel (Channel Zero) */
-        writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
+        __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
 
         /* Set bits of CONFIG register but with static context switching */
         /* FIXME: Check whether to set ACR bit depending on clock ratios */
-        writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
+        __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
 
-        writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
+        __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
 
         /* Set bits of CONFIG register with given context switching mode */
-        writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
+        __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 
         /* Initializes channel's priorities */
         sdma_set_channel_priority(&sdma->channel[0], 7);
 
-        clk_disable(sdma->clk_ipg);
-        clk_disable(sdma->clk_ahb);
+        clk_disable(sdma->clk);
 
         return 0;
 
 err_dma_alloc:
-        clk_disable(sdma->clk_ipg);
-        clk_disable(sdma->clk_ahb);
+        clk_disable(sdma->clk);
         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
         return ret;
 }
@@ -1308,14 +1269,11 @@ static int __init sdma_probe(struct platform_device *pdev)
         struct sdma_platform_data *pdata = pdev->dev.platform_data;
         int i;
         struct sdma_engine *sdma;
-        s32 *saddr_arr;
 
         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
         if (!sdma)
                 return -ENOMEM;
 
-        spin_lock_init(&sdma->channel_0_lock);
-
         sdma->dev = &pdev->dev;
 
         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1330,21 +1288,12 @@ static int __init sdma_probe(struct platform_device *pdev)
                 goto err_request_region;
         }
 
-        sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
-        if (IS_ERR(sdma->clk_ipg)) {
-                ret = PTR_ERR(sdma->clk_ipg);
+        sdma->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(sdma->clk)) {
+                ret = PTR_ERR(sdma->clk);
                 goto err_clk;
         }
 
-        sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
-        if (IS_ERR(sdma->clk_ahb)) {
-                ret = PTR_ERR(sdma->clk_ahb);
-                goto err_clk;
-        }
-
-        clk_prepare(sdma->clk_ipg);
-        clk_prepare(sdma->clk_ahb);
-
         sdma->regs = ioremap(iores->start, resource_size(iores));
         if (!sdma->regs) {
                 ret = -ENOMEM;
@@ -1361,11 +1310,6 @@ static int __init sdma_probe(struct platform_device *pdev)
                 goto err_alloc;
         }
 
-        /* initially no scripts available */
-        saddr_arr = (s32 *)sdma->script_addrs;
-        for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
-                saddr_arr[i] = -EINVAL;
-
         if (of_id)
                 pdev->id_entry = of_id->data;
         sdma->devtype = pdev->id_entry->driver_data;
@@ -1382,11 +1326,8 @@ static int __init sdma_probe(struct platform_device *pdev)
                 spin_lock_init(&sdmac->lock);
 
                 sdmac->chan.device = &sdma->dma_device;
-                dma_cookie_init(&sdmac->chan);
                 sdmac->channel = i;
 
-                tasklet_init(&sdmac->tasklet, sdma_tasklet,
-                             (unsigned long) sdmac);
                 /*
                  * Add the channel to the DMAC list. Do not add channel 0 though
                  * because we need it internally in the SDMA driver. This also means
@@ -1405,9 +1346,7 @@ static int __init sdma_probe(struct platform_device *pdev)
                 sdma_add_scripts(sdma, pdata->script_addrs);
 
         if (pdata) {
-                ret = sdma_get_firmware(sdma, pdata->fw_name);
-                if (ret)
-                        dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
+                sdma_get_firmware(sdma, pdata->fw_name);
         } else {
                 /*
                  * Because that device tree does not encode ROM script address,
@@ -1416,12 +1355,15 @@ static int __init sdma_probe(struct platform_device *pdev)
                  */
                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
                                               &fw_name);
-                if (ret)
-                        dev_warn(&pdev->dev, "failed to get firmware name\n");
-                else {
-                        ret = sdma_get_firmware(sdma, fw_name);
-                        if (ret)
-                                dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
+                if (ret) {
+                        dev_err(&pdev->dev, "failed to get firmware name\n");
+                        goto err_init;
+                }
+
+                ret = sdma_get_firmware(sdma, fw_name);
+                if (ret) {
+                        dev_err(&pdev->dev, "failed to get firmware\n");
+                        goto err_init;
                 }
         }
 
@@ -1454,6 +1396,7 @@ err_alloc:
 err_request_irq:
         iounmap(sdma->regs);
 err_ioremap:
+        clk_put(sdma->clk);
 err_clk:
         release_mem_region(iores->start, resource_size(iores));
 err_request_region:
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index a0de82e21a7..8a3fdd87db9 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -27,9 +27,6 @@
 #include <linux/interrupt.h>
 #include <linux/pm_runtime.h>
 #include <linux/intel_mid_dma.h>
-#include <linux/module.h>
-
-#include "dmaengine.h"
 
 #define MAX_CHAN        4 /*max ch across controllers*/
 #include "intel_mid_dma_regs.h"
@@ -118,15 +115,16 @@ DMAC1 interrupt Functions*/
 
 /**
  * dmac1_mask_periphral_intr -  mask the periphral interrupt
- * @mid: dma device for which masking is required
+ * @midc: dma channel for which masking is required
  *
  * Masks the DMA periphral interrupt
  * this is valid for DMAC1 family controllers only
  * This controller should have periphral mask registers already mapped
  */
-static void dmac1_mask_periphral_intr(struct middma_device *mid)
+static void dmac1_mask_periphral_intr(struct intel_mid_dma_chan *midc)
 {
         u32 pimr;
+        struct middma_device *mid = to_middma_device(midc->chan.device);
 
         if (mid->pimr_mask) {
                 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
@@ -186,6 +184,7 @@ static void enable_dma_interrupt(struct intel_mid_dma_chan *midc)
 static void disable_dma_interrupt(struct intel_mid_dma_chan *midc)
 {
         /*Check LPE PISR, make sure fwd is disabled*/
+        dmac1_mask_periphral_intr(midc);
         iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK);
         iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
         iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
@@ -282,15 +281,14 @@ static void midc_dostart(struct intel_mid_dma_chan *midc,
  * callbacks but must be called with the lock held.
  */
 static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
-                struct intel_mid_dma_desc *desc)
-                __releases(&midc->lock) __acquires(&midc->lock)
+               struct intel_mid_dma_desc *desc)
 {
         struct dma_async_tx_descriptor  *txd = &desc->txd;
         dma_async_tx_callback callback_txd = NULL;
         struct intel_mid_dma_lli        *llitem;
         void *param_txd = NULL;
 
-        dma_cookie_complete(txd);
+        midc->completed = txd->cookie;
         callback_txd = txd->callback;
         param_txd = txd->callback_param;
 
@@ -314,7 +312,6 @@ static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
                         pci_pool_free(desc->lli_pool, desc->lli,
                                                 desc->lli_phys);
                         pci_pool_destroy(desc->lli_pool);
-                        desc->lli = NULL;
                 }
                 list_move(&desc->desc_node, &midc->free_list);
                 midc->busy = false;
@@ -394,15 +391,15 @@ static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
                         }
                 }
                 /*Populate CTL_HI values*/
-                ctl_hi.ctlx.block_ts = get_block_ts(sg_dma_len(sg),
+                ctl_hi.ctlx.block_ts = get_block_ts(sg->length,
                                                         desc->width,
                                                         midc->dma->block_size);
                 /*Populate SAR and DAR values*/
-                sg_phy_addr = sg_dma_address(sg);
-                if (desc->dirn ==  DMA_MEM_TO_DEV) {
+                sg_phy_addr = sg_phys(sg);
+                if (desc->dirn ==  DMA_TO_DEVICE) {
                         lli_bloc_desc->sar  = sg_phy_addr;
                         lli_bloc_desc->dar  = mids->dma_slave.dst_addr;
-                } else if (desc->dirn ==  DMA_DEV_TO_MEM) {
+                } else if (desc->dirn ==  DMA_FROM_DEVICE) {
                         lli_bloc_desc->sar  = mids->dma_slave.src_addr;
                         lli_bloc_desc->dar  = sg_phy_addr;
                 }
@@ -427,7 +424,7 @@ DMA engine callback Functions*/
  * intel_mid_dma_tx_submit -    callback to submit DMA transaction
  * @tx: dma engine descriptor
  *
- * Submit the DMA transaction for this descriptor, start if ch idle
+ * Submit the DMA trasaction for this descriptor, start if ch idle
  */
 static dma_cookie_t intel_mid_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
@@ -436,7 +433,14 @@ static dma_cookie_t intel_mid_dma_tx_submit(struct dma_async_tx_descriptor *tx)
         dma_cookie_t            cookie;
 
         spin_lock_bh(&midc->lock);
-        cookie = dma_cookie_assign(tx);
+        cookie = midc->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        midc->chan.cookie = cookie;
+        desc->txd.cookie = cookie;
+
 
         if (list_empty(&midc->active_list))
                 list_add_tail(&desc->desc_node, &midc->active_list);
@@ -477,18 +481,29 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
                                                 dma_cookie_t cookie,
                                                 struct dma_tx_state *txstate)
 {
-        struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
-        enum dma_status ret;
+        struct intel_mid_dma_chan       *midc = to_intel_mid_dma_chan(chan);
+        dma_cookie_t            last_used;
+        dma_cookie_t            last_complete;
+        int                             ret;
+
+        last_complete = midc->completed;
+        last_used = chan->cookie;
 
-        ret = dma_cookie_status(chan, cookie, txstate);
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
         if (ret != DMA_SUCCESS) {
-                spin_lock_bh(&midc->lock);
                 midc_scan_descriptors(to_middma_device(chan->device), midc);
-                spin_unlock_bh(&midc->lock);
 
-                ret = dma_cookie_status(chan, cookie, txstate);
+                last_complete = midc->completed;
+                last_used = chan->cookie;
+
+                ret = dma_async_is_complete(cookie, last_complete, last_used);
         }
 
+        if (txstate) {
+                txstate->last = last_complete;
+                txstate->used = last_used;
+                txstate->residue = 0;
+        }
         return ret;
 }
 
@@ -552,7 +567,6 @@ static int intel_mid_dma_device_control(struct dma_chan *chan,
                         pci_pool_free(desc->lli_pool, desc->lli,
                                                 desc->lli_phys);
                         pci_pool_destroy(desc->lli_pool);
-                        desc->lli = NULL;
                 }
                 list_move(&desc->desc_node, &midc->free_list);
         }
@@ -619,13 +633,13 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
                 if (midc->dma->pimr_mask) {
                         cfg_hi.cfgx.protctl = 0x0; /*default value*/
                         cfg_hi.cfgx.fifo_mode = 1;
-                        if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
+                        if (mids->dma_slave.direction == DMA_TO_DEVICE) {
                                 cfg_hi.cfgx.src_per = 0;
                                 if (mids->device_instance == 0)
                                         cfg_hi.cfgx.dst_per = 3;
                                 if (mids->device_instance == 1)
                                         cfg_hi.cfgx.dst_per = 1;
-                        } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
+                        } else if (mids->dma_slave.direction == DMA_FROM_DEVICE) {
                                 if (mids->device_instance == 0)
                                         cfg_hi.cfgx.src_per = 2;
                                 if (mids->device_instance == 1)
@@ -669,11 +683,11 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
                 ctl_lo.ctlx.sinc = 0;
                 ctl_lo.ctlx.dinc = 0;
         } else {
-                if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
+                if (mids->dma_slave.direction == DMA_TO_DEVICE) {
                         ctl_lo.ctlx.sinc = 0;
                         ctl_lo.ctlx.dinc = 2;
                         ctl_lo.ctlx.tt_fc = 1;
-                } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
+                } else if (mids->dma_slave.direction == DMA_FROM_DEVICE) {
                         ctl_lo.ctlx.sinc = 2;
                         ctl_lo.ctlx.dinc = 0;
                         ctl_lo.ctlx.tt_fc = 2;
@@ -714,14 +728,13 @@ err_desc_get:
  * @sg_len: length of sg txn
  * @direction: DMA transfer dirtn
  * @flags: DMA flags
- * @context: transfer context (ignored)
  *
  * Prepares LLI based periphral transfer
  */
 static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
                         struct dma_chan *chan, struct scatterlist *sgl,
-                        unsigned int sg_len, enum dma_transfer_direction direction,
-                        unsigned long flags, void *context)
+                        unsigned int sg_len, enum dma_data_direction direction,
+                        unsigned long flags)
 {
         struct intel_mid_dma_chan *midc = NULL;
         struct intel_mid_dma_slave *mids = NULL;
@@ -747,7 +760,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
                         txd = intel_mid_dma_prep_memcpy(chan,
                                                 mids->dma_slave.dst_addr,
                                                 mids->dma_slave.src_addr,
-                                                sg_dma_len(sgl),
+                                                sgl->length,
                                                 flags);
                         return txd;
                 } else {
@@ -759,7 +772,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
         pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",
                         sg_len, direction, flags);
 
-        txd = intel_mid_dma_prep_memcpy(chan, 0, 0, sg_dma_len(sgl), flags);
+        txd = intel_mid_dma_prep_memcpy(chan, 0, 0, sgl->length, flags);
         if (NULL == txd) {
                 pr_err("MDMA: Prep memcpy failed\n");
                 return NULL;
@@ -815,6 +828,7 @@ static void intel_mid_dma_free_chan_resources(struct dma_chan *chan)
                 /*trying to free ch in use!!!!!*/
                 pr_err("ERR_MDMA: trying to free ch in use\n");
         }
+        pm_runtime_put(&mid->pdev->dev);
         spin_lock_bh(&midc->lock);
         midc->descs_allocated = 0;
         list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
@@ -835,7 +849,6 @@ static void intel_mid_dma_free_chan_resources(struct dma_chan *chan)
         /* Disable CH interrupts */
         iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_BLOCK);
         iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_ERR);
-        pm_runtime_put(&mid->pdev->dev);
 }
 
 /**
@@ -856,7 +869,7 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
         pm_runtime_get_sync(&mid->pdev->dev);
 
         if (mid->state == SUSPENDED) {
-                if (dma_resume(&mid->pdev->dev)) {
+                if (dma_resume(mid->pdev)) {
                         pr_err("ERR_MDMA: resume failed");
                         return -EFAULT;
                 }
@@ -869,7 +882,7 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
                 pm_runtime_put(&mid->pdev->dev);
                 return -EIO;
         }
-        dma_cookie_init(chan);
+        midc->completed = chan->cookie = 1;
 
         spin_lock_bh(&midc->lock);
         while (midc->descs_allocated < DESCS_PER_CHANNEL) {
@@ -1039,8 +1052,7 @@ static irqreturn_t intel_mid_dma_interrupt(int irq, void *data)
         }
         err_status &= mid->intr_mask;
         if (err_status) {
-                iowrite32((err_status << INT_MASK_WE),
-                          mid->dma_base + MASK_ERR);
+                iowrite32(MASK_INTR_REG(err_status), mid->dma_base + MASK_ERR);
                 call_tasklet = 1;
         }
         if (call_tasklet)
@@ -1088,8 +1100,7 @@ static int mid_setup_dma(struct pci_dev *pdev)
                                         LNW_PERIPHRAL_MASK_SIZE);
                 if (dma->mask_reg == NULL) {
                         pr_err("ERR_MDMA:Can't map periphral intr space !!\n");
-                        err = -ENOMEM;
-                        goto err_ioremap;
+                        return -ENOMEM;
                 }
         } else
                 dma->mask_reg = NULL;
@@ -1102,7 +1113,8 @@ static int mid_setup_dma(struct pci_dev *pdev)
                 struct intel_mid_dma_chan *midch = &dma->ch[i];
 
                 midch->chan.device = &dma->common;
-                dma_cookie_init(&midch->chan);
+                midch->chan.cookie =  1;
+                midch->chan.chan_id = i;
                 midch->ch_id = dma->chan_base + i;
                 pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id);
 
@@ -1138,6 +1150,7 @@ static int mid_setup_dma(struct pci_dev *pdev)
         dma_cap_set(DMA_SLAVE, dma->common.cap_mask);
         dma_cap_set(DMA_PRIVATE, dma->common.cap_mask);
         dma->common.dev = &pdev->dev;
+        dma->common.chancnt = dma->max_chan;
 
         dma->common.device_alloc_chan_resources =
                                         intel_mid_dma_alloc_chan_resources;
@@ -1186,9 +1199,6 @@ static int mid_setup_dma(struct pci_dev *pdev)
 err_engine:
         free_irq(pdev->irq, dma);
 err_irq:
-        if (dma->mask_reg)
-                iounmap(dma->mask_reg);
-err_ioremap:
         pci_pool_destroy(dma->dma_pool);
 err_dma_pool:
         pr_err("ERR_MDMA:setup_dma failed: %d\n", err);
@@ -1225,7 +1235,7 @@ static void middma_shutdown(struct pci_dev *pdev)
  * Initialize the PCI device, map BARs, query driver data.
  * Call setup_dma to complete contoller and chan initilzation
  */
-static int intel_mid_dma_probe(struct pci_dev *pdev,
+static int __devinit intel_mid_dma_probe(struct pci_dev *pdev,
                                         const struct pci_device_id *id)
 {
         struct middma_device *device;
@@ -1308,7 +1318,7 @@ err_enable_device:
  * Free up all resources and data
  * Call shutdown_dma to complete contoller and chan cleanup
  */
-static void intel_mid_dma_remove(struct pci_dev *pdev)
+static void __devexit intel_mid_dma_remove(struct pci_dev *pdev)
 {
         struct middma_device *device = pci_get_drvdata(pdev);
 
@@ -1330,9 +1340,8 @@ static void intel_mid_dma_remove(struct pci_dev *pdev)
 *
 * This function is called by OS when a power event occurs
 */
-static int dma_suspend(struct device *dev)
+int dma_suspend(struct pci_dev *pci, pm_message_t state)
 {
-        struct pci_dev *pci = to_pci_dev(dev);
         int i;
         struct middma_device *device = pci_get_drvdata(pci);
         pr_debug("MDMA: dma_suspend called\n");
@@ -1341,7 +1350,6 @@ static int dma_suspend(struct device *dev)
                 if (device->ch[i].in_use)
                         return -EAGAIN;
         }
-        dmac1_mask_periphral_intr(device);
         device->state = SUSPENDED;
         pci_save_state(pci);
         pci_disable_device(pci);
@@ -1356,9 +1364,8 @@ static int dma_suspend(struct device *dev)
 *
 * This function is called by OS when a power event occurs
 */
-int dma_resume(struct device *dev)
+int dma_resume(struct pci_dev *pci)
 {
-        struct pci_dev *pci = to_pci_dev(dev);
         int ret;
         struct middma_device *device = pci_get_drvdata(pci);
 
@@ -1424,16 +1431,16 @@ static const struct dev_pm_ops intel_mid_dma_pm = {
         .runtime_suspend = dma_runtime_suspend,
         .runtime_resume = dma_runtime_resume,
         .runtime_idle = dma_runtime_idle,
-        .suspend = dma_suspend,
-        .resume = dma_resume,
 };
 
 static struct pci_driver intel_mid_dma_pci_driver = {
         .name           =       "Intel MID DMA",
         .id_table       =       intel_mid_dma_ids,
         .probe          =       intel_mid_dma_probe,
-        .remove         =       intel_mid_dma_remove,
+        .remove         =       __devexit_p(intel_mid_dma_remove),
 #ifdef CONFIG_PM
+        .suspend = dma_suspend,
+        .resume = dma_resume,
         .driver = {
                 .pm = &intel_mid_dma_pm,
         },
diff --git a/drivers/dma/intel_mid_dma_regs.h b/drivers/dma/intel_mid_dma_regs.h
index 17b42192ea5..aea5ee88ce0 100644
--- a/drivers/dma/intel_mid_dma_regs.h
+++ b/drivers/dma/intel_mid_dma_regs.h
@@ -165,12 +165,13 @@ union intel_mid_dma_cfg_hi {
  * @dma_base: MMIO register space DMA engine base pointer
  * @ch_id: DMA channel id
  * @lock: channel spinlock
+ * @completed: DMA cookie
  * @active_list: current active descriptors
  * @queue: current queued up descriptors
  * @free_list: current free descriptors
- * @slave: dma slave structure
- * @descs_allocated: total number of descriptors allocated
- * @dma: dma device structure pointer
+ * @slave: dma slave struture
+ * @descs_allocated: total number of decsiptors allocated
+ * @dma: dma device struture pointer
  * @busy: bool representing if ch is busy (active txn) or not
  * @in_use: bool representing if ch is in use or not
  * @raw_tfr: raw trf interrupt received
@@ -182,6 +183,7 @@ struct intel_mid_dma_chan {
         void __iomem            *dma_base;
         int                     ch_id;
         spinlock_t              lock;
+        dma_cookie_t            completed;
         struct list_head        active_list;
         struct list_head        queue;
         struct list_head        free_list;
@@ -260,7 +262,7 @@ struct intel_mid_dma_desc {
         unsigned int                    lli_length;
         unsigned int                    current_lli;
         dma_addr_t                      next;
-        enum dma_transfer_direction             dirn;
+        enum dma_data_direction         dirn;
         enum dma_status                 status;
         enum dma_slave_buswidth         width; /*width of DMA txn*/
         enum intel_mid_dma_mode         cfg_mode; /*mode configuration*/
@@ -294,6 +296,6 @@ static inline struct intel_mid_dma_slave *to_intel_mid_dma_slave
 }
 
 
-int dma_resume(struct device *dev);
+int dma_resume(struct pci_dev *pci);
 
 #endif /*__INTEL_MID_DMAC_REGS_H__*/
diff --git a/drivers/dma/ioat/dca.c b/drivers/dma/ioat/dca.c
index 9b041858d10..abd9038e06b 100644
--- a/drivers/dma/ioat/dca.c
+++ b/drivers/dma/ioat/dca.c
@@ -242,7 +242,8 @@ static struct dca_ops ioat_dca_ops = {
 };
 
 
-struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase)
+struct dca_provider * __devinit
+ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase)
 {
         struct dca_provider *dca;
         struct ioat_dca_priv *ioatdca;
@@ -407,7 +408,8 @@ static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset)
         return slots;
 }
 
-struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase)
+struct dca_provider * __devinit
+ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase)
 {
         struct dca_provider *dca;
         struct ioat_dca_priv *ioatdca;
@@ -602,24 +604,8 @@ static int ioat3_dca_count_dca_slots(void *iobase, u16 dca_offset)
         return slots;
 }
 
-static inline int dca3_tag_map_invalid(u8 *tag_map)
-{
-        /*
-         * If the tag map is not programmed by the BIOS the default is:
-         * 0x80 0x80 0x80 0x80 0x80 0x00 0x00 0x00
-         *
-         * This an invalid map and will result in only 2 possible tags
-         * 0x1F and 0x00.  0x00 is an invalid DCA tag so we know that
-         * this entire definition is invalid.
-         */
-        return ((tag_map[0] == DCA_TAG_MAP_VALID) &&
-                (tag_map[1] == DCA_TAG_MAP_VALID) &&
-                (tag_map[2] == DCA_TAG_MAP_VALID) &&
-                (tag_map[3] == DCA_TAG_MAP_VALID) &&
-                (tag_map[4] == DCA_TAG_MAP_VALID));
-}
-
-struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase)
+struct dca_provider * __devinit
+ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase)
 {
         struct dca_provider *dca;
         struct ioat_dca_priv *ioatdca;
@@ -688,12 +674,6 @@ struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase)
                 ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK;
         }
 
-        if (dca3_tag_map_invalid(ioatdca->tag_map)) {
-                dev_err(&pdev->dev, "APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n");
-                free_dca_provider(dca);
-                return NULL;
-        }
-
         err = register_dca_provider(dca, &pdev->dev);
         if (err) {
                 free_dca_provider(dca);
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index 1a68a8ba87e..a4d6cb0c034 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -40,8 +40,6 @@
 #include "registers.h"
 #include "hw.h"
 
-#include "../dmaengine.h"
-
 int ioat_pending_level = 4;
 module_param(ioat_pending_level, int, 0644);
 MODULE_PARM_DESC(ioat_pending_level,
@@ -109,7 +107,6 @@ void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *c
         chan->reg_base = device->reg_base + (0x80 * (idx + 1));
         spin_lock_init(&chan->cleanup_lock);
         chan->common.device = dma;
-        dma_cookie_init(&chan->common);
         list_add_tail(&chan->common.device_node, &dma->channels);
         device->idx[idx] = chan;
         init_timer(&chan->timer);
@@ -238,7 +235,12 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 
         spin_lock_bh(&ioat->desc_lock);
         /* cookie incr and addition to used_list must be atomic */
-        cookie = dma_cookie_assign(tx);
+        cookie = c->cookie;
+        cookie++;
+        if (cookie < 0)
+                cookie = 1;
+        c->cookie = cookie;
+        tx->cookie = cookie;
         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 
         /* write address into NextDescriptor field of last desc in chain */
@@ -546,9 +548,9 @@ void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
                            PCI_DMA_TODEVICE, flags, 0);
 }
 
-dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan)
+unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
 {
-        dma_addr_t phys_complete;
+        unsigned long phys_complete;
         u64 completion;
 
         completion = *chan->completion;
@@ -569,7 +571,7 @@ dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan)
 }
 
 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
-                           dma_addr_t *phys_complete)
+                           unsigned long *phys_complete)
 {
         *phys_complete = ioat_get_current_completion(chan);
         if (*phys_complete == chan->last_completion)
@@ -580,14 +582,14 @@ bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
         return true;
 }
 
-static void __cleanup(struct ioat_dma_chan *ioat, dma_addr_t phys_complete)
+static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
 {
         struct ioat_chan_common *chan = &ioat->base;
         struct list_head *_desc, *n;
         struct dma_async_tx_descriptor *tx;
 
-        dev_dbg(to_dev(chan), "%s: phys_complete: %llx\n",
-                 __func__, (unsigned long long) phys_complete);
+        dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n",
+                 __func__, phys_complete);
         list_for_each_safe(_desc, n, &ioat->used_desc) {
                 struct ioat_desc_sw *desc;
 
@@ -601,7 +603,8 @@ static void __cleanup(struct ioat_dma_chan *ioat, dma_addr_t phys_complete)
                  */
                 dump_desc_dbg(ioat, desc);
                 if (tx->cookie) {
-                        dma_cookie_complete(tx);
+                        chan->completed_cookie = tx->cookie;
+                        tx->cookie = 0;
                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
                         ioat->active -= desc->hw->tx_cnt;
                         if (tx->callback) {
@@ -652,7 +655,7 @@ static void __cleanup(struct ioat_dma_chan *ioat, dma_addr_t phys_complete)
 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
 {
         struct ioat_chan_common *chan = &ioat->base;
-        dma_addr_t phys_complete;
+        unsigned long phys_complete;
 
         prefetch(chan->completion);
 
@@ -698,7 +701,7 @@ static void ioat1_timer_event(unsigned long data)
                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
                 spin_unlock_bh(&ioat->desc_lock);
         } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
-                dma_addr_t phys_complete;
+                unsigned long phys_complete;
 
                 spin_lock_bh(&ioat->desc_lock);
                 /* if we haven't made progress and we have already
@@ -730,15 +733,13 @@ ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 {
         struct ioat_chan_common *chan = to_chan_common(c);
         struct ioatdma_device *device = chan->device;
-        enum dma_status ret;
 
-        ret = dma_cookie_status(c, cookie, txstate);
-        if (ret == DMA_SUCCESS)
-                return ret;
+        if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
+                return DMA_SUCCESS;
 
         device->cleanup_fn((unsigned long) c);
 
-        return dma_cookie_status(c, cookie, txstate);
+        return ioat_tx_status(c, cookie, txstate);
 }
 
 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
@@ -782,7 +783,7 @@ static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
  */
 #define IOAT_TEST_SIZE 2000
 
-static void ioat_dma_test_callback(void *dma_async_param)
+static void __devinit ioat_dma_test_callback(void *dma_async_param)
 {
         struct completion *cmp = dma_async_param;
 
@@ -793,7 +794,7 @@ static void ioat_dma_test_callback(void *dma_async_param)
  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
  * @device: device to be tested
  */
-int ioat_dma_self_test(struct ioatdma_device *device)
+int __devinit ioat_dma_self_test(struct ioatdma_device *device)
 {
         int i;
         u8 *src;
@@ -994,7 +995,7 @@ static void ioat_disable_interrupts(struct ioatdma_device *device)
         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
 }
 
-int ioat_probe(struct ioatdma_device *device)
+int __devinit ioat_probe(struct ioatdma_device *device)
 {
         int err = -ENODEV;
         struct dma_device *dma = &device->common;
@@ -1049,7 +1050,7 @@ err_dma_pool:
         return err;
 }
 
-int ioat_register(struct ioatdma_device *device)
+int __devinit ioat_register(struct ioatdma_device *device)
 {
         int err = dma_async_device_register(&device->common);
 
@@ -1183,7 +1184,7 @@ void ioat_kobject_del(struct ioatdma_device *device)
         }
 }
 
-int ioat1_dma_probe(struct ioatdma_device *device, int dca)
+int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
 {
         struct pci_dev *pdev = device->pdev;
         struct dma_device *dma;
@@ -1216,7 +1217,7 @@ int ioat1_dma_probe(struct ioatdma_device *device, int dca)
         return err;
 }
 
-void ioat_dma_remove(struct ioatdma_device *device)
+void __devexit ioat_dma_remove(struct ioatdma_device *device)
 {
         struct dma_device *dma = &device->common;
 
diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h
index 087935f1565..5216c8a92a2 100644
--- a/drivers/dma/ioat/dma.h
+++ b/drivers/dma/ioat/dma.h
@@ -88,8 +88,9 @@ struct ioatdma_device {
 struct ioat_chan_common {
         struct dma_chan common;
         void __iomem *reg_base;
-        dma_addr_t last_completion;
+        unsigned long last_completion;
         spinlock_t cleanup_lock;
+        dma_cookie_t completed_cookie;
         unsigned long state;
         #define IOAT_COMPLETION_PENDING 0
         #define IOAT_COMPLETION_ACK 1
@@ -142,6 +143,28 @@ static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
         return container_of(chan, struct ioat_dma_chan, base);
 }
 
+/**
+ * ioat_tx_status - poll the status of an ioat transaction
+ * @c: channel handle
+ * @cookie: transaction identifier
+ * @txstate: if set, updated with the transaction state
+ */
+static inline enum dma_status
+ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
+                 struct dma_tx_state *txstate)
+{
+        struct ioat_chan_common *chan = to_chan_common(c);
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
+
+        last_used = c->cookie;
+        last_complete = chan->completed_cookie;
+
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+        return dma_async_is_complete(cookie, last_complete, last_used);
+}
+
 /* wrapper around hardware descriptor format + additional software fields */
 
 /**
@@ -303,13 +326,14 @@ static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
                 pci_unmap_page(pdev, addr, len, direction);
 }
 
-int ioat_probe(struct ioatdma_device *device);
-int ioat_register(struct ioatdma_device *device);
-int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
-int ioat_dma_self_test(struct ioatdma_device *device);
-void ioat_dma_remove(struct ioatdma_device *device);
-struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
-dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
+int __devinit ioat_probe(struct ioatdma_device *device);
+int __devinit ioat_register(struct ioatdma_device *device);
+int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca);
+int __devinit ioat_dma_self_test(struct ioatdma_device *device);
+void __devexit ioat_dma_remove(struct ioatdma_device *device);
+struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev,
+                                              void __iomem *iobase);
+unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
 void ioat_init_channel(struct ioatdma_device *device,
                        struct ioat_chan_common *chan, int idx);
 enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
@@ -317,7 +341,7 @@ enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
                     size_t len, struct ioat_dma_descriptor *hw);
 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
-                           dma_addr_t *phys_complete);
+                           unsigned long *phys_complete);
 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
 void ioat_kobject_del(struct ioatdma_device *device);
 extern const struct sysfs_ops ioat_sysfs_ops;
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index 82d4e306c32..5d65f837797 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -41,8 +41,6 @@
 #include "registers.h"
 #include "hw.h"
 
-#include "../dmaengine.h"
-
 int ioat_ring_alloc_order = 8;
 module_param(ioat_ring_alloc_order, int, 0644);
 MODULE_PARM_DESC(ioat_ring_alloc_order,
@@ -128,7 +126,7 @@ static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
         spin_unlock_bh(&ioat->prep_lock);
 }
 
-static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
+static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 {
         struct ioat_chan_common *chan = &ioat->base;
         struct dma_async_tx_descriptor *tx;
@@ -149,7 +147,8 @@ static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
                 dump_desc_dbg(ioat, desc);
                 if (tx->cookie) {
                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
-                        dma_cookie_complete(tx);
+                        chan->completed_cookie = tx->cookie;
+                        tx->cookie = 0;
                         if (tx->callback) {
                                 tx->callback(tx->callback_param);
                                 tx->callback = NULL;
@@ -179,7 +178,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
 static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
 {
         struct ioat_chan_common *chan = &ioat->base;
-        dma_addr_t phys_complete;
+        unsigned long phys_complete;
 
         spin_lock_bh(&chan->cleanup_lock);
         if (ioat_cleanup_preamble(chan, &phys_complete))
@@ -260,7 +259,7 @@ int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo)
 static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
 {
         struct ioat_chan_common *chan = &ioat->base;
-        dma_addr_t phys_complete;
+        unsigned long phys_complete;
 
         ioat2_quiesce(chan, 0);
         if (ioat_cleanup_preamble(chan, &phys_complete))
@@ -275,7 +274,7 @@ void ioat2_timer_event(unsigned long data)
         struct ioat_chan_common *chan = &ioat->base;
 
         if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
-                dma_addr_t phys_complete;
+                unsigned long phys_complete;
                 u64 status;
 
                 status = ioat_chansts(chan);
@@ -399,9 +398,13 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
         struct dma_chan *c = tx->chan;
         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
         struct ioat_chan_common *chan = &ioat->base;
-        dma_cookie_t cookie;
+        dma_cookie_t cookie = c->cookie;
 
-        cookie = dma_cookie_assign(tx);
+        cookie++;
+        if (cookie < 0)
+                cookie = 1;
+        tx->cookie = cookie;
+        c->cookie = cookie;
         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 
         if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
@@ -434,11 +437,12 @@ static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t f
                 return NULL;
         memset(hw, 0, sizeof(*hw));
 
-        desc = kmem_cache_zalloc(ioat2_cache, flags);
+        desc = kmem_cache_alloc(ioat2_cache, flags);
         if (!desc) {
                 pci_pool_free(dma->dma_pool, hw, phys);
                 return NULL;
         }
+        memset(desc, 0, sizeof(*desc));
 
         dma_async_tx_descriptor_init(&desc->txd, chan);
         desc->txd.tx_submit = ioat2_tx_submit_unlock;
@@ -571,9 +575,9 @@ bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
          */
         struct ioat_chan_common *chan = &ioat->base;
         struct dma_chan *c = &chan->common;
-        const u32 curr_size = ioat2_ring_size(ioat);
+        const u16 curr_size = ioat2_ring_size(ioat);
         const u16 active = ioat2_ring_active(ioat);
-        const u32 new_size = 1 << order;
+        const u16 new_size = 1 << order;
         struct ioat_ring_ent **ring;
         u16 i;
 
@@ -862,7 +866,7 @@ struct kobj_type ioat2_ktype = {
         .default_attrs = ioat2_attrs,
 };
 
-int ioat2_dma_probe(struct ioatdma_device *device, int dca)
+int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca)
 {
         struct pci_dev *pdev = device->pdev;
         struct dma_device *dma;
diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h
index e100f644e34..a2c413b2b8d 100644
--- a/drivers/dma/ioat/dma_v2.h
+++ b/drivers/dma/ioat/dma_v2.h
@@ -74,7 +74,7 @@ static inline struct ioat2_dma_chan *to_ioat2_chan(struct dma_chan *c)
         return container_of(chan, struct ioat2_dma_chan, base);
 }
 
-static inline u32 ioat2_ring_size(struct ioat2_dma_chan *ioat)
+static inline u16 ioat2_ring_size(struct ioat2_dma_chan *ioat)
 {
         return 1 << ioat->alloc_order;
 }
@@ -91,7 +91,7 @@ static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat)
         return CIRC_CNT(ioat->head, ioat->issued, ioat2_ring_size(ioat));
 }
 
-static inline u32 ioat2_ring_space(struct ioat2_dma_chan *ioat)
+static inline u16 ioat2_ring_space(struct ioat2_dma_chan *ioat)
 {
         return ioat2_ring_size(ioat) - ioat2_ring_active(ioat);
 }
@@ -155,10 +155,10 @@ static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
                chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
 }
 
-int ioat2_dma_probe(struct ioatdma_device *dev, int dca);
-int ioat3_dma_probe(struct ioatdma_device *dev, int dca);
-struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
-struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
+int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca);
+int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca);
+struct dca_provider * __devinit ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
+struct dca_provider * __devinit ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
 int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs);
 int ioat2_enumerate_channels(struct ioatdma_device *device);
 struct dma_async_tx_descriptor *
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index e5fc944de1f..f519c93a61e 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -61,7 +61,6 @@
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/prefetch.h>
-#include "../dmaengine.h"
 #include "registers.h"
 #include "hw.h"
 #include "dma.h"
@@ -257,7 +256,7 @@ static bool desc_has_ext(struct ioat_ring_ent *desc)
  * The difference from the dma_v2.c __cleanup() is that this routine
  * handles extended descriptors and dma-unmapping raid operations.
  */
-static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
+static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 {
         struct ioat_chan_common *chan = &ioat->base;
         struct ioat_ring_ent *desc;
@@ -278,8 +277,9 @@ static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
                 dump_desc_dbg(ioat, desc);
                 tx = &desc->txd;
                 if (tx->cookie) {
-                        dma_cookie_complete(tx);
+                        chan->completed_cookie = tx->cookie;
                         ioat3_dma_unmap(ioat, desc, idx + i);
+                        tx->cookie = 0;
                         if (tx->callback) {
                                 tx->callback(tx->callback_param);
                                 tx->callback = NULL;
@@ -314,7 +314,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
 static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
 {
         struct ioat_chan_common *chan = &ioat->base;
-        dma_addr_t phys_complete;
+        unsigned long phys_complete;
 
         spin_lock_bh(&chan->cleanup_lock);
         if (ioat_cleanup_preamble(chan, &phys_complete))
@@ -333,7 +333,7 @@ static void ioat3_cleanup_event(unsigned long data)
 static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
 {
         struct ioat_chan_common *chan = &ioat->base;
-        dma_addr_t phys_complete;
+        unsigned long phys_complete;
 
         ioat2_quiesce(chan, 0);
         if (ioat_cleanup_preamble(chan, &phys_complete))
@@ -348,7 +348,7 @@ static void ioat3_timer_event(unsigned long data)
         struct ioat_chan_common *chan = &ioat->base;
 
         if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
-                dma_addr_t phys_complete;
+                unsigned long phys_complete;
                 u64 status;
 
                 status = ioat_chansts(chan);
@@ -411,15 +411,13 @@ ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie,
                 struct dma_tx_state *txstate)
 {
         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
-        enum dma_status ret;
 
-        ret = dma_cookie_status(c, cookie, txstate);
-        if (ret == DMA_SUCCESS)
-                return ret;
+        if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
+                return DMA_SUCCESS;
 
         ioat3_cleanup(ioat);
 
-        return dma_cookie_status(c, cookie, txstate);
+        return ioat_tx_status(c, cookie, txstate);
 }
 
 static struct dma_async_tx_descriptor *
@@ -836,7 +834,7 @@ ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags)
         return &desc->txd;
 }
 
-static void ioat3_dma_test_callback(void *dma_async_param)
+static void __devinit ioat3_dma_test_callback(void *dma_async_param)
 {
         struct completion *cmp = dma_async_param;
 
@@ -844,7 +842,7 @@ static void ioat3_dma_test_callback(void *dma_async_param)
 }
 
 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
-static int ioat_xor_val_self_test(struct ioatdma_device *device)
+static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device)
 {
         int i, src_idx;
         struct page *dest;
@@ -1096,7 +1094,7 @@ out:
         return err;
 }
 
-static int ioat3_dma_self_test(struct ioatdma_device *device)
+static int __devinit ioat3_dma_self_test(struct ioatdma_device *device)
 {
         int rc = ioat_dma_self_test(device);
 
@@ -1149,45 +1147,7 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan)
         return ioat2_reset_sync(chan, msecs_to_jiffies(200));
 }
 
-static bool is_jf_ioat(struct pci_dev *pdev)
-{
-        switch (pdev->device) {
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
-        case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
-                return true;
-        default:
-                return false;
-        }
-}
-
-static bool is_snb_ioat(struct pci_dev *pdev)
-{
-        switch (pdev->device) {
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
-        case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
-                return true;
-        default:
-                return false;
-        }
-}
-
-int ioat3_dma_probe(struct ioatdma_device *device, int dca)
+int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
 {
         struct pci_dev *pdev = device->pdev;
         int dca_en = system_has_dca_enabled(pdev);
@@ -1207,9 +1167,6 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca)
         dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
         dma->device_free_chan_resources = ioat2_free_chan_resources;
 
-        if (is_jf_ioat(pdev) || is_snb_ioat(pdev))
-                dma->copy_align = 6;
-
         dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
         dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock;
 
diff --git a/drivers/dma/ioat/hw.h b/drivers/dma/ioat/hw.h
index d2ff3fda0b1..60e675455b6 100644
--- a/drivers/dma/ioat/hw.h
+++ b/drivers/dma/ioat/hw.h
@@ -22,6 +22,7 @@
 #define _IOAT_HW_H_
 
 /* PCI Configuration Space Values */
+#define IOAT_PCI_VID            0x8086
 #define IOAT_MMIO_BAR           0
 
 /* CB device ID's */
@@ -30,6 +31,9 @@
 #define IOAT_PCI_DID_SCNB       0x65FF
 #define IOAT_PCI_DID_SNB        0x402F
 
+#define IOAT_PCI_RID            0x00
+#define IOAT_PCI_SVID           0x8086
+#define IOAT_PCI_SID            0x8086
 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c
index 4f686c527ab..5e3a40f7994 100644
--- a/drivers/dma/ioat/pci.c
+++ b/drivers/dma/ioat/pci.c
@@ -40,17 +40,6 @@ MODULE_VERSION(IOAT_DMA_VERSION);
 MODULE_LICENSE("Dual BSD/GPL");
 MODULE_AUTHOR("Intel Corporation");
 
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB0   0x0e20
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB1   0x0e21
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB2   0x0e22
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB3   0x0e23
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB4   0x0e24
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB5   0x0e25
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB6   0x0e26
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB7   0x0e27
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB8   0x0e2e
-#define PCI_DEVICE_ID_INTEL_IOAT_IVB9   0x0e2f
-
 static struct pci_device_id ioat_pci_tbl[] = {
         /* I/OAT v1 platforms */
         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT) },
@@ -94,23 +83,13 @@ static struct pci_device_id ioat_pci_tbl[] = {
         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
 
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
-        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
-
         { 0, }
 };
 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
 
-static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
-static void ioat_remove(struct pci_dev *pdev);
+static int __devinit ioat_pci_probe(struct pci_dev *pdev,
+                                    const struct pci_device_id *id);
+static void __devexit ioat_remove(struct pci_dev *pdev);
 
 static int ioat_dca_enabled = 1;
 module_param(ioat_dca_enabled, int, 0644);
@@ -124,7 +103,7 @@ static struct pci_driver ioat_pci_driver = {
         .name           = DRV_NAME,
         .id_table       = ioat_pci_tbl,
         .probe          = ioat_pci_probe,
-        .remove         = ioat_remove,
+        .remove         = __devexit_p(ioat_remove),
 };
 
 static struct ioatdma_device *
@@ -140,7 +119,7 @@ alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
         return d;
 }
 
-static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+static int __devinit ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
         void __iomem * const *iomap;
         struct device *dev = &pdev->dev;
@@ -194,7 +173,7 @@ static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
         return 0;
 }
 
-static void ioat_remove(struct pci_dev *pdev)
+static void __devexit ioat_remove(struct pci_dev *pdev)
 {
         struct ioatdma_device *device = pci_get_drvdata(pdev);
 
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index eacb8be9981..e03f811a83d 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -36,8 +36,6 @@
 
 #include <mach/adma.h>
 
-#include "dmaengine.h"
-
 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
 #define to_iop_adma_device(dev) \
         container_of(dev, struct iop_adma_device, common)
@@ -319,7 +317,7 @@ static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
         }
 
         if (cookie > 0) {
-                iop_chan->common.completed_cookie = cookie;
+                iop_chan->completed_cookie = cookie;
                 pr_debug("\tcompleted cookie %d\n", cookie);
         }
 }
@@ -440,6 +438,18 @@ retry:
         return NULL;
 }
 
+static dma_cookie_t
+iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
+        struct iop_adma_desc_slot *desc)
+{
+        dma_cookie_t cookie = iop_chan->common.cookie;
+        cookie++;
+        if (cookie < 0)
+                cookie = 1;
+        iop_chan->common.cookie = desc->async_tx.cookie = cookie;
+        return cookie;
+}
+
 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
 {
         dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
@@ -467,7 +477,7 @@ iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
         slots_per_op = grp_start->slots_per_op;
 
         spin_lock_bh(&iop_chan->lock);
-        cookie = dma_cookie_assign(tx);
+        cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
 
         old_chain_tail = list_entry(iop_chan->chain.prev,
                 struct iop_adma_desc_slot, chain_node);
@@ -894,15 +904,24 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
                                         struct dma_tx_state *txstate)
 {
         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
-        int ret;
-
-        ret = dma_cookie_status(chan, cookie, txstate);
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
+        enum dma_status ret;
+
+        last_used = chan->cookie;
+        last_complete = iop_chan->completed_cookie;
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
         if (ret == DMA_SUCCESS)
                 return ret;
 
         iop_adma_slot_cleanup(iop_chan);
 
-        return dma_cookie_status(chan, cookie, txstate);
+        last_used = chan->cookie;
+        last_complete = iop_chan->completed_cookie;
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+        return dma_async_is_complete(cookie, last_complete, last_used);
 }
 
 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
@@ -968,7 +987,7 @@ static void iop_adma_issue_pending(struct dma_chan *chan)
  */
 #define IOP_ADMA_TEST_SIZE 2000
 
-static int iop_adma_memcpy_self_test(struct iop_adma_device *device)
+static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
 {
         int i;
         void *src, *dest;
@@ -1042,7 +1061,7 @@ out:
 }
 
 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
-static int
+static int __devinit
 iop_adma_xor_val_self_test(struct iop_adma_device *device)
 {
         int i, src_idx;
@@ -1243,7 +1262,7 @@ out:
 }
 
 #ifdef CONFIG_RAID6_PQ
-static int
+static int __devinit
 iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
 {
         /* combined sources, software pq results, and extra hw pq results */
@@ -1252,8 +1271,8 @@ iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
         struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2];
         /* address conversion buffers (dma_map / page_address) */
         void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
-        dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2];
-        dma_addr_t *pq_dest = &pq_src[IOP_ADMA_NUM_SRC_TEST];
+        dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST];
+        dma_addr_t pq_dest[2];
 
         int i;
         struct dma_async_tx_descriptor *tx;
@@ -1406,7 +1425,7 @@ out:
 }
 #endif
 
-static int iop_adma_remove(struct platform_device *dev)
+static int __devexit iop_adma_remove(struct platform_device *dev)
 {
         struct iop_adma_device *device = platform_get_drvdata(dev);
         struct dma_chan *chan, *_chan;
@@ -1429,7 +1448,7 @@ static int iop_adma_remove(struct platform_device *dev)
         return 0;
 }
 
-static int iop_adma_probe(struct platform_device *pdev)
+static int __devinit iop_adma_probe(struct platform_device *pdev)
 {
         struct resource *res;
         int ret = 0, i;
@@ -1463,7 +1482,7 @@ static int iop_adma_probe(struct platform_device *pdev)
                 goto err_free_adev;
         }
 
-        dev_dbg(&pdev->dev, "%s: allocated descriptor pool virt %p phys %p\n",
+        dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
                 __func__, adev->dma_desc_pool_virt,
                 (void *) adev->dma_desc_pool);
 
@@ -1546,7 +1565,6 @@ static int iop_adma_probe(struct platform_device *pdev)
         INIT_LIST_HEAD(&iop_chan->chain);
         INIT_LIST_HEAD(&iop_chan->all_slots);
         iop_chan->common.device = dma_dev;
-        dma_cookie_init(&iop_chan->common);
         list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
 
         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
@@ -1624,12 +1642,16 @@ static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
                 iop_desc_set_memcpy_src_addr(grp_start, 0);
 
-                cookie = dma_cookie_assign(&sw_desc->async_tx);
+                cookie = iop_chan->common.cookie;
+                cookie++;
+                if (cookie <= 1)
+                        cookie = 2;
 
                 /* initialize the completed cookie to be less than
                  * the most recently used cookie
                  */
-                iop_chan->common.completed_cookie = cookie - 1;
+                iop_chan->completed_cookie = cookie - 1;
+                iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
                 /* channel should not be busy */
                 BUG_ON(iop_chan_is_busy(iop_chan));
@@ -1677,12 +1699,16 @@ static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
                 iop_desc_set_xor_src_addr(grp_start, 0, 0);
                 iop_desc_set_xor_src_addr(grp_start, 1, 0);
 
-                cookie = dma_cookie_assign(&sw_desc->async_tx);
+                cookie = iop_chan->common.cookie;
+                cookie++;
+                if (cookie <= 1)
+                        cookie = 2;
 
                 /* initialize the completed cookie to be less than
                  * the most recently used cookie
                  */
-                iop_chan->common.completed_cookie = cookie - 1;
+                iop_chan->completed_cookie = cookie - 1;
+                iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
                 /* channel should not be busy */
                 BUG_ON(iop_chan_is_busy(iop_chan));
@@ -1709,18 +1735,30 @@ static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
         spin_unlock_bh(&iop_chan->lock);
 }
 
+MODULE_ALIAS("platform:iop-adma");
+
 static struct platform_driver iop_adma_driver = {
         .probe          = iop_adma_probe,
-        .remove         = iop_adma_remove,
+        .remove         = __devexit_p(iop_adma_remove),
         .driver         = {
                 .owner  = THIS_MODULE,
                 .name   = "iop-adma",
         },
 };
 
-module_platform_driver(iop_adma_driver);
+static int __init iop_adma_init (void)
+{
+        return platform_driver_register(&iop_adma_driver);
+}
+
+static void __exit iop_adma_exit (void)
+{
+        platform_driver_unregister(&iop_adma_driver);
+        return;
+}
+module_exit(iop_adma_exit);
+module_init(iop_adma_init);
 
 MODULE_AUTHOR("Intel Corporation");
 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:iop-adma");
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 65855373cee..6815905a772 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -21,10 +21,9 @@
 #include <linux/string.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <linux/module.h>
-#include <linux/dma/ipu-dma.h>
 
-#include "../dmaengine.h"
+#include <mach/ipu.h>
+
 #include "ipu_intern.h"
 
 #define FS_VF_IN_VALID  0x00000002
@@ -312,7 +311,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
         case IPU_PIX_FMT_RGB565:
                 params->ip.bpp  = 2;
                 params->ip.pfs  = 4;
-                params->ip.npb  = 15;
+                params->ip.npb  = 7;
                 params->ip.sat  = 2;            /* SAT = 32-bit access */
                 params->ip.ofs0 = 0;            /* Red bit offset */
                 params->ip.ofs1 = 5;            /* Green bit offset */
@@ -422,6 +421,12 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
         params->pp.nsb = 1;
 }
 
+static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
+                                        uint16_t burst_pixels)
+{
+        params->pp.npb = burst_pixels - 1;
+}
+
 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
                                     dma_addr_t buf0, dma_addr_t buf1)
 {
@@ -684,6 +689,23 @@ static int ipu_init_channel_buffer(struct idmac_channel *ichan,
         ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
         ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
         ipu_ch_param_set_rotation(&params, rot_mode);
+        /* Some channels (rotation) have restriction on burst length */
+        switch (channel) {
+        case IDMAC_IC_7:        /* Hangs with burst 8, 16, other values
+                                   invalid - Table 44-30 */
+/*
+                ipu_ch_param_set_burst_size(&params, 8);
+ */
+                break;
+        case IDMAC_SDC_0:
+        case IDMAC_SDC_1:
+                /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
+                ipu_ch_param_set_burst_size(&params, 16);
+                break;
+        case IDMAC_IC_0:
+        default:
+                break;
+        }
 
         spin_lock_irqsave(&ipu->lock, flags);
 
@@ -866,7 +888,14 @@ static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
 
         dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
 
-        cookie = dma_cookie_assign(tx);
+        cookie = ichan->dma_chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        /* from dmaengine.h: "last cookie value returned to client" */
+        ichan->dma_chan.cookie = cookie;
+        tx->cookie = cookie;
 
         /* ipu->lock can be taken under ichan->lock, but not v.v. */
         spin_lock_irqsave(&ichan->lock, flags);
@@ -1278,7 +1307,6 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
             ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
                 callback = descnew->txd.callback;
                 callback_param = descnew->txd.callback_param;
-                list_del_init(&descnew->list);
                 spin_unlock(&ichan->lock);
                 if (callback)
                         callback(callback_param);
@@ -1288,7 +1316,7 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
         /* Flip the active buffer - even if update above failed */
         ichan->active_buffer = !ichan->active_buffer;
         if (done)
-                dma_cookie_complete(&desc->txd);
+                ichan->completed = desc->txd.cookie;
 
         callback = desc->txd.callback;
         callback_param = desc->txd.callback_param;
@@ -1334,8 +1362,7 @@ static void ipu_gc_tasklet(unsigned long arg)
 /* Allocate and initialise a transfer descriptor. */
 static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
                 struct scatterlist *sgl, unsigned int sg_len,
-                enum dma_transfer_direction direction, unsigned long tx_flags,
-                void *context)
+                enum dma_data_direction direction, unsigned long tx_flags)
 {
         struct idmac_channel *ichan = to_idmac_chan(chan);
         struct idmac_tx_desc *desc = NULL;
@@ -1347,7 +1374,7 @@ static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan
             chan->chan_id != IDMAC_IC_7)
                 return NULL;
 
-        if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) {
+        if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
                 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
                 return NULL;
         }
@@ -1401,58 +1428,39 @@ static int __idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
         struct idmac_channel *ichan = to_idmac_chan(chan);
         struct idmac *idmac = to_idmac(chan->device);
-        struct ipu *ipu = to_ipu(idmac);
-        struct list_head *list, *tmp;
         unsigned long flags;
         int i;
 
-        switch (cmd) {
-        case DMA_PAUSE:
-                spin_lock_irqsave(&ipu->lock, flags);
-                ipu_ic_disable_task(ipu, chan->chan_id);
-
-                /* Return all descriptors into "prepared" state */
-                list_for_each_safe(list, tmp, &ichan->queue)
-                        list_del_init(list);
+        /* Only supports DMA_TERMINATE_ALL */
+        if (cmd != DMA_TERMINATE_ALL)
+                return -ENXIO;
 
-                ichan->sg[0] = NULL;
-                ichan->sg[1] = NULL;
+        ipu_disable_channel(idmac, ichan,
+                            ichan->status >= IPU_CHANNEL_ENABLED);
 
-                spin_unlock_irqrestore(&ipu->lock, flags);
-
-                ichan->status = IPU_CHANNEL_INITIALIZED;
-                break;
-        case DMA_TERMINATE_ALL:
-                ipu_disable_channel(idmac, ichan,
-                                    ichan->status >= IPU_CHANNEL_ENABLED);
-
-                tasklet_disable(&ipu->tasklet);
+        tasklet_disable(&to_ipu(idmac)->tasklet);
 
-                /* ichan->queue is modified in ISR, have to spinlock */
-                spin_lock_irqsave(&ichan->lock, flags);
-                list_splice_init(&ichan->queue, &ichan->free_list);
+        /* ichan->queue is modified in ISR, have to spinlock */
+        spin_lock_irqsave(&ichan->lock, flags);
+        list_splice_init(&ichan->queue, &ichan->free_list);
 
-                if (ichan->desc)
-                        for (i = 0; i < ichan->n_tx_desc; i++) {
-                                struct idmac_tx_desc *desc = ichan->desc + i;
-                                if (list_empty(&desc->list))
-                                        /* Descriptor was prepared, but not submitted */
-                                        list_add(&desc->list, &ichan->free_list);
+        if (ichan->desc)
+                for (i = 0; i < ichan->n_tx_desc; i++) {
+                        struct idmac_tx_desc *desc = ichan->desc + i;
+                        if (list_empty(&desc->list))
+                                /* Descriptor was prepared, but not submitted */
+                                list_add(&desc->list, &ichan->free_list);
 
-                                async_tx_clear_ack(&desc->txd);
-                        }
+                        async_tx_clear_ack(&desc->txd);
+                }
 
-                ichan->sg[0] = NULL;
-                ichan->sg[1] = NULL;
-                spin_unlock_irqrestore(&ichan->lock, flags);
+        ichan->sg[0] = NULL;
+        ichan->sg[1] = NULL;
+        spin_unlock_irqrestore(&ichan->lock, flags);
 
-                tasklet_enable(&ipu->tasklet);
+        tasklet_enable(&to_ipu(idmac)->tasklet);
 
-                ichan->status = IPU_CHANNEL_INITIALIZED;
-                break;
-        default:
-                return -ENOSYS;
-        }
+        ichan->status = IPU_CHANNEL_INITIALIZED;
 
         return 0;
 }
@@ -1504,7 +1512,8 @@ static int idmac_alloc_chan_resources(struct dma_chan *chan)
         BUG_ON(chan->client_count > 1);
         WARN_ON(ichan->status != IPU_CHANNEL_FREE);
 
-        dma_cookie_init(chan);
+        chan->cookie            = 1;
+        ichan->completed        = -ENXIO;
 
         ret = ipu_irq_map(chan->chan_id);
         if (ret < 0)
@@ -1593,7 +1602,9 @@ static void idmac_free_chan_resources(struct dma_chan *chan)
 static enum dma_status idmac_tx_status(struct dma_chan *chan,
                        dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
-        dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 0);
+        struct idmac_channel *ichan = to_idmac_chan(chan);
+
+        dma_set_tx_state(txstate, ichan->completed, chan->cookie, 0);
         if (cookie != chan->cookie)
                 return DMA_ERROR;
         return DMA_SUCCESS;
@@ -1629,10 +1640,11 @@ static int __init ipu_idmac_init(struct ipu *ipu)
 
                 ichan->status           = IPU_CHANNEL_FREE;
                 ichan->sec_chan_en      = false;
+                ichan->completed        = -ENXIO;
                 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
 
                 dma_chan->device        = &idmac->dma;
-                dma_cookie_init(dma_chan);
+                dma_chan->cookie        = 1;
                 dma_chan->chan_id       = i;
                 list_add_tail(&dma_chan->device_node, &dma->channels);
         }
@@ -1651,6 +1663,7 @@ static void __exit ipu_idmac_exit(struct ipu *ipu)
                 struct idmac_channel *ichan = ipu->channel + i;
 
                 idmac_control(&ichan->dma_chan, DMA_TERMINATE_ALL, 0);
+                idmac_prep_slave_sg(&ichan->dma_chan, NULL, 0, DMA_NONE, 0);
         }
 
         dma_async_device_unregister(&idmac->dma);
@@ -1662,6 +1675,7 @@ static void __exit ipu_idmac_exit(struct ipu *ipu)
 
 static int __init ipu_probe(struct platform_device *pdev)
 {
+        struct ipu_platform_data *pdata = pdev->dev.platform_data;
         struct resource *mem_ipu, *mem_ic;
         int ret;
 
@@ -1669,7 +1683,7 @@ static int __init ipu_probe(struct platform_device *pdev)
 
         mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         mem_ic  = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        if (!mem_ipu || !mem_ic)
+        if (!pdata || !mem_ipu || !mem_ic)
                 return -EINVAL;
 
         ipu_data.dev = &pdev->dev;
@@ -1686,9 +1700,10 @@ static int __init ipu_probe(struct platform_device *pdev)
                 goto err_noirq;
 
         ipu_data.irq_err = ret;
+        ipu_data.irq_base = pdata->irq_base;
 
-        dev_dbg(&pdev->dev, "fn irq %u, err irq %u\n",
-                ipu_data.irq_fn, ipu_data.irq_err);
+        dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
+                ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
 
         /* Remap IPU common registers */
         ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
@@ -1712,7 +1727,7 @@ static int __init ipu_probe(struct platform_device *pdev)
         }
 
         /* Make sure IPU HSP clock is running */
-        clk_prepare_enable(ipu_data.ipu_clk);
+        clk_enable(ipu_data.ipu_clk);
 
         /* Disable all interrupts */
         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
@@ -1744,7 +1759,7 @@ static int __init ipu_probe(struct platform_device *pdev)
 err_idmac_init:
 err_attach_irq:
         ipu_irq_detach_irq(&ipu_data, pdev);
-        clk_disable_unprepare(ipu_data.ipu_clk);
+        clk_disable(ipu_data.ipu_clk);
         clk_put(ipu_data.ipu_clk);
 err_clk_get:
         iounmap(ipu_data.reg_ic);
@@ -1762,7 +1777,7 @@ static int __exit ipu_remove(struct platform_device *pdev)
 
         ipu_idmac_exit(ipu);
         ipu_irq_detach_irq(ipu, pdev);
-        clk_disable_unprepare(ipu->ipu_clk);
+        clk_disable(ipu->ipu_clk);
         clk_put(ipu->ipu_clk);
         iounmap(ipu->reg_ic);
         iounmap(ipu->reg_ipu);
diff --git a/drivers/dma/ipu/ipu_irq.c b/drivers/dma/ipu/ipu_irq.c
index a5ee37d5320..ab8a4eff072 100644
--- a/drivers/dma/ipu/ipu_irq.c
+++ b/drivers/dma/ipu/ipu_irq.c
@@ -14,8 +14,8 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <linux/module.h>
-#include <linux/dma/ipu-dma.h>
+
+#include <mach/ipu.h>
 
 #include "ipu_intern.h"
 
@@ -81,7 +81,7 @@ static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
 /* Protects allocations from the above array of maps */
 static DEFINE_MUTEX(map_lock);
 /* Protects register accesses and individual mappings */
-static DEFINE_RAW_SPINLOCK(bank_lock);
+static DEFINE_SPINLOCK(bank_lock);
 
 static struct ipu_irq_map *src2map(unsigned int src)
 {
@@ -101,11 +101,11 @@ static void ipu_irq_unmask(struct irq_data *d)
         uint32_t reg;
         unsigned long lock_flags;
 
-        raw_spin_lock_irqsave(&bank_lock, lock_flags);
+        spin_lock_irqsave(&bank_lock, lock_flags);
 
         bank = map->bank;
         if (!bank) {
-                raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+                spin_unlock_irqrestore(&bank_lock, lock_flags);
                 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
                 return;
         }
@@ -114,7 +114,7 @@ static void ipu_irq_unmask(struct irq_data *d)
         reg |= (1UL << (map->source & 31));
         ipu_write_reg(bank->ipu, reg, bank->control);
 
-        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+        spin_unlock_irqrestore(&bank_lock, lock_flags);
 }
 
 static void ipu_irq_mask(struct irq_data *d)
@@ -124,11 +124,11 @@ static void ipu_irq_mask(struct irq_data *d)
         uint32_t reg;
         unsigned long lock_flags;
 
-        raw_spin_lock_irqsave(&bank_lock, lock_flags);
+        spin_lock_irqsave(&bank_lock, lock_flags);
 
         bank = map->bank;
         if (!bank) {
-                raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+                spin_unlock_irqrestore(&bank_lock, lock_flags);
                 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
                 return;
         }
@@ -137,7 +137,7 @@ static void ipu_irq_mask(struct irq_data *d)
         reg &= ~(1UL << (map->source & 31));
         ipu_write_reg(bank->ipu, reg, bank->control);
 
-        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+        spin_unlock_irqrestore(&bank_lock, lock_flags);
 }
 
 static void ipu_irq_ack(struct irq_data *d)
@@ -146,17 +146,17 @@ static void ipu_irq_ack(struct irq_data *d)
         struct ipu_irq_bank *bank;
         unsigned long lock_flags;
 
-        raw_spin_lock_irqsave(&bank_lock, lock_flags);
+        spin_lock_irqsave(&bank_lock, lock_flags);
 
         bank = map->bank;
         if (!bank) {
-                raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+                spin_unlock_irqrestore(&bank_lock, lock_flags);
                 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
                 return;
         }
 
         ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
-        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+        spin_unlock_irqrestore(&bank_lock, lock_flags);
 }
 
 /**
@@ -172,11 +172,11 @@ bool ipu_irq_status(unsigned int irq)
         unsigned long lock_flags;
         bool ret;
 
-        raw_spin_lock_irqsave(&bank_lock, lock_flags);
+        spin_lock_irqsave(&bank_lock, lock_flags);
         bank = map->bank;
         ret = bank && ipu_read_reg(bank->ipu, bank->status) &
                 (1UL << (map->source & 31));
-        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+        spin_unlock_irqrestore(&bank_lock, lock_flags);
 
         return ret;
 }
@@ -213,10 +213,10 @@ int ipu_irq_map(unsigned int source)
                 if (irq_map[i].source < 0) {
                         unsigned long lock_flags;
 
-                        raw_spin_lock_irqsave(&bank_lock, lock_flags);
+                        spin_lock_irqsave(&bank_lock, lock_flags);
                         irq_map[i].source = source;
                         irq_map[i].bank = irq_bank + source / 32;
-                        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+                        spin_unlock_irqrestore(&bank_lock, lock_flags);
 
                         ret = irq_map[i].irq;
                         pr_debug("IPU: mapped source %u to IRQ %u\n",
@@ -252,10 +252,10 @@ int ipu_irq_unmap(unsigned int source)
                         pr_debug("IPU: unmapped source %u from IRQ %u\n",
                                  source, irq_map[i].irq);
 
-                        raw_spin_lock_irqsave(&bank_lock, lock_flags);
+                        spin_lock_irqsave(&bank_lock, lock_flags);
                         irq_map[i].source = -EINVAL;
                         irq_map[i].bank = NULL;
-                        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
+                        spin_unlock_irqrestore(&bank_lock, lock_flags);
 
                         ret = 0;
                         break;
@@ -276,7 +276,7 @@ static void ipu_irq_err(unsigned int irq, struct irq_desc *desc)
         for (i = IPU_IRQ_NR_FN_BANKS; i < IPU_IRQ_NR_BANKS; i++) {
                 struct ipu_irq_bank *bank = irq_bank + i;
 
-                raw_spin_lock(&bank_lock);
+                spin_lock(&bank_lock);
                 status = ipu_read_reg(ipu, bank->status);
                 /*
                  * Don't think we have to clear all interrupts here, they will
@@ -284,18 +284,18 @@ static void ipu_irq_err(unsigned int irq, struct irq_desc *desc)
                  * might want to clear unhandled interrupts after the loop...
                  */
                 status &= ipu_read_reg(ipu, bank->control);
-                raw_spin_unlock(&bank_lock);
+                spin_unlock(&bank_lock);
                 while ((line = ffs(status))) {
                         struct ipu_irq_map *map;
 
                         line--;
                         status &= ~(1UL << line);
 
-                        raw_spin_lock(&bank_lock);
+                        spin_lock(&bank_lock);
                         map = src2map(32 * i + line);
                         if (map)
                                 irq = map->irq;
-                        raw_spin_unlock(&bank_lock);
+                        spin_unlock(&bank_lock);
 
                         if (!map) {
                                 pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
@@ -317,22 +317,22 @@ static void ipu_irq_fn(unsigned int irq, struct irq_desc *desc)
         for (i = 0; i < IPU_IRQ_NR_FN_BANKS; i++) {
                 struct ipu_irq_bank *bank = irq_bank + i;
 
-                raw_spin_lock(&bank_lock);
+                spin_lock(&bank_lock);
                 status = ipu_read_reg(ipu, bank->status);
                 /* Not clearing all interrupts, see above */
                 status &= ipu_read_reg(ipu, bank->control);
-                raw_spin_unlock(&bank_lock);
+                spin_unlock(&bank_lock);
                 while ((line = ffs(status))) {
                         struct ipu_irq_map *map;
 
                         line--;
                         status &= ~(1UL << line);
 
-                        raw_spin_lock(&bank_lock);
+                        spin_lock(&bank_lock);
                         map = src2map(32 * i + line);
                         if (map)
                                 irq = map->irq;
-                        raw_spin_unlock(&bank_lock);
+                        spin_unlock(&bank_lock);
 
                         if (!map) {
                                 pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
@@ -354,12 +354,10 @@ static struct irq_chip ipu_irq_chip = {
 /* Install the IRQ handler */
 int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
 {
-        unsigned int irq, i;
-        int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
-                                       numa_node_id());
+        struct ipu_platform_data *pdata = dev->dev.platform_data;
+        unsigned int irq, irq_base, i;
 
-        if (irq_base < 0)
-                return irq_base;
+        irq_base = pdata->irq_base;
 
         for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
                 irq_bank[i].ipu = ipu;
@@ -389,16 +387,15 @@ int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
         irq_set_handler_data(ipu->irq_err, ipu);
         irq_set_chained_handler(ipu->irq_err, ipu_irq_err);
 
-        ipu->irq_base = irq_base;
-
         return 0;
 }
 
 void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
 {
+        struct ipu_platform_data *pdata = dev->dev.platform_data;
         unsigned int irq, irq_base;
 
-        irq_base = ipu->irq_base;
+        irq_base = pdata->irq_base;
 
         irq_set_chained_handler(ipu->irq_fn, NULL);
         irq_set_handler_data(ipu->irq_fn, NULL);
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
deleted file mode 100644
index c6d98c00f05..00000000000
--- a/drivers/dma/mmp_pdma.c
+++ /dev/null
@@ -1,875 +0,0 @@
-/*
- * Copyright 2012 Marvell International Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-#include <linux/dmaengine.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/platform_data/mmp_dma.h>
-#include <linux/dmapool.h>
-#include <linux/of_device.h>
-#include <linux/of.h>
-
-#include "dmaengine.h"
-
-#define DCSR            0x0000
-#define DALGN           0x00a0
-#define DINT            0x00f0
-#define DDADR           0x0200
-#define DSADR           0x0204
-#define DTADR           0x0208
-#define DCMD            0x020c
-
-#define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
-#define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
-#define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
-#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
-#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
-#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
-#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
-#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
-
-#define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
-#define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
-#define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
-#define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
-#define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
-#define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
-
-#define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
-#define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
-
-#define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
-#define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
-
-#define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
-#define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
-#define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
-#define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
-#define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
-#define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
-#define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
-#define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
-#define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
-#define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
-#define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
-#define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
-#define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
-#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
-
-#define PDMA_ALIGNMENT          3
-#define PDMA_MAX_DESC_BYTES     0x1000
-
-struct mmp_pdma_desc_hw {
-        u32 ddadr;      /* Points to the next descriptor + flags */
-        u32 dsadr;      /* DSADR value for the current transfer */
-        u32 dtadr;      /* DTADR value for the current transfer */
-        u32 dcmd;       /* DCMD value for the current transfer */
-} __aligned(32);
-
-struct mmp_pdma_desc_sw {
-        struct mmp_pdma_desc_hw desc;
-        struct list_head node;
-        struct list_head tx_list;
-        struct dma_async_tx_descriptor async_tx;
-};
-
-struct mmp_pdma_phy;
-
-struct mmp_pdma_chan {
-        struct device *dev;
-        struct dma_chan chan;
-        struct dma_async_tx_descriptor desc;
-        struct mmp_pdma_phy *phy;
-        enum dma_transfer_direction dir;
-
-        /* channel's basic info */
-        struct tasklet_struct tasklet;
-        u32 dcmd;
-        u32 drcmr;
-        u32 dev_addr;
-
-        /* list for desc */
-        spinlock_t desc_lock;           /* Descriptor list lock */
-        struct list_head chain_pending; /* Link descriptors queue for pending */
-        struct list_head chain_running; /* Link descriptors queue for running */
-        bool idle;                      /* channel statue machine */
-
-        struct dma_pool *desc_pool;     /* Descriptors pool */
-};
-
-struct mmp_pdma_phy {
-        int idx;
-        void __iomem *base;
-        struct mmp_pdma_chan *vchan;
-};
-
-struct mmp_pdma_device {
-        int                             dma_channels;
-        void __iomem                    *base;
-        struct device                   *dev;
-        struct dma_device               device;
-        struct mmp_pdma_phy             *phy;
-};
-
-#define tx_to_mmp_pdma_desc(tx) container_of(tx, struct mmp_pdma_desc_sw, async_tx)
-#define to_mmp_pdma_desc(lh) container_of(lh, struct mmp_pdma_desc_sw, node)
-#define to_mmp_pdma_chan(dchan) container_of(dchan, struct mmp_pdma_chan, chan)
-#define to_mmp_pdma_dev(dmadev) container_of(dmadev, struct mmp_pdma_device, device)
-
-static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
-{
-        u32 reg = (phy->idx << 4) + DDADR;
-
-        writel(addr, phy->base + reg);
-}
-
-static void enable_chan(struct mmp_pdma_phy *phy)
-{
-        u32 reg;
-
-        if (!phy->vchan)
-                return;
-
-        reg = phy->vchan->drcmr;
-        reg = (((reg) < 64) ? 0x0100 : 0x1100) + (((reg) & 0x3f) << 2);
-        writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
-
-        reg = (phy->idx << 2) + DCSR;
-        writel(readl(phy->base + reg) | DCSR_RUN,
-                                        phy->base + reg);
-}
-
-static void disable_chan(struct mmp_pdma_phy *phy)
-{
-        u32 reg;
-
-        if (phy) {
-                reg = (phy->idx << 2) + DCSR;
-                writel(readl(phy->base + reg) & ~DCSR_RUN,
-                                                phy->base + reg);
-        }
-}
-
-static int clear_chan_irq(struct mmp_pdma_phy *phy)
-{
-        u32 dcsr;
-        u32 dint = readl(phy->base + DINT);
-        u32 reg = (phy->idx << 2) + DCSR;
-
-        if (dint & BIT(phy->idx)) {
-                /* clear irq */
-                dcsr = readl(phy->base + reg);
-                writel(dcsr, phy->base + reg);
-                if ((dcsr & DCSR_BUSERR) && (phy->vchan))
-                        dev_warn(phy->vchan->dev, "DCSR_BUSERR\n");
-                return 0;
-        }
-        return -EAGAIN;
-}
-
-static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id)
-{
-        struct mmp_pdma_phy *phy = dev_id;
-
-        if (clear_chan_irq(phy) == 0) {
-                tasklet_schedule(&phy->vchan->tasklet);
-                return IRQ_HANDLED;
-        } else
-                return IRQ_NONE;
-}
-
-static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id)
-{
-        struct mmp_pdma_device *pdev = dev_id;
-        struct mmp_pdma_phy *phy;
-        u32 dint = readl(pdev->base + DINT);
-        int i, ret;
-        int irq_num = 0;
-
-        while (dint) {
-                i = __ffs(dint);
-                dint &= (dint - 1);
-                phy = &pdev->phy[i];
-                ret = mmp_pdma_chan_handler(irq, phy);
-                if (ret == IRQ_HANDLED)
-                        irq_num++;
-        }
-
-        if (irq_num)
-                return IRQ_HANDLED;
-        else
-                return IRQ_NONE;
-}
-
-/* lookup free phy channel as descending priority */
-static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan)
-{
-        int prio, i;
-        struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device);
-        struct mmp_pdma_phy *phy;
-
-        /*
-         * dma channel priorities
-         * ch 0 - 3,  16 - 19  <--> (0)
-         * ch 4 - 7,  20 - 23  <--> (1)
-         * ch 8 - 11, 24 - 27  <--> (2)
-         * ch 12 - 15, 28 - 31  <--> (3)
-         */
-        for (prio = 0; prio <= (((pdev->dma_channels - 1) & 0xf) >> 2); prio++) {
-                for (i = 0; i < pdev->dma_channels; i++) {
-                        if (prio != ((i & 0xf) >> 2))
-                                continue;
-                        phy = &pdev->phy[i];
-                        if (!phy->vchan) {
-                                phy->vchan = pchan;
-                                return phy;
-                        }
-                }
-        }
-
-        return NULL;
-}
-
-/* desc->tx_list ==> pending list */
-static void append_pending_queue(struct mmp_pdma_chan *chan,
-                                        struct mmp_pdma_desc_sw *desc)
-{
-        struct mmp_pdma_desc_sw *tail =
-                                to_mmp_pdma_desc(chan->chain_pending.prev);
-
-        if (list_empty(&chan->chain_pending))
-                goto out_splice;
-
-        /* one irq per queue, even appended */
-        tail->desc.ddadr = desc->async_tx.phys;
-        tail->desc.dcmd &= ~DCMD_ENDIRQEN;
-
-        /* softly link to pending list */
-out_splice:
-        list_splice_tail_init(&desc->tx_list, &chan->chain_pending);
-}
-
-/**
- * start_pending_queue - transfer any pending transactions
- * pending list ==> running list
- */
-static void start_pending_queue(struct mmp_pdma_chan *chan)
-{
-        struct mmp_pdma_desc_sw *desc;
-
-        /* still in running, irq will start the pending list */
-        if (!chan->idle) {
-                dev_dbg(chan->dev, "DMA controller still busy\n");
-                return;
-        }
-
-        if (list_empty(&chan->chain_pending)) {
-                /* chance to re-fetch phy channel with higher prio */
-                if (chan->phy) {
-                        chan->phy->vchan = NULL;
-                        chan->phy = NULL;
-                }
-                dev_dbg(chan->dev, "no pending list\n");
-                return;
-        }
-
-        if (!chan->phy) {
-                chan->phy = lookup_phy(chan);
-                if (!chan->phy) {
-                        dev_dbg(chan->dev, "no free dma channel\n");
-                        return;
-                }
-        }
-
-        /*
-         * pending -> running
-         * reintilize pending list
-         */
-        desc = list_first_entry(&chan->chain_pending,
-                                struct mmp_pdma_desc_sw, node);
-        list_splice_tail_init(&chan->chain_pending, &chan->chain_running);
-
-        /*
-         * Program the descriptor's address into the DMA controller,
-         * then start the DMA transaction
-         */
-        set_desc(chan->phy, desc->async_tx.phys);
-        enable_chan(chan->phy);
-        chan->idle = false;
-}
-
-
-/* desc->tx_list ==> pending list */
-static dma_cookie_t mmp_pdma_tx_submit(struct dma_async_tx_descriptor *tx)
-{
-        struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan);
-        struct mmp_pdma_desc_sw *desc = tx_to_mmp_pdma_desc(tx);
-        struct mmp_pdma_desc_sw *child;
-        unsigned long flags;
-        dma_cookie_t cookie = -EBUSY;
-
-        spin_lock_irqsave(&chan->desc_lock, flags);
-
-        list_for_each_entry(child, &desc->tx_list, node) {
-                cookie = dma_cookie_assign(&child->async_tx);
-        }
-
-        append_pending_queue(chan, desc);
-
-        spin_unlock_irqrestore(&chan->desc_lock, flags);
-
-        return cookie;
-}
-
-struct mmp_pdma_desc_sw *mmp_pdma_alloc_descriptor(struct mmp_pdma_chan *chan)
-{
-        struct mmp_pdma_desc_sw *desc;
-        dma_addr_t pdesc;
-
-        desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
-        if (!desc) {
-                dev_err(chan->dev, "out of memory for link descriptor\n");
-                return NULL;
-        }
-
-        memset(desc, 0, sizeof(*desc));
-        INIT_LIST_HEAD(&desc->tx_list);
-        dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
-        /* each desc has submit */
-        desc->async_tx.tx_submit = mmp_pdma_tx_submit;
-        desc->async_tx.phys = pdesc;
-
-        return desc;
-}
-
-/**
- * mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel.
- *
- * This function will create a dma pool for descriptor allocation.
- * Request irq only when channel is requested
- * Return - The number of allocated descriptors.
- */
-
-static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan)
-{
-        struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
-
-        if (chan->desc_pool)
-                return 1;
-
-        chan->desc_pool =
-                dma_pool_create(dev_name(&dchan->dev->device), chan->dev,
-                                  sizeof(struct mmp_pdma_desc_sw),
-                                  __alignof__(struct mmp_pdma_desc_sw), 0);
-        if (!chan->desc_pool) {
-                dev_err(chan->dev, "unable to allocate descriptor pool\n");
-                return -ENOMEM;
-        }
-        if (chan->phy) {
-                chan->phy->vchan = NULL;
-                chan->phy = NULL;
-        }
-        chan->idle = true;
-        chan->dev_addr = 0;
-        return 1;
-}
-
-static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan,
-                                  struct list_head *list)
-{
-        struct mmp_pdma_desc_sw *desc, *_desc;
-
-        list_for_each_entry_safe(desc, _desc, list, node) {
-                list_del(&desc->node);
-                dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
-        }
-}
-
-static void mmp_pdma_free_chan_resources(struct dma_chan *dchan)
-{
-        struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
-        unsigned long flags;
-
-        spin_lock_irqsave(&chan->desc_lock, flags);
-        mmp_pdma_free_desc_list(chan, &chan->chain_pending);
-        mmp_pdma_free_desc_list(chan, &chan->chain_running);
-        spin_unlock_irqrestore(&chan->desc_lock, flags);
-
-        dma_pool_destroy(chan->desc_pool);
-        chan->desc_pool = NULL;
-        chan->idle = true;
-        chan->dev_addr = 0;
-        if (chan->phy) {
-                chan->phy->vchan = NULL;
-                chan->phy = NULL;
-        }
-        return;
-}
-
-static struct dma_async_tx_descriptor *
-mmp_pdma_prep_memcpy(struct dma_chan *dchan,
-        dma_addr_t dma_dst, dma_addr_t dma_src,
-        size_t len, unsigned long flags)
-{
-        struct mmp_pdma_chan *chan;
-        struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
-        size_t copy = 0;
-
-        if (!dchan)
-                return NULL;
-
-        if (!len)
-                return NULL;
-
-        chan = to_mmp_pdma_chan(dchan);
-
-        if (!chan->dir) {
-                chan->dir = DMA_MEM_TO_MEM;
-                chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR;
-                chan->dcmd |= DCMD_BURST32;
-        }
-
-        do {
-                /* Allocate the link descriptor from DMA pool */
-                new = mmp_pdma_alloc_descriptor(chan);
-                if (!new) {
-                        dev_err(chan->dev, "no memory for desc\n");
-                        goto fail;
-                }
-
-                copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
-
-                new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy);
-                new->desc.dsadr = dma_src;
-                new->desc.dtadr = dma_dst;
-
-                if (!first)
-                        first = new;
-                else
-                        prev->desc.ddadr = new->async_tx.phys;
-
-                new->async_tx.cookie = 0;
-                async_tx_ack(&new->async_tx);
-
-                prev = new;
-                len -= copy;
-
-                if (chan->dir == DMA_MEM_TO_DEV) {
-                        dma_src += copy;
-                } else if (chan->dir == DMA_DEV_TO_MEM) {
-                        dma_dst += copy;
-                } else if (chan->dir == DMA_MEM_TO_MEM) {
-                        dma_src += copy;
-                        dma_dst += copy;
-                }
-
-                /* Insert the link descriptor to the LD ring */
-                list_add_tail(&new->node, &first->tx_list);
-        } while (len);
-
-        first->async_tx.flags = flags; /* client is in control of this ack */
-        first->async_tx.cookie = -EBUSY;
-
-        /* last desc and fire IRQ */
-        new->desc.ddadr = DDADR_STOP;
-        new->desc.dcmd |= DCMD_ENDIRQEN;
-
-        return &first->async_tx;
-
-fail:
-        if (first)
-                mmp_pdma_free_desc_list(chan, &first->tx_list);
-        return NULL;
-}
-
-static struct dma_async_tx_descriptor *
-mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
-                         unsigned int sg_len, enum dma_transfer_direction dir,
-                         unsigned long flags, void *context)
-{
-        struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
-        struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
-        size_t len, avail;
-        struct scatterlist *sg;
-        dma_addr_t addr;
-        int i;
-
-        if ((sgl == NULL) || (sg_len == 0))
-                return NULL;
-
-        for_each_sg(sgl, sg, sg_len, i) {
-                addr = sg_dma_address(sg);
-                avail = sg_dma_len(sgl);
-
-                do {
-                        len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
-
-                        /* allocate and populate the descriptor */
-                        new = mmp_pdma_alloc_descriptor(chan);
-                        if (!new) {
-                                dev_err(chan->dev, "no memory for desc\n");
-                                goto fail;
-                        }
-
-                        new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len);
-                        if (dir == DMA_MEM_TO_DEV) {
-                                new->desc.dsadr = addr;
-                                new->desc.dtadr = chan->dev_addr;
-                        } else {
-                                new->desc.dsadr = chan->dev_addr;
-                                new->desc.dtadr = addr;
-                        }
-
-                        if (!first)
-                                first = new;
-                        else
-                                prev->desc.ddadr = new->async_tx.phys;
-
-                        new->async_tx.cookie = 0;
-                        async_tx_ack(&new->async_tx);
-                        prev = new;
-
-                        /* Insert the link descriptor to the LD ring */
-                        list_add_tail(&new->node, &first->tx_list);
-
-                        /* update metadata */
-                        addr += len;
-                        avail -= len;
-                } while (avail);
-        }
-
-        first->async_tx.cookie = -EBUSY;
-        first->async_tx.flags = flags;
-
-        /* last desc and fire IRQ */
-        new->desc.ddadr = DDADR_STOP;
-        new->desc.dcmd |= DCMD_ENDIRQEN;
-
-        return &first->async_tx;
-
-fail:
-        if (first)
-                mmp_pdma_free_desc_list(chan, &first->tx_list);
-        return NULL;
-}
-
-static int mmp_pdma_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd,
-                unsigned long arg)
-{
-        struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
-        struct dma_slave_config *cfg = (void *)arg;
-        unsigned long flags;
-        int ret = 0;
-        u32 maxburst = 0, addr = 0;
-        enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
-
-        if (!dchan)
-                return -EINVAL;
-
-        switch (cmd) {
-        case DMA_TERMINATE_ALL:
-                disable_chan(chan->phy);
-                if (chan->phy) {
-                        chan->phy->vchan = NULL;
-                        chan->phy = NULL;
-                }
-                spin_lock_irqsave(&chan->desc_lock, flags);
-                mmp_pdma_free_desc_list(chan, &chan->chain_pending);
-                mmp_pdma_free_desc_list(chan, &chan->chain_running);
-                spin_unlock_irqrestore(&chan->desc_lock, flags);
-                chan->idle = true;
-                break;
-        case DMA_SLAVE_CONFIG:
-                if (cfg->direction == DMA_DEV_TO_MEM) {
-                        chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
-                        maxburst = cfg->src_maxburst;
-                        width = cfg->src_addr_width;
-                        addr = cfg->src_addr;
-                } else if (cfg->direction == DMA_MEM_TO_DEV) {
-                        chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
-                        maxburst = cfg->dst_maxburst;
-                        width = cfg->dst_addr_width;
-                        addr = cfg->dst_addr;
-                }
-
-                if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
-                        chan->dcmd |= DCMD_WIDTH1;
-                else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
-                        chan->dcmd |= DCMD_WIDTH2;
-                else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
-                        chan->dcmd |= DCMD_WIDTH4;
-
-                if (maxburst == 8)
-                        chan->dcmd |= DCMD_BURST8;
-                else if (maxburst == 16)
-                        chan->dcmd |= DCMD_BURST16;
-                else if (maxburst == 32)
-                        chan->dcmd |= DCMD_BURST32;
-
-                if (cfg) {
-                        chan->dir = cfg->direction;
-                        chan->drcmr = cfg->slave_id;
-                }
-                chan->dev_addr = addr;
-                break;
-        default:
-                return -ENOSYS;
-        }
-
-        return ret;
-}
-
-static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan,
-                        dma_cookie_t cookie, struct dma_tx_state *txstate)
-{
-        struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
-        enum dma_status ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&chan->desc_lock, flags);
-        ret = dma_cookie_status(dchan, cookie, txstate);
-        spin_unlock_irqrestore(&chan->desc_lock, flags);
-
-        return ret;
-}
-
-/**
- * mmp_pdma_issue_pending - Issue the DMA start command
- * pending list ==> running list
- */
-static void mmp_pdma_issue_pending(struct dma_chan *dchan)
-{
-        struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
-        unsigned long flags;
-
-        spin_lock_irqsave(&chan->desc_lock, flags);
-        start_pending_queue(chan);
-        spin_unlock_irqrestore(&chan->desc_lock, flags);
-}
-
-/*
- * dma_do_tasklet
- * Do call back
- * Start pending list
- */
-static void dma_do_tasklet(unsigned long data)
-{
-        struct mmp_pdma_chan *chan = (struct mmp_pdma_chan *)data;
-        struct mmp_pdma_desc_sw *desc, *_desc;
-        LIST_HEAD(chain_cleanup);
-        unsigned long flags;
-
-        /* submit pending list; callback for each desc; free desc */
-
-        spin_lock_irqsave(&chan->desc_lock, flags);
-
-        /* update the cookie if we have some descriptors to cleanup */
-        if (!list_empty(&chan->chain_running)) {
-                dma_cookie_t cookie;
-
-                desc = to_mmp_pdma_desc(chan->chain_running.prev);
-                cookie = desc->async_tx.cookie;
-                dma_cookie_complete(&desc->async_tx);
-
-                dev_dbg(chan->dev, "completed_cookie=%d\n", cookie);
-        }
-
-        /*
-         * move the descriptors to a temporary list so we can drop the lock
-         * during the entire cleanup operation
-         */
-        list_splice_tail_init(&chan->chain_running, &chain_cleanup);
-
-        /* the hardware is now idle and ready for more */
-        chan->idle = true;
-
-        /* Start any pending transactions automatically */
-        start_pending_queue(chan);
-        spin_unlock_irqrestore(&chan->desc_lock, flags);
-
-        /* Run the callback for each descriptor, in order */
-        list_for_each_entry_safe(desc, _desc, &chain_cleanup, node) {
-                struct dma_async_tx_descriptor *txd = &desc->async_tx;
-
-                /* Remove from the list of transactions */
-                list_del(&desc->node);
-                /* Run the link descriptor callback function */
-                if (txd->callback)
-                        txd->callback(txd->callback_param);
-
-                dma_pool_free(chan->desc_pool, desc, txd->phys);
-        }
-}
-
-static int mmp_pdma_remove(struct platform_device *op)
-{
-        struct mmp_pdma_device *pdev = platform_get_drvdata(op);
-
-        dma_async_device_unregister(&pdev->device);
-        return 0;
-}
-
-static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev,
-                                                        int idx, int irq)
-{
-        struct mmp_pdma_phy *phy  = &pdev->phy[idx];
-        struct mmp_pdma_chan *chan;
-        int ret;
-
-        chan = devm_kzalloc(pdev->dev,
-                        sizeof(struct mmp_pdma_chan), GFP_KERNEL);
-        if (chan == NULL)
-                return -ENOMEM;
-
-        phy->idx = idx;
-        phy->base = pdev->base;
-
-        if (irq) {
-                ret = devm_request_irq(pdev->dev, irq,
-                        mmp_pdma_chan_handler, IRQF_DISABLED, "pdma", phy);
-                if (ret) {
-                        dev_err(pdev->dev, "channel request irq fail!\n");
-                        return ret;
-                }
-        }
-
-        spin_lock_init(&chan->desc_lock);
-        chan->dev = pdev->dev;
-        chan->chan.device = &pdev->device;
-        tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
-        INIT_LIST_HEAD(&chan->chain_pending);
-        INIT_LIST_HEAD(&chan->chain_running);
-
-        /* register virt channel to dma engine */
-        list_add_tail(&chan->chan.device_node,
-                        &pdev->device.channels);
-
-        return 0;
-}
-
-static struct of_device_id mmp_pdma_dt_ids[] = {
-        { .compatible = "marvell,pdma-1.0", },
-        {}
-};
-MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
-
-static int mmp_pdma_probe(struct platform_device *op)
-{
-        struct mmp_pdma_device *pdev;
-        const struct of_device_id *of_id;
-        struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
-        struct resource *iores;
-        int i, ret, irq = 0;
-        int dma_channels = 0, irq_num = 0;
-
-        pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
-        if (!pdev)
-                return -ENOMEM;
-        pdev->dev = &op->dev;
-
-        iores = platform_get_resource(op, IORESOURCE_MEM, 0);
-        if (!iores)
-                return -EINVAL;
-
-        pdev->base = devm_request_and_ioremap(pdev->dev, iores);
-        if (!pdev->base)
-                return -EADDRNOTAVAIL;
-
-        of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev);
-        if (of_id)
-                of_property_read_u32(pdev->dev->of_node,
-                                "#dma-channels", &dma_channels);
-        else if (pdata && pdata->dma_channels)
-                dma_channels = pdata->dma_channels;
-        else
-                dma_channels = 32;      /* default 32 channel */
-        pdev->dma_channels = dma_channels;
-
-        for (i = 0; i < dma_channels; i++) {
-                if (platform_get_irq(op, i) > 0)
-                        irq_num++;
-        }
-
-        pdev->phy = devm_kzalloc(pdev->dev,
-                dma_channels * sizeof(struct mmp_pdma_chan), GFP_KERNEL);
-        if (pdev->phy == NULL)
-                return -ENOMEM;
-
-        INIT_LIST_HEAD(&pdev->device.channels);
-
-        if (irq_num != dma_channels) {
-                /* all chan share one irq, demux inside */
-                irq = platform_get_irq(op, 0);
-                ret = devm_request_irq(pdev->dev, irq,
-                        mmp_pdma_int_handler, IRQF_DISABLED, "pdma", pdev);
-                if (ret)
-                        return ret;
-        }
-
-        for (i = 0; i < dma_channels; i++) {
-                irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i);
-                ret = mmp_pdma_chan_init(pdev, i, irq);
-                if (ret)
-                        return ret;
-        }
-
-        dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
-        dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask);
-        dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
-        pdev->device.dev = &op->dev;
-        pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources;
-        pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources;
-        pdev->device.device_tx_status = mmp_pdma_tx_status;
-        pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy;
-        pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg;
-        pdev->device.device_issue_pending = mmp_pdma_issue_pending;
-        pdev->device.device_control = mmp_pdma_control;
-        pdev->device.copy_align = PDMA_ALIGNMENT;
-
-        if (pdev->dev->coherent_dma_mask)
-                dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask);
-        else
-                dma_set_mask(pdev->dev, DMA_BIT_MASK(64));
-
-        ret = dma_async_device_register(&pdev->device);
-        if (ret) {
-                dev_err(pdev->device.dev, "unable to register\n");
-                return ret;
-        }
-
-        dev_info(pdev->device.dev, "initialized\n");
-        return 0;
-}
-
-static const struct platform_device_id mmp_pdma_id_table[] = {
-        { "mmp-pdma", },
-        { },
-};
-
-static struct platform_driver mmp_pdma_driver = {
-        .driver         = {
-                .name   = "mmp-pdma",
-                .owner  = THIS_MODULE,
-                .of_match_table = mmp_pdma_dt_ids,
-        },
-        .id_table       = mmp_pdma_id_table,
-        .probe          = mmp_pdma_probe,
-        .remove         = mmp_pdma_remove,
-};
-
-module_platform_driver(mmp_pdma_driver);
-
-MODULE_DESCRIPTION("MARVELL MMP Periphera DMA Driver");
-MODULE_AUTHOR("Marvell International Ltd.");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/mmp_tdma.c b/drivers/dma/mmp_tdma.c
deleted file mode 100644
index a9f1cd56689..00000000000
--- a/drivers/dma/mmp_tdma.c
+++ /dev/null
@@ -1,621 +0,0 @@
-/*
- * Driver For Marvell Two-channel DMA Engine
- *
- * Copyright: Marvell International Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-#include <linux/dmaengine.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <mach/regs-icu.h>
-#include <linux/platform_data/dma-mmp_tdma.h>
-#include <linux/of_device.h>
-
-#include "dmaengine.h"
-
-/*
- * Two-Channel DMA registers
- */
-#define TDBCR           0x00    /* Byte Count */
-#define TDSAR           0x10    /* Src Addr */
-#define TDDAR           0x20    /* Dst Addr */
-#define TDNDPR          0x30    /* Next Desc */
-#define TDCR            0x40    /* Control */
-#define TDCP            0x60    /* Priority*/
-#define TDCDPR          0x70    /* Current Desc */
-#define TDIMR           0x80    /* Int Mask */
-#define TDISR           0xa0    /* Int Status */
-
-/* Two-Channel DMA Control Register */
-#define TDCR_SSZ_8_BITS         (0x0 << 22)     /* Sample Size */
-#define TDCR_SSZ_12_BITS        (0x1 << 22)
-#define TDCR_SSZ_16_BITS        (0x2 << 22)
-#define TDCR_SSZ_20_BITS        (0x3 << 22)
-#define TDCR_SSZ_24_BITS        (0x4 << 22)
-#define TDCR_SSZ_32_BITS        (0x5 << 22)
-#define TDCR_SSZ_SHIFT          (0x1 << 22)
-#define TDCR_SSZ_MASK           (0x7 << 22)
-#define TDCR_SSPMOD             (0x1 << 21)     /* SSP MOD */
-#define TDCR_ABR                (0x1 << 20)     /* Channel Abort */
-#define TDCR_CDE                (0x1 << 17)     /* Close Desc Enable */
-#define TDCR_PACKMOD            (0x1 << 16)     /* Pack Mode (ADMA Only) */
-#define TDCR_CHANACT            (0x1 << 14)     /* Channel Active */
-#define TDCR_FETCHND            (0x1 << 13)     /* Fetch Next Desc */
-#define TDCR_CHANEN             (0x1 << 12)     /* Channel Enable */
-#define TDCR_INTMODE            (0x1 << 10)     /* Interrupt Mode */
-#define TDCR_CHAINMOD           (0x1 << 9)      /* Chain Mode */
-#define TDCR_BURSTSZ_MSK        (0x7 << 6)      /* Burst Size */
-#define TDCR_BURSTSZ_4B         (0x0 << 6)
-#define TDCR_BURSTSZ_8B         (0x1 << 6)
-#define TDCR_BURSTSZ_16B        (0x3 << 6)
-#define TDCR_BURSTSZ_32B        (0x6 << 6)
-#define TDCR_BURSTSZ_64B        (0x7 << 6)
-#define TDCR_BURSTSZ_SQU_32B    (0x7 << 6)
-#define TDCR_BURSTSZ_128B       (0x5 << 6)
-#define TDCR_DSTDIR_MSK         (0x3 << 4)      /* Dst Direction */
-#define TDCR_DSTDIR_ADDR_HOLD   (0x2 << 4)      /* Dst Addr Hold */
-#define TDCR_DSTDIR_ADDR_INC    (0x0 << 4)      /* Dst Addr Increment */
-#define TDCR_SRCDIR_MSK         (0x3 << 2)      /* Src Direction */
-#define TDCR_SRCDIR_ADDR_HOLD   (0x2 << 2)      /* Src Addr Hold */
-#define TDCR_SRCDIR_ADDR_INC    (0x0 << 2)      /* Src Addr Increment */
-#define TDCR_DSTDESCCONT        (0x1 << 1)
-#define TDCR_SRCDESTCONT        (0x1 << 0)
-
-/* Two-Channel DMA Int Mask Register */
-#define TDIMR_COMP              (0x1 << 0)
-
-/* Two-Channel DMA Int Status Register */
-#define TDISR_COMP              (0x1 << 0)
-
-/*
- * Two-Channel DMA Descriptor Struct
- * NOTE: desc's buf must be aligned to 16 bytes.
- */
-struct mmp_tdma_desc {
-        u32 byte_cnt;
-        u32 src_addr;
-        u32 dst_addr;
-        u32 nxt_desc;
-};
-
-enum mmp_tdma_type {
-        MMP_AUD_TDMA = 0,
-        PXA910_SQU,
-};
-
-#define TDMA_ALIGNMENT          3
-#define TDMA_MAX_XFER_BYTES    SZ_64K
-
-struct mmp_tdma_chan {
-        struct device                   *dev;
-        struct dma_chan                 chan;
-        struct dma_async_tx_descriptor  desc;
-        struct tasklet_struct           tasklet;
-
-        struct mmp_tdma_desc            *desc_arr;
-        phys_addr_t                     desc_arr_phys;
-        int                             desc_num;
-        enum dma_transfer_direction     dir;
-        dma_addr_t                      dev_addr;
-        u32                             burst_sz;
-        enum dma_slave_buswidth         buswidth;
-        enum dma_status                 status;
-
-        int                             idx;
-        enum mmp_tdma_type              type;
-        int                             irq;
-        unsigned long                   reg_base;
-
-        size_t                          buf_len;
-        size_t                          period_len;
-        size_t                          pos;
-};
-
-#define TDMA_CHANNEL_NUM 2
-struct mmp_tdma_device {
-        struct device                   *dev;
-        void __iomem                    *base;
-        struct dma_device               device;
-        struct mmp_tdma_chan            *tdmac[TDMA_CHANNEL_NUM];
-};
-
-#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
-
-static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
-{
-        writel(phys, tdmac->reg_base + TDNDPR);
-        writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
-                                        tdmac->reg_base + TDCR);
-}
-
-static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
-{
-        /* enable irq */
-        writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
-        /* enable dma chan */
-        writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
-                                        tdmac->reg_base + TDCR);
-        tdmac->status = DMA_IN_PROGRESS;
-}
-
-static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
-{
-        writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
-                                        tdmac->reg_base + TDCR);
-        tdmac->status = DMA_SUCCESS;
-}
-
-static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac)
-{
-        writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
-                                        tdmac->reg_base + TDCR);
-        tdmac->status = DMA_IN_PROGRESS;
-}
-
-static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac)
-{
-        writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
-                                        tdmac->reg_base + TDCR);
-        tdmac->status = DMA_PAUSED;
-}
-
-static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
-{
-        unsigned int tdcr;
-
-        mmp_tdma_disable_chan(tdmac);
-
-        if (tdmac->dir == DMA_MEM_TO_DEV)
-                tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
-        else if (tdmac->dir == DMA_DEV_TO_MEM)
-                tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
-
-        if (tdmac->type == MMP_AUD_TDMA) {
-                tdcr |= TDCR_PACKMOD;
-
-                switch (tdmac->burst_sz) {
-                case 4:
-                        tdcr |= TDCR_BURSTSZ_4B;
-                        break;
-                case 8:
-                        tdcr |= TDCR_BURSTSZ_8B;
-                        break;
-                case 16:
-                        tdcr |= TDCR_BURSTSZ_16B;
-                        break;
-                case 32:
-                        tdcr |= TDCR_BURSTSZ_32B;
-                        break;
-                case 64:
-                        tdcr |= TDCR_BURSTSZ_64B;
-                        break;
-                case 128:
-                        tdcr |= TDCR_BURSTSZ_128B;
-                        break;
-                default:
-                        dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
-                        return -EINVAL;
-                }
-
-                switch (tdmac->buswidth) {
-                case DMA_SLAVE_BUSWIDTH_1_BYTE:
-                        tdcr |= TDCR_SSZ_8_BITS;
-                        break;
-                case DMA_SLAVE_BUSWIDTH_2_BYTES:
-                        tdcr |= TDCR_SSZ_16_BITS;
-                        break;
-                case DMA_SLAVE_BUSWIDTH_4_BYTES:
-                        tdcr |= TDCR_SSZ_32_BITS;
-                        break;
-                default:
-                        dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
-                        return -EINVAL;
-                }
-        } else if (tdmac->type == PXA910_SQU) {
-                tdcr |= TDCR_BURSTSZ_SQU_32B;
-                tdcr |= TDCR_SSPMOD;
-        }
-
-        writel(tdcr, tdmac->reg_base + TDCR);
-        return 0;
-}
-
-static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
-{
-        u32 reg = readl(tdmac->reg_base + TDISR);
-
-        if (reg & TDISR_COMP) {
-                /* clear irq */
-                reg &= ~TDISR_COMP;
-                writel(reg, tdmac->reg_base + TDISR);
-
-                return 0;
-        }
-        return -EAGAIN;
-}
-
-static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
-{
-        struct mmp_tdma_chan *tdmac = dev_id;
-
-        if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
-                tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len;
-                tasklet_schedule(&tdmac->tasklet);
-                return IRQ_HANDLED;
-        } else
-                return IRQ_NONE;
-}
-
-static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
-{
-        struct mmp_tdma_device *tdev = dev_id;
-        int i, ret;
-        int irq_num = 0;
-
-        for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
-                struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
-
-                ret = mmp_tdma_chan_handler(irq, tdmac);
-                if (ret == IRQ_HANDLED)
-                        irq_num++;
-        }
-
-        if (irq_num)
-                return IRQ_HANDLED;
-        else
-                return IRQ_NONE;
-}
-
-static void dma_do_tasklet(unsigned long data)
-{
-        struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
-
-        if (tdmac->desc.callback)
-                tdmac->desc.callback(tdmac->desc.callback_param);
-
-}
-
-static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
-{
-        struct gen_pool *gpool;
-        int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
-
-        gpool = sram_get_gpool("asram");
-        if (tdmac->desc_arr)
-                gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
-                                size);
-        tdmac->desc_arr = NULL;
-
-        return;
-}
-
-static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
-{
-        struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
-
-        mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
-
-        return 0;
-}
-
-static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
-{
-        struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
-        int ret;
-
-        dma_async_tx_descriptor_init(&tdmac->desc, chan);
-        tdmac->desc.tx_submit = mmp_tdma_tx_submit;
-
-        if (tdmac->irq) {
-                ret = devm_request_irq(tdmac->dev, tdmac->irq,
-                        mmp_tdma_chan_handler, IRQF_DISABLED, "tdma", tdmac);
-                if (ret)
-                        return ret;
-        }
-        return 1;
-}
-
-static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
-{
-        struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
-
-        if (tdmac->irq)
-                devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
-        mmp_tdma_free_descriptor(tdmac);
-        return;
-}
-
-struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
-{
-        struct gen_pool *gpool;
-        int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
-
-        gpool = sram_get_gpool("asram");
-        if (!gpool)
-                return NULL;
-
-        tdmac->desc_arr = (void *)gen_pool_alloc(gpool, size);
-        if (!tdmac->desc_arr)
-                return NULL;
-
-        tdmac->desc_arr_phys = gen_pool_virt_to_phys(gpool,
-                        (unsigned long)tdmac->desc_arr);
-
-        return tdmac->desc_arr;
-}
-
-static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
-                struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
-                size_t period_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
-{
-        struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
-        struct mmp_tdma_desc *desc;
-        int num_periods = buf_len / period_len;
-        int i = 0, buf = 0;
-
-        if (tdmac->status != DMA_SUCCESS)
-                return NULL;
-
-        if (period_len > TDMA_MAX_XFER_BYTES) {
-                dev_err(tdmac->dev,
-                                "maximum period size exceeded: %d > %d\n",
-                                period_len, TDMA_MAX_XFER_BYTES);
-                goto err_out;
-        }
-
-        tdmac->status = DMA_IN_PROGRESS;
-        tdmac->desc_num = num_periods;
-        desc = mmp_tdma_alloc_descriptor(tdmac);
-        if (!desc)
-                goto err_out;
-
-        while (buf < buf_len) {
-                desc = &tdmac->desc_arr[i];
-
-                if (i + 1 == num_periods)
-                        desc->nxt_desc = tdmac->desc_arr_phys;
-                else
-                        desc->nxt_desc = tdmac->desc_arr_phys +
-                                sizeof(*desc) * (i + 1);
-
-                if (direction == DMA_MEM_TO_DEV) {
-                        desc->src_addr = dma_addr;
-                        desc->dst_addr = tdmac->dev_addr;
-                } else {
-                        desc->src_addr = tdmac->dev_addr;
-                        desc->dst_addr = dma_addr;
-                }
-                desc->byte_cnt = period_len;
-                dma_addr += period_len;
-                buf += period_len;
-                i++;
-        }
-
-        tdmac->buf_len = buf_len;
-        tdmac->period_len = period_len;
-        tdmac->pos = 0;
-
-        return &tdmac->desc;
-
-err_out:
-        tdmac->status = DMA_ERROR;
-        return NULL;
-}
-
-static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-                unsigned long arg)
-{
-        struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
-        struct dma_slave_config *dmaengine_cfg = (void *)arg;
-        int ret = 0;
-
-        switch (cmd) {
-        case DMA_TERMINATE_ALL:
-                mmp_tdma_disable_chan(tdmac);
-                break;
-        case DMA_PAUSE:
-                mmp_tdma_pause_chan(tdmac);
-                break;
-        case DMA_RESUME:
-                mmp_tdma_resume_chan(tdmac);
-                break;
-        case DMA_SLAVE_CONFIG:
-                if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
-                        tdmac->dev_addr = dmaengine_cfg->src_addr;
-                        tdmac->burst_sz = dmaengine_cfg->src_maxburst;
-                        tdmac->buswidth = dmaengine_cfg->src_addr_width;
-                } else {
-                        tdmac->dev_addr = dmaengine_cfg->dst_addr;
-                        tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
-                        tdmac->buswidth = dmaengine_cfg->dst_addr_width;
-                }
-                tdmac->dir = dmaengine_cfg->direction;
-                return mmp_tdma_config_chan(tdmac);
-        default:
-                ret = -ENOSYS;
-        }
-
-        return ret;
-}
-
-static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
-                        dma_cookie_t cookie, struct dma_tx_state *txstate)
-{
-        struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
-
-        dma_set_residue(txstate, tdmac->buf_len - tdmac->pos);
-
-        return tdmac->status;
-}
-
-static void mmp_tdma_issue_pending(struct dma_chan *chan)
-{
-        struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
-
-        mmp_tdma_enable_chan(tdmac);
-}
-
-static int mmp_tdma_remove(struct platform_device *pdev)
-{
-        struct mmp_tdma_device *tdev = platform_get_drvdata(pdev);
-
-        dma_async_device_unregister(&tdev->device);
-        return 0;
-}
-
-static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
-                                                int idx, int irq, int type)
-{
-        struct mmp_tdma_chan *tdmac;
-
-        if (idx >= TDMA_CHANNEL_NUM) {
-                dev_err(tdev->dev, "too many channels for device!\n");
-                return -EINVAL;
-        }
-
-        /* alloc channel */
-        tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
-        if (!tdmac) {
-                dev_err(tdev->dev, "no free memory for DMA channels!\n");
-                return -ENOMEM;
-        }
-        if (irq)
-                tdmac->irq = irq;
-        tdmac->dev         = tdev->dev;
-        tdmac->chan.device = &tdev->device;
-        tdmac->idx         = idx;
-        tdmac->type        = type;
-        tdmac->reg_base    = (unsigned long)tdev->base + idx * 4;
-        tdmac->status = DMA_SUCCESS;
-        tdev->tdmac[tdmac->idx] = tdmac;
-        tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
-
-        /* add the channel to tdma_chan list */
-        list_add_tail(&tdmac->chan.device_node,
-                        &tdev->device.channels);
-        return 0;
-}
-
-static struct of_device_id mmp_tdma_dt_ids[] = {
-        { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
-        { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
-        {}
-};
-MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
-
-static int mmp_tdma_probe(struct platform_device *pdev)
-{
-        enum mmp_tdma_type type;
-        const struct of_device_id *of_id;
-        struct mmp_tdma_device *tdev;
-        struct resource *iores;
-        int i, ret;
-        int irq = 0, irq_num = 0;
-        int chan_num = TDMA_CHANNEL_NUM;
-
-        of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
-        if (of_id)
-                type = (enum mmp_tdma_type) of_id->data;
-        else
-                type = platform_get_device_id(pdev)->driver_data;
-
-        /* always have couple channels */
-        tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
-        if (!tdev)
-                return -ENOMEM;
-
-        tdev->dev = &pdev->dev;
-
-        for (i = 0; i < chan_num; i++) {
-                if (platform_get_irq(pdev, i) > 0)
-                        irq_num++;
-        }
-
-        iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!iores)
-                return -EINVAL;
-
-        tdev->base = devm_request_and_ioremap(&pdev->dev, iores);
-        if (!tdev->base)
-                return -EADDRNOTAVAIL;
-
-        INIT_LIST_HEAD(&tdev->device.channels);
-
-        if (irq_num != chan_num) {
-                irq = platform_get_irq(pdev, 0);
-                ret = devm_request_irq(&pdev->dev, irq,
-                        mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev);
-                if (ret)
-                        return ret;
-        }
-
-        /* initialize channel parameters */
-        for (i = 0; i < chan_num; i++) {
-                irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
-                ret = mmp_tdma_chan_init(tdev, i, irq, type);
-                if (ret)
-                        return ret;
-        }
-
-        dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
-        dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
-        tdev->device.dev = &pdev->dev;
-        tdev->device.device_alloc_chan_resources =
-                                        mmp_tdma_alloc_chan_resources;
-        tdev->device.device_free_chan_resources =
-                                        mmp_tdma_free_chan_resources;
-        tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
-        tdev->device.device_tx_status = mmp_tdma_tx_status;
-        tdev->device.device_issue_pending = mmp_tdma_issue_pending;
-        tdev->device.device_control = mmp_tdma_control;
-        tdev->device.copy_align = TDMA_ALIGNMENT;
-
-        dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
-        platform_set_drvdata(pdev, tdev);
-
-        ret = dma_async_device_register(&tdev->device);
-        if (ret) {
-                dev_err(tdev->device.dev, "unable to register\n");
-                return ret;
-        }
-
-        dev_info(tdev->device.dev, "initialized\n");
-        return 0;
-}
-
-static const struct platform_device_id mmp_tdma_id_table[] = {
-        { "mmp-adma",   MMP_AUD_TDMA },
-        { "pxa910-squ", PXA910_SQU },
-        { },
-};
-
-static struct platform_driver mmp_tdma_driver = {
-        .driver         = {
-                .name   = "mmp-tdma",
-                .owner  = THIS_MODULE,
-                .of_match_table = mmp_tdma_dt_ids,
-        },
-        .id_table       = mmp_tdma_id_table,
-        .probe          = mmp_tdma_probe,
-        .remove         = mmp_tdma_remove,
-};
-
-module_platform_driver(mmp_tdma_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
-MODULE_ALIAS("platform:mmp-tdma");
-MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
-MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 2d956732aa3..b9bae94f201 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -44,8 +44,6 @@
 
 #include <linux/random.h>
 
-#include "dmaengine.h"
-
 /* Number of DMA Transfer descriptors allocated per channel */
 #define MPC_DMA_DESCRIPTORS     64
 
@@ -190,6 +188,7 @@ struct mpc_dma_chan {
         struct list_head                completed;
         struct mpc_dma_tcd              *tcd;
         dma_addr_t                      tcd_paddr;
+        dma_cookie_t                    completed_cookie;
 
         /* Lock for this structure */
         spinlock_t                      lock;
@@ -366,7 +365,7 @@ static void mpc_dma_process_completed(struct mpc_dma *mdma)
                 /* Free descriptors */
                 spin_lock_irqsave(&mchan->lock, flags);
                 list_splice_tail_init(&list, &mchan->free);
-                mchan->chan.completed_cookie = last_cookie;
+                mchan->completed_cookie = last_cookie;
                 spin_unlock_irqrestore(&mchan->lock, flags);
         }
 }
@@ -439,7 +438,13 @@ static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
                 mpc_dma_execute(mchan);
 
         /* Update cookie */
-        cookie = dma_cookie_assign(txd);
+        cookie = mchan->chan.cookie + 1;
+        if (cookie <= 0)
+                cookie = 1;
+
+        mchan->chan.cookie = cookie;
+        mdesc->desc.cookie = cookie;
+
         spin_unlock_irqrestore(&mchan->lock, flags);
 
         return cookie;
@@ -557,14 +562,17 @@ mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
                struct dma_tx_state *txstate)
 {
         struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
-        enum dma_status ret;
         unsigned long flags;
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
 
         spin_lock_irqsave(&mchan->lock, flags);
-        ret = dma_cookie_status(chan, cookie, txstate);
+        last_used = mchan->chan.cookie;
+        last_complete = mchan->completed_cookie;
         spin_unlock_irqrestore(&mchan->lock, flags);
 
-        return ret;
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+        return dma_async_is_complete(cookie, last_complete, last_used);
 }
 
 /* Prepare descriptor for memory to memory copy */
@@ -641,7 +649,7 @@ mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
         return &mdesc->desc;
 }
 
-static int mpc_dma_probe(struct platform_device *op)
+static int __devinit mpc_dma_probe(struct platform_device *op)
 {
         struct device_node *dn = op->dev.of_node;
         struct device *dev = &op->dev;
@@ -733,7 +741,9 @@ static int mpc_dma_probe(struct platform_device *op)
                 mchan = &mdma->channels[i];
 
                 mchan->chan.device = dma;
-                dma_cookie_init(&mchan->chan);
+                mchan->chan.chan_id = i;
+                mchan->chan.cookie = 1;
+                mchan->completed_cookie = mchan->chan.cookie;
 
                 INIT_LIST_HEAD(&mchan->free);
                 INIT_LIST_HEAD(&mchan->prepared);
@@ -799,7 +809,7 @@ static int mpc_dma_probe(struct platform_device *op)
         return retval;
 }
 
-static int mpc_dma_remove(struct platform_device *op)
+static int __devexit mpc_dma_remove(struct platform_device *op)
 {
         struct device *dev = &op->dev;
         struct mpc_dma *mdma = dev_get_drvdata(dev);
@@ -818,7 +828,7 @@ static struct of_device_id mpc_dma_match[] = {
 
 static struct platform_driver mpc_dma_driver = {
         .probe          = mpc_dma_probe,
-        .remove         = mpc_dma_remove,
+        .remove         = __devexit_p(mpc_dma_remove),
         .driver = {
                 .name = DRV_NAME,
                 .owner = THIS_MODULE,
@@ -826,7 +836,17 @@ static struct platform_driver mpc_dma_driver = {
         },
 };
 
-module_platform_driver(mpc_dma_driver);
+static int __init mpc_dma_init(void)
+{
+        return platform_driver_register(&mpc_dma_driver);
+}
+module_init(mpc_dma_init);
+
+static void __exit mpc_dma_exit(void)
+{
+        platform_driver_unregister(&mpc_dma_driver);
+}
+module_exit(mpc_dma_exit);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>");
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index e17fad03cb8..9a353c2216d 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -25,26 +25,20 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/memory.h>
-#include <linux/clk.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/irqdomain.h>
-#include <linux/platform_data/dma-mv_xor.h>
-
-#include "dmaengine.h"
+#include <plat/mv_xor.h>
 #include "mv_xor.h"
 
 static void mv_xor_issue_pending(struct dma_chan *chan);
 
 #define to_mv_xor_chan(chan)            \
-        container_of(chan, struct mv_xor_chan, dmachan)
+        container_of(chan, struct mv_xor_chan, common)
+
+#define to_mv_xor_device(dev)           \
+        container_of(dev, struct mv_xor_device, common)
 
 #define to_mv_xor_slot(tx)              \
         container_of(tx, struct mv_xor_desc_slot, async_tx)
 
-#define mv_chan_to_devp(chan)           \
-        ((chan)->dmadev.dev)
-
 static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
 {
         struct mv_xor_desc *hw_desc = desc->hw_desc;
@@ -169,7 +163,7 @@ static int mv_is_err_intr(u32 intr_cause)
 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
 {
         u32 val = ~(1 << (chan->idx * 16));
-        dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
+        dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
         __raw_writel(val, XOR_INTR_CAUSE(chan));
 }
 
@@ -209,9 +203,9 @@ static void mv_set_mode(struct mv_xor_chan *chan,
                 op_mode = XOR_OPERATION_MODE_MEMSET;
                 break;
         default:
-                dev_err(mv_chan_to_devp(chan),
-                        "error: unsupported operation %d.\n",
-                        type);
+                dev_printk(KERN_ERR, chan->device->common.dev,
+                           "error: unsupported operation %d.\n",
+                           type);
                 BUG();
                 return;
         }
@@ -226,7 +220,7 @@ static void mv_chan_activate(struct mv_xor_chan *chan)
 {
         u32 activation;
 
-        dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
+        dev_dbg(chan->device->common.dev, " activate chan.\n");
         activation = __raw_readl(XOR_ACTIVATION(chan));
         activation |= 0x1;
         __raw_writel(activation, XOR_ACTIVATION(chan));
@@ -254,7 +248,7 @@ static int mv_chan_xor_slot_count(size_t len, int src_cnt)
 static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
                               struct mv_xor_desc_slot *slot)
 {
-        dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n",
+        dev_dbg(mv_chan->device->common.dev, "%s %d slot %p\n",
                 __func__, __LINE__, slot);
 
         slot->slots_per_op = 0;
@@ -269,7 +263,7 @@ static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
 static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
                                    struct mv_xor_desc_slot *sw_desc)
 {
-        dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
+        dev_dbg(mv_chan->device->common.dev, "%s %d: sw_desc %p\n",
                 __func__, __LINE__, sw_desc);
         if (sw_desc->type != mv_chan->current_type)
                 mv_set_mode(mv_chan, sw_desc->type);
@@ -287,7 +281,7 @@ static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
                 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
         }
         mv_chan->pending += sw_desc->slot_cnt;
-        mv_xor_issue_pending(&mv_chan->dmachan);
+        mv_xor_issue_pending(&mv_chan->common);
 }
 
 static dma_cookie_t
@@ -311,7 +305,8 @@ mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
                  */
                 if (desc->group_head && desc->unmap_len) {
                         struct mv_xor_desc_slot *unmap = desc->group_head;
-                        struct device *dev = mv_chan_to_devp(mv_chan);
+                        struct device *dev =
+                                &mv_chan->device->pdev->dev;
                         u32 len = unmap->unmap_len;
                         enum dma_ctrl_flags flags = desc->async_tx.flags;
                         u32 src_cnt;
@@ -355,7 +350,7 @@ mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
 {
         struct mv_xor_desc_slot *iter, *_iter;
 
-        dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
+        dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
                                  completed_node) {
 
@@ -371,7 +366,7 @@ static int
 mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
         struct mv_xor_chan *mv_chan)
 {
-        dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
+        dev_dbg(mv_chan->device->common.dev, "%s %d: desc %p flags %d\n",
                 __func__, __LINE__, desc, desc->async_tx.flags);
         list_del(&desc->chain_node);
         /* the client is allowed to attach dependent operations
@@ -395,8 +390,8 @@ static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
         u32 current_desc = mv_chan_get_current_desc(mv_chan);
         int seen_current = 0;
 
-        dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
-        dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
+        dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
+        dev_dbg(mv_chan->device->common.dev, "current_desc %x\n", current_desc);
         mv_xor_clean_completed_slots(mv_chan);
 
         /* free completed slots from the chain starting with
@@ -440,7 +435,7 @@ static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
         }
 
         if (cookie > 0)
-                mv_chan->dmachan.completed_cookie = cookie;
+                mv_chan->completed_cookie = cookie;
 }
 
 static void
@@ -539,6 +534,18 @@ retry:
         return NULL;
 }
 
+static dma_cookie_t
+mv_desc_assign_cookie(struct mv_xor_chan *mv_chan,
+                      struct mv_xor_desc_slot *desc)
+{
+        dma_cookie_t cookie = mv_chan->common.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+        mv_chan->common.cookie = desc->async_tx.cookie = cookie;
+        return cookie;
+}
+
 /************************ DMA engine API functions ****************************/
 static dma_cookie_t
 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
@@ -549,14 +556,14 @@ mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
         dma_cookie_t cookie;
         int new_hw_chain = 1;
 
-        dev_dbg(mv_chan_to_devp(mv_chan),
+        dev_dbg(mv_chan->device->common.dev,
                 "%s sw_desc %p: async_tx %p\n",
                 __func__, sw_desc, &sw_desc->async_tx);
 
         grp_start = sw_desc->group_head;
 
         spin_lock_bh(&mv_chan->lock);
-        cookie = dma_cookie_assign(tx);
+        cookie = mv_desc_assign_cookie(mv_chan, sw_desc);
 
         if (list_empty(&mv_chan->chain))
                 list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
@@ -572,7 +579,7 @@ mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
                 if (!mv_can_chain(grp_start))
                         goto submit_done;
 
-                dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %x\n",
+                dev_dbg(mv_chan->device->common.dev, "Append to last desc %x\n",
                         old_chain_tail->async_tx.phys);
 
                 /* fix up the hardware chain */
@@ -606,7 +613,9 @@ static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
         int idx;
         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
         struct mv_xor_desc_slot *slot = NULL;
-        int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
+        struct mv_xor_platform_data *plat_data =
+                mv_chan->device->pdev->dev.platform_data;
+        int num_descs_in_pool = plat_data->pool_size/MV_XOR_SLOT_SIZE;
 
         /* Allocate descriptor slots */
         idx = mv_chan->slots_allocated;
@@ -617,7 +626,7 @@ static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
                                 " %d descriptor slots", idx);
                         break;
                 }
-                hw_desc = (char *) mv_chan->dma_desc_pool_virt;
+                hw_desc = (char *) mv_chan->device->dma_desc_pool_virt;
                 slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE];
 
                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
@@ -625,7 +634,7 @@ static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
                 INIT_LIST_HEAD(&slot->chain_node);
                 INIT_LIST_HEAD(&slot->slot_node);
                 INIT_LIST_HEAD(&slot->tx_list);
-                hw_desc = (char *) mv_chan->dma_desc_pool;
+                hw_desc = (char *) mv_chan->device->dma_desc_pool;
                 slot->async_tx.phys =
                         (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
                 slot->idx = idx++;
@@ -641,7 +650,7 @@ static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
                                         struct mv_xor_desc_slot,
                                         slot_node);
 
-        dev_dbg(mv_chan_to_devp(mv_chan),
+        dev_dbg(mv_chan->device->common.dev,
                 "allocated %d descriptor slots last_used: %p\n",
                 mv_chan->slots_allocated, mv_chan->last_used);
 
@@ -656,7 +665,7 @@ mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
         struct mv_xor_desc_slot *sw_desc, *grp_start;
         int slot_cnt;
 
-        dev_dbg(mv_chan_to_devp(mv_chan),
+        dev_dbg(mv_chan->device->common.dev,
                 "%s dest: %x src %x len: %u flags: %ld\n",
                 __func__, dest, src, len, flags);
         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
@@ -680,7 +689,7 @@ mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
         }
         spin_unlock_bh(&mv_chan->lock);
 
-        dev_dbg(mv_chan_to_devp(mv_chan),
+        dev_dbg(mv_chan->device->common.dev,
                 "%s sw_desc %p async_tx %p\n",
                 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : 0);
 
@@ -695,7 +704,7 @@ mv_xor_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
         struct mv_xor_desc_slot *sw_desc, *grp_start;
         int slot_cnt;
 
-        dev_dbg(mv_chan_to_devp(mv_chan),
+        dev_dbg(mv_chan->device->common.dev,
                 "%s dest: %x len: %u flags: %ld\n",
                 __func__, dest, len, flags);
         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
@@ -718,7 +727,7 @@ mv_xor_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
                 sw_desc->unmap_len = len;
         }
         spin_unlock_bh(&mv_chan->lock);
-        dev_dbg(mv_chan_to_devp(mv_chan),
+        dev_dbg(mv_chan->device->common.dev,
                 "%s sw_desc %p async_tx %p \n",
                 __func__, sw_desc, &sw_desc->async_tx);
         return sw_desc ? &sw_desc->async_tx : NULL;
@@ -737,7 +746,7 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 
         BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
 
-        dev_dbg(mv_chan_to_devp(mv_chan),
+        dev_dbg(mv_chan->device->common.dev,
                 "%s src_cnt: %d len: dest %x %u flags: %ld\n",
                 __func__, src_cnt, len, dest, flags);
 
@@ -758,7 +767,7 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
                         mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
         }
         spin_unlock_bh(&mv_chan->lock);
-        dev_dbg(mv_chan_to_devp(mv_chan),
+        dev_dbg(mv_chan->device->common.dev,
                 "%s sw_desc %p async_tx %p \n",
                 __func__, sw_desc, &sw_desc->async_tx);
         return sw_desc ? &sw_desc->async_tx : NULL;
@@ -791,12 +800,12 @@ static void mv_xor_free_chan_resources(struct dma_chan *chan)
         }
         mv_chan->last_used = NULL;
 
-        dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
+        dev_dbg(mv_chan->device->common.dev, "%s slots_allocated %d\n",
                 __func__, mv_chan->slots_allocated);
         spin_unlock_bh(&mv_chan->lock);
 
         if (in_use_descs)
-                dev_err(mv_chan_to_devp(mv_chan),
+                dev_err(mv_chan->device->common.dev,
                         "freeing %d in use descriptors!\n", in_use_descs);
 }
 
@@ -811,16 +820,27 @@ static enum dma_status mv_xor_status(struct dma_chan *chan,
                                           struct dma_tx_state *txstate)
 {
         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
         enum dma_status ret;
 
-        ret = dma_cookie_status(chan, cookie, txstate);
+        last_used = chan->cookie;
+        last_complete = mv_chan->completed_cookie;
+        mv_chan->is_complete_cookie = cookie;
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
         if (ret == DMA_SUCCESS) {
                 mv_xor_clean_completed_slots(mv_chan);
                 return ret;
         }
         mv_xor_slot_cleanup(mv_chan);
 
-        return dma_cookie_status(chan, cookie, txstate);
+        last_used = chan->cookie;
+        last_complete = mv_chan->completed_cookie;
+
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+        return dma_async_is_complete(cookie, last_complete, last_used);
 }
 
 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
@@ -828,42 +848,42 @@ static void mv_dump_xor_regs(struct mv_xor_chan *chan)
         u32 val;
 
         val = __raw_readl(XOR_CONFIG(chan));
-        dev_err(mv_chan_to_devp(chan),
-                "config       0x%08x.\n", val);
+        dev_printk(KERN_ERR, chan->device->common.dev,
+                   "config       0x%08x.\n", val);
 
         val = __raw_readl(XOR_ACTIVATION(chan));
-        dev_err(mv_chan_to_devp(chan),
-                "activation   0x%08x.\n", val);
+        dev_printk(KERN_ERR, chan->device->common.dev,
+                   "activation   0x%08x.\n", val);
 
         val = __raw_readl(XOR_INTR_CAUSE(chan));
-        dev_err(mv_chan_to_devp(chan),
-                "intr cause   0x%08x.\n", val);
+        dev_printk(KERN_ERR, chan->device->common.dev,
+                   "intr cause   0x%08x.\n", val);
 
         val = __raw_readl(XOR_INTR_MASK(chan));
-        dev_err(mv_chan_to_devp(chan),
-                "intr mask    0x%08x.\n", val);
+        dev_printk(KERN_ERR, chan->device->common.dev,
+                   "intr mask    0x%08x.\n", val);
 
         val = __raw_readl(XOR_ERROR_CAUSE(chan));
-        dev_err(mv_chan_to_devp(chan),
-                "error cause  0x%08x.\n", val);
+        dev_printk(KERN_ERR, chan->device->common.dev,
+                   "error cause  0x%08x.\n", val);
 
         val = __raw_readl(XOR_ERROR_ADDR(chan));
-        dev_err(mv_chan_to_devp(chan),
-                "error addr   0x%08x.\n", val);
+        dev_printk(KERN_ERR, chan->device->common.dev,
+                   "error addr   0x%08x.\n", val);
 }
 
 static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
                                          u32 intr_cause)
 {
         if (intr_cause & (1 << 4)) {
-             dev_dbg(mv_chan_to_devp(chan),
+             dev_dbg(chan->device->common.dev,
                      "ignore this error\n");
              return;
         }
 
-        dev_err(mv_chan_to_devp(chan),
-                "error on chan %d. intr cause 0x%08x.\n",
-                chan->idx, intr_cause);
+        dev_printk(KERN_ERR, chan->device->common.dev,
+                   "error on chan %d. intr cause 0x%08x.\n",
+                   chan->idx, intr_cause);
 
         mv_dump_xor_regs(chan);
         BUG();
@@ -874,7 +894,7 @@ static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
         struct mv_xor_chan *chan = data;
         u32 intr_cause = mv_chan_get_intr_cause(chan);
 
-        dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
+        dev_dbg(chan->device->common.dev, "intr cause %x\n", intr_cause);
 
         if (mv_is_err_intr(intr_cause))
                 mv_xor_err_interrupt_handler(chan, intr_cause);
@@ -901,7 +921,7 @@ static void mv_xor_issue_pending(struct dma_chan *chan)
  */
 #define MV_XOR_TEST_SIZE 2000
 
-static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
+static int __devinit mv_xor_memcpy_self_test(struct mv_xor_device *device)
 {
         int i;
         void *src, *dest;
@@ -910,6 +930,7 @@ static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
         dma_cookie_t cookie;
         struct dma_async_tx_descriptor *tx;
         int err = 0;
+        struct mv_xor_chan *mv_chan;
 
         src = kmalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
         if (!src)
@@ -925,7 +946,10 @@ static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
         for (i = 0; i < MV_XOR_TEST_SIZE; i++)
                 ((u8 *) src)[i] = (u8)i;
 
-        dma_chan = &mv_chan->dmachan;
+        /* Start copy, using first DMA channel */
+        dma_chan = container_of(device->common.channels.next,
+                                struct dma_chan,
+                                device_node);
         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
                 err = -ENODEV;
                 goto out;
@@ -946,17 +970,18 @@ static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
 
         if (mv_xor_status(dma_chan, cookie, NULL) !=
             DMA_SUCCESS) {
-                dev_err(dma_chan->device->dev,
-                        "Self-test copy timed out, disabling\n");
+                dev_printk(KERN_ERR, dma_chan->device->dev,
+                           "Self-test copy timed out, disabling\n");
                 err = -ENODEV;
                 goto free_resources;
         }
 
-        dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
+        mv_chan = to_mv_xor_chan(dma_chan);
+        dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
                                 MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
         if (memcmp(src, dest, MV_XOR_TEST_SIZE)) {
-                dev_err(dma_chan->device->dev,
-                        "Self-test copy failed compare, disabling\n");
+                dev_printk(KERN_ERR, dma_chan->device->dev,
+                           "Self-test copy failed compare, disabling\n");
                 err = -ENODEV;
                 goto free_resources;
         }
@@ -970,8 +995,8 @@ out:
 }
 
 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
-static int
-mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
+static int __devinit
+mv_xor_xor_self_test(struct mv_xor_device *device)
 {
         int i, src_idx;
         struct page *dest;
@@ -984,6 +1009,7 @@ mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
         u8 cmp_byte = 0;
         u32 cmp_word;
         int err = 0;
+        struct mv_xor_chan *mv_chan;
 
         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
@@ -1016,7 +1042,9 @@ mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
 
         memset(page_address(dest), 0, PAGE_SIZE);
 
-        dma_chan = &mv_chan->dmachan;
+        dma_chan = container_of(device->common.channels.next,
+                                struct dma_chan,
+                                device_node);
         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
                 err = -ENODEV;
                 goto out;
@@ -1040,21 +1068,22 @@ mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
 
         if (mv_xor_status(dma_chan, cookie, NULL) !=
             DMA_SUCCESS) {
-                dev_err(dma_chan->device->dev,
-                        "Self-test xor timed out, disabling\n");
+                dev_printk(KERN_ERR, dma_chan->device->dev,
+                           "Self-test xor timed out, disabling\n");
                 err = -ENODEV;
                 goto free_resources;
         }
 
-        dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
+        mv_chan = to_mv_xor_chan(dma_chan);
+        dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
                                 PAGE_SIZE, DMA_FROM_DEVICE);
         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
                 u32 *ptr = page_address(dest);
                 if (ptr[i] != cmp_word) {
-                        dev_err(dma_chan->device->dev,
-                                "Self-test xor failed compare, disabling."
-                                " index %d, data %x, expected %x\n", i,
-                                ptr[i], cmp_word);
+                        dev_printk(KERN_ERR, dma_chan->device->dev,
+                                   "Self-test xor failed compare, disabling."
+                                   " index %d, data %x, expected %x\n", i,
+                                   ptr[i], cmp_word);
                         err = -ENODEV;
                         goto free_resources;
                 }
@@ -1070,66 +1099,62 @@ out:
         return err;
 }
 
-/* This driver does not implement any of the optional DMA operations. */
-static int
-mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-               unsigned long arg)
-{
-        return -ENOSYS;
-}
-
-static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
+static int __devexit mv_xor_remove(struct platform_device *dev)
 {
+        struct mv_xor_device *device = platform_get_drvdata(dev);
         struct dma_chan *chan, *_chan;
-        struct device *dev = mv_chan->dmadev.dev;
+        struct mv_xor_chan *mv_chan;
+        struct mv_xor_platform_data *plat_data = dev->dev.platform_data;
 
-        dma_async_device_unregister(&mv_chan->dmadev);
+        dma_async_device_unregister(&device->common);
 
-        dma_free_coherent(dev, MV_XOR_POOL_SIZE,
-                          mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
+        dma_free_coherent(&dev->dev, plat_data->pool_size,
+                        device->dma_desc_pool_virt, device->dma_desc_pool);
 
-        list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
-                                 device_node) {
+        list_for_each_entry_safe(chan, _chan, &device->common.channels,
+                                device_node) {
+                mv_chan = to_mv_xor_chan(chan);
                 list_del(&chan->device_node);
         }
 
-        free_irq(mv_chan->irq, mv_chan);
-
         return 0;
 }
 
-static struct mv_xor_chan *
-mv_xor_channel_add(struct mv_xor_device *xordev,
-                   struct platform_device *pdev,
-                   int idx, dma_cap_mask_t cap_mask, int irq)
+static int __devinit mv_xor_probe(struct platform_device *pdev)
 {
         int ret = 0;
+        int irq;
+        struct mv_xor_device *adev;
         struct mv_xor_chan *mv_chan;
         struct dma_device *dma_dev;
+        struct mv_xor_platform_data *plat_data = pdev->dev.platform_data;
 
-        mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
-        if (!mv_chan) {
-                ret = -ENOMEM;
-                goto err_free_dma;
-        }
 
-        mv_chan->idx = idx;
-        mv_chan->irq = irq;
+        adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
+        if (!adev)
+                return -ENOMEM;
 
-        dma_dev = &mv_chan->dmadev;
+        dma_dev = &adev->common;
 
         /* allocate coherent memory for hardware descriptors
          * note: writecombine gives slightly better performance, but
          * requires that we explicitly flush the writes
          */
-        mv_chan->dma_desc_pool_virt =
-          dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE,
-                                 &mv_chan->dma_desc_pool, GFP_KERNEL);
-        if (!mv_chan->dma_desc_pool_virt)
-                return ERR_PTR(-ENOMEM);
+        adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
+                                                          plat_data->pool_size,
+                                                          &adev->dma_desc_pool,
+                                                          GFP_KERNEL);
+        if (!adev->dma_desc_pool_virt)
+                return -ENOMEM;
+
+        adev->id = plat_data->hw_id;
 
         /* discover transaction capabilites from the platform data */
-        dma_dev->cap_mask = cap_mask;
+        dma_dev->cap_mask = plat_data->cap_mask;
+        adev->pdev = pdev;
+        platform_set_drvdata(pdev, adev);
+
+        adev->shared = platform_get_drvdata(plat_data->shared);
 
         INIT_LIST_HEAD(&dma_dev->channels);
 
@@ -1138,7 +1163,6 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
         dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
         dma_dev->device_tx_status = mv_xor_status;
         dma_dev->device_issue_pending = mv_xor_issue_pending;
-        dma_dev->device_control = mv_xor_control;
         dma_dev->dev = &pdev->dev;
 
         /* set prep routines based on capability */
@@ -1151,7 +1175,15 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
                 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
         }
 
-        mv_chan->mmr_base = xordev->xor_base;
+        mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
+        if (!mv_chan) {
+                ret = -ENOMEM;
+                goto err_free_dma;
+        }
+        mv_chan->device = adev;
+        mv_chan->idx = plat_data->hw_id;
+        mv_chan->mmr_base = adev->shared->xor_base;
+
         if (!mv_chan->mmr_base) {
                 ret = -ENOMEM;
                 goto err_free_dma;
@@ -1162,8 +1194,14 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
         /* clear errors before enabling interrupts */
         mv_xor_device_clear_err_status(mv_chan);
 
-        ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
-                          0, dev_name(&pdev->dev), mv_chan);
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0) {
+                ret = irq;
+                goto err_free_dma;
+        }
+        ret = devm_request_irq(&pdev->dev, irq,
+                               mv_xor_interrupt_handler,
+                               0, dev_name(&pdev->dev), mv_chan);
         if (ret)
                 goto err_free_dma;
 
@@ -1175,26 +1213,25 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
         INIT_LIST_HEAD(&mv_chan->chain);
         INIT_LIST_HEAD(&mv_chan->completed_slots);
         INIT_LIST_HEAD(&mv_chan->all_slots);
-        mv_chan->dmachan.device = dma_dev;
-        dma_cookie_init(&mv_chan->dmachan);
+        mv_chan->common.device = dma_dev;
 
-        list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
+        list_add_tail(&mv_chan->common.device_node, &dma_dev->channels);
 
         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
-                ret = mv_xor_memcpy_self_test(mv_chan);
+                ret = mv_xor_memcpy_self_test(adev);
                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
                 if (ret)
-                        goto err_free_irq;
+                        goto err_free_dma;
         }
 
         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
-                ret = mv_xor_xor_self_test(mv_chan);
+                ret = mv_xor_xor_self_test(adev);
                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
                 if (ret)
-                        goto err_free_irq;
+                        goto err_free_dma;
         }
 
-        dev_info(&pdev->dev, "Marvell XOR: "
+        dev_printk(KERN_INFO, &pdev->dev, "Marvell XOR: "
           "( %s%s%s%s)\n",
           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
@@ -1202,21 +1239,20 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
 
         dma_async_device_register(dma_dev);
-        return mv_chan;
+        goto out;
 
-err_free_irq:
-        free_irq(mv_chan->irq, mv_chan);
  err_free_dma:
-        dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
-                          mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
-        return ERR_PTR(ret);
+        dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
+                        adev->dma_desc_pool_virt, adev->dma_desc_pool);
+ out:
+        return ret;
 }
 
 static void
-mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
-                         const struct mbus_dram_target_info *dram)
+mv_xor_conf_mbus_windows(struct mv_xor_shared_private *msp,
+                         struct mbus_dram_target_info *dram)
 {
-        void __iomem *base = xordev->xor_base;
+        void __iomem *base = msp->xor_base;
         u32 win_enable = 0;
         int i;
 
@@ -1228,7 +1264,7 @@ mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
         }
 
         for (i = 0; i < dram->num_cs; i++) {
-                const struct mbus_dram_window *cs = dram->cs + i;
+                struct mbus_dram_window *cs = dram->cs + i;
 
                 writel((cs->base & 0xffff0000) |
                        (cs->mbus_attr << 8) |
@@ -1241,179 +1277,84 @@ mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
 
         writel(win_enable, base + WINDOW_BAR_ENABLE(0));
         writel(win_enable, base + WINDOW_BAR_ENABLE(1));
-        writel(0, base + WINDOW_OVERRIDE_CTRL(0));
-        writel(0, base + WINDOW_OVERRIDE_CTRL(1));
 }
 
-static int mv_xor_probe(struct platform_device *pdev)
+static struct platform_driver mv_xor_driver = {
+        .probe          = mv_xor_probe,
+        .remove         = __devexit_p(mv_xor_remove),
+        .driver         = {
+                .owner  = THIS_MODULE,
+                .name   = MV_XOR_NAME,
+        },
+};
+
+static int mv_xor_shared_probe(struct platform_device *pdev)
 {
-        const struct mbus_dram_target_info *dram;
-        struct mv_xor_device *xordev;
-        struct mv_xor_platform_data *pdata = pdev->dev.platform_data;
+        struct mv_xor_platform_shared_data *msd = pdev->dev.platform_data;
+        struct mv_xor_shared_private *msp;
         struct resource *res;
-        int i, ret;
 
-        dev_notice(&pdev->dev, "Marvell XOR driver\n");
+        dev_printk(KERN_NOTICE, &pdev->dev, "Marvell shared XOR driver\n");
 
-        xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
-        if (!xordev)
+        msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
+        if (!msp)
                 return -ENOMEM;
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!res)
                 return -ENODEV;
 
-        xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
-                                        resource_size(res));
-        if (!xordev->xor_base)
+        msp->xor_base = devm_ioremap(&pdev->dev, res->start,
+                                     resource_size(res));
+        if (!msp->xor_base)
                 return -EBUSY;
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
         if (!res)
                 return -ENODEV;
 
-        xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
-                                             resource_size(res));
-        if (!xordev->xor_high_base)
+        msp->xor_high_base = devm_ioremap(&pdev->dev, res->start,
+                                          resource_size(res));
+        if (!msp->xor_high_base)
                 return -EBUSY;
 
-        platform_set_drvdata(pdev, xordev);
+        platform_set_drvdata(pdev, msp);
 
         /*
          * (Re-)program MBUS remapping windows if we are asked to.
          */
-        dram = mv_mbus_dram_info();
-        if (dram)
-                mv_xor_conf_mbus_windows(xordev, dram);
-
-        /* Not all platforms can gate the clock, so it is not
-         * an error if the clock does not exists.
-         */
-        xordev->clk = clk_get(&pdev->dev, NULL);
-        if (!IS_ERR(xordev->clk))
-                clk_prepare_enable(xordev->clk);
-
-        if (pdev->dev.of_node) {
-                struct device_node *np;
-                int i = 0;
-
-                for_each_child_of_node(pdev->dev.of_node, np) {
-                        dma_cap_mask_t cap_mask;
-                        int irq;
-
-                        dma_cap_zero(cap_mask);
-                        if (of_property_read_bool(np, "dmacap,memcpy"))
-                                dma_cap_set(DMA_MEMCPY, cap_mask);
-                        if (of_property_read_bool(np, "dmacap,xor"))
-                                dma_cap_set(DMA_XOR, cap_mask);
-                        if (of_property_read_bool(np, "dmacap,memset"))
-                                dma_cap_set(DMA_MEMSET, cap_mask);
-                        if (of_property_read_bool(np, "dmacap,interrupt"))
-                                dma_cap_set(DMA_INTERRUPT, cap_mask);
-
-                        irq = irq_of_parse_and_map(np, 0);
-                        if (!irq) {
-                                ret = -ENODEV;
-                                goto err_channel_add;
-                        }
-
-                        xordev->channels[i] =
-                                mv_xor_channel_add(xordev, pdev, i,
-                                                   cap_mask, irq);
-                        if (IS_ERR(xordev->channels[i])) {
-                                ret = PTR_ERR(xordev->channels[i]);
-                                xordev->channels[i] = NULL;
-                                irq_dispose_mapping(irq);
-                                goto err_channel_add;
-                        }
-
-                        i++;
-                }
-        } else if (pdata && pdata->channels) {
-                for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
-                        struct mv_xor_channel_data *cd;
-                        int irq;
-
-                        cd = &pdata->channels[i];
-                        if (!cd) {
-                                ret = -ENODEV;
-                                goto err_channel_add;
-                        }
-
-                        irq = platform_get_irq(pdev, i);
-                        if (irq < 0) {
-                                ret = irq;
-                                goto err_channel_add;
-                        }
-
-                        xordev->channels[i] =
-                                mv_xor_channel_add(xordev, pdev, i,
-                                                   cd->cap_mask, irq);
-                        if (IS_ERR(xordev->channels[i])) {
-                                ret = PTR_ERR(xordev->channels[i]);
-                                goto err_channel_add;
-                        }
-                }
-        }
+        if (msd != NULL && msd->dram != NULL)
+                mv_xor_conf_mbus_windows(msp, msd->dram);
 
         return 0;
-
-err_channel_add:
-        for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
-                if (xordev->channels[i]) {
-                        mv_xor_channel_remove(xordev->channels[i]);
-                        if (pdev->dev.of_node)
-                                irq_dispose_mapping(xordev->channels[i]->irq);
-                }
-
-        if (!IS_ERR(xordev->clk)) {
-                clk_disable_unprepare(xordev->clk);
-                clk_put(xordev->clk);
-        }
-
-        return ret;
 }
 
-static int mv_xor_remove(struct platform_device *pdev)
+static int mv_xor_shared_remove(struct platform_device *pdev)
 {
-        struct mv_xor_device *xordev = platform_get_drvdata(pdev);
-        int i;
-
-        for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
-                if (xordev->channels[i])
-                        mv_xor_channel_remove(xordev->channels[i]);
-        }
-
-        if (!IS_ERR(xordev->clk)) {
-                clk_disable_unprepare(xordev->clk);
-                clk_put(xordev->clk);
-        }
-
         return 0;
 }
 
-#ifdef CONFIG_OF
-static struct of_device_id mv_xor_dt_ids[] = {
-       { .compatible = "marvell,orion-xor", },
-       {},
-};
-MODULE_DEVICE_TABLE(of, mv_xor_dt_ids);
-#endif
-
-static struct platform_driver mv_xor_driver = {
-        .probe          = mv_xor_probe,
-        .remove         = mv_xor_remove,
+static struct platform_driver mv_xor_shared_driver = {
+        .probe          = mv_xor_shared_probe,
+        .remove         = mv_xor_shared_remove,
         .driver         = {
-                .owner          = THIS_MODULE,
-                .name           = MV_XOR_NAME,
-                .of_match_table = of_match_ptr(mv_xor_dt_ids),
+                .owner  = THIS_MODULE,
+                .name   = MV_XOR_SHARED_NAME,
         },
 };
 
 
 static int __init mv_xor_init(void)
 {
-        return platform_driver_register(&mv_xor_driver);
+        int rc;
+
+        rc = platform_driver_register(&mv_xor_shared_driver);
+        if (!rc) {
+                rc = platform_driver_register(&mv_xor_driver);
+                if (rc)
+                        platform_driver_unregister(&mv_xor_shared_driver);
+        }
+        return rc;
 }
 module_init(mv_xor_init);
 
@@ -1422,6 +1363,7 @@ module_init(mv_xor_init);
 static void __exit mv_xor_exit(void)
 {
         platform_driver_unregister(&mv_xor_driver);
+        platform_driver_unregister(&mv_xor_shared_driver);
         return;
 }
 
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h
index c632a4761fc..977b592e976 100644
--- a/drivers/dma/mv_xor.h
+++ b/drivers/dma/mv_xor.h
@@ -24,10 +24,8 @@
 #include <linux/interrupt.h>
 
 #define USE_TIMER
-#define MV_XOR_POOL_SIZE                PAGE_SIZE
 #define MV_XOR_SLOT_SIZE                64
 #define MV_XOR_THRESHOLD                1
-#define MV_XOR_MAX_CHANNELS             2
 
 #define XOR_OPERATION_MODE_XOR          0
 #define XOR_OPERATION_MODE_MEMCPY       2
@@ -53,18 +51,34 @@
 #define WINDOW_SIZE(w)          (0x270 + ((w) << 2))
 #define WINDOW_REMAP_HIGH(w)    (0x290 + ((w) << 2))
 #define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
-#define WINDOW_OVERRIDE_CTRL(chan)      (0x2A0 + ((chan) << 2))
 
+struct mv_xor_shared_private {
+        void __iomem    *xor_base;
+        void __iomem    *xor_high_base;
+};
+
+
+/**
+ * struct mv_xor_device - internal representation of a XOR device
+ * @pdev: Platform device
+ * @id: HW XOR Device selector
+ * @dma_desc_pool: base of DMA descriptor region (DMA address)
+ * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
+ * @common: embedded struct dma_device
+ */
 struct mv_xor_device {
-        void __iomem         *xor_base;
-        void __iomem         *xor_high_base;
-        struct clk           *clk;
-        struct mv_xor_chan   *channels[MV_XOR_MAX_CHANNELS];
+        struct platform_device          *pdev;
+        int                             id;
+        dma_addr_t                      dma_desc_pool;
+        void                            *dma_desc_pool_virt;
+        struct dma_device               common;
+        struct mv_xor_shared_private    *shared;
 };
 
 /**
  * struct mv_xor_chan - internal representation of a XOR channel
  * @pending: allows batching of hardware operations
+ * @completed_cookie: identifier for the most recently completed operation
  * @lock: serializes enqueue/dequeue operations to the descriptors pool
  * @mmr_base: memory mapped register base
  * @idx: the index of the xor channel
@@ -79,18 +93,15 @@ struct mv_xor_device {
  */
 struct mv_xor_chan {
         int                     pending;
+        dma_cookie_t            completed_cookie;
         spinlock_t              lock; /* protects the descriptor slot pool */
         void __iomem            *mmr_base;
         unsigned int            idx;
-        int                     irq;
         enum dma_transaction_type       current_type;
         struct list_head        chain;
         struct list_head        completed_slots;
-        dma_addr_t              dma_desc_pool;
-        void                    *dma_desc_pool_virt;
-        size_t                  pool_size;
-        struct dma_device       dmadev;
-        struct dma_chan         dmachan;
+        struct mv_xor_device    *device;
+        struct dma_chan         common;
         struct mv_xor_desc_slot *last_used;
         struct list_head        all_slots;
         int                     slots_allocated;
@@ -98,6 +109,7 @@ struct mv_xor_chan {
 #ifdef USE_TIMER
         unsigned long           cleanup_time;
         u32                     current_on_last_cleanup;
+        dma_cookie_t            is_complete_cookie;
 #endif
 };
 
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 9f02e794b12..be641cbd36f 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -22,15 +22,11 @@
 #include <linux/platform_device.h>
 #include <linux/dmaengine.h>
 #include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/fsl/mxs-dma.h>
-#include <linux/stmp_device.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
 
 #include <asm/irq.h>
-
-#include "dmaengine.h"
+#include <mach/mxs.h>
+#include <mach/dma.h>
+#include <mach/common.h>
 
 /*
  * NOTE: The term "PIO" throughout the mxs-dma implementation means
@@ -38,25 +34,29 @@
  * dma can program the controller registers of peripheral devices.
  */
 
-#define dma_is_apbh(mxs_dma)    ((mxs_dma)->type == MXS_DMA_APBH)
-#define apbh_is_old(mxs_dma)    ((mxs_dma)->dev_id == IMX23_DMA)
+#define MXS_DMA_APBH            0
+#define MXS_DMA_APBX            1
+#define dma_is_apbh()           (mxs_dma->dev_id == MXS_DMA_APBH)
+
+#define APBH_VERSION_LATEST     3
+#define apbh_is_old()           (mxs_dma->version < APBH_VERSION_LATEST)
 
 #define HW_APBHX_CTRL0                          0x000
 #define BM_APBH_CTRL0_APB_BURST8_EN             (1 << 29)
 #define BM_APBH_CTRL0_APB_BURST_EN              (1 << 28)
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
 #define BP_APBH_CTRL0_RESET_CHANNEL             16
 #define HW_APBHX_CTRL1                          0x010
 #define HW_APBHX_CTRL2                          0x020
 #define HW_APBHX_CHANNEL_CTRL                   0x030
 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL     16
-/*
- * The offset of NXTCMDAR register is different per both dma type and version,
- * while stride for each channel is all the same 0x70.
- */
-#define HW_APBHX_CHn_NXTCMDAR(d, n) \
-        (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
-#define HW_APBHX_CHn_SEMA(d, n) \
-        (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
+#define HW_APBH_VERSION                         (cpu_is_mx23() ? 0x3f0 : 0x800)
+#define HW_APBX_VERSION                         0x800
+#define BP_APBHX_VERSION_MAJOR                  24
+#define HW_APBHX_CHn_NXTCMDAR(n) \
+        (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
+#define HW_APBHX_CHn_SEMA(n) \
+        (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)
 
 /*
  * ccw bits definitions
@@ -101,8 +101,7 @@ struct mxs_dma_ccw {
         u32             pio_words[MXS_PIO_WORDS];
 };
 
-#define CCW_BLOCK_SIZE  (4 * PAGE_SIZE)
-#define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
+#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
 
 struct mxs_dma_chan {
         struct mxs_dma_engine           *mxs_dma;
@@ -112,7 +111,7 @@ struct mxs_dma_chan {
         int                             chan_irq;
         struct mxs_dma_ccw              *ccw;
         dma_addr_t                      ccw_phys;
-        int                             desc_count;
+        dma_cookie_t                    last_completed;
         enum dma_status                 status;
         unsigned int                    flags;
 #define MXS_DMA_SG_LOOP                 (1 << 0)
@@ -121,19 +120,9 @@ struct mxs_dma_chan {
 #define MXS_DMA_CHANNELS                16
 #define MXS_DMA_CHANNELS_MASK           0xffff
 
-enum mxs_dma_devtype {
-        MXS_DMA_APBH,
-        MXS_DMA_APBX,
-};
-
-enum mxs_dma_id {
-        IMX23_DMA,
-        IMX28_DMA,
-};
-
 struct mxs_dma_engine {
-        enum mxs_dma_id                 dev_id;
-        enum mxs_dma_devtype            type;
+        int                             dev_id;
+        unsigned int                    version;
         void __iomem                    *base;
         struct clk                      *clk;
         struct dma_device               dma_device;
@@ -141,88 +130,17 @@ struct mxs_dma_engine {
         struct mxs_dma_chan             mxs_chans[MXS_DMA_CHANNELS];
 };
 
-struct mxs_dma_type {
-        enum mxs_dma_id id;
-        enum mxs_dma_devtype type;
-};
-
-static struct mxs_dma_type mxs_dma_types[] = {
-        {
-                .id = IMX23_DMA,
-                .type = MXS_DMA_APBH,
-        }, {
-                .id = IMX23_DMA,
-                .type = MXS_DMA_APBX,
-        }, {
-                .id = IMX28_DMA,
-                .type = MXS_DMA_APBH,
-        }, {
-                .id = IMX28_DMA,
-                .type = MXS_DMA_APBX,
-        }
-};
-
-static struct platform_device_id mxs_dma_ids[] = {
-        {
-                .name = "imx23-dma-apbh",
-                .driver_data = (kernel_ulong_t) &mxs_dma_types[0],
-        }, {
-                .name = "imx23-dma-apbx",
-                .driver_data = (kernel_ulong_t) &mxs_dma_types[1],
-        }, {
-                .name = "imx28-dma-apbh",
-                .driver_data = (kernel_ulong_t) &mxs_dma_types[2],
-        }, {
-                .name = "imx28-dma-apbx",
-                .driver_data = (kernel_ulong_t) &mxs_dma_types[3],
-        }, {
-                /* end of list */
-        }
-};
-
-static const struct of_device_id mxs_dma_dt_ids[] = {
-        { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], },
-        { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], },
-        { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], },
-        { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], },
-        { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
-
-static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
-{
-        return container_of(chan, struct mxs_dma_chan, chan);
-}
-
-int mxs_dma_is_apbh(struct dma_chan *chan)
-{
-        struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
-        struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
-
-        return dma_is_apbh(mxs_dma);
-}
-EXPORT_SYMBOL_GPL(mxs_dma_is_apbh);
-
-int mxs_dma_is_apbx(struct dma_chan *chan)
-{
-        struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
-        struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
-
-        return !dma_is_apbh(mxs_dma);
-}
-EXPORT_SYMBOL_GPL(mxs_dma_is_apbx);
-
 static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
 {
         struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
         int chan_id = mxs_chan->chan.chan_id;
 
-        if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
+        if (dma_is_apbh() && apbh_is_old())
                 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
-                        mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
+                        mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
         else
                 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
-                        mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
+                        mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
 }
 
 static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
@@ -232,14 +150,37 @@ static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
 
         /* set cmd_addr up */
         writel(mxs_chan->ccw_phys,
-                mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
+                mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));
+
+        /* enable apbh channel clock */
+        if (dma_is_apbh()) {
+                if (apbh_is_old())
+                        writel(1 << (chan_id + BP_APBH_CTRL0_CLKGATE_CHANNEL),
+                                mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
+                else
+                        writel(1 << chan_id,
+                                mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
+        }
 
         /* write 1 to SEMA to kick off the channel */
-        writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
+        writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
 }
 
 static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
 {
+        struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
+        int chan_id = mxs_chan->chan.chan_id;
+
+        /* disable apbh channel clock */
+        if (dma_is_apbh()) {
+                if (apbh_is_old())
+                        writel(1 << (chan_id + BP_APBH_CTRL0_CLKGATE_CHANNEL),
+                                mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
+                else
+                        writel(1 << chan_id,
+                                mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
+        }
+
         mxs_chan->status = DMA_SUCCESS;
 }
 
@@ -249,12 +190,12 @@ static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
         int chan_id = mxs_chan->chan.chan_id;
 
         /* freeze the channel */
-        if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
+        if (dma_is_apbh() && apbh_is_old())
                 writel(1 << chan_id,
-                        mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
+                        mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
         else
                 writel(1 << chan_id,
-                        mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
+                        mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
 
         mxs_chan->status = DMA_PAUSED;
 }
@@ -265,19 +206,41 @@ static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
         int chan_id = mxs_chan->chan.chan_id;
 
         /* unfreeze the channel */
-        if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
+        if (dma_is_apbh() && apbh_is_old())
                 writel(1 << chan_id,
-                        mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
+                        mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
         else
                 writel(1 << chan_id,
-                        mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
+                        mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
 
         mxs_chan->status = DMA_IN_PROGRESS;
 }
 
+static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan)
+{
+        dma_cookie_t cookie = mxs_chan->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        mxs_chan->chan.cookie = cookie;
+        mxs_chan->desc.cookie = cookie;
+
+        return cookie;
+}
+
+static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
+{
+        return container_of(chan, struct mxs_dma_chan, chan);
+}
+
 static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
-        return dma_cookie_assign(tx);
+        struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan);
+
+        mxs_dma_enable_chan(mxs_chan);
+
+        return mxs_dma_assign_cookie(mxs_chan);
 }
 
 static void mxs_dma_tasklet(unsigned long data)
@@ -296,16 +259,16 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
         /* completion status */
         stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
         stat1 &= MXS_DMA_CHANNELS_MASK;
-        writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
+        writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
 
         /* error status */
         stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
-        writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
+        writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
 
         /*
          * When both completion and error of termination bits set at the
          * same time, we do not take it as an error.  IOW, it only becomes
-         * an error we need to handle here in case of either it's (1) a bus
+         * an error we need to handler here in case of ether it's (1) an bus
          * error or (2) a termination error with no completion.
          */
         stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
@@ -334,7 +297,7 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
                 stat1 &= ~(1 << channel);
 
                 if (mxs_chan->status == DMA_SUCCESS)
-                        dma_cookie_complete(&mxs_chan->desc);
+                        mxs_chan->last_completed = mxs_chan->desc.cookie;
 
                 /* schedule tasklet on this channel */
                 tasklet_schedule(&mxs_chan->tasklet);
@@ -355,15 +318,14 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
 
         mxs_chan->chan_irq = data->chan_irq;
 
-        mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev,
-                                CCW_BLOCK_SIZE, &mxs_chan->ccw_phys,
-                                GFP_KERNEL);
+        mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
+                                &mxs_chan->ccw_phys, GFP_KERNEL);
         if (!mxs_chan->ccw) {
                 ret = -ENOMEM;
                 goto err_alloc;
         }
 
-        memset(mxs_chan->ccw, 0, CCW_BLOCK_SIZE);
+        memset(mxs_chan->ccw, 0, PAGE_SIZE);
 
         if (mxs_chan->chan_irq != NO_IRQ) {
                 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
@@ -372,7 +334,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
                         goto err_irq;
         }
 
-        ret = clk_prepare_enable(mxs_dma->clk);
+        ret = clk_enable(mxs_dma->clk);
         if (ret)
                 goto err_clk;
 
@@ -389,7 +351,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
 err_clk:
         free_irq(mxs_chan->chan_irq, mxs_dma);
 err_irq:
-        dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
+        dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
                         mxs_chan->ccw, mxs_chan->ccw_phys);
 err_alloc:
         return ret;
@@ -404,38 +366,16 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan)
 
         free_irq(mxs_chan->chan_irq, mxs_dma);
 
-        dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
+        dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
                         mxs_chan->ccw, mxs_chan->ccw_phys);
 
-        clk_disable_unprepare(mxs_dma->clk);
+        clk_disable(mxs_dma->clk);
 }
 
-/*
- * How to use the flags for ->device_prep_slave_sg() :
- *    [1] If there is only one DMA command in the DMA chain, the code should be:
- *            ......
- *            ->device_prep_slave_sg(DMA_CTRL_ACK);
- *            ......
- *    [2] If there are two DMA commands in the DMA chain, the code should be
- *            ......
- *            ->device_prep_slave_sg(0);
- *            ......
- *            ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
- *            ......
- *    [3] If there are more than two DMA commands in the DMA chain, the code
- *        should be:
- *            ......
- *            ->device_prep_slave_sg(0);                                // First
- *            ......
- *            ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
- *            ......
- *            ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
- *            ......
- */
 static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
                 struct dma_chan *chan, struct scatterlist *sgl,
-                unsigned int sg_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long append)
 {
         struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
         struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
@@ -443,8 +383,7 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
         struct scatterlist *sg;
         int i, j;
         u32 *pio;
-        bool append = flags & DMA_PREP_INTERRUPT;
-        int idx = append ? mxs_chan->desc_count : 0;
+        static int idx;
 
         if (mxs_chan->status == DMA_IN_PROGRESS && !append)
                 return NULL;
@@ -470,11 +409,12 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
                 ccw->bits |= CCW_CHAIN;
                 ccw->bits &= ~CCW_IRQ;
                 ccw->bits &= ~CCW_DEC_SEM;
+                ccw->bits &= ~CCW_WAIT4END;
         } else {
                 idx = 0;
         }
 
-        if (direction == DMA_TRANS_NONE) {
+        if (direction == DMA_NONE) {
                 ccw = &mxs_chan->ccw[idx++];
                 pio = (u32 *) sgl;
 
@@ -484,17 +424,16 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
                 ccw->bits = 0;
                 ccw->bits |= CCW_IRQ;
                 ccw->bits |= CCW_DEC_SEM;
-                if (flags & DMA_CTRL_ACK)
-                        ccw->bits |= CCW_WAIT4END;
+                ccw->bits |= CCW_WAIT4END;
                 ccw->bits |= CCW_HALT_ON_TERM;
                 ccw->bits |= CCW_TERM_FLUSH;
                 ccw->bits |= BF_CCW(sg_len, PIO_NUM);
                 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
         } else {
                 for_each_sg(sgl, sg, sg_len, i) {
-                        if (sg_dma_len(sg) > MAX_XFER_BYTES) {
+                        if (sg->length > MAX_XFER_BYTES) {
                                 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
-                                                sg_dma_len(sg), MAX_XFER_BYTES);
+                                                sg->length, MAX_XFER_BYTES);
                                 goto err_out;
                         }
 
@@ -502,13 +441,13 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
 
                         ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
                         ccw->bufaddr = sg->dma_address;
-                        ccw->xfer_bytes = sg_dma_len(sg);
+                        ccw->xfer_bytes = sg->length;
 
                         ccw->bits = 0;
                         ccw->bits |= CCW_CHAIN;
                         ccw->bits |= CCW_HALT_ON_TERM;
                         ccw->bits |= CCW_TERM_FLUSH;
-                        ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
+                        ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ?
                                         MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
                                         COMMAND);
 
@@ -516,12 +455,10 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
                                 ccw->bits &= ~CCW_CHAIN;
                                 ccw->bits |= CCW_IRQ;
                                 ccw->bits |= CCW_DEC_SEM;
-                                if (flags & DMA_CTRL_ACK)
-                                        ccw->bits |= CCW_WAIT4END;
+                                ccw->bits |= CCW_WAIT4END;
                         }
                 }
         }
-        mxs_chan->desc_count = idx;
 
         return &mxs_chan->desc;
 
@@ -532,8 +469,7 @@ err_out:
 
 static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
-                size_t period_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                size_t period_len, enum dma_data_direction direction)
 {
         struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
         struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
@@ -576,7 +512,7 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
                 ccw->bits |= CCW_IRQ;
                 ccw->bits |= CCW_HALT_ON_TERM;
                 ccw->bits |= CCW_TERM_FLUSH;
-                ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
+                ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ?
                                 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
 
                 dma_addr += period_len;
@@ -584,7 +520,6 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
 
                 i++;
         }
-        mxs_chan->desc_count = i;
 
         return &mxs_chan->desc;
 
@@ -601,8 +536,8 @@ static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
         switch (cmd) {
         case DMA_TERMINATE_ALL:
-                mxs_dma_reset_chan(mxs_chan);
                 mxs_dma_disable_chan(mxs_chan);
+                mxs_dma_reset_chan(mxs_chan);
                 break;
         case DMA_PAUSE:
                 mxs_dma_pause_chan(mxs_chan);
@@ -624,52 +559,60 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
         dma_cookie_t last_used;
 
         last_used = chan->cookie;
-        dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
+        dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0);
 
         return mxs_chan->status;
 }
 
 static void mxs_dma_issue_pending(struct dma_chan *chan)
 {
-        struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
-
-        mxs_dma_enable_chan(mxs_chan);
+        /*
+         * Nothing to do. We only have a single descriptor.
+         */
 }
 
 static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
 {
         int ret;
 
-        ret = clk_prepare_enable(mxs_dma->clk);
+        ret = clk_enable(mxs_dma->clk);
         if (ret)
-                return ret;
+                goto err_out;
 
-        ret = stmp_reset_block(mxs_dma->base);
+        ret = mxs_reset_block(mxs_dma->base);
         if (ret)
                 goto err_out;
 
+        /* only major version matters */
+        mxs_dma->version = readl(mxs_dma->base +
+                                ((mxs_dma->dev_id == MXS_DMA_APBX) ?
+                                HW_APBX_VERSION : HW_APBH_VERSION)) >>
+                                BP_APBHX_VERSION_MAJOR;
+
         /* enable apbh burst */
-        if (dma_is_apbh(mxs_dma)) {
+        if (dma_is_apbh()) {
                 writel(BM_APBH_CTRL0_APB_BURST_EN,
-                        mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
+                        mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
                 writel(BM_APBH_CTRL0_APB_BURST8_EN,
-                        mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
+                        mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
         }
 
         /* enable irq for all the channels */
         writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
-                mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
+                mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
+
+        clk_disable(mxs_dma->clk);
+
+        return 0;
 
 err_out:
-        clk_disable_unprepare(mxs_dma->clk);
         return ret;
 }
 
 static int __init mxs_dma_probe(struct platform_device *pdev)
 {
-        const struct platform_device_id *id_entry;
-        const struct of_device_id *of_id;
-        const struct mxs_dma_type *dma_type;
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(pdev);
         struct mxs_dma_engine *mxs_dma;
         struct resource *iores;
         int ret, i;
@@ -678,15 +621,7 @@ static int __init mxs_dma_probe(struct platform_device *pdev)
         if (!mxs_dma)
                 return -ENOMEM;
 
-        of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
-        if (of_id)
-                id_entry = of_id->data;
-        else
-                id_entry = platform_get_device_id(pdev);
-
-        dma_type = (struct mxs_dma_type *)id_entry->driver_data;
-        mxs_dma->type = dma_type->type;
-        mxs_dma->dev_id = dma_type->id;
+        mxs_dma->dev_id = id_entry->driver_data;
 
         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
@@ -719,7 +654,6 @@ static int __init mxs_dma_probe(struct platform_device *pdev)
 
                 mxs_chan->mxs_dma = mxs_dma;
                 mxs_chan->chan.device = &mxs_dma->dma_device;
-                dma_cookie_init(&mxs_chan->chan);
 
                 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
                              (unsigned long) mxs_chan);
@@ -769,12 +703,23 @@ err_request_region:
         return ret;
 }
 
+static struct platform_device_id mxs_dma_type[] = {
+        {
+                .name = "mxs-dma-apbh",
+                .driver_data = MXS_DMA_APBH,
+        }, {
+                .name = "mxs-dma-apbx",
+                .driver_data = MXS_DMA_APBX,
+        }, {
+                /* end of list */
+        }
+};
+
 static struct platform_driver mxs_dma_driver = {
         .driver         = {
                 .name   = "mxs-dma",
-                .of_match_table = mxs_dma_dt_ids,
         },
-        .id_table       = mxs_dma_ids,
+        .id_table       = mxs_dma_type,
 };
 
 static int __init mxs_dma_module_init(void)
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
deleted file mode 100644
index 5a31264f2bd..00000000000
--- a/drivers/dma/omap-dma.c
+++ /dev/null
@@ -1,695 +0,0 @@
-/*
- * OMAP DMAengine support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/dmaengine.h>
-#include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/omap-dma.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-#include "virt-dma.h"
-
-struct omap_dmadev {
-        struct dma_device ddev;
-        spinlock_t lock;
-        struct tasklet_struct task;
-        struct list_head pending;
-};
-
-struct omap_chan {
-        struct virt_dma_chan vc;
-        struct list_head node;
-
-        struct dma_slave_config cfg;
-        unsigned dma_sig;
-        bool cyclic;
-        bool paused;
-
-        int dma_ch;
-        struct omap_desc *desc;
-        unsigned sgidx;
-};
-
-struct omap_sg {
-        dma_addr_t addr;
-        uint32_t en;            /* number of elements (24-bit) */
-        uint32_t fn;            /* number of frames (16-bit) */
-};
-
-struct omap_desc {
-        struct virt_dma_desc vd;
-        enum dma_transfer_direction dir;
-        dma_addr_t dev_addr;
-
-        int16_t fi;             /* for OMAP_DMA_SYNC_PACKET */
-        uint8_t es;             /* OMAP_DMA_DATA_TYPE_xxx */
-        uint8_t sync_mode;      /* OMAP_DMA_SYNC_xxx */
-        uint8_t sync_type;      /* OMAP_DMA_xxx_SYNC* */
-        uint8_t periph_port;    /* Peripheral port */
-
-        unsigned sglen;
-        struct omap_sg sg[0];
-};
-
-static const unsigned es_bytes[] = {
-        [OMAP_DMA_DATA_TYPE_S8] = 1,
-        [OMAP_DMA_DATA_TYPE_S16] = 2,
-        [OMAP_DMA_DATA_TYPE_S32] = 4,
-};
-
-static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
-{
-        return container_of(d, struct omap_dmadev, ddev);
-}
-
-static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
-{
-        return container_of(c, struct omap_chan, vc.chan);
-}
-
-static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
-{
-        return container_of(t, struct omap_desc, vd.tx);
-}
-
-static void omap_dma_desc_free(struct virt_dma_desc *vd)
-{
-        kfree(container_of(vd, struct omap_desc, vd));
-}
-
-static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
-        unsigned idx)
-{
-        struct omap_sg *sg = d->sg + idx;
-
-        if (d->dir == DMA_DEV_TO_MEM)
-                omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
-                        OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
-        else
-                omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
-                        OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
-
-        omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn,
-                d->sync_mode, c->dma_sig, d->sync_type);
-
-        omap_start_dma(c->dma_ch);
-}
-
-static void omap_dma_start_desc(struct omap_chan *c)
-{
-        struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
-        struct omap_desc *d;
-
-        if (!vd) {
-                c->desc = NULL;
-                return;
-        }
-
-        list_del(&vd->node);
-
-        c->desc = d = to_omap_dma_desc(&vd->tx);
-        c->sgidx = 0;
-
-        if (d->dir == DMA_DEV_TO_MEM)
-                omap_set_dma_src_params(c->dma_ch, d->periph_port,
-                        OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
-        else
-                omap_set_dma_dest_params(c->dma_ch, d->periph_port,
-                        OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
-
-        omap_dma_start_sg(c, d, 0);
-}
-
-static void omap_dma_callback(int ch, u16 status, void *data)
-{
-        struct omap_chan *c = data;
-        struct omap_desc *d;
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->vc.lock, flags);
-        d = c->desc;
-        if (d) {
-                if (!c->cyclic) {
-                        if (++c->sgidx < d->sglen) {
-                                omap_dma_start_sg(c, d, c->sgidx);
-                        } else {
-                                omap_dma_start_desc(c);
-                                vchan_cookie_complete(&d->vd);
-                        }
-                } else {
-                        vchan_cyclic_callback(&d->vd);
-                }
-        }
-        spin_unlock_irqrestore(&c->vc.lock, flags);
-}
-
-/*
- * This callback schedules all pending channels.  We could be more
- * clever here by postponing allocation of the real DMA channels to
- * this point, and freeing them when our virtual channel becomes idle.
- *
- * We would then need to deal with 'all channels in-use'
- */
-static void omap_dma_sched(unsigned long data)
-{
-        struct omap_dmadev *d = (struct omap_dmadev *)data;
-        LIST_HEAD(head);
-
-        spin_lock_irq(&d->lock);
-        list_splice_tail_init(&d->pending, &head);
-        spin_unlock_irq(&d->lock);
-
-        while (!list_empty(&head)) {
-                struct omap_chan *c = list_first_entry(&head,
-                        struct omap_chan, node);
-
-                spin_lock_irq(&c->vc.lock);
-                list_del_init(&c->node);
-                omap_dma_start_desc(c);
-                spin_unlock_irq(&c->vc.lock);
-        }
-}
-
-static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
-{
-        struct omap_chan *c = to_omap_dma_chan(chan);
-
-        dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);
-
-        return omap_request_dma(c->dma_sig, "DMA engine",
-                omap_dma_callback, c, &c->dma_ch);
-}
-
-static void omap_dma_free_chan_resources(struct dma_chan *chan)
-{
-        struct omap_chan *c = to_omap_dma_chan(chan);
-
-        vchan_free_chan_resources(&c->vc);
-        omap_free_dma(c->dma_ch);
-
-        dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
-}
-
-static size_t omap_dma_sg_size(struct omap_sg *sg)
-{
-        return sg->en * sg->fn;
-}
-
-static size_t omap_dma_desc_size(struct omap_desc *d)
-{
-        unsigned i;
-        size_t size;
-
-        for (size = i = 0; i < d->sglen; i++)
-                size += omap_dma_sg_size(&d->sg[i]);
-
-        return size * es_bytes[d->es];
-}
-
-static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
-{
-        unsigned i;
-        size_t size, es_size = es_bytes[d->es];
-
-        for (size = i = 0; i < d->sglen; i++) {
-                size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size;
-
-                if (size)
-                        size += this_size;
-                else if (addr >= d->sg[i].addr &&
-                         addr < d->sg[i].addr + this_size)
-                        size += d->sg[i].addr + this_size - addr;
-        }
-        return size;
-}
-
-static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
-        dma_cookie_t cookie, struct dma_tx_state *txstate)
-{
-        struct omap_chan *c = to_omap_dma_chan(chan);
-        struct virt_dma_desc *vd;
-        enum dma_status ret;
-        unsigned long flags;
-
-        ret = dma_cookie_status(chan, cookie, txstate);
-        if (ret == DMA_SUCCESS || !txstate)
-                return ret;
-
-        spin_lock_irqsave(&c->vc.lock, flags);
-        vd = vchan_find_desc(&c->vc, cookie);
-        if (vd) {
-                txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx));
-        } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
-                struct omap_desc *d = c->desc;
-                dma_addr_t pos;
-
-                if (d->dir == DMA_MEM_TO_DEV)
-                        pos = omap_get_dma_src_pos(c->dma_ch);
-                else if (d->dir == DMA_DEV_TO_MEM)
-                        pos = omap_get_dma_dst_pos(c->dma_ch);
-                else
-                        pos = 0;
-
-                txstate->residue = omap_dma_desc_size_pos(d, pos);
-        } else {
-                txstate->residue = 0;
-        }
-        spin_unlock_irqrestore(&c->vc.lock, flags);
-
-        return ret;
-}
-
-static void omap_dma_issue_pending(struct dma_chan *chan)
-{
-        struct omap_chan *c = to_omap_dma_chan(chan);
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->vc.lock, flags);
-        if (vchan_issue_pending(&c->vc) && !c->desc) {
-                struct omap_dmadev *d = to_omap_dma_dev(chan->device);
-                spin_lock(&d->lock);
-                if (list_empty(&c->node))
-                        list_add_tail(&c->node, &d->pending);
-                spin_unlock(&d->lock);
-                tasklet_schedule(&d->task);
-        }
-        spin_unlock_irqrestore(&c->vc.lock, flags);
-}
-
-static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
-        struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
-        enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
-{
-        struct omap_chan *c = to_omap_dma_chan(chan);
-        enum dma_slave_buswidth dev_width;
-        struct scatterlist *sgent;
-        struct omap_desc *d;
-        dma_addr_t dev_addr;
-        unsigned i, j = 0, es, en, frame_bytes, sync_type;
-        u32 burst;
-
-        if (dir == DMA_DEV_TO_MEM) {
-                dev_addr = c->cfg.src_addr;
-                dev_width = c->cfg.src_addr_width;
-                burst = c->cfg.src_maxburst;
-                sync_type = OMAP_DMA_SRC_SYNC;
-        } else if (dir == DMA_MEM_TO_DEV) {
-                dev_addr = c->cfg.dst_addr;
-                dev_width = c->cfg.dst_addr_width;
-                burst = c->cfg.dst_maxburst;
-                sync_type = OMAP_DMA_DST_SYNC;
-        } else {
-                dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
-                return NULL;
-        }
-
-        /* Bus width translates to the element size (ES) */
-        switch (dev_width) {
-        case DMA_SLAVE_BUSWIDTH_1_BYTE:
-                es = OMAP_DMA_DATA_TYPE_S8;
-                break;
-        case DMA_SLAVE_BUSWIDTH_2_BYTES:
-                es = OMAP_DMA_DATA_TYPE_S16;
-                break;
-        case DMA_SLAVE_BUSWIDTH_4_BYTES:
-                es = OMAP_DMA_DATA_TYPE_S32;
-                break;
-        default: /* not reached */
-                return NULL;
-        }
-
-        /* Now allocate and setup the descriptor. */
-        d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
-        if (!d)
-                return NULL;
-
-        d->dir = dir;
-        d->dev_addr = dev_addr;
-        d->es = es;
-        d->sync_mode = OMAP_DMA_SYNC_FRAME;
-        d->sync_type = sync_type;
-        d->periph_port = OMAP_DMA_PORT_TIPB;
-
-        /*
-         * Build our scatterlist entries: each contains the address,
-         * the number of elements (EN) in each frame, and the number of
-         * frames (FN).  Number of bytes for this entry = ES * EN * FN.
-         *
-         * Burst size translates to number of elements with frame sync.
-         * Note: DMA engine defines burst to be the number of dev-width
-         * transfers.
-         */
-        en = burst;
-        frame_bytes = es_bytes[es] * en;
-        for_each_sg(sgl, sgent, sglen, i) {
-                d->sg[j].addr = sg_dma_address(sgent);
-                d->sg[j].en = en;
-                d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
-                j++;
-        }
-
-        d->sglen = j;
-
-        return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
-}
-
-static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
-        struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
-        size_t period_len, enum dma_transfer_direction dir, unsigned long flags,
-        void *context)
-{
-        struct omap_chan *c = to_omap_dma_chan(chan);
-        enum dma_slave_buswidth dev_width;
-        struct omap_desc *d;
-        dma_addr_t dev_addr;
-        unsigned es, sync_type;
-        u32 burst;
-
-        if (dir == DMA_DEV_TO_MEM) {
-                dev_addr = c->cfg.src_addr;
-                dev_width = c->cfg.src_addr_width;
-                burst = c->cfg.src_maxburst;
-                sync_type = OMAP_DMA_SRC_SYNC;
-        } else if (dir == DMA_MEM_TO_DEV) {
-                dev_addr = c->cfg.dst_addr;
-                dev_width = c->cfg.dst_addr_width;
-                burst = c->cfg.dst_maxburst;
-                sync_type = OMAP_DMA_DST_SYNC;
-        } else {
-                dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
-                return NULL;
-        }
-
-        /* Bus width translates to the element size (ES) */
-        switch (dev_width) {
-        case DMA_SLAVE_BUSWIDTH_1_BYTE:
-                es = OMAP_DMA_DATA_TYPE_S8;
-                break;
-        case DMA_SLAVE_BUSWIDTH_2_BYTES:
-                es = OMAP_DMA_DATA_TYPE_S16;
-                break;
-        case DMA_SLAVE_BUSWIDTH_4_BYTES:
-                es = OMAP_DMA_DATA_TYPE_S32;
-                break;
-        default: /* not reached */
-                return NULL;
-        }
-
-        /* Now allocate and setup the descriptor. */
-        d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
-        if (!d)
-                return NULL;
-
-        d->dir = dir;
-        d->dev_addr = dev_addr;
-        d->fi = burst;
-        d->es = es;
-        if (burst)
-                d->sync_mode = OMAP_DMA_SYNC_PACKET;
-        else
-                d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
-        d->sync_type = sync_type;
-        d->periph_port = OMAP_DMA_PORT_MPUI;
-        d->sg[0].addr = buf_addr;
-        d->sg[0].en = period_len / es_bytes[es];
-        d->sg[0].fn = buf_len / period_len;
-        d->sglen = 1;
-
-        if (!c->cyclic) {
-                c->cyclic = true;
-                omap_dma_link_lch(c->dma_ch, c->dma_ch);
-
-                if (flags & DMA_PREP_INTERRUPT)
-                        omap_enable_dma_irq(c->dma_ch, OMAP_DMA_FRAME_IRQ);
-
-                omap_disable_dma_irq(c->dma_ch, OMAP_DMA_BLOCK_IRQ);
-        }
-
-        if (dma_omap2plus()) {
-                omap_set_dma_src_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
-                omap_set_dma_dest_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
-        }
-
-        return vchan_tx_prep(&c->vc, &d->vd, flags);
-}
-
-static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg)
-{
-        if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
-            cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
-                return -EINVAL;
-
-        memcpy(&c->cfg, cfg, sizeof(c->cfg));
-
-        return 0;
-}
-
-static int omap_dma_terminate_all(struct omap_chan *c)
-{
-        struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
-        unsigned long flags;
-        LIST_HEAD(head);
-
-        spin_lock_irqsave(&c->vc.lock, flags);
-
-        /* Prevent this channel being scheduled */
-        spin_lock(&d->lock);
-        list_del_init(&c->node);
-        spin_unlock(&d->lock);
-
-        /*
-         * Stop DMA activity: we assume the callback will not be called
-         * after omap_stop_dma() returns (even if it does, it will see
-         * c->desc is NULL and exit.)
-         */
-        if (c->desc) {
-                c->desc = NULL;
-                /* Avoid stopping the dma twice */
-                if (!c->paused)
-                        omap_stop_dma(c->dma_ch);
-        }
-
-        if (c->cyclic) {
-                c->cyclic = false;
-                c->paused = false;
-                omap_dma_unlink_lch(c->dma_ch, c->dma_ch);
-        }
-
-        vchan_get_all_descriptors(&c->vc, &head);
-        spin_unlock_irqrestore(&c->vc.lock, flags);
-        vchan_dma_desc_free_list(&c->vc, &head);
-
-        return 0;
-}
-
-static int omap_dma_pause(struct omap_chan *c)
-{
-        /* Pause/Resume only allowed with cyclic mode */
-        if (!c->cyclic)
-                return -EINVAL;
-
-        if (!c->paused) {
-                omap_stop_dma(c->dma_ch);
-                c->paused = true;
-        }
-
-        return 0;
-}
-
-static int omap_dma_resume(struct omap_chan *c)
-{
-        /* Pause/Resume only allowed with cyclic mode */
-        if (!c->cyclic)
-                return -EINVAL;
-
-        if (c->paused) {
-                omap_start_dma(c->dma_ch);
-                c->paused = false;
-        }
-
-        return 0;
-}
-
-static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-        unsigned long arg)
-{
-        struct omap_chan *c = to_omap_dma_chan(chan);
-        int ret;
-
-        switch (cmd) {
-        case DMA_SLAVE_CONFIG:
-                ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg);
-                break;
-
-        case DMA_TERMINATE_ALL:
-                ret = omap_dma_terminate_all(c);
-                break;
-
-        case DMA_PAUSE:
-                ret = omap_dma_pause(c);
-                break;
-
-        case DMA_RESUME:
-                ret = omap_dma_resume(c);
-                break;
-
-        default:
-                ret = -ENXIO;
-                break;
-        }
-
-        return ret;
-}
-
-static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
-{
-        struct omap_chan *c;
-
-        c = kzalloc(sizeof(*c), GFP_KERNEL);
-        if (!c)
-                return -ENOMEM;
-
-        c->dma_sig = dma_sig;
-        c->vc.desc_free = omap_dma_desc_free;
-        vchan_init(&c->vc, &od->ddev);
-        INIT_LIST_HEAD(&c->node);
-
-        od->ddev.chancnt++;
-
-        return 0;
-}
-
-static void omap_dma_free(struct omap_dmadev *od)
-{
-        tasklet_kill(&od->task);
-        while (!list_empty(&od->ddev.channels)) {
-                struct omap_chan *c = list_first_entry(&od->ddev.channels,
-                        struct omap_chan, vc.chan.device_node);
-
-                list_del(&c->vc.chan.device_node);
-                tasklet_kill(&c->vc.task);
-                kfree(c);
-        }
-        kfree(od);
-}
-
-static int omap_dma_probe(struct platform_device *pdev)
-{
-        struct omap_dmadev *od;
-        int rc, i;
-
-        od = kzalloc(sizeof(*od), GFP_KERNEL);
-        if (!od)
-                return -ENOMEM;
-
-        dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
-        dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
-        od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
-        od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
-        od->ddev.device_tx_status = omap_dma_tx_status;
-        od->ddev.device_issue_pending = omap_dma_issue_pending;
-        od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
-        od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
-        od->ddev.device_control = omap_dma_control;
-        od->ddev.dev = &pdev->dev;
-        INIT_LIST_HEAD(&od->ddev.channels);
-        INIT_LIST_HEAD(&od->pending);
-        spin_lock_init(&od->lock);
-
-        tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
-
-        for (i = 0; i < 127; i++) {
-                rc = omap_dma_chan_init(od, i);
-                if (rc) {
-                        omap_dma_free(od);
-                        return rc;
-                }
-        }
-
-        rc = dma_async_device_register(&od->ddev);
-        if (rc) {
-                pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
-                        rc);
-                omap_dma_free(od);
-        } else {
-                platform_set_drvdata(pdev, od);
-        }
-
-        dev_info(&pdev->dev, "OMAP DMA engine driver\n");
-
-        return rc;
-}
-
-static int omap_dma_remove(struct platform_device *pdev)
-{
-        struct omap_dmadev *od = platform_get_drvdata(pdev);
-
-        dma_async_device_unregister(&od->ddev);
-        omap_dma_free(od);
-
-        return 0;
-}
-
-static struct platform_driver omap_dma_driver = {
-        .probe  = omap_dma_probe,
-        .remove = omap_dma_remove,
-        .driver = {
-                .name = "omap-dma-engine",
-                .owner = THIS_MODULE,
-        },
-};
-
-bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
-{
-        if (chan->device->dev->driver == &omap_dma_driver.driver) {
-                struct omap_chan *c = to_omap_dma_chan(chan);
-                unsigned req = *(unsigned *)param;
-
-                return req == c->dma_sig;
-        }
-        return false;
-}
-EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
-
-static struct platform_device *pdev;
-
-static const struct platform_device_info omap_dma_dev_info = {
-        .name = "omap-dma-engine",
-        .id = -1,
-        .dma_mask = DMA_BIT_MASK(32),
-};
-
-static int omap_dma_init(void)
-{
-        int rc = platform_driver_register(&omap_dma_driver);
-
-        if (rc == 0) {
-                pdev = platform_device_register_full(&omap_dma_dev_info);
-                if (IS_ERR(pdev)) {
-                        platform_driver_unregister(&omap_dma_driver);
-                        rc = PTR_ERR(pdev);
-                }
-        }
-        return rc;
-}
-subsys_initcall(omap_dma_init);
-
-static void __exit omap_dma_exit(void)
-{
-        platform_device_unregister(pdev);
-        platform_driver_unregister(&omap_dma_driver);
-}
-module_exit(omap_dma_exit);
-
-MODULE_AUTHOR("Russell King");
-MODULE_LICENSE("GPL");
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 3f2617255ef..1ac8d4b580b 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -1,7 +1,7 @@
 /*
  * Topcliff PCH DMA controller driver
  * Copyright (c) 2010 Intel Corporation
- * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
+ * Copyright (C) 2011 OKI SEMICONDUCTOR CO., LTD.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,8 +25,6 @@
 #include <linux/module.h>
 #include <linux/pch_dma.h>
 
-#include "dmaengine.h"
-
 #define DRV_NAME "pch-dma"
 
 #define DMA_CTL0_DISABLE                0x0
@@ -62,7 +60,7 @@
 #define DMA_DESC_FOLLOW_WITHOUT_IRQ     0x2
 #define DMA_DESC_FOLLOW_WITH_IRQ        0x3
 
-#define MAX_CHAN_NR                     12
+#define MAX_CHAN_NR                     8
 
 #define DMA_MASK_CTL0_MODE      0x33333333
 #define DMA_MASK_CTL2_MODE      0x00003333
@@ -101,12 +99,13 @@ struct pch_dma_desc {
 struct pch_dma_chan {
         struct dma_chan         chan;
         void __iomem *membase;
-        enum dma_transfer_direction dir;
+        enum dma_data_direction dir;
         struct tasklet_struct   tasklet;
         unsigned long           err_status;
 
         spinlock_t              lock;
 
+        dma_cookie_t            completed_cookie;
         struct list_head        active_list;
         struct list_head        queue;
         struct list_head        free_list;
@@ -225,7 +224,7 @@ static void pdc_set_dir(struct dma_chan *chan)
                 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
                                        (DMA_CTL0_BITS_PER_CH * chan->chan_id));
                 val &= mask_mode;
-                if (pd_chan->dir == DMA_MEM_TO_DEV)
+                if (pd_chan->dir == DMA_TO_DEVICE)
                         val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
                                        DMA_CTL0_DIR_SHIFT_BITS);
                 else
@@ -243,7 +242,7 @@ static void pdc_set_dir(struct dma_chan *chan)
                 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
                                                  (DMA_CTL0_BITS_PER_CH * ch));
                 val &= mask_mode;
-                if (pd_chan->dir == DMA_MEM_TO_DEV)
+                if (pd_chan->dir == DMA_TO_DEVICE)
                         val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
                                        DMA_CTL0_DIR_SHIFT_BITS);
                 else
@@ -417,6 +416,20 @@ static void pdc_advance_work(struct pch_dma_chan *pd_chan)
         }
 }
 
+static dma_cookie_t pdc_assign_cookie(struct pch_dma_chan *pd_chan,
+                                      struct pch_dma_desc *desc)
+{
+        dma_cookie_t cookie = pd_chan->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        pd_chan->chan.cookie = cookie;
+        desc->txd.cookie = cookie;
+
+        return cookie;
+}
+
 static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
 {
         struct pch_dma_desc *desc = to_pd_desc(txd);
@@ -424,7 +437,7 @@ static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
         dma_cookie_t cookie;
 
         spin_lock(&pd_chan->lock);
-        cookie = dma_cookie_assign(txd);
+        cookie = pdc_assign_cookie(pd_chan, desc);
 
         if (list_empty(&pd_chan->active_list)) {
                 list_add_tail(&desc->desc_node, &pd_chan->active_list);
@@ -531,7 +544,7 @@ static int pd_alloc_chan_resources(struct dma_chan *chan)
         spin_lock_irq(&pd_chan->lock);
         list_splice(&tmp_list, &pd_chan->free_list);
         pd_chan->descs_allocated = i;
-        dma_cookie_init(chan);
+        pd_chan->completed_cookie = chan->cookie = 1;
         spin_unlock_irq(&pd_chan->lock);
 
         pdc_enable_irq(chan, 1);
@@ -565,12 +578,19 @@ static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
                                     struct dma_tx_state *txstate)
 {
         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
-        enum dma_status ret;
+        dma_cookie_t last_used;
+        dma_cookie_t last_completed;
+        int ret;
 
         spin_lock_irq(&pd_chan->lock);
-        ret = dma_cookie_status(chan, cookie, txstate);
+        last_completed = pd_chan->completed_cookie;
+        last_used = chan->cookie;
         spin_unlock_irq(&pd_chan->lock);
 
+        ret = dma_async_is_complete(cookie, last_completed, last_used);
+
+        dma_set_tx_state(txstate, last_completed, last_used, 0);
+
         return ret;
 }
 
@@ -587,8 +607,7 @@ static void pd_issue_pending(struct dma_chan *chan)
 
 static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
                         struct scatterlist *sgl, unsigned int sg_len,
-                        enum dma_transfer_direction direction, unsigned long flags,
-                        void *context)
+                        enum dma_data_direction direction, unsigned long flags)
 {
         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
         struct pch_dma_slave *pd_slave = chan->private;
@@ -604,9 +623,9 @@ static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
                 return NULL;
         }
 
-        if (direction == DMA_DEV_TO_MEM)
+        if (direction == DMA_FROM_DEVICE)
                 reg = pd_slave->rx_reg;
-        else if (direction == DMA_MEM_TO_DEV)
+        else if (direction == DMA_TO_DEVICE)
                 reg = pd_slave->tx_reg;
         else
                 return NULL;
@@ -621,7 +640,7 @@ static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
                         goto err_desc_get;
 
                 desc->regs.dev_addr = reg;
-                desc->regs.mem_addr = sg_dma_address(sg);
+                desc->regs.mem_addr = sg_phys(sg);
                 desc->regs.size = sg_dma_len(sg);
                 desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ;
 
@@ -843,7 +862,7 @@ static int pch_dma_resume(struct pci_dev *pdev)
 }
 #endif
 
-static int pch_dma_probe(struct pci_dev *pdev,
+static int __devinit pch_dma_probe(struct pci_dev *pdev,
                                    const struct pci_device_id *id)
 {
         struct pch_dma *pd;
@@ -853,7 +872,8 @@ static int pch_dma_probe(struct pci_dev *pdev,
         int i;
 
         nr_channels = id->driver_data;
-        pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+        pd = kzalloc(sizeof(struct pch_dma)+
+                sizeof(struct pch_dma_chan) * nr_channels, GFP_KERNEL);
         if (!pd)
                 return -ENOMEM;
 
@@ -906,6 +926,7 @@ static int pch_dma_probe(struct pci_dev *pdev,
         }
 
         pd->dma.dev = &pdev->dev;
+        pd->dma.chancnt = nr_channels;
 
         INIT_LIST_HEAD(&pd->dma.channels);
 
@@ -913,7 +934,8 @@ static int pch_dma_probe(struct pci_dev *pdev,
                 struct pch_dma_chan *pd_chan = &pd->channels[i];
 
                 pd_chan->chan.device = &pd->dma;
-                dma_cookie_init(&pd_chan->chan);
+                pd_chan->chan.cookie = 1;
+                pd_chan->chan.chan_id = i;
 
                 pd_chan->membase = &regs->desc[i];
 
@@ -961,7 +983,7 @@ err_free_mem:
         return err;
 }
 
-static void pch_dma_remove(struct pci_dev *pdev)
+static void __devexit pch_dma_remove(struct pci_dev *pdev)
 {
         struct pch_dma *pd = pci_get_drvdata(pdev);
         struct pch_dma_chan *pd_chan;
@@ -999,8 +1021,6 @@ static void pch_dma_remove(struct pci_dev *pdev)
 #define PCI_DEVICE_ID_ML7223_DMA2_4CH   0x800E
 #define PCI_DEVICE_ID_ML7223_DMA3_4CH   0x8017
 #define PCI_DEVICE_ID_ML7223_DMA4_4CH   0x803B
-#define PCI_DEVICE_ID_ML7831_DMA1_8CH   0x8810
-#define PCI_DEVICE_ID_ML7831_DMA2_4CH   0x8815
 
 DEFINE_PCI_DEVICE_TABLE(pch_dma_id_table) = {
         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 },
@@ -1013,8 +1033,6 @@ DEFINE_PCI_DEVICE_TABLE(pch_dma_id_table) = {
         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA2_4CH), 4}, /* Video SPI */
         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA3_4CH), 4}, /* Security */
         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */
-        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA1_8CH), 8}, /* UART */
-        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA2_4CH), 4}, /* SPI */
         { 0, },
 };
 
@@ -1022,7 +1040,7 @@ static struct pci_driver pch_dma_driver = {
         .name           = DRV_NAME,
         .id_table       = pch_dma_id_table,
         .probe          = pch_dma_probe,
-        .remove         = pch_dma_remove,
+        .remove         = __devexit_p(pch_dma_remove),
 #ifdef CONFIG_PM
         .suspend        = pch_dma_suspend,
         .resume         = pch_dma_resume,
@@ -1042,7 +1060,7 @@ static void __exit pch_dma_exit(void)
 module_init(pch_dma_init);
 module_exit(pch_dma_exit);
 
-MODULE_DESCRIPTION("Intel EG20T PCH / LAPIS Semicon ML7213/ML7223/ML7831 IOH "
+MODULE_DESCRIPTION("Intel EG20T PCH / OKI SEMICONDUCTOR ML7213 IOH "
                    "DMA controller driver");
 MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 80680eee017..00eee59e8b3 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -1,6 +1,4 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
+/* linux/drivers/dma/pl330.c
  *
  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  *      Jaswinder Singh <jassi.brar@samsung.com>
@@ -11,517 +9,22 @@
  * (at your option) any later version.
  */
 
-#include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/module.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
+#include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl330.h>
-#include <linux/scatterlist.h>
-#include <linux/of.h>
-
-#include "dmaengine.h"
-#define PL330_MAX_CHAN          8
-#define PL330_MAX_IRQS          32
-#define PL330_MAX_PERI          32
-
-enum pl330_srccachectrl {
-        SCCTRL0,        /* Noncacheable and nonbufferable */
-        SCCTRL1,        /* Bufferable only */
-        SCCTRL2,        /* Cacheable, but do not allocate */
-        SCCTRL3,        /* Cacheable and bufferable, but do not allocate */
-        SINVALID1,
-        SINVALID2,
-        SCCTRL6,        /* Cacheable write-through, allocate on reads only */
-        SCCTRL7,        /* Cacheable write-back, allocate on reads only */
-};
-
-enum pl330_dstcachectrl {
-        DCCTRL0,        /* Noncacheable and nonbufferable */
-        DCCTRL1,        /* Bufferable only */
-        DCCTRL2,        /* Cacheable, but do not allocate */
-        DCCTRL3,        /* Cacheable and bufferable, but do not allocate */
-        DINVALID1,      /* AWCACHE = 0x1000 */
-        DINVALID2,
-        DCCTRL6,        /* Cacheable write-through, allocate on writes only */
-        DCCTRL7,        /* Cacheable write-back, allocate on writes only */
-};
-
-enum pl330_byteswap {
-        SWAP_NO,
-        SWAP_2,
-        SWAP_4,
-        SWAP_8,
-        SWAP_16,
-};
-
-enum pl330_reqtype {
-        MEMTOMEM,
-        MEMTODEV,
-        DEVTOMEM,
-        DEVTODEV,
-};
-
-/* Register and Bit field Definitions */
-#define DS                      0x0
-#define DS_ST_STOP              0x0
-#define DS_ST_EXEC              0x1
-#define DS_ST_CMISS             0x2
-#define DS_ST_UPDTPC            0x3
-#define DS_ST_WFE               0x4
-#define DS_ST_ATBRR             0x5
-#define DS_ST_QBUSY             0x6
-#define DS_ST_WFP               0x7
-#define DS_ST_KILL              0x8
-#define DS_ST_CMPLT             0x9
-#define DS_ST_FLTCMP            0xe
-#define DS_ST_FAULT             0xf
-
-#define DPC                     0x4
-#define INTEN                   0x20
-#define ES                      0x24
-#define INTSTATUS               0x28
-#define INTCLR                  0x2c
-#define FSM                     0x30
-#define FSC                     0x34
-#define FTM                     0x38
-
-#define _FTC                    0x40
-#define FTC(n)                  (_FTC + (n)*0x4)
-
-#define _CS                     0x100
-#define CS(n)                   (_CS + (n)*0x8)
-#define CS_CNS                  (1 << 21)
-
-#define _CPC                    0x104
-#define CPC(n)                  (_CPC + (n)*0x8)
-
-#define _SA                     0x400
-#define SA(n)                   (_SA + (n)*0x20)
-
-#define _DA                     0x404
-#define DA(n)                   (_DA + (n)*0x20)
-
-#define _CC                     0x408
-#define CC(n)                   (_CC + (n)*0x20)
-
-#define CC_SRCINC               (1 << 0)
-#define CC_DSTINC               (1 << 14)
-#define CC_SRCPRI               (1 << 8)
-#define CC_DSTPRI               (1 << 22)
-#define CC_SRCNS                (1 << 9)
-#define CC_DSTNS                (1 << 23)
-#define CC_SRCIA                (1 << 10)
-#define CC_DSTIA                (1 << 24)
-#define CC_SRCBRSTLEN_SHFT      4
-#define CC_DSTBRSTLEN_SHFT      18
-#define CC_SRCBRSTSIZE_SHFT     1
-#define CC_DSTBRSTSIZE_SHFT     15
-#define CC_SRCCCTRL_SHFT        11
-#define CC_SRCCCTRL_MASK        0x7
-#define CC_DSTCCTRL_SHFT        25
-#define CC_DRCCCTRL_MASK        0x7
-#define CC_SWAP_SHFT            28
-
-#define _LC0                    0x40c
-#define LC0(n)                  (_LC0 + (n)*0x20)
-
-#define _LC1                    0x410
-#define LC1(n)                  (_LC1 + (n)*0x20)
-
-#define DBGSTATUS               0xd00
-#define DBG_BUSY                (1 << 0)
-
-#define DBGCMD                  0xd04
-#define DBGINST0                0xd08
-#define DBGINST1                0xd0c
-
-#define CR0                     0xe00
-#define CR1                     0xe04
-#define CR2                     0xe08
-#define CR3                     0xe0c
-#define CR4                     0xe10
-#define CRD                     0xe14
-
-#define PERIPH_ID               0xfe0
-#define PERIPH_REV_SHIFT        20
-#define PERIPH_REV_MASK         0xf
-#define PERIPH_REV_R0P0         0
-#define PERIPH_REV_R1P0         1
-#define PERIPH_REV_R1P1         2
-#define PCELL_ID                0xff0
-
-#define CR0_PERIPH_REQ_SET      (1 << 0)
-#define CR0_BOOT_EN_SET         (1 << 1)
-#define CR0_BOOT_MAN_NS         (1 << 2)
-#define CR0_NUM_CHANS_SHIFT     4
-#define CR0_NUM_CHANS_MASK      0x7
-#define CR0_NUM_PERIPH_SHIFT    12
-#define CR0_NUM_PERIPH_MASK     0x1f
-#define CR0_NUM_EVENTS_SHIFT    17
-#define CR0_NUM_EVENTS_MASK     0x1f
-
-#define CR1_ICACHE_LEN_SHIFT    0
-#define CR1_ICACHE_LEN_MASK     0x7
-#define CR1_NUM_ICACHELINES_SHIFT       4
-#define CR1_NUM_ICACHELINES_MASK        0xf
-
-#define CRD_DATA_WIDTH_SHIFT    0
-#define CRD_DATA_WIDTH_MASK     0x7
-#define CRD_WR_CAP_SHIFT        4
-#define CRD_WR_CAP_MASK         0x7
-#define CRD_WR_Q_DEP_SHIFT      8
-#define CRD_WR_Q_DEP_MASK       0xf
-#define CRD_RD_CAP_SHIFT        12
-#define CRD_RD_CAP_MASK         0x7
-#define CRD_RD_Q_DEP_SHIFT      16
-#define CRD_RD_Q_DEP_MASK       0xf
-#define CRD_DATA_BUFF_SHIFT     20
-#define CRD_DATA_BUFF_MASK      0x3ff
-
-#define PART                    0x330
-#define DESIGNER                0x41
-#define REVISION                0x0
-#define INTEG_CFG               0x0
-#define PERIPH_ID_VAL           ((PART << 0) | (DESIGNER << 12))
-
-#define PCELL_ID_VAL            0xb105f00d
-
-#define PL330_STATE_STOPPED             (1 << 0)
-#define PL330_STATE_EXECUTING           (1 << 1)
-#define PL330_STATE_WFE                 (1 << 2)
-#define PL330_STATE_FAULTING            (1 << 3)
-#define PL330_STATE_COMPLETING          (1 << 4)
-#define PL330_STATE_WFP                 (1 << 5)
-#define PL330_STATE_KILLING             (1 << 6)
-#define PL330_STATE_FAULT_COMPLETING    (1 << 7)
-#define PL330_STATE_CACHEMISS           (1 << 8)
-#define PL330_STATE_UPDTPC              (1 << 9)
-#define PL330_STATE_ATBARRIER           (1 << 10)
-#define PL330_STATE_QUEUEBUSY           (1 << 11)
-#define PL330_STATE_INVALID             (1 << 15)
-
-#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
-                                | PL330_STATE_WFE | PL330_STATE_FAULTING)
-
-#define CMD_DMAADDH             0x54
-#define CMD_DMAEND              0x00
-#define CMD_DMAFLUSHP           0x35
-#define CMD_DMAGO               0xa0
-#define CMD_DMALD               0x04
-#define CMD_DMALDP              0x25
-#define CMD_DMALP               0x20
-#define CMD_DMALPEND            0x28
-#define CMD_DMAKILL             0x01
-#define CMD_DMAMOV              0xbc
-#define CMD_DMANOP              0x18
-#define CMD_DMARMB              0x12
-#define CMD_DMASEV              0x34
-#define CMD_DMAST               0x08
-#define CMD_DMASTP              0x29
-#define CMD_DMASTZ              0x0c
-#define CMD_DMAWFE              0x36
-#define CMD_DMAWFP              0x30
-#define CMD_DMAWMB              0x13
-
-#define SZ_DMAADDH              3
-#define SZ_DMAEND               1
-#define SZ_DMAFLUSHP            2
-#define SZ_DMALD                1
-#define SZ_DMALDP               2
-#define SZ_DMALP                2
-#define SZ_DMALPEND             2
-#define SZ_DMAKILL              1
-#define SZ_DMAMOV               6
-#define SZ_DMANOP               1
-#define SZ_DMARMB               1
-#define SZ_DMASEV               2
-#define SZ_DMAST                1
-#define SZ_DMASTP               2
-#define SZ_DMASTZ               1
-#define SZ_DMAWFE               2
-#define SZ_DMAWFP               2
-#define SZ_DMAWMB               1
-#define SZ_DMAGO                6
-
-#define BRST_LEN(ccr)           ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
-#define BRST_SIZE(ccr)          (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
-
-#define BYTE_TO_BURST(b, ccr)   ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
-#define BURST_TO_BYTE(c, ccr)   ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
-
-/*
- * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
- * at 1byte/burst for P<->M and M<->M respectively.
- * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
- * should be enough for P<->M and M<->M respectively.
- */
-#define MCODE_BUFF_PER_REQ      256
-
-/* If the _pl330_req is available to the client */
-#define IS_FREE(req)    (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
-
-/* Use this _only_ to wait on transient states */
-#define UNTIL(t, s)     while (!(_state(t) & (s))) cpu_relax();
-
-#ifdef PL330_DEBUG_MCGEN
-static unsigned cmd_line;
-#define PL330_DBGCMD_DUMP(off, x...)    do { \
-                                                printk("%x:", cmd_line); \
-                                                printk(x); \
-                                                cmd_line += off; \
-                                        } while (0)
-#define PL330_DBGMC_START(addr)         (cmd_line = addr)
-#else
-#define PL330_DBGCMD_DUMP(off, x...)    do {} while (0)
-#define PL330_DBGMC_START(addr)         do {} while (0)
-#endif
-
-/* The number of default descriptors */
 
 #define NR_DEFAULT_DESC 16
 
-/* Populated by the PL330 core driver for DMA API driver's info */
-struct pl330_config {
-        u32     periph_id;
-        u32     pcell_id;
-#define DMAC_MODE_NS    (1 << 0)
-        unsigned int    mode;
-        unsigned int    data_bus_width:10; /* In number of bits */
-        unsigned int    data_buf_dep:10;
-        unsigned int    num_chan:4;
-        unsigned int    num_peri:6;
-        u32             peri_ns;
-        unsigned int    num_events:6;
-        u32             irq_ns;
-};
-
-/* Handle to the DMAC provided to the PL330 core */
-struct pl330_info {
-        /* Owning device */
-        struct device *dev;
-        /* Size of MicroCode buffers for each channel. */
-        unsigned mcbufsz;
-        /* ioremap'ed address of PL330 registers. */
-        void __iomem    *base;
-        /* Client can freely use it. */
-        void    *client_data;
-        /* PL330 core data, Client must not touch it. */
-        void    *pl330_data;
-        /* Populated by the PL330 core driver during pl330_add */
-        struct pl330_config     pcfg;
-        /*
-         * If the DMAC has some reset mechanism, then the
-         * client may want to provide pointer to the method.
-         */
-        void (*dmac_reset)(struct pl330_info *pi);
-};
-
-/**
- * Request Configuration.
- * The PL330 core does not modify this and uses the last
- * working configuration if the request doesn't provide any.
- *
- * The Client may want to provide this info only for the
- * first request and a request with new settings.
- */
-struct pl330_reqcfg {
-        /* Address Incrementing */
-        unsigned dst_inc:1;
-        unsigned src_inc:1;
-
-        /*
-         * For now, the SRC & DST protection levels
-         * and burst size/length are assumed same.
-         */
-        bool nonsecure;
-        bool privileged;
-        bool insnaccess;
-        unsigned brst_len:5;
-        unsigned brst_size:3; /* in power of 2 */
-
-        enum pl330_dstcachectrl dcctl;
-        enum pl330_srccachectrl scctl;
-        enum pl330_byteswap swap;
-        struct pl330_config *pcfg;
-};
-
-/*
- * One cycle of DMAC operation.
- * There may be more than one xfer in a request.
- */
-struct pl330_xfer {
-        u32 src_addr;
-        u32 dst_addr;
-        /* Size to xfer */
-        u32 bytes;
-        /*
-         * Pointer to next xfer in the list.
-         * The last xfer in the req must point to NULL.
-         */
-        struct pl330_xfer *next;
-};
-
-/* The xfer callbacks are made with one of these arguments. */
-enum pl330_op_err {
-        /* The all xfers in the request were success. */
-        PL330_ERR_NONE,
-        /* If req aborted due to global error. */
-        PL330_ERR_ABORT,
-        /* If req failed due to problem with Channel. */
-        PL330_ERR_FAIL,
-};
-
-/* A request defining Scatter-Gather List ending with NULL xfer. */
-struct pl330_req {
-        enum pl330_reqtype rqtype;
-        /* Index of peripheral for the xfer. */
-        unsigned peri:5;
-        /* Unique token for this xfer, set by the client. */
-        void *token;
-        /* Callback to be called after xfer. */
-        void (*xfer_cb)(void *token, enum pl330_op_err err);
-        /* If NULL, req will be done at last set parameters. */
-        struct pl330_reqcfg *cfg;
-        /* Pointer to first xfer in the request. */
-        struct pl330_xfer *x;
-        /* Hook to attach to DMAC's list of reqs with due callback */
-        struct list_head rqd;
-};
-
-/*
- * To know the status of the channel and DMAC, the client
- * provides a pointer to this structure. The PL330 core
- * fills it with current information.
- */
-struct pl330_chanstatus {
-        /*
-         * If the DMAC engine halted due to some error,
-         * the client should remove-add DMAC.
-         */
-        bool dmac_halted;
-        /*
-         * If channel is halted due to some error,
-         * the client should ABORT/FLUSH and START the channel.
-         */
-        bool faulting;
-        /* Location of last load */
-        u32 src_addr;
-        /* Location of last store */
-        u32 dst_addr;
-        /*
-         * Pointer to the currently active req, NULL if channel is
-         * inactive, even though the requests may be present.
-         */
-        struct pl330_req *top_req;
-        /* Pointer to req waiting second in the queue if any. */
-        struct pl330_req *wait_req;
-};
-
-enum pl330_chan_op {
-        /* Start the channel */
-        PL330_OP_START,
-        /* Abort the active xfer */
-        PL330_OP_ABORT,
-        /* Stop xfer and flush queue */
-        PL330_OP_FLUSH,
-};
-
-struct _xfer_spec {
-        u32 ccr;
-        struct pl330_req *r;
-        struct pl330_xfer *x;
-};
-
-enum dmamov_dst {
-        SAR = 0,
-        CCR,
-        DAR,
-};
-
-enum pl330_dst {
-        SRC = 0,
-        DST,
-};
-
-enum pl330_cond {
-        SINGLE,
-        BURST,
-        ALWAYS,
-};
-
-struct _pl330_req {
-        u32 mc_bus;
-        void *mc_cpu;
-        /* Number of bytes taken to setup MC for the req */
-        u32 mc_len;
-        struct pl330_req *r;
-};
-
-/* ToBeDone for tasklet */
-struct _pl330_tbd {
-        bool reset_dmac;
-        bool reset_mngr;
-        u8 reset_chan;
-};
-
-/* A DMAC Thread */
-struct pl330_thread {
-        u8 id;
-        int ev;
-        /* If the channel is not yet acquired by any client */
-        bool free;
-        /* Parent DMAC */
-        struct pl330_dmac *dmac;
-        /* Only two at a time */
-        struct _pl330_req req[2];
-        /* Index of the last enqueued request */
-        unsigned lstenq;
-        /* Index of the last submitted request or -1 if the DMA is stopped */
-        int req_running;
-};
-
-enum pl330_dmac_state {
-        UNINIT,
-        INIT,
-        DYING,
-};
-
-/* A DMAC */
-struct pl330_dmac {
-        spinlock_t              lock;
-        /* Holds list of reqs with due callbacks */
-        struct list_head        req_done;
-        /* Pointer to platform specific stuff */
-        struct pl330_info       *pinfo;
-        /* Maximum possible events/irqs */
-        int                     events[32];
-        /* BUS address of MicroCode buffer */
-        u32                     mcode_bus;
-        /* CPU address of MicroCode buffer */
-        void                    *mcode_cpu;
-        /* List of all Channel threads */
-        struct pl330_thread     *channels;
-        /* Pointer to the MANAGER thread */
-        struct pl330_thread     *manager;
-        /* To handle bad news in interrupt */
-        struct tasklet_struct   tasks;
-        struct _pl330_tbd       dmac_tbd;
-        /* State of DMAC operation */
-        enum pl330_dmac_state   state;
-};
-
 enum desc_status {
         /* In the DMAC pool */
         FREE,
         /*
-         * Allocated to some channel during prep_xxx
+         * Allocted to some channel during prep_xxx
          * Also may be sitting on the work_list.
          */
         PREP,
@@ -545,6 +48,9 @@ struct dma_pl330_chan {
         /* DMA-Engine Channel */
         struct dma_chan chan;
 
+        /* Last completed cookie */
+        dma_cookie_t completed;
+
         /* List of to be xfered descriptors */
         struct list_head work_list;
 
@@ -562,14 +68,6 @@ struct dma_pl330_chan {
          * NULL if the channel is available to be acquired.
          */
         void *pl330_chid;
-
-        /* For D-to-M and M-to-D channels */
-        int burst_sz; /* the peripheral fifo width */
-        int burst_len; /* the number of burst */
-        dma_addr_t fifo_addr;
-
-        /* for cyclic capability */
-        bool cyclic;
 };
 
 struct dma_pl330_dmac {
@@ -606,1598 +104,6 @@ struct dma_pl330_desc {
         struct dma_pl330_chan *pchan;
 };
 
-static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
-{
-        if (r && r->xfer_cb)
-                r->xfer_cb(r->token, err);
-}
-
-static inline bool _queue_empty(struct pl330_thread *thrd)
-{
-        return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
-                ? true : false;
-}
-
-static inline bool _queue_full(struct pl330_thread *thrd)
-{
-        return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
-                ? false : true;
-}
-
-static inline bool is_manager(struct pl330_thread *thrd)
-{
-        struct pl330_dmac *pl330 = thrd->dmac;
-
-        /* MANAGER is indexed at the end */
-        if (thrd->id == pl330->pinfo->pcfg.num_chan)
-                return true;
-        else
-                return false;
-}
-
-/* If manager of the thread is in Non-Secure mode */
-static inline bool _manager_ns(struct pl330_thread *thrd)
-{
-        struct pl330_dmac *pl330 = thrd->dmac;
-
-        return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
-}
-
-static inline u32 get_id(struct pl330_info *pi, u32 off)
-{
-        void __iomem *regs = pi->base;
-        u32 id = 0;
-
-        id |= (readb(regs + off + 0x0) << 0);
-        id |= (readb(regs + off + 0x4) << 8);
-        id |= (readb(regs + off + 0x8) << 16);
-        id |= (readb(regs + off + 0xc) << 24);
-
-        return id;
-}
-
-static inline u32 get_revision(u32 periph_id)
-{
-        return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
-}
-
-static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
-                enum pl330_dst da, u16 val)
-{
-        if (dry_run)
-                return SZ_DMAADDH;
-
-        buf[0] = CMD_DMAADDH;
-        buf[0] |= (da << 1);
-        *((u16 *)&buf[1]) = val;
-
-        PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
-                da == 1 ? "DA" : "SA", val);
-
-        return SZ_DMAADDH;
-}
-
-static inline u32 _emit_END(unsigned dry_run, u8 buf[])
-{
-        if (dry_run)
-                return SZ_DMAEND;
-
-        buf[0] = CMD_DMAEND;
-
-        PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
-
-        return SZ_DMAEND;
-}
-
-static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
-{
-        if (dry_run)
-                return SZ_DMAFLUSHP;
-
-        buf[0] = CMD_DMAFLUSHP;
-
-        peri &= 0x1f;
-        peri <<= 3;
-        buf[1] = peri;
-
-        PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
-
-        return SZ_DMAFLUSHP;
-}
-
-static inline u32 _emit_LD(unsigned dry_run, u8 buf[],  enum pl330_cond cond)
-{
-        if (dry_run)
-                return SZ_DMALD;
-
-        buf[0] = CMD_DMALD;
-
-        if (cond == SINGLE)
-                buf[0] |= (0 << 1) | (1 << 0);
-        else if (cond == BURST)
-                buf[0] |= (1 << 1) | (1 << 0);
-
-        PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
-                cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
-
-        return SZ_DMALD;
-}
-
-static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
-                enum pl330_cond cond, u8 peri)
-{
-        if (dry_run)
-                return SZ_DMALDP;
-
-        buf[0] = CMD_DMALDP;
-
-        if (cond == BURST)
-                buf[0] |= (1 << 1);
-
-        peri &= 0x1f;
-        peri <<= 3;
-        buf[1] = peri;
-
-        PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
-                cond == SINGLE ? 'S' : 'B', peri >> 3);
-
-        return SZ_DMALDP;
-}
-
-static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
-                unsigned loop, u8 cnt)
-{
-        if (dry_run)
-                return SZ_DMALP;
-
-        buf[0] = CMD_DMALP;
-
-        if (loop)
-                buf[0] |= (1 << 1);
-
-        cnt--; /* DMAC increments by 1 internally */
-        buf[1] = cnt;
-
-        PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
-
-        return SZ_DMALP;
-}
-
-struct _arg_LPEND {
-        enum pl330_cond cond;
-        bool forever;
-        unsigned loop;
-        u8 bjump;
-};
-
-static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
-                const struct _arg_LPEND *arg)
-{
-        enum pl330_cond cond = arg->cond;
-        bool forever = arg->forever;
-        unsigned loop = arg->loop;
-        u8 bjump = arg->bjump;
-
-        if (dry_run)
-                return SZ_DMALPEND;
-
-        buf[0] = CMD_DMALPEND;
-
-        if (loop)
-                buf[0] |= (1 << 2);
-
-        if (!forever)
-                buf[0] |= (1 << 4);
-
-        if (cond == SINGLE)
-                buf[0] |= (0 << 1) | (1 << 0);
-        else if (cond == BURST)
-                buf[0] |= (1 << 1) | (1 << 0);
-
-        buf[1] = bjump;
-
-        PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
-                        forever ? "FE" : "END",
-                        cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
-                        loop ? '1' : '0',
-                        bjump);
-
-        return SZ_DMALPEND;
-}
-
-static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
-{
-        if (dry_run)
-                return SZ_DMAKILL;
-
-        buf[0] = CMD_DMAKILL;
-
-        return SZ_DMAKILL;
-}
-
-static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
-                enum dmamov_dst dst, u32 val)
-{
-        if (dry_run)
-                return SZ_DMAMOV;
-
-        buf[0] = CMD_DMAMOV;
-        buf[1] = dst;
-        *((u32 *)&buf[2]) = val;
-
-        PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
-                dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
-
-        return SZ_DMAMOV;
-}
-
-static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
-{
-        if (dry_run)
-                return SZ_DMANOP;
-
-        buf[0] = CMD_DMANOP;
-
-        PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
-
-        return SZ_DMANOP;
-}
-
-static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
-{
-        if (dry_run)
-                return SZ_DMARMB;
-
-        buf[0] = CMD_DMARMB;
-
-        PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
-
-        return SZ_DMARMB;
-}
-
-static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
-{
-        if (dry_run)
-                return SZ_DMASEV;
-
-        buf[0] = CMD_DMASEV;
-
-        ev &= 0x1f;
-        ev <<= 3;
-        buf[1] = ev;
-
-        PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
-
-        return SZ_DMASEV;
-}
-
-static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
-{
-        if (dry_run)
-                return SZ_DMAST;
-
-        buf[0] = CMD_DMAST;
-
-        if (cond == SINGLE)
-                buf[0] |= (0 << 1) | (1 << 0);
-        else if (cond == BURST)
-                buf[0] |= (1 << 1) | (1 << 0);
-
-        PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
-                cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
-
-        return SZ_DMAST;
-}
-
-static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
-                enum pl330_cond cond, u8 peri)
-{
-        if (dry_run)
-                return SZ_DMASTP;
-
-        buf[0] = CMD_DMASTP;
-
-        if (cond == BURST)
-                buf[0] |= (1 << 1);
-
-        peri &= 0x1f;
-        peri <<= 3;
-        buf[1] = peri;
-
-        PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
-                cond == SINGLE ? 'S' : 'B', peri >> 3);
-
-        return SZ_DMASTP;
-}
-
-static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
-{
-        if (dry_run)
-                return SZ_DMASTZ;
-
-        buf[0] = CMD_DMASTZ;
-
-        PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
-
-        return SZ_DMASTZ;
-}
-
-static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
-                unsigned invalidate)
-{
-        if (dry_run)
-                return SZ_DMAWFE;
-
-        buf[0] = CMD_DMAWFE;
-
-        ev &= 0x1f;
-        ev <<= 3;
-        buf[1] = ev;
-
-        if (invalidate)
-                buf[1] |= (1 << 1);
-
-        PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
-                ev >> 3, invalidate ? ", I" : "");
-
-        return SZ_DMAWFE;
-}
-
-static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
-                enum pl330_cond cond, u8 peri)
-{
-        if (dry_run)
-                return SZ_DMAWFP;
-
-        buf[0] = CMD_DMAWFP;
-
-        if (cond == SINGLE)
-                buf[0] |= (0 << 1) | (0 << 0);
-        else if (cond == BURST)
-                buf[0] |= (1 << 1) | (0 << 0);
-        else
-                buf[0] |= (0 << 1) | (1 << 0);
-
-        peri &= 0x1f;
-        peri <<= 3;
-        buf[1] = peri;
-
-        PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
-                cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
-
-        return SZ_DMAWFP;
-}
-
-static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
-{
-        if (dry_run)
-                return SZ_DMAWMB;
-
-        buf[0] = CMD_DMAWMB;
-
-        PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
-
-        return SZ_DMAWMB;
-}
-
-struct _arg_GO {
-        u8 chan;
-        u32 addr;
-        unsigned ns;
-};
-
-static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
-                const struct _arg_GO *arg)
-{
-        u8 chan = arg->chan;
-        u32 addr = arg->addr;
-        unsigned ns = arg->ns;
-
-        if (dry_run)
-                return SZ_DMAGO;
-
-        buf[0] = CMD_DMAGO;
-        buf[0] |= (ns << 1);
-
-        buf[1] = chan & 0x7;
-
-        *((u32 *)&buf[2]) = addr;
-
-        return SZ_DMAGO;
-}
-
-#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
-
-/* Returns Time-Out */
-static bool _until_dmac_idle(struct pl330_thread *thrd)
-{
-        void __iomem *regs = thrd->dmac->pinfo->base;
-        unsigned long loops = msecs_to_loops(5);
-
-        do {
-                /* Until Manager is Idle */
-                if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
-                        break;
-
-                cpu_relax();
-        } while (--loops);
-
-        if (!loops)
-                return true;
-
-        return false;
-}
-
-static inline void _execute_DBGINSN(struct pl330_thread *thrd,
-                u8 insn[], bool as_manager)
-{
-        void __iomem *regs = thrd->dmac->pinfo->base;
-        u32 val;
-
-        val = (insn[0] << 16) | (insn[1] << 24);
-        if (!as_manager) {
-                val |= (1 << 0);
-                val |= (thrd->id << 8); /* Channel Number */
-        }
-        writel(val, regs + DBGINST0);
-
-        val = *((u32 *)&insn[2]);
-        writel(val, regs + DBGINST1);
-
-        /* If timed out due to halted state-machine */
-        if (_until_dmac_idle(thrd)) {
-                dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
-                return;
-        }
-
-        /* Get going */
-        writel(0, regs + DBGCMD);
-}
-
-/*
- * Mark a _pl330_req as free.
- * We do it by writing DMAEND as the first instruction
- * because no valid request is going to have DMAEND as
- * its first instruction to execute.
- */
-static void mark_free(struct pl330_thread *thrd, int idx)
-{
-        struct _pl330_req *req = &thrd->req[idx];
-
-        _emit_END(0, req->mc_cpu);
-        req->mc_len = 0;
-
-        thrd->req_running = -1;
-}
-
-static inline u32 _state(struct pl330_thread *thrd)
-{
-        void __iomem *regs = thrd->dmac->pinfo->base;
-        u32 val;
-
-        if (is_manager(thrd))
-                val = readl(regs + DS) & 0xf;
-        else
-                val = readl(regs + CS(thrd->id)) & 0xf;
-
-        switch (val) {
-        case DS_ST_STOP:
-                return PL330_STATE_STOPPED;
-        case DS_ST_EXEC:
-                return PL330_STATE_EXECUTING;
-        case DS_ST_CMISS:
-                return PL330_STATE_CACHEMISS;
-        case DS_ST_UPDTPC:
-                return PL330_STATE_UPDTPC;
-        case DS_ST_WFE:
-                return PL330_STATE_WFE;
-        case DS_ST_FAULT:
-                return PL330_STATE_FAULTING;
-        case DS_ST_ATBRR:
-                if (is_manager(thrd))
-                        return PL330_STATE_INVALID;
-                else
-                        return PL330_STATE_ATBARRIER;
-        case DS_ST_QBUSY:
-                if (is_manager(thrd))
-                        return PL330_STATE_INVALID;
-                else
-                        return PL330_STATE_QUEUEBUSY;
-        case DS_ST_WFP:
-                if (is_manager(thrd))
-                        return PL330_STATE_INVALID;
-                else
-                        return PL330_STATE_WFP;
-        case DS_ST_KILL:
-                if (is_manager(thrd))
-                        return PL330_STATE_INVALID;
-                else
-                        return PL330_STATE_KILLING;
-        case DS_ST_CMPLT:
-                if (is_manager(thrd))
-                        return PL330_STATE_INVALID;
-                else
-                        return PL330_STATE_COMPLETING;
-        case DS_ST_FLTCMP:
-                if (is_manager(thrd))
-                        return PL330_STATE_INVALID;
-                else
-                        return PL330_STATE_FAULT_COMPLETING;
-        default:
-                return PL330_STATE_INVALID;
-        }
-}
-
-static void _stop(struct pl330_thread *thrd)
-{
-        void __iomem *regs = thrd->dmac->pinfo->base;
-        u8 insn[6] = {0, 0, 0, 0, 0, 0};
-
-        if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
-                UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
-
-        /* Return if nothing needs to be done */
-        if (_state(thrd) == PL330_STATE_COMPLETING
-                  || _state(thrd) == PL330_STATE_KILLING
-                  || _state(thrd) == PL330_STATE_STOPPED)
-                return;
-
-        _emit_KILL(0, insn);
-
-        /* Stop generating interrupts for SEV */
-        writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
-
-        _execute_DBGINSN(thrd, insn, is_manager(thrd));
-}
-
-/* Start doing req 'idx' of thread 'thrd' */
-static bool _trigger(struct pl330_thread *thrd)
-{
-        void __iomem *regs = thrd->dmac->pinfo->base;
-        struct _pl330_req *req;
-        struct pl330_req *r;
-        struct _arg_GO go;
-        unsigned ns;
-        u8 insn[6] = {0, 0, 0, 0, 0, 0};
-        int idx;
-
-        /* Return if already ACTIVE */
-        if (_state(thrd) != PL330_STATE_STOPPED)
-                return true;
-
-        idx = 1 - thrd->lstenq;
-        if (!IS_FREE(&thrd->req[idx]))
-                req = &thrd->req[idx];
-        else {
-                idx = thrd->lstenq;
-                if (!IS_FREE(&thrd->req[idx]))
-                        req = &thrd->req[idx];
-                else
-                        req = NULL;
-        }
-
-        /* Return if no request */
-        if (!req || !req->r)
-                return true;
-
-        r = req->r;
-
-        if (r->cfg)
-                ns = r->cfg->nonsecure ? 1 : 0;
-        else if (readl(regs + CS(thrd->id)) & CS_CNS)
-                ns = 1;
-        else
-                ns = 0;
-
-        /* See 'Abort Sources' point-4 at Page 2-25 */
-        if (_manager_ns(thrd) && !ns)
-                dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
-                        __func__, __LINE__);
-
-        go.chan = thrd->id;
-        go.addr = req->mc_bus;
-        go.ns = ns;
-        _emit_GO(0, insn, &go);
-
-        /* Set to generate interrupts for SEV */
-        writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
-
-        /* Only manager can execute GO */
-        _execute_DBGINSN(thrd, insn, true);
-
-        thrd->req_running = idx;
-
-        return true;
-}
-
-static bool _start(struct pl330_thread *thrd)
-{
-        switch (_state(thrd)) {
-        case PL330_STATE_FAULT_COMPLETING:
-                UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
-
-                if (_state(thrd) == PL330_STATE_KILLING)
-                        UNTIL(thrd, PL330_STATE_STOPPED)
-
-        case PL330_STATE_FAULTING:
-                _stop(thrd);
-
-        case PL330_STATE_KILLING:
-        case PL330_STATE_COMPLETING:
-                UNTIL(thrd, PL330_STATE_STOPPED)
-
-        case PL330_STATE_STOPPED:
-                return _trigger(thrd);
-
-        case PL330_STATE_WFP:
-        case PL330_STATE_QUEUEBUSY:
-        case PL330_STATE_ATBARRIER:
-        case PL330_STATE_UPDTPC:
-        case PL330_STATE_CACHEMISS:
-        case PL330_STATE_EXECUTING:
-                return true;
-
-        case PL330_STATE_WFE: /* For RESUME, nothing yet */
-        default:
-                return false;
-        }
-}
-
-static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
-                const struct _xfer_spec *pxs, int cyc)
-{
-        int off = 0;
-        struct pl330_config *pcfg = pxs->r->cfg->pcfg;
-
-        /* check lock-up free version */
-        if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
-                while (cyc--) {
-                        off += _emit_LD(dry_run, &buf[off], ALWAYS);
-                        off += _emit_ST(dry_run, &buf[off], ALWAYS);
-                }
-        } else {
-                while (cyc--) {
-                        off += _emit_LD(dry_run, &buf[off], ALWAYS);
-                        off += _emit_RMB(dry_run, &buf[off]);
-                        off += _emit_ST(dry_run, &buf[off], ALWAYS);
-                        off += _emit_WMB(dry_run, &buf[off]);
-                }
-        }
-
-        return off;
-}
-
-static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
-                const struct _xfer_spec *pxs, int cyc)
-{
-        int off = 0;
-
-        while (cyc--) {
-                off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
-                off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
-                off += _emit_ST(dry_run, &buf[off], ALWAYS);
-                off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
-        }
-
-        return off;
-}
-
-static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
-                const struct _xfer_spec *pxs, int cyc)
-{
-        int off = 0;
-
-        while (cyc--) {
-                off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
-                off += _emit_LD(dry_run, &buf[off], ALWAYS);
-                off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
-                off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
-        }
-
-        return off;
-}
-
-static int _bursts(unsigned dry_run, u8 buf[],
-                const struct _xfer_spec *pxs, int cyc)
-{
-        int off = 0;
-
-        switch (pxs->r->rqtype) {
-        case MEMTODEV:
-                off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
-                break;
-        case DEVTOMEM:
-                off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
-                break;
-        case MEMTOMEM:
-                off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
-                break;
-        default:
-                off += 0x40000000; /* Scare off the Client */
-                break;
-        }
-
-        return off;
-}
-
-/* Returns bytes consumed and updates bursts */
-static inline int _loop(unsigned dry_run, u8 buf[],
-                unsigned long *bursts, const struct _xfer_spec *pxs)
-{
-        int cyc, cycmax, szlp, szlpend, szbrst, off;
-        unsigned lcnt0, lcnt1, ljmp0, ljmp1;
-        struct _arg_LPEND lpend;
-
-        /* Max iterations possible in DMALP is 256 */
-        if (*bursts >= 256*256) {
-                lcnt1 = 256;
-                lcnt0 = 256;
-                cyc = *bursts / lcnt1 / lcnt0;
-        } else if (*bursts > 256) {
-                lcnt1 = 256;
-                lcnt0 = *bursts / lcnt1;
-                cyc = 1;
-        } else {
-                lcnt1 = *bursts;
-                lcnt0 = 0;
-                cyc = 1;
-        }
-
-        szlp = _emit_LP(1, buf, 0, 0);
-        szbrst = _bursts(1, buf, pxs, 1);
-
-        lpend.cond = ALWAYS;
-        lpend.forever = false;
-        lpend.loop = 0;
-        lpend.bjump = 0;
-        szlpend = _emit_LPEND(1, buf, &lpend);
-
-        if (lcnt0) {
-                szlp *= 2;
-                szlpend *= 2;
-        }
-
-        /*
-         * Max bursts that we can unroll due to limit on the
-         * size of backward jump that can be encoded in DMALPEND
-         * which is 8-bits and hence 255
-         */
-        cycmax = (255 - (szlp + szlpend)) / szbrst;
-
-        cyc = (cycmax < cyc) ? cycmax : cyc;
-
-        off = 0;
-
-        if (lcnt0) {
-                off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
-                ljmp0 = off;
-        }
-
-        off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
-        ljmp1 = off;
-
-        off += _bursts(dry_run, &buf[off], pxs, cyc);
-
-        lpend.cond = ALWAYS;
-        lpend.forever = false;
-        lpend.loop = 1;
-        lpend.bjump = off - ljmp1;
-        off += _emit_LPEND(dry_run, &buf[off], &lpend);
-
-        if (lcnt0) {
-                lpend.cond = ALWAYS;
-                lpend.forever = false;
-                lpend.loop = 0;
-                lpend.bjump = off - ljmp0;
-                off += _emit_LPEND(dry_run, &buf[off], &lpend);
-        }
-
-        *bursts = lcnt1 * cyc;
-        if (lcnt0)
-                *bursts *= lcnt0;
-
-        return off;
-}
-
-static inline int _setup_loops(unsigned dry_run, u8 buf[],
-                const struct _xfer_spec *pxs)
-{
-        struct pl330_xfer *x = pxs->x;
-        u32 ccr = pxs->ccr;
-        unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
-        int off = 0;
-
-        while (bursts) {
-                c = bursts;
-                off += _loop(dry_run, &buf[off], &c, pxs);
-                bursts -= c;
-        }
-
-        return off;
-}
-
-static inline int _setup_xfer(unsigned dry_run, u8 buf[],
-                const struct _xfer_spec *pxs)
-{
-        struct pl330_xfer *x = pxs->x;
-        int off = 0;
-
-        /* DMAMOV SAR, x->src_addr */
-        off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
-        /* DMAMOV DAR, x->dst_addr */
-        off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
-
-        /* Setup Loop(s) */
-        off += _setup_loops(dry_run, &buf[off], pxs);
-
-        return off;
-}
-
-/*
- * A req is a sequence of one or more xfer units.
- * Returns the number of bytes taken to setup the MC for the req.
- */
-static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
-                unsigned index, struct _xfer_spec *pxs)
-{
-        struct _pl330_req *req = &thrd->req[index];
-        struct pl330_xfer *x;
-        u8 *buf = req->mc_cpu;
-        int off = 0;
-
-        PL330_DBGMC_START(req->mc_bus);
-
-        /* DMAMOV CCR, ccr */
-        off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
-
-        x = pxs->r->x;
-        do {
-                /* Error if xfer length is not aligned at burst size */
-                if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
-                        return -EINVAL;
-
-                pxs->x = x;
-                off += _setup_xfer(dry_run, &buf[off], pxs);
-
-                x = x->next;
-        } while (x);
-
-        /* DMASEV peripheral/event */
-        off += _emit_SEV(dry_run, &buf[off], thrd->ev);
-        /* DMAEND */
-        off += _emit_END(dry_run, &buf[off]);
-
-        return off;
-}
-
-static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
-{
-        u32 ccr = 0;
-
-        if (rqc->src_inc)
-                ccr |= CC_SRCINC;
-
-        if (rqc->dst_inc)
-                ccr |= CC_DSTINC;
-
-        /* We set same protection levels for Src and DST for now */
-        if (rqc->privileged)
-                ccr |= CC_SRCPRI | CC_DSTPRI;
-        if (rqc->nonsecure)
-                ccr |= CC_SRCNS | CC_DSTNS;
-        if (rqc->insnaccess)
-                ccr |= CC_SRCIA | CC_DSTIA;
-
-        ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
-        ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
-
-        ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
-        ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
-
-        ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
-        ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
-
-        ccr |= (rqc->swap << CC_SWAP_SHFT);
-
-        return ccr;
-}
-
-static inline bool _is_valid(u32 ccr)
-{
-        enum pl330_dstcachectrl dcctl;
-        enum pl330_srccachectrl scctl;
-
-        dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
-        scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
-
-        if (dcctl == DINVALID1 || dcctl == DINVALID2
-                        || scctl == SINVALID1 || scctl == SINVALID2)
-                return false;
-        else
-                return true;
-}
-
-/*
- * Submit a list of xfers after which the client wants notification.
- * Client is not notified after each xfer unit, just once after all
- * xfer units are done or some error occurs.
- */
-static int pl330_submit_req(void *ch_id, struct pl330_req *r)
-{
-        struct pl330_thread *thrd = ch_id;
-        struct pl330_dmac *pl330;
-        struct pl330_info *pi;
-        struct _xfer_spec xs;
-        unsigned long flags;
-        void __iomem *regs;
-        unsigned idx;
-        u32 ccr;
-        int ret = 0;
-
-        /* No Req or Unacquired Channel or DMAC */
-        if (!r || !thrd || thrd->free)
-                return -EINVAL;
-
-        pl330 = thrd->dmac;
-        pi = pl330->pinfo;
-        regs = pi->base;
-
-        if (pl330->state == DYING
-                || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
-                dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
-                        __func__, __LINE__);
-                return -EAGAIN;
-        }
-
-        /* If request for non-existing peripheral */
-        if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) {
-                dev_info(thrd->dmac->pinfo->dev,
-                                "%s:%d Invalid peripheral(%u)!\n",
-                                __func__, __LINE__, r->peri);
-                return -EINVAL;
-        }
-
-        spin_lock_irqsave(&pl330->lock, flags);
-
-        if (_queue_full(thrd)) {
-                ret = -EAGAIN;
-                goto xfer_exit;
-        }
-
-
-        /* Use last settings, if not provided */
-        if (r->cfg) {
-                /* Prefer Secure Channel */
-                if (!_manager_ns(thrd))
-                        r->cfg->nonsecure = 0;
-                else
-                        r->cfg->nonsecure = 1;
-
-                ccr = _prepare_ccr(r->cfg);
-        } else {
-                ccr = readl(regs + CC(thrd->id));
-        }
-
-        /* If this req doesn't have valid xfer settings */
-        if (!_is_valid(ccr)) {
-                ret = -EINVAL;
-                dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
-                        __func__, __LINE__, ccr);
-                goto xfer_exit;
-        }
-
-        idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
-
-        xs.ccr = ccr;
-        xs.r = r;
-
-        /* First dry run to check if req is acceptable */
-        ret = _setup_req(1, thrd, idx, &xs);
-        if (ret < 0)
-                goto xfer_exit;
-
-        if (ret > pi->mcbufsz / 2) {
-                dev_info(thrd->dmac->pinfo->dev,
-                        "%s:%d Trying increasing mcbufsz\n",
-                                __func__, __LINE__);
-                ret = -ENOMEM;
-                goto xfer_exit;
-        }
-
-        /* Hook the request */
-        thrd->lstenq = idx;
-        thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs);
-        thrd->req[idx].r = r;
-
-        ret = 0;
-
-xfer_exit:
-        spin_unlock_irqrestore(&pl330->lock, flags);
-
-        return ret;
-}
-
-static void pl330_dotask(unsigned long data)
-{
-        struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
-        struct pl330_info *pi = pl330->pinfo;
-        unsigned long flags;
-        int i;
-
-        spin_lock_irqsave(&pl330->lock, flags);
-
-        /* The DMAC itself gone nuts */
-        if (pl330->dmac_tbd.reset_dmac) {
-                pl330->state = DYING;
-                /* Reset the manager too */
-                pl330->dmac_tbd.reset_mngr = true;
-                /* Clear the reset flag */
-                pl330->dmac_tbd.reset_dmac = false;
-        }
-
-        if (pl330->dmac_tbd.reset_mngr) {
-                _stop(pl330->manager);
-                /* Reset all channels */
-                pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
-                /* Clear the reset flag */
-                pl330->dmac_tbd.reset_mngr = false;
-        }
-
-        for (i = 0; i < pi->pcfg.num_chan; i++) {
-
-                if (pl330->dmac_tbd.reset_chan & (1 << i)) {
-                        struct pl330_thread *thrd = &pl330->channels[i];
-                        void __iomem *regs = pi->base;
-                        enum pl330_op_err err;
-
-                        _stop(thrd);
-
-                        if (readl(regs + FSC) & (1 << thrd->id))
-                                err = PL330_ERR_FAIL;
-                        else
-                                err = PL330_ERR_ABORT;
-
-                        spin_unlock_irqrestore(&pl330->lock, flags);
-
-                        _callback(thrd->req[1 - thrd->lstenq].r, err);
-                        _callback(thrd->req[thrd->lstenq].r, err);
-
-                        spin_lock_irqsave(&pl330->lock, flags);
-
-                        thrd->req[0].r = NULL;
-                        thrd->req[1].r = NULL;
-                        mark_free(thrd, 0);
-                        mark_free(thrd, 1);
-
-                        /* Clear the reset flag */
-                        pl330->dmac_tbd.reset_chan &= ~(1 << i);
-                }
-        }
-
-        spin_unlock_irqrestore(&pl330->lock, flags);
-
-        return;
-}
-
-/* Returns 1 if state was updated, 0 otherwise */
-static int pl330_update(const struct pl330_info *pi)
-{
-        struct pl330_req *rqdone, *tmp;
-        struct pl330_dmac *pl330;
-        unsigned long flags;
-        void __iomem *regs;
-        u32 val;
-        int id, ev, ret = 0;
-
-        if (!pi || !pi->pl330_data)
-                return 0;
-
-        regs = pi->base;
-        pl330 = pi->pl330_data;
-
-        spin_lock_irqsave(&pl330->lock, flags);
-
-        val = readl(regs + FSM) & 0x1;
-        if (val)
-                pl330->dmac_tbd.reset_mngr = true;
-        else
-                pl330->dmac_tbd.reset_mngr = false;
-
-        val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
-        pl330->dmac_tbd.reset_chan |= val;
-        if (val) {
-                int i = 0;
-                while (i < pi->pcfg.num_chan) {
-                        if (val & (1 << i)) {
-                                dev_info(pi->dev,
-                                        "Reset Channel-%d\t CS-%x FTC-%x\n",
-                                                i, readl(regs + CS(i)),
-                                                readl(regs + FTC(i)));
-                                _stop(&pl330->channels[i]);
-                        }
-                        i++;
-                }
-        }
-
-        /* Check which event happened i.e, thread notified */
-        val = readl(regs + ES);
-        if (pi->pcfg.num_events < 32
-                        && val & ~((1 << pi->pcfg.num_events) - 1)) {
-                pl330->dmac_tbd.reset_dmac = true;
-                dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
-                ret = 1;
-                goto updt_exit;
-        }
-
-        for (ev = 0; ev < pi->pcfg.num_events; ev++) {
-                if (val & (1 << ev)) { /* Event occurred */
-                        struct pl330_thread *thrd;
-                        u32 inten = readl(regs + INTEN);
-                        int active;
-
-                        /* Clear the event */
-                        if (inten & (1 << ev))
-                                writel(1 << ev, regs + INTCLR);
-
-                        ret = 1;
-
-                        id = pl330->events[ev];
-
-                        thrd = &pl330->channels[id];
-
-                        active = thrd->req_running;
-                        if (active == -1) /* Aborted */
-                                continue;
-
-                        /* Detach the req */
-                        rqdone = thrd->req[active].r;
-                        thrd->req[active].r = NULL;
-
-                        mark_free(thrd, active);
-
-                        /* Get going again ASAP */
-                        _start(thrd);
-
-                        /* For now, just make a list of callbacks to be done */
-                        list_add_tail(&rqdone->rqd, &pl330->req_done);
-                }
-        }
-
-        /* Now that we are in no hurry, do the callbacks */
-        list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) {
-                list_del(&rqdone->rqd);
-
-                spin_unlock_irqrestore(&pl330->lock, flags);
-                _callback(rqdone, PL330_ERR_NONE);
-                spin_lock_irqsave(&pl330->lock, flags);
-        }
-
-updt_exit:
-        spin_unlock_irqrestore(&pl330->lock, flags);
-
-        if (pl330->dmac_tbd.reset_dmac
-                        || pl330->dmac_tbd.reset_mngr
-                        || pl330->dmac_tbd.reset_chan) {
-                ret = 1;
-                tasklet_schedule(&pl330->tasks);
-        }
-
-        return ret;
-}
-
-static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
-{
-        struct pl330_thread *thrd = ch_id;
-        struct pl330_dmac *pl330;
-        unsigned long flags;
-        int ret = 0, active;
-
-        if (!thrd || thrd->free || thrd->dmac->state == DYING)
-                return -EINVAL;
-
-        pl330 = thrd->dmac;
-        active = thrd->req_running;
-
-        spin_lock_irqsave(&pl330->lock, flags);
-
-        switch (op) {
-        case PL330_OP_FLUSH:
-                /* Make sure the channel is stopped */
-                _stop(thrd);
-
-                thrd->req[0].r = NULL;
-                thrd->req[1].r = NULL;
-                mark_free(thrd, 0);
-                mark_free(thrd, 1);
-                break;
-
-        case PL330_OP_ABORT:
-                /* Make sure the channel is stopped */
-                _stop(thrd);
-
-                /* ABORT is only for the active req */
-                if (active == -1)
-                        break;
-
-                thrd->req[active].r = NULL;
-                mark_free(thrd, active);
-
-                /* Start the next */
-        case PL330_OP_START:
-                if ((active == -1) && !_start(thrd))
-                        ret = -EIO;
-                break;
-
-        default:
-                ret = -EINVAL;
-        }
-
-        spin_unlock_irqrestore(&pl330->lock, flags);
-        return ret;
-}
-
-/* Reserve an event */
-static inline int _alloc_event(struct pl330_thread *thrd)
-{
-        struct pl330_dmac *pl330 = thrd->dmac;
-        struct pl330_info *pi = pl330->pinfo;
-        int ev;
-
-        for (ev = 0; ev < pi->pcfg.num_events; ev++)
-                if (pl330->events[ev] == -1) {
-                        pl330->events[ev] = thrd->id;
-                        return ev;
-                }
-
-        return -1;
-}
-
-static bool _chan_ns(const struct pl330_info *pi, int i)
-{
-        return pi->pcfg.irq_ns & (1 << i);
-}
-
-/* Upon success, returns IdentityToken for the
- * allocated channel, NULL otherwise.
- */
-static void *pl330_request_channel(const struct pl330_info *pi)
-{
-        struct pl330_thread *thrd = NULL;
-        struct pl330_dmac *pl330;
-        unsigned long flags;
-        int chans, i;
-
-        if (!pi || !pi->pl330_data)
-                return NULL;
-
-        pl330 = pi->pl330_data;
-
-        if (pl330->state == DYING)
-                return NULL;
-
-        chans = pi->pcfg.num_chan;
-
-        spin_lock_irqsave(&pl330->lock, flags);
-
-        for (i = 0; i < chans; i++) {
-                thrd = &pl330->channels[i];
-                if ((thrd->free) && (!_manager_ns(thrd) ||
-                                        _chan_ns(pi, i))) {
-                        thrd->ev = _alloc_event(thrd);
-                        if (thrd->ev >= 0) {
-                                thrd->free = false;
-                                thrd->lstenq = 1;
-                                thrd->req[0].r = NULL;
-                                mark_free(thrd, 0);
-                                thrd->req[1].r = NULL;
-                                mark_free(thrd, 1);
-                                break;
-                        }
-                }
-                thrd = NULL;
-        }
-
-        spin_unlock_irqrestore(&pl330->lock, flags);
-
-        return thrd;
-}
-
-/* Release an event */
-static inline void _free_event(struct pl330_thread *thrd, int ev)
-{
-        struct pl330_dmac *pl330 = thrd->dmac;
-        struct pl330_info *pi = pl330->pinfo;
-
-        /* If the event is valid and was held by the thread */
-        if (ev >= 0 && ev < pi->pcfg.num_events
-                        && pl330->events[ev] == thrd->id)
-                pl330->events[ev] = -1;
-}
-
-static void pl330_release_channel(void *ch_id)
-{
-        struct pl330_thread *thrd = ch_id;
-        struct pl330_dmac *pl330;
-        unsigned long flags;
-
-        if (!thrd || thrd->free)
-                return;
-
-        _stop(thrd);
-
-        _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
-        _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
-
-        pl330 = thrd->dmac;
-
-        spin_lock_irqsave(&pl330->lock, flags);
-        _free_event(thrd, thrd->ev);
-        thrd->free = true;
-        spin_unlock_irqrestore(&pl330->lock, flags);
-}
-
-/* Initialize the structure for PL330 configuration, that can be used
- * by the client driver the make best use of the DMAC
- */
-static void read_dmac_config(struct pl330_info *pi)
-{
-        void __iomem *regs = pi->base;
-        u32 val;
-
-        val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
-        val &= CRD_DATA_WIDTH_MASK;
-        pi->pcfg.data_bus_width = 8 * (1 << val);
-
-        val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
-        val &= CRD_DATA_BUFF_MASK;
-        pi->pcfg.data_buf_dep = val + 1;
-
-        val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
-        val &= CR0_NUM_CHANS_MASK;
-        val += 1;
-        pi->pcfg.num_chan = val;
-
-        val = readl(regs + CR0);
-        if (val & CR0_PERIPH_REQ_SET) {
-                val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
-                val += 1;
-                pi->pcfg.num_peri = val;
-                pi->pcfg.peri_ns = readl(regs + CR4);
-        } else {
-                pi->pcfg.num_peri = 0;
-        }
-
-        val = readl(regs + CR0);
-        if (val & CR0_BOOT_MAN_NS)
-                pi->pcfg.mode |= DMAC_MODE_NS;
-        else
-                pi->pcfg.mode &= ~DMAC_MODE_NS;
-
-        val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
-        val &= CR0_NUM_EVENTS_MASK;
-        val += 1;
-        pi->pcfg.num_events = val;
-
-        pi->pcfg.irq_ns = readl(regs + CR3);
-
-        pi->pcfg.periph_id = get_id(pi, PERIPH_ID);
-        pi->pcfg.pcell_id = get_id(pi, PCELL_ID);
-}
-
-static inline void _reset_thread(struct pl330_thread *thrd)
-{
-        struct pl330_dmac *pl330 = thrd->dmac;
-        struct pl330_info *pi = pl330->pinfo;
-
-        thrd->req[0].mc_cpu = pl330->mcode_cpu
-                                + (thrd->id * pi->mcbufsz);
-        thrd->req[0].mc_bus = pl330->mcode_bus
-                                + (thrd->id * pi->mcbufsz);
-        thrd->req[0].r = NULL;
-        mark_free(thrd, 0);
-
-        thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
-                                + pi->mcbufsz / 2;
-        thrd->req[1].mc_bus = thrd->req[0].mc_bus
-                                + pi->mcbufsz / 2;
-        thrd->req[1].r = NULL;
-        mark_free(thrd, 1);
-}
-
-static int dmac_alloc_threads(struct pl330_dmac *pl330)
-{
-        struct pl330_info *pi = pl330->pinfo;
-        int chans = pi->pcfg.num_chan;
-        struct pl330_thread *thrd;
-        int i;
-
-        /* Allocate 1 Manager and 'chans' Channel threads */
-        pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
-                                        GFP_KERNEL);
-        if (!pl330->channels)
-                return -ENOMEM;
-
-        /* Init Channel threads */
-        for (i = 0; i < chans; i++) {
-                thrd = &pl330->channels[i];
-                thrd->id = i;
-                thrd->dmac = pl330;
-                _reset_thread(thrd);
-                thrd->free = true;
-        }
-
-        /* MANAGER is indexed at the end */
-        thrd = &pl330->channels[chans];
-        thrd->id = chans;
-        thrd->dmac = pl330;
-        thrd->free = false;
-        pl330->manager = thrd;
-
-        return 0;
-}
-
-static int dmac_alloc_resources(struct pl330_dmac *pl330)
-{
-        struct pl330_info *pi = pl330->pinfo;
-        int chans = pi->pcfg.num_chan;
-        int ret;
-
-        /*
-         * Alloc MicroCode buffer for 'chans' Channel threads.
-         * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
-         */
-        pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
-                                chans * pi->mcbufsz,
-                                &pl330->mcode_bus, GFP_KERNEL);
-        if (!pl330->mcode_cpu) {
-                dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
-                        __func__, __LINE__);
-                return -ENOMEM;
-        }
-
-        ret = dmac_alloc_threads(pl330);
-        if (ret) {
-                dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
-                        __func__, __LINE__);
-                dma_free_coherent(pi->dev,
-                                chans * pi->mcbufsz,
-                                pl330->mcode_cpu, pl330->mcode_bus);
-                return ret;
-        }
-
-        return 0;
-}
-
-static int pl330_add(struct pl330_info *pi)
-{
-        struct pl330_dmac *pl330;
-        void __iomem *regs;
-        int i, ret;
-
-        if (!pi || !pi->dev)
-                return -EINVAL;
-
-        /* If already added */
-        if (pi->pl330_data)
-                return -EINVAL;
-
-        /*
-         * If the SoC can perform reset on the DMAC, then do it
-         * before reading its configuration.
-         */
-        if (pi->dmac_reset)
-                pi->dmac_reset(pi);
-
-        regs = pi->base;
-
-        /* Check if we can handle this DMAC */
-        if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL
-           || get_id(pi, PCELL_ID) != PCELL_ID_VAL) {
-                dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n",
-                        get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID));
-                return -EINVAL;
-        }
-
-        /* Read the configuration of the DMAC */
-        read_dmac_config(pi);
-
-        if (pi->pcfg.num_events == 0) {
-                dev_err(pi->dev, "%s:%d Can't work without events!\n",
-                        __func__, __LINE__);
-                return -EINVAL;
-        }
-
-        pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
-        if (!pl330) {
-                dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
-                        __func__, __LINE__);
-                return -ENOMEM;
-        }
-
-        /* Assign the info structure and private data */
-        pl330->pinfo = pi;
-        pi->pl330_data = pl330;
-
-        spin_lock_init(&pl330->lock);
-
-        INIT_LIST_HEAD(&pl330->req_done);
-
-        /* Use default MC buffer size if not provided */
-        if (!pi->mcbufsz)
-                pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
-
-        /* Mark all events as free */
-        for (i = 0; i < pi->pcfg.num_events; i++)
-                pl330->events[i] = -1;
-
-        /* Allocate resources needed by the DMAC */
-        ret = dmac_alloc_resources(pl330);
-        if (ret) {
-                dev_err(pi->dev, "Unable to create channels for DMAC\n");
-                kfree(pl330);
-                return ret;
-        }
-
-        tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
-
-        pl330->state = INIT;
-
-        return 0;
-}
-
-static int dmac_free_threads(struct pl330_dmac *pl330)
-{
-        struct pl330_info *pi = pl330->pinfo;
-        int chans = pi->pcfg.num_chan;
-        struct pl330_thread *thrd;
-        int i;
-
-        /* Release Channel threads */
-        for (i = 0; i < chans; i++) {
-                thrd = &pl330->channels[i];
-                pl330_release_channel((void *)thrd);
-        }
-
-        /* Free memory */
-        kfree(pl330->channels);
-
-        return 0;
-}
-
-static void dmac_free_resources(struct pl330_dmac *pl330)
-{
-        struct pl330_info *pi = pl330->pinfo;
-        int chans = pi->pcfg.num_chan;
-
-        dmac_free_threads(pl330);
-
-        dma_free_coherent(pi->dev, chans * pi->mcbufsz,
-                                pl330->mcode_cpu, pl330->mcode_bus);
-}
-
-static void pl330_del(struct pl330_info *pi)
-{
-        struct pl330_dmac *pl330;
-
-        if (!pi || !pi->pl330_data)
-                return;
-
-        pl330 = pi->pl330_data;
-
-        pl330->state = UNINIT;
-
-        tasklet_kill(&pl330->tasks);
-
-        /* Free DMAC resources */
-        dmac_free_resources(pl330);
-
-        kfree(pl330);
-        pi->pl330_data = NULL;
-}
-
-/* forward declaration */
-static struct amba_driver pl330_driver;
-
 static inline struct dma_pl330_chan *
 to_pchan(struct dma_chan *ch)
 {
@@ -2217,9 +123,12 @@ static inline void free_desc_list(struct list_head *list)
 {
         struct dma_pl330_dmac *pdmac;
         struct dma_pl330_desc *desc;
-        struct dma_pl330_chan *pch = NULL;
+        struct dma_pl330_chan *pch;
         unsigned long flags;
 
+        if (list_empty(list))
+                return;
+
         /* Finish off the work list */
         list_for_each_entry(desc, list, node) {
                 dma_async_tx_callback callback;
@@ -2236,10 +145,6 @@ static inline void free_desc_list(struct list_head *list)
                 desc->pchan = NULL;
         }
 
-        /* pch will be unset if list was empty */
-        if (!pch)
-                return;
-
         pdmac = pch->dmac;
 
         spin_lock_irqsave(&pdmac->pool_lock, flags);
@@ -2247,32 +152,6 @@ static inline void free_desc_list(struct list_head *list)
         spin_unlock_irqrestore(&pdmac->pool_lock, flags);
 }
 
-static inline void handle_cyclic_desc_list(struct list_head *list)
-{
-        struct dma_pl330_desc *desc;
-        struct dma_pl330_chan *pch = NULL;
-        unsigned long flags;
-
-        list_for_each_entry(desc, list, node) {
-                dma_async_tx_callback callback;
-
-                /* Change status to reload it */
-                desc->status = PREP;
-                pch = desc->pchan;
-                callback = desc->txd.callback;
-                if (callback)
-                        callback(desc->txd.callback_param);
-        }
-
-        /* pch will be unset if list was empty */
-        if (!pch)
-                return;
-
-        spin_lock_irqsave(&pch->lock, flags);
-        list_splice_tail_init(list, &pch->work_list);
-        spin_unlock_irqrestore(&pch->lock, flags);
-}
-
 static inline void fill_queue(struct dma_pl330_chan *pch)
 {
         struct dma_pl330_desc *desc;
@@ -2314,8 +193,7 @@ static void pl330_tasklet(unsigned long data)
         /* Pick up ripe tomatoes */
         list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
                 if (desc->status == DONE) {
-                        if (!pch->cyclic)
-                                dma_cookie_complete(&desc->txd);
+                        pch->completed = desc->txd.cookie;
                         list_move_tail(&desc->node, &list);
                 }
 
@@ -2327,10 +205,7 @@ static void pl330_tasklet(unsigned long data)
 
         spin_unlock_irqrestore(&pch->lock, flags);
 
-        if (pch->cyclic)
-                handle_cyclic_desc_list(&list);
-        else
-                free_desc_list(&list);
+        free_desc_list(&list);
 }
 
 static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
@@ -2352,32 +227,6 @@ static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
         tasklet_schedule(&pch->task);
 }
 
-bool pl330_filter(struct dma_chan *chan, void *param)
-{
-        u8 *peri_id;
-
-        if (chan->device->dev->driver != &pl330_driver.drv)
-                return false;
-
-#ifdef CONFIG_OF
-        if (chan->device->dev->of_node) {
-                const __be32 *prop_value;
-                phandle phandle;
-                struct device_node *node;
-
-                prop_value = ((struct property *)param)->value;
-                phandle = be32_to_cpup(prop_value++);
-                node = of_find_node_by_phandle(phandle);
-                return ((chan->private == node) &&
-                                (chan->chan_id == be32_to_cpup(prop_value)));
-        }
-#endif
-
-        peri_id = chan->private;
-        return *peri_id == (unsigned)param;
-}
-EXPORT_SYMBOL(pl330_filter);
-
 static int pl330_alloc_chan_resources(struct dma_chan *chan)
 {
         struct dma_pl330_chan *pch = to_pchan(chan);
@@ -2386,13 +235,12 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
 
         spin_lock_irqsave(&pch->lock, flags);
 
-        dma_cookie_init(chan);
-        pch->cyclic = false;
+        pch->completed = chan->cookie = 1;
 
         pch->pl330_chid = pl330_request_channel(&pdmac->pif);
         if (!pch->pl330_chid) {
                 spin_unlock_irqrestore(&pch->lock, flags);
-                return -ENOMEM;
+                return 0;
         }
 
         tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
@@ -2405,51 +253,25 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
 static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
 {
         struct dma_pl330_chan *pch = to_pchan(chan);
-        struct dma_pl330_desc *desc, *_dt;
+        struct dma_pl330_desc *desc;
         unsigned long flags;
-        struct dma_pl330_dmac *pdmac = pch->dmac;
-        struct dma_slave_config *slave_config;
-        LIST_HEAD(list);
 
-        switch (cmd) {
-        case DMA_TERMINATE_ALL:
-                spin_lock_irqsave(&pch->lock, flags);
+        /* Only supports DMA_TERMINATE_ALL */
+        if (cmd != DMA_TERMINATE_ALL)
+                return -ENXIO;
 
-                /* FLUSH the PL330 Channel thread */
-                pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
+        spin_lock_irqsave(&pch->lock, flags);
 
-                /* Mark all desc done */
-                list_for_each_entry_safe(desc, _dt, &pch->work_list , node) {
-                        desc->status = DONE;
-                        list_move_tail(&desc->node, &list);
-                }
+        /* FLUSH the PL330 Channel thread */
+        pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
 
-                list_splice_tail_init(&list, &pdmac->desc_pool);
-                spin_unlock_irqrestore(&pch->lock, flags);
-                break;
-        case DMA_SLAVE_CONFIG:
-                slave_config = (struct dma_slave_config *)arg;
-
-                if (slave_config->direction == DMA_MEM_TO_DEV) {
-                        if (slave_config->dst_addr)
-                                pch->fifo_addr = slave_config->dst_addr;
-                        if (slave_config->dst_addr_width)
-                                pch->burst_sz = __ffs(slave_config->dst_addr_width);
-                        if (slave_config->dst_maxburst)
-                                pch->burst_len = slave_config->dst_maxburst;
-                } else if (slave_config->direction == DMA_DEV_TO_MEM) {
-                        if (slave_config->src_addr)
-                                pch->fifo_addr = slave_config->src_addr;
-                        if (slave_config->src_addr_width)
-                                pch->burst_sz = __ffs(slave_config->src_addr_width);
-                        if (slave_config->src_maxburst)
-                                pch->burst_len = slave_config->src_maxburst;
-                }
-                break;
-        default:
-                dev_err(pch->dmac->pif.dev, "Not supported command.\n");
-                return -ENXIO;
-        }
+        /* Mark all desc done */
+        list_for_each_entry(desc, &pch->work_list, node)
+                desc->status = DONE;
+
+        spin_unlock_irqrestore(&pch->lock, flags);
+
+        pl330_tasklet((unsigned long) pch);
 
         return 0;
 }
@@ -2466,9 +288,6 @@ static void pl330_free_chan_resources(struct dma_chan *chan)
         pl330_release_channel(pch->pl330_chid);
         pch->pl330_chid = NULL;
 
-        if (pch->cyclic)
-                list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
-
         spin_unlock_irqrestore(&pch->lock, flags);
 }
 
@@ -2476,7 +295,18 @@ static enum dma_status
 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
                  struct dma_tx_state *txstate)
 {
-        return dma_cookie_status(chan, cookie, txstate);
+        struct dma_pl330_chan *pch = to_pchan(chan);
+        dma_cookie_t last_done, last_used;
+        int ret;
+
+        last_done = pch->completed;
+        last_used = chan->cookie;
+
+        ret = dma_async_is_complete(cookie, last_done, last_used);
+
+        dma_set_tx_state(txstate, last_done, last_used, 0);
+
+        return ret;
 }
 
 static void pl330_issue_pending(struct dma_chan *chan)
@@ -2499,16 +329,26 @@ static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
         spin_lock_irqsave(&pch->lock, flags);
 
         /* Assign cookies to all nodes */
+        cookie = tx->chan->cookie;
+
         while (!list_empty(&last->node)) {
                 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
 
-                dma_cookie_assign(&desc->txd);
+                if (++cookie < 0)
+                        cookie = 1;
+                desc->txd.cookie = cookie;
 
                 list_move_tail(&desc->node, &pch->work_list);
         }
 
-        cookie = dma_cookie_assign(&last->txd);
+        if (++cookie < 0)
+                cookie = 1;
+        last->txd.cookie = cookie;
+
         list_add_tail(&last->node, &pch->work_list);
+
+        tx->chan->cookie = cookie;
+
         spin_unlock_irqrestore(&pch->lock, flags);
 
         return cookie;
@@ -2532,7 +372,7 @@ static inline void _init_desc(struct dma_pl330_desc *desc)
 }
 
 /* Returns the number of descriptors added to the DMAC pool */
-static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
+int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
 {
         struct dma_pl330_desc *desc;
         unsigned long flags;
@@ -2586,7 +426,7 @@ pluck_desc(struct dma_pl330_dmac *pdmac)
 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
 {
         struct dma_pl330_dmac *pdmac = pch->dmac;
-        u8 *peri_id = pch->chan.private;
+        struct dma_pl330_peri *peri = pch->chan.private;
         struct dma_pl330_desc *desc;
 
         /* Pluck one desc from the pool of DMAC */
@@ -2611,8 +451,13 @@ static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
         desc->txd.cookie = 0;
         async_tx_ack(&desc->txd);
 
-        desc->req.peri = peri_id ? pch->chan.chan_id : 0;
-        desc->rqcfg.pcfg = &pch->dmac->pif.pcfg;
+        if (peri) {
+                desc->req.rqtype = peri->rqtype;
+                desc->req.peri = peri->peri_id;
+        } else {
+                desc->req.rqtype = MEMTOMEM;
+                desc->req.peri = 0;
+        }
 
         dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
 
@@ -2679,66 +524,22 @@ static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
         return burst_len;
 }
 
-static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
-                struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
-                size_t period_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
-{
-        struct dma_pl330_desc *desc;
-        struct dma_pl330_chan *pch = to_pchan(chan);
-        dma_addr_t dst;
-        dma_addr_t src;
-
-        desc = pl330_get_desc(pch);
-        if (!desc) {
-                dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
-                        __func__, __LINE__);
-                return NULL;
-        }
-
-        switch (direction) {
-        case DMA_MEM_TO_DEV:
-                desc->rqcfg.src_inc = 1;
-                desc->rqcfg.dst_inc = 0;
-                desc->req.rqtype = MEMTODEV;
-                src = dma_addr;
-                dst = pch->fifo_addr;
-                break;
-        case DMA_DEV_TO_MEM:
-                desc->rqcfg.src_inc = 0;
-                desc->rqcfg.dst_inc = 1;
-                desc->req.rqtype = DEVTOMEM;
-                src = pch->fifo_addr;
-                dst = dma_addr;
-                break;
-        default:
-                dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
-                __func__, __LINE__);
-                return NULL;
-        }
-
-        desc->rqcfg.brst_size = pch->burst_sz;
-        desc->rqcfg.brst_len = 1;
-
-        pch->cyclic = true;
-
-        fill_px(&desc->px, dst, src, period_len);
-
-        return &desc->txd;
-}
-
 static struct dma_async_tx_descriptor *
 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
                 dma_addr_t src, size_t len, unsigned long flags)
 {
         struct dma_pl330_desc *desc;
         struct dma_pl330_chan *pch = to_pchan(chan);
+        struct dma_pl330_peri *peri = chan->private;
         struct pl330_info *pi;
         int burst;
 
         if (unlikely(!pch || !len))
                 return NULL;
 
+        if (peri && peri->rqtype != MEMTOMEM)
+                return NULL;
+
         pi = &pch->dmac->pif;
 
         desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
@@ -2747,7 +548,6 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
 
         desc->rqcfg.src_inc = 1;
         desc->rqcfg.dst_inc = 1;
-        desc->req.rqtype = MEMTOMEM;
 
         /* Select max possible burst size */
         burst = pi->pcfg.data_bus_width / 8;
@@ -2771,20 +571,32 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
 
 static struct dma_async_tx_descriptor *
 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-                unsigned int sg_len, enum dma_transfer_direction direction,
-                unsigned long flg, void *context)
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flg)
 {
         struct dma_pl330_desc *first, *desc = NULL;
         struct dma_pl330_chan *pch = to_pchan(chan);
+        struct dma_pl330_peri *peri = chan->private;
         struct scatterlist *sg;
         unsigned long flags;
-        int i;
+        int i, burst_size;
         dma_addr_t addr;
 
-        if (unlikely(!pch || !sgl || !sg_len))
+        if (unlikely(!pch || !sgl || !sg_len || !peri))
+                return NULL;
+
+        /* Make sure the direction is consistent */
+        if ((direction == DMA_TO_DEVICE &&
+                                peri->rqtype != MEMTODEV) ||
+                        (direction == DMA_FROM_DEVICE &&
+                                peri->rqtype != DEVTOMEM)) {
+                dev_err(pch->dmac->pif.dev, "%s:%d Invalid Direction\n",
+                                __func__, __LINE__);
                 return NULL;
+        }
 
-        addr = pch->fifo_addr;
+        addr = peri->fifo_addr;
+        burst_size = peri->burst_sz;
 
         first = NULL;
 
@@ -2820,21 +632,19 @@ pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                 else
                         list_add_tail(&desc->node, &first->node);
 
-                if (direction == DMA_MEM_TO_DEV) {
+                if (direction == DMA_TO_DEVICE) {
                         desc->rqcfg.src_inc = 1;
                         desc->rqcfg.dst_inc = 0;
-                        desc->req.rqtype = MEMTODEV;
                         fill_px(&desc->px,
                                 addr, sg_dma_address(sg), sg_dma_len(sg));
                 } else {
                         desc->rqcfg.src_inc = 0;
                         desc->rqcfg.dst_inc = 1;
-                        desc->req.rqtype = DEVTOMEM;
                         fill_px(&desc->px,
                                 sg_dma_address(sg), addr, sg_dma_len(sg));
                 }
 
-                desc->rqcfg.brst_size = pch->burst_sz;
+                desc->rqcfg.brst_size = burst_size;
                 desc->rqcfg.brst_len = 1;
         }
 
@@ -2851,7 +661,7 @@ static irqreturn_t pl330_irq_handler(int irq, void *data)
                 return IRQ_NONE;
 }
 
-static int
+static int __devinit
 pl330_probe(struct amba_device *adev, const struct amba_id *id)
 {
         struct dma_pl330_platdata *pdat;
@@ -2886,8 +696,6 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
                 goto probe_err1;
         }
 
-        amba_set_drvdata(adev, pdmac);
-
         irq = adev->irq[0];
         ret = request_irq(irq, pl330_irq_handler, 0,
                         dev_name(&adev->dev), pi);
@@ -2909,51 +717,49 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
         INIT_LIST_HEAD(&pd->channels);
 
         /* Initialize channel parameters */
-        if (pdat)
-                num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
-        else
-                num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
-
+        num_chan = max(pdat ? pdat->nr_valid_peri : 0, (u8)pi->pcfg.num_chan);
         pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
-        if (!pdmac->peripherals) {
-                ret = -ENOMEM;
-                dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n");
-                goto probe_err4;
-        }
 
         for (i = 0; i < num_chan; i++) {
                 pch = &pdmac->peripherals[i];
-                if (!adev->dev.of_node)
-                        pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
-                else
-                        pch->chan.private = adev->dev.of_node;
+                if (pdat) {
+                        struct dma_pl330_peri *peri = &pdat->peri[i];
+
+                        switch (peri->rqtype) {
+                        case MEMTOMEM:
+                                dma_cap_set(DMA_MEMCPY, pd->cap_mask);
+                                break;
+                        case MEMTODEV:
+                        case DEVTOMEM:
+                                dma_cap_set(DMA_SLAVE, pd->cap_mask);
+                                break;
+                        default:
+                                dev_err(&adev->dev, "DEVTODEV Not Supported\n");
+                                continue;
+                        }
+                        pch->chan.private = peri;
+                } else {
+                        dma_cap_set(DMA_MEMCPY, pd->cap_mask);
+                        pch->chan.private = NULL;
+                }
 
                 INIT_LIST_HEAD(&pch->work_list);
                 spin_lock_init(&pch->lock);
                 pch->pl330_chid = NULL;
                 pch->chan.device = pd;
+                pch->chan.chan_id = i;
                 pch->dmac = pdmac;
 
                 /* Add the channel to the DMAC list */
+                pd->chancnt++;
                 list_add_tail(&pch->chan.device_node, &pd->channels);
         }
 
         pd->dev = &adev->dev;
-        if (pdat) {
-                pd->cap_mask = pdat->cap_mask;
-        } else {
-                dma_cap_set(DMA_MEMCPY, pd->cap_mask);
-                if (pi->pcfg.num_peri) {
-                        dma_cap_set(DMA_SLAVE, pd->cap_mask);
-                        dma_cap_set(DMA_CYCLIC, pd->cap_mask);
-                        dma_cap_set(DMA_PRIVATE, pd->cap_mask);
-                }
-        }
 
         pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
         pd->device_free_chan_resources = pl330_free_chan_resources;
         pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
-        pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
         pd->device_tx_status = pl330_tx_status;
         pd->device_prep_slave_sg = pl330_prep_slave_sg;
         pd->device_control = pl330_control;
@@ -2965,6 +771,8 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
                 goto probe_err4;
         }
 
+        amba_set_drvdata(adev, pdmac);
+
         dev_info(&adev->dev,
                 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
         dev_info(&adev->dev,
@@ -2988,7 +796,7 @@ probe_err1:
         return ret;
 }
 
-static int pl330_remove(struct amba_device *adev)
+static int __devexit pl330_remove(struct amba_device *adev)
 {
         struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
         struct dma_pl330_chan *pch, *_p;
@@ -3038,8 +846,6 @@ static struct amba_id pl330_ids[] = {
         { 0, 0 },
 };
 
-MODULE_DEVICE_TABLE(amba, pl330_ids);
-
 static struct amba_driver pl330_driver = {
         .drv = {
                 .owner = THIS_MODULE,
@@ -3050,7 +856,18 @@ static struct amba_driver pl330_driver = {
         .remove = pl330_remove,
 };
 
-module_amba_driver(pl330_driver);
+static int __init pl330_init(void)
+{
+        return amba_driver_register(&pl330_driver);
+}
+module_init(pl330_init);
+
+static void __exit pl330_exit(void)
+{
+        amba_driver_unregister(&pl330_driver);
+        return;
+}
+module_exit(pl330_exit);
 
 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index 5d3d95569a1..fc457a7e883 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -46,7 +46,6 @@
 #include <asm/dcr.h>
 #include <asm/dcr-regs.h>
 #include "adma.h"
-#include "../dmaengine.h"
 
 enum ppc_adma_init_code {
         PPC_ADMA_INIT_OK = 0,
@@ -1931,7 +1930,7 @@ static void __ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
                                 if (end_of_chain && slot_cnt) {
                                         /* Should wait for ZeroSum completion */
                                         if (cookie > 0)
-                                                chan->common.completed_cookie = cookie;
+                                                chan->completed_cookie = cookie;
                                         return;
                                 }
 
@@ -1961,7 +1960,7 @@ static void __ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
         BUG_ON(!seen_current);
 
         if (cookie > 0) {
-                chan->common.completed_cookie = cookie;
+                chan->completed_cookie = cookie;
                 pr_debug("\tcompleted cookie %d\n", cookie);
         }
 
@@ -2151,6 +2150,22 @@ static int ppc440spe_adma_alloc_chan_resources(struct dma_chan *chan)
 }
 
 /**
+ * ppc440spe_desc_assign_cookie - assign a cookie
+ */
+static dma_cookie_t ppc440spe_desc_assign_cookie(
+                struct ppc440spe_adma_chan *chan,
+                struct ppc440spe_adma_desc_slot *desc)
+{
+        dma_cookie_t cookie = chan->common.cookie;
+
+        cookie++;
+        if (cookie < 0)
+                cookie = 1;
+        chan->common.cookie = desc->async_tx.cookie = cookie;
+        return cookie;
+}
+
+/**
  * ppc440spe_rxor_set_region_data -
  */
 static void ppc440spe_rxor_set_region(struct ppc440spe_adma_desc_slot *desc,
@@ -2220,7 +2235,8 @@ static dma_cookie_t ppc440spe_adma_tx_submit(struct dma_async_tx_descriptor *tx)
         slots_per_op = group_start->slots_per_op;
 
         spin_lock_bh(&chan->lock);
-        cookie = dma_cookie_assign(tx);
+
+        cookie = ppc440spe_desc_assign_cookie(chan, sw_desc);
 
         if (unlikely(list_empty(&chan->chain))) {
                 /* first peer */
@@ -3928,16 +3944,28 @@ static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
                         dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
         struct ppc440spe_adma_chan *ppc440spe_chan;
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
         enum dma_status ret;
 
         ppc440spe_chan = to_ppc440spe_adma_chan(chan);
-        ret = dma_cookie_status(chan, cookie, txstate);
+        last_used = chan->cookie;
+        last_complete = ppc440spe_chan->completed_cookie;
+
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
         if (ret == DMA_SUCCESS)
                 return ret;
 
         ppc440spe_adma_slot_cleanup(ppc440spe_chan);
 
-        return dma_cookie_status(chan, cookie, txstate);
+        last_used = chan->cookie;
+        last_complete = ppc440spe_chan->completed_cookie;
+
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+        return dma_async_is_complete(cookie, last_complete, last_used);
 }
 
 /**
@@ -4022,12 +4050,16 @@ static void ppc440spe_chan_start_null_xor(struct ppc440spe_adma_chan *chan)
                 async_tx_ack(&sw_desc->async_tx);
                 ppc440spe_desc_init_null_xor(group_start);
 
-                cookie = dma_cookie_assign(&sw_desc->async_tx);
+                cookie = chan->common.cookie;
+                cookie++;
+                if (cookie <= 1)
+                        cookie = 2;
 
                 /* initialize the completed cookie to be less than
                  * the most recently used cookie
                  */
-                chan->common.completed_cookie = cookie - 1;
+                chan->completed_cookie = cookie - 1;
+                chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
                 /* channel should not be busy */
                 BUG_ON(ppc440spe_chan_is_busy(chan));
@@ -4361,7 +4393,7 @@ static void ppc440spe_adma_release_irqs(struct ppc440spe_adma_device *adev,
 /**
  * ppc440spe_adma_probe - probe the asynch device
  */
-static int ppc440spe_adma_probe(struct platform_device *ofdev)
+static int __devinit ppc440spe_adma_probe(struct platform_device *ofdev)
 {
         struct device_node *np = ofdev->dev.of_node;
         struct resource res;
@@ -4446,7 +4478,7 @@ static int ppc440spe_adma_probe(struct platform_device *ofdev)
                 ret = -ENOMEM;
                 goto err_dma_alloc;
         }
-        dev_dbg(&ofdev->dev, "allocated descriptor pool virt 0x%p phys 0x%llx\n",
+        dev_dbg(&ofdev->dev, "allocted descriptor pool virt 0x%p phys 0x%llx\n",
                 adev->dma_desc_pool_virt, (u64)adev->dma_desc_pool);
 
         regs = ioremap(res.start, resource_size(&res));
@@ -4497,7 +4529,6 @@ static int ppc440spe_adma_probe(struct platform_device *ofdev)
         INIT_LIST_HEAD(&chan->all_slots);
         chan->device = adev;
         chan->common.device = &adev->common;
-        dma_cookie_init(&chan->common);
         list_add_tail(&chan->common.device_node, &adev->common.channels);
         tasklet_init(&chan->irq_tasklet, ppc440spe_adma_tasklet,
                      (unsigned long)chan);
@@ -4592,7 +4623,7 @@ out:
 /**
  * ppc440spe_adma_remove - remove the asynch device
  */
-static int ppc440spe_adma_remove(struct platform_device *ofdev)
+static int __devexit ppc440spe_adma_remove(struct platform_device *ofdev)
 {
         struct ppc440spe_adma_device *adev = dev_get_drvdata(&ofdev->dev);
         struct device_node *np = ofdev->dev.of_node;
@@ -4905,7 +4936,7 @@ out_free:
         return ret;
 }
 
-static const struct of_device_id ppc440spe_adma_of_match[] = {
+static const struct of_device_id ppc440spe_adma_of_match[] __devinitconst = {
         { .compatible   = "ibm,dma-440spe", },
         { .compatible   = "amcc,xor-accelerator", },
         {},
@@ -4914,7 +4945,7 @@ MODULE_DEVICE_TABLE(of, ppc440spe_adma_of_match);
 
 static struct platform_driver ppc440spe_adma_driver = {
         .probe = ppc440spe_adma_probe,
-        .remove = ppc440spe_adma_remove,
+        .remove = __devexit_p(ppc440spe_adma_remove),
         .driver = {
                 .name = "PPC440SP(E)-ADMA",
                 .owner = THIS_MODULE,
diff --git a/drivers/dma/ppc4xx/adma.h b/drivers/dma/ppc4xx/adma.h
index 26b7a5ed9ac..8ada5a812e3 100644
--- a/drivers/dma/ppc4xx/adma.h
+++ b/drivers/dma/ppc4xx/adma.h
@@ -81,6 +81,7 @@ struct ppc440spe_adma_device {
  * @common: common dmaengine channel object members
  * @all_slots: complete domain of slots usable by the channel
  * @pending: allows batching of hardware operations
+ * @completed_cookie: identifier for the most recently completed operation
  * @slots_allocated: records the actual size of the descriptor slot pool
  * @hw_chain_inited: h/w descriptor chain initialization flag
  * @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
@@ -98,6 +99,7 @@ struct ppc440spe_adma_chan {
         struct list_head all_slots;
         struct ppc440spe_adma_desc_slot *last_used;
         int pending;
+        dma_cookie_t completed_cookie;
         int slots_allocated;
         int hw_chain_inited;
         struct tasklet_struct irq_tasklet;
diff --git a/drivers/dma/sa11x0-dma.c b/drivers/dma/sa11x0-dma.c
deleted file mode 100644
index 461a91ab70b..00000000000
--- a/drivers/dma/sa11x0-dma.c
+++ /dev/null
@@ -1,1105 +0,0 @@
-/*
- * SA11x0 DMAengine support
- *
- * Copyright (C) 2012 Russell King
- *   Derived in part from arch/arm/mach-sa1100/dma.c,
- *   Copyright (C) 2000, 2001 by Nicolas Pitre
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/sched.h>
-#include <linux/device.h>
-#include <linux/dmaengine.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/sa11x0-dma.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-#include "virt-dma.h"
-
-#define NR_PHY_CHAN     6
-#define DMA_ALIGN       3
-#define DMA_MAX_SIZE    0x1fff
-#define DMA_CHUNK_SIZE  0x1000
-
-#define DMA_DDAR        0x00
-#define DMA_DCSR_S      0x04
-#define DMA_DCSR_C      0x08
-#define DMA_DCSR_R      0x0c
-#define DMA_DBSA        0x10
-#define DMA_DBTA        0x14
-#define DMA_DBSB        0x18
-#define DMA_DBTB        0x1c
-#define DMA_SIZE        0x20
-
-#define DCSR_RUN        (1 << 0)
-#define DCSR_IE         (1 << 1)
-#define DCSR_ERROR      (1 << 2)
-#define DCSR_DONEA      (1 << 3)
-#define DCSR_STRTA      (1 << 4)
-#define DCSR_DONEB      (1 << 5)
-#define DCSR_STRTB      (1 << 6)
-#define DCSR_BIU        (1 << 7)
-
-#define DDAR_RW         (1 << 0)        /* 0 = W, 1 = R */
-#define DDAR_E          (1 << 1)        /* 0 = LE, 1 = BE */
-#define DDAR_BS         (1 << 2)        /* 0 = BS4, 1 = BS8 */
-#define DDAR_DW         (1 << 3)        /* 0 = 8b, 1 = 16b */
-#define DDAR_Ser0UDCTr  (0x0 << 4)
-#define DDAR_Ser0UDCRc  (0x1 << 4)
-#define DDAR_Ser1SDLCTr (0x2 << 4)
-#define DDAR_Ser1SDLCRc (0x3 << 4)
-#define DDAR_Ser1UARTTr (0x4 << 4)
-#define DDAR_Ser1UARTRc (0x5 << 4)
-#define DDAR_Ser2ICPTr  (0x6 << 4)
-#define DDAR_Ser2ICPRc  (0x7 << 4)
-#define DDAR_Ser3UARTTr (0x8 << 4)
-#define DDAR_Ser3UARTRc (0x9 << 4)
-#define DDAR_Ser4MCP0Tr (0xa << 4)
-#define DDAR_Ser4MCP0Rc (0xb << 4)
-#define DDAR_Ser4MCP1Tr (0xc << 4)
-#define DDAR_Ser4MCP1Rc (0xd << 4)
-#define DDAR_Ser4SSPTr  (0xe << 4)
-#define DDAR_Ser4SSPRc  (0xf << 4)
-
-struct sa11x0_dma_sg {
-        u32                     addr;
-        u32                     len;
-};
-
-struct sa11x0_dma_desc {
-        struct virt_dma_desc    vd;
-
-        u32                     ddar;
-        size_t                  size;
-        unsigned                period;
-        bool                    cyclic;
-
-        unsigned                sglen;
-        struct sa11x0_dma_sg    sg[0];
-};
-
-struct sa11x0_dma_phy;
-
-struct sa11x0_dma_chan {
-        struct virt_dma_chan    vc;
-
-        /* protected by c->vc.lock */
-        struct sa11x0_dma_phy   *phy;
-        enum dma_status         status;
-
-        /* protected by d->lock */
-        struct list_head        node;
-
-        u32                     ddar;
-        const char              *name;
-};
-
-struct sa11x0_dma_phy {
-        void __iomem            *base;
-        struct sa11x0_dma_dev   *dev;
-        unsigned                num;
-
-        struct sa11x0_dma_chan  *vchan;
-
-        /* Protected by c->vc.lock */
-        unsigned                sg_load;
-        struct sa11x0_dma_desc  *txd_load;
-        unsigned                sg_done;
-        struct sa11x0_dma_desc  *txd_done;
-#ifdef CONFIG_PM_SLEEP
-        u32                     dbs[2];
-        u32                     dbt[2];
-        u32                     dcsr;
-#endif
-};
-
-struct sa11x0_dma_dev {
-        struct dma_device       slave;
-        void __iomem            *base;
-        spinlock_t              lock;
-        struct tasklet_struct   task;
-        struct list_head        chan_pending;
-        struct sa11x0_dma_phy   phy[NR_PHY_CHAN];
-};
-
-static struct sa11x0_dma_chan *to_sa11x0_dma_chan(struct dma_chan *chan)
-{
-        return container_of(chan, struct sa11x0_dma_chan, vc.chan);
-}
-
-static struct sa11x0_dma_dev *to_sa11x0_dma(struct dma_device *dmadev)
-{
-        return container_of(dmadev, struct sa11x0_dma_dev, slave);
-}
-
-static struct sa11x0_dma_desc *sa11x0_dma_next_desc(struct sa11x0_dma_chan *c)
-{
-        struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
-
-        return vd ? container_of(vd, struct sa11x0_dma_desc, vd) : NULL;
-}
-
-static void sa11x0_dma_free_desc(struct virt_dma_desc *vd)
-{
-        kfree(container_of(vd, struct sa11x0_dma_desc, vd));
-}
-
-static void sa11x0_dma_start_desc(struct sa11x0_dma_phy *p, struct sa11x0_dma_desc *txd)
-{
-        list_del(&txd->vd.node);
-        p->txd_load = txd;
-        p->sg_load = 0;
-
-        dev_vdbg(p->dev->slave.dev, "pchan %u: txd %p[%x]: starting: DDAR:%x\n",
-                p->num, &txd->vd, txd->vd.tx.cookie, txd->ddar);
-}
-
-static void noinline sa11x0_dma_start_sg(struct sa11x0_dma_phy *p,
-        struct sa11x0_dma_chan *c)
-{
-        struct sa11x0_dma_desc *txd = p->txd_load;
-        struct sa11x0_dma_sg *sg;
-        void __iomem *base = p->base;
-        unsigned dbsx, dbtx;
-        u32 dcsr;
-
-        if (!txd)
-                return;
-
-        dcsr = readl_relaxed(base + DMA_DCSR_R);
-
-        /* Don't try to load the next transfer if both buffers are started */
-        if ((dcsr & (DCSR_STRTA | DCSR_STRTB)) == (DCSR_STRTA | DCSR_STRTB))
-                return;
-
-        if (p->sg_load == txd->sglen) {
-                if (!txd->cyclic) {
-                        struct sa11x0_dma_desc *txn = sa11x0_dma_next_desc(c);
-
-                        /*
-                         * We have reached the end of the current descriptor.
-                         * Peek at the next descriptor, and if compatible with
-                         * the current, start processing it.
-                         */
-                        if (txn && txn->ddar == txd->ddar) {
-                                txd = txn;
-                                sa11x0_dma_start_desc(p, txn);
-                        } else {
-                                p->txd_load = NULL;
-                                return;
-                        }
-                } else {
-                        /* Cyclic: reset back to beginning */
-                        p->sg_load = 0;
-                }
-        }
-
-        sg = &txd->sg[p->sg_load++];
-
-        /* Select buffer to load according to channel status */
-        if (((dcsr & (DCSR_BIU | DCSR_STRTB)) == (DCSR_BIU | DCSR_STRTB)) ||
-            ((dcsr & (DCSR_BIU | DCSR_STRTA)) == 0)) {
-                dbsx = DMA_DBSA;
-                dbtx = DMA_DBTA;
-                dcsr = DCSR_STRTA | DCSR_IE | DCSR_RUN;
-        } else {
-                dbsx = DMA_DBSB;
-                dbtx = DMA_DBTB;
-                dcsr = DCSR_STRTB | DCSR_IE | DCSR_RUN;
-        }
-
-        writel_relaxed(sg->addr, base + dbsx);
-        writel_relaxed(sg->len, base + dbtx);
-        writel(dcsr, base + DMA_DCSR_S);
-
-        dev_dbg(p->dev->slave.dev, "pchan %u: load: DCSR:%02x DBS%c:%08x DBT%c:%08x\n",
-                p->num, dcsr,
-                'A' + (dbsx == DMA_DBSB), sg->addr,
-                'A' + (dbtx == DMA_DBTB), sg->len);
-}
-
-static void noinline sa11x0_dma_complete(struct sa11x0_dma_phy *p,
-        struct sa11x0_dma_chan *c)
-{
-        struct sa11x0_dma_desc *txd = p->txd_done;
-
-        if (++p->sg_done == txd->sglen) {
-                if (!txd->cyclic) {
-                        vchan_cookie_complete(&txd->vd);
-
-                        p->sg_done = 0;
-                        p->txd_done = p->txd_load;
-
-                        if (!p->txd_done)
-                                tasklet_schedule(&p->dev->task);
-                } else {
-                        if ((p->sg_done % txd->period) == 0)
-                                vchan_cyclic_callback(&txd->vd);
-
-                        /* Cyclic: reset back to beginning */
-                        p->sg_done = 0;
-                }
-        }
-
-        sa11x0_dma_start_sg(p, c);
-}
-
-static irqreturn_t sa11x0_dma_irq(int irq, void *dev_id)
-{
-        struct sa11x0_dma_phy *p = dev_id;
-        struct sa11x0_dma_dev *d = p->dev;
-        struct sa11x0_dma_chan *c;
-        u32 dcsr;
-
-        dcsr = readl_relaxed(p->base + DMA_DCSR_R);
-        if (!(dcsr & (DCSR_ERROR | DCSR_DONEA | DCSR_DONEB)))
-                return IRQ_NONE;
-
-        /* Clear reported status bits */
-        writel_relaxed(dcsr & (DCSR_ERROR | DCSR_DONEA | DCSR_DONEB),
-                p->base + DMA_DCSR_C);
-
-        dev_dbg(d->slave.dev, "pchan %u: irq: DCSR:%02x\n", p->num, dcsr);
-
-        if (dcsr & DCSR_ERROR) {
-                dev_err(d->slave.dev, "pchan %u: error. DCSR:%02x DDAR:%08x DBSA:%08x DBTA:%08x DBSB:%08x DBTB:%08x\n",
-                        p->num, dcsr,
-                        readl_relaxed(p->base + DMA_DDAR),
-                        readl_relaxed(p->base + DMA_DBSA),
-                        readl_relaxed(p->base + DMA_DBTA),
-                        readl_relaxed(p->base + DMA_DBSB),
-                        readl_relaxed(p->base + DMA_DBTB));
-        }
-
-        c = p->vchan;
-        if (c) {
-                unsigned long flags;
-
-                spin_lock_irqsave(&c->vc.lock, flags);
-                /*
-                 * Now that we're holding the lock, check that the vchan
-                 * really is associated with this pchan before touching the
-                 * hardware.  This should always succeed, because we won't
-                 * change p->vchan or c->phy while the channel is actively
-                 * transferring.
-                 */
-                if (c->phy == p) {
-                        if (dcsr & DCSR_DONEA)
-                                sa11x0_dma_complete(p, c);
-                        if (dcsr & DCSR_DONEB)
-                                sa11x0_dma_complete(p, c);
-                }
-                spin_unlock_irqrestore(&c->vc.lock, flags);
-        }
-
-        return IRQ_HANDLED;
-}
-
-static void sa11x0_dma_start_txd(struct sa11x0_dma_chan *c)
-{
-        struct sa11x0_dma_desc *txd = sa11x0_dma_next_desc(c);
-
-        /* If the issued list is empty, we have no further txds to process */
-        if (txd) {
-                struct sa11x0_dma_phy *p = c->phy;
-
-                sa11x0_dma_start_desc(p, txd);
-                p->txd_done = txd;
-                p->sg_done = 0;
-
-                /* The channel should not have any transfers started */
-                WARN_ON(readl_relaxed(p->base + DMA_DCSR_R) &
-                                      (DCSR_STRTA | DCSR_STRTB));
-
-                /* Clear the run and start bits before changing DDAR */
-                writel_relaxed(DCSR_RUN | DCSR_STRTA | DCSR_STRTB,
-                               p->base + DMA_DCSR_C);
-                writel_relaxed(txd->ddar, p->base + DMA_DDAR);
-
-                /* Try to start both buffers */
-                sa11x0_dma_start_sg(p, c);
-                sa11x0_dma_start_sg(p, c);
-        }
-}
-
-static void sa11x0_dma_tasklet(unsigned long arg)
-{
-        struct sa11x0_dma_dev *d = (struct sa11x0_dma_dev *)arg;
-        struct sa11x0_dma_phy *p;
-        struct sa11x0_dma_chan *c;
-        unsigned pch, pch_alloc = 0;
-
-        dev_dbg(d->slave.dev, "tasklet enter\n");
-
-        list_for_each_entry(c, &d->slave.channels, vc.chan.device_node) {
-                spin_lock_irq(&c->vc.lock);
-                p = c->phy;
-                if (p && !p->txd_done) {
-                        sa11x0_dma_start_txd(c);
-                        if (!p->txd_done) {
-                                /* No current txd associated with this channel */
-                                dev_dbg(d->slave.dev, "pchan %u: free\n", p->num);
-
-                                /* Mark this channel free */
-                                c->phy = NULL;
-                                p->vchan = NULL;
-                        }
-                }
-                spin_unlock_irq(&c->vc.lock);
-        }
-
-        spin_lock_irq(&d->lock);
-        for (pch = 0; pch < NR_PHY_CHAN; pch++) {
-                p = &d->phy[pch];
-
-                if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
-                        c = list_first_entry(&d->chan_pending,
-                                struct sa11x0_dma_chan, node);
-                        list_del_init(&c->node);
-
-                        pch_alloc |= 1 << pch;
-
-                        /* Mark this channel allocated */
-                        p->vchan = c;
-
-                        dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
-                }
-        }
-        spin_unlock_irq(&d->lock);
-
-        for (pch = 0; pch < NR_PHY_CHAN; pch++) {
-                if (pch_alloc & (1 << pch)) {
-                        p = &d->phy[pch];
-                        c = p->vchan;
-
-                        spin_lock_irq(&c->vc.lock);
-                        c->phy = p;
-
-                        sa11x0_dma_start_txd(c);
-                        spin_unlock_irq(&c->vc.lock);
-                }
-        }
-
-        dev_dbg(d->slave.dev, "tasklet exit\n");
-}
-
-
-static int sa11x0_dma_alloc_chan_resources(struct dma_chan *chan)
-{
-        return 0;
-}
-
-static void sa11x0_dma_free_chan_resources(struct dma_chan *chan)
-{
-        struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
-        struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
-        unsigned long flags;
-
-        spin_lock_irqsave(&d->lock, flags);
-        list_del_init(&c->node);
-        spin_unlock_irqrestore(&d->lock, flags);
-
-        vchan_free_chan_resources(&c->vc);
-}
-
-static dma_addr_t sa11x0_dma_pos(struct sa11x0_dma_phy *p)
-{
-        unsigned reg;
-        u32 dcsr;
-
-        dcsr = readl_relaxed(p->base + DMA_DCSR_R);
-
-        if ((dcsr & (DCSR_BIU | DCSR_STRTA)) == DCSR_STRTA ||
-            (dcsr & (DCSR_BIU | DCSR_STRTB)) == DCSR_BIU)
-                reg = DMA_DBSA;
-        else
-                reg = DMA_DBSB;
-
-        return readl_relaxed(p->base + reg);
-}
-
-static enum dma_status sa11x0_dma_tx_status(struct dma_chan *chan,
-        dma_cookie_t cookie, struct dma_tx_state *state)
-{
-        struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
-        struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
-        struct sa11x0_dma_phy *p;
-        struct virt_dma_desc *vd;
-        unsigned long flags;
-        enum dma_status ret;
-
-        ret = dma_cookie_status(&c->vc.chan, cookie, state);
-        if (ret == DMA_SUCCESS)
-                return ret;
-
-        if (!state)
-                return c->status;
-
-        spin_lock_irqsave(&c->vc.lock, flags);
-        p = c->phy;
-
-        /*
-         * If the cookie is on our issue queue, then the residue is
-         * its total size.
-         */
-        vd = vchan_find_desc(&c->vc, cookie);
-        if (vd) {
-                state->residue = container_of(vd, struct sa11x0_dma_desc, vd)->size;
-        } else if (!p) {
-                state->residue = 0;
-        } else {
-                struct sa11x0_dma_desc *txd;
-                size_t bytes = 0;
-
-                if (p->txd_done && p->txd_done->vd.tx.cookie == cookie)
-                        txd = p->txd_done;
-                else if (p->txd_load && p->txd_load->vd.tx.cookie == cookie)
-                        txd = p->txd_load;
-                else
-                        txd = NULL;
-
-                ret = c->status;
-                if (txd) {
-                        dma_addr_t addr = sa11x0_dma_pos(p);
-                        unsigned i;
-
-                        dev_vdbg(d->slave.dev, "tx_status: addr:%x\n", addr);
-
-                        for (i = 0; i < txd->sglen; i++) {
-                                dev_vdbg(d->slave.dev, "tx_status: [%u] %x+%x\n",
-                                        i, txd->sg[i].addr, txd->sg[i].len);
-                                if (addr >= txd->sg[i].addr &&
-                                    addr < txd->sg[i].addr + txd->sg[i].len) {
-                                        unsigned len;
-
-                                        len = txd->sg[i].len -
-                                                (addr - txd->sg[i].addr);
-                                        dev_vdbg(d->slave.dev, "tx_status: [%u] +%x\n",
-                                                i, len);
-                                        bytes += len;
-                                        i++;
-                                        break;
-                                }
-                        }
-                        for (; i < txd->sglen; i++) {
-                                dev_vdbg(d->slave.dev, "tx_status: [%u] %x+%x ++\n",
-                                        i, txd->sg[i].addr, txd->sg[i].len);
-                                bytes += txd->sg[i].len;
-                        }
-                }
-                state->residue = bytes;
-        }
-        spin_unlock_irqrestore(&c->vc.lock, flags);
-
-        dev_vdbg(d->slave.dev, "tx_status: bytes 0x%zx\n", state->residue);
-
-        return ret;
-}
-
-/*
- * Move pending txds to the issued list, and re-init pending list.
- * If not already pending, add this channel to the list of pending
- * channels and trigger the tasklet to run.
- */
-static void sa11x0_dma_issue_pending(struct dma_chan *chan)
-{
-        struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
-        struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->vc.lock, flags);
-        if (vchan_issue_pending(&c->vc)) {
-                if (!c->phy) {
-                        spin_lock(&d->lock);
-                        if (list_empty(&c->node)) {
-                                list_add_tail(&c->node, &d->chan_pending);
-                                tasklet_schedule(&d->task);
-                                dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
-                        }
-                        spin_unlock(&d->lock);
-                }
-        } else
-                dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
-        spin_unlock_irqrestore(&c->vc.lock, flags);
-}
-
-static struct dma_async_tx_descriptor *sa11x0_dma_prep_slave_sg(
-        struct dma_chan *chan, struct scatterlist *sg, unsigned int sglen,
-        enum dma_transfer_direction dir, unsigned long flags, void *context)
-{
-        struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
-        struct sa11x0_dma_desc *txd;
-        struct scatterlist *sgent;
-        unsigned i, j = sglen;
-        size_t size = 0;
-
-        /* SA11x0 channels can only operate in their native direction */
-        if (dir != (c->ddar & DDAR_RW ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV)) {
-                dev_err(chan->device->dev, "vchan %p: bad DMA direction: DDAR:%08x dir:%u\n",
-                        &c->vc, c->ddar, dir);
-                return NULL;
-        }
-
-        /* Do not allow zero-sized txds */
-        if (sglen == 0)
-                return NULL;
-
-        for_each_sg(sg, sgent, sglen, i) {
-                dma_addr_t addr = sg_dma_address(sgent);
-                unsigned int len = sg_dma_len(sgent);
-
-                if (len > DMA_MAX_SIZE)
-                        j += DIV_ROUND_UP(len, DMA_MAX_SIZE & ~DMA_ALIGN) - 1;
-                if (addr & DMA_ALIGN) {
-                        dev_dbg(chan->device->dev, "vchan %p: bad buffer alignment: %08x\n",
-                                &c->vc, addr);
-                        return NULL;
-                }
-        }
-
-        txd = kzalloc(sizeof(*txd) + j * sizeof(txd->sg[0]), GFP_ATOMIC);
-        if (!txd) {
-                dev_dbg(chan->device->dev, "vchan %p: kzalloc failed\n", &c->vc);
-                return NULL;
-        }
-
-        j = 0;
-        for_each_sg(sg, sgent, sglen, i) {
-                dma_addr_t addr = sg_dma_address(sgent);
-                unsigned len = sg_dma_len(sgent);
-
-                size += len;
-
-                do {
-                        unsigned tlen = len;
-
-                        /*
-                         * Check whether the transfer will fit.  If not, try
-                         * to split the transfer up such that we end up with
-                         * equal chunks - but make sure that we preserve the
-                         * alignment.  This avoids small segments.
-                         */
-                        if (tlen > DMA_MAX_SIZE) {
-                                unsigned mult = DIV_ROUND_UP(tlen,
-                                        DMA_MAX_SIZE & ~DMA_ALIGN);
-
-                                tlen = (tlen / mult) & ~DMA_ALIGN;
-                        }
-
-                        txd->sg[j].addr = addr;
-                        txd->sg[j].len = tlen;
-
-                        addr += tlen;
-                        len -= tlen;
-                        j++;
-                } while (len);
-        }
-
-        txd->ddar = c->ddar;
-        txd->size = size;
-        txd->sglen = j;
-
-        dev_dbg(chan->device->dev, "vchan %p: txd %p: size %u nr %u\n",
-                &c->vc, &txd->vd, txd->size, txd->sglen);
-
-        return vchan_tx_prep(&c->vc, &txd->vd, flags);
-}
-
-static struct dma_async_tx_descriptor *sa11x0_dma_prep_dma_cyclic(
-        struct dma_chan *chan, dma_addr_t addr, size_t size, size_t period,
-        enum dma_transfer_direction dir, unsigned long flags, void *context)
-{
-        struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
-        struct sa11x0_dma_desc *txd;
-        unsigned i, j, k, sglen, sgperiod;
-
-        /* SA11x0 channels can only operate in their native direction */
-        if (dir != (c->ddar & DDAR_RW ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV)) {
-                dev_err(chan->device->dev, "vchan %p: bad DMA direction: DDAR:%08x dir:%u\n",
-                        &c->vc, c->ddar, dir);
-                return NULL;
-        }
-
-        sgperiod = DIV_ROUND_UP(period, DMA_MAX_SIZE & ~DMA_ALIGN);
-        sglen = size * sgperiod / period;
-
-        /* Do not allow zero-sized txds */
-        if (sglen == 0)
-                return NULL;
-
-        txd = kzalloc(sizeof(*txd) + sglen * sizeof(txd->sg[0]), GFP_ATOMIC);
-        if (!txd) {
-                dev_dbg(chan->device->dev, "vchan %p: kzalloc failed\n", &c->vc);
-                return NULL;
-        }
-
-        for (i = k = 0; i < size / period; i++) {
-                size_t tlen, len = period;
-
-                for (j = 0; j < sgperiod; j++, k++) {
-                        tlen = len;
-
-                        if (tlen > DMA_MAX_SIZE) {
-                                unsigned mult = DIV_ROUND_UP(tlen, DMA_MAX_SIZE & ~DMA_ALIGN);
-                                tlen = (tlen / mult) & ~DMA_ALIGN;
-                        }
-
-                        txd->sg[k].addr = addr;
-                        txd->sg[k].len = tlen;
-                        addr += tlen;
-                        len -= tlen;
-                }
-
-                WARN_ON(len != 0);
-        }
-
-        WARN_ON(k != sglen);
-
-        txd->ddar = c->ddar;
-        txd->size = size;
-        txd->sglen = sglen;
-        txd->cyclic = 1;
-        txd->period = sgperiod;
-
-        return vchan_tx_prep(&c->vc, &txd->vd, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-}
-
-static int sa11x0_dma_slave_config(struct sa11x0_dma_chan *c, struct dma_slave_config *cfg)
-{
-        u32 ddar = c->ddar & ((0xf << 4) | DDAR_RW);
-        dma_addr_t addr;
-        enum dma_slave_buswidth width;
-        u32 maxburst;
-
-        if (ddar & DDAR_RW) {
-                addr = cfg->src_addr;
-                width = cfg->src_addr_width;
-                maxburst = cfg->src_maxburst;
-        } else {
-                addr = cfg->dst_addr;
-                width = cfg->dst_addr_width;
-                maxburst = cfg->dst_maxburst;
-        }
-
-        if ((width != DMA_SLAVE_BUSWIDTH_1_BYTE &&
-             width != DMA_SLAVE_BUSWIDTH_2_BYTES) ||
-            (maxburst != 4 && maxburst != 8))
-                return -EINVAL;
-
-        if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
-                ddar |= DDAR_DW;
-        if (maxburst == 8)
-                ddar |= DDAR_BS;
-
-        dev_dbg(c->vc.chan.device->dev, "vchan %p: dma_slave_config addr %x width %u burst %u\n",
-                &c->vc, addr, width, maxburst);
-
-        c->ddar = ddar | (addr & 0xf0000000) | (addr & 0x003ffffc) << 6;
-
-        return 0;
-}
-
-static int sa11x0_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-        unsigned long arg)
-{
-        struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
-        struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
-        struct sa11x0_dma_phy *p;
-        LIST_HEAD(head);
-        unsigned long flags;
-        int ret;
-
-        switch (cmd) {
-        case DMA_SLAVE_CONFIG:
-                return sa11x0_dma_slave_config(c, (struct dma_slave_config *)arg);
-
-        case DMA_TERMINATE_ALL:
-                dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
-                /* Clear the tx descriptor lists */
-                spin_lock_irqsave(&c->vc.lock, flags);
-                vchan_get_all_descriptors(&c->vc, &head);
-
-                p = c->phy;
-                if (p) {
-                        dev_dbg(d->slave.dev, "pchan %u: terminating\n", p->num);
-                        /* vchan is assigned to a pchan - stop the channel */
-                        writel(DCSR_RUN | DCSR_IE |
-                                DCSR_STRTA | DCSR_DONEA |
-                                DCSR_STRTB | DCSR_DONEB,
-                                p->base + DMA_DCSR_C);
-
-                        if (p->txd_load) {
-                                if (p->txd_load != p->txd_done)
-                                        list_add_tail(&p->txd_load->vd.node, &head);
-                                p->txd_load = NULL;
-                        }
-                        if (p->txd_done) {
-                                list_add_tail(&p->txd_done->vd.node, &head);
-                                p->txd_done = NULL;
-                        }
-                        c->phy = NULL;
-                        spin_lock(&d->lock);
-                        p->vchan = NULL;
-                        spin_unlock(&d->lock);
-                        tasklet_schedule(&d->task);
-                }
-                spin_unlock_irqrestore(&c->vc.lock, flags);
-                vchan_dma_desc_free_list(&c->vc, &head);
-                ret = 0;
-                break;
-
-        case DMA_PAUSE:
-                dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
-                spin_lock_irqsave(&c->vc.lock, flags);
-                if (c->status == DMA_IN_PROGRESS) {
-                        c->status = DMA_PAUSED;
-
-                        p = c->phy;
-                        if (p) {
-                                writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C);
-                        } else {
-                                spin_lock(&d->lock);
-                                list_del_init(&c->node);
-                                spin_unlock(&d->lock);
-                        }
-                }
-                spin_unlock_irqrestore(&c->vc.lock, flags);
-                ret = 0;
-                break;
-
-        case DMA_RESUME:
-                dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
-                spin_lock_irqsave(&c->vc.lock, flags);
-                if (c->status == DMA_PAUSED) {
-                        c->status = DMA_IN_PROGRESS;
-
-                        p = c->phy;
-                        if (p) {
-                                writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_S);
-                        } else if (!list_empty(&c->vc.desc_issued)) {
-                                spin_lock(&d->lock);
-                                list_add_tail(&c->node, &d->chan_pending);
-                                spin_unlock(&d->lock);
-                        }
-                }
-                spin_unlock_irqrestore(&c->vc.lock, flags);
-                ret = 0;
-                break;
-
-        default:
-                ret = -ENXIO;
-                break;
-        }
-
-        return ret;
-}
-
-struct sa11x0_dma_channel_desc {
-        u32 ddar;
-        const char *name;
-};
-
-#define CD(d1, d2) { .ddar = DDAR_##d1 | d2, .name = #d1 }
-static const struct sa11x0_dma_channel_desc chan_desc[] = {
-        CD(Ser0UDCTr, 0),
-        CD(Ser0UDCRc, DDAR_RW),
-        CD(Ser1SDLCTr, 0),
-        CD(Ser1SDLCRc, DDAR_RW),
-        CD(Ser1UARTTr, 0),
-        CD(Ser1UARTRc, DDAR_RW),
-        CD(Ser2ICPTr, 0),
-        CD(Ser2ICPRc, DDAR_RW),
-        CD(Ser3UARTTr, 0),
-        CD(Ser3UARTRc, DDAR_RW),
-        CD(Ser4MCP0Tr, 0),
-        CD(Ser4MCP0Rc, DDAR_RW),
-        CD(Ser4MCP1Tr, 0),
-        CD(Ser4MCP1Rc, DDAR_RW),
-        CD(Ser4SSPTr, 0),
-        CD(Ser4SSPRc, DDAR_RW),
-};
-
-static int sa11x0_dma_init_dmadev(struct dma_device *dmadev,
-        struct device *dev)
-{
-        unsigned i;
-
-        dmadev->chancnt = ARRAY_SIZE(chan_desc);
-        INIT_LIST_HEAD(&dmadev->channels);
-        dmadev->dev = dev;
-        dmadev->device_alloc_chan_resources = sa11x0_dma_alloc_chan_resources;
-        dmadev->device_free_chan_resources = sa11x0_dma_free_chan_resources;
-        dmadev->device_control = sa11x0_dma_control;
-        dmadev->device_tx_status = sa11x0_dma_tx_status;
-        dmadev->device_issue_pending = sa11x0_dma_issue_pending;
-
-        for (i = 0; i < dmadev->chancnt; i++) {
-                struct sa11x0_dma_chan *c;
-
-                c = kzalloc(sizeof(*c), GFP_KERNEL);
-                if (!c) {
-                        dev_err(dev, "no memory for channel %u\n", i);
-                        return -ENOMEM;
-                }
-
-                c->status = DMA_IN_PROGRESS;
-                c->ddar = chan_desc[i].ddar;
-                c->name = chan_desc[i].name;
-                INIT_LIST_HEAD(&c->node);
-
-                c->vc.desc_free = sa11x0_dma_free_desc;
-                vchan_init(&c->vc, dmadev);
-        }
-
-        return dma_async_device_register(dmadev);
-}
-
-static int sa11x0_dma_request_irq(struct platform_device *pdev, int nr,
-        void *data)
-{
-        int irq = platform_get_irq(pdev, nr);
-
-        if (irq <= 0)
-                return -ENXIO;
-
-        return request_irq(irq, sa11x0_dma_irq, 0, dev_name(&pdev->dev), data);
-}
-
-static void sa11x0_dma_free_irq(struct platform_device *pdev, int nr,
-        void *data)
-{
-        int irq = platform_get_irq(pdev, nr);
-        if (irq > 0)
-                free_irq(irq, data);
-}
-
-static void sa11x0_dma_free_channels(struct dma_device *dmadev)
-{
-        struct sa11x0_dma_chan *c, *cn;
-
-        list_for_each_entry_safe(c, cn, &dmadev->channels, vc.chan.device_node) {
-                list_del(&c->vc.chan.device_node);
-                tasklet_kill(&c->vc.task);
-                kfree(c);
-        }
-}
-
-static int sa11x0_dma_probe(struct platform_device *pdev)
-{
-        struct sa11x0_dma_dev *d;
-        struct resource *res;
-        unsigned i;
-        int ret;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res)
-                return -ENXIO;
-
-        d = kzalloc(sizeof(*d), GFP_KERNEL);
-        if (!d) {
-                ret = -ENOMEM;
-                goto err_alloc;
-        }
-
-        spin_lock_init(&d->lock);
-        INIT_LIST_HEAD(&d->chan_pending);
-
-        d->base = ioremap(res->start, resource_size(res));
-        if (!d->base) {
-                ret = -ENOMEM;
-                goto err_ioremap;
-        }
-
-        tasklet_init(&d->task, sa11x0_dma_tasklet, (unsigned long)d);
-
-        for (i = 0; i < NR_PHY_CHAN; i++) {
-                struct sa11x0_dma_phy *p = &d->phy[i];
-
-                p->dev = d;
-                p->num = i;
-                p->base = d->base + i * DMA_SIZE;
-                writel_relaxed(DCSR_RUN | DCSR_IE | DCSR_ERROR |
-                        DCSR_DONEA | DCSR_STRTA | DCSR_DONEB | DCSR_STRTB,
-                        p->base + DMA_DCSR_C);
-                writel_relaxed(0, p->base + DMA_DDAR);
-
-                ret = sa11x0_dma_request_irq(pdev, i, p);
-                if (ret) {
-                        while (i) {
-                                i--;
-                                sa11x0_dma_free_irq(pdev, i, &d->phy[i]);
-                        }
-                        goto err_irq;
-                }
-        }
-
-        dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
-        dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
-        d->slave.device_prep_slave_sg = sa11x0_dma_prep_slave_sg;
-        d->slave.device_prep_dma_cyclic = sa11x0_dma_prep_dma_cyclic;
-        ret = sa11x0_dma_init_dmadev(&d->slave, &pdev->dev);
-        if (ret) {
-                dev_warn(d->slave.dev, "failed to register slave async device: %d\n",
-                        ret);
-                goto err_slave_reg;
-        }
-
-        platform_set_drvdata(pdev, d);
-        return 0;
-
- err_slave_reg:
-        sa11x0_dma_free_channels(&d->slave);
-        for (i = 0; i < NR_PHY_CHAN; i++)
-                sa11x0_dma_free_irq(pdev, i, &d->phy[i]);
- err_irq:
-        tasklet_kill(&d->task);
-        iounmap(d->base);
- err_ioremap:
-        kfree(d);
- err_alloc:
-        return ret;
-}
-
-static int sa11x0_dma_remove(struct platform_device *pdev)
-{
-        struct sa11x0_dma_dev *d = platform_get_drvdata(pdev);
-        unsigned pch;
-
-        dma_async_device_unregister(&d->slave);
-
-        sa11x0_dma_free_channels(&d->slave);
-        for (pch = 0; pch < NR_PHY_CHAN; pch++)
-                sa11x0_dma_free_irq(pdev, pch, &d->phy[pch]);
-        tasklet_kill(&d->task);
-        iounmap(d->base);
-        kfree(d);
-
-        return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int sa11x0_dma_suspend(struct device *dev)
-{
-        struct sa11x0_dma_dev *d = dev_get_drvdata(dev);
-        unsigned pch;
-
-        for (pch = 0; pch < NR_PHY_CHAN; pch++) {
-                struct sa11x0_dma_phy *p = &d->phy[pch];
-                u32 dcsr, saved_dcsr;
-
-                dcsr = saved_dcsr = readl_relaxed(p->base + DMA_DCSR_R);
-                if (dcsr & DCSR_RUN) {
-                        writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C);
-                        dcsr = readl_relaxed(p->base + DMA_DCSR_R);
-                }
-
-                saved_dcsr &= DCSR_RUN | DCSR_IE;
-                if (dcsr & DCSR_BIU) {
-                        p->dbs[0] = readl_relaxed(p->base + DMA_DBSB);
-                        p->dbt[0] = readl_relaxed(p->base + DMA_DBTB);
-                        p->dbs[1] = readl_relaxed(p->base + DMA_DBSA);
-                        p->dbt[1] = readl_relaxed(p->base + DMA_DBTA);
-                        saved_dcsr |= (dcsr & DCSR_STRTA ? DCSR_STRTB : 0) |
-                                      (dcsr & DCSR_STRTB ? DCSR_STRTA : 0);
-                } else {
-                        p->dbs[0] = readl_relaxed(p->base + DMA_DBSA);
-                        p->dbt[0] = readl_relaxed(p->base + DMA_DBTA);
-                        p->dbs[1] = readl_relaxed(p->base + DMA_DBSB);
-                        p->dbt[1] = readl_relaxed(p->base + DMA_DBTB);
-                        saved_dcsr |= dcsr & (DCSR_STRTA | DCSR_STRTB);
-                }
-                p->dcsr = saved_dcsr;
-
-                writel(DCSR_STRTA | DCSR_STRTB, p->base + DMA_DCSR_C);
-        }
-
-        return 0;
-}
-
-static int sa11x0_dma_resume(struct device *dev)
-{
-        struct sa11x0_dma_dev *d = dev_get_drvdata(dev);
-        unsigned pch;
-
-        for (pch = 0; pch < NR_PHY_CHAN; pch++) {
-                struct sa11x0_dma_phy *p = &d->phy[pch];
-                struct sa11x0_dma_desc *txd = NULL;
-                u32 dcsr = readl_relaxed(p->base + DMA_DCSR_R);
-
-                WARN_ON(dcsr & (DCSR_BIU | DCSR_STRTA | DCSR_STRTB | DCSR_RUN));
-
-                if (p->txd_done)
-                        txd = p->txd_done;
-                else if (p->txd_load)
-                        txd = p->txd_load;
-
-                if (!txd)
-                        continue;
-
-                writel_relaxed(txd->ddar, p->base + DMA_DDAR);
-
-                writel_relaxed(p->dbs[0], p->base + DMA_DBSA);
-                writel_relaxed(p->dbt[0], p->base + DMA_DBTA);
-                writel_relaxed(p->dbs[1], p->base + DMA_DBSB);
-                writel_relaxed(p->dbt[1], p->base + DMA_DBTB);
-                writel_relaxed(p->dcsr, p->base + DMA_DCSR_S);
-        }
-
-        return 0;
-}
-#endif
-
-static const struct dev_pm_ops sa11x0_dma_pm_ops = {
-        .suspend_noirq = sa11x0_dma_suspend,
-        .resume_noirq = sa11x0_dma_resume,
-        .freeze_noirq = sa11x0_dma_suspend,
-        .thaw_noirq = sa11x0_dma_resume,
-        .poweroff_noirq = sa11x0_dma_suspend,
-        .restore_noirq = sa11x0_dma_resume,
-};
-
-static struct platform_driver sa11x0_dma_driver = {
-        .driver = {
-                .name   = "sa11x0-dma",
-                .owner  = THIS_MODULE,
-                .pm     = &sa11x0_dma_pm_ops,
-        },
-        .probe          = sa11x0_dma_probe,
-        .remove         = sa11x0_dma_remove,
-};
-
-bool sa11x0_dma_filter_fn(struct dma_chan *chan, void *param)
-{
-        if (chan->device->dev->driver == &sa11x0_dma_driver.driver) {
-                struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
-                const char *p = param;
-
-                return !strcmp(c->name, p);
-        }
-        return false;
-}
-EXPORT_SYMBOL(sa11x0_dma_filter_fn);
-
-static int __init sa11x0_dma_init(void)
-{
-        return platform_driver_register(&sa11x0_dma_driver);
-}
-subsys_initcall(sa11x0_dma_init);
-
-static void __exit sa11x0_dma_exit(void)
-{
-        platform_driver_unregister(&sa11x0_dma_driver);
-}
-module_exit(sa11x0_dma_exit);
-
-MODULE_AUTHOR("Russell King");
-MODULE_DESCRIPTION("SA-11x0 DMA driver");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:sa11x0-dma");
diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile
deleted file mode 100644
index 54ae9572b0a..00000000000
--- a/drivers/dma/sh/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-$(CONFIG_SH_DMAE) += shdma-base.o
-obj-$(CONFIG_SH_DMAE) += shdma.o
diff --git a/drivers/dma/sh/shdma-base.c b/drivers/dma/sh/shdma-base.c
deleted file mode 100644
index f4cd946d259..00000000000
--- a/drivers/dma/sh/shdma-base.c
+++ /dev/null
@@ -1,943 +0,0 @@
-/*
- * Dmaengine driver base library for DMA controllers, found on SH-based SoCs
- *
- * extracted from shdma.c
- *
- * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
- * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
- *
- * This is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- */
-
-#include <linux/delay.h>
-#include <linux/shdma-base.h>
-#include <linux/dmaengine.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/pm_runtime.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-#include "../dmaengine.h"
-
-/* DMA descriptor control */
-enum shdma_desc_status {
-        DESC_IDLE,
-        DESC_PREPARED,
-        DESC_SUBMITTED,
-        DESC_COMPLETED, /* completed, have to call callback */
-        DESC_WAITING,   /* callback called, waiting for ack / re-submit */
-};
-
-#define NR_DESCS_PER_CHANNEL 32
-
-#define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
-#define to_shdma_dev(d) container_of(d, struct shdma_dev, dma_dev)
-
-/*
- * For slave DMA we assume, that there is a finite number of DMA slaves in the
- * system, and that each such slave can only use a finite number of channels.
- * We use slave channel IDs to make sure, that no such slave channel ID is
- * allocated more than once.
- */
-static unsigned int slave_num = 256;
-module_param(slave_num, uint, 0444);
-
-/* A bitmask with slave_num bits */
-static unsigned long *shdma_slave_used;
-
-/* Called under spin_lock_irq(&schan->chan_lock") */
-static void shdma_chan_xfer_ld_queue(struct shdma_chan *schan)
-{
-        struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
-        const struct shdma_ops *ops = sdev->ops;
-        struct shdma_desc *sdesc;
-
-        /* DMA work check */
-        if (ops->channel_busy(schan))
-                return;
-
-        /* Find the first not transferred descriptor */
-        list_for_each_entry(sdesc, &schan->ld_queue, node)
-                if (sdesc->mark == DESC_SUBMITTED) {
-                        ops->start_xfer(schan, sdesc);
-                        break;
-                }
-}
-
-static dma_cookie_t shdma_tx_submit(struct dma_async_tx_descriptor *tx)
-{
-        struct shdma_desc *chunk, *c, *desc =
-                container_of(tx, struct shdma_desc, async_tx),
-                *last = desc;
-        struct shdma_chan *schan = to_shdma_chan(tx->chan);
-        dma_async_tx_callback callback = tx->callback;
-        dma_cookie_t cookie;
-        bool power_up;
-
-        spin_lock_irq(&schan->chan_lock);
-
-        power_up = list_empty(&schan->ld_queue);
-
-        cookie = dma_cookie_assign(tx);
-
-        /* Mark all chunks of this descriptor as submitted, move to the queue */
-        list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
-                /*
-                 * All chunks are on the global ld_free, so, we have to find
-                 * the end of the chain ourselves
-                 */
-                if (chunk != desc && (chunk->mark == DESC_IDLE ||
-                                      chunk->async_tx.cookie > 0 ||
-                                      chunk->async_tx.cookie == -EBUSY ||
-                                      &chunk->node == &schan->ld_free))
-                        break;
-                chunk->mark = DESC_SUBMITTED;
-                /* Callback goes to the last chunk */
-                chunk->async_tx.callback = NULL;
-                chunk->cookie = cookie;
-                list_move_tail(&chunk->node, &schan->ld_queue);
-                last = chunk;
-
-                dev_dbg(schan->dev, "submit #%d@%p on %d\n",
-                        tx->cookie, &last->async_tx, schan->id);
-        }
-
-        last->async_tx.callback = callback;
-        last->async_tx.callback_param = tx->callback_param;
-
-        if (power_up) {
-                int ret;
-                schan->pm_state = SHDMA_PM_BUSY;
-
-                ret = pm_runtime_get(schan->dev);
-
-                spin_unlock_irq(&schan->chan_lock);
-                if (ret < 0)
-                        dev_err(schan->dev, "%s(): GET = %d\n", __func__, ret);
-
-                pm_runtime_barrier(schan->dev);
-
-                spin_lock_irq(&schan->chan_lock);
-
-                /* Have we been reset, while waiting? */
-                if (schan->pm_state != SHDMA_PM_ESTABLISHED) {
-                        struct shdma_dev *sdev =
-                                to_shdma_dev(schan->dma_chan.device);
-                        const struct shdma_ops *ops = sdev->ops;
-                        dev_dbg(schan->dev, "Bring up channel %d\n",
-                                schan->id);
-                        /*
-                         * TODO: .xfer_setup() might fail on some platforms.
-                         * Make it int then, on error remove chunks from the
-                         * queue again
-                         */
-                        ops->setup_xfer(schan, schan->slave_id);
-
-                        if (schan->pm_state == SHDMA_PM_PENDING)
-                                shdma_chan_xfer_ld_queue(schan);
-                        schan->pm_state = SHDMA_PM_ESTABLISHED;
-                }
-        } else {
-                /*
-                 * Tell .device_issue_pending() not to run the queue, interrupts
-                 * will do it anyway
-                 */
-                schan->pm_state = SHDMA_PM_PENDING;
-        }
-
-        spin_unlock_irq(&schan->chan_lock);
-
-        return cookie;
-}
-
-/* Called with desc_lock held */
-static struct shdma_desc *shdma_get_desc(struct shdma_chan *schan)
-{
-        struct shdma_desc *sdesc;
-
-        list_for_each_entry(sdesc, &schan->ld_free, node)
-                if (sdesc->mark != DESC_PREPARED) {
-                        BUG_ON(sdesc->mark != DESC_IDLE);
-                        list_del(&sdesc->node);
-                        return sdesc;
-                }
-
-        return NULL;
-}
-
-static int shdma_setup_slave(struct shdma_chan *schan, int slave_id)
-{
-        struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
-        const struct shdma_ops *ops = sdev->ops;
-        int ret;
-
-        if (slave_id < 0 || slave_id >= slave_num)
-                return -EINVAL;
-
-        if (test_and_set_bit(slave_id, shdma_slave_used))
-                return -EBUSY;
-
-        ret = ops->set_slave(schan, slave_id, false);
-        if (ret < 0) {
-                clear_bit(slave_id, shdma_slave_used);
-                return ret;
-        }
-
-        schan->slave_id = slave_id;
-
-        return 0;
-}
-
-/*
- * This is the standard shdma filter function to be used as a replacement to the
- * "old" method, using the .private pointer. If for some reason you allocate a
- * channel without slave data, use something like ERR_PTR(-EINVAL) as a filter
- * parameter. If this filter is used, the slave driver, after calling
- * dma_request_channel(), will also have to call dmaengine_slave_config() with
- * .slave_id, .direction, and either .src_addr or .dst_addr set.
- * NOTE: this filter doesn't support multiple DMAC drivers with the DMA_SLAVE
- * capability! If this becomes a requirement, hardware glue drivers, using this
- * services would have to provide their own filters, which first would check
- * the device driver, similar to how other DMAC drivers, e.g., sa11x0-dma.c, do
- * this, and only then, in case of a match, call this common filter.
- */
-bool shdma_chan_filter(struct dma_chan *chan, void *arg)
-{
-        struct shdma_chan *schan = to_shdma_chan(chan);
-        struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
-        const struct shdma_ops *ops = sdev->ops;
-        int slave_id = (int)arg;
-        int ret;
-
-        if (slave_id < 0)
-                /* No slave requested - arbitrary channel */
-                return true;
-
-        if (slave_id >= slave_num)
-                return false;
-
-        ret = ops->set_slave(schan, slave_id, true);
-        if (ret < 0)
-                return false;
-
-        return true;
-}
-EXPORT_SYMBOL(shdma_chan_filter);
-
-static int shdma_alloc_chan_resources(struct dma_chan *chan)
-{
-        struct shdma_chan *schan = to_shdma_chan(chan);
-        struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
-        const struct shdma_ops *ops = sdev->ops;
-        struct shdma_desc *desc;
-        struct shdma_slave *slave = chan->private;
-        int ret, i;
-
-        /*
-         * This relies on the guarantee from dmaengine that alloc_chan_resources
-         * never runs concurrently with itself or free_chan_resources.
-         */
-        if (slave) {
-                /* Legacy mode: .private is set in filter */
-                ret = shdma_setup_slave(schan, slave->slave_id);
-                if (ret < 0)
-                        goto esetslave;
-        } else {
-                schan->slave_id = -EINVAL;
-        }
-
-        schan->desc = kcalloc(NR_DESCS_PER_CHANNEL,
-                              sdev->desc_size, GFP_KERNEL);
-        if (!schan->desc) {
-                ret = -ENOMEM;
-                goto edescalloc;
-        }
-        schan->desc_num = NR_DESCS_PER_CHANNEL;
-
-        for (i = 0; i < NR_DESCS_PER_CHANNEL; i++) {
-                desc = ops->embedded_desc(schan->desc, i);
-                dma_async_tx_descriptor_init(&desc->async_tx,
-                                             &schan->dma_chan);
-                desc->async_tx.tx_submit = shdma_tx_submit;
-                desc->mark = DESC_IDLE;
-
-                list_add(&desc->node, &schan->ld_free);
-        }
-
-        return NR_DESCS_PER_CHANNEL;
-
-edescalloc:
-        if (slave)
-esetslave:
-                clear_bit(slave->slave_id, shdma_slave_used);
-        chan->private = NULL;
-        return ret;
-}
-
-static dma_async_tx_callback __ld_cleanup(struct shdma_chan *schan, bool all)
-{
-        struct shdma_desc *desc, *_desc;
-        /* Is the "exposed" head of a chain acked? */
-        bool head_acked = false;
-        dma_cookie_t cookie = 0;
-        dma_async_tx_callback callback = NULL;
-        void *param = NULL;
-        unsigned long flags;
-
-        spin_lock_irqsave(&schan->chan_lock, flags);
-        list_for_each_entry_safe(desc, _desc, &schan->ld_queue, node) {
-                struct dma_async_tx_descriptor *tx = &desc->async_tx;
-
-                BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
-                BUG_ON(desc->mark != DESC_SUBMITTED &&
-                       desc->mark != DESC_COMPLETED &&
-                       desc->mark != DESC_WAITING);
-
-                /*
-                 * queue is ordered, and we use this loop to (1) clean up all
-                 * completed descriptors, and to (2) update descriptor flags of
-                 * any chunks in a (partially) completed chain
-                 */
-                if (!all && desc->mark == DESC_SUBMITTED &&
-                    desc->cookie != cookie)
-                        break;
-
-                if (tx->cookie > 0)
-                        cookie = tx->cookie;
-
-                if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
-                        if (schan->dma_chan.completed_cookie != desc->cookie - 1)
-                                dev_dbg(schan->dev,
-                                        "Completing cookie %d, expected %d\n",
-                                        desc->cookie,
-                                        schan->dma_chan.completed_cookie + 1);
-                        schan->dma_chan.completed_cookie = desc->cookie;
-                }
-
-                /* Call callback on the last chunk */
-                if (desc->mark == DESC_COMPLETED && tx->callback) {
-                        desc->mark = DESC_WAITING;
-                        callback = tx->callback;
-                        param = tx->callback_param;
-                        dev_dbg(schan->dev, "descriptor #%d@%p on %d callback\n",
-                                tx->cookie, tx, schan->id);
-                        BUG_ON(desc->chunks != 1);
-                        break;
-                }
-
-                if (tx->cookie > 0 || tx->cookie == -EBUSY) {
-                        if (desc->mark == DESC_COMPLETED) {
-                                BUG_ON(tx->cookie < 0);
-                                desc->mark = DESC_WAITING;
-                        }
-                        head_acked = async_tx_test_ack(tx);
-                } else {
-                        switch (desc->mark) {
-                        case DESC_COMPLETED:
-                                desc->mark = DESC_WAITING;
-                                /* Fall through */
-                        case DESC_WAITING:
-                                if (head_acked)
-                                        async_tx_ack(&desc->async_tx);
-                        }
-                }
-
-                dev_dbg(schan->dev, "descriptor %p #%d completed.\n",
-                        tx, tx->cookie);
-
-                if (((desc->mark == DESC_COMPLETED ||
-                      desc->mark == DESC_WAITING) &&
-                     async_tx_test_ack(&desc->async_tx)) || all) {
-                        /* Remove from ld_queue list */
-                        desc->mark = DESC_IDLE;
-
-                        list_move(&desc->node, &schan->ld_free);
-
-                        if (list_empty(&schan->ld_queue)) {
-                                dev_dbg(schan->dev, "Bring down channel %d\n", schan->id);
-                                pm_runtime_put(schan->dev);
-                                schan->pm_state = SHDMA_PM_ESTABLISHED;
-                        }
-                }
-        }
-
-        if (all && !callback)
-                /*
-                 * Terminating and the loop completed normally: forgive
-                 * uncompleted cookies
-                 */
-                schan->dma_chan.completed_cookie = schan->dma_chan.cookie;
-
-        spin_unlock_irqrestore(&schan->chan_lock, flags);
-
-        if (callback)
-                callback(param);
-
-        return callback;
-}
-
-/*
- * shdma_chan_ld_cleanup - Clean up link descriptors
- *
- * Clean up the ld_queue of DMA channel.
- */
-static void shdma_chan_ld_cleanup(struct shdma_chan *schan, bool all)
-{
-        while (__ld_cleanup(schan, all))
-                ;
-}
-
-/*
- * shdma_free_chan_resources - Free all resources of the channel.
- */
-static void shdma_free_chan_resources(struct dma_chan *chan)
-{
-        struct shdma_chan *schan = to_shdma_chan(chan);
-        struct shdma_dev *sdev = to_shdma_dev(chan->device);
-        const struct shdma_ops *ops = sdev->ops;
-        LIST_HEAD(list);
-
-        /* Protect against ISR */
-        spin_lock_irq(&schan->chan_lock);
-        ops->halt_channel(schan);
-        spin_unlock_irq(&schan->chan_lock);
-
-        /* Now no new interrupts will occur */
-
-        /* Prepared and not submitted descriptors can still be on the queue */
-        if (!list_empty(&schan->ld_queue))
-                shdma_chan_ld_cleanup(schan, true);
-
-        if (schan->slave_id >= 0) {
-                /* The caller is holding dma_list_mutex */
-                clear_bit(schan->slave_id, shdma_slave_used);
-                chan->private = NULL;
-        }
-
-        spin_lock_irq(&schan->chan_lock);
-
-        list_splice_init(&schan->ld_free, &list);
-        schan->desc_num = 0;
-
-        spin_unlock_irq(&schan->chan_lock);
-
-        kfree(schan->desc);
-}
-
-/**
- * shdma_add_desc - get, set up and return one transfer descriptor
- * @schan:      DMA channel
- * @flags:      DMA transfer flags
- * @dst:        destination DMA address, incremented when direction equals
- *              DMA_DEV_TO_MEM or DMA_MEM_TO_MEM
- * @src:        source DMA address, incremented when direction equals
- *              DMA_MEM_TO_DEV or DMA_MEM_TO_MEM
- * @len:        DMA transfer length
- * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
- * @direction:  needed for slave DMA to decide which address to keep constant,
- *              equals DMA_MEM_TO_MEM for MEMCPY
- * Returns 0 or an error
- * Locks: called with desc_lock held
- */
-static struct shdma_desc *shdma_add_desc(struct shdma_chan *schan,
-        unsigned long flags, dma_addr_t *dst, dma_addr_t *src, size_t *len,
-        struct shdma_desc **first, enum dma_transfer_direction direction)
-{
-        struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
-        const struct shdma_ops *ops = sdev->ops;
-        struct shdma_desc *new;
-        size_t copy_size = *len;
-
-        if (!copy_size)
-                return NULL;
-
-        /* Allocate the link descriptor from the free list */
-        new = shdma_get_desc(schan);
-        if (!new) {
-                dev_err(schan->dev, "No free link descriptor available\n");
-                return NULL;
-        }
-
-        ops->desc_setup(schan, new, *src, *dst, &copy_size);
-
-        if (!*first) {
-                /* First desc */
-                new->async_tx.cookie = -EBUSY;
-                *first = new;
-        } else {
-                /* Other desc - invisible to the user */
-                new->async_tx.cookie = -EINVAL;
-        }
-
-        dev_dbg(schan->dev,
-                "chaining (%u/%u)@%x -> %x with %p, cookie %d\n",
-                copy_size, *len, *src, *dst, &new->async_tx,
-                new->async_tx.cookie);
-
-        new->mark = DESC_PREPARED;
-        new->async_tx.flags = flags;
-        new->direction = direction;
-        new->partial = 0;
-
-        *len -= copy_size;
-        if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV)
-                *src += copy_size;
-        if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM)
-                *dst += copy_size;
-
-        return new;
-}
-
-/*
- * shdma_prep_sg - prepare transfer descriptors from an SG list
- *
- * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
- * converted to scatter-gather to guarantee consistent locking and a correct
- * list manipulation. For slave DMA direction carries the usual meaning, and,
- * logically, the SG list is RAM and the addr variable contains slave address,
- * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
- * and the SG list contains only one element and points at the source buffer.
- */
-static struct dma_async_tx_descriptor *shdma_prep_sg(struct shdma_chan *schan,
-        struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
-        enum dma_transfer_direction direction, unsigned long flags)
-{
-        struct scatterlist *sg;
-        struct shdma_desc *first = NULL, *new = NULL /* compiler... */;
-        LIST_HEAD(tx_list);
-        int chunks = 0;
-        unsigned long irq_flags;
-        int i;
-
-        for_each_sg(sgl, sg, sg_len, i)
-                chunks += DIV_ROUND_UP(sg_dma_len(sg), schan->max_xfer_len);
-
-        /* Have to lock the whole loop to protect against concurrent release */
-        spin_lock_irqsave(&schan->chan_lock, irq_flags);
-
-        /*
-         * Chaining:
-         * first descriptor is what user is dealing with in all API calls, its
-         *      cookie is at first set to -EBUSY, at tx-submit to a positive
-         *      number
-         * if more than one chunk is needed further chunks have cookie = -EINVAL
-         * the last chunk, if not equal to the first, has cookie = -ENOSPC
-         * all chunks are linked onto the tx_list head with their .node heads
-         *      only during this function, then they are immediately spliced
-         *      back onto the free list in form of a chain
-         */
-        for_each_sg(sgl, sg, sg_len, i) {
-                dma_addr_t sg_addr = sg_dma_address(sg);
-                size_t len = sg_dma_len(sg);
-
-                if (!len)
-                        goto err_get_desc;
-
-                do {
-                        dev_dbg(schan->dev, "Add SG #%d@%p[%d], dma %llx\n",
-                                i, sg, len, (unsigned long long)sg_addr);
-
-                        if (direction == DMA_DEV_TO_MEM)
-                                new = shdma_add_desc(schan, flags,
-                                                &sg_addr, addr, &len, &first,
-                                                direction);
-                        else
-                                new = shdma_add_desc(schan, flags,
-                                                addr, &sg_addr, &len, &first,
-                                                direction);
-                        if (!new)
-                                goto err_get_desc;
-
-                        new->chunks = chunks--;
-                        list_add_tail(&new->node, &tx_list);
-                } while (len);
-        }
-
-        if (new != first)
-                new->async_tx.cookie = -ENOSPC;
-
-        /* Put them back on the free list, so, they don't get lost */
-        list_splice_tail(&tx_list, &schan->ld_free);
-
-        spin_unlock_irqrestore(&schan->chan_lock, irq_flags);
-
-        return &first->async_tx;
-
-err_get_desc:
-        list_for_each_entry(new, &tx_list, node)
-                new->mark = DESC_IDLE;
-        list_splice(&tx_list, &schan->ld_free);
-
-        spin_unlock_irqrestore(&schan->chan_lock, irq_flags);
-
-        return NULL;
-}
-
-static struct dma_async_tx_descriptor *shdma_prep_memcpy(
-        struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
-        size_t len, unsigned long flags)
-{
-        struct shdma_chan *schan = to_shdma_chan(chan);
-        struct scatterlist sg;
-
-        if (!chan || !len)
-                return NULL;
-
-        BUG_ON(!schan->desc_num);
-
-        sg_init_table(&sg, 1);
-        sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
-                    offset_in_page(dma_src));
-        sg_dma_address(&sg) = dma_src;
-        sg_dma_len(&sg) = len;
-
-        return shdma_prep_sg(schan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM, flags);
-}
-
-static struct dma_async_tx_descriptor *shdma_prep_slave_sg(
-        struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
-        enum dma_transfer_direction direction, unsigned long flags, void *context)
-{
-        struct shdma_chan *schan = to_shdma_chan(chan);
-        struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
-        const struct shdma_ops *ops = sdev->ops;
-        int slave_id = schan->slave_id;
-        dma_addr_t slave_addr;
-
-        if (!chan)
-                return NULL;
-
-        BUG_ON(!schan->desc_num);
-
-        /* Someone calling slave DMA on a generic channel? */
-        if (slave_id < 0 || !sg_len) {
-                dev_warn(schan->dev, "%s: bad parameter: len=%d, id=%d\n",
-                         __func__, sg_len, slave_id);
-                return NULL;
-        }
-
-        slave_addr = ops->slave_addr(schan);
-
-        return shdma_prep_sg(schan, sgl, sg_len, &slave_addr,
-                              direction, flags);
-}
-
-static int shdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-                          unsigned long arg)
-{
-        struct shdma_chan *schan = to_shdma_chan(chan);
-        struct shdma_dev *sdev = to_shdma_dev(chan->device);
-        const struct shdma_ops *ops = sdev->ops;
-        struct dma_slave_config *config;
-        unsigned long flags;
-        int ret;
-
-        if (!chan)
-                return -EINVAL;
-
-        switch (cmd) {
-        case DMA_TERMINATE_ALL:
-                spin_lock_irqsave(&schan->chan_lock, flags);
-                ops->halt_channel(schan);
-
-                if (ops->get_partial && !list_empty(&schan->ld_queue)) {
-                        /* Record partial transfer */
-                        struct shdma_desc *desc = list_first_entry(&schan->ld_queue,
-                                                struct shdma_desc, node);
-                        desc->partial = ops->get_partial(schan, desc);
-                }
-
-                spin_unlock_irqrestore(&schan->chan_lock, flags);
-
-                shdma_chan_ld_cleanup(schan, true);
-                break;
-        case DMA_SLAVE_CONFIG:
-                /*
-                 * So far only .slave_id is used, but the slave drivers are
-                 * encouraged to also set a transfer direction and an address.
-                 */
-                if (!arg)
-                        return -EINVAL;
-                /*
-                 * We could lock this, but you shouldn't be configuring the
-                 * channel, while using it...
-                 */
-                config = (struct dma_slave_config *)arg;
-                ret = shdma_setup_slave(schan, config->slave_id);
-                if (ret < 0)
-                        return ret;
-                break;
-        default:
-                return -ENXIO;
-        }
-
-        return 0;
-}
-
-static void shdma_issue_pending(struct dma_chan *chan)
-{
-        struct shdma_chan *schan = to_shdma_chan(chan);
-
-        spin_lock_irq(&schan->chan_lock);
-        if (schan->pm_state == SHDMA_PM_ESTABLISHED)
-                shdma_chan_xfer_ld_queue(schan);
-        else
-                schan->pm_state = SHDMA_PM_PENDING;
-        spin_unlock_irq(&schan->chan_lock);
-}
-
-static enum dma_status shdma_tx_status(struct dma_chan *chan,
-                                        dma_cookie_t cookie,
-                                        struct dma_tx_state *txstate)
-{
-        struct shdma_chan *schan = to_shdma_chan(chan);
-        enum dma_status status;
-        unsigned long flags;
-
-        shdma_chan_ld_cleanup(schan, false);
-
-        spin_lock_irqsave(&schan->chan_lock, flags);
-
-        status = dma_cookie_status(chan, cookie, txstate);
-
-        /*
-         * If we don't find cookie on the queue, it has been aborted and we have
-         * to report error
-         */
-        if (status != DMA_SUCCESS) {
-                struct shdma_desc *sdesc;
-                status = DMA_ERROR;
-                list_for_each_entry(sdesc, &schan->ld_queue, node)
-                        if (sdesc->cookie == cookie) {
-                                status = DMA_IN_PROGRESS;
-                                break;
-                        }
-        }
-
-        spin_unlock_irqrestore(&schan->chan_lock, flags);
-
-        return status;
-}
-
-/* Called from error IRQ or NMI */
-bool shdma_reset(struct shdma_dev *sdev)
-{
-        const struct shdma_ops *ops = sdev->ops;
-        struct shdma_chan *schan;
-        unsigned int handled = 0;
-        int i;
-
-        /* Reset all channels */
-        shdma_for_each_chan(schan, sdev, i) {
-                struct shdma_desc *sdesc;
-                LIST_HEAD(dl);
-
-                if (!schan)
-                        continue;
-
-                spin_lock(&schan->chan_lock);
-
-                /* Stop the channel */
-                ops->halt_channel(schan);
-
-                list_splice_init(&schan->ld_queue, &dl);
-
-                if (!list_empty(&dl)) {
-                        dev_dbg(schan->dev, "Bring down channel %d\n", schan->id);
-                        pm_runtime_put(schan->dev);
-                }
-                schan->pm_state = SHDMA_PM_ESTABLISHED;
-
-                spin_unlock(&schan->chan_lock);
-
-                /* Complete all  */
-                list_for_each_entry(sdesc, &dl, node) {
-                        struct dma_async_tx_descriptor *tx = &sdesc->async_tx;
-                        sdesc->mark = DESC_IDLE;
-                        if (tx->callback)
-                                tx->callback(tx->callback_param);
-                }
-
-                spin_lock(&schan->chan_lock);
-                list_splice(&dl, &schan->ld_free);
-                spin_unlock(&schan->chan_lock);
-
-                handled++;
-        }
-
-        return !!handled;
-}
-EXPORT_SYMBOL(shdma_reset);
-
-static irqreturn_t chan_irq(int irq, void *dev)
-{
-        struct shdma_chan *schan = dev;
-        const struct shdma_ops *ops =
-                to_shdma_dev(schan->dma_chan.device)->ops;
-        irqreturn_t ret;
-
-        spin_lock(&schan->chan_lock);
-
-        ret = ops->chan_irq(schan, irq) ? IRQ_WAKE_THREAD : IRQ_NONE;
-
-        spin_unlock(&schan->chan_lock);
-
-        return ret;
-}
-
-static irqreturn_t chan_irqt(int irq, void *dev)
-{
-        struct shdma_chan *schan = dev;
-        const struct shdma_ops *ops =
-                to_shdma_dev(schan->dma_chan.device)->ops;
-        struct shdma_desc *sdesc;
-
-        spin_lock_irq(&schan->chan_lock);
-        list_for_each_entry(sdesc, &schan->ld_queue, node) {
-                if (sdesc->mark == DESC_SUBMITTED &&
-                    ops->desc_completed(schan, sdesc)) {
-                        dev_dbg(schan->dev, "done #%d@%p\n",
-                                sdesc->async_tx.cookie, &sdesc->async_tx);
-                        sdesc->mark = DESC_COMPLETED;
-                        break;
-                }
-        }
-        /* Next desc */
-        shdma_chan_xfer_ld_queue(schan);
-        spin_unlock_irq(&schan->chan_lock);
-
-        shdma_chan_ld_cleanup(schan, false);
-
-        return IRQ_HANDLED;
-}
-
-int shdma_request_irq(struct shdma_chan *schan, int irq,
-                           unsigned long flags, const char *name)
-{
-        int ret = request_threaded_irq(irq, chan_irq, chan_irqt,
-                                       flags, name, schan);
-
-        schan->irq = ret < 0 ? ret : irq;
-
-        return ret;
-}
-EXPORT_SYMBOL(shdma_request_irq);
-
-void shdma_free_irq(struct shdma_chan *schan)
-{
-        if (schan->irq >= 0)
-                free_irq(schan->irq, schan);
-}
-EXPORT_SYMBOL(shdma_free_irq);
-
-void shdma_chan_probe(struct shdma_dev *sdev,
-                           struct shdma_chan *schan, int id)
-{
-        schan->pm_state = SHDMA_PM_ESTABLISHED;
-
-        /* reference struct dma_device */
-        schan->dma_chan.device = &sdev->dma_dev;
-        dma_cookie_init(&schan->dma_chan);
-
-        schan->dev = sdev->dma_dev.dev;
-        schan->id = id;
-
-        if (!schan->max_xfer_len)
-                schan->max_xfer_len = PAGE_SIZE;
-
-        spin_lock_init(&schan->chan_lock);
-
-        /* Init descripter manage list */
-        INIT_LIST_HEAD(&schan->ld_queue);
-        INIT_LIST_HEAD(&schan->ld_free);
-
-        /* Add the channel to DMA device channel list */
-        list_add_tail(&schan->dma_chan.device_node,
-                        &sdev->dma_dev.channels);
-        sdev->schan[sdev->dma_dev.chancnt++] = schan;
-}
-EXPORT_SYMBOL(shdma_chan_probe);
-
-void shdma_chan_remove(struct shdma_chan *schan)
-{
-        list_del(&schan->dma_chan.device_node);
-}
-EXPORT_SYMBOL(shdma_chan_remove);
-
-int shdma_init(struct device *dev, struct shdma_dev *sdev,
-                    int chan_num)
-{
-        struct dma_device *dma_dev = &sdev->dma_dev;
-
-        /*
-         * Require all call-backs for now, they can trivially be made optional
-         * later as required
-         */
-        if (!sdev->ops ||
-            !sdev->desc_size ||
-            !sdev->ops->embedded_desc ||
-            !sdev->ops->start_xfer ||
-            !sdev->ops->setup_xfer ||
-            !sdev->ops->set_slave ||
-            !sdev->ops->desc_setup ||
-            !sdev->ops->slave_addr ||
-            !sdev->ops->channel_busy ||
-            !sdev->ops->halt_channel ||
-            !sdev->ops->desc_completed)
-                return -EINVAL;
-
-        sdev->schan = kcalloc(chan_num, sizeof(*sdev->schan), GFP_KERNEL);
-        if (!sdev->schan)
-                return -ENOMEM;
-
-        INIT_LIST_HEAD(&dma_dev->channels);
-
-        /* Common and MEMCPY operations */
-        dma_dev->device_alloc_chan_resources
-                = shdma_alloc_chan_resources;
-        dma_dev->device_free_chan_resources = shdma_free_chan_resources;
-        dma_dev->device_prep_dma_memcpy = shdma_prep_memcpy;
-        dma_dev->device_tx_status = shdma_tx_status;
-        dma_dev->device_issue_pending = shdma_issue_pending;
-
-        /* Compulsory for DMA_SLAVE fields */
-        dma_dev->device_prep_slave_sg = shdma_prep_slave_sg;
-        dma_dev->device_control = shdma_control;
-
-        dma_dev->dev = dev;
-
-        return 0;
-}
-EXPORT_SYMBOL(shdma_init);
-
-void shdma_cleanup(struct shdma_dev *sdev)
-{
-        kfree(sdev->schan);
-}
-EXPORT_SYMBOL(shdma_cleanup);
-
-static int __init shdma_enter(void)
-{
-        shdma_slave_used = kzalloc(DIV_ROUND_UP(slave_num, BITS_PER_LONG) *
-                                    sizeof(long), GFP_KERNEL);
-        if (!shdma_slave_used)
-                return -ENOMEM;
-        return 0;
-}
-module_init(shdma_enter);
-
-static void __exit shdma_exit(void)
-{
-        kfree(shdma_slave_used);
-}
-module_exit(shdma_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("SH-DMA driver base library");
-MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
diff --git a/drivers/dma/sh/shdma.c b/drivers/dma/sh/shdma.c
deleted file mode 100644
index 3315e4be9b8..00000000000
--- a/drivers/dma/sh/shdma.c
+++ /dev/null
@@ -1,955 +0,0 @@
-/*
- * Renesas SuperH DMA Engine support
- *
- * base is drivers/dma/flsdma.c
- *
- * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
- * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
- *
- * This is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * - DMA of SuperH does not have Hardware DMA chain mode.
- * - MAX DMA size is 16MB.
- *
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/dmaengine.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
-#include <linux/sh_dma.h>
-#include <linux/notifier.h>
-#include <linux/kdebug.h>
-#include <linux/spinlock.h>
-#include <linux/rculist.h>
-
-#include "../dmaengine.h"
-#include "shdma.h"
-
-#define SH_DMAE_DRV_NAME "sh-dma-engine"
-
-/* Default MEMCPY transfer size = 2^2 = 4 bytes */
-#define LOG2_DEFAULT_XFER_SIZE  2
-#define SH_DMA_SLAVE_NUMBER 256
-#define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
-
-/*
- * Used for write-side mutual exclusion for the global device list,
- * read-side synchronization by way of RCU, and per-controller data.
- */
-static DEFINE_SPINLOCK(sh_dmae_lock);
-static LIST_HEAD(sh_dmae_devices);
-
-static void chclr_write(struct sh_dmae_chan *sh_dc, u32 data)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
-
-        __raw_writel(data, shdev->chan_reg +
-                     shdev->pdata->channel[sh_dc->shdma_chan.id].chclr_offset);
-}
-
-static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
-{
-        __raw_writel(data, sh_dc->base + reg / sizeof(u32));
-}
-
-static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
-{
-        return __raw_readl(sh_dc->base + reg / sizeof(u32));
-}
-
-static u16 dmaor_read(struct sh_dmae_device *shdev)
-{
-        u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
-
-        if (shdev->pdata->dmaor_is_32bit)
-                return __raw_readl(addr);
-        else
-                return __raw_readw(addr);
-}
-
-static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
-{
-        u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
-
-        if (shdev->pdata->dmaor_is_32bit)
-                __raw_writel(data, addr);
-        else
-                __raw_writew(data, addr);
-}
-
-static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
-
-        __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32));
-}
-
-static u32 chcr_read(struct sh_dmae_chan *sh_dc)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
-
-        return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32));
-}
-
-/*
- * Reset DMA controller
- *
- * SH7780 has two DMAOR register
- */
-static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
-{
-        unsigned short dmaor;
-        unsigned long flags;
-
-        spin_lock_irqsave(&sh_dmae_lock, flags);
-
-        dmaor = dmaor_read(shdev);
-        dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
-
-        spin_unlock_irqrestore(&sh_dmae_lock, flags);
-}
-
-static int sh_dmae_rst(struct sh_dmae_device *shdev)
-{
-        unsigned short dmaor;
-        unsigned long flags;
-
-        spin_lock_irqsave(&sh_dmae_lock, flags);
-
-        dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
-
-        if (shdev->pdata->chclr_present) {
-                int i;
-                for (i = 0; i < shdev->pdata->channel_num; i++) {
-                        struct sh_dmae_chan *sh_chan = shdev->chan[i];
-                        if (sh_chan)
-                                chclr_write(sh_chan, 0);
-                }
-        }
-
-        dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
-
-        dmaor = dmaor_read(shdev);
-
-        spin_unlock_irqrestore(&sh_dmae_lock, flags);
-
-        if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
-                dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
-                return -EIO;
-        }
-        if (shdev->pdata->dmaor_init & ~dmaor)
-                dev_warn(shdev->shdma_dev.dma_dev.dev,
-                         "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
-                         dmaor, shdev->pdata->dmaor_init);
-        return 0;
-}
-
-static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
-{
-        u32 chcr = chcr_read(sh_chan);
-
-        if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
-                return true; /* working */
-
-        return false; /* waiting */
-}
-
-static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
-        struct sh_dmae_pdata *pdata = shdev->pdata;
-        int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
-                ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
-
-        if (cnt >= pdata->ts_shift_num)
-                cnt = 0;
-
-        return pdata->ts_shift[cnt];
-}
-
-static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
-        struct sh_dmae_pdata *pdata = shdev->pdata;
-        int i;
-
-        for (i = 0; i < pdata->ts_shift_num; i++)
-                if (pdata->ts_shift[i] == l2size)
-                        break;
-
-        if (i == pdata->ts_shift_num)
-                i = 0;
-
-        return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
-                ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
-}
-
-static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
-{
-        sh_dmae_writel(sh_chan, hw->sar, SAR);
-        sh_dmae_writel(sh_chan, hw->dar, DAR);
-        sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
-}
-
-static void dmae_start(struct sh_dmae_chan *sh_chan)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
-        u32 chcr = chcr_read(sh_chan);
-
-        if (shdev->pdata->needs_tend_set)
-                sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
-
-        chcr |= CHCR_DE | shdev->chcr_ie_bit;
-        chcr_write(sh_chan, chcr & ~CHCR_TE);
-}
-
-static void dmae_init(struct sh_dmae_chan *sh_chan)
-{
-        /*
-         * Default configuration for dual address memory-memory transfer.
-         * 0x400 represents auto-request.
-         */
-        u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
-                                                   LOG2_DEFAULT_XFER_SIZE);
-        sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
-        chcr_write(sh_chan, chcr);
-}
-
-static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
-{
-        /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
-        if (dmae_is_busy(sh_chan))
-                return -EBUSY;
-
-        sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
-        chcr_write(sh_chan, val);
-
-        return 0;
-}
-
-static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
-        struct sh_dmae_pdata *pdata = shdev->pdata;
-        const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
-        u16 __iomem *addr = shdev->dmars;
-        unsigned int shift = chan_pdata->dmars_bit;
-
-        if (dmae_is_busy(sh_chan))
-                return -EBUSY;
-
-        if (pdata->no_dmars)
-                return 0;
-
-        /* in the case of a missing DMARS resource use first memory window */
-        if (!addr)
-                addr = (u16 __iomem *)shdev->chan_reg;
-        addr += chan_pdata->dmars / sizeof(u16);
-
-        __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
-                     addr);
-
-        return 0;
-}
-
-static void sh_dmae_start_xfer(struct shdma_chan *schan,
-                               struct shdma_desc *sdesc)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
-                                                    shdma_chan);
-        struct sh_dmae_desc *sh_desc = container_of(sdesc,
-                                        struct sh_dmae_desc, shdma_desc);
-        dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
-                sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
-                sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
-        /* Get the ld start address from ld_queue */
-        dmae_set_reg(sh_chan, &sh_desc->hw);
-        dmae_start(sh_chan);
-}
-
-static bool sh_dmae_channel_busy(struct shdma_chan *schan)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
-                                                    shdma_chan);
-        return dmae_is_busy(sh_chan);
-}
-
-static void sh_dmae_setup_xfer(struct shdma_chan *schan,
-                               int slave_id)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
-                                                    shdma_chan);
-
-        if (slave_id >= 0) {
-                const struct sh_dmae_slave_config *cfg =
-                        sh_chan->config;
-
-                dmae_set_dmars(sh_chan, cfg->mid_rid);
-                dmae_set_chcr(sh_chan, cfg->chcr);
-        } else {
-                dmae_init(sh_chan);
-        }
-}
-
-static const struct sh_dmae_slave_config *dmae_find_slave(
-        struct sh_dmae_chan *sh_chan, int slave_id)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
-        struct sh_dmae_pdata *pdata = shdev->pdata;
-        const struct sh_dmae_slave_config *cfg;
-        int i;
-
-        if (slave_id >= SH_DMA_SLAVE_NUMBER)
-                return NULL;
-
-        for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
-                if (cfg->slave_id == slave_id)
-                        return cfg;
-
-        return NULL;
-}
-
-static int sh_dmae_set_slave(struct shdma_chan *schan,
-                             int slave_id, bool try)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
-                                                    shdma_chan);
-        const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
-        if (!cfg)
-                return -ENODEV;
-
-        if (!try)
-                sh_chan->config = cfg;
-
-        return 0;
-}
-
-static void dmae_halt(struct sh_dmae_chan *sh_chan)
-{
-        struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
-        u32 chcr = chcr_read(sh_chan);
-
-        chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
-        chcr_write(sh_chan, chcr);
-}
-
-static int sh_dmae_desc_setup(struct shdma_chan *schan,
-                              struct shdma_desc *sdesc,
-                              dma_addr_t src, dma_addr_t dst, size_t *len)
-{
-        struct sh_dmae_desc *sh_desc = container_of(sdesc,
-                                        struct sh_dmae_desc, shdma_desc);
-
-        if (*len > schan->max_xfer_len)
-                *len = schan->max_xfer_len;
-
-        sh_desc->hw.sar = src;
-        sh_desc->hw.dar = dst;
-        sh_desc->hw.tcr = *len;
-
-        return 0;
-}
-
-static void sh_dmae_halt(struct shdma_chan *schan)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
-                                                    shdma_chan);
-        dmae_halt(sh_chan);
-}
-
-static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
-                                                    shdma_chan);
-
-        if (!(chcr_read(sh_chan) & CHCR_TE))
-                return false;
-
-        /* DMA stop */
-        dmae_halt(sh_chan);
-
-        return true;
-}
-
-static size_t sh_dmae_get_partial(struct shdma_chan *schan,
-                                  struct shdma_desc *sdesc)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
-                                                    shdma_chan);
-        struct sh_dmae_desc *sh_desc = container_of(sdesc,
-                                        struct sh_dmae_desc, shdma_desc);
-        return (sh_desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
-                sh_chan->xmit_shift;
-}
-
-/* Called from error IRQ or NMI */
-static bool sh_dmae_reset(struct sh_dmae_device *shdev)
-{
-        bool ret;
-
-        /* halt the dma controller */
-        sh_dmae_ctl_stop(shdev);
-
-        /* We cannot detect, which channel caused the error, have to reset all */
-        ret = shdma_reset(&shdev->shdma_dev);
-
-        sh_dmae_rst(shdev);
-
-        return ret;
-}
-
-static irqreturn_t sh_dmae_err(int irq, void *data)
-{
-        struct sh_dmae_device *shdev = data;
-
-        if (!(dmaor_read(shdev) & DMAOR_AE))
-                return IRQ_NONE;
-
-        sh_dmae_reset(shdev);
-        return IRQ_HANDLED;
-}
-
-static bool sh_dmae_desc_completed(struct shdma_chan *schan,
-                                   struct shdma_desc *sdesc)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan,
-                                        struct sh_dmae_chan, shdma_chan);
-        struct sh_dmae_desc *sh_desc = container_of(sdesc,
-                                        struct sh_dmae_desc, shdma_desc);
-        u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
-        u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
-
-        return  (sdesc->direction == DMA_DEV_TO_MEM &&
-                 (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
-                (sdesc->direction != DMA_DEV_TO_MEM &&
-                 (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
-}
-
-static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
-{
-        /* Fast path out if NMIF is not asserted for this controller */
-        if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
-                return false;
-
-        return sh_dmae_reset(shdev);
-}
-
-static int sh_dmae_nmi_handler(struct notifier_block *self,
-                               unsigned long cmd, void *data)
-{
-        struct sh_dmae_device *shdev;
-        int ret = NOTIFY_DONE;
-        bool triggered;
-
-        /*
-         * Only concern ourselves with NMI events.
-         *
-         * Normally we would check the die chain value, but as this needs
-         * to be architecture independent, check for NMI context instead.
-         */
-        if (!in_nmi())
-                return NOTIFY_DONE;
-
-        rcu_read_lock();
-        list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
-                /*
-                 * Only stop if one of the controllers has NMIF asserted,
-                 * we do not want to interfere with regular address error
-                 * handling or NMI events that don't concern the DMACs.
-                 */
-                triggered = sh_dmae_nmi_notify(shdev);
-                if (triggered == true)
-                        ret = NOTIFY_OK;
-        }
-        rcu_read_unlock();
-
-        return ret;
-}
-
-static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
-        .notifier_call  = sh_dmae_nmi_handler,
-
-        /* Run before NMI debug handler and KGDB */
-        .priority       = 1,
-};
-
-static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
-                                        int irq, unsigned long flags)
-{
-        const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
-        struct shdma_dev *sdev = &shdev->shdma_dev;
-        struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
-        struct sh_dmae_chan *sh_chan;
-        struct shdma_chan *schan;
-        int err;
-
-        sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
-        if (!sh_chan) {
-                dev_err(sdev->dma_dev.dev,
-                        "No free memory for allocating dma channels!\n");
-                return -ENOMEM;
-        }
-
-        schan = &sh_chan->shdma_chan;
-        schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
-
-        shdma_chan_probe(sdev, schan, id);
-
-        sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
-
-        /* set up channel irq */
-        if (pdev->id >= 0)
-                snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
-                         "sh-dmae%d.%d", pdev->id, id);
-        else
-                snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
-                         "sh-dma%d", id);
-
-        err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
-        if (err) {
-                dev_err(sdev->dma_dev.dev,
-                        "DMA channel %d request_irq error %d\n",
-                        id, err);
-                goto err_no_irq;
-        }
-
-        shdev->chan[id] = sh_chan;
-        return 0;
-
-err_no_irq:
-        /* remove from dmaengine device node */
-        shdma_chan_remove(schan);
-        kfree(sh_chan);
-        return err;
-}
-
-static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
-{
-        struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
-        struct shdma_chan *schan;
-        int i;
-
-        shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
-                struct sh_dmae_chan *sh_chan = container_of(schan,
-                                        struct sh_dmae_chan, shdma_chan);
-                BUG_ON(!schan);
-
-                shdma_free_irq(&sh_chan->shdma_chan);
-
-                shdma_chan_remove(schan);
-                kfree(sh_chan);
-        }
-        dma_dev->chancnt = 0;
-}
-
-static void sh_dmae_shutdown(struct platform_device *pdev)
-{
-        struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
-        sh_dmae_ctl_stop(shdev);
-}
-
-static int sh_dmae_runtime_suspend(struct device *dev)
-{
-        return 0;
-}
-
-static int sh_dmae_runtime_resume(struct device *dev)
-{
-        struct sh_dmae_device *shdev = dev_get_drvdata(dev);
-
-        return sh_dmae_rst(shdev);
-}
-
-#ifdef CONFIG_PM
-static int sh_dmae_suspend(struct device *dev)
-{
-        return 0;
-}
-
-static int sh_dmae_resume(struct device *dev)
-{
-        struct sh_dmae_device *shdev = dev_get_drvdata(dev);
-        int i, ret;
-
-        ret = sh_dmae_rst(shdev);
-        if (ret < 0)
-                dev_err(dev, "Failed to reset!\n");
-
-        for (i = 0; i < shdev->pdata->channel_num; i++) {
-                struct sh_dmae_chan *sh_chan = shdev->chan[i];
-
-                if (!sh_chan->shdma_chan.desc_num)
-                        continue;
-
-                if (sh_chan->shdma_chan.slave_id >= 0) {
-                        const struct sh_dmae_slave_config *cfg = sh_chan->config;
-                        dmae_set_dmars(sh_chan, cfg->mid_rid);
-                        dmae_set_chcr(sh_chan, cfg->chcr);
-                } else {
-                        dmae_init(sh_chan);
-                }
-        }
-
-        return 0;
-}
-#else
-#define sh_dmae_suspend NULL
-#define sh_dmae_resume NULL
-#endif
-
-const struct dev_pm_ops sh_dmae_pm = {
-        .suspend                = sh_dmae_suspend,
-        .resume                 = sh_dmae_resume,
-        .runtime_suspend        = sh_dmae_runtime_suspend,
-        .runtime_resume         = sh_dmae_runtime_resume,
-};
-
-static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
-{
-        struct sh_dmae_chan *sh_chan = container_of(schan,
-                                        struct sh_dmae_chan, shdma_chan);
-
-        /*
-         * Implicit BUG_ON(!sh_chan->config)
-         * This is an exclusive slave DMA operation, may only be called after a
-         * successful slave configuration.
-         */
-        return sh_chan->config->addr;
-}
-
-static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
-{
-        return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
-}
-
-static const struct shdma_ops sh_dmae_shdma_ops = {
-        .desc_completed = sh_dmae_desc_completed,
-        .halt_channel = sh_dmae_halt,
-        .channel_busy = sh_dmae_channel_busy,
-        .slave_addr = sh_dmae_slave_addr,
-        .desc_setup = sh_dmae_desc_setup,
-        .set_slave = sh_dmae_set_slave,
-        .setup_xfer = sh_dmae_setup_xfer,
-        .start_xfer = sh_dmae_start_xfer,
-        .embedded_desc = sh_dmae_embedded_desc,
-        .chan_irq = sh_dmae_chan_irq,
-        .get_partial = sh_dmae_get_partial,
-};
-
-static int sh_dmae_probe(struct platform_device *pdev)
-{
-        struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
-        unsigned long irqflags = IRQF_DISABLED,
-                chan_flag[SH_DMAE_MAX_CHANNELS] = {};
-        int errirq, chan_irq[SH_DMAE_MAX_CHANNELS];
-        int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
-        struct sh_dmae_device *shdev;
-        struct dma_device *dma_dev;
-        struct resource *chan, *dmars, *errirq_res, *chanirq_res;
-
-        /* get platform data */
-        if (!pdata || !pdata->channel_num)
-                return -ENODEV;
-
-        chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        /* DMARS area is optional */
-        dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        /*
-         * IRQ resources:
-         * 1. there always must be at least one IRQ IO-resource. On SH4 it is
-         *    the error IRQ, in which case it is the only IRQ in this resource:
-         *    start == end. If it is the only IRQ resource, all channels also
-         *    use the same IRQ.
-         * 2. DMA channel IRQ resources can be specified one per resource or in
-         *    ranges (start != end)
-         * 3. iff all events (channels and, optionally, error) on this
-         *    controller use the same IRQ, only one IRQ resource can be
-         *    specified, otherwise there must be one IRQ per channel, even if
-         *    some of them are equal
-         * 4. if all IRQs on this controller are equal or if some specific IRQs
-         *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
-         *    requested with the IRQF_SHARED flag
-         */
-        errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        if (!chan || !errirq_res)
-                return -ENODEV;
-
-        if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
-                dev_err(&pdev->dev, "DMAC register region already claimed\n");
-                return -EBUSY;
-        }
-
-        if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
-                dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
-                err = -EBUSY;
-                goto ermrdmars;
-        }
-
-        err = -ENOMEM;
-        shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
-        if (!shdev) {
-                dev_err(&pdev->dev, "Not enough memory\n");
-                goto ealloc;
-        }
-
-        dma_dev = &shdev->shdma_dev.dma_dev;
-
-        shdev->chan_reg = ioremap(chan->start, resource_size(chan));
-        if (!shdev->chan_reg)
-                goto emapchan;
-        if (dmars) {
-                shdev->dmars = ioremap(dmars->start, resource_size(dmars));
-                if (!shdev->dmars)
-                        goto emapdmars;
-        }
-
-        if (!pdata->slave_only)
-                dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
-        if (pdata->slave && pdata->slave_num)
-                dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
-
-        /* Default transfer size of 32 bytes requires 32-byte alignment */
-        dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
-
-        shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
-        shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
-        err = shdma_init(&pdev->dev, &shdev->shdma_dev,
-                              pdata->channel_num);
-        if (err < 0)
-                goto eshdma;
-
-        /* platform data */
-        shdev->pdata = pdev->dev.platform_data;
-
-        if (pdata->chcr_offset)
-                shdev->chcr_offset = pdata->chcr_offset;
-        else
-                shdev->chcr_offset = CHCR;
-
-        if (pdata->chcr_ie_bit)
-                shdev->chcr_ie_bit = pdata->chcr_ie_bit;
-        else
-                shdev->chcr_ie_bit = CHCR_IE;
-
-        platform_set_drvdata(pdev, shdev);
-
-        pm_runtime_enable(&pdev->dev);
-        err = pm_runtime_get_sync(&pdev->dev);
-        if (err < 0)
-                dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
-
-        spin_lock_irq(&sh_dmae_lock);
-        list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
-        spin_unlock_irq(&sh_dmae_lock);
-
-        /* reset dma controller - only needed as a test */
-        err = sh_dmae_rst(shdev);
-        if (err)
-                goto rst_err;
-
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
-        chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
-
-        if (!chanirq_res)
-                chanirq_res = errirq_res;
-        else
-                irqres++;
-
-        if (chanirq_res == errirq_res ||
-            (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
-                irqflags = IRQF_SHARED;
-
-        errirq = errirq_res->start;
-
-        err = request_irq(errirq, sh_dmae_err, irqflags,
-                          "DMAC Address Error", shdev);
-        if (err) {
-                dev_err(&pdev->dev,
-                        "DMA failed requesting irq #%d, error %d\n",
-                        errirq, err);
-                goto eirq_err;
-        }
-
-#else
-        chanirq_res = errirq_res;
-#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
-
-        if (chanirq_res->start == chanirq_res->end &&
-            !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
-                /* Special case - all multiplexed */
-                for (; irq_cnt < pdata->channel_num; irq_cnt++) {
-                        if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
-                                chan_irq[irq_cnt] = chanirq_res->start;
-                                chan_flag[irq_cnt] = IRQF_SHARED;
-                        } else {
-                                irq_cap = 1;
-                                break;
-                        }
-                }
-        } else {
-                do {
-                        for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
-                                if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
-                                        irq_cap = 1;
-                                        break;
-                                }
-
-                                if ((errirq_res->flags & IORESOURCE_BITS) ==
-                                    IORESOURCE_IRQ_SHAREABLE)
-                                        chan_flag[irq_cnt] = IRQF_SHARED;
-                                else
-                                        chan_flag[irq_cnt] = IRQF_DISABLED;
-                                dev_dbg(&pdev->dev,
-                                        "Found IRQ %d for channel %d\n",
-                                        i, irq_cnt);
-                                chan_irq[irq_cnt++] = i;
-                        }
-
-                        if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
-                                break;
-
-                        chanirq_res = platform_get_resource(pdev,
-                                                IORESOURCE_IRQ, ++irqres);
-                } while (irq_cnt < pdata->channel_num && chanirq_res);
-        }
-
-        /* Create DMA Channel */
-        for (i = 0; i < irq_cnt; i++) {
-                err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
-                if (err)
-                        goto chan_probe_err;
-        }
-
-        if (irq_cap)
-                dev_notice(&pdev->dev, "Attempting to register %d DMA "
-                           "channels when a maximum of %d are supported.\n",
-                           pdata->channel_num, SH_DMAE_MAX_CHANNELS);
-
-        pm_runtime_put(&pdev->dev);
-
-        err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
-        if (err < 0)
-                goto edmadevreg;
-
-        return err;
-
-edmadevreg:
-        pm_runtime_get(&pdev->dev);
-
-chan_probe_err:
-        sh_dmae_chan_remove(shdev);
-
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
-        free_irq(errirq, shdev);
-eirq_err:
-#endif
-rst_err:
-        spin_lock_irq(&sh_dmae_lock);
-        list_del_rcu(&shdev->node);
-        spin_unlock_irq(&sh_dmae_lock);
-
-        pm_runtime_put(&pdev->dev);
-        pm_runtime_disable(&pdev->dev);
-
-        platform_set_drvdata(pdev, NULL);
-        shdma_cleanup(&shdev->shdma_dev);
-eshdma:
-        if (dmars)
-                iounmap(shdev->dmars);
-emapdmars:
-        iounmap(shdev->chan_reg);
-        synchronize_rcu();
-emapchan:
-        kfree(shdev);
-ealloc:
-        if (dmars)
-                release_mem_region(dmars->start, resource_size(dmars));
-ermrdmars:
-        release_mem_region(chan->start, resource_size(chan));
-
-        return err;
-}
-
-static int sh_dmae_remove(struct platform_device *pdev)
-{
-        struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
-        struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
-        struct resource *res;
-        int errirq = platform_get_irq(pdev, 0);
-
-        dma_async_device_unregister(dma_dev);
-
-        if (errirq > 0)
-                free_irq(errirq, shdev);
-
-        spin_lock_irq(&sh_dmae_lock);
-        list_del_rcu(&shdev->node);
-        spin_unlock_irq(&sh_dmae_lock);
-
-        pm_runtime_disable(&pdev->dev);
-
-        sh_dmae_chan_remove(shdev);
-        shdma_cleanup(&shdev->shdma_dev);
-
-        if (shdev->dmars)
-                iounmap(shdev->dmars);
-        iounmap(shdev->chan_reg);
-
-        platform_set_drvdata(pdev, NULL);
-
-        synchronize_rcu();
-        kfree(shdev);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (res)
-                release_mem_region(res->start, resource_size(res));
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        if (res)
-                release_mem_region(res->start, resource_size(res));
-
-        return 0;
-}
-
-static struct platform_driver sh_dmae_driver = {
-        .driver         = {
-                .owner  = THIS_MODULE,
-                .pm     = &sh_dmae_pm,
-                .name   = SH_DMAE_DRV_NAME,
-        },
-        .remove         = sh_dmae_remove,
-        .shutdown       = sh_dmae_shutdown,
-};
-
-static int __init sh_dmae_init(void)
-{
-        /* Wire up NMI handling */
-        int err = register_die_notifier(&sh_dmae_nmi_notifier);
-        if (err)
-                return err;
-
-        return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
-}
-module_init(sh_dmae_init);
-
-static void __exit sh_dmae_exit(void)
-{
-        platform_driver_unregister(&sh_dmae_driver);
-
-        unregister_die_notifier(&sh_dmae_nmi_notifier);
-}
-module_exit(sh_dmae_exit);
-
-MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
-MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);
diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h
deleted file mode 100644
index 9314e93225d..00000000000
--- a/drivers/dma/sh/shdma.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Renesas SuperH DMA Engine support
- *
- * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
- *
- * This is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __DMA_SHDMA_H
-#define __DMA_SHDMA_H
-
-#include <linux/sh_dma.h>
-#include <linux/shdma-base.h>
-#include <linux/dmaengine.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-
-#define SH_DMAE_MAX_CHANNELS 20
-#define SH_DMAE_TCR_MAX 0x00FFFFFF      /* 16MB */
-
-struct device;
-
-struct sh_dmae_chan {
-        struct shdma_chan shdma_chan;
-        const struct sh_dmae_slave_config *config; /* Slave DMA configuration */
-        int xmit_shift;                 /* log_2(bytes_per_xfer) */
-        u32 __iomem *base;
-        char dev_id[16];                /* unique name per DMAC of channel */
-        int pm_error;
-};
-
-struct sh_dmae_device {
-        struct shdma_dev shdma_dev;
-        struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
-        struct sh_dmae_pdata *pdata;
-        struct list_head node;
-        u32 __iomem *chan_reg;
-        u16 __iomem *dmars;
-        unsigned int chcr_offset;
-        u32 chcr_ie_bit;
-};
-
-struct sh_dmae_regs {
-        u32 sar; /* SAR / source address */
-        u32 dar; /* DAR / destination address */
-        u32 tcr; /* TCR / transfer count */
-};
-
-struct sh_dmae_desc {
-        struct sh_dmae_regs hw;
-        struct shdma_desc shdma_desc;
-};
-
-#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
-#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
-#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
-#define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
-                                     struct sh_dmae_device, shdma_dev.dma_dev)
-
-#endif  /* __DMA_SHDMA_H */
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
deleted file mode 100644
index 94674a96c64..00000000000
--- a/drivers/dma/sirf-dma.c
+++ /dev/null
@@ -1,689 +0,0 @@
-/*
- * DMA controller driver for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/dmaengine.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <linux/sirfsoc_dma.h>
-
-#include "dmaengine.h"
-
-#define SIRFSOC_DMA_DESCRIPTORS                 16
-#define SIRFSOC_DMA_CHANNELS                    16
-
-#define SIRFSOC_DMA_CH_ADDR                     0x00
-#define SIRFSOC_DMA_CH_XLEN                     0x04
-#define SIRFSOC_DMA_CH_YLEN                     0x08
-#define SIRFSOC_DMA_CH_CTRL                     0x0C
-
-#define SIRFSOC_DMA_WIDTH_0                     0x100
-#define SIRFSOC_DMA_CH_VALID                    0x140
-#define SIRFSOC_DMA_CH_INT                      0x144
-#define SIRFSOC_DMA_INT_EN                      0x148
-#define SIRFSOC_DMA_CH_LOOP_CTRL                0x150
-
-#define SIRFSOC_DMA_MODE_CTRL_BIT               4
-#define SIRFSOC_DMA_DIR_CTRL_BIT                5
-
-/* xlen and dma_width register is in 4 bytes boundary */
-#define SIRFSOC_DMA_WORD_LEN                    4
-
-struct sirfsoc_dma_desc {
-        struct dma_async_tx_descriptor  desc;
-        struct list_head                node;
-
-        /* SiRFprimaII 2D-DMA parameters */
-
-        int             xlen;           /* DMA xlen */
-        int             ylen;           /* DMA ylen */
-        int             width;          /* DMA width */
-        int             dir;
-        bool            cyclic;         /* is loop DMA? */
-        u32             addr;           /* DMA buffer address */
-};
-
-struct sirfsoc_dma_chan {
-        struct dma_chan                 chan;
-        struct list_head                free;
-        struct list_head                prepared;
-        struct list_head                queued;
-        struct list_head                active;
-        struct list_head                completed;
-        unsigned long                   happened_cyclic;
-        unsigned long                   completed_cyclic;
-
-        /* Lock for this structure */
-        spinlock_t                      lock;
-
-        int                             mode;
-};
-
-struct sirfsoc_dma {
-        struct dma_device               dma;
-        struct tasklet_struct           tasklet;
-        struct sirfsoc_dma_chan         channels[SIRFSOC_DMA_CHANNELS];
-        void __iomem                    *base;
-        int                             irq;
-};
-
-#define DRV_NAME        "sirfsoc_dma"
-
-/* Convert struct dma_chan to struct sirfsoc_dma_chan */
-static inline
-struct sirfsoc_dma_chan *dma_chan_to_sirfsoc_dma_chan(struct dma_chan *c)
-{
-        return container_of(c, struct sirfsoc_dma_chan, chan);
-}
-
-/* Convert struct dma_chan to struct sirfsoc_dma */
-static inline struct sirfsoc_dma *dma_chan_to_sirfsoc_dma(struct dma_chan *c)
-{
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(c);
-        return container_of(schan, struct sirfsoc_dma, channels[c->chan_id]);
-}
-
-/* Execute all queued DMA descriptors */
-static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan)
-{
-        struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
-        int cid = schan->chan.chan_id;
-        struct sirfsoc_dma_desc *sdesc = NULL;
-
-        /*
-         * lock has been held by functions calling this, so we don't hold
-         * lock again
-         */
-
-        sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc,
-                node);
-        /* Move the first queued descriptor to active list */
-        list_move_tail(&sdesc->node, &schan->active);
-
-        /* Start the DMA transfer */
-        writel_relaxed(sdesc->width, sdma->base + SIRFSOC_DMA_WIDTH_0 +
-                cid * 4);
-        writel_relaxed(cid | (schan->mode << SIRFSOC_DMA_MODE_CTRL_BIT) |
-                (sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT),
-                sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL);
-        writel_relaxed(sdesc->xlen, sdma->base + cid * 0x10 +
-                SIRFSOC_DMA_CH_XLEN);
-        writel_relaxed(sdesc->ylen, sdma->base + cid * 0x10 +
-                SIRFSOC_DMA_CH_YLEN);
-        writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) |
-                (1 << cid), sdma->base + SIRFSOC_DMA_INT_EN);
-
-        /*
-         * writel has an implict memory write barrier to make sure data is
-         * flushed into memory before starting DMA
-         */
-        writel(sdesc->addr >> 2, sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR);
-
-        if (sdesc->cyclic) {
-                writel((1 << cid) | 1 << (cid + 16) |
-                        readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL),
-                        sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
-                schan->happened_cyclic = schan->completed_cyclic = 0;
-        }
-}
-
-/* Interrupt handler */
-static irqreturn_t sirfsoc_dma_irq(int irq, void *data)
-{
-        struct sirfsoc_dma *sdma = data;
-        struct sirfsoc_dma_chan *schan;
-        struct sirfsoc_dma_desc *sdesc = NULL;
-        u32 is;
-        int ch;
-
-        is = readl(sdma->base + SIRFSOC_DMA_CH_INT);
-        while ((ch = fls(is) - 1) >= 0) {
-                is &= ~(1 << ch);
-                writel_relaxed(1 << ch, sdma->base + SIRFSOC_DMA_CH_INT);
-                schan = &sdma->channels[ch];
-
-                spin_lock(&schan->lock);
-
-                sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
-                        node);
-                if (!sdesc->cyclic) {
-                        /* Execute queued descriptors */
-                        list_splice_tail_init(&schan->active, &schan->completed);
-                        if (!list_empty(&schan->queued))
-                                sirfsoc_dma_execute(schan);
-                } else
-                        schan->happened_cyclic++;
-
-                spin_unlock(&schan->lock);
-        }
-
-        /* Schedule tasklet */
-        tasklet_schedule(&sdma->tasklet);
-
-        return IRQ_HANDLED;
-}
-
-/* process completed descriptors */
-static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma)
-{
-        dma_cookie_t last_cookie = 0;
-        struct sirfsoc_dma_chan *schan;
-        struct sirfsoc_dma_desc *sdesc;
-        struct dma_async_tx_descriptor *desc;
-        unsigned long flags;
-        unsigned long happened_cyclic;
-        LIST_HEAD(list);
-        int i;
-
-        for (i = 0; i < sdma->dma.chancnt; i++) {
-                schan = &sdma->channels[i];
-
-                /* Get all completed descriptors */
-                spin_lock_irqsave(&schan->lock, flags);
-                if (!list_empty(&schan->completed)) {
-                        list_splice_tail_init(&schan->completed, &list);
-                        spin_unlock_irqrestore(&schan->lock, flags);
-
-                        /* Execute callbacks and run dependencies */
-                        list_for_each_entry(sdesc, &list, node) {
-                                desc = &sdesc->desc;
-
-                                if (desc->callback)
-                                        desc->callback(desc->callback_param);
-
-                                last_cookie = desc->cookie;
-                                dma_run_dependencies(desc);
-                        }
-
-                        /* Free descriptors */
-                        spin_lock_irqsave(&schan->lock, flags);
-                        list_splice_tail_init(&list, &schan->free);
-                        schan->chan.completed_cookie = last_cookie;
-                        spin_unlock_irqrestore(&schan->lock, flags);
-                } else {
-                        /* for cyclic channel, desc is always in active list */
-                        sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc,
-                                node);
-
-                        if (!sdesc || (sdesc && !sdesc->cyclic)) {
-                                /* without active cyclic DMA */
-                                spin_unlock_irqrestore(&schan->lock, flags);
-                                continue;
-                        }
-
-                        /* cyclic DMA */
-                        happened_cyclic = schan->happened_cyclic;
-                        spin_unlock_irqrestore(&schan->lock, flags);
-
-                        desc = &sdesc->desc;
-                        while (happened_cyclic != schan->completed_cyclic) {
-                                if (desc->callback)
-                                        desc->callback(desc->callback_param);
-                                schan->completed_cyclic++;
-                        }
-                }
-        }
-}
-
-/* DMA Tasklet */
-static void sirfsoc_dma_tasklet(unsigned long data)
-{
-        struct sirfsoc_dma *sdma = (void *)data;
-
-        sirfsoc_dma_process_completed(sdma);
-}
-
-/* Submit descriptor to hardware */
-static dma_cookie_t sirfsoc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
-{
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(txd->chan);
-        struct sirfsoc_dma_desc *sdesc;
-        unsigned long flags;
-        dma_cookie_t cookie;
-
-        sdesc = container_of(txd, struct sirfsoc_dma_desc, desc);
-
-        spin_lock_irqsave(&schan->lock, flags);
-
-        /* Move descriptor to queue */
-        list_move_tail(&sdesc->node, &schan->queued);
-
-        cookie = dma_cookie_assign(txd);
-
-        spin_unlock_irqrestore(&schan->lock, flags);
-
-        return cookie;
-}
-
-static int sirfsoc_dma_slave_config(struct sirfsoc_dma_chan *schan,
-        struct dma_slave_config *config)
-{
-        unsigned long flags;
-
-        if ((config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
-                (config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES))
-                return -EINVAL;
-
-        spin_lock_irqsave(&schan->lock, flags);
-        schan->mode = (config->src_maxburst == 4 ? 1 : 0);
-        spin_unlock_irqrestore(&schan->lock, flags);
-
-        return 0;
-}
-
-static int sirfsoc_dma_terminate_all(struct sirfsoc_dma_chan *schan)
-{
-        struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
-        int cid = schan->chan.chan_id;
-        unsigned long flags;
-
-        writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) &
-                ~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN);
-        writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);
-
-        writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL)
-                & ~((1 << cid) | 1 << (cid + 16)),
-                        sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
-
-        spin_lock_irqsave(&schan->lock, flags);
-        list_splice_tail_init(&schan->active, &schan->free);
-        list_splice_tail_init(&schan->queued, &schan->free);
-        spin_unlock_irqrestore(&schan->lock, flags);
-
-        return 0;
-}
-
-static int sirfsoc_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-        unsigned long arg)
-{
-        struct dma_slave_config *config;
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
-
-        switch (cmd) {
-        case DMA_TERMINATE_ALL:
-                return sirfsoc_dma_terminate_all(schan);
-        case DMA_SLAVE_CONFIG:
-                config = (struct dma_slave_config *)arg;
-                return sirfsoc_dma_slave_config(schan, config);
-
-        default:
-                break;
-        }
-
-        return -ENOSYS;
-}
-
-/* Alloc channel resources */
-static int sirfsoc_dma_alloc_chan_resources(struct dma_chan *chan)
-{
-        struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
-        struct sirfsoc_dma_desc *sdesc;
-        unsigned long flags;
-        LIST_HEAD(descs);
-        int i;
-
-        /* Alloc descriptors for this channel */
-        for (i = 0; i < SIRFSOC_DMA_DESCRIPTORS; i++) {
-                sdesc = kzalloc(sizeof(*sdesc), GFP_KERNEL);
-                if (!sdesc) {
-                        dev_notice(sdma->dma.dev, "Memory allocation error. "
-                                "Allocated only %u descriptors\n", i);
-                        break;
-                }
-
-                dma_async_tx_descriptor_init(&sdesc->desc, chan);
-                sdesc->desc.flags = DMA_CTRL_ACK;
-                sdesc->desc.tx_submit = sirfsoc_dma_tx_submit;
-
-                list_add_tail(&sdesc->node, &descs);
-        }
-
-        /* Return error only if no descriptors were allocated */
-        if (i == 0)
-                return -ENOMEM;
-
-        spin_lock_irqsave(&schan->lock, flags);
-
-        list_splice_tail_init(&descs, &schan->free);
-        spin_unlock_irqrestore(&schan->lock, flags);
-
-        return i;
-}
-
-/* Free channel resources */
-static void sirfsoc_dma_free_chan_resources(struct dma_chan *chan)
-{
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
-        struct sirfsoc_dma_desc *sdesc, *tmp;
-        unsigned long flags;
-        LIST_HEAD(descs);
-
-        spin_lock_irqsave(&schan->lock, flags);
-
-        /* Channel must be idle */
-        BUG_ON(!list_empty(&schan->prepared));
-        BUG_ON(!list_empty(&schan->queued));
-        BUG_ON(!list_empty(&schan->active));
-        BUG_ON(!list_empty(&schan->completed));
-
-        /* Move data */
-        list_splice_tail_init(&schan->free, &descs);
-
-        spin_unlock_irqrestore(&schan->lock, flags);
-
-        /* Free descriptors */
-        list_for_each_entry_safe(sdesc, tmp, &descs, node)
-                kfree(sdesc);
-}
-
-/* Send pending descriptor to hardware */
-static void sirfsoc_dma_issue_pending(struct dma_chan *chan)
-{
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
-        unsigned long flags;
-
-        spin_lock_irqsave(&schan->lock, flags);
-
-        if (list_empty(&schan->active) && !list_empty(&schan->queued))
-                sirfsoc_dma_execute(schan);
-
-        spin_unlock_irqrestore(&schan->lock, flags);
-}
-
-/* Check request completion status */
-static enum dma_status
-sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
-        struct dma_tx_state *txstate)
-{
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
-        unsigned long flags;
-        enum dma_status ret;
-
-        spin_lock_irqsave(&schan->lock, flags);
-        ret = dma_cookie_status(chan, cookie, txstate);
-        spin_unlock_irqrestore(&schan->lock, flags);
-
-        return ret;
-}
-
-static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
-        struct dma_chan *chan, struct dma_interleaved_template *xt,
-        unsigned long flags)
-{
-        struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
-        struct sirfsoc_dma_desc *sdesc = NULL;
-        unsigned long iflags;
-        int ret;
-
-        if ((xt->dir != DMA_MEM_TO_DEV) && (xt->dir != DMA_DEV_TO_MEM)) {
-                ret = -EINVAL;
-                goto err_dir;
-        }
-
-        /* Get free descriptor */
-        spin_lock_irqsave(&schan->lock, iflags);
-        if (!list_empty(&schan->free)) {
-                sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc,
-                        node);
-                list_del(&sdesc->node);
-        }
-        spin_unlock_irqrestore(&schan->lock, iflags);
-
-        if (!sdesc) {
-                /* try to free completed descriptors */
-                sirfsoc_dma_process_completed(sdma);
-                ret = 0;
-                goto no_desc;
-        }
-
-        /* Place descriptor in prepared list */
-        spin_lock_irqsave(&schan->lock, iflags);
-
-        /*
-         * Number of chunks in a frame can only be 1 for prima2
-         * and ylen (number of frame - 1) must be at least 0
-         */
-        if ((xt->frame_size == 1) && (xt->numf > 0)) {
-                sdesc->cyclic = 0;
-                sdesc->xlen = xt->sgl[0].size / SIRFSOC_DMA_WORD_LEN;
-                sdesc->width = (xt->sgl[0].size + xt->sgl[0].icg) /
-                                SIRFSOC_DMA_WORD_LEN;
-                sdesc->ylen = xt->numf - 1;
-                if (xt->dir == DMA_MEM_TO_DEV) {
-                        sdesc->addr = xt->src_start;
-                        sdesc->dir = 1;
-                } else {
-                        sdesc->addr = xt->dst_start;
-                        sdesc->dir = 0;
-                }
-
-                list_add_tail(&sdesc->node, &schan->prepared);
-        } else {
-                pr_err("sirfsoc DMA Invalid xfer\n");
-                ret = -EINVAL;
-                goto err_xfer;
-        }
-        spin_unlock_irqrestore(&schan->lock, iflags);
-
-        return &sdesc->desc;
-err_xfer:
-        spin_unlock_irqrestore(&schan->lock, iflags);
-no_desc:
-err_dir:
-        return ERR_PTR(ret);
-}
-
-static struct dma_async_tx_descriptor *
-sirfsoc_dma_prep_cyclic(struct dma_chan *chan, dma_addr_t addr,
-        size_t buf_len, size_t period_len,
-        enum dma_transfer_direction direction, unsigned long flags, void *context)
-{
-        struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
-        struct sirfsoc_dma_desc *sdesc = NULL;
-        unsigned long iflags;
-
-        /*
-         * we only support cycle transfer with 2 period
-         * If the X-length is set to 0, it would be the loop mode.
-         * The DMA address keeps increasing until reaching the end of a loop
-         * area whose size is defined by (DMA_WIDTH x (Y_LENGTH + 1)). Then
-         * the DMA address goes back to the beginning of this area.
-         * In loop mode, the DMA data region is divided into two parts, BUFA
-         * and BUFB. DMA controller generates interrupts twice in each loop:
-         * when the DMA address reaches the end of BUFA or the end of the
-         * BUFB
-         */
-        if (buf_len !=  2 * period_len)
-                return ERR_PTR(-EINVAL);
-
-        /* Get free descriptor */
-        spin_lock_irqsave(&schan->lock, iflags);
-        if (!list_empty(&schan->free)) {
-                sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc,
-                        node);
-                list_del(&sdesc->node);
-        }
-        spin_unlock_irqrestore(&schan->lock, iflags);
-
-        if (!sdesc)
-                return 0;
-
-        /* Place descriptor in prepared list */
-        spin_lock_irqsave(&schan->lock, iflags);
-        sdesc->addr = addr;
-        sdesc->cyclic = 1;
-        sdesc->xlen = 0;
-        sdesc->ylen = buf_len / SIRFSOC_DMA_WORD_LEN - 1;
-        sdesc->width = 1;
-        list_add_tail(&sdesc->node, &schan->prepared);
-        spin_unlock_irqrestore(&schan->lock, iflags);
-
-        return &sdesc->desc;
-}
-
-/*
- * The DMA controller consists of 16 independent DMA channels.
- * Each channel is allocated to a different function
- */
-bool sirfsoc_dma_filter_id(struct dma_chan *chan, void *chan_id)
-{
-        unsigned int ch_nr = (unsigned int) chan_id;
-
-        if (ch_nr == chan->chan_id +
-                chan->device->dev_id * SIRFSOC_DMA_CHANNELS)
-                return true;
-
-        return false;
-}
-EXPORT_SYMBOL(sirfsoc_dma_filter_id);
-
-static int sirfsoc_dma_probe(struct platform_device *op)
-{
-        struct device_node *dn = op->dev.of_node;
-        struct device *dev = &op->dev;
-        struct dma_device *dma;
-        struct sirfsoc_dma *sdma;
-        struct sirfsoc_dma_chan *schan;
-        struct resource res;
-        ulong regs_start, regs_size;
-        u32 id;
-        int ret, i;
-
-        sdma = devm_kzalloc(dev, sizeof(*sdma), GFP_KERNEL);
-        if (!sdma) {
-                dev_err(dev, "Memory exhausted!\n");
-                return -ENOMEM;
-        }
-
-        if (of_property_read_u32(dn, "cell-index", &id)) {
-                dev_err(dev, "Fail to get DMAC index\n");
-                return -ENODEV;
-        }
-
-        sdma->irq = irq_of_parse_and_map(dn, 0);
-        if (sdma->irq == NO_IRQ) {
-                dev_err(dev, "Error mapping IRQ!\n");
-                return -EINVAL;
-        }
-
-        ret = of_address_to_resource(dn, 0, &res);
-        if (ret) {
-                dev_err(dev, "Error parsing memory region!\n");
-                goto irq_dispose;
-        }
-
-        regs_start = res.start;
-        regs_size = resource_size(&res);
-
-        sdma->base = devm_ioremap(dev, regs_start, regs_size);
-        if (!sdma->base) {
-                dev_err(dev, "Error mapping memory region!\n");
-                ret = -ENOMEM;
-                goto irq_dispose;
-        }
-
-        ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME, sdma);
-        if (ret) {
-                dev_err(dev, "Error requesting IRQ!\n");
-                ret = -EINVAL;
-                goto irq_dispose;
-        }
-
-        dma = &sdma->dma;
-        dma->dev = dev;
-        dma->chancnt = SIRFSOC_DMA_CHANNELS;
-
-        dma->device_alloc_chan_resources = sirfsoc_dma_alloc_chan_resources;
-        dma->device_free_chan_resources = sirfsoc_dma_free_chan_resources;
-        dma->device_issue_pending = sirfsoc_dma_issue_pending;
-        dma->device_control = sirfsoc_dma_control;
-        dma->device_tx_status = sirfsoc_dma_tx_status;
-        dma->device_prep_interleaved_dma = sirfsoc_dma_prep_interleaved;
-        dma->device_prep_dma_cyclic = sirfsoc_dma_prep_cyclic;
-
-        INIT_LIST_HEAD(&dma->channels);
-        dma_cap_set(DMA_SLAVE, dma->cap_mask);
-        dma_cap_set(DMA_CYCLIC, dma->cap_mask);
-        dma_cap_set(DMA_INTERLEAVE, dma->cap_mask);
-        dma_cap_set(DMA_PRIVATE, dma->cap_mask);
-
-        for (i = 0; i < dma->chancnt; i++) {
-                schan = &sdma->channels[i];
-
-                schan->chan.device = dma;
-                dma_cookie_init(&schan->chan);
-
-                INIT_LIST_HEAD(&schan->free);
-                INIT_LIST_HEAD(&schan->prepared);
-                INIT_LIST_HEAD(&schan->queued);
-                INIT_LIST_HEAD(&schan->active);
-                INIT_LIST_HEAD(&schan->completed);
-
-                spin_lock_init(&schan->lock);
-                list_add_tail(&schan->chan.device_node, &dma->channels);
-        }
-
-        tasklet_init(&sdma->tasklet, sirfsoc_dma_tasklet, (unsigned long)sdma);
-
-        /* Register DMA engine */
-        dev_set_drvdata(dev, sdma);
-        ret = dma_async_device_register(dma);
-        if (ret)
-                goto free_irq;
-
-        dev_info(dev, "initialized SIRFSOC DMAC driver\n");
-
-        return 0;
-
-free_irq:
-        free_irq(sdma->irq, sdma);
-irq_dispose:
-        irq_dispose_mapping(sdma->irq);
-        return ret;
-}
-
-static int sirfsoc_dma_remove(struct platform_device *op)
-{
-        struct device *dev = &op->dev;
-        struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
-
-        dma_async_device_unregister(&sdma->dma);
-        free_irq(sdma->irq, sdma);
-        irq_dispose_mapping(sdma->irq);
-        return 0;
-}
-
-static struct of_device_id sirfsoc_dma_match[] = {
-        { .compatible = "sirf,prima2-dmac", },
-        {},
-};
-
-static struct platform_driver sirfsoc_dma_driver = {
-        .probe          = sirfsoc_dma_probe,
-        .remove         = sirfsoc_dma_remove,
-        .driver = {
-                .name = DRV_NAME,
-                .owner = THIS_MODULE,
-                .of_match_table = sirfsoc_dma_match,
-        },
-};
-
-module_platform_driver(sirfsoc_dma_driver);
-
-MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
-        "Barry Song <baohua.song@csr.com>");
-MODULE_DESCRIPTION("SIRFSOC DMA control driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 23c5573e62d..467e4dcb20a 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -9,19 +9,15 @@
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
-#include <linux/export.h>
 #include <linux/dmaengine.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
-#include <linux/pm.h>
-#include <linux/pm_runtime.h>
 #include <linux/err.h>
 #include <linux/amba/bus.h>
-#include <linux/regulator/consumer.h>
-#include <linux/platform_data/dma-ste-dma40.h>
 
-#include "dmaengine.h"
+#include <plat/ste_dma40.h>
+
 #include "ste_dma40_ll.h"
 
 #define D40_NAME "dma40"
@@ -35,9 +31,6 @@
 /* Maximum iterations taken before giving up suspending a channel */
 #define D40_SUSPEND_MAX_IT 500
 
-/* Milliseconds */
-#define DMA40_AUTOSUSPEND_DELAY 100
-
 /* Hardware requirement on LCLA alignment */
 #define LCLA_ALIGNMENT 0x40000
 
@@ -68,71 +61,6 @@ enum d40_command {
         D40_DMA_SUSPENDED       = 3
 };
 
-/*
- * enum d40_events - The different Event Enables for the event lines.
- *
- * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
- * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
- * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
- * @D40_ROUND_EVENTLINE: Status check for event line.
- */
-
-enum d40_events {
-        D40_DEACTIVATE_EVENTLINE        = 0,
-        D40_ACTIVATE_EVENTLINE          = 1,
-        D40_SUSPEND_REQ_EVENTLINE       = 2,
-        D40_ROUND_EVENTLINE             = 3
-};
-
-/*
- * These are the registers that has to be saved and later restored
- * when the DMA hw is powered off.
- * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
- */
-static u32 d40_backup_regs[] = {
-        D40_DREG_LCPA,
-        D40_DREG_LCLA,
-        D40_DREG_PRMSE,
-        D40_DREG_PRMSO,
-        D40_DREG_PRMOE,
-        D40_DREG_PRMOO,
-};
-
-#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
-
-/* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
-static u32 d40_backup_regs_v3[] = {
-        D40_DREG_PSEG1,
-        D40_DREG_PSEG2,
-        D40_DREG_PSEG3,
-        D40_DREG_PSEG4,
-        D40_DREG_PCEG1,
-        D40_DREG_PCEG2,
-        D40_DREG_PCEG3,
-        D40_DREG_PCEG4,
-        D40_DREG_RSEG1,
-        D40_DREG_RSEG2,
-        D40_DREG_RSEG3,
-        D40_DREG_RSEG4,
-        D40_DREG_RCEG1,
-        D40_DREG_RCEG2,
-        D40_DREG_RCEG3,
-        D40_DREG_RCEG4,
-};
-
-#define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
-
-static u32 d40_backup_regs_chan[] = {
-        D40_CHAN_REG_SSCFG,
-        D40_CHAN_REG_SSELT,
-        D40_CHAN_REG_SSPTR,
-        D40_CHAN_REG_SSLNK,
-        D40_CHAN_REG_SDCFG,
-        D40_CHAN_REG_SDELT,
-        D40_CHAN_REG_SDPTR,
-        D40_CHAN_REG_SDLNK,
-};
-
 /**
  * struct d40_lli_pool - Structure for keeping LLIs in memory
  *
@@ -167,7 +95,7 @@ struct d40_lli_pool {
  * during a transfer.
  * @node: List entry.
  * @is_in_client_list: true if the client owns this descriptor.
- * @cyclic: true if this is a cyclic job
+ * the previous one.
  *
  * This descriptor is used for both logical and physical transfers.
  */
@@ -214,7 +142,6 @@ struct d40_lcla_pool {
  * channels.
  *
  * @lock: A lock protection this entity.
- * @reserved: True if used by secure world or otherwise.
  * @num: The physical channel number of this entity.
  * @allocated_src: Bit mapped to show which src event line's are mapped to
  * this physical channel. Can also be free or physically allocated.
@@ -224,7 +151,6 @@ struct d40_lcla_pool {
  */
 struct d40_phy_res {
         spinlock_t lock;
-        bool       reserved;
         int        num;
         u32        allocated_src;
         u32        allocated_dst;
@@ -237,6 +163,8 @@ struct d40_base;
  *
  * @lock: A spinlock to protect this struct.
  * @log_num: The logical number, if any of this channel.
+ * @completed: Starts with 1, after first interrupt it is set to dma engine's
+ * current cookie.
  * @pending_tx: The number of pending transfers. Used between interrupt handler
  * and tasklet.
  * @busy: Set to true when transfer is ongoing on this channel.
@@ -256,6 +184,7 @@ struct d40_base;
  * @src_def_cfg: Default cfg register setting for src.
  * @dst_def_cfg: Default cfg register setting for dst.
  * @log_def: Default logical channel settings.
+ * @lcla: Space for one dst src pair for logical channel transfers.
  * @lcpa: Pointer to dst and src lcpa settings.
  * @runtime_addr: runtime configured address.
  * @runtime_direction: runtime configured direction.
@@ -265,6 +194,8 @@ struct d40_base;
 struct d40_chan {
         spinlock_t                       lock;
         int                              log_num;
+        /* ID of the most recent completed transfer */
+        int                              completed;
         int                              pending_tx;
         bool                             busy;
         struct d40_phy_res              *phy_chan;
@@ -285,7 +216,7 @@ struct d40_chan {
         struct d40_log_lli_full         *lcpa;
         /* Runtime reconfiguration */
         dma_addr_t                      runtime_addr;
-        enum dma_transfer_direction     runtime_direction;
+        enum dma_data_direction         runtime_direction;
 };
 
 /**
@@ -309,7 +240,6 @@ struct d40_chan {
  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
  * @dma_slave: dma_device channels that can do only do slave transfers.
  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
- * @phy_chans: Room for all possible physical channels in system.
  * @log_chans: Room for all possible logical channels in system.
  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
  * to log_chans entries.
@@ -317,20 +247,12 @@ struct d40_chan {
  * to phy_chans entries.
  * @plat_data: Pointer to provided platform_data which is the driver
  * configuration.
- * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
  * @phy_res: Vector containing all physical channels.
  * @lcla_pool: lcla pool settings and data.
  * @lcpa_base: The virtual mapped address of LCPA.
  * @phy_lcpa: The physical address of the LCPA.
  * @lcpa_size: The size of the LCPA area.
  * @desc_slab: cache for descriptors.
- * @reg_val_backup: Here the values of some hardware registers are stored
- * before the DMA is powered off. They are restored when the power is back on.
- * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
- * later.
- * @reg_val_backup_chan: Backup data for standard channel parameter registers.
- * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
- * @initialized: true if the dma has been initialized
  */
 struct d40_base {
         spinlock_t                       interrupt_lock;
@@ -352,7 +274,6 @@ struct d40_base {
         struct d40_chan                 **lookup_log_chans;
         struct d40_chan                 **lookup_phy_chans;
         struct stedma40_platform_data    *plat_data;
-        struct regulator                 *lcpa_regulator;
         /* Physical half channels */
         struct d40_phy_res               *phy_res;
         struct d40_lcla_pool              lcla_pool;
@@ -360,11 +281,6 @@ struct d40_base {
         dma_addr_t                        phy_lcpa;
         resource_size_t                   lcpa_size;
         struct kmem_cache                *desc_slab;
-        u32                               reg_val_backup[BACKUP_REGS_SZ];
-        u32                               reg_val_backup_v3[BACKUP_REGS_SZ_V3];
-        u32                              *reg_val_backup_chan;
-        u16                               gcc_pwr_off_mask;
-        bool                              initialized;
 };
 
 /**
@@ -562,14 +478,13 @@ static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
                 struct d40_desc *d;
                 struct d40_desc *_d;
 
-                list_for_each_entry_safe(d, _d, &d40c->client, node) {
+                list_for_each_entry_safe(d, _d, &d40c->client, node)
                         if (async_tx_test_ack(&d->txd)) {
                                 d40_desc_remove(d);
                                 desc = d;
                                 memset(desc, 0, sizeof(*desc));
                                 break;
                         }
-                }
         }
 
         if (!desc)
@@ -620,7 +535,6 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
         bool cyclic = desc->cyclic;
         int curr_lcla = -EINVAL;
         int first_lcla = 0;
-        bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
         bool linkback;
 
         /*
@@ -693,16 +607,11 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
                                        &lli->src[lli_current],
                                        next_lcla, flags);
 
-                /*
-                 * Cache maintenance is not needed if lcla is
-                 * mapped in esram
-                 */
-                if (!use_esram_lcla) {
-                        dma_sync_single_range_for_device(chan->base->dev,
-                                                pool->dma_addr, lcla_offset,
-                                                2 * sizeof(struct d40_log_lli),
-                                                DMA_TO_DEVICE);
-                }
+                dma_sync_single_range_for_device(chan->base->dev,
+                                        pool->dma_addr, lcla_offset,
+                                        2 * sizeof(struct d40_log_lli),
+                                        DMA_TO_DEVICE);
+
                 curr_lcla = next_lcla;
 
                 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
@@ -830,64 +739,10 @@ static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
         return len;
 }
 
+/* Support functions for logical channels */
 
-#ifdef CONFIG_PM
-static void dma40_backup(void __iomem *baseaddr, u32 *backup,
-                         u32 *regaddr, int num, bool save)
-{
-        int i;
-
-        for (i = 0; i < num; i++) {
-                void __iomem *addr = baseaddr + regaddr[i];
-
-                if (save)
-                        backup[i] = readl_relaxed(addr);
-                else
-                        writel_relaxed(backup[i], addr);
-        }
-}
-
-static void d40_save_restore_registers(struct d40_base *base, bool save)
-{
-        int i;
-
-        /* Save/Restore channel specific registers */
-        for (i = 0; i < base->num_phy_chans; i++) {
-                void __iomem *addr;
-                int idx;
-
-                if (base->phy_res[i].reserved)
-                        continue;
-
-                addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
-                idx = i * ARRAY_SIZE(d40_backup_regs_chan);
-
-                dma40_backup(addr, &base->reg_val_backup_chan[idx],
-                             d40_backup_regs_chan,
-                             ARRAY_SIZE(d40_backup_regs_chan),
-                             save);
-        }
-
-        /* Save/Restore global registers */
-        dma40_backup(base->virtbase, base->reg_val_backup,
-                     d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
-                     save);
-
-        /* Save/Restore registers only existing on dma40 v3 and later */
-        if (base->rev >= 3)
-                dma40_backup(base->virtbase, base->reg_val_backup_v3,
-                             d40_backup_regs_v3,
-                             ARRAY_SIZE(d40_backup_regs_v3),
-                             save);
-}
-#else
-static void d40_save_restore_registers(struct d40_base *base, bool save)
-{
-}
-#endif
-
-static int __d40_execute_command_phy(struct d40_chan *d40c,
-                                     enum d40_command command)
+static int d40_channel_execute_command(struct d40_chan *d40c,
+                                       enum d40_command command)
 {
         u32 status;
         int i;
@@ -896,12 +751,6 @@ static int __d40_execute_command_phy(struct d40_chan *d40c,
         unsigned long flags;
         u32 wmask;
 
-        if (command == D40_DMA_STOP) {
-                ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
-                if (ret)
-                        return ret;
-        }
-
         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
 
         if (d40c->phy_chan->num % 2 == 0)
@@ -995,109 +844,67 @@ static void d40_term_all(struct d40_chan *d40c)
                 }
 
         d40c->pending_tx = 0;
+        d40c->busy = false;
 }
 
-static void __d40_config_set_event(struct d40_chan *d40c,
-                                   enum d40_events event_type, u32 event,
-                                   int reg)
+static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
+                                   u32 event, int reg)
 {
         void __iomem *addr = chan_base(d40c) + reg;
         int tries;
-        u32 status;
-
-        switch (event_type) {
-
-        case D40_DEACTIVATE_EVENTLINE:
 
+        if (!enable) {
                 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
                        | ~D40_EVENTLINE_MASK(event), addr);
-                break;
-
-        case D40_SUSPEND_REQ_EVENTLINE:
-                status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
-                          D40_EVENTLINE_POS(event);
-
-                if (status == D40_DEACTIVATE_EVENTLINE ||
-                    status == D40_SUSPEND_REQ_EVENTLINE)
-                        break;
-
-                writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
-                       | ~D40_EVENTLINE_MASK(event), addr);
-
-                for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
-
-                        status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
-                                  D40_EVENTLINE_POS(event);
-
-                        cpu_relax();
-                        /*
-                         * Reduce the number of bus accesses while
-                         * waiting for the DMA to suspend.
-                         */
-                        udelay(3);
-
-                        if (status == D40_DEACTIVATE_EVENTLINE)
-                                break;
-                }
-
-                if (tries == D40_SUSPEND_MAX_IT) {
-                        chan_err(d40c,
-                                "unable to stop the event_line chl %d (log: %d)"
-                                "status %x\n", d40c->phy_chan->num,
-                                 d40c->log_num, status);
-                }
-                break;
+                return;
+        }
 
-        case D40_ACTIVATE_EVENTLINE:
         /*
          * The hardware sometimes doesn't register the enable when src and dst
          * event lines are active on the same logical channel.  Retry to ensure
          * it does.  Usually only one retry is sufficient.
          */
-                tries = 100;
-                while (--tries) {
-                        writel((D40_ACTIVATE_EVENTLINE <<
-                                D40_EVENTLINE_POS(event)) |
-                                ~D40_EVENTLINE_MASK(event), addr);
-
-                        if (readl(addr) & D40_EVENTLINE_MASK(event))
-                                break;
-                }
-
-                if (tries != 99)
-                        dev_dbg(chan2dev(d40c),
-                                "[%s] workaround enable S%cLNK (%d tries)\n",
-                                __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
-                                100 - tries);
+        tries = 100;
+        while (--tries) {
+                writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
+                       | ~D40_EVENTLINE_MASK(event), addr);
 
-                WARN_ON(!tries);
-                break;
+                if (readl(addr) & D40_EVENTLINE_MASK(event))
+                        break;
+        }
 
-        case D40_ROUND_EVENTLINE:
-                BUG();
-                break;
+        if (tries != 99)
+                dev_dbg(chan2dev(d40c),
+                        "[%s] workaround enable S%cLNK (%d tries)\n",
+                        __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
+                        100 - tries);
 
-        }
+        WARN_ON(!tries);
 }
 
-static void d40_config_set_event(struct d40_chan *d40c,
-                                 enum d40_events event_type)
+static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
 {
+        unsigned long flags;
+
+        spin_lock_irqsave(&d40c->phy_chan->lock, flags);
+
         /* Enable event line connected to device (or memcpy) */
         if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
             (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
 
-                __d40_config_set_event(d40c, event_type, event,
+                __d40_config_set_event(d40c, do_enable, event,
                                        D40_CHAN_REG_SSLNK);
         }
 
         if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
 
-                __d40_config_set_event(d40c, event_type, event,
+                __d40_config_set_event(d40c, do_enable, event,
                                        D40_CHAN_REG_SDLNK);
         }
+
+        spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
 }
 
 static u32 d40_chan_has_events(struct d40_chan *d40c)
@@ -1111,64 +918,6 @@ static u32 d40_chan_has_events(struct d40_chan *d40c)
         return val;
 }
 
-static int
-__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
-{
-        unsigned long flags;
-        int ret = 0;
-        u32 active_status;
-        void __iomem *active_reg;
-
-        if (d40c->phy_chan->num % 2 == 0)
-                active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
-        else
-                active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
-
-
-        spin_lock_irqsave(&d40c->phy_chan->lock, flags);
-
-        switch (command) {
-        case D40_DMA_STOP:
-        case D40_DMA_SUSPEND_REQ:
-
-                active_status = (readl(active_reg) &
-                                 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
-                                 D40_CHAN_POS(d40c->phy_chan->num);
-
-                if (active_status == D40_DMA_RUN)
-                        d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
-                else
-                        d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
-
-                if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
-                        ret = __d40_execute_command_phy(d40c, command);
-
-                break;
-
-        case D40_DMA_RUN:
-
-                d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
-                ret = __d40_execute_command_phy(d40c, command);
-                break;
-
-        case D40_DMA_SUSPENDED:
-                BUG();
-                break;
-        }
-
-        spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
-        return ret;
-}
-
-static int d40_channel_execute_command(struct d40_chan *d40c,
-                                       enum d40_command command)
-{
-        if (chan_is_logical(d40c))
-                return __d40_execute_command_log(d40c, command);
-        else
-                return __d40_execute_command_phy(d40c, command);
-}
-
 static u32 d40_get_prmo(struct d40_chan *d40c)
 {
         static const unsigned int phy_map[] = {
@@ -1223,10 +972,6 @@ static void d40_config_write(struct d40_chan *d40c)
                 /* Set LIDX for lcla */
                 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
                 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
-
-                /* Clear LNK which will be used by d40_chan_has_events() */
-                writel(0, chanbase + D40_CHAN_REG_SSLNK);
-                writel(0, chanbase + D40_CHAN_REG_SDLNK);
         }
 }
 
@@ -1267,13 +1012,19 @@ static int d40_pause(struct d40_chan *d40c)
         if (!d40c->busy)
                 return 0;
 
-        pm_runtime_get_sync(d40c->base->dev);
         spin_lock_irqsave(&d40c->lock, flags);
 
         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
+        if (res == 0) {
+                if (chan_is_logical(d40c)) {
+                        d40_config_set_event(d40c, false);
+                        /* Resume the other logical channels if any */
+                        if (d40_chan_has_events(d40c))
+                                res = d40_channel_execute_command(d40c,
+                                                                  D40_DMA_RUN);
+                }
+        }
 
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
         spin_unlock_irqrestore(&d40c->lock, flags);
         return res;
 }
@@ -1287,18 +1038,44 @@ static int d40_resume(struct d40_chan *d40c)
                 return 0;
 
         spin_lock_irqsave(&d40c->lock, flags);
-        pm_runtime_get_sync(d40c->base->dev);
+
+        if (d40c->base->rev == 0)
+                if (chan_is_logical(d40c)) {
+                        res = d40_channel_execute_command(d40c,
+                                                          D40_DMA_SUSPEND_REQ);
+                        goto no_suspend;
+                }
 
         /* If bytes left to transfer or linked tx resume job */
-        if (d40_residue(d40c) || d40_tx_is_linked(d40c))
+        if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
+
+                if (chan_is_logical(d40c))
+                        d40_config_set_event(d40c, true);
+
                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
+        }
 
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
+no_suspend:
         spin_unlock_irqrestore(&d40c->lock, flags);
         return res;
 }
 
+static int d40_terminate_all(struct d40_chan *chan)
+{
+        unsigned long flags;
+        int ret = 0;
+
+        ret = d40_pause(chan);
+        if (!ret && chan_is_physical(chan))
+                ret = d40_channel_execute_command(chan, D40_DMA_STOP);
+
+        spin_lock_irqsave(&chan->lock, flags);
+        d40_term_all(chan);
+        spin_unlock_irqrestore(&chan->lock, flags);
+
+        return ret;
+}
+
 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 {
         struct d40_chan *d40c = container_of(tx->chan,
@@ -1306,18 +1083,39 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
                                              chan);
         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
         unsigned long flags;
-        dma_cookie_t cookie;
 
         spin_lock_irqsave(&d40c->lock, flags);
-        cookie = dma_cookie_assign(tx);
+
+        d40c->chan.cookie++;
+
+        if (d40c->chan.cookie < 0)
+                d40c->chan.cookie = 1;
+
+        d40d->txd.cookie = d40c->chan.cookie;
+
         d40_desc_queue(d40c, d40d);
+
         spin_unlock_irqrestore(&d40c->lock, flags);
 
-        return cookie;
+        return tx->cookie;
 }
 
 static int d40_start(struct d40_chan *d40c)
 {
+        if (d40c->base->rev == 0) {
+                int err;
+
+                if (chan_is_logical(d40c)) {
+                        err = d40_channel_execute_command(d40c,
+                                                          D40_DMA_SUSPEND_REQ);
+                        if (err)
+                                return err;
+                }
+        }
+
+        if (chan_is_logical(d40c))
+                d40_config_set_event(d40c, true);
+
         return d40_channel_execute_command(d40c, D40_DMA_RUN);
 }
 
@@ -1330,10 +1128,7 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
         d40d = d40_first_queued(d40c);
 
         if (d40d != NULL) {
-                if (!d40c->busy) {
-                        d40c->busy = true;
-                        pm_runtime_get_sync(d40c->base->dev);
-                }
+                d40c->busy = true;
 
                 /* Remove from queue */
                 d40_desc_remove(d40d);
@@ -1394,8 +1189,6 @@ static void dma_tc_handle(struct d40_chan *d40c)
 
                 if (d40_queue_start(d40c) == NULL)
                         d40c->busy = false;
-                pm_runtime_mark_last_busy(d40c->base->dev);
-                pm_runtime_put_autosuspend(d40c->base->dev);
         }
 
         d40c->pending_tx++;
@@ -1419,7 +1212,7 @@ static void dma_tasklet(unsigned long data)
                 goto err;
 
         if (!d40d->cyclic)
-                dma_cookie_complete(&d40d->txd);
+                d40c->completed = d40d->txd.cookie;
 
         /*
          * If terminating a channel pending_tx is set to zero.
@@ -1460,8 +1253,8 @@ static void dma_tasklet(unsigned long data)
 
         return;
 
-err:
-        /* Rescue manouver if receiving double interrupts */
+ err:
+        /* Rescue manoeuvre if receiving double interrupts */
         if (d40c->pending_tx > 0)
                 d40c->pending_tx--;
         spin_unlock_irqrestore(&d40c->lock, flags);
@@ -1611,16 +1404,11 @@ static int d40_validate_conf(struct d40_chan *d40c,
         return res;
 }
 
-static bool d40_alloc_mask_set(struct d40_phy_res *phy,
-                               bool is_src, int log_event_line, bool is_log,
-                               bool *first_user)
+static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
+                               int log_event_line, bool is_log)
 {
         unsigned long flags;
         spin_lock_irqsave(&phy->lock, flags);
-
-        *first_user = ((phy->allocated_src | phy->allocated_dst)
-                        == D40_ALLOC_FREE);
-
         if (!is_log) {
                 /* Physical interrupts are masked per physical full channel */
                 if (phy->allocated_src == D40_ALLOC_FREE &&
@@ -1701,7 +1489,7 @@ out:
         return is_free;
 }
 
-static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
+static int d40_allocate_channel(struct d40_chan *d40c)
 {
         int dev_type;
         int event_group;
@@ -1737,8 +1525,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
                         for (i = 0; i < d40c->base->num_phy_chans; i++) {
 
                                 if (d40_alloc_mask_set(&phys[i], is_src,
-                                                       0, is_log,
-                                                       first_phy_user))
+                                                       0, is_log))
                                         goto found_phy;
                         }
                 } else
@@ -1748,8 +1535,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
                                         if (d40_alloc_mask_set(&phys[i],
                                                                is_src,
                                                                0,
-                                                               is_log,
-                                                               first_phy_user))
+                                                               is_log))
                                                 goto found_phy;
                                 }
                         }
@@ -1765,25 +1551,6 @@ found_phy:
         /* Find logical channel */
         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
                 int phy_num = j + event_group * 2;
-
-                if (d40c->dma_cfg.use_fixed_channel) {
-                        i = d40c->dma_cfg.phy_channel;
-
-                        if ((i != phy_num) && (i != phy_num + 1)) {
-                                dev_err(chan2dev(d40c),
-                                        "invalid fixed phy channel %d\n", i);
-                                return -EINVAL;
-                        }
-
-                        if (d40_alloc_mask_set(&phys[i], is_src, event_line,
-                                               is_log, first_phy_user))
-                                goto found_log;
-
-                        dev_err(chan2dev(d40c),
-                                "could not allocate fixed phy channel %d\n", i);
-                        return -EINVAL;
-                }
-
                 /*
                  * Spread logical channels across all available physical rather
                  * than pack every logical channel at the first available phy
@@ -1792,15 +1559,13 @@ found_phy:
                 if (is_src) {
                         for (i = phy_num; i < phy_num + 2; i++) {
                                 if (d40_alloc_mask_set(&phys[i], is_src,
-                                                       event_line, is_log,
-                                                       first_phy_user))
+                                                       event_line, is_log))
                                         goto found_log;
                         }
                 } else {
                         for (i = phy_num + 1; i >= phy_num; i--) {
                                 if (d40_alloc_mask_set(&phys[i], is_src,
-                                                       event_line, is_log,
-                                                       first_phy_user))
+                                                       event_line, is_log))
                                         goto found_log;
                         }
                 }
@@ -1842,6 +1607,7 @@ static int d40_config_memcpy(struct d40_chan *d40c)
         return 0;
 }
 
+
 static int d40_free_dma(struct d40_chan *d40c)
 {
 
@@ -1876,33 +1642,50 @@ static int d40_free_dma(struct d40_chan *d40c)
                 return -EINVAL;
         }
 
-        pm_runtime_get_sync(d40c->base->dev);
-        res = d40_channel_execute_command(d40c, D40_DMA_STOP);
+        res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
         if (res) {
-                chan_err(d40c, "stop failed\n");
-                goto out;
+                chan_err(d40c, "suspend failed\n");
+                return res;
         }
 
-        d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
+        if (chan_is_logical(d40c)) {
+                /* Release logical channel, deactivate the event line */
 
-        if (chan_is_logical(d40c))
+                d40_config_set_event(d40c, false);
                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
-        else
-                d40c->base->lookup_phy_chans[phy->num] = NULL;
 
-        if (d40c->busy) {
-                pm_runtime_mark_last_busy(d40c->base->dev);
-                pm_runtime_put_autosuspend(d40c->base->dev);
+                /*
+                 * Check if there are more logical allocation
+                 * on this phy channel.
+                 */
+                if (!d40_alloc_mask_free(phy, is_src, event)) {
+                        /* Resume the other logical channels if any */
+                        if (d40_chan_has_events(d40c)) {
+                                res = d40_channel_execute_command(d40c,
+                                                                  D40_DMA_RUN);
+                                if (res) {
+                                        chan_err(d40c,
+                                                "Executing RUN command\n");
+                                        return res;
+                                }
+                        }
+                        return 0;
+                }
+        } else {
+                (void) d40_alloc_mask_free(phy, is_src, 0);
         }
 
-        d40c->busy = false;
+        /* Release physical channel */
+        res = d40_channel_execute_command(d40c, D40_DMA_STOP);
+        if (res) {
+                chan_err(d40c, "Failed to stop channel\n");
+                return res;
+        }
         d40c->phy_chan = NULL;
         d40c->configured = false;
-out:
+        d40c->base->lookup_phy_chans[phy->num] = NULL;
 
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
-        return res;
+        return 0;
 }
 
 static bool d40_is_paused(struct d40_chan *d40c)
@@ -2071,7 +1854,7 @@ err:
 }
 
 static dma_addr_t
-d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
+d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
 {
         struct stedma40_platform_data *plat = chan->base->plat_data;
         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
@@ -2080,9 +1863,9 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
         if (chan->runtime_addr)
                 return chan->runtime_addr;
 
-        if (direction == DMA_DEV_TO_MEM)
+        if (direction == DMA_FROM_DEVICE)
                 addr = plat->dev_rx[cfg->src_dev_type];
-        else if (direction == DMA_MEM_TO_DEV)
+        else if (direction == DMA_TO_DEVICE)
                 addr = plat->dev_tx[cfg->dst_dev_type];
 
         return addr;
@@ -2091,7 +1874,7 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
 static struct dma_async_tx_descriptor *
 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
             struct scatterlist *sg_dst, unsigned int sg_len,
-            enum dma_transfer_direction direction, unsigned long dma_flags)
+            enum dma_data_direction direction, unsigned long dma_flags)
 {
         struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
         dma_addr_t src_dev_addr = 0;
@@ -2115,12 +1898,12 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
         if (sg_next(&sg_src[sg_len - 1]) == sg_src)
                 desc->cyclic = true;
 
-        if (direction != DMA_TRANS_NONE) {
+        if (direction != DMA_NONE) {
                 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
 
-                if (direction == DMA_DEV_TO_MEM)
+                if (direction == DMA_FROM_DEVICE)
                         src_dev_addr = dev_addr;
-                else if (direction == DMA_MEM_TO_DEV)
+                else if (direction == DMA_TO_DEVICE)
                         dst_dev_addr = dev_addr;
         }
 
@@ -2217,7 +2000,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
         bool is_free_phy;
         spin_lock_irqsave(&d40c->lock, flags);
 
-        dma_cookie_init(chan);
+        d40c->completed = chan->cookie = 1;
 
         /* If no dma configuration is set use default configuration (memcpy) */
         if (!d40c->configured) {
@@ -2227,15 +2010,14 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
                         goto fail;
                 }
         }
+        is_free_phy = (d40c->phy_chan == NULL);
 
-        err = d40_allocate_channel(d40c, &is_free_phy);
+        err = d40_allocate_channel(d40c);
         if (err) {
                 chan_err(d40c, "Failed to allocate channel\n");
-                d40c->configured = false;
                 goto fail;
         }
 
-        pm_runtime_get_sync(d40c->base->dev);
         /* Fill in basic CFG register values */
         d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
                     &d40c->dst_def_cfg, chan_is_logical(d40c));
@@ -2255,12 +2037,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
                           D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
         }
 
-        dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
-                 chan_is_logical(d40c) ? "logical" : "physical",
-                 d40c->phy_chan->num,
-                 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
-
-
         /*
          * Only write channel configuration to the DMA if the physical
          * resource is free. In case of multiple logical channels
@@ -2269,8 +2045,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
         if (is_free_phy)
                 d40_config_write(d40c);
 fail:
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
         spin_unlock_irqrestore(&d40c->lock, flags);
         return err;
 }
@@ -2333,11 +2107,10 @@ d40_prep_memcpy_sg(struct dma_chan *chan,
 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
                                                          struct scatterlist *sgl,
                                                          unsigned int sg_len,
-                                                         enum dma_transfer_direction direction,
-                                                         unsigned long dma_flags,
-                                                         void *context)
+                                                         enum dma_data_direction direction,
+                                                         unsigned long dma_flags)
 {
-        if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
+        if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE)
                 return NULL;
 
         return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
@@ -2346,8 +2119,7 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
 static struct dma_async_tx_descriptor *
 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
                      size_t buf_len, size_t period_len,
-                     enum dma_transfer_direction direction, unsigned long flags,
-                     void *context)
+                     enum dma_data_direction direction)
 {
         unsigned int periods = buf_len / period_len;
         struct dma_async_tx_descriptor *txd;
@@ -2362,7 +2134,7 @@ dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
         }
 
         sg[periods].offset = 0;
-        sg_dma_len(&sg[periods]) = 0;
+        sg[periods].length = 0;
         sg[periods].page_link =
                 ((unsigned long)sg | 0x01) & ~0x02;
 
@@ -2379,19 +2151,25 @@ static enum dma_status d40_tx_status(struct dma_chan *chan,
                                      struct dma_tx_state *txstate)
 {
         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
-        enum dma_status ret;
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
+        int ret;
 
         if (d40c->phy_chan == NULL) {
                 chan_err(d40c, "Cannot read status of unallocated channel\n");
                 return -EINVAL;
         }
 
-        ret = dma_cookie_status(chan, cookie, txstate);
-        if (ret != DMA_SUCCESS)
-                dma_set_residue(txstate, stedma40_residue(chan));
+        last_complete = d40c->completed;
+        last_used = chan->cookie;
 
         if (d40_is_paused(d40c))
                 ret = DMA_PAUSED;
+        else
+                ret = dma_async_is_complete(cookie, last_complete, last_used);
+
+        dma_set_tx_state(txstate, last_complete, last_used,
+                         stedma40_residue(chan));
 
         return ret;
 }
@@ -2417,31 +2195,6 @@ static void d40_issue_pending(struct dma_chan *chan)
         spin_unlock_irqrestore(&d40c->lock, flags);
 }
 
-static void d40_terminate_all(struct dma_chan *chan)
-{
-        unsigned long flags;
-        struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
-        int ret;
-
-        spin_lock_irqsave(&d40c->lock, flags);
-
-        pm_runtime_get_sync(d40c->base->dev);
-        ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
-        if (ret)
-                chan_err(d40c, "Failed to stop channel\n");
-
-        d40_term_all(d40c);
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
-        if (d40c->busy) {
-                pm_runtime_mark_last_busy(d40c->base->dev);
-                pm_runtime_put_autosuspend(d40c->base->dev);
-        }
-        d40c->busy = false;
-
-        spin_unlock_irqrestore(&d40c->lock, flags);
-}
-
 static int
 dma40_config_to_halfchannel(struct d40_chan *d40c,
                             struct stedma40_half_channel_info *info,
@@ -2515,7 +2268,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
         dst_addr_width = config->dst_addr_width;
         dst_maxburst = config->dst_maxburst;
 
-        if (config->direction == DMA_DEV_TO_MEM) {
+        if (config->direction == DMA_FROM_DEVICE) {
                 dma_addr_t dev_addr_rx =
                         d40c->base->plat_data->dev_rx[cfg->src_dev_type];
 
@@ -2538,7 +2291,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
                 if (dst_maxburst == 0)
                         dst_maxburst = src_maxburst;
 
-        } else if (config->direction == DMA_MEM_TO_DEV) {
+        } else if (config->direction == DMA_TO_DEVICE) {
                 dma_addr_t dev_addr_tx =
                         d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
 
@@ -2603,7 +2356,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
                 "configured channel %s for %s, data width %d/%d, "
                 "maxburst %d/%d elements, LE, no flow control\n",
                 dma_chan_name(chan),
-                (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
+                (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
                 src_addr_width, dst_addr_width,
                 src_maxburst, dst_maxburst);
 
@@ -2622,8 +2375,7 @@ static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
         switch (cmd) {
         case DMA_TERMINATE_ALL:
-                d40_terminate_all(chan);
-                return 0;
+                return d40_terminate_all(d40c);
         case DMA_PAUSE:
                 return d40_pause(d40c);
         case DMA_RESUME:
@@ -2766,72 +2518,6 @@ failure1:
         return err;
 }
 
-/* Suspend resume functionality */
-#ifdef CONFIG_PM
-static int dma40_pm_suspend(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct d40_base *base = platform_get_drvdata(pdev);
-        int ret = 0;
-        if (!pm_runtime_suspended(dev))
-                return -EBUSY;
-
-        if (base->lcpa_regulator)
-                ret = regulator_disable(base->lcpa_regulator);
-        return ret;
-}
-
-static int dma40_runtime_suspend(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct d40_base *base = platform_get_drvdata(pdev);
-
-        d40_save_restore_registers(base, true);
-
-        /* Don't disable/enable clocks for v1 due to HW bugs */
-        if (base->rev != 1)
-                writel_relaxed(base->gcc_pwr_off_mask,
-                               base->virtbase + D40_DREG_GCC);
-
-        return 0;
-}
-
-static int dma40_runtime_resume(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct d40_base *base = platform_get_drvdata(pdev);
-
-        if (base->initialized)
-                d40_save_restore_registers(base, false);
-
-        writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
-                       base->virtbase + D40_DREG_GCC);
-        return 0;
-}
-
-static int dma40_resume(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct d40_base *base = platform_get_drvdata(pdev);
-        int ret = 0;
-
-        if (base->lcpa_regulator)
-                ret = regulator_enable(base->lcpa_regulator);
-
-        return ret;
-}
-
-static const struct dev_pm_ops dma40_pm_ops = {
-        .suspend                = dma40_pm_suspend,
-        .runtime_suspend        = dma40_runtime_suspend,
-        .runtime_resume         = dma40_runtime_resume,
-        .resume                 = dma40_resume,
-};
-#define DMA40_PM_OPS    (&dma40_pm_ops)
-#else
-#define DMA40_PM_OPS    NULL
-#endif
-
 /* Initialization functions. */
 
 static int __init d40_phy_res_init(struct d40_base *base)
@@ -2840,7 +2526,6 @@ static int __init d40_phy_res_init(struct d40_base *base)
         int num_phy_chans_avail = 0;
         u32 val[2];
         int odd_even_bit = -2;
-        int gcc = D40_DREG_GCC_ENA;
 
         val[0] = readl(base->virtbase + D40_DREG_PRSME);
         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
@@ -2852,17 +2537,9 @@ static int __init d40_phy_res_init(struct d40_base *base)
                         /* Mark security only channels as occupied */
                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
-                        base->phy_res[i].reserved = true;
-                        gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
-                                                       D40_DREG_GCC_SRC);
-                        gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
-                                                       D40_DREG_GCC_DST);
-
-
                 } else {
                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
-                        base->phy_res[i].reserved = false;
                         num_phy_chans_avail++;
                 }
                 spin_lock_init(&base->phy_res[i].lock);
@@ -2874,11 +2551,6 @@ static int __init d40_phy_res_init(struct d40_base *base)
 
                 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
                 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
-                base->phy_res[chan].reserved = true;
-                gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
-                                               D40_DREG_GCC_SRC);
-                gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
-                                               D40_DREG_GCC_DST);
                 num_phy_chans_avail--;
         }
 
@@ -2899,15 +2571,6 @@ static int __init d40_phy_res_init(struct d40_base *base)
                 val[0] = val[0] >> 2;
         }
 
-        /*
-         * To keep things simple, Enable all clocks initially.
-         * The clocks will get managed later post channel allocation.
-         * The clocks for the event lines on which reserved channels exists
-         * are not managed here.
-         */
-        writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
-        base->gcc_pwr_off_mask = gcc;
-
         return num_phy_chans_avail;
 }
 
@@ -2920,23 +2583,19 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
         struct d40_base *base = NULL;
         int num_log_chans = 0;
         int num_phy_chans;
-        int clk_ret = -EINVAL;
         int i;
         u32 pid;
         u32 cid;
         u8 rev;
 
         clk = clk_get(&pdev->dev, NULL);
+
         if (IS_ERR(clk)) {
                 d40_err(&pdev->dev, "No matching clock found\n");
                 goto failure;
         }
 
-        clk_ret = clk_prepare_enable(clk);
-        if (clk_ret) {
-                d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
-                goto failure;
-        }
+        clk_enable(clk);
 
         /* Get IO for DMAC base address */
         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
@@ -2984,12 +2643,6 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
         dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
                  rev, res->start);
 
-        if (rev < 2) {
-                d40_err(&pdev->dev, "hardware revision: %d is not supported",
-                        rev);
-                goto failure;
-        }
-
         plat_data = pdev->dev.platform_data;
 
         /* Count the number of logical channels in use */
@@ -3045,15 +2698,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
                         goto failure;
         }
 
-        base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
-                                            sizeof(d40_backup_regs_chan),
+        base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
+                                            sizeof(struct d40_desc *) *
+                                            D40_LCLA_LINK_PER_EVENT_GRP,
                                             GFP_KERNEL);
-        if (!base->reg_val_backup_chan)
-                goto failure;
-
-        base->lcla_pool.alloc_map =
-                kzalloc(num_phy_chans * sizeof(struct d40_desc *)
-                        * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
         if (!base->lcla_pool.alloc_map)
                 goto failure;
 
@@ -3066,10 +2714,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
         return base;
 
 failure:
-        if (!clk_ret)
-                clk_disable_unprepare(clk);
-        if (!IS_ERR(clk))
+        if (!IS_ERR(clk)) {
+                clk_disable(clk);
                 clk_put(clk);
+        }
         if (virtbase)
                 iounmap(virtbase);
         if (res)
@@ -3080,7 +2728,6 @@ failure:
 
         if (base) {
                 kfree(base->lcla_pool.alloc_map);
-                kfree(base->reg_val_backup_chan);
                 kfree(base->lookup_log_chans);
                 kfree(base->lookup_phy_chans);
                 kfree(base->phy_res);
@@ -3093,9 +2740,9 @@ failure:
 static void __init d40_hw_init(struct d40_base *base)
 {
 
-        static struct d40_reg_val dma_init_reg[] = {
+        static const struct d40_reg_val dma_init_reg[] = {
                 /* Clock every part of the DMA block from start */
-                { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
+                { .reg = D40_DREG_GCC,    .val = 0x0000ff01},
 
                 /* Interrupts on all logical channels */
                 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
@@ -3295,31 +2942,11 @@ static int __init d40_probe(struct platform_device *pdev)
                 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
                 goto failure;
         }
-        /* If lcla has to be located in ESRAM we don't need to allocate */
-        if (base->plat_data->use_esram_lcla) {
-                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-                                                        "lcla_esram");
-                if (!res) {
-                        ret = -ENOENT;
-                        d40_err(&pdev->dev,
-                                "No \"lcla_esram\" memory resource\n");
-                        goto failure;
-                }
-                base->lcla_pool.base = ioremap(res->start,
-                                                resource_size(res));
-                if (!base->lcla_pool.base) {
-                        ret = -ENOMEM;
-                        d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
-                        goto failure;
-                }
-                writel(res->start, base->virtbase + D40_DREG_LCLA);
 
-        } else {
-                ret = d40_lcla_allocate(base);
-                if (ret) {
-                        d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
-                        goto failure;
-                }
+        ret = d40_lcla_allocate(base);
+        if (ret) {
+                d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
+                goto failure;
         }
 
         spin_lock_init(&base->lcla_pool.lock);
@@ -3332,32 +2959,6 @@ static int __init d40_probe(struct platform_device *pdev)
                 goto failure;
         }
 
-        pm_runtime_irq_safe(base->dev);
-        pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
-        pm_runtime_use_autosuspend(base->dev);
-        pm_runtime_enable(base->dev);
-        pm_runtime_resume(base->dev);
-
-        if (base->plat_data->use_esram_lcla) {
-
-                base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
-                if (IS_ERR(base->lcpa_regulator)) {
-                        d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
-                        base->lcpa_regulator = NULL;
-                        goto failure;
-                }
-
-                ret = regulator_enable(base->lcpa_regulator);
-                if (ret) {
-                        d40_err(&pdev->dev,
-                                "Failed to enable lcpa_regulator\n");
-                        regulator_put(base->lcpa_regulator);
-                        base->lcpa_regulator = NULL;
-                        goto failure;
-                }
-        }
-
-        base->initialized = true;
         err = d40_dmaengine_init(base, num_reserved_chans);
         if (err)
                 goto failure;
@@ -3374,11 +2975,6 @@ failure:
                 if (base->virtbase)
                         iounmap(base->virtbase);
 
-                if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
-                        iounmap(base->lcla_pool.base);
-                        base->lcla_pool.base = NULL;
-                }
-
                 if (base->lcla_pool.dma_addr)
                         dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
                                          SZ_1K * base->num_phy_chans,
@@ -3401,11 +2997,6 @@ failure:
                         clk_put(base->clk);
                 }
 
-                if (base->lcpa_regulator) {
-                        regulator_disable(base->lcpa_regulator);
-                        regulator_put(base->lcpa_regulator);
-                }
-
                 kfree(base->lcla_pool.alloc_map);
                 kfree(base->lookup_log_chans);
                 kfree(base->lookup_phy_chans);
@@ -3421,7 +3012,6 @@ static struct platform_driver d40_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name  = D40_NAME,
-                .pm = DMA40_PM_OPS,
         },
 };
 
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 851ad56e840..cad9e1daedf 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -6,7 +6,7 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/platform_data/dma-ste-dma40.h>
+#include <plat/ste_dma40.h>
 
 #include "ste_dma40_ll.h"
 
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index 6d47373f3f5..b44c455158d 100644
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -16,8 +16,6 @@
 
 #define D40_TYPE_TO_GROUP(type) (type / 16)
 #define D40_TYPE_TO_EVENT(type) (type % 16)
-#define D40_GROUP_SIZE 8
-#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
 
 /* Most bits of the CFG register are the same in log as in phy mode */
 #define D40_SREG_CFG_MST_POS            15
@@ -62,6 +60,8 @@
 #define D40_SREG_ELEM_LOG_LIDX_MASK     (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
 
 /* Link register */
+#define D40_DEACTIVATE_EVENTLINE        0x0
+#define D40_ACTIVATE_EVENTLINE          0x1
 #define D40_EVENTLINE_POS(i)            (2 * i)
 #define D40_EVENTLINE_MASK(i)           (0x3 << D40_EVENTLINE_POS(i))
 
@@ -123,15 +123,6 @@
 
 /* DMA Register Offsets */
 #define D40_DREG_GCC            0x000
-#define D40_DREG_GCC_ENA        0x1
-/* This assumes that there are only 4 event groups */
-#define D40_DREG_GCC_ENABLE_ALL 0xff01
-#define D40_DREG_GCC_EVTGRP_POS 8
-#define D40_DREG_GCC_SRC 0
-#define D40_DREG_GCC_DST 1
-#define D40_DREG_GCC_EVTGRP_ENA(x, y) \
-        (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
-
 #define D40_DREG_PRTYP          0x004
 #define D40_DREG_PRSME          0x008
 #define D40_DREG_PRSMO          0x00C
@@ -202,7 +193,7 @@
 /* LLI related structures */
 
 /**
- * struct d40_phy_lli - The basic configuration register for each physical
+ * struct d40_phy_lli - The basic configration register for each physical
  * channel.
  *
  * @reg_cfg: The configuration register.
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
deleted file mode 100644
index c39e61bc817..00000000000
--- a/drivers/dma/tegra20-apb-dma.c
+++ /dev/null
@@ -1,1429 +0,0 @@
-/*
- * DMA driver for Nvidia's Tegra20 APB DMA controller.
- *
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/dmaengine.h>
-#include <linux/dma-mapping.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
-#include <linux/slab.h>
-
-#include <mach/clk.h>
-#include "dmaengine.h"
-
-#define TEGRA_APBDMA_GENERAL                    0x0
-#define TEGRA_APBDMA_GENERAL_ENABLE             BIT(31)
-
-#define TEGRA_APBDMA_CONTROL                    0x010
-#define TEGRA_APBDMA_IRQ_MASK                   0x01c
-#define TEGRA_APBDMA_IRQ_MASK_SET               0x020
-
-/* CSR register */
-#define TEGRA_APBDMA_CHAN_CSR                   0x00
-#define TEGRA_APBDMA_CSR_ENB                    BIT(31)
-#define TEGRA_APBDMA_CSR_IE_EOC                 BIT(30)
-#define TEGRA_APBDMA_CSR_HOLD                   BIT(29)
-#define TEGRA_APBDMA_CSR_DIR                    BIT(28)
-#define TEGRA_APBDMA_CSR_ONCE                   BIT(27)
-#define TEGRA_APBDMA_CSR_FLOW                   BIT(21)
-#define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT          16
-#define TEGRA_APBDMA_CSR_WCOUNT_MASK            0xFFFC
-
-/* STATUS register */
-#define TEGRA_APBDMA_CHAN_STATUS                0x004
-#define TEGRA_APBDMA_STATUS_BUSY                BIT(31)
-#define TEGRA_APBDMA_STATUS_ISE_EOC             BIT(30)
-#define TEGRA_APBDMA_STATUS_HALT                BIT(29)
-#define TEGRA_APBDMA_STATUS_PING_PONG           BIT(28)
-#define TEGRA_APBDMA_STATUS_COUNT_SHIFT         2
-#define TEGRA_APBDMA_STATUS_COUNT_MASK          0xFFFC
-
-/* AHB memory address */
-#define TEGRA_APBDMA_CHAN_AHBPTR                0x010
-
-/* AHB sequence register */
-#define TEGRA_APBDMA_CHAN_AHBSEQ                0x14
-#define TEGRA_APBDMA_AHBSEQ_INTR_ENB            BIT(31)
-#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8         (0 << 28)
-#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16        (1 << 28)
-#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32        (2 << 28)
-#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64        (3 << 28)
-#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128       (4 << 28)
-#define TEGRA_APBDMA_AHBSEQ_DATA_SWAP           BIT(27)
-#define TEGRA_APBDMA_AHBSEQ_BURST_1             (4 << 24)
-#define TEGRA_APBDMA_AHBSEQ_BURST_4             (5 << 24)
-#define TEGRA_APBDMA_AHBSEQ_BURST_8             (6 << 24)
-#define TEGRA_APBDMA_AHBSEQ_DBL_BUF             BIT(19)
-#define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT          16
-#define TEGRA_APBDMA_AHBSEQ_WRAP_NONE           0
-
-/* APB address */
-#define TEGRA_APBDMA_CHAN_APBPTR                0x018
-
-/* APB sequence register */
-#define TEGRA_APBDMA_CHAN_APBSEQ                0x01c
-#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8         (0 << 28)
-#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16        (1 << 28)
-#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32        (2 << 28)
-#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64        (3 << 28)
-#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128       (4 << 28)
-#define TEGRA_APBDMA_APBSEQ_DATA_SWAP           BIT(27)
-#define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1         (1 << 16)
-
-/*
- * If any burst is in flight and DMA paused then this is the time to complete
- * on-flight burst and update DMA status register.
- */
-#define TEGRA_APBDMA_BURST_COMPLETE_TIME        20
-
-/* Channel base address offset from APBDMA base address */
-#define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET    0x1000
-
-/* DMA channel register space size */
-#define TEGRA_APBDMA_CHANNEL_REGISTER_SIZE      0x20
-
-struct tegra_dma;
-
-/*
- * tegra_dma_chip_data Tegra chip specific DMA data
- * @nr_channels: Number of channels available in the controller.
- * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
- */
-struct tegra_dma_chip_data {
-        int nr_channels;
-        int max_dma_count;
-};
-
-/* DMA channel registers */
-struct tegra_dma_channel_regs {
-        unsigned long   csr;
-        unsigned long   ahb_ptr;
-        unsigned long   apb_ptr;
-        unsigned long   ahb_seq;
-        unsigned long   apb_seq;
-};
-
-/*
- * tegra_dma_sg_req: Dma request details to configure hardware. This
- * contains the details for one transfer to configure DMA hw.
- * The client's request for data transfer can be broken into multiple
- * sub-transfer as per requester details and hw support.
- * This sub transfer get added in the list of transfer and point to Tegra
- * DMA descriptor which manages the transfer details.
- */
-struct tegra_dma_sg_req {
-        struct tegra_dma_channel_regs   ch_regs;
-        int                             req_len;
-        bool                            configured;
-        bool                            last_sg;
-        bool                            half_done;
-        struct list_head                node;
-        struct tegra_dma_desc           *dma_desc;
-};
-
-/*
- * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
- * This descriptor keep track of transfer status, callbacks and request
- * counts etc.
- */
-struct tegra_dma_desc {
-        struct dma_async_tx_descriptor  txd;
-        int                             bytes_requested;
-        int                             bytes_transferred;
-        enum dma_status                 dma_status;
-        struct list_head                node;
-        struct list_head                tx_list;
-        struct list_head                cb_node;
-        int                             cb_count;
-};
-
-struct tegra_dma_channel;
-
-typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
-                                bool to_terminate);
-
-/* tegra_dma_channel: Channel specific information */
-struct tegra_dma_channel {
-        struct dma_chan         dma_chan;
-        char                    name[30];
-        bool                    config_init;
-        int                     id;
-        int                     irq;
-        unsigned long           chan_base_offset;
-        spinlock_t              lock;
-        bool                    busy;
-        struct tegra_dma        *tdma;
-        bool                    cyclic;
-
-        /* Different lists for managing the requests */
-        struct list_head        free_sg_req;
-        struct list_head        pending_sg_req;
-        struct list_head        free_dma_desc;
-        struct list_head        cb_desc;
-
-        /* ISR handler and tasklet for bottom half of isr handling */
-        dma_isr_handler         isr_handler;
-        struct tasklet_struct   tasklet;
-        dma_async_tx_callback   callback;
-        void                    *callback_param;
-
-        /* Channel-slave specific configuration */
-        struct dma_slave_config dma_sconfig;
-};
-
-/* tegra_dma: Tegra DMA specific information */
-struct tegra_dma {
-        struct dma_device               dma_dev;
-        struct device                   *dev;
-        struct clk                      *dma_clk;
-        spinlock_t                      global_lock;
-        void __iomem                    *base_addr;
-        const struct tegra_dma_chip_data *chip_data;
-
-        /* Some register need to be cache before suspend */
-        u32                             reg_gen;
-
-        /* Last member of the structure */
-        struct tegra_dma_channel channels[0];
-};
-
-static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
-{
-        writel(val, tdma->base_addr + reg);
-}
-
-static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
-{
-        return readl(tdma->base_addr + reg);
-}
-
-static inline void tdc_write(struct tegra_dma_channel *tdc,
-                u32 reg, u32 val)
-{
-        writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
-}
-
-static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
-{
-        return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
-}
-
-static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
-{
-        return container_of(dc, struct tegra_dma_channel, dma_chan);
-}
-
-static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
-                struct dma_async_tx_descriptor *td)
-{
-        return container_of(td, struct tegra_dma_desc, txd);
-}
-
-static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
-{
-        return &tdc->dma_chan.dev->device;
-}
-
-static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
-static int tegra_dma_runtime_suspend(struct device *dev);
-static int tegra_dma_runtime_resume(struct device *dev);
-
-/* Get DMA desc from free list, if not there then allocate it.  */
-static struct tegra_dma_desc *tegra_dma_desc_get(
-                struct tegra_dma_channel *tdc)
-{
-        struct tegra_dma_desc *dma_desc;
-        unsigned long flags;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-
-        /* Do not allocate if desc are waiting for ack */
-        list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
-                if (async_tx_test_ack(&dma_desc->txd)) {
-                        list_del(&dma_desc->node);
-                        spin_unlock_irqrestore(&tdc->lock, flags);
-                        return dma_desc;
-                }
-        }
-
-        spin_unlock_irqrestore(&tdc->lock, flags);
-
-        /* Allocate DMA desc */
-        dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
-        if (!dma_desc) {
-                dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
-                return NULL;
-        }
-
-        dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
-        dma_desc->txd.tx_submit = tegra_dma_tx_submit;
-        dma_desc->txd.flags = 0;
-        return dma_desc;
-}
-
-static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
-                struct tegra_dma_desc *dma_desc)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-        if (!list_empty(&dma_desc->tx_list))
-                list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
-        list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
-        spin_unlock_irqrestore(&tdc->lock, flags);
-}
-
-static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
-                struct tegra_dma_channel *tdc)
-{
-        struct tegra_dma_sg_req *sg_req = NULL;
-        unsigned long flags;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-        if (!list_empty(&tdc->free_sg_req)) {
-                sg_req = list_first_entry(&tdc->free_sg_req,
-                                        typeof(*sg_req), node);
-                list_del(&sg_req->node);
-                spin_unlock_irqrestore(&tdc->lock, flags);
-                return sg_req;
-        }
-        spin_unlock_irqrestore(&tdc->lock, flags);
-
-        sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
-        if (!sg_req)
-                dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
-        return sg_req;
-}
-
-static int tegra_dma_slave_config(struct dma_chan *dc,
-                struct dma_slave_config *sconfig)
-{
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-
-        if (!list_empty(&tdc->pending_sg_req)) {
-                dev_err(tdc2dev(tdc), "Configuration not allowed\n");
-                return -EBUSY;
-        }
-
-        memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
-        tdc->config_init = true;
-        return 0;
-}
-
-static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
-        bool wait_for_burst_complete)
-{
-        struct tegra_dma *tdma = tdc->tdma;
-
-        spin_lock(&tdma->global_lock);
-        tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
-        if (wait_for_burst_complete)
-                udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
-}
-
-static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
-{
-        struct tegra_dma *tdma = tdc->tdma;
-
-        tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
-        spin_unlock(&tdma->global_lock);
-}
-
-static void tegra_dma_stop(struct tegra_dma_channel *tdc)
-{
-        u32 csr;
-        u32 status;
-
-        /* Disable interrupts */
-        csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
-        csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
-
-        /* Disable DMA */
-        csr &= ~TEGRA_APBDMA_CSR_ENB;
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
-
-        /* Clear interrupt status if it is there */
-        status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
-        if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
-                dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
-                tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
-        }
-        tdc->busy = false;
-}
-
-static void tegra_dma_start(struct tegra_dma_channel *tdc,
-                struct tegra_dma_sg_req *sg_req)
-{
-        struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
-
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
-
-        /* Start DMA */
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
-                                ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
-}
-
-static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
-                struct tegra_dma_sg_req *nsg_req)
-{
-        unsigned long status;
-
-        /*
-         * The DMA controller reloads the new configuration for next transfer
-         * after last burst of current transfer completes.
-         * If there is no IEC status then this makes sure that last burst
-         * has not be completed. There may be case that last burst is on
-         * flight and so it can complete but because DMA is paused, it
-         * will not generates interrupt as well as not reload the new
-         * configuration.
-         * If there is already IEC status then interrupt handler need to
-         * load new configuration.
-         */
-        tegra_dma_global_pause(tdc, false);
-        status  = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
-
-        /*
-         * If interrupt is pending then do nothing as the ISR will handle
-         * the programing for new request.
-         */
-        if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
-                dev_err(tdc2dev(tdc),
-                        "Skipping new configuration as interrupt is pending\n");
-                tegra_dma_global_resume(tdc);
-                return;
-        }
-
-        /* Safe to program new configuration */
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
-        tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
-                                nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
-        nsg_req->configured = true;
-
-        tegra_dma_global_resume(tdc);
-}
-
-static void tdc_start_head_req(struct tegra_dma_channel *tdc)
-{
-        struct tegra_dma_sg_req *sg_req;
-
-        if (list_empty(&tdc->pending_sg_req))
-                return;
-
-        sg_req = list_first_entry(&tdc->pending_sg_req,
-                                        typeof(*sg_req), node);
-        tegra_dma_start(tdc, sg_req);
-        sg_req->configured = true;
-        tdc->busy = true;
-}
-
-static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
-{
-        struct tegra_dma_sg_req *hsgreq;
-        struct tegra_dma_sg_req *hnsgreq;
-
-        if (list_empty(&tdc->pending_sg_req))
-                return;
-
-        hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
-        if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
-                hnsgreq = list_first_entry(&hsgreq->node,
-                                        typeof(*hnsgreq), node);
-                tegra_dma_configure_for_next(tdc, hnsgreq);
-        }
-}
-
-static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
-        struct tegra_dma_sg_req *sg_req, unsigned long status)
-{
-        return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
-}
-
-static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
-{
-        struct tegra_dma_sg_req *sgreq;
-        struct tegra_dma_desc *dma_desc;
-
-        while (!list_empty(&tdc->pending_sg_req)) {
-                sgreq = list_first_entry(&tdc->pending_sg_req,
-                                                typeof(*sgreq), node);
-                list_move_tail(&sgreq->node, &tdc->free_sg_req);
-                if (sgreq->last_sg) {
-                        dma_desc = sgreq->dma_desc;
-                        dma_desc->dma_status = DMA_ERROR;
-                        list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
-
-                        /* Add in cb list if it is not there. */
-                        if (!dma_desc->cb_count)
-                                list_add_tail(&dma_desc->cb_node,
-                                                        &tdc->cb_desc);
-                        dma_desc->cb_count++;
-                }
-        }
-        tdc->isr_handler = NULL;
-}
-
-static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
-                struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
-{
-        struct tegra_dma_sg_req *hsgreq = NULL;
-
-        if (list_empty(&tdc->pending_sg_req)) {
-                dev_err(tdc2dev(tdc), "Dma is running without req\n");
-                tegra_dma_stop(tdc);
-                return false;
-        }
-
-        /*
-         * Check that head req on list should be in flight.
-         * If it is not in flight then abort transfer as
-         * looping of transfer can not continue.
-         */
-        hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
-        if (!hsgreq->configured) {
-                tegra_dma_stop(tdc);
-                dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
-                tegra_dma_abort_all(tdc);
-                return false;
-        }
-
-        /* Configure next request */
-        if (!to_terminate)
-                tdc_configure_next_head_desc(tdc);
-        return true;
-}
-
-static void handle_once_dma_done(struct tegra_dma_channel *tdc,
-        bool to_terminate)
-{
-        struct tegra_dma_sg_req *sgreq;
-        struct tegra_dma_desc *dma_desc;
-
-        tdc->busy = false;
-        sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
-        dma_desc = sgreq->dma_desc;
-        dma_desc->bytes_transferred += sgreq->req_len;
-
-        list_del(&sgreq->node);
-        if (sgreq->last_sg) {
-                dma_desc->dma_status = DMA_SUCCESS;
-                dma_cookie_complete(&dma_desc->txd);
-                if (!dma_desc->cb_count)
-                        list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
-                dma_desc->cb_count++;
-                list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
-        }
-        list_add_tail(&sgreq->node, &tdc->free_sg_req);
-
-        /* Do not start DMA if it is going to be terminate */
-        if (to_terminate || list_empty(&tdc->pending_sg_req))
-                return;
-
-        tdc_start_head_req(tdc);
-        return;
-}
-
-static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
-                bool to_terminate)
-{
-        struct tegra_dma_sg_req *sgreq;
-        struct tegra_dma_desc *dma_desc;
-        bool st;
-
-        sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
-        dma_desc = sgreq->dma_desc;
-        dma_desc->bytes_transferred += sgreq->req_len;
-
-        /* Callback need to be call */
-        if (!dma_desc->cb_count)
-                list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
-        dma_desc->cb_count++;
-
-        /* If not last req then put at end of pending list */
-        if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
-                list_move_tail(&sgreq->node, &tdc->pending_sg_req);
-                sgreq->configured = false;
-                st = handle_continuous_head_request(tdc, sgreq, to_terminate);
-                if (!st)
-                        dma_desc->dma_status = DMA_ERROR;
-        }
-        return;
-}
-
-static void tegra_dma_tasklet(unsigned long data)
-{
-        struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
-        dma_async_tx_callback callback = NULL;
-        void *callback_param = NULL;
-        struct tegra_dma_desc *dma_desc;
-        unsigned long flags;
-        int cb_count;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-        while (!list_empty(&tdc->cb_desc)) {
-                dma_desc  = list_first_entry(&tdc->cb_desc,
-                                        typeof(*dma_desc), cb_node);
-                list_del(&dma_desc->cb_node);
-                callback = dma_desc->txd.callback;
-                callback_param = dma_desc->txd.callback_param;
-                cb_count = dma_desc->cb_count;
-                dma_desc->cb_count = 0;
-                spin_unlock_irqrestore(&tdc->lock, flags);
-                while (cb_count-- && callback)
-                        callback(callback_param);
-                spin_lock_irqsave(&tdc->lock, flags);
-        }
-        spin_unlock_irqrestore(&tdc->lock, flags);
-}
-
-static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
-{
-        struct tegra_dma_channel *tdc = dev_id;
-        unsigned long status;
-        unsigned long flags;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-
-        status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
-        if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
-                tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
-                tdc->isr_handler(tdc, false);
-                tasklet_schedule(&tdc->tasklet);
-                spin_unlock_irqrestore(&tdc->lock, flags);
-                return IRQ_HANDLED;
-        }
-
-        spin_unlock_irqrestore(&tdc->lock, flags);
-        dev_info(tdc2dev(tdc),
-                "Interrupt already served status 0x%08lx\n", status);
-        return IRQ_NONE;
-}
-
-static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
-{
-        struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
-        unsigned long flags;
-        dma_cookie_t cookie;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-        dma_desc->dma_status = DMA_IN_PROGRESS;
-        cookie = dma_cookie_assign(&dma_desc->txd);
-        list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
-        spin_unlock_irqrestore(&tdc->lock, flags);
-        return cookie;
-}
-
-static void tegra_dma_issue_pending(struct dma_chan *dc)
-{
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-        unsigned long flags;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-        if (list_empty(&tdc->pending_sg_req)) {
-                dev_err(tdc2dev(tdc), "No DMA request\n");
-                goto end;
-        }
-        if (!tdc->busy) {
-                tdc_start_head_req(tdc);
-
-                /* Continuous single mode: Configure next req */
-                if (tdc->cyclic) {
-                        /*
-                         * Wait for 1 burst time for configure DMA for
-                         * next transfer.
-                         */
-                        udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
-                        tdc_configure_next_head_desc(tdc);
-                }
-        }
-end:
-        spin_unlock_irqrestore(&tdc->lock, flags);
-        return;
-}
-
-static void tegra_dma_terminate_all(struct dma_chan *dc)
-{
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-        struct tegra_dma_sg_req *sgreq;
-        struct tegra_dma_desc *dma_desc;
-        unsigned long flags;
-        unsigned long status;
-        bool was_busy;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-        if (list_empty(&tdc->pending_sg_req)) {
-                spin_unlock_irqrestore(&tdc->lock, flags);
-                return;
-        }
-
-        if (!tdc->busy)
-                goto skip_dma_stop;
-
-        /* Pause DMA before checking the queue status */
-        tegra_dma_global_pause(tdc, true);
-
-        status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
-        if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
-                dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
-                tdc->isr_handler(tdc, true);
-                status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
-        }
-
-        was_busy = tdc->busy;
-        tegra_dma_stop(tdc);
-
-        if (!list_empty(&tdc->pending_sg_req) && was_busy) {
-                sgreq = list_first_entry(&tdc->pending_sg_req,
-                                        typeof(*sgreq), node);
-                sgreq->dma_desc->bytes_transferred +=
-                                get_current_xferred_count(tdc, sgreq, status);
-        }
-        tegra_dma_global_resume(tdc);
-
-skip_dma_stop:
-        tegra_dma_abort_all(tdc);
-
-        while (!list_empty(&tdc->cb_desc)) {
-                dma_desc  = list_first_entry(&tdc->cb_desc,
-                                        typeof(*dma_desc), cb_node);
-                list_del(&dma_desc->cb_node);
-                dma_desc->cb_count = 0;
-        }
-        spin_unlock_irqrestore(&tdc->lock, flags);
-}
-
-static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
-        dma_cookie_t cookie, struct dma_tx_state *txstate)
-{
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-        struct tegra_dma_desc *dma_desc;
-        struct tegra_dma_sg_req *sg_req;
-        enum dma_status ret;
-        unsigned long flags;
-        unsigned int residual;
-
-        spin_lock_irqsave(&tdc->lock, flags);
-
-        ret = dma_cookie_status(dc, cookie, txstate);
-        if (ret == DMA_SUCCESS) {
-                dma_set_residue(txstate, 0);
-                spin_unlock_irqrestore(&tdc->lock, flags);
-                return ret;
-        }
-
-        /* Check on wait_ack desc status */
-        list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
-                if (dma_desc->txd.cookie == cookie) {
-                        residual =  dma_desc->bytes_requested -
-                                        (dma_desc->bytes_transferred %
-                                                dma_desc->bytes_requested);
-                        dma_set_residue(txstate, residual);
-                        ret = dma_desc->dma_status;
-                        spin_unlock_irqrestore(&tdc->lock, flags);
-                        return ret;
-                }
-        }
-
-        /* Check in pending list */
-        list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
-                dma_desc = sg_req->dma_desc;
-                if (dma_desc->txd.cookie == cookie) {
-                        residual =  dma_desc->bytes_requested -
-                                        (dma_desc->bytes_transferred %
-                                                dma_desc->bytes_requested);
-                        dma_set_residue(txstate, residual);
-                        ret = dma_desc->dma_status;
-                        spin_unlock_irqrestore(&tdc->lock, flags);
-                        return ret;
-                }
-        }
-
-        dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
-        spin_unlock_irqrestore(&tdc->lock, flags);
-        return ret;
-}
-
-static int tegra_dma_device_control(struct dma_chan *dc, enum dma_ctrl_cmd cmd,
-                        unsigned long arg)
-{
-        switch (cmd) {
-        case DMA_SLAVE_CONFIG:
-                return tegra_dma_slave_config(dc,
-                                (struct dma_slave_config *)arg);
-
-        case DMA_TERMINATE_ALL:
-                tegra_dma_terminate_all(dc);
-                return 0;
-
-        default:
-                break;
-        }
-
-        return -ENXIO;
-}
-
-static inline int get_bus_width(struct tegra_dma_channel *tdc,
-                enum dma_slave_buswidth slave_bw)
-{
-        switch (slave_bw) {
-        case DMA_SLAVE_BUSWIDTH_1_BYTE:
-                return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
-        case DMA_SLAVE_BUSWIDTH_2_BYTES:
-                return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
-        case DMA_SLAVE_BUSWIDTH_4_BYTES:
-                return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
-        case DMA_SLAVE_BUSWIDTH_8_BYTES:
-                return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
-        default:
-                dev_warn(tdc2dev(tdc),
-                        "slave bw is not supported, using 32bits\n");
-                return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
-        }
-}
-
-static inline int get_burst_size(struct tegra_dma_channel *tdc,
-        u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
-{
-        int burst_byte;
-        int burst_ahb_width;
-
-        /*
-         * burst_size from client is in terms of the bus_width.
-         * convert them into AHB memory width which is 4 byte.
-         */
-        burst_byte = burst_size * slave_bw;
-        burst_ahb_width = burst_byte / 4;
-
-        /* If burst size is 0 then calculate the burst size based on length */
-        if (!burst_ahb_width) {
-                if (len & 0xF)
-                        return TEGRA_APBDMA_AHBSEQ_BURST_1;
-                else if ((len >> 4) & 0x1)
-                        return TEGRA_APBDMA_AHBSEQ_BURST_4;
-                else
-                        return TEGRA_APBDMA_AHBSEQ_BURST_8;
-        }
-        if (burst_ahb_width < 4)
-                return TEGRA_APBDMA_AHBSEQ_BURST_1;
-        else if (burst_ahb_width < 8)
-                return TEGRA_APBDMA_AHBSEQ_BURST_4;
-        else
-                return TEGRA_APBDMA_AHBSEQ_BURST_8;
-}
-
-static int get_transfer_param(struct tegra_dma_channel *tdc,
-        enum dma_transfer_direction direction, unsigned long *apb_addr,
-        unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
-        enum dma_slave_buswidth *slave_bw)
-{
-
-        switch (direction) {
-        case DMA_MEM_TO_DEV:
-                *apb_addr = tdc->dma_sconfig.dst_addr;
-                *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
-                *burst_size = tdc->dma_sconfig.dst_maxburst;
-                *slave_bw = tdc->dma_sconfig.dst_addr_width;
-                *csr = TEGRA_APBDMA_CSR_DIR;
-                return 0;
-
-        case DMA_DEV_TO_MEM:
-                *apb_addr = tdc->dma_sconfig.src_addr;
-                *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
-                *burst_size = tdc->dma_sconfig.src_maxburst;
-                *slave_bw = tdc->dma_sconfig.src_addr_width;
-                *csr = 0;
-                return 0;
-
-        default:
-                dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
-                return -EINVAL;
-        }
-        return -EINVAL;
-}
-
-static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
-        struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
-        enum dma_transfer_direction direction, unsigned long flags,
-        void *context)
-{
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-        struct tegra_dma_desc *dma_desc;
-        unsigned int        i;
-        struct scatterlist      *sg;
-        unsigned long csr, ahb_seq, apb_ptr, apb_seq;
-        struct list_head req_list;
-        struct tegra_dma_sg_req  *sg_req = NULL;
-        u32 burst_size;
-        enum dma_slave_buswidth slave_bw;
-        int ret;
-
-        if (!tdc->config_init) {
-                dev_err(tdc2dev(tdc), "dma channel is not configured\n");
-                return NULL;
-        }
-        if (sg_len < 1) {
-                dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
-                return NULL;
-        }
-
-        ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
-                                &burst_size, &slave_bw);
-        if (ret < 0)
-                return NULL;
-
-        INIT_LIST_HEAD(&req_list);
-
-        ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
-        ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
-                                        TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
-        ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
-
-        csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
-        csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
-        if (flags & DMA_PREP_INTERRUPT)
-                csr |= TEGRA_APBDMA_CSR_IE_EOC;
-
-        apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
-
-        dma_desc = tegra_dma_desc_get(tdc);
-        if (!dma_desc) {
-                dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
-                return NULL;
-        }
-        INIT_LIST_HEAD(&dma_desc->tx_list);
-        INIT_LIST_HEAD(&dma_desc->cb_node);
-        dma_desc->cb_count = 0;
-        dma_desc->bytes_requested = 0;
-        dma_desc->bytes_transferred = 0;
-        dma_desc->dma_status = DMA_IN_PROGRESS;
-
-        /* Make transfer requests */
-        for_each_sg(sgl, sg, sg_len, i) {
-                u32 len, mem;
-
-                mem = sg_dma_address(sg);
-                len = sg_dma_len(sg);
-
-                if ((len & 3) || (mem & 3) ||
-                                (len > tdc->tdma->chip_data->max_dma_count)) {
-                        dev_err(tdc2dev(tdc),
-                                "Dma length/memory address is not supported\n");
-                        tegra_dma_desc_put(tdc, dma_desc);
-                        return NULL;
-                }
-
-                sg_req = tegra_dma_sg_req_get(tdc);
-                if (!sg_req) {
-                        dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
-                        tegra_dma_desc_put(tdc, dma_desc);
-                        return NULL;
-                }
-
-                ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
-                dma_desc->bytes_requested += len;
-
-                sg_req->ch_regs.apb_ptr = apb_ptr;
-                sg_req->ch_regs.ahb_ptr = mem;
-                sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
-                sg_req->ch_regs.apb_seq = apb_seq;
-                sg_req->ch_regs.ahb_seq = ahb_seq;
-                sg_req->configured = false;
-                sg_req->last_sg = false;
-                sg_req->dma_desc = dma_desc;
-                sg_req->req_len = len;
-
-                list_add_tail(&sg_req->node, &dma_desc->tx_list);
-        }
-        sg_req->last_sg = true;
-        if (flags & DMA_CTRL_ACK)
-                dma_desc->txd.flags = DMA_CTRL_ACK;
-
-        /*
-         * Make sure that mode should not be conflicting with currently
-         * configured mode.
-         */
-        if (!tdc->isr_handler) {
-                tdc->isr_handler = handle_once_dma_done;
-                tdc->cyclic = false;
-        } else {
-                if (tdc->cyclic) {
-                        dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
-                        tegra_dma_desc_put(tdc, dma_desc);
-                        return NULL;
-                }
-        }
-
-        return &dma_desc->txd;
-}
-
-struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
-        struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
-        size_t period_len, enum dma_transfer_direction direction,
-        unsigned long flags, void *context)
-{
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-        struct tegra_dma_desc *dma_desc = NULL;
-        struct tegra_dma_sg_req  *sg_req = NULL;
-        unsigned long csr, ahb_seq, apb_ptr, apb_seq;
-        int len;
-        size_t remain_len;
-        dma_addr_t mem = buf_addr;
-        u32 burst_size;
-        enum dma_slave_buswidth slave_bw;
-        int ret;
-
-        if (!buf_len || !period_len) {
-                dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
-                return NULL;
-        }
-
-        if (!tdc->config_init) {
-                dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
-                return NULL;
-        }
-
-        /*
-         * We allow to take more number of requests till DMA is
-         * not started. The driver will loop over all requests.
-         * Once DMA is started then new requests can be queued only after
-         * terminating the DMA.
-         */
-        if (tdc->busy) {
-                dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
-                return NULL;
-        }
-
-        /*
-         * We only support cycle transfer when buf_len is multiple of
-         * period_len.
-         */
-        if (buf_len % period_len) {
-                dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
-                return NULL;
-        }
-
-        len = period_len;
-        if ((len & 3) || (buf_addr & 3) ||
-                        (len > tdc->tdma->chip_data->max_dma_count)) {
-                dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
-                return NULL;
-        }
-
-        ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
-                                &burst_size, &slave_bw);
-        if (ret < 0)
-                return NULL;
-
-
-        ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
-        ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
-                                        TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
-        ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
-
-        csr |= TEGRA_APBDMA_CSR_FLOW | TEGRA_APBDMA_CSR_IE_EOC;
-        csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
-
-        apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
-
-        dma_desc = tegra_dma_desc_get(tdc);
-        if (!dma_desc) {
-                dev_err(tdc2dev(tdc), "not enough descriptors available\n");
-                return NULL;
-        }
-
-        INIT_LIST_HEAD(&dma_desc->tx_list);
-        INIT_LIST_HEAD(&dma_desc->cb_node);
-        dma_desc->cb_count = 0;
-
-        dma_desc->bytes_transferred = 0;
-        dma_desc->bytes_requested = buf_len;
-        remain_len = buf_len;
-
-        /* Split transfer equal to period size */
-        while (remain_len) {
-                sg_req = tegra_dma_sg_req_get(tdc);
-                if (!sg_req) {
-                        dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
-                        tegra_dma_desc_put(tdc, dma_desc);
-                        return NULL;
-                }
-
-                ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
-                sg_req->ch_regs.apb_ptr = apb_ptr;
-                sg_req->ch_regs.ahb_ptr = mem;
-                sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
-                sg_req->ch_regs.apb_seq = apb_seq;
-                sg_req->ch_regs.ahb_seq = ahb_seq;
-                sg_req->configured = false;
-                sg_req->half_done = false;
-                sg_req->last_sg = false;
-                sg_req->dma_desc = dma_desc;
-                sg_req->req_len = len;
-
-                list_add_tail(&sg_req->node, &dma_desc->tx_list);
-                remain_len -= len;
-                mem += len;
-        }
-        sg_req->last_sg = true;
-        dma_desc->txd.flags = 0;
-
-        /*
-         * Make sure that mode should not be conflicting with currently
-         * configured mode.
-         */
-        if (!tdc->isr_handler) {
-                tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
-                tdc->cyclic = true;
-        } else {
-                if (!tdc->cyclic) {
-                        dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
-                        tegra_dma_desc_put(tdc, dma_desc);
-                        return NULL;
-                }
-        }
-
-        return &dma_desc->txd;
-}
-
-static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
-{
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-        struct tegra_dma *tdma = tdc->tdma;
-        int ret;
-
-        dma_cookie_init(&tdc->dma_chan);
-        tdc->config_init = false;
-        ret = clk_prepare_enable(tdma->dma_clk);
-        if (ret < 0)
-                dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
-        return ret;
-}
-
-static void tegra_dma_free_chan_resources(struct dma_chan *dc)
-{
-        struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-        struct tegra_dma *tdma = tdc->tdma;
-
-        struct tegra_dma_desc *dma_desc;
-        struct tegra_dma_sg_req *sg_req;
-        struct list_head dma_desc_list;
-        struct list_head sg_req_list;
-        unsigned long flags;
-
-        INIT_LIST_HEAD(&dma_desc_list);
-        INIT_LIST_HEAD(&sg_req_list);
-
-        dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
-
-        if (tdc->busy)
-                tegra_dma_terminate_all(dc);
-
-        spin_lock_irqsave(&tdc->lock, flags);
-        list_splice_init(&tdc->pending_sg_req, &sg_req_list);
-        list_splice_init(&tdc->free_sg_req, &sg_req_list);
-        list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
-        INIT_LIST_HEAD(&tdc->cb_desc);
-        tdc->config_init = false;
-        spin_unlock_irqrestore(&tdc->lock, flags);
-
-        while (!list_empty(&dma_desc_list)) {
-                dma_desc = list_first_entry(&dma_desc_list,
-                                        typeof(*dma_desc), node);
-                list_del(&dma_desc->node);
-                kfree(dma_desc);
-        }
-
-        while (!list_empty(&sg_req_list)) {
-                sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
-                list_del(&sg_req->node);
-                kfree(sg_req);
-        }
-        clk_disable_unprepare(tdma->dma_clk);
-}
-
-/* Tegra20 specific DMA controller information */
-static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
-        .nr_channels            = 16,
-        .max_dma_count          = 1024UL * 64,
-};
-
-#if defined(CONFIG_OF)
-/* Tegra30 specific DMA controller information */
-static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
-        .nr_channels            = 32,
-        .max_dma_count          = 1024UL * 64,
-};
-
-static const struct of_device_id tegra_dma_of_match[] = {
-        {
-                .compatible = "nvidia,tegra30-apbdma",
-                .data = &tegra30_dma_chip_data,
-        }, {
-                .compatible = "nvidia,tegra20-apbdma",
-                .data = &tegra20_dma_chip_data,
-        }, {
-        },
-};
-MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
-#endif
-
-static int tegra_dma_probe(struct platform_device *pdev)
-{
-        struct resource *res;
-        struct tegra_dma *tdma;
-        int ret;
-        int i;
-        const struct tegra_dma_chip_data *cdata = NULL;
-
-        if (pdev->dev.of_node) {
-                const struct of_device_id *match;
-                match = of_match_device(of_match_ptr(tegra_dma_of_match),
-                                        &pdev->dev);
-                if (!match) {
-                        dev_err(&pdev->dev, "Error: No device match found\n");
-                        return -ENODEV;
-                }
-                cdata = match->data;
-        } else {
-                /* If no device tree then fallback to tegra20 */
-                cdata = &tegra20_dma_chip_data;
-        }
-
-        tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
-                        sizeof(struct tegra_dma_channel), GFP_KERNEL);
-        if (!tdma) {
-                dev_err(&pdev->dev, "Error: memory allocation failed\n");
-                return -ENOMEM;
-        }
-
-        tdma->dev = &pdev->dev;
-        tdma->chip_data = cdata;
-        platform_set_drvdata(pdev, tdma);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "No mem resource for DMA\n");
-                return -EINVAL;
-        }
-
-        tdma->base_addr = devm_request_and_ioremap(&pdev->dev, res);
-        if (!tdma->base_addr) {
-                dev_err(&pdev->dev,
-                        "Cannot request memregion/iomap dma address\n");
-                return -EADDRNOTAVAIL;
-        }
-
-        tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
-        if (IS_ERR(tdma->dma_clk)) {
-                dev_err(&pdev->dev, "Error: Missing controller clock\n");
-                return PTR_ERR(tdma->dma_clk);
-        }
-
-        spin_lock_init(&tdma->global_lock);
-
-        pm_runtime_enable(&pdev->dev);
-        if (!pm_runtime_enabled(&pdev->dev)) {
-                ret = tegra_dma_runtime_resume(&pdev->dev);
-                if (ret) {
-                        dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
-                                ret);
-                        goto err_pm_disable;
-                }
-        }
-
-        /* Enable clock before accessing registers */
-        ret = clk_prepare_enable(tdma->dma_clk);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
-                goto err_pm_disable;
-        }
-
-        /* Reset DMA controller */
-        tegra_periph_reset_assert(tdma->dma_clk);
-        udelay(2);
-        tegra_periph_reset_deassert(tdma->dma_clk);
-
-        /* Enable global DMA registers */
-        tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
-        tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
-        tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
-
-        clk_disable_unprepare(tdma->dma_clk);
-
-        INIT_LIST_HEAD(&tdma->dma_dev.channels);
-        for (i = 0; i < cdata->nr_channels; i++) {
-                struct tegra_dma_channel *tdc = &tdma->channels[i];
-
-                tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
-                                        i * TEGRA_APBDMA_CHANNEL_REGISTER_SIZE;
-
-                res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
-                if (!res) {
-                        ret = -EINVAL;
-                        dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
-                        goto err_irq;
-                }
-                tdc->irq = res->start;
-                snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
-                ret = devm_request_irq(&pdev->dev, tdc->irq,
-                                tegra_dma_isr, 0, tdc->name, tdc);
-                if (ret) {
-                        dev_err(&pdev->dev,
-                                "request_irq failed with err %d channel %d\n",
-                                i, ret);
-                        goto err_irq;
-                }
-
-                tdc->dma_chan.device = &tdma->dma_dev;
-                dma_cookie_init(&tdc->dma_chan);
-                list_add_tail(&tdc->dma_chan.device_node,
-                                &tdma->dma_dev.channels);
-                tdc->tdma = tdma;
-                tdc->id = i;
-
-                tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
-                                (unsigned long)tdc);
-                spin_lock_init(&tdc->lock);
-
-                INIT_LIST_HEAD(&tdc->pending_sg_req);
-                INIT_LIST_HEAD(&tdc->free_sg_req);
-                INIT_LIST_HEAD(&tdc->free_dma_desc);
-                INIT_LIST_HEAD(&tdc->cb_desc);
-        }
-
-        dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
-        dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
-        dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
-
-        tdma->dma_dev.dev = &pdev->dev;
-        tdma->dma_dev.device_alloc_chan_resources =
-                                        tegra_dma_alloc_chan_resources;
-        tdma->dma_dev.device_free_chan_resources =
-                                        tegra_dma_free_chan_resources;
-        tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
-        tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
-        tdma->dma_dev.device_control = tegra_dma_device_control;
-        tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
-        tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
-
-        ret = dma_async_device_register(&tdma->dma_dev);
-        if (ret < 0) {
-                dev_err(&pdev->dev,
-                        "Tegra20 APB DMA driver registration failed %d\n", ret);
-                goto err_irq;
-        }
-
-        dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
-                        cdata->nr_channels);
-        return 0;
-
-err_irq:
-        while (--i >= 0) {
-                struct tegra_dma_channel *tdc = &tdma->channels[i];
-                tasklet_kill(&tdc->tasklet);
-        }
-
-err_pm_disable:
-        pm_runtime_disable(&pdev->dev);
-        if (!pm_runtime_status_suspended(&pdev->dev))
-                tegra_dma_runtime_suspend(&pdev->dev);
-        return ret;
-}
-
-static int tegra_dma_remove(struct platform_device *pdev)
-{
-        struct tegra_dma *tdma = platform_get_drvdata(pdev);
-        int i;
-        struct tegra_dma_channel *tdc;
-
-        dma_async_device_unregister(&tdma->dma_dev);
-
-        for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
-                tdc = &tdma->channels[i];
-                tasklet_kill(&tdc->tasklet);
-        }
-
-        pm_runtime_disable(&pdev->dev);
-        if (!pm_runtime_status_suspended(&pdev->dev))
-                tegra_dma_runtime_suspend(&pdev->dev);
-
-        return 0;
-}
-
-static int tegra_dma_runtime_suspend(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct tegra_dma *tdma = platform_get_drvdata(pdev);
-
-        clk_disable_unprepare(tdma->dma_clk);
-        return 0;
-}
-
-static int tegra_dma_runtime_resume(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct tegra_dma *tdma = platform_get_drvdata(pdev);
-        int ret;
-
-        ret = clk_prepare_enable(tdma->dma_clk);
-        if (ret < 0) {
-                dev_err(dev, "clk_enable failed: %d\n", ret);
-                return ret;
-        }
-        return 0;
-}
-
-static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
-#ifdef CONFIG_PM_RUNTIME
-        .runtime_suspend = tegra_dma_runtime_suspend,
-        .runtime_resume = tegra_dma_runtime_resume,
-#endif
-};
-
-static struct platform_driver tegra_dmac_driver = {
-        .driver = {
-                .name   = "tegra-apbdma",
-                .owner = THIS_MODULE,
-                .pm     = &tegra_dma_dev_pm_ops,
-                .of_match_table = of_match_ptr(tegra_dma_of_match),
-        },
-        .probe          = tegra_dma_probe,
-        .remove         = tegra_dma_remove,
-};
-
-module_platform_driver(tegra_dmac_driver);
-
-MODULE_ALIAS("platform:tegra20-apbdma");
-MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
-MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index 952f823901a..f69f90a6187 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -31,8 +31,6 @@
 
 #include <linux/timb_dma.h>
 
-#include "dmaengine.h"
-
 #define DRIVER_NAME "timb-dma"
 
 /* Global DMA registers */
@@ -86,12 +84,13 @@ struct timb_dma_chan {
                                         especially the lists and descriptors,
                                         from races between the tasklet and calls
                                         from above */
+        dma_cookie_t            last_completed_cookie;
         bool                    ongoing;
         struct list_head        active_list;
         struct list_head        queue;
         struct list_head        free_list;
         unsigned int            bytes_per_line;
-        enum dma_transfer_direction     direction;
+        enum dma_data_direction direction;
         unsigned int            descs; /* Descriptors to allocate */
         unsigned int            desc_elems; /* number of elems per descriptor */
 };
@@ -167,10 +166,10 @@ static void __td_unmap_desc(struct timb_dma_chan *td_chan, const u8 *dma_desc,
 
         if (single)
                 dma_unmap_single(chan2dev(&td_chan->chan), addr, len,
-                        DMA_TO_DEVICE);
+                        td_chan->direction);
         else
                 dma_unmap_page(chan2dev(&td_chan->chan), addr, len,
-                        DMA_TO_DEVICE);
+                        td_chan->direction);
 }
 
 static void __td_unmap_descs(struct timb_dma_desc *td_desc, bool single)
@@ -236,7 +235,7 @@ static void __td_start_dma(struct timb_dma_chan *td_chan)
                 "td_chan: %p, chan: %d, membase: %p\n",
                 td_chan, td_chan->chan.chan_id, td_chan->membase);
 
-        if (td_chan->direction == DMA_DEV_TO_MEM) {
+        if (td_chan->direction == DMA_FROM_DEVICE) {
 
                 /* descriptor address */
                 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
@@ -279,13 +278,13 @@ static void __td_finish(struct timb_dma_chan *td_chan)
                 txd->cookie);
 
         /* make sure to stop the transfer */
-        if (td_chan->direction == DMA_DEV_TO_MEM)
+        if (td_chan->direction == DMA_FROM_DEVICE)
                 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER);
 /* Currently no support for stopping DMA transfers
         else
                 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
 */
-        dma_cookie_complete(txd);
+        td_chan->last_completed_cookie = txd->cookie;
         td_chan->ongoing = false;
 
         callback = txd->callback;
@@ -350,7 +349,12 @@ static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd)
         dma_cookie_t cookie;
 
         spin_lock_bh(&td_chan->lock);
-        cookie = dma_cookie_assign(txd);
+
+        cookie = txd->chan->cookie;
+        if (++cookie < 0)
+                cookie = 1;
+        txd->chan->cookie = cookie;
+        txd->cookie = cookie;
 
         if (list_empty(&td_chan->active_list)) {
                 dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__,
@@ -477,7 +481,8 @@ static int td_alloc_chan_resources(struct dma_chan *chan)
         }
 
         spin_lock_bh(&td_chan->lock);
-        dma_cookie_init(chan);
+        td_chan->last_completed_cookie = 1;
+        chan->cookie = 1;
         spin_unlock_bh(&td_chan->lock);
 
         return 0;
@@ -510,13 +515,24 @@ static void td_free_chan_resources(struct dma_chan *chan)
 static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
                                     struct dma_tx_state *txstate)
 {
-        enum dma_status ret;
+        struct timb_dma_chan *td_chan =
+                container_of(chan, struct timb_dma_chan, chan);
+        dma_cookie_t            last_used;
+        dma_cookie_t            last_complete;
+        int                     ret;
 
         dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
 
-        ret = dma_cookie_status(chan, cookie, txstate);
+        last_complete = td_chan->last_completed_cookie;
+        last_used = chan->cookie;
+
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
+
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
 
-        dev_dbg(chan2dev(chan), "%s: exit, ret: %d\n",  __func__, ret);
+        dev_dbg(chan2dev(chan),
+                "%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
+                __func__, ret, last_complete, last_used);
 
         return ret;
 }
@@ -542,8 +558,7 @@ static void td_issue_pending(struct dma_chan *chan)
 
 static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
         struct scatterlist *sgl, unsigned int sg_len,
-        enum dma_transfer_direction direction, unsigned long flags,
-        void *context)
+        enum dma_data_direction direction, unsigned long flags)
 {
         struct timb_dma_chan *td_chan =
                 container_of(chan, struct timb_dma_chan, chan);
@@ -591,7 +606,7 @@ static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
         }
 
         dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys,
-                td_desc->desc_list_len, DMA_MEM_TO_DEV);
+                td_desc->desc_list_len, DMA_TO_DEVICE);
 
         return &td_desc->txd;
 }
@@ -667,7 +682,7 @@ static irqreturn_t td_irq(int irq, void *devid)
 }
 
 
-static int td_probe(struct platform_device *pdev)
+static int __devinit td_probe(struct platform_device *pdev)
 {
         struct timb_dma_platform_data *pdata = pdev->dev.platform_data;
         struct timb_dma *td;
@@ -738,7 +753,7 @@ static int td_probe(struct platform_device *pdev)
 
         INIT_LIST_HEAD(&td->dma.channels);
 
-        for (i = 0; i < pdata->nr_channels; i++) {
+        for (i = 0; i < pdata->nr_channels; i++, td->dma.chancnt++) {
                 struct timb_dma_chan *td_chan = &td->channels[i];
                 struct timb_dma_platform_data_channel *pchan =
                         pdata->channels + i;
@@ -747,11 +762,12 @@ static int td_probe(struct platform_device *pdev)
                 if ((i % 2) == pchan->rx) {
                         dev_err(&pdev->dev, "Wrong channel configuration\n");
                         err = -EINVAL;
-                        goto err_free_irq;
+                        goto err_tasklet_kill;
                 }
 
                 td_chan->chan.device = &td->dma;
-                dma_cookie_init(&td_chan->chan);
+                td_chan->chan.cookie = 1;
+                td_chan->chan.chan_id = i;
                 spin_lock_init(&td_chan->lock);
                 INIT_LIST_HEAD(&td_chan->active_list);
                 INIT_LIST_HEAD(&td_chan->queue);
@@ -760,8 +776,8 @@ static int td_probe(struct platform_device *pdev)
                 td_chan->descs = pchan->descriptors;
                 td_chan->desc_elems = pchan->descriptor_elements;
                 td_chan->bytes_per_line = pchan->bytes_per_line;
-                td_chan->direction = pchan->rx ? DMA_DEV_TO_MEM :
-                        DMA_MEM_TO_DEV;
+                td_chan->direction = pchan->rx ? DMA_FROM_DEVICE :
+                        DMA_TO_DEVICE;
 
                 td_chan->membase = td->membase +
                         (i / 2) * TIMBDMA_INSTANCE_OFFSET +
@@ -798,7 +814,7 @@ err_release_region:
 
 }
 
-static int td_remove(struct platform_device *pdev)
+static int __devexit td_remove(struct platform_device *pdev)
 {
         struct timb_dma *td = platform_get_drvdata(pdev);
         struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -826,7 +842,17 @@ static struct platform_driver td_driver = {
         .remove = __exit_p(td_remove),
 };
 
-module_platform_driver(td_driver);
+static int __init td_init(void)
+{
+        return platform_driver_register(&td_driver);
+}
+module_init(td_init);
+
+static void __exit td_exit(void)
+{
+        platform_driver_unregister(&td_driver);
+}
+module_exit(td_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("Timberdale DMA controller driver");
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index 913f55c76c9..cbd83e362b5 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -15,8 +15,6 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/scatterlist.h>
-
-#include "dmaengine.h"
 #include "txx9dmac.h"
 
 static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
@@ -281,6 +279,21 @@ static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
         }
 }
 
+/* Called with dc->lock held and bh disabled */
+static dma_cookie_t
+txx9dmac_assign_cookie(struct txx9dmac_chan *dc, struct txx9dmac_desc *desc)
+{
+        dma_cookie_t cookie = dc->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        dc->chan.cookie = cookie;
+        desc->txd.cookie = cookie;
+
+        return cookie;
+}
+
 /*----------------------------------------------------------------------*/
 
 static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
@@ -411,7 +424,7 @@ txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
         dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
                  txd->cookie, desc);
 
-        dma_cookie_complete(txd);
+        dc->completed = txd->cookie;
         callback = txd->callback;
         param = txd->callback_param;
 
@@ -725,7 +738,7 @@ static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
         dma_cookie_t cookie;
 
         spin_lock_bh(&dc->lock);
-        cookie = dma_cookie_assign(tx);
+        cookie = txx9dmac_assign_cookie(dc, desc);
 
         dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
                  desc->txd.cookie, desc);
@@ -832,8 +845,8 @@ txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 
 static struct dma_async_tx_descriptor *
 txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-                unsigned int sg_len, enum dma_transfer_direction direction,
-                unsigned long flags, void *context)
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags)
 {
         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
         struct txx9dmac_dev *ddev = dc->ddev;
@@ -847,9 +860,9 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 
         BUG_ON(!ds || !ds->reg_width);
         if (ds->tx_reg)
-                BUG_ON(direction != DMA_MEM_TO_DEV);
+                BUG_ON(direction != DMA_TO_DEVICE);
         else
-                BUG_ON(direction != DMA_DEV_TO_MEM);
+                BUG_ON(direction != DMA_FROM_DEVICE);
         if (unlikely(!sg_len))
                 return NULL;
 
@@ -869,7 +882,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                 mem = sg_dma_address(sg);
 
                 if (__is_dmac64(ddev)) {
-                        if (direction == DMA_MEM_TO_DEV) {
+                        if (direction == DMA_TO_DEVICE) {
                                 desc->hwdesc.SAR = mem;
                                 desc->hwdesc.DAR = ds->tx_reg;
                         } else {
@@ -878,7 +891,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                         }
                         desc->hwdesc.CNTR = sg_dma_len(sg);
                 } else {
-                        if (direction == DMA_MEM_TO_DEV) {
+                        if (direction == DMA_TO_DEVICE) {
                                 desc->hwdesc32.SAR = mem;
                                 desc->hwdesc32.DAR = ds->tx_reg;
                         } else {
@@ -887,7 +900,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                         }
                         desc->hwdesc32.CNTR = sg_dma_len(sg);
                 }
-                if (direction == DMA_MEM_TO_DEV) {
+                if (direction == DMA_TO_DEVICE) {
                         sai = ds->reg_width;
                         dai = 0;
                 } else {
@@ -959,17 +972,27 @@ txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
                    struct dma_tx_state *txstate)
 {
         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
-        enum dma_status ret;
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
+        int ret;
 
-        ret = dma_cookie_status(chan, cookie, txstate);
+        last_complete = dc->completed;
+        last_used = chan->cookie;
+
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
         if (ret != DMA_SUCCESS) {
                 spin_lock_bh(&dc->lock);
                 txx9dmac_scan_descriptors(dc);
                 spin_unlock_bh(&dc->lock);
 
-                ret = dma_cookie_status(chan, cookie, txstate);
+                last_complete = dc->completed;
+                last_used = chan->cookie;
+
+                ret = dma_async_is_complete(cookie, last_complete, last_used);
         }
 
+        dma_set_tx_state(txstate, last_complete, last_used, 0);
+
         return ret;
 }
 
@@ -1034,7 +1057,7 @@ static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
                 return -EIO;
         }
 
-        dma_cookie_init(chan);
+        dc->completed = chan->cookie = 1;
 
         dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
         txx9dmac_chan_set_SMPCHN(dc);
@@ -1163,7 +1186,7 @@ static int __init txx9dmac_chan_probe(struct platform_device *pdev)
         dc->ddev->chan[ch] = dc;
         dc->chan.device = &dc->dma;
         list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
-        dma_cookie_init(&dc->chan);
+        dc->chan.cookie = dc->completed = 1;
 
         if (is_dmac64(dc))
                 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
diff --git a/drivers/dma/txx9dmac.h b/drivers/dma/txx9dmac.h
index f5a76059888..365d42366b9 100644
--- a/drivers/dma/txx9dmac.h
+++ b/drivers/dma/txx9dmac.h
@@ -172,6 +172,7 @@ struct txx9dmac_chan {
         spinlock_t              lock;
 
         /* these other elements are all protected by lock */
+        dma_cookie_t            completed;
         struct list_head        active_list;
         struct list_head        queue;
         struct list_head        free_list;
diff --git a/drivers/dma/virt-dma.c b/drivers/dma/virt-dma.c
deleted file mode 100644
index 6f80432a3f0..00000000000
--- a/drivers/dma/virt-dma.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Virtual DMA channel support for DMAengine
- *
- * Copyright (C) 2012 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/device.h>
-#include <linux/dmaengine.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-
-#include "virt-dma.h"
-
-static struct virt_dma_desc *to_virt_desc(struct dma_async_tx_descriptor *tx)
-{
-        return container_of(tx, struct virt_dma_desc, tx);
-}
-
-dma_cookie_t vchan_tx_submit(struct dma_async_tx_descriptor *tx)
-{
-        struct virt_dma_chan *vc = to_virt_chan(tx->chan);
-        struct virt_dma_desc *vd = to_virt_desc(tx);
-        unsigned long flags;
-        dma_cookie_t cookie;
-
-        spin_lock_irqsave(&vc->lock, flags);
-        cookie = dma_cookie_assign(tx);
-
-        list_add_tail(&vd->node, &vc->desc_submitted);
-        spin_unlock_irqrestore(&vc->lock, flags);
-
-        dev_dbg(vc->chan.device->dev, "vchan %p: txd %p[%x]: submitted\n",
-                vc, vd, cookie);
-
-        return cookie;
-}
-EXPORT_SYMBOL_GPL(vchan_tx_submit);
-
-struct virt_dma_desc *vchan_find_desc(struct virt_dma_chan *vc,
-        dma_cookie_t cookie)
-{
-        struct virt_dma_desc *vd;
-
-        list_for_each_entry(vd, &vc->desc_issued, node)
-                if (vd->tx.cookie == cookie)
-                        return vd;
-
-        return NULL;
-}
-EXPORT_SYMBOL_GPL(vchan_find_desc);
-
-/*
- * This tasklet handles the completion of a DMA descriptor by
- * calling its callback and freeing it.
- */
-static void vchan_complete(unsigned long arg)
-{
-        struct virt_dma_chan *vc = (struct virt_dma_chan *)arg;
-        struct virt_dma_desc *vd;
-        dma_async_tx_callback cb = NULL;
-        void *cb_data = NULL;
-        LIST_HEAD(head);
-
-        spin_lock_irq(&vc->lock);
-        list_splice_tail_init(&vc->desc_completed, &head);
-        vd = vc->cyclic;
-        if (vd) {
-                vc->cyclic = NULL;
-                cb = vd->tx.callback;
-                cb_data = vd->tx.callback_param;
-        }
-        spin_unlock_irq(&vc->lock);
-
-        if (cb)
-                cb(cb_data);
-
-        while (!list_empty(&head)) {
-                vd = list_first_entry(&head, struct virt_dma_desc, node);
-                cb = vd->tx.callback;
-                cb_data = vd->tx.callback_param;
-
-                list_del(&vd->node);
-
-                vc->desc_free(vd);
-
-                if (cb)
-                        cb(cb_data);
-        }
-}
-
-void vchan_dma_desc_free_list(struct virt_dma_chan *vc, struct list_head *head)
-{
-        while (!list_empty(head)) {
-                struct virt_dma_desc *vd = list_first_entry(head,
-                        struct virt_dma_desc, node);
-                list_del(&vd->node);
-                dev_dbg(vc->chan.device->dev, "txd %p: freeing\n", vd);
-                vc->desc_free(vd);
-        }
-}
-EXPORT_SYMBOL_GPL(vchan_dma_desc_free_list);
-
-void vchan_init(struct virt_dma_chan *vc, struct dma_device *dmadev)
-{
-        dma_cookie_init(&vc->chan);
-
-        spin_lock_init(&vc->lock);
-        INIT_LIST_HEAD(&vc->desc_submitted);
-        INIT_LIST_HEAD(&vc->desc_issued);
-        INIT_LIST_HEAD(&vc->desc_completed);
-
-        tasklet_init(&vc->task, vchan_complete, (unsigned long)vc);
-
-        vc->chan.device = dmadev;
-        list_add_tail(&vc->chan.device_node, &dmadev->channels);
-}
-EXPORT_SYMBOL_GPL(vchan_init);
-
-MODULE_AUTHOR("Russell King");
-MODULE_LICENSE("GPL");
diff --git a/drivers/dma/virt-dma.h b/drivers/dma/virt-dma.h
deleted file mode 100644
index 85c19d63f9f..00000000000
--- a/drivers/dma/virt-dma.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Virtual DMA channel support for DMAengine
- *
- * Copyright (C) 2012 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef VIRT_DMA_H
-#define VIRT_DMA_H
-
-#include <linux/dmaengine.h>
-#include <linux/interrupt.h>
-
-#include "dmaengine.h"
-
-struct virt_dma_desc {
-        struct dma_async_tx_descriptor tx;
-        /* protected by vc.lock */
-        struct list_head node;
-};
-
-struct virt_dma_chan {
-        struct dma_chan chan;
-        struct tasklet_struct task;
-        void (*desc_free)(struct virt_dma_desc *);
-
-        spinlock_t lock;
-
-        /* protected by vc.lock */
-        struct list_head desc_submitted;
-        struct list_head desc_issued;
-        struct list_head desc_completed;
-
-        struct virt_dma_desc *cyclic;
-};
-
-static inline struct virt_dma_chan *to_virt_chan(struct dma_chan *chan)
-{
-        return container_of(chan, struct virt_dma_chan, chan);
-}
-
-void vchan_dma_desc_free_list(struct virt_dma_chan *vc, struct list_head *head);
-void vchan_init(struct virt_dma_chan *vc, struct dma_device *dmadev);
-struct virt_dma_desc *vchan_find_desc(struct virt_dma_chan *, dma_cookie_t);
-
-/**
- * vchan_tx_prep - prepare a descriptor
- * vc: virtual channel allocating this descriptor
- * vd: virtual descriptor to prepare
- * tx_flags: flags argument passed in to prepare function
- */
-static inline struct dma_async_tx_descriptor *vchan_tx_prep(struct virt_dma_chan *vc,
-        struct virt_dma_desc *vd, unsigned long tx_flags)
-{
-        extern dma_cookie_t vchan_tx_submit(struct dma_async_tx_descriptor *);
-
-        dma_async_tx_descriptor_init(&vd->tx, &vc->chan);
-        vd->tx.flags = tx_flags;
-        vd->tx.tx_submit = vchan_tx_submit;
-
-        return &vd->tx;
-}
-
-/**
- * vchan_issue_pending - move submitted descriptors to issued list
- * vc: virtual channel to update
- *
- * vc.lock must be held by caller
- */
-static inline bool vchan_issue_pending(struct virt_dma_chan *vc)
-{
-        list_splice_tail_init(&vc->desc_submitted, &vc->desc_issued);
-        return !list_empty(&vc->desc_issued);
-}
-
-/**
- * vchan_cookie_complete - report completion of a descriptor
- * vd: virtual descriptor to update
- *
- * vc.lock must be held by caller
- */
-static inline void vchan_cookie_complete(struct virt_dma_desc *vd)
-{
-        struct virt_dma_chan *vc = to_virt_chan(vd->tx.chan);
-
-        dma_cookie_complete(&vd->tx);
-        dev_vdbg(vc->chan.device->dev, "txd %p[%x]: marked complete\n",
-                vd, vd->tx.cookie);
-        list_add_tail(&vd->node, &vc->desc_completed);
-
-        tasklet_schedule(&vc->task);
-}
-
-/**
- * vchan_cyclic_callback - report the completion of a period
- * vd: virtual descriptor
- */
-static inline void vchan_cyclic_callback(struct virt_dma_desc *vd)
-{
-        struct virt_dma_chan *vc = to_virt_chan(vd->tx.chan);
-
-        vc->cyclic = vd;
-        tasklet_schedule(&vc->task);
-}
-
-/**
- * vchan_next_desc - peek at the next descriptor to be processed
- * vc: virtual channel to obtain descriptor from
- *
- * vc.lock must be held by caller
- */
-static inline struct virt_dma_desc *vchan_next_desc(struct virt_dma_chan *vc)
-{
-        if (list_empty(&vc->desc_issued))
-                return NULL;
-
-        return list_first_entry(&vc->desc_issued, struct virt_dma_desc, node);
-}
-
-/**
- * vchan_get_all_descriptors - obtain all submitted and issued descriptors
- * vc: virtual channel to get descriptors from
- * head: list of descriptors found
- *
- * vc.lock must be held by caller
- *
- * Removes all submitted and issued descriptors from internal lists, and
- * provides a list of all descriptors found
- */
-static inline void vchan_get_all_descriptors(struct virt_dma_chan *vc,
-        struct list_head *head)
-{
-        list_splice_tail_init(&vc->desc_submitted, head);
-        list_splice_tail_init(&vc->desc_issued, head);
-        list_splice_tail_init(&vc->desc_completed, head);
-}
-
-static inline void vchan_free_chan_resources(struct virt_dma_chan *vc)
-{
-        unsigned long flags;
-        LIST_HEAD(head);
-
-        spin_lock_irqsave(&vc->lock, flags);
-        vchan_get_all_descriptors(vc, &head);
-        spin_unlock_irqrestore(&vc->lock, flags);
-
-        vchan_dma_desc_free_list(vc, &head);
-}
-
-#endif