Patched in Tegra support.

1 files changed, 197 insertions, 607 deletions

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 23c5573e62d..467e4dcb20a 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -9,19 +9,15 @@
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
-#include <linux/export.h>
 #include <linux/dmaengine.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
-#include <linux/pm.h>
-#include <linux/pm_runtime.h>
 #include <linux/err.h>
 #include <linux/amba/bus.h>
-#include <linux/regulator/consumer.h>
-#include <linux/platform_data/dma-ste-dma40.h>
 
-#include "dmaengine.h"
+#include <plat/ste_dma40.h>
+
 #include "ste_dma40_ll.h"
 
 #define D40_NAME "dma40"
@@ -35,9 +31,6 @@
 /* Maximum iterations taken before giving up suspending a channel */
 #define D40_SUSPEND_MAX_IT 500
 
-/* Milliseconds */
-#define DMA40_AUTOSUSPEND_DELAY 100
-
 /* Hardware requirement on LCLA alignment */
 #define LCLA_ALIGNMENT 0x40000
 
@@ -68,71 +61,6 @@ enum d40_command {
         D40_DMA_SUSPENDED       = 3
 };
 
-/*
- * enum d40_events - The different Event Enables for the event lines.
- *
- * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
- * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
- * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
- * @D40_ROUND_EVENTLINE: Status check for event line.
- */
-
-enum d40_events {
-        D40_DEACTIVATE_EVENTLINE        = 0,
-        D40_ACTIVATE_EVENTLINE          = 1,
-        D40_SUSPEND_REQ_EVENTLINE       = 2,
-        D40_ROUND_EVENTLINE             = 3
-};
-
-/*
- * These are the registers that has to be saved and later restored
- * when the DMA hw is powered off.
- * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
- */
-static u32 d40_backup_regs[] = {
-        D40_DREG_LCPA,
-        D40_DREG_LCLA,
-        D40_DREG_PRMSE,
-        D40_DREG_PRMSO,
-        D40_DREG_PRMOE,
-        D40_DREG_PRMOO,
-};
-
-#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
-
-/* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
-static u32 d40_backup_regs_v3[] = {
-        D40_DREG_PSEG1,
-        D40_DREG_PSEG2,
-        D40_DREG_PSEG3,
-        D40_DREG_PSEG4,
-        D40_DREG_PCEG1,
-        D40_DREG_PCEG2,
-        D40_DREG_PCEG3,
-        D40_DREG_PCEG4,
-        D40_DREG_RSEG1,
-        D40_DREG_RSEG2,
-        D40_DREG_RSEG3,
-        D40_DREG_RSEG4,
-        D40_DREG_RCEG1,
-        D40_DREG_RCEG2,
-        D40_DREG_RCEG3,
-        D40_DREG_RCEG4,
-};
-
-#define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
-
-static u32 d40_backup_regs_chan[] = {
-        D40_CHAN_REG_SSCFG,
-        D40_CHAN_REG_SSELT,
-        D40_CHAN_REG_SSPTR,
-        D40_CHAN_REG_SSLNK,
-        D40_CHAN_REG_SDCFG,
-        D40_CHAN_REG_SDELT,
-        D40_CHAN_REG_SDPTR,
-        D40_CHAN_REG_SDLNK,
-};
-
 /**
  * struct d40_lli_pool - Structure for keeping LLIs in memory
  *
@@ -167,7 +95,7 @@ struct d40_lli_pool {
  * during a transfer.
  * @node: List entry.
  * @is_in_client_list: true if the client owns this descriptor.
- * @cyclic: true if this is a cyclic job
+ * the previous one.
  *
  * This descriptor is used for both logical and physical transfers.
  */
@@ -214,7 +142,6 @@ struct d40_lcla_pool {
  * channels.
  *
  * @lock: A lock protection this entity.
- * @reserved: True if used by secure world or otherwise.
  * @num: The physical channel number of this entity.
  * @allocated_src: Bit mapped to show which src event line's are mapped to
  * this physical channel. Can also be free or physically allocated.
@@ -224,7 +151,6 @@ struct d40_lcla_pool {
  */
 struct d40_phy_res {
         spinlock_t lock;
-        bool       reserved;
         int        num;
         u32        allocated_src;
         u32        allocated_dst;
@@ -237,6 +163,8 @@ struct d40_base;
  *
  * @lock: A spinlock to protect this struct.
  * @log_num: The logical number, if any of this channel.
+ * @completed: Starts with 1, after first interrupt it is set to dma engine's
+ * current cookie.
  * @pending_tx: The number of pending transfers. Used between interrupt handler
  * and tasklet.
  * @busy: Set to true when transfer is ongoing on this channel.
@@ -256,6 +184,7 @@ struct d40_base;
  * @src_def_cfg: Default cfg register setting for src.
  * @dst_def_cfg: Default cfg register setting for dst.
  * @log_def: Default logical channel settings.
+ * @lcla: Space for one dst src pair for logical channel transfers.
  * @lcpa: Pointer to dst and src lcpa settings.
  * @runtime_addr: runtime configured address.
  * @runtime_direction: runtime configured direction.
@@ -265,6 +194,8 @@ struct d40_base;
 struct d40_chan {
         spinlock_t                       lock;
         int                              log_num;
+        /* ID of the most recent completed transfer */
+        int                              completed;
         int                              pending_tx;
         bool                             busy;
         struct d40_phy_res              *phy_chan;
@@ -285,7 +216,7 @@ struct d40_chan {
         struct d40_log_lli_full         *lcpa;
         /* Runtime reconfiguration */
         dma_addr_t                      runtime_addr;
-        enum dma_transfer_direction     runtime_direction;
+        enum dma_data_direction         runtime_direction;
 };
 
 /**
@@ -309,7 +240,6 @@ struct d40_chan {
  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
  * @dma_slave: dma_device channels that can do only do slave transfers.
  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
- * @phy_chans: Room for all possible physical channels in system.
  * @log_chans: Room for all possible logical channels in system.
  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
  * to log_chans entries.
@@ -317,20 +247,12 @@ struct d40_chan {
  * to phy_chans entries.
  * @plat_data: Pointer to provided platform_data which is the driver
  * configuration.
- * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
  * @phy_res: Vector containing all physical channels.
  * @lcla_pool: lcla pool settings and data.
  * @lcpa_base: The virtual mapped address of LCPA.
  * @phy_lcpa: The physical address of the LCPA.
  * @lcpa_size: The size of the LCPA area.
  * @desc_slab: cache for descriptors.
- * @reg_val_backup: Here the values of some hardware registers are stored
- * before the DMA is powered off. They are restored when the power is back on.
- * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
- * later.
- * @reg_val_backup_chan: Backup data for standard channel parameter registers.
- * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
- * @initialized: true if the dma has been initialized
  */
 struct d40_base {
         spinlock_t                       interrupt_lock;
@@ -352,7 +274,6 @@ struct d40_base {
         struct d40_chan                 **lookup_log_chans;
         struct d40_chan                 **lookup_phy_chans;
         struct stedma40_platform_data    *plat_data;
-        struct regulator                 *lcpa_regulator;
         /* Physical half channels */
         struct d40_phy_res               *phy_res;
         struct d40_lcla_pool              lcla_pool;
@@ -360,11 +281,6 @@ struct d40_base {
         dma_addr_t                        phy_lcpa;
         resource_size_t                   lcpa_size;
         struct kmem_cache                *desc_slab;
-        u32                               reg_val_backup[BACKUP_REGS_SZ];
-        u32                               reg_val_backup_v3[BACKUP_REGS_SZ_V3];
-        u32                              *reg_val_backup_chan;
-        u16                               gcc_pwr_off_mask;
-        bool                              initialized;
 };
 
 /**
@@ -562,14 +478,13 @@ static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
                 struct d40_desc *d;
                 struct d40_desc *_d;
 
-                list_for_each_entry_safe(d, _d, &d40c->client, node) {
+                list_for_each_entry_safe(d, _d, &d40c->client, node)
                         if (async_tx_test_ack(&d->txd)) {
                                 d40_desc_remove(d);
                                 desc = d;
                                 memset(desc, 0, sizeof(*desc));
                                 break;
                         }
-                }
         }
 
         if (!desc)
@@ -620,7 +535,6 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
         bool cyclic = desc->cyclic;
         int curr_lcla = -EINVAL;
         int first_lcla = 0;
-        bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
         bool linkback;
 
         /*
@@ -693,16 +607,11 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
                                        &lli->src[lli_current],
                                        next_lcla, flags);
 
-                /*
-                 * Cache maintenance is not needed if lcla is
-                 * mapped in esram
-                 */
-                if (!use_esram_lcla) {
-                        dma_sync_single_range_for_device(chan->base->dev,
-                                                pool->dma_addr, lcla_offset,
-                                                2 * sizeof(struct d40_log_lli),
-                                                DMA_TO_DEVICE);
-                }
+                dma_sync_single_range_for_device(chan->base->dev,
+                                        pool->dma_addr, lcla_offset,
+                                        2 * sizeof(struct d40_log_lli),
+                                        DMA_TO_DEVICE);
+
                 curr_lcla = next_lcla;
 
                 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
@@ -830,64 +739,10 @@ static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
         return len;
 }
 
+/* Support functions for logical channels */
 
-#ifdef CONFIG_PM
-static void dma40_backup(void __iomem *baseaddr, u32 *backup,
-                         u32 *regaddr, int num, bool save)
-{
-        int i;
-
-        for (i = 0; i < num; i++) {
-                void __iomem *addr = baseaddr + regaddr[i];
-
-                if (save)
-                        backup[i] = readl_relaxed(addr);
-                else
-                        writel_relaxed(backup[i], addr);
-        }
-}
-
-static void d40_save_restore_registers(struct d40_base *base, bool save)
-{
-        int i;
-
-        /* Save/Restore channel specific registers */
-        for (i = 0; i < base->num_phy_chans; i++) {
-                void __iomem *addr;
-                int idx;
-
-                if (base->phy_res[i].reserved)
-                        continue;
-
-                addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
-                idx = i * ARRAY_SIZE(d40_backup_regs_chan);
-
-                dma40_backup(addr, &base->reg_val_backup_chan[idx],
-                             d40_backup_regs_chan,
-                             ARRAY_SIZE(d40_backup_regs_chan),
-                             save);
-        }
-
-        /* Save/Restore global registers */
-        dma40_backup(base->virtbase, base->reg_val_backup,
-                     d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
-                     save);
-
-        /* Save/Restore registers only existing on dma40 v3 and later */
-        if (base->rev >= 3)
-                dma40_backup(base->virtbase, base->reg_val_backup_v3,
-                             d40_backup_regs_v3,
-                             ARRAY_SIZE(d40_backup_regs_v3),
-                             save);
-}
-#else
-static void d40_save_restore_registers(struct d40_base *base, bool save)
-{
-}
-#endif
-
-static int __d40_execute_command_phy(struct d40_chan *d40c,
-                                     enum d40_command command)
+static int d40_channel_execute_command(struct d40_chan *d40c,
+                                       enum d40_command command)
 {
         u32 status;
         int i;
@@ -896,12 +751,6 @@ static int __d40_execute_command_phy(struct d40_chan *d40c,
         unsigned long flags;
         u32 wmask;
 
-        if (command == D40_DMA_STOP) {
-                ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
-                if (ret)
-                        return ret;
-        }
-
         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
 
         if (d40c->phy_chan->num % 2 == 0)
@@ -995,109 +844,67 @@ static void d40_term_all(struct d40_chan *d40c)
                 }
 
         d40c->pending_tx = 0;
+        d40c->busy = false;
 }
 
-static void __d40_config_set_event(struct d40_chan *d40c,
-                                   enum d40_events event_type, u32 event,
-                                   int reg)
+static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
+                                   u32 event, int reg)
 {
         void __iomem *addr = chan_base(d40c) + reg;
         int tries;
-        u32 status;
-
-        switch (event_type) {
-
-        case D40_DEACTIVATE_EVENTLINE:
 
+        if (!enable) {
                 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
                        | ~D40_EVENTLINE_MASK(event), addr);
-                break;
-
-        case D40_SUSPEND_REQ_EVENTLINE:
-                status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
-                          D40_EVENTLINE_POS(event);
-
-                if (status == D40_DEACTIVATE_EVENTLINE ||
-                    status == D40_SUSPEND_REQ_EVENTLINE)
-                        break;
-
-                writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
-                       | ~D40_EVENTLINE_MASK(event), addr);
-
-                for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
-
-                        status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
-                                  D40_EVENTLINE_POS(event);
-
-                        cpu_relax();
-                        /*
-                         * Reduce the number of bus accesses while
-                         * waiting for the DMA to suspend.
-                         */
-                        udelay(3);
-
-                        if (status == D40_DEACTIVATE_EVENTLINE)
-                                break;
-                }
-
-                if (tries == D40_SUSPEND_MAX_IT) {
-                        chan_err(d40c,
-                                "unable to stop the event_line chl %d (log: %d)"
-                                "status %x\n", d40c->phy_chan->num,
-                                 d40c->log_num, status);
-                }
-                break;
+                return;
+        }
 
-        case D40_ACTIVATE_EVENTLINE:
         /*
          * The hardware sometimes doesn't register the enable when src and dst
          * event lines are active on the same logical channel.  Retry to ensure
          * it does.  Usually only one retry is sufficient.
          */
-                tries = 100;
-                while (--tries) {
-                        writel((D40_ACTIVATE_EVENTLINE <<
-                                D40_EVENTLINE_POS(event)) |
-                                ~D40_EVENTLINE_MASK(event), addr);
-
-                        if (readl(addr) & D40_EVENTLINE_MASK(event))
-                                break;
-                }
-
-                if (tries != 99)
-                        dev_dbg(chan2dev(d40c),
-                                "[%s] workaround enable S%cLNK (%d tries)\n",
-                                __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
-                                100 - tries);
+        tries = 100;
+        while (--tries) {
+                writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
+                       | ~D40_EVENTLINE_MASK(event), addr);
 
-                WARN_ON(!tries);
-                break;
+                if (readl(addr) & D40_EVENTLINE_MASK(event))
+                        break;
+        }
 
-        case D40_ROUND_EVENTLINE:
-                BUG();
-                break;
+        if (tries != 99)
+                dev_dbg(chan2dev(d40c),
+                        "[%s] workaround enable S%cLNK (%d tries)\n",
+                        __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
+                        100 - tries);
 
-        }
+        WARN_ON(!tries);
 }
 
-static void d40_config_set_event(struct d40_chan *d40c,
-                                 enum d40_events event_type)
+static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
 {
+        unsigned long flags;
+
+        spin_lock_irqsave(&d40c->phy_chan->lock, flags);
+
         /* Enable event line connected to device (or memcpy) */
         if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
             (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
 
-                __d40_config_set_event(d40c, event_type, event,
+                __d40_config_set_event(d40c, do_enable, event,
                                        D40_CHAN_REG_SSLNK);
         }
 
         if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
 
-                __d40_config_set_event(d40c, event_type, event,
+                __d40_config_set_event(d40c, do_enable, event,
                                        D40_CHAN_REG_SDLNK);
         }
+
+        spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
 }
 
 static u32 d40_chan_has_events(struct d40_chan *d40c)
@@ -1111,64 +918,6 @@ static u32 d40_chan_has_events(struct d40_chan *d40c)
         return val;
 }
 
-static int
-__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
-{
-        unsigned long flags;
-        int ret = 0;
-        u32 active_status;
-        void __iomem *active_reg;
-
-        if (d40c->phy_chan->num % 2 == 0)
-                active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
-        else
-                active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
-
-
-        spin_lock_irqsave(&d40c->phy_chan->lock, flags);
-
-        switch (command) {
-        case D40_DMA_STOP:
-        case D40_DMA_SUSPEND_REQ:
-
-                active_status = (readl(active_reg) &
-                                 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
-                                 D40_CHAN_POS(d40c->phy_chan->num);
-
-                if (active_status == D40_DMA_RUN)
-                        d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
-                else
-                        d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
-
-                if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
-                        ret = __d40_execute_command_phy(d40c, command);
-
-                break;
-
-        case D40_DMA_RUN:
-
-                d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
-                ret = __d40_execute_command_phy(d40c, command);
-                break;
-
-        case D40_DMA_SUSPENDED:
-                BUG();
-                break;
-        }
-
-        spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
-        return ret;
-}
-
-static int d40_channel_execute_command(struct d40_chan *d40c,
-                                       enum d40_command command)
-{
-        if (chan_is_logical(d40c))
-                return __d40_execute_command_log(d40c, command);
-        else
-                return __d40_execute_command_phy(d40c, command);
-}
-
 static u32 d40_get_prmo(struct d40_chan *d40c)
 {
         static const unsigned int phy_map[] = {
@@ -1223,10 +972,6 @@ static void d40_config_write(struct d40_chan *d40c)
                 /* Set LIDX for lcla */
                 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
                 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
-
-                /* Clear LNK which will be used by d40_chan_has_events() */
-                writel(0, chanbase + D40_CHAN_REG_SSLNK);
-                writel(0, chanbase + D40_CHAN_REG_SDLNK);
         }
 }
 
@@ -1267,13 +1012,19 @@ static int d40_pause(struct d40_chan *d40c)
         if (!d40c->busy)
                 return 0;
 
-        pm_runtime_get_sync(d40c->base->dev);
         spin_lock_irqsave(&d40c->lock, flags);
 
         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
+        if (res == 0) {
+                if (chan_is_logical(d40c)) {
+                        d40_config_set_event(d40c, false);
+                        /* Resume the other logical channels if any */
+                        if (d40_chan_has_events(d40c))
+                                res = d40_channel_execute_command(d40c,
+                                                                  D40_DMA_RUN);
+                }
+        }
 
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
         spin_unlock_irqrestore(&d40c->lock, flags);
         return res;
 }
@@ -1287,18 +1038,44 @@ static int d40_resume(struct d40_chan *d40c)
                 return 0;
 
         spin_lock_irqsave(&d40c->lock, flags);
-        pm_runtime_get_sync(d40c->base->dev);
+
+        if (d40c->base->rev == 0)
+                if (chan_is_logical(d40c)) {
+                        res = d40_channel_execute_command(d40c,
+                                                          D40_DMA_SUSPEND_REQ);
+                        goto no_suspend;
+                }
 
         /* If bytes left to transfer or linked tx resume job */
-        if (d40_residue(d40c) || d40_tx_is_linked(d40c))
+        if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
+
+                if (chan_is_logical(d40c))
+                        d40_config_set_event(d40c, true);
+
                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
+        }
 
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
+no_suspend:
         spin_unlock_irqrestore(&d40c->lock, flags);
         return res;
 }
 
+static int d40_terminate_all(struct d40_chan *chan)
+{
+        unsigned long flags;
+        int ret = 0;
+
+        ret = d40_pause(chan);
+        if (!ret && chan_is_physical(chan))
+                ret = d40_channel_execute_command(chan, D40_DMA_STOP);
+
+        spin_lock_irqsave(&chan->lock, flags);
+        d40_term_all(chan);
+        spin_unlock_irqrestore(&chan->lock, flags);
+
+        return ret;
+}
+
 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 {
         struct d40_chan *d40c = container_of(tx->chan,
@@ -1306,18 +1083,39 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
                                              chan);
         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
         unsigned long flags;
-        dma_cookie_t cookie;
 
         spin_lock_irqsave(&d40c->lock, flags);
-        cookie = dma_cookie_assign(tx);
+
+        d40c->chan.cookie++;
+
+        if (d40c->chan.cookie < 0)
+                d40c->chan.cookie = 1;
+
+        d40d->txd.cookie = d40c->chan.cookie;
+
         d40_desc_queue(d40c, d40d);
+
         spin_unlock_irqrestore(&d40c->lock, flags);
 
-        return cookie;
+        return tx->cookie;
 }
 
 static int d40_start(struct d40_chan *d40c)
 {
+        if (d40c->base->rev == 0) {
+                int err;
+
+                if (chan_is_logical(d40c)) {
+                        err = d40_channel_execute_command(d40c,
+                                                          D40_DMA_SUSPEND_REQ);
+                        if (err)
+                                return err;
+                }
+        }
+
+        if (chan_is_logical(d40c))
+                d40_config_set_event(d40c, true);
+
         return d40_channel_execute_command(d40c, D40_DMA_RUN);
 }
 
@@ -1330,10 +1128,7 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
         d40d = d40_first_queued(d40c);
 
         if (d40d != NULL) {
-                if (!d40c->busy) {
-                        d40c->busy = true;
-                        pm_runtime_get_sync(d40c->base->dev);
-                }
+                d40c->busy = true;
 
                 /* Remove from queue */
                 d40_desc_remove(d40d);
@@ -1394,8 +1189,6 @@ static void dma_tc_handle(struct d40_chan *d40c)
 
                 if (d40_queue_start(d40c) == NULL)
                         d40c->busy = false;
-                pm_runtime_mark_last_busy(d40c->base->dev);
-                pm_runtime_put_autosuspend(d40c->base->dev);
         }
 
         d40c->pending_tx++;
@@ -1419,7 +1212,7 @@ static void dma_tasklet(unsigned long data)
                 goto err;
 
         if (!d40d->cyclic)
-                dma_cookie_complete(&d40d->txd);
+                d40c->completed = d40d->txd.cookie;
 
         /*
          * If terminating a channel pending_tx is set to zero.
@@ -1460,8 +1253,8 @@ static void dma_tasklet(unsigned long data)
 
         return;
 
-err:
-        /* Rescue manouver if receiving double interrupts */
+ err:
+        /* Rescue manoeuvre if receiving double interrupts */
         if (d40c->pending_tx > 0)
                 d40c->pending_tx--;
         spin_unlock_irqrestore(&d40c->lock, flags);
@@ -1611,16 +1404,11 @@ static int d40_validate_conf(struct d40_chan *d40c,
         return res;
 }
 
-static bool d40_alloc_mask_set(struct d40_phy_res *phy,
-                               bool is_src, int log_event_line, bool is_log,
-                               bool *first_user)
+static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
+                               int log_event_line, bool is_log)
 {
         unsigned long flags;
         spin_lock_irqsave(&phy->lock, flags);
-
-        *first_user = ((phy->allocated_src | phy->allocated_dst)
-                        == D40_ALLOC_FREE);
-
         if (!is_log) {
                 /* Physical interrupts are masked per physical full channel */
                 if (phy->allocated_src == D40_ALLOC_FREE &&
@@ -1701,7 +1489,7 @@ out:
         return is_free;
 }
 
-static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
+static int d40_allocate_channel(struct d40_chan *d40c)
 {
         int dev_type;
         int event_group;
@@ -1737,8 +1525,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
                         for (i = 0; i < d40c->base->num_phy_chans; i++) {
 
                                 if (d40_alloc_mask_set(&phys[i], is_src,
-                                                       0, is_log,
-                                                       first_phy_user))
+                                                       0, is_log))
                                         goto found_phy;
                         }
                 } else
@@ -1748,8 +1535,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
                                         if (d40_alloc_mask_set(&phys[i],
                                                                is_src,
                                                                0,
-                                                               is_log,
-                                                               first_phy_user))
+                                                               is_log))
                                                 goto found_phy;
                                 }
                         }
@@ -1765,25 +1551,6 @@ found_phy:
         /* Find logical channel */
         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
                 int phy_num = j + event_group * 2;
-
-                if (d40c->dma_cfg.use_fixed_channel) {
-                        i = d40c->dma_cfg.phy_channel;
-
-                        if ((i != phy_num) && (i != phy_num + 1)) {
-                                dev_err(chan2dev(d40c),
-                                        "invalid fixed phy channel %d\n", i);
-                                return -EINVAL;
-                        }
-
-                        if (d40_alloc_mask_set(&phys[i], is_src, event_line,
-                                               is_log, first_phy_user))
-                                goto found_log;
-
-                        dev_err(chan2dev(d40c),
-                                "could not allocate fixed phy channel %d\n", i);
-                        return -EINVAL;
-                }
-
                 /*
                  * Spread logical channels across all available physical rather
                  * than pack every logical channel at the first available phy
@@ -1792,15 +1559,13 @@ found_phy:
                 if (is_src) {
                         for (i = phy_num; i < phy_num + 2; i++) {
                                 if (d40_alloc_mask_set(&phys[i], is_src,
-                                                       event_line, is_log,
-                                                       first_phy_user))
+                                                       event_line, is_log))
                                         goto found_log;
                         }
                 } else {
                         for (i = phy_num + 1; i >= phy_num; i--) {
                                 if (d40_alloc_mask_set(&phys[i], is_src,
-                                                       event_line, is_log,
-                                                       first_phy_user))
+                                                       event_line, is_log))
                                         goto found_log;
                         }
                 }
@@ -1842,6 +1607,7 @@ static int d40_config_memcpy(struct d40_chan *d40c)
         return 0;
 }
 
+
 static int d40_free_dma(struct d40_chan *d40c)
 {
 
@@ -1876,33 +1642,50 @@ static int d40_free_dma(struct d40_chan *d40c)
                 return -EINVAL;
         }
 
-        pm_runtime_get_sync(d40c->base->dev);
-        res = d40_channel_execute_command(d40c, D40_DMA_STOP);
+        res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
         if (res) {
-                chan_err(d40c, "stop failed\n");
-                goto out;
+                chan_err(d40c, "suspend failed\n");
+                return res;
         }
 
-        d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
+        if (chan_is_logical(d40c)) {
+                /* Release logical channel, deactivate the event line */
 
-        if (chan_is_logical(d40c))
+                d40_config_set_event(d40c, false);
                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
-        else
-                d40c->base->lookup_phy_chans[phy->num] = NULL;
 
-        if (d40c->busy) {
-                pm_runtime_mark_last_busy(d40c->base->dev);
-                pm_runtime_put_autosuspend(d40c->base->dev);
+                /*
+                 * Check if there are more logical allocation
+                 * on this phy channel.
+                 */
+                if (!d40_alloc_mask_free(phy, is_src, event)) {
+                        /* Resume the other logical channels if any */
+                        if (d40_chan_has_events(d40c)) {
+                                res = d40_channel_execute_command(d40c,
+                                                                  D40_DMA_RUN);
+                                if (res) {
+                                        chan_err(d40c,
+                                                "Executing RUN command\n");
+                                        return res;
+                                }
+                        }
+                        return 0;
+                }
+        } else {
+                (void) d40_alloc_mask_free(phy, is_src, 0);
         }
 
-        d40c->busy = false;
+        /* Release physical channel */
+        res = d40_channel_execute_command(d40c, D40_DMA_STOP);
+        if (res) {
+                chan_err(d40c, "Failed to stop channel\n");
+                return res;
+        }
         d40c->phy_chan = NULL;
         d40c->configured = false;
-out:
+        d40c->base->lookup_phy_chans[phy->num] = NULL;
 
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
-        return res;
+        return 0;
 }
 
 static bool d40_is_paused(struct d40_chan *d40c)
@@ -2071,7 +1854,7 @@ err:
 }
 
 static dma_addr_t
-d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
+d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
 {
         struct stedma40_platform_data *plat = chan->base->plat_data;
         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
@@ -2080,9 +1863,9 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
         if (chan->runtime_addr)
                 return chan->runtime_addr;
 
-        if (direction == DMA_DEV_TO_MEM)
+        if (direction == DMA_FROM_DEVICE)
                 addr = plat->dev_rx[cfg->src_dev_type];
-        else if (direction == DMA_MEM_TO_DEV)
+        else if (direction == DMA_TO_DEVICE)
                 addr = plat->dev_tx[cfg->dst_dev_type];
 
         return addr;
@@ -2091,7 +1874,7 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
 static struct dma_async_tx_descriptor *
 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
             struct scatterlist *sg_dst, unsigned int sg_len,
-            enum dma_transfer_direction direction, unsigned long dma_flags)
+            enum dma_data_direction direction, unsigned long dma_flags)
 {
         struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
         dma_addr_t src_dev_addr = 0;
@@ -2115,12 +1898,12 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
         if (sg_next(&sg_src[sg_len - 1]) == sg_src)
                 desc->cyclic = true;
 
-        if (direction != DMA_TRANS_NONE) {
+        if (direction != DMA_NONE) {
                 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
 
-                if (direction == DMA_DEV_TO_MEM)
+                if (direction == DMA_FROM_DEVICE)
                         src_dev_addr = dev_addr;
-                else if (direction == DMA_MEM_TO_DEV)
+                else if (direction == DMA_TO_DEVICE)
                         dst_dev_addr = dev_addr;
         }
 
@@ -2217,7 +2000,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
         bool is_free_phy;
         spin_lock_irqsave(&d40c->lock, flags);
 
-        dma_cookie_init(chan);
+        d40c->completed = chan->cookie = 1;
 
         /* If no dma configuration is set use default configuration (memcpy) */
         if (!d40c->configured) {
@@ -2227,15 +2010,14 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
                         goto fail;
                 }
         }
+        is_free_phy = (d40c->phy_chan == NULL);
 
-        err = d40_allocate_channel(d40c, &is_free_phy);
+        err = d40_allocate_channel(d40c);
         if (err) {
                 chan_err(d40c, "Failed to allocate channel\n");
-                d40c->configured = false;
                 goto fail;
         }
 
-        pm_runtime_get_sync(d40c->base->dev);
         /* Fill in basic CFG register values */
         d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
                     &d40c->dst_def_cfg, chan_is_logical(d40c));
@@ -2255,12 +2037,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
                           D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
         }
 
-        dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
-                 chan_is_logical(d40c) ? "logical" : "physical",
-                 d40c->phy_chan->num,
-                 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
-
-
         /*
          * Only write channel configuration to the DMA if the physical
          * resource is free. In case of multiple logical channels
@@ -2269,8 +2045,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
         if (is_free_phy)
                 d40_config_write(d40c);
 fail:
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
         spin_unlock_irqrestore(&d40c->lock, flags);
         return err;
 }
@@ -2333,11 +2107,10 @@ d40_prep_memcpy_sg(struct dma_chan *chan,
 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
                                                          struct scatterlist *sgl,
                                                          unsigned int sg_len,
-                                                         enum dma_transfer_direction direction,
-                                                         unsigned long dma_flags,
-                                                         void *context)
+                                                         enum dma_data_direction direction,
+                                                         unsigned long dma_flags)
 {
-        if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
+        if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE)
                 return NULL;
 
         return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
@@ -2346,8 +2119,7 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
 static struct dma_async_tx_descriptor *
 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
                      size_t buf_len, size_t period_len,
-                     enum dma_transfer_direction direction, unsigned long flags,
-                     void *context)
+                     enum dma_data_direction direction)
 {
         unsigned int periods = buf_len / period_len;
         struct dma_async_tx_descriptor *txd;
@@ -2362,7 +2134,7 @@ dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
         }
 
         sg[periods].offset = 0;
-        sg_dma_len(&sg[periods]) = 0;
+        sg[periods].length = 0;
         sg[periods].page_link =
                 ((unsigned long)sg | 0x01) & ~0x02;
 
@@ -2379,19 +2151,25 @@ static enum dma_status d40_tx_status(struct dma_chan *chan,
                                      struct dma_tx_state *txstate)
 {
         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
-        enum dma_status ret;
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
+        int ret;
 
         if (d40c->phy_chan == NULL) {
                 chan_err(d40c, "Cannot read status of unallocated channel\n");
                 return -EINVAL;
         }
 
-        ret = dma_cookie_status(chan, cookie, txstate);
-        if (ret != DMA_SUCCESS)
-                dma_set_residue(txstate, stedma40_residue(chan));
+        last_complete = d40c->completed;
+        last_used = chan->cookie;
 
         if (d40_is_paused(d40c))
                 ret = DMA_PAUSED;
+        else
+                ret = dma_async_is_complete(cookie, last_complete, last_used);
+
+        dma_set_tx_state(txstate, last_complete, last_used,
+                         stedma40_residue(chan));
 
         return ret;
 }
@@ -2417,31 +2195,6 @@ static void d40_issue_pending(struct dma_chan *chan)
         spin_unlock_irqrestore(&d40c->lock, flags);
 }
 
-static void d40_terminate_all(struct dma_chan *chan)
-{
-        unsigned long flags;
-        struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
-        int ret;
-
-        spin_lock_irqsave(&d40c->lock, flags);
-
-        pm_runtime_get_sync(d40c->base->dev);
-        ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
-        if (ret)
-                chan_err(d40c, "Failed to stop channel\n");
-
-        d40_term_all(d40c);
-        pm_runtime_mark_last_busy(d40c->base->dev);
-        pm_runtime_put_autosuspend(d40c->base->dev);
-        if (d40c->busy) {
-                pm_runtime_mark_last_busy(d40c->base->dev);
-                pm_runtime_put_autosuspend(d40c->base->dev);
-        }
-        d40c->busy = false;
-
-        spin_unlock_irqrestore(&d40c->lock, flags);
-}
-
 static int
 dma40_config_to_halfchannel(struct d40_chan *d40c,
                             struct stedma40_half_channel_info *info,
@@ -2515,7 +2268,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
         dst_addr_width = config->dst_addr_width;
         dst_maxburst = config->dst_maxburst;
 
-        if (config->direction == DMA_DEV_TO_MEM) {
+        if (config->direction == DMA_FROM_DEVICE) {
                 dma_addr_t dev_addr_rx =
                         d40c->base->plat_data->dev_rx[cfg->src_dev_type];
 
@@ -2538,7 +2291,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
                 if (dst_maxburst == 0)
                         dst_maxburst = src_maxburst;
 
-        } else if (config->direction == DMA_MEM_TO_DEV) {
+        } else if (config->direction == DMA_TO_DEVICE) {
                 dma_addr_t dev_addr_tx =
                         d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
 
@@ -2603,7 +2356,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
                 "configured channel %s for %s, data width %d/%d, "
                 "maxburst %d/%d elements, LE, no flow control\n",
                 dma_chan_name(chan),
-                (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
+                (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
                 src_addr_width, dst_addr_width,
                 src_maxburst, dst_maxburst);
 
@@ -2622,8 +2375,7 @@ static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
         switch (cmd) {
         case DMA_TERMINATE_ALL:
-                d40_terminate_all(chan);
-                return 0;
+                return d40_terminate_all(d40c);
         case DMA_PAUSE:
                 return d40_pause(d40c);
         case DMA_RESUME:
@@ -2766,72 +2518,6 @@ failure1:
         return err;
 }
 
-/* Suspend resume functionality */
-#ifdef CONFIG_PM
-static int dma40_pm_suspend(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct d40_base *base = platform_get_drvdata(pdev);
-        int ret = 0;
-        if (!pm_runtime_suspended(dev))
-                return -EBUSY;
-
-        if (base->lcpa_regulator)
-                ret = regulator_disable(base->lcpa_regulator);
-        return ret;
-}
-
-static int dma40_runtime_suspend(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct d40_base *base = platform_get_drvdata(pdev);
-
-        d40_save_restore_registers(base, true);
-
-        /* Don't disable/enable clocks for v1 due to HW bugs */
-        if (base->rev != 1)
-                writel_relaxed(base->gcc_pwr_off_mask,
-                               base->virtbase + D40_DREG_GCC);
-
-        return 0;
-}
-
-static int dma40_runtime_resume(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct d40_base *base = platform_get_drvdata(pdev);
-
-        if (base->initialized)
-                d40_save_restore_registers(base, false);
-
-        writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
-                       base->virtbase + D40_DREG_GCC);
-        return 0;
-}
-
-static int dma40_resume(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct d40_base *base = platform_get_drvdata(pdev);
-        int ret = 0;
-
-        if (base->lcpa_regulator)
-                ret = regulator_enable(base->lcpa_regulator);
-
-        return ret;
-}
-
-static const struct dev_pm_ops dma40_pm_ops = {
-        .suspend                = dma40_pm_suspend,
-        .runtime_suspend        = dma40_runtime_suspend,
-        .runtime_resume         = dma40_runtime_resume,
-        .resume                 = dma40_resume,
-};
-#define DMA40_PM_OPS    (&dma40_pm_ops)
-#else
-#define DMA40_PM_OPS    NULL
-#endif
-
 /* Initialization functions. */
 
 static int __init d40_phy_res_init(struct d40_base *base)
@@ -2840,7 +2526,6 @@ static int __init d40_phy_res_init(struct d40_base *base)
         int num_phy_chans_avail = 0;
         u32 val[2];
         int odd_even_bit = -2;
-        int gcc = D40_DREG_GCC_ENA;
 
         val[0] = readl(base->virtbase + D40_DREG_PRSME);
         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
@@ -2852,17 +2537,9 @@ static int __init d40_phy_res_init(struct d40_base *base)
                         /* Mark security only channels as occupied */
                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
-                        base->phy_res[i].reserved = true;
-                        gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
-                                                       D40_DREG_GCC_SRC);
-                        gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
-                                                       D40_DREG_GCC_DST);
-
-
                 } else {
                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
-                        base->phy_res[i].reserved = false;
                         num_phy_chans_avail++;
                 }
                 spin_lock_init(&base->phy_res[i].lock);
@@ -2874,11 +2551,6 @@ static int __init d40_phy_res_init(struct d40_base *base)
 
                 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
                 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
-                base->phy_res[chan].reserved = true;
-                gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
-                                               D40_DREG_GCC_SRC);
-                gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
-                                               D40_DREG_GCC_DST);
                 num_phy_chans_avail--;
         }
 
@@ -2899,15 +2571,6 @@ static int __init d40_phy_res_init(struct d40_base *base)
                 val[0] = val[0] >> 2;
         }
 
-        /*
-         * To keep things simple, Enable all clocks initially.
-         * The clocks will get managed later post channel allocation.
-         * The clocks for the event lines on which reserved channels exists
-         * are not managed here.
-         */
-        writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
-        base->gcc_pwr_off_mask = gcc;
-
         return num_phy_chans_avail;
 }
 
@@ -2920,23 +2583,19 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
         struct d40_base *base = NULL;
         int num_log_chans = 0;
         int num_phy_chans;
-        int clk_ret = -EINVAL;
         int i;
         u32 pid;
         u32 cid;
         u8 rev;
 
         clk = clk_get(&pdev->dev, NULL);
+
         if (IS_ERR(clk)) {
                 d40_err(&pdev->dev, "No matching clock found\n");
                 goto failure;
         }
 
-        clk_ret = clk_prepare_enable(clk);
-        if (clk_ret) {
-                d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
-                goto failure;
-        }
+        clk_enable(clk);
 
         /* Get IO for DMAC base address */
         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
@@ -2984,12 +2643,6 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
         dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
                  rev, res->start);
 
-        if (rev < 2) {
-                d40_err(&pdev->dev, "hardware revision: %d is not supported",
-                        rev);
-                goto failure;
-        }
-
         plat_data = pdev->dev.platform_data;
 
         /* Count the number of logical channels in use */
@@ -3045,15 +2698,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
                         goto failure;
         }
 
-        base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
-                                            sizeof(d40_backup_regs_chan),
+        base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
+                                            sizeof(struct d40_desc *) *
+                                            D40_LCLA_LINK_PER_EVENT_GRP,
                                             GFP_KERNEL);
-        if (!base->reg_val_backup_chan)
-                goto failure;
-
-        base->lcla_pool.alloc_map =
-                kzalloc(num_phy_chans * sizeof(struct d40_desc *)
-                        * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
         if (!base->lcla_pool.alloc_map)
                 goto failure;
 
@@ -3066,10 +2714,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
         return base;
 
 failure:
-        if (!clk_ret)
-                clk_disable_unprepare(clk);
-        if (!IS_ERR(clk))
+        if (!IS_ERR(clk)) {
+                clk_disable(clk);
                 clk_put(clk);
+        }
         if (virtbase)
                 iounmap(virtbase);
         if (res)
@@ -3080,7 +2728,6 @@ failure:
 
         if (base) {
                 kfree(base->lcla_pool.alloc_map);
-                kfree(base->reg_val_backup_chan);
                 kfree(base->lookup_log_chans);
                 kfree(base->lookup_phy_chans);
                 kfree(base->phy_res);
@@ -3093,9 +2740,9 @@ failure:
 static void __init d40_hw_init(struct d40_base *base)
 {
 
-        static struct d40_reg_val dma_init_reg[] = {
+        static const struct d40_reg_val dma_init_reg[] = {
                 /* Clock every part of the DMA block from start */
-                { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
+                { .reg = D40_DREG_GCC,    .val = 0x0000ff01},
 
                 /* Interrupts on all logical channels */
                 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
@@ -3295,31 +2942,11 @@ static int __init d40_probe(struct platform_device *pdev)
                 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
                 goto failure;
         }
-        /* If lcla has to be located in ESRAM we don't need to allocate */
-        if (base->plat_data->use_esram_lcla) {
-                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-                                                        "lcla_esram");
-                if (!res) {
-                        ret = -ENOENT;
-                        d40_err(&pdev->dev,
-                                "No \"lcla_esram\" memory resource\n");
-                        goto failure;
-                }
-                base->lcla_pool.base = ioremap(res->start,
-                                                resource_size(res));
-                if (!base->lcla_pool.base) {
-                        ret = -ENOMEM;
-                        d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
-                        goto failure;
-                }
-                writel(res->start, base->virtbase + D40_DREG_LCLA);
 
-        } else {
-                ret = d40_lcla_allocate(base);
-                if (ret) {
-                        d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
-                        goto failure;
-                }
+        ret = d40_lcla_allocate(base);
+        if (ret) {
+                d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
+                goto failure;
         }
 
         spin_lock_init(&base->lcla_pool.lock);
@@ -3332,32 +2959,6 @@ static int __init d40_probe(struct platform_device *pdev)
                 goto failure;
         }
 
-        pm_runtime_irq_safe(base->dev);
-        pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
-        pm_runtime_use_autosuspend(base->dev);
-        pm_runtime_enable(base->dev);
-        pm_runtime_resume(base->dev);
-
-        if (base->plat_data->use_esram_lcla) {
-
-                base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
-                if (IS_ERR(base->lcpa_regulator)) {
-                        d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
-                        base->lcpa_regulator = NULL;
-                        goto failure;
-                }
-
-                ret = regulator_enable(base->lcpa_regulator);
-                if (ret) {
-                        d40_err(&pdev->dev,
-                                "Failed to enable lcpa_regulator\n");
-                        regulator_put(base->lcpa_regulator);
-                        base->lcpa_regulator = NULL;
-                        goto failure;
-                }
-        }
-
-        base->initialized = true;
         err = d40_dmaengine_init(base, num_reserved_chans);
         if (err)
                 goto failure;
@@ -3374,11 +2975,6 @@ failure:
                 if (base->virtbase)
                         iounmap(base->virtbase);
 
-                if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
-                        iounmap(base->lcla_pool.base);
-                        base->lcla_pool.base = NULL;
-                }
-
                 if (base->lcla_pool.dma_addr)
                         dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
                                          SZ_1K * base->num_phy_chans,
@@ -3401,11 +2997,6 @@ failure:
                         clk_put(base->clk);
                 }
 
-                if (base->lcpa_regulator) {
-                        regulator_disable(base->lcpa_regulator);
-                        regulator_put(base->lcpa_regulator);
-                }
-
                 kfree(base->lcla_pool.alloc_map);
                 kfree(base->lookup_log_chans);
                 kfree(base->lookup_phy_chans);
@@ -3421,7 +3012,6 @@ static struct platform_driver d40_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name  = D40_NAME,
-                .pm = DMA40_PM_OPS,
         },
 };