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authorPaul Walmsley <paul@pwsan.com>2012-09-10 16:17:50 -0400
committerPaul Walmsley <paul@pwsan.com>2012-11-12 21:18:50 -0500
commite127539fb355848b5e3f08d97b4df49c83789aa1 (patch)
tree2138c240d6910811d59d1d8d23c45bd1020ed46c /arch
parent368edee33ea929434cd950b8eeb77fa296df882e (diff)
ARM: AM33xx: clock: drop obsolete clock data
Drop the now-obsolete AM33xx original OMAP clock data. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock33xx_data.c1107
1 files changed, 0 insertions, 1107 deletions
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
deleted file mode 100644
index 1cb79cc5808..00000000000
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ /dev/null
@@ -1,1107 +0,0 @@
1/*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20
21#include "soc.h"
22#include "iomap.h"
23#include "control.h"
24#include "clock.h"
25#include "cm.h"
26#include "cm33xx.h"
27#include "cm-regbits-33xx.h"
28#include "prm.h"
29
30/* Maximum DPLL multiplier, divider values for AM33XX */
31#define AM33XX_MAX_DPLL_MULT 2047
32#define AM33XX_MAX_DPLL_DIV 128
33
34/* Modulemode control */
35#define AM33XX_MODULEMODE_HWCTRL 0
36#define AM33XX_MODULEMODE_SWCTRL 1
37
38/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
39 * physically present, in such a case HWMOD enabling of
40 * clock would be failure with default parent. And timer
41 * probe thinks clock is already enabled, this leads to
42 * crash upon accessing timer 3 & 6 registers in probe.
43 * Fix by setting parent of both these timers to master
44 * oscillator clock.
45 */
46static inline void am33xx_init_timer_parent(struct clk *clk)
47{
48 omap2_clksel_set_parent(clk, clk->parent);
49}
50
51/* Root clocks */
52
53/* RTC 32k */
54static struct clk clk_32768_ck = {
55 .name = "clk_32768_ck",
56 .clkdm_name = "l4_rtc_clkdm",
57 .rate = 32768,
58 .ops = &clkops_null,
59};
60
61/* On-Chip 32KHz RC OSC */
62static struct clk clk_rc32k_ck = {
63 .name = "clk_rc32k_ck",
64 .rate = 32000,
65 .ops = &clkops_null,
66};
67
68/* Crystal input clks */
69static struct clk virt_24000000_ck = {
70 .name = "virt_24000000_ck",
71 .rate = 24000000,
72 .ops = &clkops_null,
73};
74
75static struct clk virt_25000000_ck = {
76 .name = "virt_25000000_ck",
77 .rate = 25000000,
78 .ops = &clkops_null,
79};
80
81/* Oscillator clock */
82/* 19.2, 24, 25 or 26 MHz */
83static const struct clksel sys_clkin_sel[] = {
84 { .parent = &virt_19200000_ck, .rates = div_1_0_rates },
85 { .parent = &virt_24000000_ck, .rates = div_1_1_rates },
86 { .parent = &virt_25000000_ck, .rates = div_1_2_rates },
87 { .parent = &virt_26000000_ck, .rates = div_1_3_rates },
88 { .parent = NULL },
89};
90
91/* External clock - 12 MHz */
92static struct clk tclkin_ck = {
93 .name = "tclkin_ck",
94 .rate = 12000000,
95 .ops = &clkops_null,
96};
97
98/*
99 * sys_clk in: input to the dpll and also used as funtional clock for,
100 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
101 *
102 */
103static struct clk sys_clkin_ck = {
104 .name = "sys_clkin_ck",
105 .parent = &virt_24000000_ck,
106 .init = &omap2_init_clksel_parent,
107 .clksel_reg = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
108 .clksel_mask = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK,
109 .clksel = sys_clkin_sel,
110 .ops = &clkops_null,
111 .recalc = &omap2_clksel_recalc,
112};
113
114/* DPLL_CORE */
115static struct dpll_data dpll_core_dd = {
116 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
117 .clk_bypass = &sys_clkin_ck,
118 .clk_ref = &sys_clkin_ck,
119 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
120 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
121 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
122 .mult_mask = AM33XX_DPLL_MULT_MASK,
123 .div1_mask = AM33XX_DPLL_DIV_MASK,
124 .enable_mask = AM33XX_DPLL_EN_MASK,
125 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
126 .max_multiplier = AM33XX_MAX_DPLL_MULT,
127 .max_divider = AM33XX_MAX_DPLL_DIV,
128 .min_divider = 1,
129};
130
131/* CLKDCOLDO output */
132static struct clk dpll_core_ck = {
133 .name = "dpll_core_ck",
134 .parent = &sys_clkin_ck,
135 .dpll_data = &dpll_core_dd,
136 .init = &omap2_init_dpll_parent,
137 .ops = &clkops_omap3_core_dpll_ops,
138 .recalc = &omap3_dpll_recalc,
139};
140
141static struct clk dpll_core_x2_ck = {
142 .name = "dpll_core_x2_ck",
143 .parent = &dpll_core_ck,
144 .flags = CLOCK_CLKOUTX2,
145 .ops = &clkops_null,
146 .recalc = &omap3_clkoutx2_recalc,
147};
148
149
150static const struct clksel dpll_core_m4_div[] = {
151 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
152 { .parent = NULL },
153};
154
155static struct clk dpll_core_m4_ck = {
156 .name = "dpll_core_m4_ck",
157 .parent = &dpll_core_x2_ck,
158 .init = &omap2_init_clksel_parent,
159 .clksel = dpll_core_m4_div,
160 .clksel_reg = AM33XX_CM_DIV_M4_DPLL_CORE,
161 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
162 .ops = &clkops_null,
163 .recalc = &omap2_clksel_recalc,
164 .round_rate = &omap2_clksel_round_rate,
165 .set_rate = &omap2_clksel_set_rate,
166};
167
168static const struct clksel dpll_core_m5_div[] = {
169 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
170 { .parent = NULL },
171};
172
173static struct clk dpll_core_m5_ck = {
174 .name = "dpll_core_m5_ck",
175 .parent = &dpll_core_x2_ck,
176 .init = &omap2_init_clksel_parent,
177 .clksel = dpll_core_m5_div,
178 .clksel_reg = AM33XX_CM_DIV_M5_DPLL_CORE,
179 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
180 .ops = &clkops_null,
181 .recalc = &omap2_clksel_recalc,
182 .round_rate = &omap2_clksel_round_rate,
183 .set_rate = &omap2_clksel_set_rate,
184};
185
186static const struct clksel dpll_core_m6_div[] = {
187 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
188 { .parent = NULL },
189};
190
191static struct clk dpll_core_m6_ck = {
192 .name = "dpll_core_m6_ck",
193 .parent = &dpll_core_x2_ck,
194 .init = &omap2_init_clksel_parent,
195 .clksel = dpll_core_m6_div,
196 .clksel_reg = AM33XX_CM_DIV_M6_DPLL_CORE,
197 .clksel_mask = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
198 .ops = &clkops_null,
199 .recalc = &omap2_clksel_recalc,
200 .round_rate = &omap2_clksel_round_rate,
201 .set_rate = &omap2_clksel_set_rate,
202};
203
204/* DPLL_MPU */
205static struct dpll_data dpll_mpu_dd = {
206 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
207 .clk_bypass = &sys_clkin_ck,
208 .clk_ref = &sys_clkin_ck,
209 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
210 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
211 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
212 .mult_mask = AM33XX_DPLL_MULT_MASK,
213 .div1_mask = AM33XX_DPLL_DIV_MASK,
214 .enable_mask = AM33XX_DPLL_EN_MASK,
215 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
216 .max_multiplier = AM33XX_MAX_DPLL_MULT,
217 .max_divider = AM33XX_MAX_DPLL_DIV,
218 .min_divider = 1,
219};
220
221/* CLKOUT: fdpll/M2 */
222static struct clk dpll_mpu_ck = {
223 .name = "dpll_mpu_ck",
224 .parent = &sys_clkin_ck,
225 .dpll_data = &dpll_mpu_dd,
226 .init = &omap2_init_dpll_parent,
227 .ops = &clkops_omap3_noncore_dpll_ops,
228 .recalc = &omap3_dpll_recalc,
229 .round_rate = &omap2_dpll_round_rate,
230 .set_rate = &omap3_noncore_dpll_set_rate,
231};
232
233/*
234 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
235 * and ALT_CLK1/2)
236 */
237static const struct clksel dpll_mpu_m2_div[] = {
238 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
239 { .parent = NULL },
240};
241
242static struct clk dpll_mpu_m2_ck = {
243 .name = "dpll_mpu_m2_ck",
244 .clkdm_name = "mpu_clkdm",
245 .parent = &dpll_mpu_ck,
246 .clksel = dpll_mpu_m2_div,
247 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_MPU,
248 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
249 .ops = &clkops_null,
250 .recalc = &omap2_clksel_recalc,
251 .round_rate = &omap2_clksel_round_rate,
252 .set_rate = &omap2_clksel_set_rate,
253};
254
255/* DPLL_DDR */
256static struct dpll_data dpll_ddr_dd = {
257 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
258 .clk_bypass = &sys_clkin_ck,
259 .clk_ref = &sys_clkin_ck,
260 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
261 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
262 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
263 .mult_mask = AM33XX_DPLL_MULT_MASK,
264 .div1_mask = AM33XX_DPLL_DIV_MASK,
265 .enable_mask = AM33XX_DPLL_EN_MASK,
266 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
267 .max_multiplier = AM33XX_MAX_DPLL_MULT,
268 .max_divider = AM33XX_MAX_DPLL_DIV,
269 .min_divider = 1,
270};
271
272/* CLKOUT: fdpll/M2 */
273static struct clk dpll_ddr_ck = {
274 .name = "dpll_ddr_ck",
275 .parent = &sys_clkin_ck,
276 .dpll_data = &dpll_ddr_dd,
277 .init = &omap2_init_dpll_parent,
278 .ops = &clkops_null,
279 .recalc = &omap3_dpll_recalc,
280};
281
282/*
283 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
284 * and ALT_CLK1/2)
285 */
286static const struct clksel dpll_ddr_m2_div[] = {
287 { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
288 { .parent = NULL },
289};
290
291static struct clk dpll_ddr_m2_ck = {
292 .name = "dpll_ddr_m2_ck",
293 .parent = &dpll_ddr_ck,
294 .clksel = dpll_ddr_m2_div,
295 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DDR,
296 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
297 .ops = &clkops_null,
298 .recalc = &omap2_clksel_recalc,
299 .round_rate = &omap2_clksel_round_rate,
300 .set_rate = &omap2_clksel_set_rate,
301};
302
303/* emif_fck functional clock */
304static struct clk dpll_ddr_m2_div2_ck = {
305 .name = "dpll_ddr_m2_div2_ck",
306 .clkdm_name = "l3_clkdm",
307 .parent = &dpll_ddr_m2_ck,
308 .ops = &clkops_null,
309 .fixed_div = 2,
310 .recalc = &omap_fixed_divisor_recalc,
311};
312
313/* DPLL_DISP */
314static struct dpll_data dpll_disp_dd = {
315 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
316 .clk_bypass = &sys_clkin_ck,
317 .clk_ref = &sys_clkin_ck,
318 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
319 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
320 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
321 .mult_mask = AM33XX_DPLL_MULT_MASK,
322 .div1_mask = AM33XX_DPLL_DIV_MASK,
323 .enable_mask = AM33XX_DPLL_EN_MASK,
324 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
325 .max_multiplier = AM33XX_MAX_DPLL_MULT,
326 .max_divider = AM33XX_MAX_DPLL_DIV,
327 .min_divider = 1,
328};
329
330/* CLKOUT: fdpll/M2 */
331static struct clk dpll_disp_ck = {
332 .name = "dpll_disp_ck",
333 .parent = &sys_clkin_ck,
334 .dpll_data = &dpll_disp_dd,
335 .init = &omap2_init_dpll_parent,
336 .ops = &clkops_null,
337 .recalc = &omap3_dpll_recalc,
338 .round_rate = &omap2_dpll_round_rate,
339 .set_rate = &omap3_noncore_dpll_set_rate,
340};
341
342/*
343 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
344 * and ALT_CLK1/2)
345 */
346static const struct clksel dpll_disp_m2_div[] = {
347 { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
348 { .parent = NULL },
349};
350
351static struct clk dpll_disp_m2_ck = {
352 .name = "dpll_disp_m2_ck",
353 .parent = &dpll_disp_ck,
354 .clksel = dpll_disp_m2_div,
355 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DISP,
356 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
357 .ops = &clkops_null,
358 .recalc = &omap2_clksel_recalc,
359 .round_rate = &omap2_clksel_round_rate,
360 .set_rate = &omap2_clksel_set_rate,
361};
362
363/* DPLL_PER */
364static struct dpll_data dpll_per_dd = {
365 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
366 .clk_bypass = &sys_clkin_ck,
367 .clk_ref = &sys_clkin_ck,
368 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
369 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
370 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
371 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
372 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
373 .enable_mask = AM33XX_DPLL_EN_MASK,
374 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
375 .max_multiplier = AM33XX_MAX_DPLL_MULT,
376 .max_divider = AM33XX_MAX_DPLL_DIV,
377 .min_divider = 1,
378 .flags = DPLL_J_TYPE,
379};
380
381/* CLKDCOLDO */
382static struct clk dpll_per_ck = {
383 .name = "dpll_per_ck",
384 .parent = &sys_clkin_ck,
385 .dpll_data = &dpll_per_dd,
386 .init = &omap2_init_dpll_parent,
387 .ops = &clkops_null,
388 .recalc = &omap3_dpll_recalc,
389 .round_rate = &omap2_dpll_round_rate,
390 .set_rate = &omap3_noncore_dpll_set_rate,
391};
392
393/* CLKOUT: fdpll/M2 */
394static const struct clksel dpll_per_m2_div[] = {
395 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
396 { .parent = NULL },
397};
398
399static struct clk dpll_per_m2_ck = {
400 .name = "dpll_per_m2_ck",
401 .parent = &dpll_per_ck,
402 .clksel = dpll_per_m2_div,
403 .clksel_reg = AM33XX_CM_DIV_M2_DPLL_PER,
404 .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
405 .ops = &clkops_null,
406 .recalc = &omap2_clksel_recalc,
407 .round_rate = &omap2_clksel_round_rate,
408 .set_rate = &omap2_clksel_set_rate,
409};
410
411static struct clk dpll_per_m2_div4_wkupdm_ck = {
412 .name = "dpll_per_m2_div4_wkupdm_ck",
413 .clkdm_name = "l4_wkup_clkdm",
414 .parent = &dpll_per_m2_ck,
415 .fixed_div = 4,
416 .ops = &clkops_null,
417 .recalc = &omap_fixed_divisor_recalc,
418};
419
420static struct clk dpll_per_m2_div4_ck = {
421 .name = "dpll_per_m2_div4_ck",
422 .clkdm_name = "l4ls_clkdm",
423 .parent = &dpll_per_m2_ck,
424 .fixed_div = 4,
425 .ops = &clkops_null,
426 .recalc = &omap_fixed_divisor_recalc,
427};
428
429static struct clk l3_gclk = {
430 .name = "l3_gclk",
431 .clkdm_name = "l3_clkdm",
432 .parent = &dpll_core_m4_ck,
433 .ops = &clkops_null,
434 .recalc = &followparent_recalc,
435};
436
437static struct clk dpll_core_m4_div2_ck = {
438 .name = "dpll_core_m4_div2_ck",
439 .clkdm_name = "l4_wkup_clkdm",
440 .parent = &dpll_core_m4_ck,
441 .ops = &clkops_null,
442 .fixed_div = 2,
443 .recalc = &omap_fixed_divisor_recalc,
444};
445
446static struct clk l4_rtc_gclk = {
447 .name = "l4_rtc_gclk",
448 .parent = &dpll_core_m4_ck,
449 .ops = &clkops_null,
450 .fixed_div = 2,
451 .recalc = &omap_fixed_divisor_recalc,
452};
453
454static struct clk clk_24mhz = {
455 .name = "clk_24mhz",
456 .parent = &dpll_per_m2_ck,
457 .fixed_div = 8,
458 .ops = &clkops_null,
459 .recalc = &omap_fixed_divisor_recalc,
460};
461
462/*
463 * Below clock nodes describes clockdomains derived out
464 * of core clock.
465 */
466static struct clk l4hs_gclk = {
467 .name = "l4hs_gclk",
468 .clkdm_name = "l4hs_clkdm",
469 .parent = &dpll_core_m4_ck,
470 .ops = &clkops_null,
471 .recalc = &followparent_recalc,
472};
473
474static struct clk l3s_gclk = {
475 .name = "l3s_gclk",
476 .clkdm_name = "l3s_clkdm",
477 .parent = &dpll_core_m4_div2_ck,
478 .ops = &clkops_null,
479 .recalc = &followparent_recalc,
480};
481
482static struct clk l4fw_gclk = {
483 .name = "l4fw_gclk",
484 .clkdm_name = "l4fw_clkdm",
485 .parent = &dpll_core_m4_div2_ck,
486 .ops = &clkops_null,
487 .recalc = &followparent_recalc,
488};
489
490static struct clk l4ls_gclk = {
491 .name = "l4ls_gclk",
492 .clkdm_name = "l4ls_clkdm",
493 .parent = &dpll_core_m4_div2_ck,
494 .ops = &clkops_null,
495 .recalc = &followparent_recalc,
496};
497
498static struct clk sysclk_div_ck = {
499 .name = "sysclk_div_ck",
500 .parent = &dpll_core_m4_ck,
501 .ops = &clkops_null,
502 .recalc = &followparent_recalc,
503};
504
505/*
506 * In order to match the clock domain with hwmod clockdomain entry,
507 * separate clock nodes is required for the modules which are
508 * directly getting their funtioncal clock from sys_clkin.
509 */
510static struct clk adc_tsc_fck = {
511 .name = "adc_tsc_fck",
512 .clkdm_name = "l4_wkup_clkdm",
513 .parent = &sys_clkin_ck,
514 .ops = &clkops_null,
515 .recalc = &followparent_recalc,
516};
517
518static struct clk dcan0_fck = {
519 .name = "dcan0_fck",
520 .clkdm_name = "l4ls_clkdm",
521 .parent = &sys_clkin_ck,
522 .ops = &clkops_null,
523 .recalc = &followparent_recalc,
524};
525
526static struct clk dcan1_fck = {
527 .name = "dcan1_fck",
528 .clkdm_name = "l4ls_clkdm",
529 .parent = &sys_clkin_ck,
530 .ops = &clkops_null,
531 .recalc = &followparent_recalc,
532};
533
534static struct clk mcasp0_fck = {
535 .name = "mcasp0_fck",
536 .clkdm_name = "l3s_clkdm",
537 .parent = &sys_clkin_ck,
538 .ops = &clkops_null,
539 .recalc = &followparent_recalc,
540};
541
542static struct clk mcasp1_fck = {
543 .name = "mcasp1_fck",
544 .clkdm_name = "l3s_clkdm",
545 .parent = &sys_clkin_ck,
546 .ops = &clkops_null,
547 .recalc = &followparent_recalc,
548};
549
550static struct clk smartreflex0_fck = {
551 .name = "smartreflex0_fck",
552 .clkdm_name = "l4_wkup_clkdm",
553 .parent = &sys_clkin_ck,
554 .ops = &clkops_null,
555 .recalc = &followparent_recalc,
556};
557
558static struct clk smartreflex1_fck = {
559 .name = "smartreflex1_fck",
560 .clkdm_name = "l4_wkup_clkdm",
561 .parent = &sys_clkin_ck,
562 .ops = &clkops_null,
563 .recalc = &followparent_recalc,
564};
565
566/*
567 * Modules clock nodes
568 *
569 * The following clock leaf nodes are added for the moment because:
570 *
571 * - hwmod data is not present for these modules, either hwmod
572 * control is not required or its not populated.
573 * - Driver code is not yet migrated to use hwmod/runtime pm
574 * - Modules outside kernel access (to disable them by default)
575 *
576 * - debugss
577 * - mmu (gfx domain)
578 * - cefuse
579 * - usbotg_fck (its additional clock and not really a modulemode)
580 * - ieee5000
581 */
582static struct clk debugss_ick = {
583 .name = "debugss_ick",
584 .clkdm_name = "l3_aon_clkdm",
585 .parent = &dpll_core_m4_ck,
586 .ops = &clkops_omap2_dflt,
587 .enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
588 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
589 .recalc = &followparent_recalc,
590};
591
592static struct clk mmu_fck = {
593 .name = "mmu_fck",
594 .clkdm_name = "gfx_l3_clkdm",
595 .parent = &dpll_core_m4_ck,
596 .ops = &clkops_omap2_dflt,
597 .enable_reg = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
598 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
599 .recalc = &followparent_recalc,
600};
601
602static struct clk cefuse_fck = {
603 .name = "cefuse_fck",
604 .clkdm_name = "l4_cefuse_clkdm",
605 .parent = &sys_clkin_ck,
606 .enable_reg = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
607 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
608 .ops = &clkops_omap2_dflt,
609 .recalc = &followparent_recalc,
610};
611
612/*
613 * clkdiv32 is generated from fixed division of 732.4219
614 */
615static struct clk clkdiv32k_ick = {
616 .name = "clkdiv32k_ick",
617 .clkdm_name = "clk_24mhz_clkdm",
618 .rate = 32768,
619 .parent = &clk_24mhz,
620 .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
621 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
622 .ops = &clkops_omap2_dflt,
623};
624
625static struct clk usbotg_fck = {
626 .name = "usbotg_fck",
627 .clkdm_name = "l3s_clkdm",
628 .parent = &dpll_per_ck,
629 .enable_reg = AM33XX_CM_CLKDCOLDO_DPLL_PER,
630 .enable_bit = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
631 .ops = &clkops_omap2_dflt,
632 .recalc = &followparent_recalc,
633};
634
635static struct clk ieee5000_fck = {
636 .name = "ieee5000_fck",
637 .clkdm_name = "l3s_clkdm",
638 .parent = &dpll_core_m4_div2_ck,
639 .enable_reg = AM33XX_CM_PER_IEEE5000_CLKCTRL,
640 .enable_bit = AM33XX_MODULEMODE_SWCTRL,
641 .ops = &clkops_omap2_dflt,
642 .recalc = &followparent_recalc,
643};
644
645/* Timers */
646static const struct clksel timer1_clkmux_sel[] = {
647 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
648 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
649 { .parent = &tclkin_ck, .rates = div_1_2_rates },
650 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
651 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
652 { .parent = NULL },
653};
654
655static struct clk timer1_fck = {
656 .name = "timer1_fck",
657 .clkdm_name = "l4ls_clkdm",
658 .parent = &sys_clkin_ck,
659 .init = &omap2_init_clksel_parent,
660 .clksel = timer1_clkmux_sel,
661 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
662 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
663 .ops = &clkops_null,
664 .recalc = &omap2_clksel_recalc,
665};
666
667static const struct clksel timer2_to_7_clk_sel[] = {
668 { .parent = &tclkin_ck, .rates = div_1_0_rates },
669 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
670 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
671 { .parent = NULL },
672};
673
674static struct clk timer2_fck = {
675 .name = "timer2_fck",
676 .clkdm_name = "l4ls_clkdm",
677 .parent = &sys_clkin_ck,
678 .init = &omap2_init_clksel_parent,
679 .clksel = timer2_to_7_clk_sel,
680 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
681 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
682 .ops = &clkops_null,
683 .recalc = &omap2_clksel_recalc,
684};
685
686static struct clk timer3_fck = {
687 .name = "timer3_fck",
688 .clkdm_name = "l4ls_clkdm",
689 .parent = &sys_clkin_ck,
690 .init = &am33xx_init_timer_parent,
691 .clksel = timer2_to_7_clk_sel,
692 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
693 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
694 .ops = &clkops_null,
695 .recalc = &omap2_clksel_recalc,
696};
697
698static struct clk timer4_fck = {
699 .name = "timer4_fck",
700 .clkdm_name = "l4ls_clkdm",
701 .parent = &sys_clkin_ck,
702 .init = &omap2_init_clksel_parent,
703 .clksel = timer2_to_7_clk_sel,
704 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
705 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
706 .ops = &clkops_null,
707 .recalc = &omap2_clksel_recalc,
708};
709
710static struct clk timer5_fck = {
711 .name = "timer5_fck",
712 .clkdm_name = "l4ls_clkdm",
713 .parent = &sys_clkin_ck,
714 .init = &omap2_init_clksel_parent,
715 .clksel = timer2_to_7_clk_sel,
716 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
717 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
718 .ops = &clkops_null,
719 .recalc = &omap2_clksel_recalc,
720};
721
722static struct clk timer6_fck = {
723 .name = "timer6_fck",
724 .clkdm_name = "l4ls_clkdm",
725 .parent = &sys_clkin_ck,
726 .init = &am33xx_init_timer_parent,
727 .clksel = timer2_to_7_clk_sel,
728 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
729 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
730 .ops = &clkops_null,
731 .recalc = &omap2_clksel_recalc,
732};
733
734static struct clk timer7_fck = {
735 .name = "timer7_fck",
736 .clkdm_name = "l4ls_clkdm",
737 .parent = &sys_clkin_ck,
738 .init = &omap2_init_clksel_parent,
739 .clksel = timer2_to_7_clk_sel,
740 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
741 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
742 .ops = &clkops_null,
743 .recalc = &omap2_clksel_recalc,
744};
745
746static struct clk cpsw_125mhz_gclk = {
747 .name = "cpsw_125mhz_gclk",
748 .clkdm_name = "cpsw_125mhz_clkdm",
749 .parent = &dpll_core_m5_ck,
750 .ops = &clkops_null,
751 .fixed_div = 2,
752 .recalc = &omap_fixed_divisor_recalc,
753};
754
755static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
756 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
757 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
758 { .parent = NULL },
759};
760
761static struct clk cpsw_cpts_rft_clk = {
762 .name = "cpsw_cpts_rft_clk",
763 .clkdm_name = "cpsw_125mhz_clkdm",
764 .parent = &dpll_core_m5_ck,
765 .clksel = cpsw_cpts_rft_clkmux_sel,
766 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
767 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
768 .ops = &clkops_null,
769 .recalc = &followparent_recalc,
770};
771
772/* gpio */
773static const struct clksel gpio0_dbclk_mux_sel[] = {
774 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
775 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
776 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
777 { .parent = NULL },
778};
779
780static struct clk gpio0_dbclk_mux_ck = {
781 .name = "gpio0_dbclk_mux_ck",
782 .clkdm_name = "l4_wkup_clkdm",
783 .parent = &clk_rc32k_ck,
784 .init = &omap2_init_clksel_parent,
785 .clksel = gpio0_dbclk_mux_sel,
786 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
787 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
788 .ops = &clkops_null,
789 .recalc = &omap2_clksel_recalc,
790};
791
792static struct clk gpio0_dbclk = {
793 .name = "gpio0_dbclk",
794 .clkdm_name = "l4_wkup_clkdm",
795 .parent = &gpio0_dbclk_mux_ck,
796 .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
797 .enable_bit = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
798 .ops = &clkops_omap2_dflt,
799 .recalc = &followparent_recalc,
800};
801
802static struct clk gpio1_dbclk = {
803 .name = "gpio1_dbclk",
804 .clkdm_name = "l4ls_clkdm",
805 .parent = &clkdiv32k_ick,
806 .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL,
807 .enable_bit = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
808 .ops = &clkops_omap2_dflt,
809 .recalc = &followparent_recalc,
810};
811
812static struct clk gpio2_dbclk = {
813 .name = "gpio2_dbclk",
814 .clkdm_name = "l4ls_clkdm",
815 .parent = &clkdiv32k_ick,
816 .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL,
817 .enable_bit = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
818 .ops = &clkops_omap2_dflt,
819 .recalc = &followparent_recalc,
820};
821
822static struct clk gpio3_dbclk = {
823 .name = "gpio3_dbclk",
824 .clkdm_name = "l4ls_clkdm",
825 .parent = &clkdiv32k_ick,
826 .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL,
827 .enable_bit = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
828 .ops = &clkops_omap2_dflt,
829 .recalc = &followparent_recalc,
830};
831
832static const struct clksel pruss_ocp_clk_mux_sel[] = {
833 { .parent = &l3_gclk, .rates = div_1_0_rates },
834 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
835 { .parent = NULL },
836};
837
838static struct clk pruss_ocp_gclk = {
839 .name = "pruss_ocp_gclk",
840 .clkdm_name = "pruss_ocp_clkdm",
841 .parent = &l3_gclk,
842 .init = &omap2_init_clksel_parent,
843 .clksel = pruss_ocp_clk_mux_sel,
844 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
845 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
846 .ops = &clkops_null,
847 .recalc = &followparent_recalc,
848};
849
850static const struct clksel lcd_clk_mux_sel[] = {
851 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
852 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
853 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
854 { .parent = NULL },
855};
856
857static struct clk lcd_gclk = {
858 .name = "lcd_gclk",
859 .clkdm_name = "lcdc_clkdm",
860 .parent = &dpll_disp_m2_ck,
861 .init = &omap2_init_clksel_parent,
862 .clksel = lcd_clk_mux_sel,
863 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
864 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
865 .ops = &clkops_null,
866 .recalc = &followparent_recalc,
867};
868
869static struct clk mmc_clk = {
870 .name = "mmc_clk",
871 .clkdm_name = "l4ls_clkdm",
872 .parent = &dpll_per_m2_ck,
873 .ops = &clkops_null,
874 .fixed_div = 2,
875 .recalc = &omap_fixed_divisor_recalc,
876};
877
878static struct clk mmc2_fck = {
879 .name = "mmc2_fck",
880 .clkdm_name = "l3s_clkdm",
881 .parent = &mmc_clk,
882 .ops = &clkops_null,
883 .recalc = &followparent_recalc,
884};
885
886static const struct clksel gfx_clksel_sel[] = {
887 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
888 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
889 { .parent = NULL },
890};
891
892static struct clk gfx_fclk_clksel_ck = {
893 .name = "gfx_fclk_clksel_ck",
894 .parent = &dpll_core_m4_ck,
895 .clksel = gfx_clksel_sel,
896 .ops = &clkops_null,
897 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
898 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
899 .recalc = &omap2_clksel_recalc,
900};
901
902static const struct clksel_rate div_1_0_2_1_rates[] = {
903 { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
904 { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
905 { .div = 0 },
906};
907
908static const struct clksel gfx_div_sel[] = {
909 { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
910 { .parent = NULL },
911};
912
913static struct clk gfx_fck_div_ck = {
914 .name = "gfx_fck_div_ck",
915 .clkdm_name = "gfx_l3_clkdm",
916 .parent = &gfx_fclk_clksel_ck,
917 .init = &omap2_init_clksel_parent,
918 .clksel = gfx_div_sel,
919 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
920 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
921 .recalc = &omap2_clksel_recalc,
922 .round_rate = &omap2_clksel_round_rate,
923 .set_rate = &omap2_clksel_set_rate,
924 .ops = &clkops_null,
925};
926
927static const struct clksel sysclkout_pre_sel[] = {
928 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
929 { .parent = &l3_gclk, .rates = div_1_1_rates },
930 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
931 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
932 { .parent = &lcd_gclk, .rates = div_1_4_rates },
933 { .parent = NULL },
934};
935
936static struct clk sysclkout_pre_ck = {
937 .name = "sysclkout_pre_ck",
938 .parent = &clk_32768_ck,
939 .init = &omap2_init_clksel_parent,
940 .clksel = sysclkout_pre_sel,
941 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
942 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
943 .ops = &clkops_null,
944 .recalc = &omap2_clksel_recalc,
945};
946
947/* Divide by 8 clock rates with default clock is 1/1*/
948static const struct clksel_rate div8_rates[] = {
949 { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
950 { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
951 { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
952 { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
953 { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
954 { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
955 { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
956 { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
957 { .div = 0 },
958};
959
960static const struct clksel clkout2_div[] = {
961 { .parent = &sysclkout_pre_ck, .rates = div8_rates },
962 { .parent = NULL },
963};
964
965static struct clk clkout2_ck = {
966 .name = "clkout2_ck",
967 .parent = &sysclkout_pre_ck,
968 .ops = &clkops_omap2_dflt,
969 .clksel = clkout2_div,
970 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
971 .clksel_mask = AM33XX_CLKOUT2DIV_MASK,
972 .enable_reg = AM33XX_CM_CLKOUT_CTRL,
973 .enable_bit = AM33XX_CLKOUT2EN_SHIFT,
974 .recalc = &omap2_clksel_recalc,
975 .round_rate = &omap2_clksel_round_rate,
976 .set_rate = &omap2_clksel_set_rate,
977};
978
979static const struct clksel wdt_clkmux_sel[] = {
980 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
981 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
982 { .parent = NULL },
983};
984
985static struct clk wdt1_fck = {
986 .name = "wdt1_fck",
987 .clkdm_name = "l4_wkup_clkdm",
988 .parent = &clk_rc32k_ck,
989 .init = &omap2_init_clksel_parent,
990 .clksel = wdt_clkmux_sel,
991 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
992 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
993 .ops = &clkops_null,
994 .recalc = &omap2_clksel_recalc,
995};
996
997/*
998 * clkdev
999 */
1000static struct omap_clk am33xx_clks[] = {
1001 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
1002 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
1003 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
1004 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
1005 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
1006 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
1007 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
1008 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
1009 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
1010 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
1011 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
1012 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
1013 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
1014 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
1015 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
1016 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
1017 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
1018 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
1019 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
1020 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
1021 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
1022 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
1023 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
1024 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
1025 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
1026 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
1027 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
1028 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
1029 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
1030 CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX),
1031 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
1032 CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX),
1033 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
1034 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
1035 CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX),
1036 CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX),
1037 CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX),
1038 CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
1039 CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX),
1040 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
1041 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
1042 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
1043 CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
1044 CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
1045 CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
1046 CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
1047 CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
1048 CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
1049 CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
1050 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
1051 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
1052 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
1053 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
1054 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
1055 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
1056 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
1057 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
1058 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
1059 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
1060 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
1061 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
1062 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
1063 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
1064 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
1065 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
1066 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
1067 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
1068 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
1069 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
1070 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
1071 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
1072 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
1073 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
1074 CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
1075};
1076
1077int __init am33xx_clk_init(void)
1078{
1079 struct omap_clk *c;
1080 u32 cpu_clkflg;
1081
1082 if (soc_is_am33xx()) {
1083 cpu_mask = RATE_IN_AM33XX;
1084 cpu_clkflg = CK_AM33XX;
1085 }
1086
1087 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1088 clk_preinit(c->lk.clk);
1089
1090 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
1091 if (c->cpu & cpu_clkflg) {
1092 clkdev_add(&c->lk);
1093 clk_register(c->lk.clk);
1094 omap2_init_clk_clkdm(c->lk.clk);
1095 }
1096 }
1097
1098 recalculate_root_clocks();
1099
1100 /*
1101 * Only enable those clocks we will need, let the drivers
1102 * enable other clocks as necessary
1103 */
1104 clk_enable_init_clocks();
1105
1106 return 0;
1107}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 02:04:18 -0400