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authorPaul Walmsley <paul@pwsan.com>2012-09-10 16:08:12 -0400
committerPaul Walmsley <paul@pwsan.com>2012-11-12 21:18:50 -0500
commit368edee33ea929434cd950b8eeb77fa296df882e (patch)
tree1617a1e0b6f3409863803e5770f8de1a79305471 /arch
parent25f4214e388dda818765b670fb608f2e6467d877 (diff)
ARM: OMAP3xxx: clk: drop obsolete clock data
Drop the now-obsolete OMAP3xxx original OMAP clock data. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c3591
1 files changed, 0 insertions, 3591 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
deleted file mode 100644
index eaa7f2f233c..00000000000
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ /dev/null
@@ -1,3591 +0,0 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19#include <linux/kernel.h>
20#include <linux/clk.h>
21#include <linux/list.h>
22#include <linux/io.h>
23
24#include "soc.h"
25#include "iomap.h"
26#include "clock.h"
27#include "clock3xxx.h"
28#include "clock34xx.h"
29#include "clock36xx.h"
30#include "clock3517.h"
31#include "cm3xxx.h"
32#include "cm-regbits-34xx.h"
33#include "prm2xxx_3xxx.h"
34#include "prm-regbits-34xx.h"
35#include "control.h"
36
37/*
38 * clocks
39 */
40
41#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
42
43/* Maximum DPLL multiplier, divider values for OMAP3 */
44#define OMAP3_MAX_DPLL_MULT 2047
45#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
46#define OMAP3_MAX_DPLL_DIV 128
47
48/*
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
51 * DPLL3 supplies CORE domain clocks.
52 * DPLL4 supplies peripheral clocks.
53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 */
55
56/* Forward declarations for DPLL bypass clocks */
57static struct clk dpll1_fck;
58static struct clk dpll2_fck;
59
60/* PRM CLOCKS */
61
62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
66 .rate = 32768,
67};
68
69static struct clk secure_32k_fck = {
70 .name = "secure_32k_fck",
71 .ops = &clkops_null,
72 .rate = 32768,
73};
74
75/* Virtual source clocks for osc_sys_ck */
76static struct clk virt_12m_ck = {
77 .name = "virt_12m_ck",
78 .ops = &clkops_null,
79 .rate = 12000000,
80};
81
82static struct clk virt_13m_ck = {
83 .name = "virt_13m_ck",
84 .ops = &clkops_null,
85 .rate = 13000000,
86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92};
93
94static struct clk virt_38_4m_ck = {
95 .name = "virt_38_4m_ck",
96 .ops = &clkops_null,
97 .rate = 38400000,
98};
99
100static const struct clksel_rate osc_sys_12m_rates[] = {
101 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
102 { .div = 0 }
103};
104
105static const struct clksel_rate osc_sys_13m_rates[] = {
106 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
107 { .div = 0 }
108};
109
110static const struct clksel_rate osc_sys_16_8m_rates[] = {
111 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
112 { .div = 0 }
113};
114
115static const struct clksel_rate osc_sys_19_2m_rates[] = {
116 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
117 { .div = 0 }
118};
119
120static const struct clksel_rate osc_sys_26m_rates[] = {
121 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
122 { .div = 0 }
123};
124
125static const struct clksel_rate osc_sys_38_4m_rates[] = {
126 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
127 { .div = 0 }
128};
129
130static const struct clksel osc_sys_clksel[] = {
131 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
132 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
133 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
134 { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates },
135 { .parent = &virt_26000000_ck, .rates = osc_sys_26m_rates },
136 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
137 { .parent = NULL },
138};
139
140/* Oscillator clock */
141/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
142static struct clk osc_sys_ck = {
143 .name = "osc_sys_ck",
144 .ops = &clkops_null,
145 .init = &omap2_init_clksel_parent,
146 .clksel_reg = OMAP3430_PRM_CLKSEL,
147 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
148 .clksel = osc_sys_clksel,
149 /* REVISIT: deal with autoextclkmode? */
150 .recalc = &omap2_clksel_recalc,
151};
152
153static const struct clksel_rate div2_rates[] = {
154 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
155 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
156 { .div = 0 }
157};
158
159static const struct clksel sys_clksel[] = {
160 { .parent = &osc_sys_ck, .rates = div2_rates },
161 { .parent = NULL }
162};
163
164/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
165/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
166static struct clk sys_ck = {
167 .name = "sys_ck",
168 .ops = &clkops_null,
169 .parent = &osc_sys_ck,
170 .init = &omap2_init_clksel_parent,
171 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
172 .clksel_mask = OMAP_SYSCLKDIV_MASK,
173 .clksel = sys_clksel,
174 .recalc = &omap2_clksel_recalc,
175};
176
177static struct clk sys_altclk = {
178 .name = "sys_altclk",
179 .ops = &clkops_null,
180};
181
182/* Optional external clock input for some McBSPs */
183static struct clk mcbsp_clks = {
184 .name = "mcbsp_clks",
185 .ops = &clkops_null,
186};
187
188/* PRM EXTERNAL CLOCK OUTPUT */
189
190static struct clk sys_clkout1 = {
191 .name = "sys_clkout1",
192 .ops = &clkops_omap2_dflt,
193 .parent = &osc_sys_ck,
194 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
195 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
196 .recalc = &followparent_recalc,
197};
198
199/* DPLLS */
200
201/* CM CLOCKS */
202
203static const struct clksel_rate div16_dpll_rates[] = {
204 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
205 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
206 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
207 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
208 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
209 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
210 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
211 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
212 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
213 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
214 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
215 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
216 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
217 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
218 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
219 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
220 { .div = 0 }
221};
222
223static const struct clksel_rate dpll4_rates[] = {
224 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
225 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
226 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
227 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
228 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
229 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
230 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
231 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
232 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
233 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
234 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
235 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
236 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
237 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
238 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
239 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
240 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
241 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
242 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
243 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
244 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
245 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
246 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
247 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
248 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
249 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
250 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
251 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
252 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
253 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
254 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
255 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
256 { .div = 0 }
257};
258
259/* DPLL1 */
260/* MPU clock source */
261/* Type: DPLL */
262static struct dpll_data dpll1_dd = {
263 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
264 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
265 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
266 .clk_bypass = &dpll1_fck,
267 .clk_ref = &sys_ck,
268 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
269 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
270 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
271 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
272 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
273 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
274 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
275 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
276 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
277 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
278 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
279 .max_multiplier = OMAP3_MAX_DPLL_MULT,
280 .min_divider = 1,
281 .max_divider = OMAP3_MAX_DPLL_DIV,
282};
283
284static struct clk dpll1_ck = {
285 .name = "dpll1_ck",
286 .ops = &clkops_omap3_noncore_dpll_ops,
287 .parent = &sys_ck,
288 .dpll_data = &dpll1_dd,
289 .round_rate = &omap2_dpll_round_rate,
290 .set_rate = &omap3_noncore_dpll_set_rate,
291 .clkdm_name = "dpll1_clkdm",
292 .recalc = &omap3_dpll_recalc,
293};
294
295/*
296 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
297 * DPLL isn't bypassed.
298 */
299static struct clk dpll1_x2_ck = {
300 .name = "dpll1_x2_ck",
301 .ops = &clkops_null,
302 .parent = &dpll1_ck,
303 .recalc = &omap3_clkoutx2_recalc,
304};
305
306/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
307static const struct clksel div16_dpll1_x2m2_clksel[] = {
308 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
309 { .parent = NULL }
310};
311
312/*
313 * Does not exist in the TRM - needed to separate the M2 divider from
314 * bypass selection in mpu_ck
315 */
316static struct clk dpll1_x2m2_ck = {
317 .name = "dpll1_x2m2_ck",
318 .ops = &clkops_null,
319 .parent = &dpll1_x2_ck,
320 .init = &omap2_init_clksel_parent,
321 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
322 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
323 .clksel = div16_dpll1_x2m2_clksel,
324 .recalc = &omap2_clksel_recalc,
325};
326
327/* DPLL2 */
328/* IVA2 clock source */
329/* Type: DPLL */
330
331static struct dpll_data dpll2_dd = {
332 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
333 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
334 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
335 .clk_bypass = &dpll2_fck,
336 .clk_ref = &sys_ck,
337 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
338 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
339 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
340 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
341 (1 << DPLL_LOW_POWER_BYPASS),
342 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
343 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
344 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
345 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
346 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
347 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
348 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
349 .max_multiplier = OMAP3_MAX_DPLL_MULT,
350 .min_divider = 1,
351 .max_divider = OMAP3_MAX_DPLL_DIV,
352};
353
354static struct clk dpll2_ck = {
355 .name = "dpll2_ck",
356 .ops = &clkops_omap3_noncore_dpll_ops,
357 .parent = &sys_ck,
358 .dpll_data = &dpll2_dd,
359 .round_rate = &omap2_dpll_round_rate,
360 .set_rate = &omap3_noncore_dpll_set_rate,
361 .clkdm_name = "dpll2_clkdm",
362 .recalc = &omap3_dpll_recalc,
363};
364
365static const struct clksel div16_dpll2_m2x2_clksel[] = {
366 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
367 { .parent = NULL }
368};
369
370/*
371 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
372 * or CLKOUTX2. CLKOUT seems most plausible.
373 */
374static struct clk dpll2_m2_ck = {
375 .name = "dpll2_m2_ck",
376 .ops = &clkops_null,
377 .parent = &dpll2_ck,
378 .init = &omap2_init_clksel_parent,
379 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
380 OMAP3430_CM_CLKSEL2_PLL),
381 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
382 .clksel = div16_dpll2_m2x2_clksel,
383 .recalc = &omap2_clksel_recalc,
384};
385
386/*
387 * DPLL3
388 * Source clock for all interfaces and for some device fclks
389 * REVISIT: Also supports fast relock bypass - not included below
390 */
391static struct dpll_data dpll3_dd = {
392 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
393 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
394 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
395 .clk_bypass = &sys_ck,
396 .clk_ref = &sys_ck,
397 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
398 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
399 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
400 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
401 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
402 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
403 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
404 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
405 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
406 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
407 .max_multiplier = OMAP3_MAX_DPLL_MULT,
408 .min_divider = 1,
409 .max_divider = OMAP3_MAX_DPLL_DIV,
410};
411
412static struct clk dpll3_ck = {
413 .name = "dpll3_ck",
414 .ops = &clkops_omap3_core_dpll_ops,
415 .parent = &sys_ck,
416 .dpll_data = &dpll3_dd,
417 .round_rate = &omap2_dpll_round_rate,
418 .clkdm_name = "dpll3_clkdm",
419 .recalc = &omap3_dpll_recalc,
420};
421
422/*
423 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
424 * DPLL isn't bypassed
425 */
426static struct clk dpll3_x2_ck = {
427 .name = "dpll3_x2_ck",
428 .ops = &clkops_null,
429 .parent = &dpll3_ck,
430 .recalc = &omap3_clkoutx2_recalc,
431};
432
433static const struct clksel_rate div31_dpll3_rates[] = {
434 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
435 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
436 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
437 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
438 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
439 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
440 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
441 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
442 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
443 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
444 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
445 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
446 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
447 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
448 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
449 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
450 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
451 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
452 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
453 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
454 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
455 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 0 },
466};
467
468static const struct clksel div31_dpll3m2_clksel[] = {
469 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
470 { .parent = NULL }
471};
472
473/* DPLL3 output M2 - primary control point for CORE speed */
474static struct clk dpll3_m2_ck = {
475 .name = "dpll3_m2_ck",
476 .ops = &clkops_null,
477 .parent = &dpll3_ck,
478 .init = &omap2_init_clksel_parent,
479 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
480 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
481 .clksel = div31_dpll3m2_clksel,
482 .round_rate = &omap2_clksel_round_rate,
483 .set_rate = &omap3_core_dpll_m2_set_rate,
484 .recalc = &omap2_clksel_recalc,
485};
486
487static struct clk core_ck = {
488 .name = "core_ck",
489 .ops = &clkops_null,
490 .parent = &dpll3_m2_ck,
491 .recalc = &followparent_recalc,
492};
493
494static struct clk dpll3_m2x2_ck = {
495 .name = "dpll3_m2x2_ck",
496 .ops = &clkops_null,
497 .parent = &dpll3_m2_ck,
498 .recalc = &omap3_clkoutx2_recalc,
499};
500
501/* The PWRDN bit is apparently only available on 3430ES2 and above */
502static const struct clksel div16_dpll3_clksel[] = {
503 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
504 { .parent = NULL }
505};
506
507/* This virtual clock is the source for dpll3_m3x2_ck */
508static struct clk dpll3_m3_ck = {
509 .name = "dpll3_m3_ck",
510 .ops = &clkops_null,
511 .parent = &dpll3_ck,
512 .init = &omap2_init_clksel_parent,
513 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
514 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
515 .clksel = div16_dpll3_clksel,
516 .recalc = &omap2_clksel_recalc,
517};
518
519/* The PWRDN bit is apparently only available on 3430ES2 and above */
520static struct clk dpll3_m3x2_ck = {
521 .name = "dpll3_m3x2_ck",
522 .ops = &clkops_omap2_dflt_wait,
523 .parent = &dpll3_m3_ck,
524 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
525 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
526 .flags = INVERT_ENABLE,
527 .clkdm_name = "dpll3_clkdm",
528 .recalc = &omap3_clkoutx2_recalc,
529};
530
531static struct clk emu_core_alwon_ck = {
532 .name = "emu_core_alwon_ck",
533 .ops = &clkops_null,
534 .parent = &dpll3_m3x2_ck,
535 .clkdm_name = "dpll3_clkdm",
536 .recalc = &followparent_recalc,
537};
538
539/* DPLL4 */
540/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
541/* Type: DPLL */
542static struct dpll_data dpll4_dd;
543
544static struct dpll_data dpll4_dd_34xx __initdata = {
545 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
546 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
547 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
548 .clk_bypass = &sys_ck,
549 .clk_ref = &sys_ck,
550 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
551 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
552 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
553 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
554 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
555 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
556 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
557 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
558 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
559 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
560 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
561 .max_multiplier = OMAP3_MAX_DPLL_MULT,
562 .min_divider = 1,
563 .max_divider = OMAP3_MAX_DPLL_DIV,
564};
565
566static struct dpll_data dpll4_dd_3630 __initdata = {
567 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
568 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
569 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
570 .clk_bypass = &sys_ck,
571 .clk_ref = &sys_ck,
572 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
573 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
574 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
575 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
576 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
577 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
578 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
579 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
580 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
581 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
582 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
583 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
584 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
585 .min_divider = 1,
586 .max_divider = OMAP3_MAX_DPLL_DIV,
587 .flags = DPLL_J_TYPE
588};
589
590static struct clk dpll4_ck = {
591 .name = "dpll4_ck",
592 .ops = &clkops_omap3_noncore_dpll_ops,
593 .parent = &sys_ck,
594 .dpll_data = &dpll4_dd,
595 .round_rate = &omap2_dpll_round_rate,
596 .set_rate = &omap3_dpll4_set_rate,
597 .clkdm_name = "dpll4_clkdm",
598 .recalc = &omap3_dpll_recalc,
599};
600
601/*
602 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
603 * DPLL isn't bypassed --
604 * XXX does this serve any downstream clocks?
605 */
606static struct clk dpll4_x2_ck = {
607 .name = "dpll4_x2_ck",
608 .ops = &clkops_null,
609 .parent = &dpll4_ck,
610 .recalc = &omap3_clkoutx2_recalc,
611};
612
613static const struct clksel dpll4_clksel[] = {
614 { .parent = &dpll4_ck, .rates = dpll4_rates },
615 { .parent = NULL }
616};
617
618/* This virtual clock is the source for dpll4_m2x2_ck */
619static struct clk dpll4_m2_ck = {
620 .name = "dpll4_m2_ck",
621 .ops = &clkops_null,
622 .parent = &dpll4_ck,
623 .init = &omap2_init_clksel_parent,
624 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
625 .clksel_mask = OMAP3630_DIV_96M_MASK,
626 .clksel = dpll4_clksel,
627 .recalc = &omap2_clksel_recalc,
628};
629
630/* The PWRDN bit is apparently only available on 3430ES2 and above */
631static struct clk dpll4_m2x2_ck = {
632 .name = "dpll4_m2x2_ck",
633 .ops = &clkops_omap2_dflt_wait,
634 .parent = &dpll4_m2_ck,
635 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
636 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
637 .flags = INVERT_ENABLE,
638 .clkdm_name = "dpll4_clkdm",
639 .recalc = &omap3_clkoutx2_recalc,
640};
641
642/*
643 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
644 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
645 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
646 * CM_96K_(F)CLK.
647 */
648
649/* Adding 192MHz Clock node needed by SGX */
650static struct clk omap_192m_alwon_fck = {
651 .name = "omap_192m_alwon_fck",
652 .ops = &clkops_null,
653 .parent = &dpll4_m2x2_ck,
654 .recalc = &followparent_recalc,
655};
656
657static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
658 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
659 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
660 { .div = 0 }
661};
662
663static const struct clksel omap_96m_alwon_fck_clksel[] = {
664 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
665 { .parent = NULL }
666};
667
668static const struct clksel_rate omap_96m_dpll_rates[] = {
669 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
670 { .div = 0 }
671};
672
673static const struct clksel_rate omap_96m_sys_rates[] = {
674 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
675 { .div = 0 }
676};
677
678static struct clk omap_96m_alwon_fck = {
679 .name = "omap_96m_alwon_fck",
680 .ops = &clkops_null,
681 .parent = &dpll4_m2x2_ck,
682 .recalc = &followparent_recalc,
683};
684
685static struct clk omap_96m_alwon_fck_3630 = {
686 .name = "omap_96m_alwon_fck",
687 .parent = &omap_192m_alwon_fck,
688 .init = &omap2_init_clksel_parent,
689 .ops = &clkops_null,
690 .recalc = &omap2_clksel_recalc,
691 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
692 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
693 .clksel = omap_96m_alwon_fck_clksel
694};
695
696static struct clk cm_96m_fck = {
697 .name = "cm_96m_fck",
698 .ops = &clkops_null,
699 .parent = &omap_96m_alwon_fck,
700 .recalc = &followparent_recalc,
701};
702
703static const struct clksel omap_96m_fck_clksel[] = {
704 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
705 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
706 { .parent = NULL }
707};
708
709static struct clk omap_96m_fck = {
710 .name = "omap_96m_fck",
711 .ops = &clkops_null,
712 .parent = &sys_ck,
713 .init = &omap2_init_clksel_parent,
714 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
715 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
716 .clksel = omap_96m_fck_clksel,
717 .recalc = &omap2_clksel_recalc,
718};
719
720/* This virtual clock is the source for dpll4_m3x2_ck */
721static struct clk dpll4_m3_ck = {
722 .name = "dpll4_m3_ck",
723 .ops = &clkops_null,
724 .parent = &dpll4_ck,
725 .init = &omap2_init_clksel_parent,
726 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
727 .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
728 .clksel = dpll4_clksel,
729 .recalc = &omap2_clksel_recalc,
730};
731
732/* The PWRDN bit is apparently only available on 3430ES2 and above */
733static struct clk dpll4_m3x2_ck = {
734 .name = "dpll4_m3x2_ck",
735 .ops = &clkops_omap2_dflt_wait,
736 .parent = &dpll4_m3_ck,
737 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
738 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
739 .flags = INVERT_ENABLE,
740 .clkdm_name = "dpll4_clkdm",
741 .recalc = &omap3_clkoutx2_recalc,
742};
743
744static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
745 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
746 { .div = 0 }
747};
748
749static const struct clksel_rate omap_54m_alt_rates[] = {
750 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
751 { .div = 0 }
752};
753
754static const struct clksel omap_54m_clksel[] = {
755 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
756 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
757 { .parent = NULL }
758};
759
760static struct clk omap_54m_fck = {
761 .name = "omap_54m_fck",
762 .ops = &clkops_null,
763 .init = &omap2_init_clksel_parent,
764 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
765 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
766 .clksel = omap_54m_clksel,
767 .recalc = &omap2_clksel_recalc,
768};
769
770static const struct clksel_rate omap_48m_cm96m_rates[] = {
771 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
772 { .div = 0 }
773};
774
775static const struct clksel_rate omap_48m_alt_rates[] = {
776 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
777 { .div = 0 }
778};
779
780static const struct clksel omap_48m_clksel[] = {
781 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
782 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
783 { .parent = NULL }
784};
785
786static struct clk omap_48m_fck = {
787 .name = "omap_48m_fck",
788 .ops = &clkops_null,
789 .init = &omap2_init_clksel_parent,
790 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
791 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
792 .clksel = omap_48m_clksel,
793 .recalc = &omap2_clksel_recalc,
794};
795
796static struct clk omap_12m_fck = {
797 .name = "omap_12m_fck",
798 .ops = &clkops_null,
799 .parent = &omap_48m_fck,
800 .fixed_div = 4,
801 .recalc = &omap_fixed_divisor_recalc,
802};
803
804/* This virtual clock is the source for dpll4_m4x2_ck */
805static struct clk dpll4_m4_ck = {
806 .name = "dpll4_m4_ck",
807 .ops = &clkops_null,
808 .parent = &dpll4_ck,
809 .init = &omap2_init_clksel_parent,
810 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
811 .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
812 .clksel = dpll4_clksel,
813 .recalc = &omap2_clksel_recalc,
814 .set_rate = &omap2_clksel_set_rate,
815 .round_rate = &omap2_clksel_round_rate,
816};
817
818/* The PWRDN bit is apparently only available on 3430ES2 and above */
819static struct clk dpll4_m4x2_ck = {
820 .name = "dpll4_m4x2_ck",
821 .ops = &clkops_omap2_dflt_wait,
822 .parent = &dpll4_m4_ck,
823 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
824 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
825 .flags = INVERT_ENABLE,
826 .clkdm_name = "dpll4_clkdm",
827 .recalc = &omap3_clkoutx2_recalc,
828};
829
830/* This virtual clock is the source for dpll4_m5x2_ck */
831static struct clk dpll4_m5_ck = {
832 .name = "dpll4_m5_ck",
833 .ops = &clkops_null,
834 .parent = &dpll4_ck,
835 .init = &omap2_init_clksel_parent,
836 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
837 .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
838 .clksel = dpll4_clksel,
839 .set_rate = &omap2_clksel_set_rate,
840 .round_rate = &omap2_clksel_round_rate,
841 .recalc = &omap2_clksel_recalc,
842};
843
844/* The PWRDN bit is apparently only available on 3430ES2 and above */
845static struct clk dpll4_m5x2_ck = {
846 .name = "dpll4_m5x2_ck",
847 .ops = &clkops_omap2_dflt_wait,
848 .parent = &dpll4_m5_ck,
849 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
850 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
851 .flags = INVERT_ENABLE,
852 .clkdm_name = "dpll4_clkdm",
853 .recalc = &omap3_clkoutx2_recalc,
854};
855
856/* This virtual clock is the source for dpll4_m6x2_ck */
857static struct clk dpll4_m6_ck = {
858 .name = "dpll4_m6_ck",
859 .ops = &clkops_null,
860 .parent = &dpll4_ck,
861 .init = &omap2_init_clksel_parent,
862 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
863 .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
864 .clksel = dpll4_clksel,
865 .recalc = &omap2_clksel_recalc,
866};
867
868/* The PWRDN bit is apparently only available on 3430ES2 and above */
869static struct clk dpll4_m6x2_ck = {
870 .name = "dpll4_m6x2_ck",
871 .ops = &clkops_omap2_dflt_wait,
872 .parent = &dpll4_m6_ck,
873 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
874 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
875 .flags = INVERT_ENABLE,
876 .clkdm_name = "dpll4_clkdm",
877 .recalc = &omap3_clkoutx2_recalc,
878};
879
880static struct clk emu_per_alwon_ck = {
881 .name = "emu_per_alwon_ck",
882 .ops = &clkops_null,
883 .parent = &dpll4_m6x2_ck,
884 .clkdm_name = "dpll4_clkdm",
885 .recalc = &followparent_recalc,
886};
887
888/* DPLL5 */
889/* Supplies 120MHz clock, USIM source clock */
890/* Type: DPLL */
891/* 3430ES2 only */
892static struct dpll_data dpll5_dd = {
893 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
894 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
895 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
896 .clk_bypass = &sys_ck,
897 .clk_ref = &sys_ck,
898 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
899 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
900 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
901 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
902 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
903 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
904 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
905 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
906 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
907 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
908 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
909 .max_multiplier = OMAP3_MAX_DPLL_MULT,
910 .min_divider = 1,
911 .max_divider = OMAP3_MAX_DPLL_DIV,
912};
913
914static struct clk dpll5_ck = {
915 .name = "dpll5_ck",
916 .ops = &clkops_omap3_noncore_dpll_ops,
917 .parent = &sys_ck,
918 .dpll_data = &dpll5_dd,
919 .round_rate = &omap2_dpll_round_rate,
920 .set_rate = &omap3_noncore_dpll_set_rate,
921 .clkdm_name = "dpll5_clkdm",
922 .recalc = &omap3_dpll_recalc,
923};
924
925static const struct clksel div16_dpll5_clksel[] = {
926 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
927 { .parent = NULL }
928};
929
930static struct clk dpll5_m2_ck = {
931 .name = "dpll5_m2_ck",
932 .ops = &clkops_null,
933 .parent = &dpll5_ck,
934 .init = &omap2_init_clksel_parent,
935 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
936 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
937 .clksel = div16_dpll5_clksel,
938 .recalc = &omap2_clksel_recalc,
939};
940
941/* CM EXTERNAL CLOCK OUTPUTS */
942
943static const struct clksel_rate clkout2_src_core_rates[] = {
944 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
945 { .div = 0 }
946};
947
948static const struct clksel_rate clkout2_src_sys_rates[] = {
949 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
950 { .div = 0 }
951};
952
953static const struct clksel_rate clkout2_src_96m_rates[] = {
954 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
955 { .div = 0 }
956};
957
958static const struct clksel_rate clkout2_src_54m_rates[] = {
959 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
960 { .div = 0 }
961};
962
963static const struct clksel clkout2_src_clksel[] = {
964 { .parent = &core_ck, .rates = clkout2_src_core_rates },
965 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
966 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
967 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
968 { .parent = NULL }
969};
970
971static struct clk clkout2_src_ck = {
972 .name = "clkout2_src_ck",
973 .ops = &clkops_omap2_dflt,
974 .init = &omap2_init_clksel_parent,
975 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
976 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
977 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
978 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
979 .clksel = clkout2_src_clksel,
980 .clkdm_name = "core_clkdm",
981 .recalc = &omap2_clksel_recalc,
982};
983
984static const struct clksel_rate sys_clkout2_rates[] = {
985 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
986 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
987 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
988 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
989 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
990 { .div = 0 },
991};
992
993static const struct clksel sys_clkout2_clksel[] = {
994 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
995 { .parent = NULL },
996};
997
998static struct clk sys_clkout2 = {
999 .name = "sys_clkout2",
1000 .ops = &clkops_null,
1001 .init = &omap2_init_clksel_parent,
1002 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1003 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1004 .clksel = sys_clkout2_clksel,
1005 .recalc = &omap2_clksel_recalc,
1006 .round_rate = &omap2_clksel_round_rate,
1007 .set_rate = &omap2_clksel_set_rate
1008};
1009
1010/* CM OUTPUT CLOCKS */
1011
1012static struct clk corex2_fck = {
1013 .name = "corex2_fck",
1014 .ops = &clkops_null,
1015 .parent = &dpll3_m2x2_ck,
1016 .recalc = &followparent_recalc,
1017};
1018
1019/* DPLL power domain clock controls */
1020
1021static const struct clksel_rate div4_rates[] = {
1022 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1023 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1024 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1025 { .div = 0 }
1026};
1027
1028static const struct clksel div4_core_clksel[] = {
1029 { .parent = &core_ck, .rates = div4_rates },
1030 { .parent = NULL }
1031};
1032
1033/*
1034 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1035 * may be inconsistent here?
1036 */
1037static struct clk dpll1_fck = {
1038 .name = "dpll1_fck",
1039 .ops = &clkops_null,
1040 .parent = &core_ck,
1041 .init = &omap2_init_clksel_parent,
1042 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1043 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1044 .clksel = div4_core_clksel,
1045 .recalc = &omap2_clksel_recalc,
1046};
1047
1048static struct clk mpu_ck = {
1049 .name = "mpu_ck",
1050 .ops = &clkops_null,
1051 .parent = &dpll1_x2m2_ck,
1052 .clkdm_name = "mpu_clkdm",
1053 .recalc = &followparent_recalc,
1054};
1055
1056/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1057static const struct clksel_rate arm_fck_rates[] = {
1058 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1059 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1060 { .div = 0 },
1061};
1062
1063static const struct clksel arm_fck_clksel[] = {
1064 { .parent = &mpu_ck, .rates = arm_fck_rates },
1065 { .parent = NULL }
1066};
1067
1068static struct clk arm_fck = {
1069 .name = "arm_fck",
1070 .ops = &clkops_null,
1071 .parent = &mpu_ck,
1072 .init = &omap2_init_clksel_parent,
1073 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1074 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1075 .clksel = arm_fck_clksel,
1076 .recalc = &omap2_clksel_recalc,
1077};
1078
1079/* XXX What about neon_clkdm ? */
1080
1081/*
1082 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1083 * although it is referenced - so this is a guess
1084 */
1085static struct clk emu_mpu_alwon_ck = {
1086 .name = "emu_mpu_alwon_ck",
1087 .ops = &clkops_null,
1088 .parent = &mpu_ck,
1089 .recalc = &followparent_recalc,
1090};
1091
1092static struct clk dpll2_fck = {
1093 .name = "dpll2_fck",
1094 .ops = &clkops_null,
1095 .parent = &core_ck,
1096 .init = &omap2_init_clksel_parent,
1097 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1098 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1099 .clksel = div4_core_clksel,
1100 .recalc = &omap2_clksel_recalc,
1101};
1102
1103static struct clk iva2_ck = {
1104 .name = "iva2_ck",
1105 .ops = &clkops_omap2_dflt_wait,
1106 .parent = &dpll2_m2_ck,
1107 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1108 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1109 .clkdm_name = "iva2_clkdm",
1110 .recalc = &followparent_recalc,
1111};
1112
1113/* Common interface clocks */
1114
1115static const struct clksel div2_core_clksel[] = {
1116 { .parent = &core_ck, .rates = div2_rates },
1117 { .parent = NULL }
1118};
1119
1120static struct clk l3_ick = {
1121 .name = "l3_ick",
1122 .ops = &clkops_null,
1123 .parent = &core_ck,
1124 .init = &omap2_init_clksel_parent,
1125 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1126 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1127 .clksel = div2_core_clksel,
1128 .recalc = &omap2_clksel_recalc,
1129};
1130
1131static const struct clksel div2_l3_clksel[] = {
1132 { .parent = &l3_ick, .rates = div2_rates },
1133 { .parent = NULL }
1134};
1135
1136static struct clk l4_ick = {
1137 .name = "l4_ick",
1138 .ops = &clkops_null,
1139 .parent = &l3_ick,
1140 .init = &omap2_init_clksel_parent,
1141 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1142 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1143 .clksel = div2_l3_clksel,
1144 .recalc = &omap2_clksel_recalc,
1145
1146};
1147
1148static const struct clksel div2_l4_clksel[] = {
1149 { .parent = &l4_ick, .rates = div2_rates },
1150 { .parent = NULL }
1151};
1152
1153static struct clk rm_ick = {
1154 .name = "rm_ick",
1155 .ops = &clkops_null,
1156 .parent = &l4_ick,
1157 .init = &omap2_init_clksel_parent,
1158 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1159 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1160 .clksel = div2_l4_clksel,
1161 .recalc = &omap2_clksel_recalc,
1162};
1163
1164/* GFX power domain */
1165
1166/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1167
1168static const struct clksel gfx_l3_clksel[] = {
1169 { .parent = &l3_ick, .rates = gfx_l3_rates },
1170 { .parent = NULL }
1171};
1172
1173/*
1174 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1175 * This interface clock does not have a CM_AUTOIDLE bit
1176 */
1177static struct clk gfx_l3_ck = {
1178 .name = "gfx_l3_ck",
1179 .ops = &clkops_omap2_dflt_wait,
1180 .parent = &l3_ick,
1181 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1182 .enable_bit = OMAP_EN_GFX_SHIFT,
1183 .recalc = &followparent_recalc,
1184};
1185
1186static struct clk gfx_l3_fck = {
1187 .name = "gfx_l3_fck",
1188 .ops = &clkops_null,
1189 .parent = &gfx_l3_ck,
1190 .init = &omap2_init_clksel_parent,
1191 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1192 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1193 .clksel = gfx_l3_clksel,
1194 .clkdm_name = "gfx_3430es1_clkdm",
1195 .recalc = &omap2_clksel_recalc,
1196};
1197
1198static struct clk gfx_l3_ick = {
1199 .name = "gfx_l3_ick",
1200 .ops = &clkops_null,
1201 .parent = &gfx_l3_ck,
1202 .clkdm_name = "gfx_3430es1_clkdm",
1203 .recalc = &followparent_recalc,
1204};
1205
1206static struct clk gfx_cg1_ck = {
1207 .name = "gfx_cg1_ck",
1208 .ops = &clkops_omap2_dflt_wait,
1209 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1210 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1211 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1212 .clkdm_name = "gfx_3430es1_clkdm",
1213 .recalc = &followparent_recalc,
1214};
1215
1216static struct clk gfx_cg2_ck = {
1217 .name = "gfx_cg2_ck",
1218 .ops = &clkops_omap2_dflt_wait,
1219 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1220 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1221 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1222 .clkdm_name = "gfx_3430es1_clkdm",
1223 .recalc = &followparent_recalc,
1224};
1225
1226/* SGX power domain - 3430ES2 only */
1227
1228static const struct clksel_rate sgx_core_rates[] = {
1229 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1230 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1231 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1232 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1233 { .div = 0 },
1234};
1235
1236static const struct clksel_rate sgx_192m_rates[] = {
1237 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1238 { .div = 0 },
1239};
1240
1241static const struct clksel_rate sgx_corex2_rates[] = {
1242 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1243 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1244 { .div = 0 },
1245};
1246
1247static const struct clksel_rate sgx_96m_rates[] = {
1248 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1249 { .div = 0 },
1250};
1251
1252static const struct clksel sgx_clksel[] = {
1253 { .parent = &core_ck, .rates = sgx_core_rates },
1254 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1255 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1256 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1257 { .parent = NULL }
1258};
1259
1260static struct clk sgx_fck = {
1261 .name = "sgx_fck",
1262 .ops = &clkops_omap2_dflt_wait,
1263 .init = &omap2_init_clksel_parent,
1264 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1265 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1266 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1267 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1268 .clksel = sgx_clksel,
1269 .clkdm_name = "sgx_clkdm",
1270 .recalc = &omap2_clksel_recalc,
1271 .set_rate = &omap2_clksel_set_rate,
1272 .round_rate = &omap2_clksel_round_rate
1273};
1274
1275/* This interface clock does not have a CM_AUTOIDLE bit */
1276static struct clk sgx_ick = {
1277 .name = "sgx_ick",
1278 .ops = &clkops_omap2_dflt_wait,
1279 .parent = &l3_ick,
1280 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1281 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1282 .clkdm_name = "sgx_clkdm",
1283 .recalc = &followparent_recalc,
1284};
1285
1286/* CORE power domain */
1287
1288static struct clk d2d_26m_fck = {
1289 .name = "d2d_26m_fck",
1290 .ops = &clkops_omap2_dflt_wait,
1291 .parent = &sys_ck,
1292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1293 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1294 .clkdm_name = "d2d_clkdm",
1295 .recalc = &followparent_recalc,
1296};
1297
1298static struct clk modem_fck = {
1299 .name = "modem_fck",
1300 .ops = &clkops_omap2_mdmclk_dflt_wait,
1301 .parent = &sys_ck,
1302 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1303 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1304 .clkdm_name = "d2d_clkdm",
1305 .recalc = &followparent_recalc,
1306};
1307
1308static struct clk sad2d_ick = {
1309 .name = "sad2d_ick",
1310 .ops = &clkops_omap2_iclk_dflt_wait,
1311 .parent = &l3_ick,
1312 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1313 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1314 .clkdm_name = "d2d_clkdm",
1315 .recalc = &followparent_recalc,
1316};
1317
1318static struct clk mad2d_ick = {
1319 .name = "mad2d_ick",
1320 .ops = &clkops_omap2_iclk_dflt_wait,
1321 .parent = &l3_ick,
1322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1323 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1324 .clkdm_name = "d2d_clkdm",
1325 .recalc = &followparent_recalc,
1326};
1327
1328static const struct clksel omap343x_gpt_clksel[] = {
1329 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1330 { .parent = &sys_ck, .rates = gpt_sys_rates },
1331 { .parent = NULL}
1332};
1333
1334static struct clk gpt10_fck = {
1335 .name = "gpt10_fck",
1336 .ops = &clkops_omap2_dflt_wait,
1337 .parent = &sys_ck,
1338 .init = &omap2_init_clksel_parent,
1339 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1340 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1341 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1342 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1343 .clksel = omap343x_gpt_clksel,
1344 .clkdm_name = "core_l4_clkdm",
1345 .recalc = &omap2_clksel_recalc,
1346};
1347
1348static struct clk gpt11_fck = {
1349 .name = "gpt11_fck",
1350 .ops = &clkops_omap2_dflt_wait,
1351 .parent = &sys_ck,
1352 .init = &omap2_init_clksel_parent,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1354 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1355 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1356 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1357 .clksel = omap343x_gpt_clksel,
1358 .clkdm_name = "core_l4_clkdm",
1359 .recalc = &omap2_clksel_recalc,
1360};
1361
1362static struct clk cpefuse_fck = {
1363 .name = "cpefuse_fck",
1364 .ops = &clkops_omap2_dflt,
1365 .parent = &sys_ck,
1366 .clkdm_name = "core_l4_clkdm",
1367 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1368 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1369 .recalc = &followparent_recalc,
1370};
1371
1372static struct clk ts_fck = {
1373 .name = "ts_fck",
1374 .ops = &clkops_omap2_dflt,
1375 .parent = &omap_32k_fck,
1376 .clkdm_name = "core_l4_clkdm",
1377 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1378 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1379 .recalc = &followparent_recalc,
1380};
1381
1382static struct clk usbtll_fck = {
1383 .name = "usbtll_fck",
1384 .ops = &clkops_omap2_dflt_wait,
1385 .parent = &dpll5_m2_ck,
1386 .clkdm_name = "core_l4_clkdm",
1387 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1388 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1389 .recalc = &followparent_recalc,
1390};
1391
1392/* CORE 96M FCLK-derived clocks */
1393
1394static struct clk core_96m_fck = {
1395 .name = "core_96m_fck",
1396 .ops = &clkops_null,
1397 .parent = &omap_96m_fck,
1398 .clkdm_name = "core_l4_clkdm",
1399 .recalc = &followparent_recalc,
1400};
1401
1402static struct clk mmchs3_fck = {
1403 .name = "mmchs3_fck",
1404 .ops = &clkops_omap2_dflt_wait,
1405 .parent = &core_96m_fck,
1406 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1407 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1408 .clkdm_name = "core_l4_clkdm",
1409 .recalc = &followparent_recalc,
1410};
1411
1412static struct clk mmchs2_fck = {
1413 .name = "mmchs2_fck",
1414 .ops = &clkops_omap2_dflt_wait,
1415 .parent = &core_96m_fck,
1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1418 .clkdm_name = "core_l4_clkdm",
1419 .recalc = &followparent_recalc,
1420};
1421
1422static struct clk mspro_fck = {
1423 .name = "mspro_fck",
1424 .ops = &clkops_omap2_dflt_wait,
1425 .parent = &core_96m_fck,
1426 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1427 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1428 .clkdm_name = "core_l4_clkdm",
1429 .recalc = &followparent_recalc,
1430};
1431
1432static struct clk mmchs1_fck = {
1433 .name = "mmchs1_fck",
1434 .ops = &clkops_omap2_dflt_wait,
1435 .parent = &core_96m_fck,
1436 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1438 .clkdm_name = "core_l4_clkdm",
1439 .recalc = &followparent_recalc,
1440};
1441
1442static struct clk i2c3_fck = {
1443 .name = "i2c3_fck",
1444 .ops = &clkops_omap2_dflt_wait,
1445 .parent = &core_96m_fck,
1446 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1447 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1448 .clkdm_name = "core_l4_clkdm",
1449 .recalc = &followparent_recalc,
1450};
1451
1452static struct clk i2c2_fck = {
1453 .name = "i2c2_fck",
1454 .ops = &clkops_omap2_dflt_wait,
1455 .parent = &core_96m_fck,
1456 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1457 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1458 .clkdm_name = "core_l4_clkdm",
1459 .recalc = &followparent_recalc,
1460};
1461
1462static struct clk i2c1_fck = {
1463 .name = "i2c1_fck",
1464 .ops = &clkops_omap2_dflt_wait,
1465 .parent = &core_96m_fck,
1466 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1467 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1468 .clkdm_name = "core_l4_clkdm",
1469 .recalc = &followparent_recalc,
1470};
1471
1472/*
1473 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1474 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1475 */
1476static const struct clksel_rate common_mcbsp_96m_rates[] = {
1477 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1478 { .div = 0 }
1479};
1480
1481static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1482 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1483 { .div = 0 }
1484};
1485
1486static const struct clksel mcbsp_15_clksel[] = {
1487 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1488 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1489 { .parent = NULL }
1490};
1491
1492static struct clk mcbsp5_fck = {
1493 .name = "mcbsp5_fck",
1494 .ops = &clkops_omap2_dflt_wait,
1495 .init = &omap2_init_clksel_parent,
1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1498 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1499 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1500 .clksel = mcbsp_15_clksel,
1501 .clkdm_name = "core_l4_clkdm",
1502 .recalc = &omap2_clksel_recalc,
1503};
1504
1505static struct clk mcbsp1_fck = {
1506 .name = "mcbsp1_fck",
1507 .ops = &clkops_omap2_dflt_wait,
1508 .init = &omap2_init_clksel_parent,
1509 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1510 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1511 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1512 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1513 .clksel = mcbsp_15_clksel,
1514 .clkdm_name = "core_l4_clkdm",
1515 .recalc = &omap2_clksel_recalc,
1516};
1517
1518/* CORE_48M_FCK-derived clocks */
1519
1520static struct clk core_48m_fck = {
1521 .name = "core_48m_fck",
1522 .ops = &clkops_null,
1523 .parent = &omap_48m_fck,
1524 .clkdm_name = "core_l4_clkdm",
1525 .recalc = &followparent_recalc,
1526};
1527
1528static struct clk mcspi4_fck = {
1529 .name = "mcspi4_fck",
1530 .ops = &clkops_omap2_dflt_wait,
1531 .parent = &core_48m_fck,
1532 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1533 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1534 .recalc = &followparent_recalc,
1535 .clkdm_name = "core_l4_clkdm",
1536};
1537
1538static struct clk mcspi3_fck = {
1539 .name = "mcspi3_fck",
1540 .ops = &clkops_omap2_dflt_wait,
1541 .parent = &core_48m_fck,
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1544 .recalc = &followparent_recalc,
1545 .clkdm_name = "core_l4_clkdm",
1546};
1547
1548static struct clk mcspi2_fck = {
1549 .name = "mcspi2_fck",
1550 .ops = &clkops_omap2_dflt_wait,
1551 .parent = &core_48m_fck,
1552 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1553 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1554 .recalc = &followparent_recalc,
1555 .clkdm_name = "core_l4_clkdm",
1556};
1557
1558static struct clk mcspi1_fck = {
1559 .name = "mcspi1_fck",
1560 .ops = &clkops_omap2_dflt_wait,
1561 .parent = &core_48m_fck,
1562 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1563 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1564 .recalc = &followparent_recalc,
1565 .clkdm_name = "core_l4_clkdm",
1566};
1567
1568static struct clk uart2_fck = {
1569 .name = "uart2_fck",
1570 .ops = &clkops_omap2_dflt_wait,
1571 .parent = &core_48m_fck,
1572 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1573 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1574 .clkdm_name = "core_l4_clkdm",
1575 .recalc = &followparent_recalc,
1576};
1577
1578static struct clk uart1_fck = {
1579 .name = "uart1_fck",
1580 .ops = &clkops_omap2_dflt_wait,
1581 .parent = &core_48m_fck,
1582 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1583 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1584 .clkdm_name = "core_l4_clkdm",
1585 .recalc = &followparent_recalc,
1586};
1587
1588static struct clk fshostusb_fck = {
1589 .name = "fshostusb_fck",
1590 .ops = &clkops_omap2_dflt_wait,
1591 .parent = &core_48m_fck,
1592 .clkdm_name = "core_l4_clkdm",
1593 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1595 .recalc = &followparent_recalc,
1596};
1597
1598/* CORE_12M_FCK based clocks */
1599
1600static struct clk core_12m_fck = {
1601 .name = "core_12m_fck",
1602 .ops = &clkops_null,
1603 .parent = &omap_12m_fck,
1604 .clkdm_name = "core_l4_clkdm",
1605 .recalc = &followparent_recalc,
1606};
1607
1608static struct clk hdq_fck = {
1609 .name = "hdq_fck",
1610 .ops = &clkops_omap2_dflt_wait,
1611 .parent = &core_12m_fck,
1612 .clkdm_name = "core_l4_clkdm",
1613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1614 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1615 .recalc = &followparent_recalc,
1616};
1617
1618/* DPLL3-derived clock */
1619
1620static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1621 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1622 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1623 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1624 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1625 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1626 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1627 { .div = 0 }
1628};
1629
1630static const struct clksel ssi_ssr_clksel[] = {
1631 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1632 { .parent = NULL }
1633};
1634
1635static struct clk ssi_ssr_fck_3430es1 = {
1636 .name = "ssi_ssr_fck",
1637 .ops = &clkops_omap2_dflt,
1638 .init = &omap2_init_clksel_parent,
1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1640 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1641 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1642 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1643 .clksel = ssi_ssr_clksel,
1644 .clkdm_name = "core_l4_clkdm",
1645 .recalc = &omap2_clksel_recalc,
1646};
1647
1648static struct clk ssi_ssr_fck_3430es2 = {
1649 .name = "ssi_ssr_fck",
1650 .ops = &clkops_omap3430es2_ssi_wait,
1651 .init = &omap2_init_clksel_parent,
1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1654 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1655 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1656 .clksel = ssi_ssr_clksel,
1657 .clkdm_name = "core_l4_clkdm",
1658 .recalc = &omap2_clksel_recalc,
1659};
1660
1661static struct clk ssi_sst_fck_3430es1 = {
1662 .name = "ssi_sst_fck",
1663 .ops = &clkops_null,
1664 .parent = &ssi_ssr_fck_3430es1,
1665 .fixed_div = 2,
1666 .recalc = &omap_fixed_divisor_recalc,
1667};
1668
1669static struct clk ssi_sst_fck_3430es2 = {
1670 .name = "ssi_sst_fck",
1671 .ops = &clkops_null,
1672 .parent = &ssi_ssr_fck_3430es2,
1673 .fixed_div = 2,
1674 .recalc = &omap_fixed_divisor_recalc,
1675};
1676
1677
1678
1679/* CORE_L3_ICK based clocks */
1680
1681/*
1682 * XXX must add clk_enable/clk_disable for these if standard code won't
1683 * handle it
1684 */
1685static struct clk core_l3_ick = {
1686 .name = "core_l3_ick",
1687 .ops = &clkops_null,
1688 .parent = &l3_ick,
1689 .clkdm_name = "core_l3_clkdm",
1690 .recalc = &followparent_recalc,
1691};
1692
1693static struct clk hsotgusb_ick_3430es1 = {
1694 .name = "hsotgusb_ick",
1695 .ops = &clkops_omap2_iclk_dflt,
1696 .parent = &core_l3_ick,
1697 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1698 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1699 .clkdm_name = "core_l3_clkdm",
1700 .recalc = &followparent_recalc,
1701};
1702
1703static struct clk hsotgusb_ick_3430es2 = {
1704 .name = "hsotgusb_ick",
1705 .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
1706 .parent = &core_l3_ick,
1707 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1708 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1709 .clkdm_name = "core_l3_clkdm",
1710 .recalc = &followparent_recalc,
1711};
1712
1713/* This interface clock does not have a CM_AUTOIDLE bit */
1714static struct clk sdrc_ick = {
1715 .name = "sdrc_ick",
1716 .ops = &clkops_omap2_dflt_wait,
1717 .parent = &core_l3_ick,
1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1719 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1720 .flags = ENABLE_ON_INIT,
1721 .clkdm_name = "core_l3_clkdm",
1722 .recalc = &followparent_recalc,
1723};
1724
1725static struct clk gpmc_fck = {
1726 .name = "gpmc_fck",
1727 .ops = &clkops_null,
1728 .parent = &core_l3_ick,
1729 .flags = ENABLE_ON_INIT, /* huh? */
1730 .clkdm_name = "core_l3_clkdm",
1731 .recalc = &followparent_recalc,
1732};
1733
1734/* SECURITY_L3_ICK based clocks */
1735
1736static struct clk security_l3_ick = {
1737 .name = "security_l3_ick",
1738 .ops = &clkops_null,
1739 .parent = &l3_ick,
1740 .recalc = &followparent_recalc,
1741};
1742
1743static struct clk pka_ick = {
1744 .name = "pka_ick",
1745 .ops = &clkops_omap2_iclk_dflt_wait,
1746 .parent = &security_l3_ick,
1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1748 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1749 .recalc = &followparent_recalc,
1750};
1751
1752/* CORE_L4_ICK based clocks */
1753
1754static struct clk core_l4_ick = {
1755 .name = "core_l4_ick",
1756 .ops = &clkops_null,
1757 .parent = &l4_ick,
1758 .clkdm_name = "core_l4_clkdm",
1759 .recalc = &followparent_recalc,
1760};
1761
1762static struct clk usbtll_ick = {
1763 .name = "usbtll_ick",
1764 .ops = &clkops_omap2_iclk_dflt_wait,
1765 .parent = &core_l4_ick,
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1767 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1768 .clkdm_name = "core_l4_clkdm",
1769 .recalc = &followparent_recalc,
1770};
1771
1772static struct clk mmchs3_ick = {
1773 .name = "mmchs3_ick",
1774 .ops = &clkops_omap2_iclk_dflt_wait,
1775 .parent = &core_l4_ick,
1776 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1778 .clkdm_name = "core_l4_clkdm",
1779 .recalc = &followparent_recalc,
1780};
1781
1782/* Intersystem Communication Registers - chassis mode only */
1783static struct clk icr_ick = {
1784 .name = "icr_ick",
1785 .ops = &clkops_omap2_iclk_dflt_wait,
1786 .parent = &core_l4_ick,
1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1789 .clkdm_name = "core_l4_clkdm",
1790 .recalc = &followparent_recalc,
1791};
1792
1793static struct clk aes2_ick = {
1794 .name = "aes2_ick",
1795 .ops = &clkops_omap2_iclk_dflt_wait,
1796 .parent = &core_l4_ick,
1797 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1799 .clkdm_name = "core_l4_clkdm",
1800 .recalc = &followparent_recalc,
1801};
1802
1803static struct clk sha12_ick = {
1804 .name = "sha12_ick",
1805 .ops = &clkops_omap2_iclk_dflt_wait,
1806 .parent = &core_l4_ick,
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1809 .clkdm_name = "core_l4_clkdm",
1810 .recalc = &followparent_recalc,
1811};
1812
1813static struct clk des2_ick = {
1814 .name = "des2_ick",
1815 .ops = &clkops_omap2_iclk_dflt_wait,
1816 .parent = &core_l4_ick,
1817 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1818 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1819 .clkdm_name = "core_l4_clkdm",
1820 .recalc = &followparent_recalc,
1821};
1822
1823static struct clk mmchs2_ick = {
1824 .name = "mmchs2_ick",
1825 .ops = &clkops_omap2_iclk_dflt_wait,
1826 .parent = &core_l4_ick,
1827 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1828 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1829 .clkdm_name = "core_l4_clkdm",
1830 .recalc = &followparent_recalc,
1831};
1832
1833static struct clk mmchs1_ick = {
1834 .name = "mmchs1_ick",
1835 .ops = &clkops_omap2_iclk_dflt_wait,
1836 .parent = &core_l4_ick,
1837 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1838 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1839 .clkdm_name = "core_l4_clkdm",
1840 .recalc = &followparent_recalc,
1841};
1842
1843static struct clk mspro_ick = {
1844 .name = "mspro_ick",
1845 .ops = &clkops_omap2_iclk_dflt_wait,
1846 .parent = &core_l4_ick,
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1849 .clkdm_name = "core_l4_clkdm",
1850 .recalc = &followparent_recalc,
1851};
1852
1853static struct clk hdq_ick = {
1854 .name = "hdq_ick",
1855 .ops = &clkops_omap2_iclk_dflt_wait,
1856 .parent = &core_l4_ick,
1857 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1858 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1859 .clkdm_name = "core_l4_clkdm",
1860 .recalc = &followparent_recalc,
1861};
1862
1863static struct clk mcspi4_ick = {
1864 .name = "mcspi4_ick",
1865 .ops = &clkops_omap2_iclk_dflt_wait,
1866 .parent = &core_l4_ick,
1867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1868 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1869 .clkdm_name = "core_l4_clkdm",
1870 .recalc = &followparent_recalc,
1871};
1872
1873static struct clk mcspi3_ick = {
1874 .name = "mcspi3_ick",
1875 .ops = &clkops_omap2_iclk_dflt_wait,
1876 .parent = &core_l4_ick,
1877 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1878 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1879 .clkdm_name = "core_l4_clkdm",
1880 .recalc = &followparent_recalc,
1881};
1882
1883static struct clk mcspi2_ick = {
1884 .name = "mcspi2_ick",
1885 .ops = &clkops_omap2_iclk_dflt_wait,
1886 .parent = &core_l4_ick,
1887 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1888 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1889 .clkdm_name = "core_l4_clkdm",
1890 .recalc = &followparent_recalc,
1891};
1892
1893static struct clk mcspi1_ick = {
1894 .name = "mcspi1_ick",
1895 .ops = &clkops_omap2_iclk_dflt_wait,
1896 .parent = &core_l4_ick,
1897 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1898 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1899 .clkdm_name = "core_l4_clkdm",
1900 .recalc = &followparent_recalc,
1901};
1902
1903static struct clk i2c3_ick = {
1904 .name = "i2c3_ick",
1905 .ops = &clkops_omap2_iclk_dflt_wait,
1906 .parent = &core_l4_ick,
1907 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1908 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1909 .clkdm_name = "core_l4_clkdm",
1910 .recalc = &followparent_recalc,
1911};
1912
1913static struct clk i2c2_ick = {
1914 .name = "i2c2_ick",
1915 .ops = &clkops_omap2_iclk_dflt_wait,
1916 .parent = &core_l4_ick,
1917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1918 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1919 .clkdm_name = "core_l4_clkdm",
1920 .recalc = &followparent_recalc,
1921};
1922
1923static struct clk i2c1_ick = {
1924 .name = "i2c1_ick",
1925 .ops = &clkops_omap2_iclk_dflt_wait,
1926 .parent = &core_l4_ick,
1927 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1928 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1929 .clkdm_name = "core_l4_clkdm",
1930 .recalc = &followparent_recalc,
1931};
1932
1933static struct clk uart2_ick = {
1934 .name = "uart2_ick",
1935 .ops = &clkops_omap2_iclk_dflt_wait,
1936 .parent = &core_l4_ick,
1937 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1938 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1939 .clkdm_name = "core_l4_clkdm",
1940 .recalc = &followparent_recalc,
1941};
1942
1943static struct clk uart1_ick = {
1944 .name = "uart1_ick",
1945 .ops = &clkops_omap2_iclk_dflt_wait,
1946 .parent = &core_l4_ick,
1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1948 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1949 .clkdm_name = "core_l4_clkdm",
1950 .recalc = &followparent_recalc,
1951};
1952
1953static struct clk gpt11_ick = {
1954 .name = "gpt11_ick",
1955 .ops = &clkops_omap2_iclk_dflt_wait,
1956 .parent = &core_l4_ick,
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1958 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1959 .clkdm_name = "core_l4_clkdm",
1960 .recalc = &followparent_recalc,
1961};
1962
1963static struct clk gpt10_ick = {
1964 .name = "gpt10_ick",
1965 .ops = &clkops_omap2_iclk_dflt_wait,
1966 .parent = &core_l4_ick,
1967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1968 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1969 .clkdm_name = "core_l4_clkdm",
1970 .recalc = &followparent_recalc,
1971};
1972
1973static struct clk mcbsp5_ick = {
1974 .name = "mcbsp5_ick",
1975 .ops = &clkops_omap2_iclk_dflt_wait,
1976 .parent = &core_l4_ick,
1977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1978 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1979 .clkdm_name = "core_l4_clkdm",
1980 .recalc = &followparent_recalc,
1981};
1982
1983static struct clk mcbsp1_ick = {
1984 .name = "mcbsp1_ick",
1985 .ops = &clkops_omap2_iclk_dflt_wait,
1986 .parent = &core_l4_ick,
1987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1988 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1989 .clkdm_name = "core_l4_clkdm",
1990 .recalc = &followparent_recalc,
1991};
1992
1993static struct clk fac_ick = {
1994 .name = "fac_ick",
1995 .ops = &clkops_omap2_iclk_dflt_wait,
1996 .parent = &core_l4_ick,
1997 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1999 .clkdm_name = "core_l4_clkdm",
2000 .recalc = &followparent_recalc,
2001};
2002
2003static struct clk mailboxes_ick = {
2004 .name = "mailboxes_ick",
2005 .ops = &clkops_omap2_iclk_dflt_wait,
2006 .parent = &core_l4_ick,
2007 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2008 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2009 .clkdm_name = "core_l4_clkdm",
2010 .recalc = &followparent_recalc,
2011};
2012
2013static struct clk omapctrl_ick = {
2014 .name = "omapctrl_ick",
2015 .ops = &clkops_omap2_iclk_dflt_wait,
2016 .parent = &core_l4_ick,
2017 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2018 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2019 .flags = ENABLE_ON_INIT,
2020 .clkdm_name = "core_l4_clkdm",
2021 .recalc = &followparent_recalc,
2022};
2023
2024/* SSI_L4_ICK based clocks */
2025
2026static struct clk ssi_l4_ick = {
2027 .name = "ssi_l4_ick",
2028 .ops = &clkops_null,
2029 .parent = &l4_ick,
2030 .clkdm_name = "core_l4_clkdm",
2031 .recalc = &followparent_recalc,
2032};
2033
2034static struct clk ssi_ick_3430es1 = {
2035 .name = "ssi_ick",
2036 .ops = &clkops_omap2_iclk_dflt,
2037 .parent = &ssi_l4_ick,
2038 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2039 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2040 .clkdm_name = "core_l4_clkdm",
2041 .recalc = &followparent_recalc,
2042};
2043
2044static struct clk ssi_ick_3430es2 = {
2045 .name = "ssi_ick",
2046 .ops = &clkops_omap3430es2_iclk_ssi_wait,
2047 .parent = &ssi_l4_ick,
2048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2050 .clkdm_name = "core_l4_clkdm",
2051 .recalc = &followparent_recalc,
2052};
2053
2054/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2055 * but l4_ick makes more sense to me */
2056
2057static const struct clksel usb_l4_clksel[] = {
2058 { .parent = &l4_ick, .rates = div2_rates },
2059 { .parent = NULL },
2060};
2061
2062static struct clk usb_l4_ick = {
2063 .name = "usb_l4_ick",
2064 .ops = &clkops_omap2_iclk_dflt_wait,
2065 .parent = &l4_ick,
2066 .init = &omap2_init_clksel_parent,
2067 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2068 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2069 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2070 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2071 .clksel = usb_l4_clksel,
2072 .clkdm_name = "core_l4_clkdm",
2073 .recalc = &omap2_clksel_recalc,
2074};
2075
2076/* SECURITY_L4_ICK2 based clocks */
2077
2078static struct clk security_l4_ick2 = {
2079 .name = "security_l4_ick2",
2080 .ops = &clkops_null,
2081 .parent = &l4_ick,
2082 .recalc = &followparent_recalc,
2083};
2084
2085static struct clk aes1_ick = {
2086 .name = "aes1_ick",
2087 .ops = &clkops_omap2_iclk_dflt_wait,
2088 .parent = &security_l4_ick2,
2089 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2090 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2091 .recalc = &followparent_recalc,
2092};
2093
2094static struct clk rng_ick = {
2095 .name = "rng_ick",
2096 .ops = &clkops_omap2_iclk_dflt_wait,
2097 .parent = &security_l4_ick2,
2098 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2099 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2100 .recalc = &followparent_recalc,
2101};
2102
2103static struct clk sha11_ick = {
2104 .name = "sha11_ick",
2105 .ops = &clkops_omap2_iclk_dflt_wait,
2106 .parent = &security_l4_ick2,
2107 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2108 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2109 .recalc = &followparent_recalc,
2110};
2111
2112static struct clk des1_ick = {
2113 .name = "des1_ick",
2114 .ops = &clkops_omap2_iclk_dflt_wait,
2115 .parent = &security_l4_ick2,
2116 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2117 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2118 .recalc = &followparent_recalc,
2119};
2120
2121/* DSS */
2122static struct clk dss1_alwon_fck_3430es1 = {
2123 .name = "dss1_alwon_fck",
2124 .ops = &clkops_omap2_dflt,
2125 .parent = &dpll4_m4x2_ck,
2126 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2127 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2128 .clkdm_name = "dss_clkdm",
2129 .recalc = &followparent_recalc,
2130};
2131
2132static struct clk dss1_alwon_fck_3430es2 = {
2133 .name = "dss1_alwon_fck",
2134 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2135 .parent = &dpll4_m4x2_ck,
2136 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2137 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2138 .clkdm_name = "dss_clkdm",
2139 .recalc = &followparent_recalc,
2140};
2141
2142static struct clk dss_tv_fck = {
2143 .name = "dss_tv_fck",
2144 .ops = &clkops_omap2_dflt,
2145 .parent = &omap_54m_fck,
2146 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2147 .enable_bit = OMAP3430_EN_TV_SHIFT,
2148 .clkdm_name = "dss_clkdm",
2149 .recalc = &followparent_recalc,
2150};
2151
2152static struct clk dss_96m_fck = {
2153 .name = "dss_96m_fck",
2154 .ops = &clkops_omap2_dflt,
2155 .parent = &omap_96m_fck,
2156 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2157 .enable_bit = OMAP3430_EN_TV_SHIFT,
2158 .clkdm_name = "dss_clkdm",
2159 .recalc = &followparent_recalc,
2160};
2161
2162static struct clk dss2_alwon_fck = {
2163 .name = "dss2_alwon_fck",
2164 .ops = &clkops_omap2_dflt,
2165 .parent = &sys_ck,
2166 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2167 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2168 .clkdm_name = "dss_clkdm",
2169 .recalc = &followparent_recalc,
2170};
2171
2172static struct clk dss_ick_3430es1 = {
2173 /* Handles both L3 and L4 clocks */
2174 .name = "dss_ick",
2175 .ops = &clkops_omap2_iclk_dflt,
2176 .parent = &l4_ick,
2177 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2178 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2179 .clkdm_name = "dss_clkdm",
2180 .recalc = &followparent_recalc,
2181};
2182
2183static struct clk dss_ick_3430es2 = {
2184 /* Handles both L3 and L4 clocks */
2185 .name = "dss_ick",
2186 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2187 .parent = &l4_ick,
2188 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2189 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2190 .clkdm_name = "dss_clkdm",
2191 .recalc = &followparent_recalc,
2192};
2193
2194/* CAM */
2195
2196static struct clk cam_mclk = {
2197 .name = "cam_mclk",
2198 .ops = &clkops_omap2_dflt,
2199 .parent = &dpll4_m5x2_ck,
2200 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2201 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2202 .clkdm_name = "cam_clkdm",
2203 .recalc = &followparent_recalc,
2204};
2205
2206static struct clk cam_ick = {
2207 /* Handles both L3 and L4 clocks */
2208 .name = "cam_ick",
2209 .ops = &clkops_omap2_iclk_dflt,
2210 .parent = &l4_ick,
2211 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2212 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2213 .clkdm_name = "cam_clkdm",
2214 .recalc = &followparent_recalc,
2215};
2216
2217static struct clk csi2_96m_fck = {
2218 .name = "csi2_96m_fck",
2219 .ops = &clkops_omap2_dflt,
2220 .parent = &core_96m_fck,
2221 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2222 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2223 .clkdm_name = "cam_clkdm",
2224 .recalc = &followparent_recalc,
2225};
2226
2227/* USBHOST - 3430ES2 only */
2228
2229static struct clk usbhost_120m_fck = {
2230 .name = "usbhost_120m_fck",
2231 .ops = &clkops_omap2_dflt,
2232 .parent = &dpll5_m2_ck,
2233 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2234 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2235 .clkdm_name = "usbhost_clkdm",
2236 .recalc = &followparent_recalc,
2237};
2238
2239static struct clk usbhost_48m_fck = {
2240 .name = "usbhost_48m_fck",
2241 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2242 .parent = &omap_48m_fck,
2243 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2244 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2245 .clkdm_name = "usbhost_clkdm",
2246 .recalc = &followparent_recalc,
2247};
2248
2249static struct clk usbhost_ick = {
2250 /* Handles both L3 and L4 clocks */
2251 .name = "usbhost_ick",
2252 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2253 .parent = &l4_ick,
2254 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2255 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2256 .clkdm_name = "usbhost_clkdm",
2257 .recalc = &followparent_recalc,
2258};
2259
2260/* WKUP */
2261
2262static const struct clksel_rate usim_96m_rates[] = {
2263 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2264 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2265 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2266 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2267 { .div = 0 },
2268};
2269
2270static const struct clksel_rate usim_120m_rates[] = {
2271 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2272 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2273 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2274 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2275 { .div = 0 },
2276};
2277
2278static const struct clksel usim_clksel[] = {
2279 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2280 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2281 { .parent = &sys_ck, .rates = div2_rates },
2282 { .parent = NULL },
2283};
2284
2285/* 3430ES2 only */
2286static struct clk usim_fck = {
2287 .name = "usim_fck",
2288 .ops = &clkops_omap2_dflt_wait,
2289 .init = &omap2_init_clksel_parent,
2290 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2291 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2292 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2293 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2294 .clksel = usim_clksel,
2295 .recalc = &omap2_clksel_recalc,
2296};
2297
2298/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2299static struct clk gpt1_fck = {
2300 .name = "gpt1_fck",
2301 .ops = &clkops_omap2_dflt_wait,
2302 .init = &omap2_init_clksel_parent,
2303 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2304 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2305 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2306 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2307 .clksel = omap343x_gpt_clksel,
2308 .clkdm_name = "wkup_clkdm",
2309 .recalc = &omap2_clksel_recalc,
2310};
2311
2312static struct clk wkup_32k_fck = {
2313 .name = "wkup_32k_fck",
2314 .ops = &clkops_null,
2315 .parent = &omap_32k_fck,
2316 .clkdm_name = "wkup_clkdm",
2317 .recalc = &followparent_recalc,
2318};
2319
2320static struct clk gpio1_dbck = {
2321 .name = "gpio1_dbck",
2322 .ops = &clkops_omap2_dflt,
2323 .parent = &wkup_32k_fck,
2324 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2325 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2326 .clkdm_name = "wkup_clkdm",
2327 .recalc = &followparent_recalc,
2328};
2329
2330static struct clk wdt2_fck = {
2331 .name = "wdt2_fck",
2332 .ops = &clkops_omap2_dflt_wait,
2333 .parent = &wkup_32k_fck,
2334 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2335 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2336 .clkdm_name = "wkup_clkdm",
2337 .recalc = &followparent_recalc,
2338};
2339
2340static struct clk wkup_l4_ick = {
2341 .name = "wkup_l4_ick",
2342 .ops = &clkops_null,
2343 .parent = &sys_ck,
2344 .clkdm_name = "wkup_clkdm",
2345 .recalc = &followparent_recalc,
2346};
2347
2348/* 3430ES2 only */
2349/* Never specifically named in the TRM, so we have to infer a likely name */
2350static struct clk usim_ick = {
2351 .name = "usim_ick",
2352 .ops = &clkops_omap2_iclk_dflt_wait,
2353 .parent = &wkup_l4_ick,
2354 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2355 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2356 .clkdm_name = "wkup_clkdm",
2357 .recalc = &followparent_recalc,
2358};
2359
2360static struct clk wdt2_ick = {
2361 .name = "wdt2_ick",
2362 .ops = &clkops_omap2_iclk_dflt_wait,
2363 .parent = &wkup_l4_ick,
2364 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2365 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2366 .clkdm_name = "wkup_clkdm",
2367 .recalc = &followparent_recalc,
2368};
2369
2370static struct clk wdt1_ick = {
2371 .name = "wdt1_ick",
2372 .ops = &clkops_omap2_iclk_dflt_wait,
2373 .parent = &wkup_l4_ick,
2374 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2375 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2376 .clkdm_name = "wkup_clkdm",
2377 .recalc = &followparent_recalc,
2378};
2379
2380static struct clk gpio1_ick = {
2381 .name = "gpio1_ick",
2382 .ops = &clkops_omap2_iclk_dflt_wait,
2383 .parent = &wkup_l4_ick,
2384 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2385 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2386 .clkdm_name = "wkup_clkdm",
2387 .recalc = &followparent_recalc,
2388};
2389
2390static struct clk omap_32ksync_ick = {
2391 .name = "omap_32ksync_ick",
2392 .ops = &clkops_omap2_iclk_dflt_wait,
2393 .parent = &wkup_l4_ick,
2394 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2395 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2396 .clkdm_name = "wkup_clkdm",
2397 .recalc = &followparent_recalc,
2398};
2399
2400/* XXX This clock no longer exists in 3430 TRM rev F */
2401static struct clk gpt12_ick = {
2402 .name = "gpt12_ick",
2403 .ops = &clkops_omap2_iclk_dflt_wait,
2404 .parent = &wkup_l4_ick,
2405 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2406 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2407 .clkdm_name = "wkup_clkdm",
2408 .recalc = &followparent_recalc,
2409};
2410
2411static struct clk gpt1_ick = {
2412 .name = "gpt1_ick",
2413 .ops = &clkops_omap2_iclk_dflt_wait,
2414 .parent = &wkup_l4_ick,
2415 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2416 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2417 .clkdm_name = "wkup_clkdm",
2418 .recalc = &followparent_recalc,
2419};
2420
2421
2422
2423/* PER clock domain */
2424
2425static struct clk per_96m_fck = {
2426 .name = "per_96m_fck",
2427 .ops = &clkops_null,
2428 .parent = &omap_96m_alwon_fck,
2429 .clkdm_name = "per_clkdm",
2430 .recalc = &followparent_recalc,
2431};
2432
2433static struct clk per_48m_fck = {
2434 .name = "per_48m_fck",
2435 .ops = &clkops_null,
2436 .parent = &omap_48m_fck,
2437 .clkdm_name = "per_clkdm",
2438 .recalc = &followparent_recalc,
2439};
2440
2441static struct clk uart3_fck = {
2442 .name = "uart3_fck",
2443 .ops = &clkops_omap2_dflt_wait,
2444 .parent = &per_48m_fck,
2445 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2446 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2447 .clkdm_name = "per_clkdm",
2448 .recalc = &followparent_recalc,
2449};
2450
2451static struct clk uart4_fck = {
2452 .name = "uart4_fck",
2453 .ops = &clkops_omap2_dflt_wait,
2454 .parent = &per_48m_fck,
2455 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2456 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2457 .clkdm_name = "per_clkdm",
2458 .recalc = &followparent_recalc,
2459};
2460
2461static struct clk uart4_fck_am35xx = {
2462 .name = "uart4_fck",
2463 .ops = &clkops_omap2_dflt_wait,
2464 .parent = &core_48m_fck,
2465 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2466 .enable_bit = AM35XX_EN_UART4_SHIFT,
2467 .clkdm_name = "core_l4_clkdm",
2468 .recalc = &followparent_recalc,
2469};
2470
2471static struct clk gpt2_fck = {
2472 .name = "gpt2_fck",
2473 .ops = &clkops_omap2_dflt_wait,
2474 .init = &omap2_init_clksel_parent,
2475 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2476 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2477 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2478 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2479 .clksel = omap343x_gpt_clksel,
2480 .clkdm_name = "per_clkdm",
2481 .recalc = &omap2_clksel_recalc,
2482};
2483
2484static struct clk gpt3_fck = {
2485 .name = "gpt3_fck",
2486 .ops = &clkops_omap2_dflt_wait,
2487 .init = &omap2_init_clksel_parent,
2488 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2489 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2490 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2491 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2492 .clksel = omap343x_gpt_clksel,
2493 .clkdm_name = "per_clkdm",
2494 .recalc = &omap2_clksel_recalc,
2495};
2496
2497static struct clk gpt4_fck = {
2498 .name = "gpt4_fck",
2499 .ops = &clkops_omap2_dflt_wait,
2500 .init = &omap2_init_clksel_parent,
2501 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2502 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2503 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2504 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2505 .clksel = omap343x_gpt_clksel,
2506 .clkdm_name = "per_clkdm",
2507 .recalc = &omap2_clksel_recalc,
2508};
2509
2510static struct clk gpt5_fck = {
2511 .name = "gpt5_fck",
2512 .ops = &clkops_omap2_dflt_wait,
2513 .init = &omap2_init_clksel_parent,
2514 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2515 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2516 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2517 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2518 .clksel = omap343x_gpt_clksel,
2519 .clkdm_name = "per_clkdm",
2520 .recalc = &omap2_clksel_recalc,
2521};
2522
2523static struct clk gpt6_fck = {
2524 .name = "gpt6_fck",
2525 .ops = &clkops_omap2_dflt_wait,
2526 .init = &omap2_init_clksel_parent,
2527 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2528 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2529 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2530 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2531 .clksel = omap343x_gpt_clksel,
2532 .clkdm_name = "per_clkdm",
2533 .recalc = &omap2_clksel_recalc,
2534};
2535
2536static struct clk gpt7_fck = {
2537 .name = "gpt7_fck",
2538 .ops = &clkops_omap2_dflt_wait,
2539 .init = &omap2_init_clksel_parent,
2540 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2541 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2542 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2543 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2544 .clksel = omap343x_gpt_clksel,
2545 .clkdm_name = "per_clkdm",
2546 .recalc = &omap2_clksel_recalc,
2547};
2548
2549static struct clk gpt8_fck = {
2550 .name = "gpt8_fck",
2551 .ops = &clkops_omap2_dflt_wait,
2552 .init = &omap2_init_clksel_parent,
2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2554 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2555 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2556 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2557 .clksel = omap343x_gpt_clksel,
2558 .clkdm_name = "per_clkdm",
2559 .recalc = &omap2_clksel_recalc,
2560};
2561
2562static struct clk gpt9_fck = {
2563 .name = "gpt9_fck",
2564 .ops = &clkops_omap2_dflt_wait,
2565 .init = &omap2_init_clksel_parent,
2566 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2567 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2568 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2569 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2570 .clksel = omap343x_gpt_clksel,
2571 .clkdm_name = "per_clkdm",
2572 .recalc = &omap2_clksel_recalc,
2573};
2574
2575static struct clk per_32k_alwon_fck = {
2576 .name = "per_32k_alwon_fck",
2577 .ops = &clkops_null,
2578 .parent = &omap_32k_fck,
2579 .clkdm_name = "per_clkdm",
2580 .recalc = &followparent_recalc,
2581};
2582
2583static struct clk gpio6_dbck = {
2584 .name = "gpio6_dbck",
2585 .ops = &clkops_omap2_dflt,
2586 .parent = &per_32k_alwon_fck,
2587 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2588 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2589 .clkdm_name = "per_clkdm",
2590 .recalc = &followparent_recalc,
2591};
2592
2593static struct clk gpio5_dbck = {
2594 .name = "gpio5_dbck",
2595 .ops = &clkops_omap2_dflt,
2596 .parent = &per_32k_alwon_fck,
2597 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2598 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2599 .clkdm_name = "per_clkdm",
2600 .recalc = &followparent_recalc,
2601};
2602
2603static struct clk gpio4_dbck = {
2604 .name = "gpio4_dbck",
2605 .ops = &clkops_omap2_dflt,
2606 .parent = &per_32k_alwon_fck,
2607 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2608 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2609 .clkdm_name = "per_clkdm",
2610 .recalc = &followparent_recalc,
2611};
2612
2613static struct clk gpio3_dbck = {
2614 .name = "gpio3_dbck",
2615 .ops = &clkops_omap2_dflt,
2616 .parent = &per_32k_alwon_fck,
2617 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2618 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2619 .clkdm_name = "per_clkdm",
2620 .recalc = &followparent_recalc,
2621};
2622
2623static struct clk gpio2_dbck = {
2624 .name = "gpio2_dbck",
2625 .ops = &clkops_omap2_dflt,
2626 .parent = &per_32k_alwon_fck,
2627 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2628 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2629 .clkdm_name = "per_clkdm",
2630 .recalc = &followparent_recalc,
2631};
2632
2633static struct clk wdt3_fck = {
2634 .name = "wdt3_fck",
2635 .ops = &clkops_omap2_dflt_wait,
2636 .parent = &per_32k_alwon_fck,
2637 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2638 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2639 .clkdm_name = "per_clkdm",
2640 .recalc = &followparent_recalc,
2641};
2642
2643static struct clk per_l4_ick = {
2644 .name = "per_l4_ick",
2645 .ops = &clkops_null,
2646 .parent = &l4_ick,
2647 .clkdm_name = "per_clkdm",
2648 .recalc = &followparent_recalc,
2649};
2650
2651static struct clk gpio6_ick = {
2652 .name = "gpio6_ick",
2653 .ops = &clkops_omap2_iclk_dflt_wait,
2654 .parent = &per_l4_ick,
2655 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2656 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2657 .clkdm_name = "per_clkdm",
2658 .recalc = &followparent_recalc,
2659};
2660
2661static struct clk gpio5_ick = {
2662 .name = "gpio5_ick",
2663 .ops = &clkops_omap2_iclk_dflt_wait,
2664 .parent = &per_l4_ick,
2665 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2666 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2667 .clkdm_name = "per_clkdm",
2668 .recalc = &followparent_recalc,
2669};
2670
2671static struct clk gpio4_ick = {
2672 .name = "gpio4_ick",
2673 .ops = &clkops_omap2_iclk_dflt_wait,
2674 .parent = &per_l4_ick,
2675 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2676 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2677 .clkdm_name = "per_clkdm",
2678 .recalc = &followparent_recalc,
2679};
2680
2681static struct clk gpio3_ick = {
2682 .name = "gpio3_ick",
2683 .ops = &clkops_omap2_iclk_dflt_wait,
2684 .parent = &per_l4_ick,
2685 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2686 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2687 .clkdm_name = "per_clkdm",
2688 .recalc = &followparent_recalc,
2689};
2690
2691static struct clk gpio2_ick = {
2692 .name = "gpio2_ick",
2693 .ops = &clkops_omap2_iclk_dflt_wait,
2694 .parent = &per_l4_ick,
2695 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2696 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2697 .clkdm_name = "per_clkdm",
2698 .recalc = &followparent_recalc,
2699};
2700
2701static struct clk wdt3_ick = {
2702 .name = "wdt3_ick",
2703 .ops = &clkops_omap2_iclk_dflt_wait,
2704 .parent = &per_l4_ick,
2705 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2706 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2707 .clkdm_name = "per_clkdm",
2708 .recalc = &followparent_recalc,
2709};
2710
2711static struct clk uart3_ick = {
2712 .name = "uart3_ick",
2713 .ops = &clkops_omap2_iclk_dflt_wait,
2714 .parent = &per_l4_ick,
2715 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2716 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2717 .clkdm_name = "per_clkdm",
2718 .recalc = &followparent_recalc,
2719};
2720
2721static struct clk uart4_ick = {
2722 .name = "uart4_ick",
2723 .ops = &clkops_omap2_iclk_dflt_wait,
2724 .parent = &per_l4_ick,
2725 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2726 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2727 .clkdm_name = "per_clkdm",
2728 .recalc = &followparent_recalc,
2729};
2730
2731static struct clk gpt9_ick = {
2732 .name = "gpt9_ick",
2733 .ops = &clkops_omap2_iclk_dflt_wait,
2734 .parent = &per_l4_ick,
2735 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2736 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2737 .clkdm_name = "per_clkdm",
2738 .recalc = &followparent_recalc,
2739};
2740
2741static struct clk gpt8_ick = {
2742 .name = "gpt8_ick",
2743 .ops = &clkops_omap2_iclk_dflt_wait,
2744 .parent = &per_l4_ick,
2745 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2746 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2747 .clkdm_name = "per_clkdm",
2748 .recalc = &followparent_recalc,
2749};
2750
2751static struct clk gpt7_ick = {
2752 .name = "gpt7_ick",
2753 .ops = &clkops_omap2_iclk_dflt_wait,
2754 .parent = &per_l4_ick,
2755 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2756 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2757 .clkdm_name = "per_clkdm",
2758 .recalc = &followparent_recalc,
2759};
2760
2761static struct clk gpt6_ick = {
2762 .name = "gpt6_ick",
2763 .ops = &clkops_omap2_iclk_dflt_wait,
2764 .parent = &per_l4_ick,
2765 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2766 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2767 .clkdm_name = "per_clkdm",
2768 .recalc = &followparent_recalc,
2769};
2770
2771static struct clk gpt5_ick = {
2772 .name = "gpt5_ick",
2773 .ops = &clkops_omap2_iclk_dflt_wait,
2774 .parent = &per_l4_ick,
2775 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2776 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2777 .clkdm_name = "per_clkdm",
2778 .recalc = &followparent_recalc,
2779};
2780
2781static struct clk gpt4_ick = {
2782 .name = "gpt4_ick",
2783 .ops = &clkops_omap2_iclk_dflt_wait,
2784 .parent = &per_l4_ick,
2785 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2786 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2787 .clkdm_name = "per_clkdm",
2788 .recalc = &followparent_recalc,
2789};
2790
2791static struct clk gpt3_ick = {
2792 .name = "gpt3_ick",
2793 .ops = &clkops_omap2_iclk_dflt_wait,
2794 .parent = &per_l4_ick,
2795 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2796 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2797 .clkdm_name = "per_clkdm",
2798 .recalc = &followparent_recalc,
2799};
2800
2801static struct clk gpt2_ick = {
2802 .name = "gpt2_ick",
2803 .ops = &clkops_omap2_iclk_dflt_wait,
2804 .parent = &per_l4_ick,
2805 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2806 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2807 .clkdm_name = "per_clkdm",
2808 .recalc = &followparent_recalc,
2809};
2810
2811static struct clk mcbsp2_ick = {
2812 .name = "mcbsp2_ick",
2813 .ops = &clkops_omap2_iclk_dflt_wait,
2814 .parent = &per_l4_ick,
2815 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2816 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2817 .clkdm_name = "per_clkdm",
2818 .recalc = &followparent_recalc,
2819};
2820
2821static struct clk mcbsp3_ick = {
2822 .name = "mcbsp3_ick",
2823 .ops = &clkops_omap2_iclk_dflt_wait,
2824 .parent = &per_l4_ick,
2825 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2826 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2827 .clkdm_name = "per_clkdm",
2828 .recalc = &followparent_recalc,
2829};
2830
2831static struct clk mcbsp4_ick = {
2832 .name = "mcbsp4_ick",
2833 .ops = &clkops_omap2_iclk_dflt_wait,
2834 .parent = &per_l4_ick,
2835 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2836 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2837 .clkdm_name = "per_clkdm",
2838 .recalc = &followparent_recalc,
2839};
2840
2841static const struct clksel mcbsp_234_clksel[] = {
2842 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2843 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2844 { .parent = NULL }
2845};
2846
2847static struct clk mcbsp2_fck = {
2848 .name = "mcbsp2_fck",
2849 .ops = &clkops_omap2_dflt_wait,
2850 .init = &omap2_init_clksel_parent,
2851 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2852 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2853 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2854 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2855 .clksel = mcbsp_234_clksel,
2856 .clkdm_name = "per_clkdm",
2857 .recalc = &omap2_clksel_recalc,
2858};
2859
2860static struct clk mcbsp3_fck = {
2861 .name = "mcbsp3_fck",
2862 .ops = &clkops_omap2_dflt_wait,
2863 .init = &omap2_init_clksel_parent,
2864 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2865 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2866 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2867 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2868 .clksel = mcbsp_234_clksel,
2869 .clkdm_name = "per_clkdm",
2870 .recalc = &omap2_clksel_recalc,
2871};
2872
2873static struct clk mcbsp4_fck = {
2874 .name = "mcbsp4_fck",
2875 .ops = &clkops_omap2_dflt_wait,
2876 .init = &omap2_init_clksel_parent,
2877 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2878 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2879 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2880 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2881 .clksel = mcbsp_234_clksel,
2882 .clkdm_name = "per_clkdm",
2883 .recalc = &omap2_clksel_recalc,
2884};
2885
2886/* EMU clocks */
2887
2888/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2889
2890static const struct clksel_rate emu_src_sys_rates[] = {
2891 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2892 { .div = 0 },
2893};
2894
2895static const struct clksel_rate emu_src_core_rates[] = {
2896 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2897 { .div = 0 },
2898};
2899
2900static const struct clksel_rate emu_src_per_rates[] = {
2901 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2902 { .div = 0 },
2903};
2904
2905static const struct clksel_rate emu_src_mpu_rates[] = {
2906 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2907 { .div = 0 },
2908};
2909
2910static const struct clksel emu_src_clksel[] = {
2911 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2912 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2913 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2914 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2915 { .parent = NULL },
2916};
2917
2918/*
2919 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2920 * to switch the source of some of the EMU clocks.
2921 * XXX Are there CLKEN bits for these EMU clks?
2922 */
2923static struct clk emu_src_ck = {
2924 .name = "emu_src_ck",
2925 .ops = &clkops_null,
2926 .init = &omap2_init_clksel_parent,
2927 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2928 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2929 .clksel = emu_src_clksel,
2930 .clkdm_name = "emu_clkdm",
2931 .recalc = &omap2_clksel_recalc,
2932};
2933
2934static const struct clksel_rate pclk_emu_rates[] = {
2935 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2936 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2937 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2938 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2939 { .div = 0 },
2940};
2941
2942static const struct clksel pclk_emu_clksel[] = {
2943 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2944 { .parent = NULL },
2945};
2946
2947static struct clk pclk_fck = {
2948 .name = "pclk_fck",
2949 .ops = &clkops_null,
2950 .init = &omap2_init_clksel_parent,
2951 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2952 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2953 .clksel = pclk_emu_clksel,
2954 .recalc = &omap2_clksel_recalc,
2955};
2956
2957static const struct clksel_rate pclkx2_emu_rates[] = {
2958 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2959 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2960 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2961 { .div = 0 },
2962};
2963
2964static const struct clksel pclkx2_emu_clksel[] = {
2965 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2966 { .parent = NULL },
2967};
2968
2969static struct clk pclkx2_fck = {
2970 .name = "pclkx2_fck",
2971 .ops = &clkops_null,
2972 .init = &omap2_init_clksel_parent,
2973 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2974 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2975 .clksel = pclkx2_emu_clksel,
2976 .recalc = &omap2_clksel_recalc,
2977};
2978
2979static const struct clksel atclk_emu_clksel[] = {
2980 { .parent = &emu_src_ck, .rates = div2_rates },
2981 { .parent = NULL },
2982};
2983
2984static struct clk atclk_fck = {
2985 .name = "atclk_fck",
2986 .ops = &clkops_null,
2987 .init = &omap2_init_clksel_parent,
2988 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2989 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2990 .clksel = atclk_emu_clksel,
2991 .recalc = &omap2_clksel_recalc,
2992};
2993
2994static struct clk traceclk_src_fck = {
2995 .name = "traceclk_src_fck",
2996 .ops = &clkops_null,
2997 .init = &omap2_init_clksel_parent,
2998 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2999 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3000 .clksel = emu_src_clksel,
3001 .recalc = &omap2_clksel_recalc,
3002};
3003
3004static const struct clksel_rate traceclk_rates[] = {
3005 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3006 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3007 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3008 { .div = 0 },
3009};
3010
3011static const struct clksel traceclk_clksel[] = {
3012 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3013 { .parent = NULL },
3014};
3015
3016static struct clk traceclk_fck = {
3017 .name = "traceclk_fck",
3018 .ops = &clkops_null,
3019 .init = &omap2_init_clksel_parent,
3020 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3021 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3022 .clksel = traceclk_clksel,
3023 .recalc = &omap2_clksel_recalc,
3024};
3025
3026/* SR clocks */
3027
3028/* SmartReflex fclk (VDD1) */
3029static struct clk sr1_fck = {
3030 .name = "sr1_fck",
3031 .ops = &clkops_omap2_dflt_wait,
3032 .parent = &sys_ck,
3033 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3034 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3035 .clkdm_name = "wkup_clkdm",
3036 .recalc = &followparent_recalc,
3037};
3038
3039/* SmartReflex fclk (VDD2) */
3040static struct clk sr2_fck = {
3041 .name = "sr2_fck",
3042 .ops = &clkops_omap2_dflt_wait,
3043 .parent = &sys_ck,
3044 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3045 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3046 .clkdm_name = "wkup_clkdm",
3047 .recalc = &followparent_recalc,
3048};
3049
3050static struct clk sr_l4_ick = {
3051 .name = "sr_l4_ick",
3052 .ops = &clkops_null, /* RMK: missing? */
3053 .parent = &l4_ick,
3054 .clkdm_name = "core_l4_clkdm",
3055 .recalc = &followparent_recalc,
3056};
3057
3058/* SECURE_32K_FCK clocks */
3059
3060static struct clk gpt12_fck = {
3061 .name = "gpt12_fck",
3062 .ops = &clkops_null,
3063 .parent = &secure_32k_fck,
3064 .clkdm_name = "wkup_clkdm",
3065 .recalc = &followparent_recalc,
3066};
3067
3068static struct clk wdt1_fck = {
3069 .name = "wdt1_fck",
3070 .ops = &clkops_null,
3071 .parent = &secure_32k_fck,
3072 .clkdm_name = "wkup_clkdm",
3073 .recalc = &followparent_recalc,
3074};
3075
3076/* Clocks for AM35XX */
3077static struct clk ipss_ick = {
3078 .name = "ipss_ick",
3079 .ops = &clkops_am35xx_ipss_wait,
3080 .parent = &core_l3_ick,
3081 .clkdm_name = "core_l3_clkdm",
3082 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3083 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3084 .recalc = &followparent_recalc,
3085};
3086
3087static struct clk emac_ick = {
3088 .name = "emac_ick",
3089 .ops = &clkops_am35xx_ipss_module_wait,
3090 .parent = &ipss_ick,
3091 .clkdm_name = "core_l3_clkdm",
3092 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3093 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3094 .recalc = &followparent_recalc,
3095};
3096
3097static struct clk rmii_ck = {
3098 .name = "rmii_ck",
3099 .ops = &clkops_null,
3100 .rate = 50000000,
3101};
3102
3103static struct clk emac_fck = {
3104 .name = "emac_fck",
3105 .ops = &clkops_omap2_dflt,
3106 .parent = &rmii_ck,
3107 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3108 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3109 .recalc = &followparent_recalc,
3110};
3111
3112static struct clk hsotgusb_ick_am35xx = {
3113 .name = "hsotgusb_ick",
3114 .ops = &clkops_am35xx_ipss_module_wait,
3115 .parent = &ipss_ick,
3116 .clkdm_name = "core_l3_clkdm",
3117 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3118 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3119 .recalc = &followparent_recalc,
3120};
3121
3122static struct clk hsotgusb_fck_am35xx = {
3123 .name = "hsotgusb_fck",
3124 .ops = &clkops_omap2_dflt,
3125 .parent = &sys_ck,
3126 .clkdm_name = "core_l3_clkdm",
3127 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3128 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3129 .recalc = &followparent_recalc,
3130};
3131
3132static struct clk hecc_ck = {
3133 .name = "hecc_ck",
3134 .ops = &clkops_am35xx_ipss_module_wait,
3135 .parent = &sys_ck,
3136 .clkdm_name = "core_l3_clkdm",
3137 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3138 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3139 .recalc = &followparent_recalc,
3140};
3141
3142static struct clk vpfe_ick = {
3143 .name = "vpfe_ick",
3144 .ops = &clkops_am35xx_ipss_module_wait,
3145 .parent = &ipss_ick,
3146 .clkdm_name = "core_l3_clkdm",
3147 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3148 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3149 .recalc = &followparent_recalc,
3150};
3151
3152static struct clk pclk_ck = {
3153 .name = "pclk_ck",
3154 .ops = &clkops_null,
3155 .rate = 27000000,
3156};
3157
3158static struct clk vpfe_fck = {
3159 .name = "vpfe_fck",
3160 .ops = &clkops_omap2_dflt,
3161 .parent = &pclk_ck,
3162 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3163 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3164 .recalc = &followparent_recalc,
3165};
3166
3167/*
3168 * The UART1/2 functional clock acts as the functional clock for
3169 * UART4. No separate fclk control available. XXX Well now we have a
3170 * uart4_fck that is apparently used as the UART4 functional clock,
3171 * but it also seems that uart1_fck or uart2_fck are still needed, at
3172 * least for UART4 softresets to complete. This really needs
3173 * clarification.
3174 */
3175static struct clk uart4_ick_am35xx = {
3176 .name = "uart4_ick",
3177 .ops = &clkops_omap2_iclk_dflt_wait,
3178 .parent = &core_l4_ick,
3179 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3180 .enable_bit = AM35XX_EN_UART4_SHIFT,
3181 .clkdm_name = "core_l4_clkdm",
3182 .recalc = &followparent_recalc,
3183};
3184
3185static struct clk dummy_apb_pclk = {
3186 .name = "apb_pclk",
3187 .ops = &clkops_null,
3188};
3189
3190/*
3191 * clkdev
3192 */
3193
3194static struct omap_clk omap3xxx_clks[] = {
3195 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3196 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3197 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3198 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3199 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3200 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
3201 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
3202 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3203 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3204 CLK("twl", "fck", &osc_sys_ck, CK_3XXX),
3205 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3206 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3207 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3208 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3209 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3210 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3211 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3212 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3213 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3214 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3215 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3216 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3217 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3218 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3219 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3220 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3221 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3222 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3223 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3224 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3225 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3226 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3227 CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
3228 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3229 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3230 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3231 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3232 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3233 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3234 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3235 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3236 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3237 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3238 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3239 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3240 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3241 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3242 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3243 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3244 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3245 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3246 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3247 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3248 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3249 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3250 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3251 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3252 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3253 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3254 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3255 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3256 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3257 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3258 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3259 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
3260 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3261 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3262 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3263 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3264 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3265 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3266 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3267 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3268 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3269 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3270 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3271 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3272 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3273 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3274 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3275 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3276 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3277 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3278 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3279 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3280 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
3281 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3282 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
3283 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
3284 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
3285 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
3286 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
3287 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
3288 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3289 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
3290 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
3291 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
3292 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
3293 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3294 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3295 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3296 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3297 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3298 CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
3299 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3300 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3301 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3302 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3303 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3304 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3305 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3306 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3307 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3308 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3309 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3310 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3311 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3312 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3313 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3314 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3315 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3316 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3317 CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3318 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3319 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3320 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3321 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3322 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3323 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3324 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
3325 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
3326 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3327 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3328 CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
3329 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3330 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3331 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3332 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3333 CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
3334 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
3335 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
3336 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
3337 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3338 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3339 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3340 CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
3341 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
3342 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
3343 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3344 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3345 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3346 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3347 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3348 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3349 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
3350 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
3351 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3352 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3353 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3354 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3355 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3356 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3357 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3358 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3359 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3360 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3361 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3362 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3363 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3364 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3365 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
3366 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
3367 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
3368 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3369 CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
3370 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3371 CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3372 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3373 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3374 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3375 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3376 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3377 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3378 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3379 CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
3380 CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
3381 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
3382 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
3383 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
3384 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3385 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3386 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3387 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3388 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3389 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
3390 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3391 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3392 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3393 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3394 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3395 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3396 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3397 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3398 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
3399 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3400 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3401 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3402 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3403 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3404 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3405 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3406 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3407 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3408 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
3409 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3410 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3411 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3412 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3413 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3414 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3415 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3416 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3417 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3418 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3419 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3420 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3421 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3422 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3423 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3424 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3425 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3426 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3427 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3428 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3429 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3430 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3431 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3432 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3433 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3434 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3435 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3436 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3437 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3438 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3439 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3440 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3441 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3442 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3443 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3444 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
3445 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
3446 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
3447 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3448 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3449 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3450 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
3451 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3452 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3453 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3454 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3455 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3456 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3457 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3458 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3459 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3460 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3461 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3462 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3463 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3464 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3465 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3466 CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
3467 CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
3468 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3469 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3470 CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX),
3471 CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX),
3472 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3473 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3474 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3475 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3476 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3477 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3478 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3479 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3480 CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
3481};
3482
3483
3484int __init omap3xxx_clk_init(void)
3485{
3486 struct omap_clk *c;
3487 u32 cpu_clkflg = 0;
3488
3489 if (soc_is_am35xx()) {
3490 cpu_mask = RATE_IN_34XX;
3491 cpu_clkflg = CK_AM35XX;
3492 } else if (cpu_is_omap3630()) {
3493 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3494 cpu_clkflg = CK_36XX;
3495 } else if (cpu_is_ti816x()) {
3496 cpu_mask = RATE_IN_TI816X;
3497 cpu_clkflg = CK_TI816X;
3498 } else if (soc_is_am33xx()) {
3499 cpu_mask = RATE_IN_AM33XX;
3500 } else if (cpu_is_ti814x()) {
3501 cpu_mask = RATE_IN_TI814X;
3502 } else if (cpu_is_omap34xx()) {
3503 if (omap_rev() == OMAP3430_REV_ES1_0) {
3504 cpu_mask = RATE_IN_3430ES1;
3505 cpu_clkflg = CK_3430ES1;
3506 } else {
3507 /*
3508 * Assume that anything that we haven't matched yet
3509 * has 3430ES2-type clocks.
3510 */
3511 cpu_mask = RATE_IN_3430ES2PLUS;
3512 cpu_clkflg = CK_3430ES2PLUS;
3513 }
3514 } else {
3515 WARN(1, "clock: could not identify OMAP3 variant\n");
3516 }
3517
3518 if (omap3_has_192mhz_clk())
3519 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3520
3521 if (cpu_is_omap3630()) {
3522 /*
3523 * XXX This type of dynamic rewriting of the clock tree is
3524 * deprecated and should be revised soon.
3525 *
3526 * For 3630: override clkops_omap2_dflt_wait for the
3527 * clocks affected from PWRDN reset Limitation
3528 */
3529 dpll3_m3x2_ck.ops =
3530 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3531 dpll4_m2x2_ck.ops =
3532 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3533 dpll4_m3x2_ck.ops =
3534 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3535 dpll4_m4x2_ck.ops =
3536 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3537 dpll4_m5x2_ck.ops =
3538 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3539 dpll4_m6x2_ck.ops =
3540 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3541 }
3542
3543 /*
3544 * XXX This type of dynamic rewriting of the clock tree is
3545 * deprecated and should be revised soon.
3546 */
3547 if (cpu_is_omap3630())
3548 dpll4_dd = dpll4_dd_3630;
3549 else
3550 dpll4_dd = dpll4_dd_34xx;
3551
3552 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3553 c++)
3554 clk_preinit(c->lk.clk);
3555
3556 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3557 c++)
3558 if (c->cpu & cpu_clkflg) {
3559 clkdev_add(&c->lk);
3560 clk_register(c->lk.clk);
3561 omap2_init_clk_clkdm(c->lk.clk);
3562 }
3563
3564 /* Disable autoidle on all clocks; let the PM code enable it later */
3565 omap_clk_disable_autoidle_all();
3566
3567 recalculate_root_clocks();
3568
3569 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3570 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3571 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3572
3573 /*
3574 * Only enable those clocks we will need, let the drivers
3575 * enable other clocks as necessary
3576 */
3577 clk_enable_init_clocks();
3578
3579 /*
3580 * Lock DPLL5 -- here only until other device init code can
3581 * handle this
3582 */
3583 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3584 omap3_clk_lock_dpll5();
3585
3586 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3587 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3588 arm_fck_p = clk_get(NULL, "arm_fck");
3589
3590 return 0;
3591}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 02:12:58 -0400