Patched in Tegra support.

1 files changed, 166 insertions, 675 deletions

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 9392f527f10..57dcbd4308f 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -34,12 +34,10 @@
 #include <asm/current.h>
 #include <asm/apicdef.h>
 #include <linux/atomic.h>
-#include <linux/jump_label.h>
 #include "kvm_cache_regs.h"
 #include "irq.h"
 #include "trace.h"
 #include "x86.h"
-#include "cpuid.h"
 
 #ifndef CONFIG_X86_64
 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
@@ -66,13 +64,14 @@
 #define APIC_DEST_NOSHORT               0x0
 #define APIC_DEST_MASK                  0x800
 #define MAX_APIC_VECTOR                 256
-#define APIC_VECTORS_PER_REG            32
 
 #define VEC_POS(v) ((v) & (32 - 1))
 #define REG_POS(v) (((v) >> 5) << 4)
 
-static unsigned int min_timer_period_us = 500;
-module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
+static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
+{
+        return *((u32 *) (apic->regs + reg_off));
+}
 
 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
 {
@@ -89,11 +88,6 @@ static inline int apic_test_and_clear_vector(int vec, void *bitmap)
         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 }
 
-static inline int apic_test_vector(int vec, void *bitmap)
-{
-        return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
-}
-
 static inline void apic_set_vector(int vec, void *bitmap)
 {
         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
@@ -104,33 +98,19 @@ static inline void apic_clear_vector(int vec, void *bitmap)
         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 }
 
-static inline int __apic_test_and_set_vector(int vec, void *bitmap)
+static inline int apic_hw_enabled(struct kvm_lapic *apic)
 {
-        return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
+        return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 }
 
-static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
+static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 {
-        return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
-}
-
-struct static_key_deferred apic_hw_disabled __read_mostly;
-struct static_key_deferred apic_sw_disabled __read_mostly;
-
-static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
-{
-        if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
-                if (val & APIC_SPIV_APIC_ENABLED)
-                        static_key_slow_dec_deferred(&apic_sw_disabled);
-                else
-                        static_key_slow_inc(&apic_sw_disabled.key);
-        }
-        apic_set_reg(apic, APIC_SPIV, val);
+        return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 }
 
 static inline int apic_enabled(struct kvm_lapic *apic)
 {
-        return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
+        return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 }
 
 #define LVT_MASK        \
@@ -140,137 +120,24 @@ static inline int apic_enabled(struct kvm_lapic *apic)
         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 
-static inline int apic_x2apic_mode(struct kvm_lapic *apic)
-{
-        return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
-}
-
 static inline int kvm_apic_id(struct kvm_lapic *apic)
 {
-        return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
-}
-
-static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr)
-{
-        u16 cid;
-        ldr >>= 32 - map->ldr_bits;
-        cid = (ldr >> map->cid_shift) & map->cid_mask;
-
-        BUG_ON(cid >= ARRAY_SIZE(map->logical_map));
-
-        return cid;
-}
-
-static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr)
-{
-        ldr >>= (32 - map->ldr_bits);
-        return ldr & map->lid_mask;
-}
-
-static void recalculate_apic_map(struct kvm *kvm)
-{
-        struct kvm_apic_map *new, *old = NULL;
-        struct kvm_vcpu *vcpu;
-        int i;
-
-        new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
-
-        mutex_lock(&kvm->arch.apic_map_lock);
-
-        if (!new)
-                goto out;
-
-        new->ldr_bits = 8;
-        /* flat mode is default */
-        new->cid_shift = 8;
-        new->cid_mask = 0;
-        new->lid_mask = 0xff;
-
-        kvm_for_each_vcpu(i, vcpu, kvm) {
-                struct kvm_lapic *apic = vcpu->arch.apic;
-                u16 cid, lid;
-                u32 ldr;
-
-                if (!kvm_apic_present(vcpu))
-                        continue;
-
-                /*
-                 * All APICs have to be configured in the same mode by an OS.
-                 * We take advatage of this while building logical id loockup
-                 * table. After reset APICs are in xapic/flat mode, so if we
-                 * find apic with different setting we assume this is the mode
-                 * OS wants all apics to be in; build lookup table accordingly.
-                 */
-                if (apic_x2apic_mode(apic)) {
-                        new->ldr_bits = 32;
-                        new->cid_shift = 16;
-                        new->cid_mask = new->lid_mask = 0xffff;
-                } else if (kvm_apic_sw_enabled(apic) &&
-                                !new->cid_mask /* flat mode */ &&
-                                kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
-                        new->cid_shift = 4;
-                        new->cid_mask = 0xf;
-                        new->lid_mask = 0xf;
-                }
-
-                new->phys_map[kvm_apic_id(apic)] = apic;
-
-                ldr = kvm_apic_get_reg(apic, APIC_LDR);
-                cid = apic_cluster_id(new, ldr);
-                lid = apic_logical_id(new, ldr);
-
-                if (lid)
-                        new->logical_map[cid][ffs(lid) - 1] = apic;
-        }
-out:
-        old = rcu_dereference_protected(kvm->arch.apic_map,
-                        lockdep_is_held(&kvm->arch.apic_map_lock));
-        rcu_assign_pointer(kvm->arch.apic_map, new);
-        mutex_unlock(&kvm->arch.apic_map_lock);
-
-        if (old)
-                kfree_rcu(old, rcu);
-}
-
-static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
-{
-        apic_set_reg(apic, APIC_ID, id << 24);
-        recalculate_apic_map(apic->vcpu->kvm);
-}
-
-static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
-{
-        apic_set_reg(apic, APIC_LDR, id);
-        recalculate_apic_map(apic->vcpu->kvm);
+        return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 }
 
 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 {
-        return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
+        return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 }
 
 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 {
-        return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
-}
-
-static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
-{
-        return ((kvm_apic_get_reg(apic, APIC_LVTT) &
-                apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
+        return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 }
 
 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 {
-        return ((kvm_apic_get_reg(apic, APIC_LVTT) &
-                apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
-}
-
-static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
-{
-        return ((kvm_apic_get_reg(apic, APIC_LVTT) &
-                apic->lapic_timer.timer_mode_mask) ==
-                        APIC_LVT_TIMER_TSCDEADLINE);
+        return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 }
 
 static inline int apic_lvt_nmi_mode(u32 lvt_val)
@@ -284,7 +151,7 @@ void kvm_apic_set_version(struct kvm_vcpu *vcpu)
         struct kvm_cpuid_entry2 *feat;
         u32 v = APIC_VERSION;
 
-        if (!kvm_vcpu_has_lapic(vcpu))
+        if (!irqchip_in_kernel(vcpu->kvm))
                 return;
 
         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
@@ -293,8 +160,13 @@ void kvm_apic_set_version(struct kvm_vcpu *vcpu)
         apic_set_reg(apic, APIC_LVR, v);
 }
 
-static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
-        LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
+static inline int apic_x2apic_mode(struct kvm_lapic *apic)
+{
+        return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
+}
+
+static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
+        LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
         LINT_MASK, LINT_MASK,   /* LVT0-1 */
@@ -303,31 +175,16 @@ static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 
 static int find_highest_vector(void *bitmap)
 {
-        int vec;
-        u32 *reg;
-
-        for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
-             vec >= 0; vec -= APIC_VECTORS_PER_REG) {
-                reg = bitmap + REG_POS(vec);
-                if (*reg)
-                        return fls(*reg) - 1 + vec;
-        }
-
-        return -1;
-}
+        u32 *word = bitmap;
+        int word_offset = MAX_APIC_VECTOR >> 5;
 
-static u8 count_vectors(void *bitmap)
-{
-        int vec;
-        u32 *reg;
-        u8 count = 0;
+        while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
+                continue;
 
-        for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
-                reg = bitmap + REG_POS(vec);
-                count += hweight32(*reg);
-        }
-
-        return count;
+        if (likely(!word_offset && !word[0]))
+                return -1;
+        else
+                return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 }
 
 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
@@ -362,29 +219,9 @@ static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
                 apic->irr_pending = true;
 }
 
-static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
-{
-        if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
-                ++apic->isr_count;
-        BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
-        /*
-         * ISR (in service register) bit is set when injecting an interrupt.
-         * The highest vector is injected. Thus the latest bit set matches
-         * the highest bit in ISR.
-         */
-        apic->highest_isr_cache = vec;
-}
-
-static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
-{
-        if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
-                --apic->isr_count;
-        BUG_ON(apic->isr_count < 0);
-        apic->highest_isr_cache = -1;
-}
-
 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 {
+        struct kvm_lapic *apic = vcpu->arch.apic;
         int highest_irr;
 
         /* This may race with setting of irr in __apic_accept_irq() and
@@ -392,9 +229,9 @@ int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
          * will cause vmexit immediately and the value will be recalculated
          * on the next vmentry.
          */
-        if (!kvm_vcpu_has_lapic(vcpu))
+        if (!apic)
                 return 0;
-        highest_irr = apic_find_highest_irr(vcpu->arch.apic);
+        highest_irr = apic_find_highest_irr(apic);
 
         return highest_irr;
 }
@@ -410,61 +247,9 @@ int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
                         irq->level, irq->trig_mode);
 }
 
-static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
-{
-
-        return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
-                                      sizeof(val));
-}
-
-static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
-{
-
-        return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
-                                      sizeof(*val));
-}
-
-static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
-{
-        return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
-}
-
-static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
-{
-        u8 val;
-        if (pv_eoi_get_user(vcpu, &val) < 0)
-                apic_debug("Can't read EOI MSR value: 0x%llx\n",
-                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
-        return val & 0x1;
-}
-
-static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
-{
-        if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
-                apic_debug("Can't set EOI MSR value: 0x%llx\n",
-                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
-                return;
-        }
-        __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
-}
-
-static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
-{
-        if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
-                apic_debug("Can't clear EOI MSR value: 0x%llx\n",
-                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
-                return;
-        }
-        __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
-}
-
 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 {
         int result;
-        if (!apic->isr_count)
-                return -1;
-        if (likely(apic->highest_isr_cache != -1))
-                return apic->highest_isr_cache;
 
         result = find_highest_vector(apic->regs + APIC_ISR);
         ASSERT(result == -1 || result >= 16);
@@ -477,8 +262,8 @@ static void apic_update_ppr(struct kvm_lapic *apic)
         u32 tpr, isrv, ppr, old_ppr;
         int isr;
 
-        old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
-        tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
+        old_ppr = apic_get_reg(apic, APIC_PROCPRI);
+        tpr = apic_get_reg(apic, APIC_TASKPRI);
         isr = apic_find_highest_isr(apic);
         isrv = (isr != -1) ? isr : 0;
 
@@ -514,13 +299,13 @@ int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
         u32 logical_id;
 
         if (apic_x2apic_mode(apic)) {
-                logical_id = kvm_apic_get_reg(apic, APIC_LDR);
+                logical_id = apic_get_reg(apic, APIC_LDR);
                 return logical_id & mda;
         }
 
-        logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
+        logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 
-        switch (kvm_apic_get_reg(apic, APIC_DFR)) {
+        switch (apic_get_reg(apic, APIC_DFR)) {
         case APIC_DFR_FLAT:
                 if (logical_id & mda)
                         result = 1;
@@ -531,8 +316,8 @@ int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
                         result = 1;
                 break;
         default:
-                apic_debug("Bad DFR vcpu %d: %08x\n",
-                           apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
+                printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
+                       apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
                 break;
         }
 
@@ -569,80 +354,14 @@ int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
                 result = (target != source);
                 break;
         default:
-                apic_debug("kvm: apic: Bad dest shorthand value %x\n",
-                           short_hand);
+                printk(KERN_WARNING "Bad dest shorthand value %x\n",
+                       short_hand);
                 break;
         }
 
         return result;
 }
 
-bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
-                struct kvm_lapic_irq *irq, int *r)
-{
-        struct kvm_apic_map *map;
-        unsigned long bitmap = 1;
-        struct kvm_lapic **dst;
-        int i;
-        bool ret = false;
-
-        *r = -1;
-
-        if (irq->shorthand == APIC_DEST_SELF) {
-                *r = kvm_apic_set_irq(src->vcpu, irq);
-                return true;
-        }
-
-        if (irq->shorthand)
-                return false;
-
-        rcu_read_lock();
-        map = rcu_dereference(kvm->arch.apic_map);
-
-        if (!map)
-                goto out;
-
-        if (irq->dest_mode == 0) { /* physical mode */
-                if (irq->delivery_mode == APIC_DM_LOWEST ||
-                                irq->dest_id == 0xff)
-                        goto out;
-                dst = &map->phys_map[irq->dest_id & 0xff];
-        } else {
-                u32 mda = irq->dest_id << (32 - map->ldr_bits);
-
-                dst = map->logical_map[apic_cluster_id(map, mda)];
-
-                bitmap = apic_logical_id(map, mda);
-
-                if (irq->delivery_mode == APIC_DM_LOWEST) {
-                        int l = -1;
-                        for_each_set_bit(i, &bitmap, 16) {
-                                if (!dst[i])
-                                        continue;
-                                if (l < 0)
-                                        l = i;
-                                else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
-                                        l = i;
-                        }
-
-                        bitmap = (l >= 0) ? 1 << l : 0;
-                }
-        }
-
-        for_each_set_bit(i, &bitmap, 16) {
-                if (!dst[i])
-                        continue;
-                if (*r < 0)
-                        *r = 0;
-                *r += kvm_apic_set_irq(dst[i]->vcpu, irq);
-        }
-
-        ret = true;
-out:
-        rcu_read_unlock();
-        return ret;
-}
-
 /*
  * Add a pending IRQ into lapic.
  * Return 1 if successfully added and 0 if discarded.
@@ -682,11 +401,11 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                 break;
 
         case APIC_DM_REMRD:
-                apic_debug("Ignoring delivery mode 3\n");
+                printk(KERN_DEBUG "Ignoring delivery mode 3\n");
                 break;
 
         case APIC_DM_SMI:
-                apic_debug("Ignoring guest SMI\n");
+                printk(KERN_DEBUG "Ignoring guest SMI\n");
                 break;
 
         case APIC_DM_NMI:
@@ -696,7 +415,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                 break;
 
         case APIC_DM_INIT:
-                if (!trig_mode || level) {
+                if (level) {
                         result = 1;
                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
                         kvm_make_request(KVM_REQ_EVENT, vcpu);
@@ -740,39 +459,33 @@ int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 }
 
-static int apic_set_eoi(struct kvm_lapic *apic)
+static void apic_set_eoi(struct kvm_lapic *apic)
 {
         int vector = apic_find_highest_isr(apic);
-
-        trace_kvm_eoi(apic, vector);
-
+        int trigger_mode;
         /*
          * Not every write EOI will has corresponding ISR,
          * one example is when Kernel check timer on setup_IO_APIC
          */
         if (vector == -1)
-                return vector;
+                return;
 
-        apic_clear_isr(vector, apic);
+        apic_clear_vector(vector, apic->regs + APIC_ISR);
         apic_update_ppr(apic);
 
-        if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
-            kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
-                int trigger_mode;
-                if (apic_test_vector(vector, apic->regs + APIC_TMR))
-                        trigger_mode = IOAPIC_LEVEL_TRIG;
-                else
-                        trigger_mode = IOAPIC_EDGE_TRIG;
+        if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
+                trigger_mode = IOAPIC_LEVEL_TRIG;
+        else
+                trigger_mode = IOAPIC_EDGE_TRIG;
+        if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
-        }
         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
-        return vector;
 }
 
 static void apic_send_ipi(struct kvm_lapic *apic)
 {
-        u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
-        u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
+        u32 icr_low = apic_get_reg(apic, APIC_ICR);
+        u32 icr_high = apic_get_reg(apic, APIC_ICR2);
         struct kvm_lapic_irq irq;
 
         irq.vector = icr_low & APIC_VECTOR_MASK;
@@ -807,7 +520,7 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
         ASSERT(apic != NULL);
 
         /* if initial count is 0, current count should also be 0 */
-        if (kvm_apic_get_reg(apic, APIC_TMICT) == 0)
+        if (apic_get_reg(apic, APIC_TMICT) == 0)
                 return 0;
 
         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
@@ -852,24 +565,20 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
                         val = kvm_apic_id(apic) << 24;
                 break;
         case APIC_ARBPRI:
-                apic_debug("Access APIC ARBPRI register which is for P6\n");
+                printk(KERN_WARNING "Access APIC ARBPRI register "
+                       "which is for P6\n");
                 break;
 
         case APIC_TMCCT:        /* Timer CCR */
-                if (apic_lvtt_tscdeadline(apic))
-                        return 0;
-
                 val = apic_get_tmcct(apic);
                 break;
-        case APIC_PROCPRI:
-                apic_update_ppr(apic);
-                val = kvm_apic_get_reg(apic, offset);
-                break;
+
         case APIC_TASKPRI:
                 report_tpr_access(apic, false);
                 /* fall thru */
         default:
-                val = kvm_apic_get_reg(apic, offset);
+                apic_update_ppr(apic);
+                val = apic_get_reg(apic, offset);
                 break;
         }
 
@@ -886,7 +595,7 @@ static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 {
         unsigned char alignment = offset & 0xf;
         u32 result;
-        /* this bitmask has a bit cleared for each reserved register */
+        /* this bitmask has a bit cleared for each reserver register */
         static const u64 rmask = 0x43ff01ffffffe70cULL;
 
         if ((alignment + len) > 4) {
@@ -921,7 +630,7 @@ static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 
 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 {
-        return kvm_apic_hw_enabled(apic) &&
+        return apic_hw_enabled(apic) &&
             addr >= apic->base_address &&
             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 }
@@ -944,7 +653,7 @@ static void update_divide_count(struct kvm_lapic *apic)
 {
         u32 tmp1, tmp2, tdcr;
 
-        tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
+        tdcr = apic_get_reg(apic, APIC_TDCR);
         tmp1 = tdcr & 0xf;
         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
         apic->divide_count = 0x1 << (tmp2 & 0x7);
@@ -955,77 +664,42 @@ static void update_divide_count(struct kvm_lapic *apic)
 
 static void start_apic_timer(struct kvm_lapic *apic)
 {
-        ktime_t now;
-        atomic_set(&apic->lapic_timer.pending, 0);
+        ktime_t now = apic->lapic_timer.timer.base->get_time();
 
-        if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
-                /* lapic timer in oneshot or periodic mode */
-                now = apic->lapic_timer.timer.base->get_time();
-                apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
-                            * APIC_BUS_CYCLE_NS * apic->divide_count;
+        apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
+                    APIC_BUS_CYCLE_NS * apic->divide_count;
+        atomic_set(&apic->lapic_timer.pending, 0);
 
-                if (!apic->lapic_timer.period)
-                        return;
-                /*
-                 * Do not allow the guest to program periodic timers with small
-                 * interval, since the hrtimers are not throttled by the host
-                 * scheduler.
-                 */
-                if (apic_lvtt_period(apic)) {
-                        s64 min_period = min_timer_period_us * 1000LL;
-
-                        if (apic->lapic_timer.period < min_period) {
-                                pr_info_ratelimited(
-                                    "kvm: vcpu %i: requested %lld ns "
-                                    "lapic timer period limited to %lld ns\n",
-                                    apic->vcpu->vcpu_id,
-                                    apic->lapic_timer.period, min_period);
-                                apic->lapic_timer.period = min_period;
-                        }
-                }
+        if (!apic->lapic_timer.period)
+                return;
+        /*
+         * Do not allow the guest to program periodic timers with small
+         * interval, since the hrtimers are not throttled by the host
+         * scheduler.
+         */
+        if (apic_lvtt_period(apic)) {
+                if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
+                        apic->lapic_timer.period = NSEC_PER_MSEC/2;
+        }
 
-                hrtimer_start(&apic->lapic_timer.timer,
-                              ktime_add_ns(now, apic->lapic_timer.period),
-                              HRTIMER_MODE_ABS);
+        hrtimer_start(&apic->lapic_timer.timer,
+                      ktime_add_ns(now, apic->lapic_timer.period),
+                      HRTIMER_MODE_ABS);
 
-                apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
+        apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
                            PRIx64 ", "
                            "timer initial count 0x%x, period %lldns, "
                            "expire @ 0x%016" PRIx64 ".\n", __func__,
                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
-                           kvm_apic_get_reg(apic, APIC_TMICT),
+                           apic_get_reg(apic, APIC_TMICT),
                            apic->lapic_timer.period,
                            ktime_to_ns(ktime_add_ns(now,
                                         apic->lapic_timer.period)));
-        } else if (apic_lvtt_tscdeadline(apic)) {
-                /* lapic timer in tsc deadline mode */
-                u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
-                u64 ns = 0;
-                struct kvm_vcpu *vcpu = apic->vcpu;
-                unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
-                unsigned long flags;
-
-                if (unlikely(!tscdeadline || !this_tsc_khz))
-                        return;
-
-                local_irq_save(flags);
-
-                now = apic->lapic_timer.timer.base->get_time();
-                guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
-                if (likely(tscdeadline > guest_tsc)) {
-                        ns = (tscdeadline - guest_tsc) * 1000000ULL;
-                        do_div(ns, this_tsc_khz);
-                }
-                hrtimer_start(&apic->lapic_timer.timer,
-                        ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
-
-                local_irq_restore(flags);
-        }
 }
 
 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 {
-        int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
+        int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 
         if (apic_lvt_nmi_mode(lvt0_val)) {
                 if (!nmi_wd_enabled) {
@@ -1046,7 +720,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
         switch (reg) {
         case APIC_ID:           /* Local APIC ID */
                 if (!apic_x2apic_mode(apic))
-                        kvm_apic_set_id(apic, val >> 24);
+                        apic_set_reg(apic, APIC_ID, val);
                 else
                         ret = 1;
                 break;
@@ -1062,30 +736,29 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 
         case APIC_LDR:
                 if (!apic_x2apic_mode(apic))
-                        kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
+                        apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
                 else
                         ret = 1;
                 break;
 
         case APIC_DFR:
-                if (!apic_x2apic_mode(apic)) {
+                if (!apic_x2apic_mode(apic))
                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
-                        recalculate_apic_map(apic->vcpu->kvm);
-                } else
+                else
                         ret = 1;
                 break;
 
         case APIC_SPIV: {
                 u32 mask = 0x3ff;
-                if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
+                if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
                         mask |= APIC_SPIV_DIRECTED_EOI;
-                apic_set_spiv(apic, val & mask);
+                apic_set_reg(apic, APIC_SPIV, val & mask);
                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
                         int i;
                         u32 lvt_val;
 
                         for (i = 0; i < APIC_LVT_NUM; i++) {
-                                lvt_val = kvm_apic_get_reg(apic,
+                                lvt_val = apic_get_reg(apic,
                                                        APIC_LVTT + 0x10 * i);
                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
                                              lvt_val | APIC_LVT_MASKED);
@@ -1109,12 +782,13 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 
         case APIC_LVT0:
                 apic_manage_nmi_watchdog(apic, val);
+        case APIC_LVTT:
         case APIC_LVTTHMR:
         case APIC_LVTPC:
         case APIC_LVT1:
         case APIC_LVTERR:
                 /* TODO: Check vector */
-                if (!kvm_apic_sw_enabled(apic))
+                if (!apic_sw_enabled(apic))
                         val |= APIC_LVT_MASKED;
 
                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
@@ -1122,22 +796,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 
                 break;
 
-        case APIC_LVTT:
-                if ((kvm_apic_get_reg(apic, APIC_LVTT) &
-                    apic->lapic_timer.timer_mode_mask) !=
-                   (val & apic->lapic_timer.timer_mode_mask))
-                        hrtimer_cancel(&apic->lapic_timer.timer);
-
-                if (!kvm_apic_sw_enabled(apic))
-                        val |= APIC_LVT_MASKED;
-                val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
-                apic_set_reg(apic, APIC_LVTT, val);
-                break;
-
         case APIC_TMICT:
-                if (apic_lvtt_tscdeadline(apic))
-                        break;
-
                 hrtimer_cancel(&apic->lapic_timer.timer);
                 apic_set_reg(apic, APIC_TMICT, val);
                 start_apic_timer(apic);
@@ -1145,14 +804,14 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 
         case APIC_TDCR:
                 if (val & 4)
-                        apic_debug("KVM_WRITE:TDCR %x\n", val);
+                        printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
                 apic_set_reg(apic, APIC_TDCR, val);
                 update_divide_count(apic);
                 break;
 
         case APIC_ESR:
                 if (apic_x2apic_mode(apic) && val != 0) {
-                        apic_debug("KVM_WRITE:ESR not zero %x\n", val);
+                        printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
                         ret = 1;
                 }
                 break;
@@ -1205,32 +864,17 @@ static int apic_mmio_write(struct kvm_io_device *this,
         return 0;
 }
 
-void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
-{
-        if (kvm_vcpu_has_lapic(vcpu))
-                apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
-}
-EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
-
 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 {
-        struct kvm_lapic *apic = vcpu->arch.apic;
-
         if (!vcpu->arch.apic)
                 return;
 
-        hrtimer_cancel(&apic->lapic_timer.timer);
-
-        if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
-                static_key_slow_dec_deferred(&apic_hw_disabled);
-
-        if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
-                static_key_slow_dec_deferred(&apic_sw_disabled);
+        hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 
-        if (apic->regs)
-                free_page((unsigned long)apic->regs);
+        if (vcpu->arch.apic->regs)
+                free_page((unsigned long)vcpu->arch.apic->regs);
 
-        kfree(apic);
+        kfree(vcpu->arch.apic);
 }
 
 /*
@@ -1239,49 +883,24 @@ void kvm_free_lapic(struct kvm_vcpu *vcpu)
  *----------------------------------------------------------------------
  */
 
-u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
-{
-        struct kvm_lapic *apic = vcpu->arch.apic;
-
-        if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
-                        apic_lvtt_period(apic))
-                return 0;
-
-        return apic->lapic_timer.tscdeadline;
-}
-
-void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
-{
-        struct kvm_lapic *apic = vcpu->arch.apic;
-
-        if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
-                        apic_lvtt_period(apic))
-                return;
-
-        hrtimer_cancel(&apic->lapic_timer.timer);
-        apic->lapic_timer.tscdeadline = data;
-        start_apic_timer(apic);
-}
-
 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
 
-        if (!kvm_vcpu_has_lapic(vcpu))
+        if (!apic)
                 return;
-
         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
-                     | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
+                     | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 }
 
 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 {
+        struct kvm_lapic *apic = vcpu->arch.apic;
         u64 tpr;
 
-        if (!kvm_vcpu_has_lapic(vcpu))
+        if (!apic)
                 return 0;
-
-        tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
+        tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 
         return (tpr & 0xf0) >> 4;
 }
@@ -1296,23 +915,14 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
                 return;
         }
 
-        /* update jump label if enable bit changes */
-        if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) {
-                if (value & MSR_IA32_APICBASE_ENABLE)
-                        static_key_slow_dec_deferred(&apic_hw_disabled);
-                else
-                        static_key_slow_inc(&apic_hw_disabled.key);
-                recalculate_apic_map(vcpu->kvm);
-        }
-
         if (!kvm_vcpu_is_bsp(apic->vcpu))
                 value &= ~MSR_IA32_APICBASE_BSP;
 
         vcpu->arch.apic_base = value;
         if (apic_x2apic_mode(apic)) {
                 u32 id = kvm_apic_id(apic);
-                u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
-                kvm_apic_set_ldr(apic, ldr);
+                u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
+                apic_set_reg(apic, APIC_LDR, ldr);
         }
         apic->base_address = apic->vcpu->arch.apic_base &
                              MSR_IA32_APICBASE_BASE;
@@ -1337,7 +947,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
         /* Stop the timer in case it's a reset to an active apic */
         hrtimer_cancel(&apic->lapic_timer.timer);
 
-        kvm_apic_set_id(apic, vcpu->vcpu_id);
+        apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
         kvm_apic_set_version(apic->vcpu);
 
         for (i = 0; i < APIC_LVT_NUM; i++)
@@ -1346,9 +956,9 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 
         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
-        apic_set_spiv(apic, 0xff);
+        apic_set_reg(apic, APIC_SPIV, 0xff);
         apic_set_reg(apic, APIC_TASKPRI, 0);
-        kvm_apic_set_ldr(apic, 0);
+        apic_set_reg(apic, APIC_LDR, 0);
         apic_set_reg(apic, APIC_ESR, 0);
         apic_set_reg(apic, APIC_ICR, 0);
         apic_set_reg(apic, APIC_ICR2, 0);
@@ -1360,18 +970,13 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
         }
         apic->irr_pending = false;
-        apic->isr_count = 0;
-        apic->highest_isr_cache = -1;
         update_divide_count(apic);
         atomic_set(&apic->lapic_timer.pending, 0);
         if (kvm_vcpu_is_bsp(vcpu))
-                kvm_lapic_set_base(vcpu,
-                                vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
-        vcpu->arch.pv_eoi.msr_val = 0;
+                vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
         apic_update_ppr(apic);
 
         vcpu->arch.apic_arb_prio = 0;
-        vcpu->arch.apic_attention = 0;
 
         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
@@ -1379,34 +984,45 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
                    vcpu->arch.apic_base, apic->base_address);
 }
 
+bool kvm_apic_present(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
+}
+
+int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
+{
+        return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
+}
+
 /*
  *----------------------------------------------------------------------
  * timer interface
  *----------------------------------------------------------------------
  */
 
-static bool lapic_is_periodic(struct kvm_lapic *apic)
+static bool lapic_is_periodic(struct kvm_timer *ktimer)
 {
+        struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
+                                              lapic_timer);
         return apic_lvtt_period(apic);
 }
 
 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 {
-        struct kvm_lapic *apic = vcpu->arch.apic;
+        struct kvm_lapic *lapic = vcpu->arch.apic;
 
-        if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
-                        apic_lvt_enabled(apic, APIC_LVTT))
-                return atomic_read(&apic->lapic_timer.pending);
+        if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
+                return atomic_read(&lapic->lapic_timer.pending);
 
         return 0;
 }
 
-int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
+static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
 {
-        u32 reg = kvm_apic_get_reg(apic, lvt_type);
+        u32 reg = apic_get_reg(apic, lvt_type);
         int vector, mode, trig_mode;
 
-        if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
+        if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
                 vector = reg & APIC_VECTOR_MASK;
                 mode = reg & APIC_MODE_MASK;
                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
@@ -1423,40 +1039,15 @@ void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
                 kvm_apic_local_deliver(apic, APIC_LVT0);
 }
 
+static struct kvm_timer_ops lapic_timer_ops = {
+        .is_periodic = lapic_is_periodic,
+};
+
 static const struct kvm_io_device_ops apic_mmio_ops = {
         .read     = apic_mmio_read,
         .write    = apic_mmio_write,
 };
 
-static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
-{
-        struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
-        struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
-        struct kvm_vcpu *vcpu = apic->vcpu;
-        wait_queue_head_t *q = &vcpu->wq;
-
-        /*
-         * There is a race window between reading and incrementing, but we do
-         * not care about potentially losing timer events in the !reinject
-         * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
-         * in vcpu_enter_guest.
-         */
-        if (!atomic_read(&ktimer->pending)) {
-                atomic_inc(&ktimer->pending);
-                /* FIXME: this code should not know anything about vcpus */
-                kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
-        }
-
-        if (waitqueue_active(q))
-                wake_up_interruptible(q);
-
-        if (lapic_is_periodic(apic)) {
-                hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
-                return HRTIMER_RESTART;
-        } else
-                return HRTIMER_NORESTART;
-}
-
 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic;
@@ -1480,17 +1071,14 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu)
 
         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
                      HRTIMER_MODE_ABS);
-        apic->lapic_timer.timer.function = apic_timer_fn;
+        apic->lapic_timer.timer.function = kvm_timer_fn;
+        apic->lapic_timer.t_ops = &lapic_timer_ops;
+        apic->lapic_timer.kvm = vcpu->kvm;
+        apic->lapic_timer.vcpu = vcpu;
 
-        /*
-         * APIC is created enabled. This will prevent kvm_lapic_set_base from
-         * thinking that APIC satet has changed.
-         */
-        vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
-        kvm_lapic_set_base(vcpu,
-                        APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
+        apic->base_address = APIC_DEFAULT_PHYS_BASE;
+        vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
 
-        static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
         kvm_lapic_reset(vcpu);
         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
 
@@ -1506,23 +1094,23 @@ int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
         struct kvm_lapic *apic = vcpu->arch.apic;
         int highest_irr;
 
-        if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
+        if (!apic || !apic_enabled(apic))
                 return -1;
 
         apic_update_ppr(apic);
         highest_irr = apic_find_highest_irr(apic);
         if ((highest_irr == -1) ||
-            ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
+            ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
                 return -1;
         return highest_irr;
 }
 
 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
 {
-        u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
+        u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
         int r = 0;
 
-        if (!kvm_apic_hw_enabled(vcpu->arch.apic))
+        if (!apic_hw_enabled(vcpu->arch.apic))
                 r = 1;
         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
@@ -1534,10 +1122,7 @@ void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
 
-        if (!kvm_vcpu_has_lapic(vcpu))
-                return;
-
-        if (atomic_read(&apic->lapic_timer.pending) > 0) {
+        if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
                         atomic_dec(&apic->lapic_timer.pending);
         }
@@ -1551,23 +1136,18 @@ int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
         if (vector == -1)
                 return -1;
 
-        apic_set_isr(vector, apic);
+        apic_set_vector(vector, apic->regs + APIC_ISR);
         apic_update_ppr(apic);
         apic_clear_irr(vector, apic);
         return vector;
 }
 
-void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
-                struct kvm_lapic_state *s)
+void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
 
-        kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
-        /* set SPIV separately to get count of SW disabled APICs right */
-        apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
-        memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
-        /* call kvm_apic_set_id() to put apic into apic_map */
-        kvm_apic_set_id(apic, kvm_apic_id(apic));
+        apic->base_address = vcpu->arch.apic_base &
+                             MSR_IA32_APICBASE_BASE;
         kvm_apic_set_version(vcpu);
 
         apic_update_ppr(apic);
@@ -1575,117 +1155,49 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
         update_divide_count(apic);
         start_apic_timer(apic);
         apic->irr_pending = true;
-        apic->isr_count = count_vectors(apic->regs + APIC_ISR);
-        apic->highest_isr_cache = -1;
         kvm_make_request(KVM_REQ_EVENT, vcpu);
 }
 
 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
 {
+        struct kvm_lapic *apic = vcpu->arch.apic;
         struct hrtimer *timer;
 
-        if (!kvm_vcpu_has_lapic(vcpu))
+        if (!apic)
                 return;
 
-        timer = &vcpu->arch.apic->lapic_timer.timer;
+        timer = &apic->lapic_timer.timer;
         if (hrtimer_cancel(timer))
                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
 }
 
-/*
- * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
- *
- * Detect whether guest triggered PV EOI since the
- * last entry. If yes, set EOI on guests's behalf.
- * Clear PV EOI in guest memory in any case.
- */
-static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
-                                        struct kvm_lapic *apic)
-{
-        bool pending;
-        int vector;
-        /*
-         * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
-         * and KVM_PV_EOI_ENABLED in guest memory as follows:
-         *
-         * KVM_APIC_PV_EOI_PENDING is unset:
-         *      -> host disabled PV EOI.
-         * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
-         *      -> host enabled PV EOI, guest did not execute EOI yet.
-         * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
-         *      -> host enabled PV EOI, guest executed EOI.
-         */
-        BUG_ON(!pv_eoi_enabled(vcpu));
-        pending = pv_eoi_get_pending(vcpu);
-        /*
-         * Clear pending bit in any case: it will be set again on vmentry.
-         * While this might not be ideal from performance point of view,
-         * this makes sure pv eoi is only enabled when we know it's safe.
-         */
-        pv_eoi_clr_pending(vcpu);
-        if (pending)
-                return;
-        vector = apic_set_eoi(apic);
-        trace_kvm_pv_eoi(apic, vector);
-}
-
 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
 {
         u32 data;
         void *vapic;
 
-        if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
-                apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
-
-        if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
+        if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
                 return;
 
-        vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
+        vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
-        kunmap_atomic(vapic);
+        kunmap_atomic(vapic, KM_USER0);
 
         apic_set_tpr(vcpu->arch.apic, data & 0xff);
 }
 
-/*
- * apic_sync_pv_eoi_to_guest - called before vmentry
- *
- * Detect whether it's safe to enable PV EOI and
- * if yes do so.
- */
-static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
-                                        struct kvm_lapic *apic)
-{
-        if (!pv_eoi_enabled(vcpu) ||
-            /* IRR set or many bits in ISR: could be nested. */
-            apic->irr_pending ||
-            /* Cache not set: could be safe but we don't bother. */
-            apic->highest_isr_cache == -1 ||
-            /* Need EOI to update ioapic. */
-            kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
-                /*
-                 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
-                 * so we need not do anything here.
-                 */
-                return;
-        }
-
-        pv_eoi_set_pending(apic->vcpu);
-}
-
 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
 {
         u32 data, tpr;
         int max_irr, max_isr;
-        struct kvm_lapic *apic = vcpu->arch.apic;
+        struct kvm_lapic *apic;
         void *vapic;
 
-        apic_sync_pv_eoi_to_guest(vcpu, apic);
-
-        if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
+        if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
                 return;
 
-        tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
+        apic = vcpu->arch.apic;
+        tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
         max_irr = apic_find_highest_irr(apic);
         if (max_irr < 0)
                 max_irr = 0;
@@ -1694,18 +1206,17 @@ void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
                 max_isr = 0;
         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
 
-        vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
+        vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
-        kunmap_atomic(vapic);
+        kunmap_atomic(vapic, KM_USER0);
 }
 
 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
 {
+        if (!irqchip_in_kernel(vcpu->kvm))
+                return;
+
         vcpu->arch.apic->vapic_addr = vapic_addr;
-        if (vapic_addr)
-                __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
-        else
-                __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
 }
 
 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
@@ -1744,7 +1255,7 @@ int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
 
-        if (!kvm_vcpu_has_lapic(vcpu))
+        if (!irqchip_in_kernel(vcpu->kvm))
                 return 1;
 
         /* if this is ICR write vector before command */
@@ -1758,7 +1269,7 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
         struct kvm_lapic *apic = vcpu->arch.apic;
         u32 low, high = 0;
 
-        if (!kvm_vcpu_has_lapic(vcpu))
+        if (!irqchip_in_kernel(vcpu->kvm))
                 return 1;
 
         if (apic_reg_read(apic, reg, 4, &low))
@@ -1770,23 +1281,3 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
 
         return 0;
 }
-
-int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
-{
-        u64 addr = data & ~KVM_MSR_ENABLED;
-        if (!IS_ALIGNED(addr, 4))
-                return 1;
-
-        vcpu->arch.pv_eoi.msr_val = data;
-        if (!pv_eoi_enabled(vcpu))
-                return 0;
-        return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
-                                         addr);
-}
-
-void kvm_lapic_init(void)
-{
-        /* do not patch jump label more than once per second */
-        jump_label_rate_limit(&apic_hw_disabled, HZ);
-        jump_label_rate_limit(&apic_sw_disabled, HZ);
-}