Patched in Tegra support.

1 files changed, 33 insertions, 63 deletions

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 6ec04daf423..16c4d256b76 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -5,7 +5,6 @@
  *
  * Copyright (C) 2005-2007 Cavium Networks
  */
-#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
@@ -22,14 +21,13 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/r4kcache.h>
-#include <asm/traps.h>
+#include <asm/system.h>
 #include <asm/mmu_context.h>
 #include <asm/war.h>
 
 #include <asm/octeon/octeon.h>
 
 unsigned long long cache_err_dcache[NR_CPUS];
-EXPORT_SYMBOL_GPL(cache_err_dcache);
 
 /**
  * Octeon automatically flushes the dcache on tlb changes, so
@@ -83,9 +81,9 @@ static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
         if (vma)
                 mask = *mm_cpumask(vma->vm_mm);
         else
-                mask = *cpu_online_mask;
-        cpumask_clear_cpu(cpu, &mask);
-        for_each_cpu(cpu, &mask)
+                mask = cpu_online_map;
+        cpu_clear(cpu, mask);
+        for_each_cpu_mask(cpu, mask)
                 octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
 
         preempt_enable();
@@ -171,10 +169,6 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
                 octeon_flush_icache_all_cores(vma);
 }
 
-static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
-{
-        BUG();
-}
 
 /**
  * Probe Octeon's caches
@@ -225,7 +219,7 @@ static void __cpuinit probe_octeon(void)
                 break;
 
         default:
-                panic("Unsupported Cavium Networks CPU type");
+                panic("Unsupported Cavium Networks CPU type\n");
                 break;
         }
 
@@ -251,11 +245,6 @@ static void __cpuinit probe_octeon(void)
         }
 }
 
-static void  __cpuinit octeon_cache_error_setup(void)
-{
-        extern char except_vec2_octeon;
-        set_handler(0x100, &except_vec2_octeon, 0x80);
-}
 
 /**
  * Setup the Octeon cache flush routines
@@ -263,6 +252,12 @@ static void  __cpuinit octeon_cache_error_setup(void)
  */
 void __cpuinit octeon_cache_init(void)
 {
+        extern unsigned long ebase;
+        extern char except_vec2_octeon;
+
+        memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80);
+        octeon_flush_cache_sigtramp(ebase + 0x100);
+
         probe_octeon();
 
         shm_align_mask = PAGE_SIZE - 1;
@@ -278,67 +273,43 @@ void __cpuinit octeon_cache_init(void)
         flush_icache_range              = octeon_flush_icache_range;
         local_flush_icache_range        = local_octeon_flush_icache_range;
 
-        __flush_kernel_vmap_range       = octeon_flush_kernel_vmap_range;
-
         build_clear_page();
         build_copy_page();
-
-        board_cache_error_setup = octeon_cache_error_setup;
 }
 
-/*
+/**
  * Handle a cache error exception
  */
-static RAW_NOTIFIER_HEAD(co_cache_error_chain);
-
-int register_co_cache_error_notifier(struct notifier_block *nb)
-{
-        return raw_notifier_chain_register(&co_cache_error_chain, nb);
-}
-EXPORT_SYMBOL_GPL(register_co_cache_error_notifier);
 
-int unregister_co_cache_error_notifier(struct notifier_block *nb)
+static void  cache_parity_error_octeon(int non_recoverable)
 {
-        return raw_notifier_chain_unregister(&co_cache_error_chain, nb);
-}
-EXPORT_SYMBOL_GPL(unregister_co_cache_error_notifier);
-
-static void co_cache_error_call_notifiers(unsigned long val)
-{
-        int rv = raw_notifier_call_chain(&co_cache_error_chain, val, NULL);
-        if ((rv & ~NOTIFY_STOP_MASK) != NOTIFY_OK) {
-                u64 dcache_err;
-                unsigned long coreid = cvmx_get_core_num();
-                u64 icache_err = read_octeon_c0_icacheerr();
-
-                if (val) {
-                        dcache_err = cache_err_dcache[coreid];
-                        cache_err_dcache[coreid] = 0;
-                } else {
-                        dcache_err = read_octeon_c0_dcacheerr();
-                }
-
-                pr_err("Core%lu: Cache error exception:\n", coreid);
-                pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
-                if (icache_err & 1) {
-                        pr_err("CacheErr (Icache) == %llx\n",
-                               (unsigned long long)icache_err);
-                        write_octeon_c0_icacheerr(0);
-                }
-                if (dcache_err & 1) {
-                        pr_err("CacheErr (Dcache) == %llx\n",
-                               (unsigned long long)dcache_err);
-                }
+        unsigned long coreid = cvmx_get_core_num();
+        uint64_t icache_err = read_octeon_c0_icacheerr();
+
+        pr_err("Cache error exception:\n");
+        pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
+        if (icache_err & 1) {
+                pr_err("CacheErr (Icache) == %llx\n",
+                       (unsigned long long)icache_err);
+                write_octeon_c0_icacheerr(0);
+        }
+        if (cache_err_dcache[coreid] & 1) {
+                pr_err("CacheErr (Dcache) == %llx\n",
+                       (unsigned long long)cache_err_dcache[coreid]);
+                cache_err_dcache[coreid] = 0;
         }
+
+        if (non_recoverable)
+                panic("Can't handle cache error: nested exception");
 }
 
-/*
+/**
  * Called when the the exception is recoverable
  */
 
 asmlinkage void cache_parity_error_octeon_recoverable(void)
 {
-        co_cache_error_call_notifiers(0);
+        cache_parity_error_octeon(0);
 }
 
 /**
@@ -347,6 +318,5 @@ asmlinkage void cache_parity_error_octeon_recoverable(void)
 
 asmlinkage void cache_parity_error_octeon_non_recoverable(void)
 {
-        co_cache_error_call_notifiers(1);
-        panic("Can't handle cache error: nested exception");
+        cache_parity_error_octeon(1);
 }