blackfin: cplb: add support for bf60x

Bf60x support big CPLB pages, this commit enable it.

Signed-off-by: Bob Liu <lliubbo@gmail.com>

2 files changed, 8 insertions, 2 deletions

diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 886e00014d7..3e366dc2d6e 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -139,7 +139,7 @@ void __init generate_cplb_tables_all(void)
         dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
         dcplb_bounds[i_d++].data = 0;
         /* BootROM -- largest one should be less than 1 meg.  */
-        dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+        dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
         dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
         if (L2_LENGTH) {
                 /* Addressing hole up to L2 SRAM.  */
@@ -178,7 +178,7 @@ void __init generate_cplb_tables_all(void)
         icplb_bounds[i_i].eaddr = BOOT_ROM_START;
         icplb_bounds[i_i++].data = 0;
         /* BootROM -- largest one should be less than 1 meg.  */
-        icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+        icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
         icplb_bounds[i_i++].data = SDRAM_IGENERIC;
 
         if (L2_LENGTH) {
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
index 5b88861d618..e854f9066cb 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
@@ -179,6 +179,12 @@ MGR_ATTR static int dcplb_miss(int cpu)
                 addr = addr1;
         }
 
+#ifdef CONFIG_BF60x
+        if ((addr >= ASYNC_BANK0_BASE)
+                && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
+                d_data |= PAGE_SIZE_64MB;
+#endif
+
         /* Pick entry to evict */
         idx = evict_one_dcplb(cpu);