drm/radeon: fix typo in evergreen dma fence

SRBM write packet takes DW aligned registers.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f92f6bb1887..dcdff14dc13 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3231,7 +3231,7 @@ void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
         /* flush HDP */
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
-        radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
+        radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
         radeon_ring_write(ring, 1);
 }