From ddee87f208b6229d2910dd5930c87089dc56c87e Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 25 Feb 2010 15:04:14 +0100 Subject: ARM: 5959/1: ARM: perf-events: request PMU interrupts with IRQF_NOBALANCING If IRQ balancing is used on a multicore ARM system, PMU interrupt lines may be relocated onto CPUs other than the one causing the counter overflow. This can result in misattribution of events to the wrong core and, in the case that the CPU handling the interrupt has not experience counter overflow, the interrupt can be disabled because the handler returns IRQ_NONE. This patch adds the IRQF_NOBALANCING flag to the request_irq call in perf_events.c. Acked-by: Jamie Iles Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/kernel/perf_event.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/kernel') diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index c54ceb3d1f9..b44d15948b5 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -332,7 +332,8 @@ armpmu_reserve_hardware(void) for (i = 0; i < pmu_irqs->num_irqs; ++i) { err = request_irq(pmu_irqs->irqs[i], armpmu->handle_irq, - IRQF_DISABLED, "armpmu", NULL); + IRQF_DISABLED | IRQF_NOBALANCING, + "armpmu", NULL); if (err) { pr_warning("unable to request IRQ%d for ARM " "perf counters\n", pmu_irqs->irqs[i]); -- cgit v1.2.2 From d10fca9f39238b07cc670b441d2b423de30359d2 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 26 Feb 2010 10:46:15 +0100 Subject: ARM: 5960/1: ARM: perf-events: fix v7 event selection mask The event selection mask for ARMv7 cores [ARMV7_EVTSEL_MASK] is incorrectly set to 0x7f. This means that the top bit of an event ID is ignored, so counting branch misses (id=0x10) and ISBs (id=0x90) give the same results. This patch sets the event selection mask to the correct value of 0xff. Signed-off-by: Jean Pihet Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/kernel/perf_event.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/kernel') diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index b44d15948b5..c45a155a73d 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -1625,7 +1625,7 @@ enum armv7_counters { /* * EVTSEL: Event selection reg */ -#define ARMV7_EVTSEL_MASK 0x7f /* Mask for writable bits */ +#define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */ /* * SELECT: Counter selection reg -- cgit v1.2.2 From 1027247f6eb727db6c600b9eb02796f0766ae704 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 12 Feb 2010 14:36:24 +0000 Subject: ARM: Add L2 cache handling to smp boot support The page table and secondary data which we're asking the secondary CPU to make use of has to hit RAM to ensure that the secondary CPU can see it since it may not be taking part in coherency or cache searches at this point. Acked-by: Santosh Shilimkar Signed-off-by: Russell King --- arch/arm/kernel/smp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/kernel') diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 57162af53dc..577543f3857 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -99,6 +99,7 @@ int __cpuinit __cpu_up(unsigned int cpu) *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) | PMD_TYPE_SECT | PMD_SECT_AP_WRITE); flush_pmd_entry(pmd); + outer_clean_range(__pa(pmd), __pa(pmd + 1)); /* * We need to tell the secondary core where to find @@ -106,7 +107,8 @@ int __cpuinit __cpu_up(unsigned int cpu) */ secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; secondary_data.pgdir = virt_to_phys(pgd); - wmb(); + __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data)); + outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1)); /* * Now bring the CPU into our world. -- cgit v1.2.2 From 5d8614cc5d6c5c02b7995ed97303481d4e3a8cc7 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 12 Mar 2010 11:03:58 +0100 Subject: ARM: 5989/1: ARM: KGDB: add support for SMP platforms To support SMP platforms, KGDB requires the architecture backend to implement the kgdb_roundup_cpus function. This patch, taken against 2.6.33, implements the function for ARM based on the MIPS port. Cc: Jason Wessel Cc: Jean-Michel Hautbois Cc: KGDB Mailing List Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/kernel/kgdb.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/kernel') diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c index ba8ccfede96..a5b846b9895 100644 --- a/arch/arm/kernel/kgdb.c +++ b/arch/arm/kernel/kgdb.c @@ -9,6 +9,7 @@ * Authors: George Davis * Deepak Saxena */ +#include #include #include @@ -158,6 +159,18 @@ static struct undef_hook kgdb_compiled_brkpt_hook = { .fn = kgdb_compiled_brk_fn }; +static void kgdb_call_nmi_hook(void *ignored) +{ + kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs()); +} + +void kgdb_roundup_cpus(unsigned long flags) +{ + local_irq_enable(); + smp_call_function(kgdb_call_nmi_hook, NULL, 0); + local_irq_disable(); +} + /** * kgdb_arch_init - Perform any architecture specific initalization. * -- cgit v1.2.2 From 8e4971f2fb2380ce66196136e113d04196b80fcd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Anders=20Grafstr=C3=B6m?= Date: Mon, 15 Mar 2010 16:04:14 +0100 Subject: ARM: 5991/1: Fix regression in restore_user_regs macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ARMv5T and earlier require that a ldm {}^ instruction is not followed by an instruction that accesses banked registers. This patch restores the nop that was lost in commit b86040a59feb255a8193173caa4d5199464433d5. Signed-off-by: Anders Grafström Signed-off-by: Russell King --- arch/arm/kernel/entry-header.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/kernel') diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 7e9ed1eea40..d93f976fb38 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -102,6 +102,8 @@ .else ldmdb sp, {r0 - lr}^ @ get calling r0 - lr .endif + mov r0, r0 @ ARMv5T and earlier require a nop + @ after ldm {}^ add sp, sp, #S_FRAME_SIZE - S_PC movs pc, lr @ return & move spsr_svc into cpsr .endm -- cgit v1.2.2