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| * config bluetooth as modulesAndy Green2012-08-17
| | | | | | | | | | | | | | | | | | | | With this, you need the following in /etc/rc.local on ubuntu to get working BT modprobe hci_uart modprobe btwilink /usr/bin/uim & Signed-off-by: Andy Green <andy.green@linaro.org>
| * omap2 panda add btwilink deviceAndy Green2012-08-17
| | | | | | | | | | | | | | Without btwilink device instantiation, nothing happens on the bluetooth side Signed-off-by: Andy Green <andy.green@linaro.org>
| * omap2 panda upgrade bluetooth supportAndy Green2012-08-17
| | | | | | | | | | | | | | | | | | Bluetooth driver for wl12xx BT module now assumes there are more members defined in platform_data, blows up if they aren't there. This patch adds them. Signed-off-by: Andy Green <andy.green@linaro.org>
| * Subject: [PATCH 20/21] Subject: [PATCH 18/19] OMAP2: DSS2: Adding ↵Jassi Brar2012-08-17
| | | | | | | | | | | | | | | | | | i2c_bus_num to panel_generic_dpi_data to probe the eeprom The i2c_bus_num can be used to probe needed information from the eeprom, like EDID from DVI monitors. Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
| * Subject: [PATCH 19/21] Subject: [PATCH 19/19] panda: select HDMI as default ↵Sebastien Jan2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | video output Tested with following kernel command line arguments: vram=32M omapfb.vram=0:8M,1:8M The omapfb.vram is necessary to properly size the FB, else FB are sized for a 640x480 screen, and cannot be properly re-sized afterwards. Signed-off-by: Sebastien Jan <s-jan@ti.com>
| * config omap2plus highmemAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * Subject: [PATCH 1/3] arm/dt: Add Pandaboard devicetree supportGrant Likely2012-08-17
| | | | | | | | | | | | Enable basic device tree support on Pandaboard Signed-off-by: Grant Likely <grant.likely@linaro.org>
| * config omap2plus ehci usb ethernetAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * config omap2plus wl12xx and bluetoothAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * config omap2plus cpufreq cpuidleAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * config omap2plus dss builtinAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * config omap2plus ext4 and preemptAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * config omap2plus devtmpfsAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * ARM: L2: Add and export outer_clean_allVikram Pandita2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | The Errata 588369 and 539766 demands that clean all operation be done as clean each way at a time This patch also raps the implementation under the CONFIG errata macro so that for non-errata version silicon it can be disabled Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Woodruff, Richard <r-woodruff2@ti.com>
| * OMAP2+: PANDA: Clean up casting warning on MAC setting codeAndy Green2012-08-17
| | | | | | | | | | | | Clean up casting warning Signed-off-by: Andy Green <andy.green@linaro.org>
| * OMAP2+: PANDA: Fix up random or missing MAC addresses for eth0 and wlan0Andy Green2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch registers a network device notifier callback to set the mac addresses for the onboard network assets of Panda correctly, despite the drivers involved have used a random or all-zeros MAC address. The technique was suggested by Alan Cox on lkml. It works by device path so it corrects the MAC addresses even if the drivers are in modules loaded in an order that changes their interface name from usual (eg, the onboard module might be "wlan1" if there is a USB wireless stick plugged in and its module is inserted first.) Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andy Green <andy.green@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * OMAP2+: add cpu id register to MAC address helperAndy Green2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a generic helper function that can set a MAC address using data from the OMAP unique CPU ID register. For comparison purposes this produces a MAC address of 2e:40:70:f0:12:06 for the ethernet device on my Panda. Signed-off-by: Andy Green <andy.green@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * config early printk enabledAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * config introduce omap4_defconfigAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * OMAP4: PM: Export omap4_get_base*() rather than global address pointersSantosh Shilimkar2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | This patch exports APIs to get base address for GIC distributor, CPU interface, SCU and PL310 L2 Cache which are used in OMAP4 PM code. This was suggested by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com>
| * OMAP4: PM: Add SAR RAM supportSantosh Shilimkar2012-08-17
| | | | | | | | | | | | | | | | This patch adds SAR RAM support on OMAP4430. SAR RAM used to save and restore the HW context in low power modes. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com>
| * OMAP4: PM: Add CPUX OFF mode supportSantosh Shilimkar2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the CPU0 and CPU1 off mode support. CPUX close switch retention (CSWR) is not supported by hardware design. The CPUx OFF mode isn't supported on OMAP4430 ES1.0 CPUx sleep code is common for hotplug, suspend and CPUilde. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com>
| * OMAP4: PM: Add suppport for IO wakeupRajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | | | This patch adds support for IO wakeup infrasturcture [Todd: avoided multiple pwrdms_setup] Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Todd Poynor <toddpoynor@google.com>
| * omap4460 changes need missing includesAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * OMAP3+: PM: voltagedomain: introduce dependent voltage domain supportVishwanath BS2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There could be dependencies between various voltage domains for maintaining system performance or hardware limitation reasons like VDD<X> should be at voltage v1 when VDD<Y> is at voltage v2. This patch introduce dependent vdd information structures in the voltage layer which can be used to populate these dependencies for a voltage domain. Based on original patch from Thara. NOTE: OMAP4460 dependency table is not frozen yet, hence not added. [nm@ti.com: cleanups and squash for OMAP3,4 data] Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Cc: Thara Gopinath <thara@ti.com>
| * ARM: L2X0: Add the Prefetch Control Register bits to header.Santosh Shilimkar2012-08-17
| | | | | | | | | | | | While at this, fix some indentation issues in cache-l2x0.h Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * OMAP4460 cleanup static def nonstatic prototypeAndy Green2012-08-17
| | | | | | | | Signed-off-by: Andy Green <andy.green@linaro.org>
| * OMAP4460: OPP: Update MPU and IVA dependencyRajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | | | | | | | Define new tables for 4460 specific MPU and IVA voltage dependencies. Also uncomment the 4430 specific dependencies since CORE voltage scale is functional now. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP4460: cpufreq: Use the virtual clock node to scale MPURajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | 4460 has a new virtual clock node modeled to handle DCC and other async bridge dependencies. Make cpufreq use the virtual node for scaling. Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP4: PM44: Handle 4460 clk name delta for mpuNishanth Menon2012-08-17
| | | | | | | | | | | | | | | | The DPLL for MPU should now be virt_dpll_mpu_ck instead of dpll_mpu_ck for OMAP4460. Fix this for idle changes Reported-by: Colin Cross <ccross@google.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP4460: L2X0: Temporary work-around for stability.Santosh Shilimkar2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP4460 ES1.0 seems to suffer from stability with L2 cache enabled. The root-cause analysis is ongoing but in meantime this chabe is to enable a software WA with L2 cache enabled build. The WA consist of locking certain cache ways based on their positions on the physical memory layout. Downside of this WA is that effective L2 cache size will be 512 KB instead of 1 MB. Of course this is temporary WA and needs to removed once the root cause and the right fix is found. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * OMAP4: L2X0: Update PL310 register bits for OMAP4460Santosh Shilimkar2012-08-17
| | | | | | | | | | | | | | On OMAP4460, L2 double line fill feature is available. Enable the same along with optimal POR offset. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * Merge branch 'v3.0-4460-fixes' into omap-pm-integrationNishanth Menon2012-08-17
| |
| * OMAP4: OPP: add OMAP4460 definitionsVishwanath BS2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add OMAP4460 OPP definitions for voltage and frequencies based on OMAP4460 ES1.0 DM Operating Condition Addendum Version 0.1 The following exceptions are present: * Smartreflex support is still on experimental mode: the gains and min limits are currently pending characterization data. The values are picked up currently from TI's Kernel 2.6.35: git://git.omapzoom.org/kernel/omap.git p-android-omap-2.6.35-4460-wip dcfa2a4 * Efuse offset for core OPP100-OV setting is not clear in documentation and seems to be not supported in K35 * IVA OPPs beyond OPP100 are disabled due to the delta between max OMAP4460 current requirements and Phoenix Max supply on VCORE2 in the default configuration - boards which have supply which can support this should explicitly call opp_enable and enable the same. * MPU OPPs > OPPTURBO can easily be detected using a efuse burnt - currently disabled pending clock cleanups. [nm@ti.com: cleanups and updates from Datamanual and k35 source] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
| * OMAP4: PM: Handle 4460 clk name delta for mpuNishanth Menon2012-08-17
| | | | | | | | | | | | | | | | The DPLL for MPU should now be dpll_mpu_ck instead of virt_dpll_mpu_ck for 4460. Reported-by: Colin Cross <ccross@google.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP4460: dpll: Control async bridge to ABE and L3/MA to EMIFRajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | On OMAP4460 when the MPU Frequency is above 748Mhz, the programmable divider for the Async bridge to ABE must be set to MPU-Freq/8. For lower frequency, it should be MPU-Freq/4. Similarly for MPU Frequency above 920Mhz, the programmable divider for the async bridge to L3 and Memory Adapter interfaces of EMIF must be MPU-Freq/4. For lower frequency, they should be MPU-Freq/2. Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP4460: dpll: Support MPU frequencies > 1 GhzRajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP4460 platform needs DCC (Duty cycle correction) enabled for frequencies above 1GHz from the MPU DPLL. Also on 4460, the MPU clk for frequencies higher than 1Ghz is sourced from CLKOUTX2_M3, instead of CLKOUT_M2, while value of M3 is fixed to 1. Hence for frequencies higher than 1 Ghz, the dpll should be locked at half the rate so the CLKOUTX2_M3 out then matches the requested rate. To do this a virtual clock node 'virt_dpll_mpu_ck' is modeled, which has custom recalc, round_rate and set_rate functions implemented which handle all the above requirements. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
| * OMAP4: clockdomain: Reuse on 4460 using CHIP_IS_44XXRajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | The 4460 platform has no difference in the clockdomains as compared to the 4430 platform. Hence just update the .omap_chip field to make sure the same clockdomains model data can be reused on the 4460 platform. Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP4: powerdomain: Update MPU powerdomain for 4460Rajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | | | | | The 4460 platform has changes in the MPU powerdomain, hence model a new powerdomain for it and identify is using the CHIP_IS_OMAP446X macro. Also move all the common powerdomains to use CHIP_IS_44XX so they are reused on OMAP4460. Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP4: clocks: Update the clock tree with 4460 clock nodesRajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | | | OMAP4460 platform has a few clock nodes which are added and a few which are missing (compared to the 4430 platform) Update the clock tree accordingly and handle these nodes using the clock flags (CK_*). Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP4: clocks: distinguish 4430 and 4460Rajendra Nayak2012-08-17
| | | | | | | | | | | | | | | | | | OMAP4460 platform has a few clock nodes which are added and a few which are missing (compared to the 4430 platform) rename current 4430 definitions to 44XX and followon patches will introduce the 4460 changes Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP4: hwmod: differentiate 4430 and 4460 bandgapNishanth Menon2012-08-17
| | | | | | | | | | | | | | | | OMAP4430 and 4460 have slightly different functional clocks. we need to map this back into hwmod database as well to ensure sanity. Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP4460: hwmod: Do not reset GPIO1 during hwmod initMoiz Sonasath2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For OMAP4460, GPIO-7 of bank1 is used for controling the TPS modes, hence GPIO1 should not be reset during init as reset will cause the TPS voltage to drop to 0.9 V. IMPORTANT: this patch has been rejected upstream: http://marc.info/?t=130637509100002&r=1&w=2 Recommendation is: omap_hwmod_no_setup_reset in board files we fork in that respect to make it easier for boards following TI reference schematics. Originally from: http://git.omapzoom.org/?p=kernel/omap.git;a=commitdiff;h=52ae4f0de03b17c064d9ce90a580230f1a596ec1 [nm@ti.com: upstream version] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Moiz Sonasath <m-sonasath@ti.com>
| * OMAP4: hwmod: make current hwmods common for 4460 and 4430Aneesh V2012-08-17
| | | | | | | | | | | | | | | | | | | | Make all hwmod data used for OMAP4430 available for the OMAP44XX class so that OMAP4460 can use them. We will modify the required 4460 hwmod in further patch(es). [nm@ti.com: just rebased to .39] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com>
| * OMAP4: PRM: OMAP4460 specific PRM and CM register bitshiftsRajendra Nayak2012-08-17
| | | | | | | | | | | | | | This patch adds additional register bitshifts for registers added in OMAP4460 platform. Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP: ID: introduce chip detection for OMAP4460Aneesh V2012-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for detecting the latest in the OMAP4 family: OMAP4460 Among other changes, the new chip also can support 1.5GHz A9s, 1080p stereoscopic 3D and 12 MP stereo (dual camera). In addition, we have changes to OPPs supported, clock tree etc, hence having a chip detection is required. Starting from OMAP4460 ES1.0, we are moving from HAWKEYE to Ramp system for chip identification. Since the bit offsets are the same, just rename the variable for dual use. For more details on OMAP4460, see Highlights: http://focus.ti.com/general/docs/wtbu/wtbuproductcontent.tsp?contentId=53243&navigationId=12843&templateId=6123 Public TRM is available here as usual: http://focus.ti.com/general/docs/wtbu/wtbudocumentcenter.tsp?templateId=6123&navigationId=12667 [nm@ti.com: cleanups and introduction of ramp system] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com>
| * m68k: Correct the Atari ALLOWINT definitionMikael Pettersson2012-08-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BugLink: http://bugs.launchpad.net/bugs/1034988 commit c663600584a596b5e66258cc10716fb781a5c2c9 upstream. Booting a 3.2, 3.3, or 3.4-rc4 kernel on an Atari using the `nfeth' ethernet device triggers a WARN_ONCE() in generic irq handling code on the first irq for that device: WARNING: at kernel/irq/handle.c:146 handle_irq_event_percpu+0x134/0x142() irq 3 handler nfeth_interrupt+0x0/0x194 enabled interrupts Modules linked in: Call Trace: [<000299b2>] warn_slowpath_common+0x48/0x6a [<000299c0>] warn_slowpath_common+0x56/0x6a [<00029a4c>] warn_slowpath_fmt+0x2a/0x32 [<0005b34c>] handle_irq_event_percpu+0x134/0x142 [<0005b34c>] handle_irq_event_percpu+0x134/0x142 [<0000a584>] nfeth_interrupt+0x0/0x194 [<001ba0a8>] schedule_preempt_disabled+0x0/0xc [<0005b37a>] handle_irq_event+0x20/0x2c [<0005add4>] generic_handle_irq+0x2c/0x3a [<00002ab6>] do_IRQ+0x20/0x32 [<0000289e>] auto_irqhandler_fixup+0x4/0x6 [<00003144>] cpu_idle+0x22/0x2e [<001b8a78>] printk+0x0/0x18 [<0024d112>] start_kernel+0x37a/0x386 [<0003021d>] __do_proc_dointvec+0xb1/0x366 [<0003021d>] __do_proc_dointvec+0xb1/0x366 [<0024c31e>] _sinittext+0x31e/0x9c0 After invoking the irq's handler the kernel sees !irqs_disabled() and concludes that the handler erroneously enabled interrupts. However, debugging shows that !irqs_disabled() is true even before the handler is invoked, which indicates a problem in the platform code rather than the specific driver. The warning does not occur in 3.1 or older kernels. It turns out that the ALLOWINT definition for Atari is incorrect. The Atari definition of ALLOWINT is ~0x400, the stated purpose of that is to avoid taking HSYNC interrupts. irqs_disabled() returns true if the 3-bit ipl & 4 is non-zero. The nfeth interrupt runs at ipl 3 (it's autovector 3), but 3 & 4 is zero so irqs_disabled() is false, and the warning above is generated. When interrupts are explicitly disabled, ipl is set to 7. When they are enabled, ipl is masked with ALLOWINT. On Atari this will result in ipl = 3, which blocks interrupts at ipl 3 and below. So how come nfeth interrupts at ipl 3 are received at all? That's because ipl is reset to 2 by Atari-specific code in default_idle(), again with the stated purpose of blocking HSYNC interrupts. This discrepancy means that ipl 3 can remain blocked for longer than intended. Both default_idle() and falcon_hblhandler() identify HSYNC with ipl 2, and the "Atari ST/.../F030 Hardware Register Listing" agrees, but ALLOWINT is defined as if HSYNC was ipl 3. [As an experiment I modified default_idle() to reset ipl to 3, and as expected that resulted in all nfeth interrupts being blocked.] The fix is simple: define ALLOWINT as ~0x500 instead. This makes arch_local_irq_enable() consistent with default_idle(), and prevents the !irqs_disabled() problems for ipl 3 interrupts. Tested on Atari running in an Aranym VM. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Tested-by: Michael Schmitz <schmitzmic@googlemail.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
| * m68k: Make sys_atomic_cmpxchg_32 work on classic m68kAndreas Schwab2012-08-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BugLink: http://bugs.launchpad.net/bugs/1034988 commit 9e2760d18b3cf179534bbc27692c84879c61b97c upstream. User space access must always go through uaccess accessors, since on classic m68k user space and kernel space are completely separate. Signed-off-by: Andreas Schwab <schwab@linux-m68k.org> Tested-by: Thorsten Glaser <tg@debian.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
| * ARM: OMAP2+: OPP: Fix to ensure check of right oppdef after bad oneNishanth Menon2012-08-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BugLink: http://bugs.launchpad.net/bugs/1034988 commit b110547e586eb5825bc1d04aa9147bff83b57672 upstream. Commit 9fa2df6b90786301b175e264f5fa9846aba81a65 (ARM: OMAP2+: OPP: allow OPP enumeration to continue if device is not present) makes the logic: for (i = 0; i < opp_def_size; i++) { <snip> if (!oh || !oh->od) { <snip> continue; } <snip> opp_def++; } In short, the moment we hit a "Bad OPP", we end up looping the list comparing against the bad opp definition pointer for the rest of the iteration count. Instead, increment opp_def in the for loop itself and allow continue to be used in code without much thought so that we check the next set of OPP definition pointers :) Cc: Steve Sakoman <steve@sakoman.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
| * powerpc: Fix wrong divisor in usecs_to_cputimeAndreas Schwab2012-08-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BugLink: http://bugs.launchpad.net/bugs/1034988 commit 9f5072d4f63f28d30d343573830ac6c85fc0deff upstream. Commit d57af9b (taskstats: use real microsecond granularity for CPU times) renamed msecs_to_cputime to usecs_to_cputime, but failed to update all numbers on the way. This causes nonsensical cpu idle/iowait values to be displayed in /proc/stat (the only user of usecs_to_cputime so far). This also renames __cputime_msec_factor to __cputime_usec_factor, adapting its value and using it directly in cputime_to_usecs instead of doing two multiplications. Signed-off-by: Andreas Schwab <schwab@linux-m68k.org> Acked-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Michal Hocko <mhocko@suse.cz> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-22 11:35:16 -0400