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| | | * | | | | ARM: SMP: collect IPI and local timer IRQs for /proc/statRussell King2010-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IPI and local timer interrupts weren't being properly accounted for in /proc/stat. Collect them from the irq_stat structure, and return their sum. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: SMP: provide individual IPI interrupt statisticsRussell King2010-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This separates out the individual IPI interrupt counts from the total IPI count, which allows better visibility of what IPIs are being used for. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: fix /proc/interrupts formattingRussell King2010-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per x86, align the initial column according to how many IRQs we have. Also, provide an english explaination for the 'LOC:' and 'IPI:' lines. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: SMP: move ipi_count into irq_stat structureRussell King2010-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the ipi_count into irq_stat, which allows the ipi_data structure to be entirely removed. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: SMP: provide accessors for irq_stat dataRussell King2010-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide __inc_irq_stat() and __get_irq_stat() to increment and read the irq stat counters. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: include local timer irq stats only when local timers configuredRussell King2010-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: SMP: pass an ipi number to smp_cross_call()Russell King2010-12-03
| | | | |_|/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to use smp_cross_call() to trigger a number of different software generated interrupts, rather than combining them all on one SGI. Recover the SGI number via do_IPI. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: DMA: add support for DMA debuggingRussell King2011-01-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ARM support for the DMA debug infrastructure, which allows the DMA API usage to be debugged. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()Russell King2011-01-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the page_to_dma() and dma_to_page() macros with their PFN equivalents. This allows us to map parts of memory which do not have a struct page allocated to them to bus addresses. This will be used internally by dma_alloc_coherent()/dma_alloc_writecombine(). Build tested on Versatile, OMAP1, IOP13xx and KS8695. Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 6541/1: move sev definition to common system.h include fileShiraz Hashim2010-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sev is used to send wakeup event to other cores in ARMv6K and above. This has been moved from platform specific part to standard common ARM header file (asm/system.h). Also introduced wfi() and wfe(). Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: provide an early platform initialization hookRussell King2010-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows platforms to hook into the initialization early to setup things like scheduler clocks, etc. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: simplify early machine init hooksRussell King2010-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than storing each machine init hook separately, store a pointer to the machine description record and dereference this instead. This pointer is only available while the init sections are present, which is not a problem as we only use it from init code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 6538/1: Subarch IRQ handler macros V3Magnus Damm2010-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per subarch interrupt handler macros V3. This patch breaks out code from the irq_handler macro into arch_irq_handler and arch_irq_handler_default. The macros are put in the header file "entry-macro-multi.S" The arch_irq_handler_default macro is designed to be used by irq_handler in entry-armv.S while arch_irq_handler is suitable for per-subarch use. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 6532/1: Allow machine to specify it's own IRQ handlers at run-timeeric miao2010-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally different ARM platform has different way to decode the IRQ hardware status and demultiplex to the corresponding IRQ handler. This is highly optimized by macro irq_handler in entry-armv.S, and each machine defines their own macro to decode the IRQ number. However, this prevents multiple machine classes to be built into a single kernel. By allowing each machine to specify thier own handler, and making function pointer 'handle_arch_irq' to point to it at run time, this can be solved. And introduce CONFIG_MULTI_IRQ_HANDLER to allow both solutions to work. Comparing with the highly optimized macro of irq_handler, the new function must be written with care not to lose too much performance. And the IPI stuff on SMP is expected to move to the provided arch IRQ handler as well. The assembly code to invoke handle_arch_irq is optimized by Russell King. Signed-off-by: Eric Miao <eric.miao@canonical.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: implement support for read-mostly sectionsRussell King2010-12-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As our SMP implementation uses MESI protocols. Grouping together data which is mostly only read together means that we avoid unnecessary cache line bouncing when this code shares a cache line with other data. In other words, cache lines associated with read-mostly data are expected to spend most of their time in shared state. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 6483/1: arm & sh: factorised duplicated clkdev.cJean-Christop PLAGNIOL-VILLARD2010-11-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | factorise some generic infrastructure to assist looking up struct clks for the ARM & SH architecture. as the code is identical at 99% put the arch specific code for allocation as example in asm/clkdev.h Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUsCatalin Marinas2010-11-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the domain switching functionality via the set_fs and __switch_to functions on cores that have a TLS register. Currently, the ioremap and vmalloc areas share the same level 1 page tables and therefore have the same domain (DOMAIN_KERNEL). When the kernel domain is modified from Client to Manager (via the __set_fs or in the __switch_to function), the XN (eXecute Never) bit is overridden and newer CPUs can speculatively prefetch the ioremap'ed memory. Linux performs the kernel domain switching to allow user-specific functions (copy_to/from_user, get/put_user etc.) to access kernel memory. In order for these functions to work with the kernel domain set to Client, the patch modifies the LDRT/STRT and related instructions to the LDR/STR ones. The user pages access rights are also modified for kernel read-only access rather than read/write so that the copy-on-write mechanism still works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register (CPU_32v6K is defined) since writing the TLS value to the high vectors page isn't possible. The user addresses passed to the kernel are checked by the access_ok() function so that they do not point to the kernel space. Tested-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | | Merge branch 'clksrc' into develRussell King2011-01-05
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-vexpress/v2m.c arch/arm/plat-omap/counter_32k.c arch/arm/plat-versatile/Makefile
| | * | | | | | ARM: sched_clock: provide common infrastructure for sched_clock()Russell King2010-12-22
| | | |_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide common sched_clock() infrastructure for platforms to use to create a 64-bit ns based sched_clock() implementation from a counter running at a non-variable clock rate. This implementation is based upon maintaining an epoch for the counter and an epoch for the nanosecond time. When we desire a sched_clock() time, we calculate the number of counter ticks since the last epoch update, convert this to nanoseconds and add to the epoch nanoseconds. We regularly refresh these epochs within the counter wrap interval. We perform a similar calculation as above, and store the new epochs. We read and write the epochs in such a way that sched_clock() can easily (and locklessly) detect when an update is in progress, and repeat the loading of these constants when they're known not to be stable. The one caveat is that sched_clock() is not called in the middle of an update. We achieve that by disabling IRQs. Finally, if the clock rate is known at compile time, the counter to ns conversion factors can be specified, allowing sched_clock() to be tightly optimized. We ensure that these factors are correct by providing an initialization function which performs a run-time check. Acked-by: Peter Zijlstra <peterz@infradead.org> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Mikael Pettersson <mikpe@it.uu.se> Tested-by: Eric Miao <eric.y.miao@gmail.com> Tested-by: Olof Johansson <olof@lixom.net> Tested-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | Merge branch 'ftrace' of git://github.com/rabinv/linux-2.6 into devel-stableRussell King2010-11-26
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| | | * | | | ARM: place C irq handlers in IRQ_ENTRY for ftraceRabin Vincent2010-11-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When FUNCTION_GRAPH_TRACER is enabled, place do_IRQ() and friends in the IRQ_ENTRY section so that the irq-related features of the function graph tracer work. Signed-off-by: Rabin Vincent <rabin@rab.in>
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| *-----------. \ \ \ \ \ Merge branches 'ftrace', 'gic', 'io', 'kexec', 'mod', 'sa11x0', 'sh' and ↵Russell King2011-01-05
| |\ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|/ / / / / | | |/| | | | | | | / / / | | | | | | | | |_|/ / / | | | | | | | |/| | | / | | | | | |_|_|_|_|_|/ | | | | |/| | | | | | 'versatile' into devel
| | | | | | | | * | | ARM: 6432/1: move timer-sp.c from versatile to commonRob Herring2010-11-04
| | | | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Rob Herring <rob.herring@smooth-stone.com> The timer-sp h/w used on versatile platforms can also be used for other platforms, so move it to a common location. Signed-off-by: Rob Herring <rob.herring@smooth-stone.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * / / / ARM: module: clean up handling of ELF unwind tablesRussell King2010-12-01
| | | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need to keep pointers to the ELF sections available while the module is loaded - we only need the section pointers while we're finding and registering the unwind tables, which can all be done during the finalize stage of loading. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | | ARM: 6518/1: kexec: Fix crash_setup_regs() for ARMv7 and CONFIG_THUMB2_KERNELDave Martin2010-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Fix kexec build failure with CONFIG_THUMB2_KERNEL. * Avoids deprecated/forbidden sp and pc usage in for ARMv7 onwards, retaining compatibility with older architecture versions. * The pc value saved to newregs is now aligned on a predictable instruction boundary. (stmia { ... pc } or str pc has implementation-defined results in most versions of the ARM architecutre, and is prohibited (unpredictable) in Thumb-2.) * Switch to named inline asm arguments (else I get readily confused ...) The resulting code should be compatible with all architecture versions >= v3, with or without CONFIG_THUMB2_KERNEL. Reviewed-by: Will Deacon <will.deacon@arm.com> Tested-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | | ARM: 6517/1: kexec: Add missing memory clobber to inline asm in ↵Dave Martin2010-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | crash_setup_regs() Currently, the inline asm is passed &newregs->ARM_r0 as in input, when modifying multiple fields of newregs. It's plausible to assume that GCC will assume newregs->ARM_r0 is modified when passed the address, but unfortunately this assumption is incorrect. Also, GCC has no way to guess that the other ARM_r* fields are modified without the addition of a "memory" clobber. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | | ARM: 6486/1: provide zero vmcore_elf64_check_arch()Mika Westerberg2010-11-30
| | | |_|/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we don't support 64-bit ELF vmcores. This also prevents the following warning: fs/proc/vmcore.c: In function 'parse_crash_elf64_headers': fs/proc/vmcore.c:502: warning: passing argument 1 of 'elf_check_arch' from incompatible pointer type Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | | ARM: io: simplify ioremap* and iounmap definitionsRussell King2010-12-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need to repeat the same definitions of the ioremap*(), once in terms of __arch_ioremap() and again in terms of __arm_ioremap(). Instead, if the platform hasn't provided an __arch_ioremap, define this to be __arm_ioremap, and only define the ioremap*() set using __arch_ioremap. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | | ARM: io: make iounmap() a simple macroRussell King2010-12-08
| | | |/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defining iounmap() with arguments prevents it from being used as a function pointer, causing platforms to work around this. Instead, define it to be a simple macro. Do the same for __arch_io(re|un)map too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: GIC: move enablement of PPI interrupts to gic.cRussell King2010-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid adding nasty genirq-specific code to local timers to enable PPI interrupts. Instead, provide a gic function to do this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: GIC: private a standard get_irqnr_preamble assembler macroRussell King2010-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a standard get_irqnr_preamble assembler macro for platforms to use, which retrieves the base address of the GIC CPU interface from gic_cpu_base_addr. Allow platforms to override this by defining HAVE_GET_IRQNR_PREAMBLE. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: GIC: consolidate gic_cpu_base_addr to common GIC codeRussell King2010-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_initRussell King2010-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: GIC: provide a single initialization function for boot CPURussell King2010-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: 6475/1: Introduce asm/hardware/entry-macro-gic.SMagnus Damm2010-12-07
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is the identical GIC demux implementation merge V3. Instead of implementing same code over and over simply share it in entry-macro-gic.S. The shared code is based on the realview implementation. Each GIC demux instance still has to setup the base address of the controller using the get_irqnr_preamble macro. The rest of the GIC specific code can be shared. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | Merge branch 'fix' of ↵Russell King2011-01-03
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| | * | | | | ARM: it8152: add IT8152_LAST_IRQ definition to fix build errorMike Rapoport2011-01-03
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 6ac6b817f3f4c23c5febd960d8deb343e13af5f3 (ARM: pxa: encode IRQ number into .nr_irqs) removed definition of ITE_LAST_IRQ which caused the following build error: CC arch/arm/common/it8152.o arch/arm/common/it8152.c: In function 'it8152_init_irq': arch/arm/common/it8152.c:86: error: 'IT8152_LAST_IRQ' undeclared (first use in this function) arch/arm/common/it8152.c:86: error: (Each undeclared identifier is reported only once arch/arm/common/it8152.c:86: error: for each function it appears in.) make[2]: *** [arch/arm/common/it8152.o] Error 1 Defining the IT8152_LAST_IRQ in the arch/arm/include/hardware/it8152.c fixes the build. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | | | ARM: 6605/1: Add missing include "asm/memory.h"Axel Lin2011-01-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes below build error by adding the missing asm/memory.h, which is needed for arch_is_coherent(). $ make pxa3xx_defconfig; make CC init/do_mounts_rd.o In file included from include/linux/list_bl.h:5, from include/linux/rculist_bl.h:7, from include/linux/dcache.h:7, from include/linux/fs.h:381, from init/do_mounts_rd.c:3: include/linux/bit_spinlock.h: In function 'bit_spin_unlock': include/linux/bit_spinlock.h:61: error: implicit declaration of function 'arch_is_coherent' make[1]: *** [init/do_mounts_rd.o] Error 1 make: *** [init] Error 2 Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Peter Huewe <peterhuewe@gmx.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: 6536/1: Add missing SZ_{32,64,128}Stephen Warren2010-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... and also remove misleading comment stating that this header is auto-generated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Uwe Kleine-Knig <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: get rid of kmap_high_l1_vipt()Nicolas Pitre2010-12-19
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3e4d3af501 "mm: stack based kmap_atomic()", it is no longer necessary to carry an ad hoc version of kmap_atomic() added in commit 7e5a69e83b "ARM: 6007/1: fix highmem with VIPT cache and DMA" to cope with reentrancy. In fact, it is now actively wrong to rely on fixed kmap type indices (namely KM_L1_CACHE) as kmap_atomic() totally ignores them now and a concurrent instance of it may reuse any slot for any purpose. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * | | | ARM: 6490/1: MM: bugfix: initialize spinlock for init_mm.contextMyungJoo Ham2010-11-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | init_mm used at kernel/sched.c:idle_task_exit() has spin_lock (init_mm.context.id_lock) that is not initialized when spin_lock/unlock is called at an ARM machine. Note that mm_struct.context.id_lock is usually initialized except for the instance of init_mm at linux/arch/arm/mm/context.c Not initializing this spinlock incurs "BUG: pinlock bad magic" warning when spinlock debug is enabled. We have observed such instances when testing PM in S5PC210 machines. Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6489/1: thumb2: fix incorrect optimisation in usraccWill Deacon2010-11-21
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8b592783 added a Thumb-2 variant of usracc which, when it is called with \rept=2, calls usraccoff once with an offset of 0 and secondly with a hard-coded offset of 4 in order to avoid incrementing the pointer again. If \inc != 4 then we will store the data to the wrong offset from \ptr. Luckily, the only caller that passes \rept=2 to this function is __clear_user so we haven't been actively corrupting user data. This patch fixes usracc to pass \inc instead of #4 to usraccoff when it is called a second time. Cc: <stable@kernel.org> Reported-by: Tony Thompson <tony.thompson@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: improve compiler's ability to optimize page tablesRussell King2010-11-21
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Allow the compiler to better optimize the page table walking code by avoiding over-complex pmd_addr_end() calculations. These calculations prevent the compiler spotting that we'll never iterate over the PMD table, causing it to create double nested loops where a single loop will do. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: pxa: fix the missing definition of IRQ_BOARD_ENDEric Miao2010-11-03
| |/ | | | | | | | | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@marvell.com> Cc: Mike Rapoport <mike@compulab.co.il>
| * Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-10-30
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (215 commits) ARM: memblock: setup lowmem mappings using memblock ARM: memblock: move meminfo into find_limits directly ARM: memblock: convert free_highpages() to use memblock ARM: move freeing of highmem pages out of mem_init() ARM: memblock: convert memory detail printing to use memblock ARM: memblock: use memblock to free memory into arm_bootmem_init() ARM: memblock: use memblock when initializing memory allocators ARM: ensure membank array is always sorted ARM: 6466/1: implement flush_icache_all for the rest of the CPUs ARM: 6464/2: fix spinlock recursion in adjust_pte() ARM: fix memblock breakage ARM: 6465/1: Fix data abort accessing proc_info from __lookup_processor_type ARM: 6460/1: ixp2000: fix type of ixp2000_timer_interrupt ARM: 6449/1: Fix for compiler warning of uninitialized variable. ARM: 6445/1: fixup TCM memory types ARM: imx: Add wake functionality to GPIO ARM: mx5: Add gpio-keys to mx51 babbage board ARM: imx: Add gpio-keys to plat-mxc mx31_3ds: Fix spi registration mx31_3ds: Fix the logic for detecting the debug board ...
| | * Merge branch 'devel-stable' into develRussell King2010-10-28
| | |\
| | | * Merge branch 'l2x0-pull-rmk' of ↵Russell King2010-10-28
| | | |\ | | | | | | | | | | | | | | | git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into devel-stable
| | | | * ARM: l2x0: Determine the cache sizeSantosh Shilimkar2010-10-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cache size is needed for to optimise range based maintainance operations Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
| | | | * ARM: l2x0: Fix coding-style in the cache-l2x0.hSantosh Shilimkar2010-10-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace tab with space after #define to be consisten with other define in the file. Also move the bit mask below the register offsets. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
| | | | * arm: Disable outer (L2) cache in kexecThomas Gleixner2010-10-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kexec does not disable the outer cache before disabling the inner caches in cpu_proc_fin(). So L2 is enabled across the kexec jump. When the new kernel enables chaches again, it randomly crashes. Disabling L2 before calling cpu_proc_fin() cures the problem. Disabling L2 requires the following new functions: flush_all(), inv_all() and disable(). Add them to outer_cache_fns and call them from the kexec code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
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