| Commit message (Collapse) | Author | Age |
| |
|
|
|
|
| |
Compile with CONFIG_NP_SECTION=y
|
|\ |
|
| | |
|
|\| |
|
| | |
|
|\|
| |
| |
| |
| |
| | |
Conflicts:
include/litmus/color.h
litmus/Makefile
|
| |
| |
| |
| | |
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
|
| | |
|
| | |
|
| |\ |
|
| | | |
|
| | |
| | |
| | |
| | | |
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
| | |
| | |
| | | |
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| |/
| |
| |
| |
| |
| |
| |
| | |
Conflicts:
include/litmus/color.h
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
|
| |
| |
| |
| | |
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| |
| |
| |
| |
| |
| | |
This is not tested and probably won't work.
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
|
| | |
|
| | |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The ARM arch_{read,write}_trylock implementations include unused
backwards branch labels, since we don't retry the locking operation
if the exclusive store fails.
This patch removes the labels.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Ticket spinlocks ensure locking fairness by introducing a FIFO-like
nature to the granting of lock acquisitions and also reducing the
thundering herd effect when spinning on a lock by allowing the cacheline
to remain in a shared state amongst the waiting CPUs. This is especially
important on systems where memory-access times are not necessarily
uniform when accessing the lock structure (for example, on a
multi-cluster platform where the lock is allocated into L1 when a CPU
releases it).
This patch implements the ticket spinlock algorithm for ARM, replacing
the simpler implementation for ARMv6+ processors.
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Try and fix the cycle counter on ARMv7 CPUs (unsuccessful).
Use the multi-core timer on the ODROID-X to count cycles.
Add lockdown register access to proc.
Add proc options to disable prefetching for L1/L2 cache.
Add test to lockdown.c to print the time to read in various WSSs.
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| |
| |
| |
| | |
This commit is dirty and will be cleaned up when blocking states are tested.
|
| | |
|
|\|
| |
| |
| |
| |
| |
| |
| |
| | |
Conflicts:
arch/arm/mm/cache-l2x0.c
litmus/color_proc.c
litmus/lockdown.c
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| |
| |
| |
| |
| |
| |
| | |
Note: Highmem pages will need to be vmapped in the kernel, or we need to
not use HIGHMEM pages.
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
|
| | |
|
| |\ |
|
| | | |
|
| | | |
|
| | |
| | |
| | |
| | | |
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Conflicts:
arch/arm/mach-omap2/board-omap4panda.c
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| |/
| |
| |
| |
| |
| |
| |
| | |
Conflicts:
arch/arm/mm/cache-l2x0.c
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| |
| |
| |
| | |
Currently is always preempting. This needs to be configurable via proc.
|
| |\
| | |
| | |
| | | |
wip-mc
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
|\ \ \
| | |/
| |/|
| | |
| | |
| | |
| | | |
This is a PandaBoard only merge.
Conflicts:
arch/arm/include/asm/hardware/cache-l2x0.h
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Commit e6f51fb826ce98d436f445aae4eb9e9dba1f30e8 added some floating
point support for LITMUS^RT, but it used 64-bit division that ARM does
not support. Therefore, use the division functions from math64.h.
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
| | |
| | |
| | | |
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
| | |
| | |
| | | |
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Fighting unfixed U-Boots and other beasts that may the cache in
a locked-down state when starting the kernel, we make sure to
disable all cache lock-down when initializing the l2x0 so we
are in a known state.
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Adrian Bunk <adrian.bunk@movial.com>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reported-by: Jan Rinze <janrinze@gmail.com>
Tested-by: Robert Marklund <robert.marklund@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|
| | |
| | |
| | |
| | | |
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
|