aboutsummaryrefslogtreecommitdiffstats
path: root/include/video/omapdss.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/video/omapdss.h')
-rw-r--r--include/video/omapdss.h641
1 files changed, 641 insertions, 0 deletions
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
new file mode 100644
index 00000000000..892b97f8e15
--- /dev/null
+++ b/include/video/omapdss.h
@@ -0,0 +1,641 @@
1/*
2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
24#include <linux/platform_device.h>
25#include <asm/atomic.h>
26
27#define DISPC_IRQ_FRAMEDONE (1 << 0)
28#define DISPC_IRQ_VSYNC (1 << 1)
29#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
30#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
31#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
32#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
33#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
34#define DISPC_IRQ_GFX_END_WIN (1 << 7)
35#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
36#define DISPC_IRQ_OCP_ERR (1 << 9)
37#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
38#define DISPC_IRQ_VID1_END_WIN (1 << 11)
39#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
40#define DISPC_IRQ_VID2_END_WIN (1 << 13)
41#define DISPC_IRQ_SYNC_LOST (1 << 14)
42#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
43#define DISPC_IRQ_WAKEUP (1 << 16)
44#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
45#define DISPC_IRQ_VSYNC2 (1 << 18)
46#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
47#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
48
49struct omap_dss_device;
50struct omap_overlay_manager;
51
52enum omap_display_type {
53 OMAP_DISPLAY_TYPE_NONE = 0,
54 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
55 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
56 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
57 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
58 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
59 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
60};
61
62enum omap_plane {
63 OMAP_DSS_GFX = 0,
64 OMAP_DSS_VIDEO1 = 1,
65 OMAP_DSS_VIDEO2 = 2
66};
67
68enum omap_channel {
69 OMAP_DSS_CHANNEL_LCD = 0,
70 OMAP_DSS_CHANNEL_DIGIT = 1,
71 OMAP_DSS_CHANNEL_LCD2 = 2,
72};
73
74enum omap_color_mode {
75 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
76 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
77 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
78 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
79 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
80 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
81 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
82 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
83 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
84 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
85 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
86 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
87 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
88 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
89 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
90 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
91 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
92 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
93 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
94};
95
96enum omap_lcd_display_type {
97 OMAP_DSS_LCD_DISPLAY_STN,
98 OMAP_DSS_LCD_DISPLAY_TFT,
99};
100
101enum omap_dss_load_mode {
102 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
103 OMAP_DSS_LOAD_CLUT_ONLY = 1,
104 OMAP_DSS_LOAD_FRAME_ONLY = 2,
105 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
106};
107
108enum omap_dss_trans_key_type {
109 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
110 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
111};
112
113enum omap_rfbi_te_mode {
114 OMAP_DSS_RFBI_TE_MODE_1 = 1,
115 OMAP_DSS_RFBI_TE_MODE_2 = 2,
116};
117
118enum omap_panel_config {
119 OMAP_DSS_LCD_IVS = 1<<0,
120 OMAP_DSS_LCD_IHS = 1<<1,
121 OMAP_DSS_LCD_IPC = 1<<2,
122 OMAP_DSS_LCD_IEO = 1<<3,
123 OMAP_DSS_LCD_RF = 1<<4,
124 OMAP_DSS_LCD_ONOFF = 1<<5,
125
126 OMAP_DSS_LCD_TFT = 1<<20,
127};
128
129enum omap_dss_venc_type {
130 OMAP_DSS_VENC_TYPE_COMPOSITE,
131 OMAP_DSS_VENC_TYPE_SVIDEO,
132};
133
134enum omap_display_caps {
135 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
136 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
137};
138
139enum omap_dss_update_mode {
140 OMAP_DSS_UPDATE_DISABLED = 0,
141 OMAP_DSS_UPDATE_AUTO,
142 OMAP_DSS_UPDATE_MANUAL,
143};
144
145enum omap_dss_display_state {
146 OMAP_DSS_DISPLAY_DISABLED = 0,
147 OMAP_DSS_DISPLAY_ACTIVE,
148 OMAP_DSS_DISPLAY_SUSPENDED,
149};
150
151/* XXX perhaps this should be removed */
152enum omap_dss_overlay_managers {
153 OMAP_DSS_OVL_MGR_LCD,
154 OMAP_DSS_OVL_MGR_TV,
155 OMAP_DSS_OVL_MGR_LCD2,
156};
157
158enum omap_dss_rotation_type {
159 OMAP_DSS_ROT_DMA = 0,
160 OMAP_DSS_ROT_VRFB = 1,
161};
162
163/* clockwise rotation angle */
164enum omap_dss_rotation_angle {
165 OMAP_DSS_ROT_0 = 0,
166 OMAP_DSS_ROT_90 = 1,
167 OMAP_DSS_ROT_180 = 2,
168 OMAP_DSS_ROT_270 = 3,
169};
170
171enum omap_overlay_caps {
172 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
173 OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
174};
175
176enum omap_overlay_manager_caps {
177 OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
178};
179
180enum omap_dss_clk_source {
181 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
182 * OMAP4: DSS_FCLK */
183 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
184 * OMAP4: PLL1_CLK1 */
185 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
186 * OMAP4: PLL1_CLK2 */
187 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
188 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
189};
190
191/* RFBI */
192
193struct rfbi_timings {
194 int cs_on_time;
195 int cs_off_time;
196 int we_on_time;
197 int we_off_time;
198 int re_on_time;
199 int re_off_time;
200 int we_cycle_time;
201 int re_cycle_time;
202 int cs_pulse_width;
203 int access_time;
204
205 int clk_div;
206
207 u32 tim[5]; /* set by rfbi_convert_timings() */
208
209 int converted;
210};
211
212void omap_rfbi_write_command(const void *buf, u32 len);
213void omap_rfbi_read_data(void *buf, u32 len);
214void omap_rfbi_write_data(const void *buf, u32 len);
215void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
216 u16 x, u16 y,
217 u16 w, u16 h);
218int omap_rfbi_enable_te(bool enable, unsigned line);
219int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
220 unsigned hs_pulse_time, unsigned vs_pulse_time,
221 int hs_pol_inv, int vs_pol_inv, int extif_div);
222void rfbi_bus_lock(void);
223void rfbi_bus_unlock(void);
224
225/* DSI */
226void dsi_bus_lock(struct omap_dss_device *dssdev);
227void dsi_bus_unlock(struct omap_dss_device *dssdev);
228int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
229 int len);
230int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
231 u8 dcs_cmd);
232int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
233 u8 param);
234int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
235 u8 *data, int len);
236int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
237 u8 *buf, int buflen);
238int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
239 u8 *data);
240int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
241 u8 *data1, u8 *data2);
242int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
243 u16 len);
244int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
245int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
246
247/* Board specific data */
248struct omap_dss_board_info {
249 int (*get_last_off_on_transaction_id)(struct device *dev);
250 int num_devices;
251 struct omap_dss_device **devices;
252 struct omap_dss_device *default_device;
253 void (*dsi_mux_pads)(bool enable);
254};
255
256#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
257/* Init with the board info */
258extern int omap_display_init(struct omap_dss_board_info *board_data);
259#else
260static inline int omap_display_init(struct omap_dss_board_info *board_data)
261{
262 return 0;
263}
264#endif
265
266struct omap_display_platform_data {
267 struct omap_dss_board_info *board_data;
268 /* TODO: Additional members to be added when PM is considered */
269
270 bool (*opt_clock_available)(const char *clk_role);
271};
272
273struct omap_video_timings {
274 /* Unit: pixels */
275 u16 x_res;
276 /* Unit: pixels */
277 u16 y_res;
278 /* Unit: KHz */
279 u32 pixel_clock;
280 /* Unit: pixel clocks */
281 u16 hsw; /* Horizontal synchronization pulse width */
282 /* Unit: pixel clocks */
283 u16 hfp; /* Horizontal front porch */
284 /* Unit: pixel clocks */
285 u16 hbp; /* Horizontal back porch */
286 /* Unit: line clocks */
287 u16 vsw; /* Vertical synchronization pulse width */
288 /* Unit: line clocks */
289 u16 vfp; /* Vertical front porch */
290 /* Unit: line clocks */
291 u16 vbp; /* Vertical back porch */
292};
293
294#ifdef CONFIG_OMAP2_DSS_VENC
295/* Hardcoded timings for tv modes. Venc only uses these to
296 * identify the mode, and does not actually use the configs
297 * itself. However, the configs should be something that
298 * a normal monitor can also show */
299extern const struct omap_video_timings omap_dss_pal_timings;
300extern const struct omap_video_timings omap_dss_ntsc_timings;
301#endif
302
303struct omap_overlay_info {
304 bool enabled;
305
306 u32 paddr;
307 void __iomem *vaddr;
308 u32 p_uv_addr; /* for NV12 format */
309 u16 screen_width;
310 u16 width;
311 u16 height;
312 enum omap_color_mode color_mode;
313 u8 rotation;
314 enum omap_dss_rotation_type rotation_type;
315 bool mirror;
316
317 u16 pos_x;
318 u16 pos_y;
319 u16 out_width; /* if 0, out_width == width */
320 u16 out_height; /* if 0, out_height == height */
321 u8 global_alpha;
322 u8 pre_mult_alpha;
323};
324
325struct omap_overlay {
326 struct kobject kobj;
327 struct list_head list;
328
329 /* static fields */
330 const char *name;
331 int id;
332 enum omap_color_mode supported_modes;
333 enum omap_overlay_caps caps;
334
335 /* dynamic fields */
336 struct omap_overlay_manager *manager;
337 struct omap_overlay_info info;
338
339 /* if true, info has been changed, but not applied() yet */
340 bool info_dirty;
341
342 int (*set_manager)(struct omap_overlay *ovl,
343 struct omap_overlay_manager *mgr);
344 int (*unset_manager)(struct omap_overlay *ovl);
345
346 int (*set_overlay_info)(struct omap_overlay *ovl,
347 struct omap_overlay_info *info);
348 void (*get_overlay_info)(struct omap_overlay *ovl,
349 struct omap_overlay_info *info);
350
351 int (*wait_for_go)(struct omap_overlay *ovl);
352};
353
354struct omap_overlay_manager_info {
355 u32 default_color;
356
357 enum omap_dss_trans_key_type trans_key_type;
358 u32 trans_key;
359 bool trans_enabled;
360
361 bool alpha_enabled;
362};
363
364struct omap_overlay_manager {
365 struct kobject kobj;
366 struct list_head list;
367
368 /* static fields */
369 const char *name;
370 int id;
371 enum omap_overlay_manager_caps caps;
372 int num_overlays;
373 struct omap_overlay **overlays;
374 enum omap_display_type supported_displays;
375
376 /* dynamic fields */
377 struct omap_dss_device *device;
378 struct omap_overlay_manager_info info;
379
380 bool device_changed;
381 /* if true, info has been changed but not applied() yet */
382 bool info_dirty;
383
384 int (*set_device)(struct omap_overlay_manager *mgr,
385 struct omap_dss_device *dssdev);
386 int (*unset_device)(struct omap_overlay_manager *mgr);
387
388 int (*set_manager_info)(struct omap_overlay_manager *mgr,
389 struct omap_overlay_manager_info *info);
390 void (*get_manager_info)(struct omap_overlay_manager *mgr,
391 struct omap_overlay_manager_info *info);
392
393 int (*apply)(struct omap_overlay_manager *mgr);
394 int (*wait_for_go)(struct omap_overlay_manager *mgr);
395 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
396
397 int (*enable)(struct omap_overlay_manager *mgr);
398 int (*disable)(struct omap_overlay_manager *mgr);
399};
400
401struct omap_dss_device {
402 struct device dev;
403
404 enum omap_display_type type;
405
406 enum omap_channel channel;
407
408 union {
409 struct {
410 u8 data_lines;
411 } dpi;
412
413 struct {
414 u8 channel;
415 u8 data_lines;
416 } rfbi;
417
418 struct {
419 u8 datapairs;
420 } sdi;
421
422 struct {
423 u8 clk_lane;
424 u8 clk_pol;
425 u8 data1_lane;
426 u8 data1_pol;
427 u8 data2_lane;
428 u8 data2_pol;
429 u8 data3_lane;
430 u8 data3_pol;
431 u8 data4_lane;
432 u8 data4_pol;
433
434 int module;
435
436 bool ext_te;
437 u8 ext_te_gpio;
438 } dsi;
439
440 struct {
441 enum omap_dss_venc_type type;
442 bool invert_polarity;
443 } venc;
444 } phy;
445
446 struct {
447 struct {
448 struct {
449 u16 lck_div;
450 u16 pck_div;
451 enum omap_dss_clk_source lcd_clk_src;
452 } channel;
453
454 enum omap_dss_clk_source dispc_fclk_src;
455 } dispc;
456
457 struct {
458 u16 regn;
459 u16 regm;
460 u16 regm_dispc;
461 u16 regm_dsi;
462
463 u16 lp_clk_div;
464 enum omap_dss_clk_source dsi_fclk_src;
465 } dsi;
466
467 struct {
468 u16 regn;
469 u16 regm2;
470 } hdmi;
471 } clocks;
472
473 struct {
474 struct omap_video_timings timings;
475
476 int acbi; /* ac-bias pin transitions per interrupt */
477 /* Unit: line clocks */
478 int acb; /* ac-bias pin frequency */
479
480 enum omap_panel_config config;
481 } panel;
482
483 struct {
484 u8 pixel_size;
485 struct rfbi_timings rfbi_timings;
486 } ctrl;
487
488 int reset_gpio;
489
490 int max_backlight_level;
491
492 const char *name;
493
494 /* used to match device to driver */
495 const char *driver_name;
496
497 void *data;
498
499 struct omap_dss_driver *driver;
500
501 /* helper variable for driver suspend/resume */
502 bool activate_after_resume;
503
504 enum omap_display_caps caps;
505
506 struct omap_overlay_manager *manager;
507
508 enum omap_dss_display_state state;
509
510 /* platform specific */
511 int (*platform_enable)(struct omap_dss_device *dssdev);
512 void (*platform_disable)(struct omap_dss_device *dssdev);
513 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
514 int (*get_backlight)(struct omap_dss_device *dssdev);
515};
516
517struct omap_dss_driver {
518 struct device_driver driver;
519
520 int (*probe)(struct omap_dss_device *);
521 void (*remove)(struct omap_dss_device *);
522
523 int (*enable)(struct omap_dss_device *display);
524 void (*disable)(struct omap_dss_device *display);
525 int (*suspend)(struct omap_dss_device *display);
526 int (*resume)(struct omap_dss_device *display);
527 int (*run_test)(struct omap_dss_device *display, int test);
528
529 int (*set_update_mode)(struct omap_dss_device *dssdev,
530 enum omap_dss_update_mode);
531 enum omap_dss_update_mode (*get_update_mode)(
532 struct omap_dss_device *dssdev);
533
534 int (*update)(struct omap_dss_device *dssdev,
535 u16 x, u16 y, u16 w, u16 h);
536 int (*sync)(struct omap_dss_device *dssdev);
537
538 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
539 int (*get_te)(struct omap_dss_device *dssdev);
540
541 u8 (*get_rotate)(struct omap_dss_device *dssdev);
542 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
543
544 bool (*get_mirror)(struct omap_dss_device *dssdev);
545 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
546
547 int (*memory_read)(struct omap_dss_device *dssdev,
548 void *buf, size_t size,
549 u16 x, u16 y, u16 w, u16 h);
550
551 void (*get_resolution)(struct omap_dss_device *dssdev,
552 u16 *xres, u16 *yres);
553 void (*get_dimensions)(struct omap_dss_device *dssdev,
554 u32 *width, u32 *height);
555 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
556
557 int (*check_timings)(struct omap_dss_device *dssdev,
558 struct omap_video_timings *timings);
559 void (*set_timings)(struct omap_dss_device *dssdev,
560 struct omap_video_timings *timings);
561 void (*get_timings)(struct omap_dss_device *dssdev,
562 struct omap_video_timings *timings);
563
564 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
565 u32 (*get_wss)(struct omap_dss_device *dssdev);
566};
567
568int omap_dss_register_driver(struct omap_dss_driver *);
569void omap_dss_unregister_driver(struct omap_dss_driver *);
570
571void omap_dss_get_device(struct omap_dss_device *dssdev);
572void omap_dss_put_device(struct omap_dss_device *dssdev);
573#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
574struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
575struct omap_dss_device *omap_dss_find_device(void *data,
576 int (*match)(struct omap_dss_device *dssdev, void *data));
577
578int omap_dss_start_device(struct omap_dss_device *dssdev);
579void omap_dss_stop_device(struct omap_dss_device *dssdev);
580
581int omap_dss_get_num_overlay_managers(void);
582struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
583
584int omap_dss_get_num_overlays(void);
585struct omap_overlay *omap_dss_get_overlay(int num);
586
587void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
588 u16 *xres, u16 *yres);
589int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
590
591typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
592int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
593int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
594
595int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
596int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
597 unsigned long timeout);
598
599#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
600#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
601
602void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
603 bool enable);
604int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
605
606int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
607 u16 *x, u16 *y, u16 *w, u16 *h,
608 bool enlarge_update_area);
609int omap_dsi_update(struct omap_dss_device *dssdev,
610 int channel,
611 u16 x, u16 y, u16 w, u16 h,
612 void (*callback)(int, void *), void *data);
613int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
614int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
615void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
616
617int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
618void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
619 bool disconnect_lanes, bool enter_ulps);
620
621int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
622void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
623void dpi_set_timings(struct omap_dss_device *dssdev,
624 struct omap_video_timings *timings);
625int dpi_check_timings(struct omap_dss_device *dssdev,
626 struct omap_video_timings *timings);
627
628int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
629void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
630
631int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
632void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
633int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
634 u16 *x, u16 *y, u16 *w, u16 *h);
635int omap_rfbi_update(struct omap_dss_device *dssdev,
636 u16 x, u16 y, u16 w, u16 h,
637 void (*callback)(void *), void *data);
638int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
639 int data_lines);
640
641#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 14:42:56 -0500