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Diffstat (limited to 'include/asm-arm/arch-ixp4xx/ixp4xx-regs.h')
-rw-r--r--include/asm-arm/arch-ixp4xx/ixp4xx-regs.h638
1 files changed, 0 insertions, 638 deletions
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
deleted file mode 100644
index 68aca8554f5..00000000000
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ /dev/null
@@ -1,638 +0,0 @@
1/*
2 * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3 *
4 * Register definitions for IXP4xx chipset. This file contains
5 * register location and bit definitions only. Platform specific
6 * definitions and helper function declarations are in platform.h
7 * and machine-name.h.
8 *
9 * Copyright (C) 2002 Intel Corporation.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#ifndef _ASM_ARM_IXP4XX_H_
19#define _ASM_ARM_IXP4XX_H_
20
21/*
22 * IXP4xx Linux Memory Map:
23 *
24 * Phy Size Virt Description
25 * =========================================================================
26 *
27 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
28 *
29 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
30 *
31 * 0x50000000 0x10000000 ioremap'd EXP BUS
32 *
33 * 0x6000000 0x00004000 ioremap'd QMgr
34 *
35 * 0xC0000000 0x00001000 0xffbff000 PCI CFG
36 *
37 * 0xC4000000 0x00001000 0xffbfe000 EXP CFG
38 *
39 * 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
40 */
41
42/*
43 * Queue Manager
44 */
45#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
46#define IXP4XX_QMGR_REGION_SIZE (0x00004000)
47
48/*
49 * Expansion BUS Configuration registers
50 */
51#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
52#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000)
53#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
54
55/*
56 * PCI Config registers
57 */
58#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
59#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000)
60#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
61
62/*
63 * Peripheral space
64 */
65#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
66#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000)
67#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
68
69/*
70 * Debug UART
71 *
72 * This is basically a remap of UART1 into a region that is section
73 * aligned so that it * can be used with the low-level debug code.
74 */
75#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
76#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000)
77#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
78
79#define IXP4XX_EXP_CS0_OFFSET 0x00
80#define IXP4XX_EXP_CS1_OFFSET 0x04
81#define IXP4XX_EXP_CS2_OFFSET 0x08
82#define IXP4XX_EXP_CS3_OFFSET 0x0C
83#define IXP4XX_EXP_CS4_OFFSET 0x10
84#define IXP4XX_EXP_CS5_OFFSET 0x14
85#define IXP4XX_EXP_CS6_OFFSET 0x18
86#define IXP4XX_EXP_CS7_OFFSET 0x1C
87#define IXP4XX_EXP_CFG0_OFFSET 0x20
88#define IXP4XX_EXP_CFG1_OFFSET 0x24
89#define IXP4XX_EXP_CFG2_OFFSET 0x28
90#define IXP4XX_EXP_CFG3_OFFSET 0x2C
91
92/*
93 * Expansion Bus Controller registers.
94 */
95#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
96
97#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
98#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
99#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
100#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
101#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
102#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
103#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
104#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
105
106#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
107#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
108#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
109#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
110
111
112/*
113 * Peripheral Space Register Region Base Addresses
114 */
115#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
116#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
117#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
118#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
119#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
120#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
121#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
122#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
123#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
124#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
125#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
126#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
127/* ixp46X only */
128#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
129#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
130#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
131#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
132#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
133#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
134#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
135
136
137#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
138#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
139#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
140#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
141#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
142#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
143#define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
144#define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
145#define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
146#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
147#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
148#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
149/* ixp46X only */
150#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
151#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
152#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
153#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
154#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
155#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
156#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
157
158/*
159 * Constants to make it easy to access Interrupt Controller registers
160 */
161#define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */
162#define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */
163#define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
164#define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */
165#define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */
166#define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */
167#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
168#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
169
170/*
171 * IXP465-only
172 */
173#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */
174#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */
175#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */
176#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */
177#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */
178#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */
179
180
181/*
182 * Interrupt Controller Register Definitions.
183 */
184
185#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
186
187#define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
188#define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
189#define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
190#define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
191#define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
192#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
193#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
194#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
195#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
196#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
197#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
198#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
199#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
200#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
201
202/*
203 * Constants to make it easy to access GPIO registers
204 */
205#define IXP4XX_GPIO_GPOUTR_OFFSET 0x00
206#define IXP4XX_GPIO_GPOER_OFFSET 0x04
207#define IXP4XX_GPIO_GPINR_OFFSET 0x08
208#define IXP4XX_GPIO_GPISR_OFFSET 0x0C
209#define IXP4XX_GPIO_GPIT1R_OFFSET 0x10
210#define IXP4XX_GPIO_GPIT2R_OFFSET 0x14
211#define IXP4XX_GPIO_GPCLKR_OFFSET 0x18
212#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
213
214/*
215 * GPIO Register Definitions.
216 * [Only perform 32bit reads/writes]
217 */
218#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
219
220#define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
221#define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
222#define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
223#define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
224#define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
225#define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
226#define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
227#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
228
229/*
230 * GPIO register bit definitions
231 */
232
233/* Interrupt styles
234 */
235#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
236#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
237#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
238#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
239#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
240
241/*
242 * Mask used to clear interrupt styles
243 */
244#define IXP4XX_GPIO_STYLE_CLEAR 0x7
245#define IXP4XX_GPIO_STYLE_SIZE 3
246
247/*
248 * Constants to make it easy to access Timer Control/Status registers
249 */
250#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
251#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
252#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
253#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
254#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
255#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
256#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
257#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
258#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
259
260/*
261 * Operating System Timer Register Definitions.
262 */
263
264#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
265
266#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
267#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
268#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
269#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
270#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
271#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
272#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
273#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
274#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
275
276/*
277 * Timer register values and bit definitions
278 */
279#define IXP4XX_OST_ENABLE 0x00000001
280#define IXP4XX_OST_ONE_SHOT 0x00000002
281/* Low order bits of reload value ignored */
282#define IXP4XX_OST_RELOAD_MASK 0x00000003
283#define IXP4XX_OST_DISABLED 0x00000000
284#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
285#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
286#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
287#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
288#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
289
290#define IXP4XX_WDT_KEY 0x0000482E
291
292#define IXP4XX_WDT_RESET_ENABLE 0x00000001
293#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
294#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
295
296
297/*
298 * Constants to make it easy to access PCI Control/Status registers
299 */
300#define PCI_NP_AD_OFFSET 0x00
301#define PCI_NP_CBE_OFFSET 0x04
302#define PCI_NP_WDATA_OFFSET 0x08
303#define PCI_NP_RDATA_OFFSET 0x0c
304#define PCI_CRP_AD_CBE_OFFSET 0x10
305#define PCI_CRP_WDATA_OFFSET 0x14
306#define PCI_CRP_RDATA_OFFSET 0x18
307#define PCI_CSR_OFFSET 0x1c
308#define PCI_ISR_OFFSET 0x20
309#define PCI_INTEN_OFFSET 0x24
310#define PCI_DMACTRL_OFFSET 0x28
311#define PCI_AHBMEMBASE_OFFSET 0x2c
312#define PCI_AHBIOBASE_OFFSET 0x30
313#define PCI_PCIMEMBASE_OFFSET 0x34
314#define PCI_AHBDOORBELL_OFFSET 0x38
315#define PCI_PCIDOORBELL_OFFSET 0x3C
316#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
317#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
318#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
319#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
320#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
321#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
322
323/*
324 * PCI Control/Status Registers
325 */
326#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
327
328#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
329#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
330#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
331#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
332#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
333#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
334#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
335#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
336#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
337#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
338#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
339#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
340#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
341#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
342#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
343#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
344#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
345#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
346#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
347#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
348#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
349#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
350
351/*
352 * PCI register values and bit definitions
353 */
354
355/* CSR bit definitions */
356#define PCI_CSR_HOST 0x00000001
357#define PCI_CSR_ARBEN 0x00000002
358#define PCI_CSR_ADS 0x00000004
359#define PCI_CSR_PDS 0x00000008
360#define PCI_CSR_ABE 0x00000010
361#define PCI_CSR_DBT 0x00000020
362#define PCI_CSR_ASE 0x00000100
363#define PCI_CSR_IC 0x00008000
364
365/* ISR (Interrupt status) Register bit definitions */
366#define PCI_ISR_PSE 0x00000001
367#define PCI_ISR_PFE 0x00000002
368#define PCI_ISR_PPE 0x00000004
369#define PCI_ISR_AHBE 0x00000008
370#define PCI_ISR_APDC 0x00000010
371#define PCI_ISR_PADC 0x00000020
372#define PCI_ISR_ADB 0x00000040
373#define PCI_ISR_PDB 0x00000080
374
375/* INTEN (Interrupt Enable) Register bit definitions */
376#define PCI_INTEN_PSE 0x00000001
377#define PCI_INTEN_PFE 0x00000002
378#define PCI_INTEN_PPE 0x00000004
379#define PCI_INTEN_AHBE 0x00000008
380#define PCI_INTEN_APDC 0x00000010
381#define PCI_INTEN_PADC 0x00000020
382#define PCI_INTEN_ADB 0x00000040
383#define PCI_INTEN_PDB 0x00000080
384
385/*
386 * Shift value for byte enable on NP cmd/byte enable register
387 */
388#define IXP4XX_PCI_NP_CBE_BESL 4
389
390/*
391 * PCI commands supported by NP access unit
392 */
393#define NP_CMD_IOREAD 0x2
394#define NP_CMD_IOWRITE 0x3
395#define NP_CMD_CONFIGREAD 0xa
396#define NP_CMD_CONFIGWRITE 0xb
397#define NP_CMD_MEMREAD 0x6
398#define NP_CMD_MEMWRITE 0x7
399
400/*
401 * Constants for CRP access into local config space
402 */
403#define CRP_AD_CBE_BESL 20
404#define CRP_AD_CBE_WRITE 0x00010000
405
406
407/*
408 * USB Device Controller
409 *
410 * These are used by the USB gadget driver, so they don't follow the
411 * IXP4XX_ naming convetions.
412 *
413 */
414# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
415
416/* UDC Undocumented - Reserved1 */
417#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
418/* UDC Undocumented - Reserved2 */
419#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
420/* UDC Undocumented - Reserved3 */
421#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
422/* UDC Control Register */
423#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
424/* UDC Endpoint 0 Control/Status Register */
425#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
426/* UDC Endpoint 1 (IN) Control/Status Register */
427#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
428/* UDC Endpoint 2 (OUT) Control/Status Register */
429#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
430/* UDC Endpoint 3 (IN) Control/Status Register */
431#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
432/* UDC Endpoint 4 (OUT) Control/Status Register */
433#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
434/* UDC Endpoint 5 (Interrupt) Control/Status Register */
435#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
436/* UDC Endpoint 6 (IN) Control/Status Register */
437#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
438/* UDC Endpoint 7 (OUT) Control/Status Register */
439#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
440/* UDC Endpoint 8 (IN) Control/Status Register */
441#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
442/* UDC Endpoint 9 (OUT) Control/Status Register */
443#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
444/* UDC Endpoint 10 (Interrupt) Control/Status Register */
445#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
446/* UDC Endpoint 11 (IN) Control/Status Register */
447#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
448/* UDC Endpoint 12 (OUT) Control/Status Register */
449#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
450/* UDC Endpoint 13 (IN) Control/Status Register */
451#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
452/* UDC Endpoint 14 (OUT) Control/Status Register */
453#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
454/* UDC Endpoint 15 (Interrupt) Control/Status Register */
455#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
456/* UDC Frame Number Register High */
457#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
458/* UDC Frame Number Register Low */
459#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
460/* UDC Byte Count Reg 2 */
461#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
462/* UDC Byte Count Reg 4 */
463#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
464/* UDC Byte Count Reg 7 */
465#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
466/* UDC Byte Count Reg 9 */
467#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
468/* UDC Byte Count Reg 12 */
469#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
470/* UDC Byte Count Reg 14 */
471#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
472/* UDC Endpoint 0 Data Register */
473#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
474/* UDC Endpoint 1 Data Register */
475#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
476/* UDC Endpoint 2 Data Register */
477#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
478/* UDC Endpoint 3 Data Register */
479#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
480/* UDC Endpoint 4 Data Register */
481#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
482/* UDC Endpoint 5 Data Register */
483#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
484/* UDC Endpoint 6 Data Register */
485#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
486/* UDC Endpoint 7 Data Register */
487#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
488/* UDC Endpoint 8 Data Register */
489#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
490/* UDC Endpoint 9 Data Register */
491#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
492/* UDC Endpoint 10 Data Register */
493#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
494/* UDC Endpoint 11 Data Register */
495#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
496/* UDC Endpoint 12 Data Register */
497#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
498/* UDC Endpoint 13 Data Register */
499#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
500/* UDC Endpoint 14 Data Register */
501#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
502/* UDC Endpoint 15 Data Register */
503#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
504/* UDC Interrupt Control Register 0 */
505#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
506/* UDC Interrupt Control Register 1 */
507#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
508/* UDC Status Interrupt Register 0 */
509#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
510/* UDC Status Interrupt Register 1 */
511#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
512
513#define UDCCR_UDE (1 << 0) /* UDC enable */
514#define UDCCR_UDA (1 << 1) /* UDC active */
515#define UDCCR_RSM (1 << 2) /* Device resume */
516#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
517#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
518#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
519#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
520#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
521
522#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
523#define UDCCS0_IPR (1 << 1) /* IN packet ready */
524#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
525#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
526#define UDCCS0_SST (1 << 4) /* Sent stall */
527#define UDCCS0_FST (1 << 5) /* Force stall */
528#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
529#define UDCCS0_SA (1 << 7) /* Setup active */
530
531#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
532#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
533#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
534#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
535#define UDCCS_BI_SST (1 << 4) /* Sent stall */
536#define UDCCS_BI_FST (1 << 5) /* Force stall */
537#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
538
539#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
540#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
541#define UDCCS_BO_DME (1 << 3) /* DMA enable */
542#define UDCCS_BO_SST (1 << 4) /* Sent stall */
543#define UDCCS_BO_FST (1 << 5) /* Force stall */
544#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
545#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
546
547#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
548#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
549#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
550#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
551#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
552
553#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
554#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
555#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
556#define UDCCS_IO_DME (1 << 3) /* DMA enable */
557#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
558#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
559
560#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
561#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
562#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
563#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
564#define UDCCS_INT_SST (1 << 4) /* Sent stall */
565#define UDCCS_INT_FST (1 << 5) /* Force stall */
566#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
567
568#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
569#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
570#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
571#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
572#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
573#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
574#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
575#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
576
577#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
578#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
579#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
580#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
581#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
582#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
583#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
584#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
585
586#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
587#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
588#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
589#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
590#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
591#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
592#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
593#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
594
595#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
596#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
597#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
598#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
599#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
600#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
601#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
602#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
603
604#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
605
606/* "fuse" bits of IXP_EXP_CFG2 */
607#define IXP4XX_FEATURE_RCOMP (1 << 0)
608#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
609#define IXP4XX_FEATURE_HASH (1 << 2)
610#define IXP4XX_FEATURE_AES (1 << 3)
611#define IXP4XX_FEATURE_DES (1 << 4)
612#define IXP4XX_FEATURE_HDLC (1 << 5)
613#define IXP4XX_FEATURE_AAL (1 << 6)
614#define IXP4XX_FEATURE_HSS (1 << 7)
615#define IXP4XX_FEATURE_UTOPIA (1 << 8)
616#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
617#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
618#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
619#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
620#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
621#define IXP4XX_FEATURE_PCI (1 << 14)
622#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
623#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
624#define IXP4XX_FEATURE_USB_HOST (1 << 18)
625#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
626#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
627#define IXP4XX_FEATURE_RSA (1 << 21)
628#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
629#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
630
631#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
632 IXP4XX_FEATURE_USB_HOST | \
633 IXP4XX_FEATURE_NPEA_ETH | \
634 IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
635 IXP4XX_FEATURE_RSA | \
636 IXP4XX_FEATURE_XSCALE_MAX_FREQ)
637
638#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 10:15:22 -0500