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path: root/drivers/video/omap2/dss/dsi.c
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Diffstat (limited to 'drivers/video/omap2/dss/dsi.c')
-rw-r--r--drivers/video/omap2/dss/dsi.c27
1 files changed, 15 insertions, 12 deletions
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index aa4f7a5fae2..ddf3a056082 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -792,7 +792,8 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
792} 792}
793 793
794/* calculate clock rates using dividers in cinfo */ 794/* calculate clock rates using dividers in cinfo */
795static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo) 795static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
796 struct dsi_clock_info *cinfo)
796{ 797{
797 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX) 798 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
798 return -EINVAL; 799 return -EINVAL;
@@ -812,7 +813,7 @@ static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
812 * with DSS2_FCK source also */ 813 * with DSS2_FCK source also */
813 cinfo->highfreq = 0; 814 cinfo->highfreq = 0;
814 } else { 815 } else {
815 cinfo->clkin = dispc_pclk_rate(); 816 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
816 817
817 if (cinfo->clkin < 32000000) 818 if (cinfo->clkin < 32000000)
818 cinfo->highfreq = 0; 819 cinfo->highfreq = 0;
@@ -1206,8 +1207,8 @@ void dsi_dump_clocks(struct seq_file *s)
1206 1207
1207 seq_printf(s, "VP_CLK\t\t%lu\n" 1208 seq_printf(s, "VP_CLK\t\t%lu\n"
1208 "VP_PCLK\t\t%lu\n", 1209 "VP_PCLK\t\t%lu\n",
1209 dispc_lclk_rate(), 1210 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1210 dispc_pclk_rate()); 1211 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
1211 1212
1212 enable_clocks(0); 1213 enable_clocks(0);
1213} 1214}
@@ -2888,7 +2889,7 @@ int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
2888 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { 2889 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2889 dss_setup_partial_planes(dssdev, x, y, w, h, 2890 dss_setup_partial_planes(dssdev, x, y, w, h,
2890 enlarge_update_area); 2891 enlarge_update_area);
2891 dispc_set_lcd_size(*w, *h); 2892 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
2892 } 2893 }
2893 2894
2894 return 0; 2895 return 0;
@@ -2947,12 +2948,14 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2947 return r; 2948 return r;
2948 } 2949 }
2949 2950
2950 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT); 2951 dispc_set_lcd_display_type(dssdev->manager->id,
2952 OMAP_DSS_LCD_DISPLAY_TFT);
2951 2953
2952 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI); 2954 dispc_set_parallel_interface_mode(dssdev->manager->id,
2953 dispc_enable_fifohandcheck(1); 2955 OMAP_DSS_PARALLELMODE_DSI);
2956 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
2954 2957
2955 dispc_set_tft_data_lines(dssdev->ctrl.pixel_size); 2958 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
2956 2959
2957 { 2960 {
2958 struct omap_video_timings timings = { 2961 struct omap_video_timings timings = {
@@ -2964,7 +2967,7 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2964 .vbp = 0, 2967 .vbp = 0,
2965 }; 2968 };
2966 2969
2967 dispc_set_lcd_timings(&timings); 2970 dispc_set_lcd_timings(dssdev->manager->id, &timings);
2968 } 2971 }
2969 2972
2970 return 0; 2973 return 0;
@@ -2987,7 +2990,7 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
2987 cinfo.regm = dssdev->phy.dsi.div.regm; 2990 cinfo.regm = dssdev->phy.dsi.div.regm;
2988 cinfo.regm3 = dssdev->phy.dsi.div.regm3; 2991 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
2989 cinfo.regm4 = dssdev->phy.dsi.div.regm4; 2992 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
2990 r = dsi_calc_clock_rates(&cinfo); 2993 r = dsi_calc_clock_rates(dssdev, &cinfo);
2991 if (r) { 2994 if (r) {
2992 DSSERR("Failed to calc dsi clocks\n"); 2995 DSSERR("Failed to calc dsi clocks\n");
2993 return r; 2996 return r;
@@ -3019,7 +3022,7 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3019 return r; 3022 return r;
3020 } 3023 }
3021 3024
3022 r = dispc_set_clock_div(&dispc_cinfo); 3025 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3023 if (r) { 3026 if (r) {
3024 DSSERR("Failed to set dispc clocks\n"); 3027 DSSERR("Failed to set dispc clocks\n");
3025 return r; 3028 return r;