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path: root/drivers/gpu/pvr/sgx/sgxreset.c
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Diffstat (limited to 'drivers/gpu/pvr/sgx/sgxreset.c')
-rw-r--r--drivers/gpu/pvr/sgx/sgxreset.c499
1 files changed, 499 insertions, 0 deletions
diff --git a/drivers/gpu/pvr/sgx/sgxreset.c b/drivers/gpu/pvr/sgx/sgxreset.c
new file mode 100644
index 00000000000..ee9f572ea74
--- /dev/null
+++ b/drivers/gpu/pvr/sgx/sgxreset.c
@@ -0,0 +1,499 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#include "sgxdefs.h"
28#include "sgxmmu.h"
29#include "services_headers.h"
30#include "sgxinfokm.h"
31#include "sgxconfig.h"
32
33#include "pdump_km.h"
34
35
36static IMG_VOID SGXResetSoftReset(PVRSRV_SGXDEV_INFO *psDevInfo,
37 IMG_BOOL bResetBIF,
38 IMG_UINT32 ui32PDUMPFlags,
39 IMG_BOOL bPDump)
40{
41 IMG_UINT32 ui32SoftResetRegVal;
42
43#if defined(SGX_FEATURE_MP)
44 ui32SoftResetRegVal =
45 EUR_CR_MASTER_SOFT_RESET_IPF_RESET_MASK |
46 EUR_CR_MASTER_SOFT_RESET_DPM_RESET_MASK |
47 EUR_CR_MASTER_SOFT_RESET_VDM_RESET_MASK;
48
49#if defined(SGX_FEATURE_PTLA)
50 ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_MASK;
51#endif
52#if defined(SGX_FEATURE_SYSTEM_CACHE)
53 ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_SLC_RESET_MASK;
54#endif
55
56 if (bResetBIF)
57 {
58 ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_BIF_RESET_MASK;
59 }
60
61 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32SoftResetRegVal);
62 if (bPDump)
63 {
64 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32SoftResetRegVal, ui32PDUMPFlags);
65 }
66#endif
67
68 ui32SoftResetRegVal =
69
70 EUR_CR_SOFT_RESET_DPM_RESET_MASK |
71 EUR_CR_SOFT_RESET_TA_RESET_MASK |
72 EUR_CR_SOFT_RESET_USE_RESET_MASK |
73 EUR_CR_SOFT_RESET_ISP_RESET_MASK |
74 EUR_CR_SOFT_RESET_TSP_RESET_MASK;
75
76#ifdef EUR_CR_SOFT_RESET_TWOD_RESET_MASK
77 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_TWOD_RESET_MASK;
78#endif
79#if defined(EUR_CR_SOFT_RESET_TE_RESET_MASK)
80 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_TE_RESET_MASK;
81#endif
82#if defined(EUR_CR_SOFT_RESET_MTE_RESET_MASK)
83 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_MTE_RESET_MASK;
84#endif
85#if defined(EUR_CR_SOFT_RESET_ISP2_RESET_MASK)
86 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_ISP2_RESET_MASK;
87#endif
88#if defined(EUR_CR_SOFT_RESET_PDS_RESET_MASK)
89 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_PDS_RESET_MASK;
90#endif
91#if defined(EUR_CR_SOFT_RESET_PBE_RESET_MASK)
92 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_PBE_RESET_MASK;
93#endif
94#if defined(EUR_CR_SOFT_RESET_CACHEL2_RESET_MASK)
95 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_CACHEL2_RESET_MASK;
96#endif
97#if defined(EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK)
98 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK;
99#endif
100#if defined(EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK)
101 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK;
102#endif
103#if defined(EUR_CR_SOFT_RESET_MADD_RESET_MASK)
104 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_MADD_RESET_MASK;
105#endif
106#if defined(EUR_CR_SOFT_RESET_ITR_RESET_MASK)
107 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_ITR_RESET_MASK;
108#endif
109#if defined(EUR_CR_SOFT_RESET_TEX_RESET_MASK)
110 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_TEX_RESET_MASK;
111#endif
112#if defined(EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK)
113 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK;
114#endif
115#if defined(EUR_CR_SOFT_RESET_VDM_RESET_MASK)
116 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_VDM_RESET_MASK;
117#endif
118#if defined(EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK)
119 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK;
120#endif
121#if defined(EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK)
122 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK;
123#endif
124
125#if !defined(PDUMP)
126 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
127#endif
128
129 if (bResetBIF)
130 {
131 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_BIF_RESET_MASK;
132 }
133
134 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32SoftResetRegVal);
135 if (bPDump)
136 {
137 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32SoftResetRegVal, ui32PDUMPFlags);
138 }
139}
140
141
142static IMG_VOID SGXResetSleep(PVRSRV_SGXDEV_INFO *psDevInfo,
143 IMG_UINT32 ui32PDUMPFlags,
144 IMG_BOOL bPDump)
145{
146#if !defined(PDUMP)
147 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
148#endif
149
150
151 OSWaitus(100 * 1000000 / psDevInfo->ui32CoreClockSpeed);
152 if (bPDump)
153 {
154 PDUMPIDLWITHFLAGS(30, ui32PDUMPFlags);
155#if defined(PDUMP)
156 PDumpRegRead(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32PDUMPFlags);
157#endif
158 }
159
160}
161
162
163static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo,
164 IMG_UINT32 ui32PDUMPFlags,
165 IMG_BOOL bPDump)
166{
167 IMG_UINT32 ui32RegVal;
168
169
170#if defined(EUR_CR_BIF_CTRL_INVAL)
171 ui32RegVal = EUR_CR_BIF_CTRL_INVAL_ALL_MASK;
172 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, ui32RegVal);
173 if (bPDump)
174 {
175 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL_INVAL, ui32RegVal, ui32PDUMPFlags);
176 }
177#else
178 ui32RegVal = EUR_CR_BIF_CTRL_INVALDC_MASK;
179 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
180 if (bPDump)
181 {
182 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
183 }
184
185 ui32RegVal = 0;
186 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
187 if (bPDump)
188 {
189 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
190 }
191#endif
192 SGXResetSleep(psDevInfo, ui32PDUMPFlags, bPDump);
193
194#if !defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
195 {
196
197
198
199 if (PollForValueKM((IMG_UINT32 *)((IMG_UINT8*)psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
200 0,
201 EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
202 MAX_HW_TIME_US/WAIT_TRY_COUNT,
203 WAIT_TRY_COUNT) != PVRSRV_OK)
204 {
205 PVR_DPF((PVR_DBG_ERROR,"Wait for DC invalidate failed."));
206 PVR_DBG_BREAK;
207 }
208
209 if (bPDump)
210 {
211 PDUMPREGPOLWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_REQ_STAT, 0, EUR_CR_BIF_MEM_REQ_STAT_READS_MASK, ui32PDUMPFlags);
212 }
213 }
214#endif
215}
216
217
218IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
219 IMG_BOOL bHardwareRecovery,
220 IMG_UINT32 ui32PDUMPFlags)
221{
222 IMG_UINT32 ui32RegVal;
223#if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK)
224 const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK;
225#else
226 const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
227#endif
228
229#ifndef PDUMP
230 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
231#endif
232
233 psDevInfo->ui32NumResets++;
234
235 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n");
236
237#if defined(FIX_HW_BRN_23944)
238
239 ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
240 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
241 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
242
243 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
244
245 ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
246 if (ui32RegVal & ui32BifFaultMask)
247 {
248
249 ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK | EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK;
250 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
251 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
252
253 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
254
255 ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
256 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
257 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
258
259 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
260 }
261#endif
262
263
264 SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_TRUE);
265
266 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
267
268
269
270#if defined(SGX_FEATURE_36BIT_MMU)
271
272 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK);
273 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags);
274#endif
275
276 ui32RegVal = 0;
277 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
278 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
279#if defined(SGX_FEATURE_MP)
280 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_CTRL, ui32RegVal);
281 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
282#endif
283#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
284 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK_SET, ui32RegVal);
285 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK_SET, ui32RegVal, ui32PDUMPFlags);
286 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
287 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
288#endif
289
290 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
291 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags);
292
293#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
294 {
295 IMG_UINT32 ui32DirList, ui32DirListReg;
296
297 for (ui32DirList = 1;
298 ui32DirList < SGX_FEATURE_BIF_NUM_DIRLISTS;
299 ui32DirList++)
300 {
301 ui32DirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (ui32DirList - 1);
302 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32DirListReg, ui32RegVal);
303 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, ui32DirListReg, ui32RegVal, ui32PDUMPFlags);
304 }
305 }
306#endif
307
308#if defined(EUR_CR_BIF_MEM_ARB_CONFIG)
309
310
311 ui32RegVal = (12UL << EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT) |
312 (7UL << EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT) |
313 (12UL << EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT);
314 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal);
315 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal, ui32PDUMPFlags);
316#endif
317
318#if defined(SGX_FEATURE_SYSTEM_CACHE)
319#if defined(SGX_FEATURE_MP)
320 #if defined(SGX_BYPASS_SYSTEM_CACHE)
321 #error SGX_BYPASS_SYSTEM_CACHE not supported
322 #else
323 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK |
324 (0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT);
325 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
326 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
327
328 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
329 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
330 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
331 #endif
332#else
333 #if defined(SGX_BYPASS_SYSTEM_CACHE)
334
335 ui32RegVal = MNE_CR_CTRL_BYPASS_ALL_MASK;
336 #else
337 #if defined(FIX_HW_BRN_26620)
338 ui32RegVal = 0;
339 #else
340
341 ui32RegVal = MNE_CR_CTRL_BYP_CC_MASK;
342 #endif
343 #endif
344 OSWriteHWReg(psDevInfo->pvRegsBaseKM, MNE_CR_CTRL, ui32RegVal);
345 PDUMPREG(SGX_PDUMPREG_NAME, MNE_CR_CTRL, ui32RegVal);
346#endif
347#endif
348
349 if (bHardwareRecovery)
350 {
351
352
353
354
355
356
357
358 ui32RegVal = (IMG_UINT32)psDevInfo->sBIFResetPDDevPAddr.uiAddr;
359 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
360
361 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
362
363
364 SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
365 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
366
367 SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
368
369
370
371 for (;;)
372 {
373 IMG_UINT32 ui32BifIntStat = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
374 IMG_DEV_VIRTADDR sBifFault;
375 IMG_UINT32 ui32PDIndex, ui32PTIndex;
376
377 if ((ui32BifIntStat & ui32BifFaultMask) == 0)
378 {
379 break;
380 }
381
382
383
384
385 sBifFault.uiAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_FAULT);
386 PVR_DPF((PVR_DBG_WARNING, "SGXReset: Page fault 0x%x/0x%x", ui32BifIntStat, sBifFault.uiAddr));
387 ui32PDIndex = sBifFault.uiAddr >> (SGX_MMU_PAGE_SHIFT + SGX_MMU_PT_SHIFT);
388 ui32PTIndex = (sBifFault.uiAddr & SGX_MMU_PT_MASK) >> SGX_MMU_PAGE_SHIFT;
389
390
391 SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_FALSE);
392
393
394 psDevInfo->pui32BIFResetPD[ui32PDIndex] = (psDevInfo->sBIFResetPTDevPAddr.uiAddr
395 >>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
396 | SGX_MMU_PDE_PAGE_SIZE_4K
397 | SGX_MMU_PDE_VALID;
398 psDevInfo->pui32BIFResetPT[ui32PTIndex] = (psDevInfo->sBIFResetPageDevPAddr.uiAddr
399 >>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
400 | SGX_MMU_PTE_VALID;
401
402
403 ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
404 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32RegVal);
405 ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
406 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32RegVal);
407
408 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
409
410
411 SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_FALSE);
412 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
413
414
415 SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
416
417
418 psDevInfo->pui32BIFResetPD[ui32PDIndex] = 0;
419 psDevInfo->pui32BIFResetPT[ui32PTIndex] = 0;
420 }
421 }
422 else
423 {
424
425 SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
426 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
427 }
428
429
430
431 #if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
432
433 ui32RegVal = (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT);
434
435 #if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
436
437 ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_2D_SHIFT);
438 #endif
439
440 #if defined(FIX_HW_BRN_23410)
441
442 ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_TA_SHIFT);
443 #endif
444
445 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
446 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
447 #endif
448
449 {
450 IMG_UINT32 ui32EDMDirListReg;
451
452
453 #if (SGX_BIF_DIR_LIST_INDEX_EDM == 0)
454 ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE0;
455 #else
456
457 ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1);
458 #endif
459
460#if defined(FIX_HW_BRN_28011)
461 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT);
462 PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, EUR_CR_BIF_DIR_LIST_BASE0, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
463#endif
464
465 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32EDMDirListReg, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT);
466 PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, ui32EDMDirListReg, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
467 }
468
469#if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
470
471 #if ((SGX_2D_HEAP_BASE & ~EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK) != 0)
472 #error "SGXReset: SGX_2D_HEAP_BASE doesn't match EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK alignment"
473 #endif
474
475 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_TWOD_REQ_BASE, SGX_2D_HEAP_BASE);
476 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_TWOD_REQ_BASE, SGX_2D_HEAP_BASE, ui32PDUMPFlags);
477#endif
478
479
480 SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
481
482 PVR_DPF((PVR_DBG_MESSAGE,"Soft Reset of SGX"));
483
484
485 ui32RegVal = 0;
486#if defined(SGX_FEATURE_MP)
487 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
488 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
489#endif
490 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32RegVal);
491 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
492
493
494 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
495
496 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX reset sequence\r\n");
497}
498
499
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 21:50:44 -0400