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path: root/drivers/gpu/pvr/sgx/sgxinit.c
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Diffstat (limited to 'drivers/gpu/pvr/sgx/sgxinit.c')
-rw-r--r--drivers/gpu/pvr/sgx/sgxinit.c441
1 files changed, 294 insertions, 147 deletions
diff --git a/drivers/gpu/pvr/sgx/sgxinit.c b/drivers/gpu/pvr/sgx/sgxinit.c
index 3872102029f..e73c067bd4f 100644
--- a/drivers/gpu/pvr/sgx/sgxinit.c
+++ b/drivers/gpu/pvr/sgx/sgxinit.c
@@ -51,6 +51,7 @@
51 51
52#include "lists.h" 52#include "lists.h"
53#include "srvkm.h" 53#include "srvkm.h"
54#include "ttrace.h"
54 55
55#define VAR(x) #x 56#define VAR(x) #x
56 57
@@ -74,7 +75,8 @@ IMG_BOOL SGX_ISRHandler(IMG_VOID *pvData);
74 75
75static 76static
76PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo, 77PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo,
77 PVRSRV_DEVICE_NODE *psDeviceNode); 78 PVRSRV_DEVICE_NODE *psDeviceNode,
79 IMG_HANDLE hDevMemContext);
78#if defined(PDUMP) 80#if defined(PDUMP)
79static 81static
80PVRSRV_ERROR SGXResetPDump(PVRSRV_DEVICE_NODE *psDeviceNode); 82PVRSRV_ERROR SGXResetPDump(PVRSRV_DEVICE_NODE *psDeviceNode);
@@ -111,7 +113,11 @@ static IMG_UINT32 DeinitDevInfo(PVRSRV_SGXDEV_INFO *psDevInfo)
111 113
112static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc, 114static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
113 PVRSRV_DEVICE_NODE *psDeviceNode, 115 PVRSRV_DEVICE_NODE *psDeviceNode,
116#if defined (SUPPORT_SID_INTERFACE)
117 SGX_BRIDGE_INIT_INFO_KM *psInitInfo)
118#else
114 SGX_BRIDGE_INIT_INFO *psInitInfo) 119 SGX_BRIDGE_INIT_INFO *psInitInfo)
120#endif
115{ 121{
116 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; 122 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
117 PVRSRV_ERROR eError; 123 PVRSRV_ERROR eError;
@@ -135,7 +141,7 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
135 141
136 psDevInfo->psKernelSGXTA3DCtlMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXTA3DCtlMemInfo; 142 psDevInfo->psKernelSGXTA3DCtlMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXTA3DCtlMemInfo;
137 143
138 psDevInfo->psKernelSGXMiscMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXMiscMemInfo; 144 psDevInfo->psKernelSGXMiscMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXMiscMemInfo;
139 145
140#if defined(SGX_SUPPORT_HWPROFILING) 146#if defined(SGX_SUPPORT_HWPROFILING)
141 psDevInfo->psKernelHWProfilingMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelHWProfilingMemInfo; 147 psDevInfo->psKernelHWProfilingMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelHWProfilingMemInfo;
@@ -151,6 +157,10 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
151#if defined(FIX_HW_BRN_29823) 157#if defined(FIX_HW_BRN_29823)
152 psDevInfo->psKernelDummyTermStreamMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelDummyTermStreamMemInfo; 158 psDevInfo->psKernelDummyTermStreamMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelDummyTermStreamMemInfo;
153#endif 159#endif
160#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31425)
161 psDevInfo->psKernelVDMSnapShotBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMSnapShotBufferMemInfo;
162 psDevInfo->psKernelVDMCtrlStreamBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMCtrlStreamBufferMemInfo;
163#endif
154#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) 164#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
155 psDevInfo->psKernelEDMStatusBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelEDMStatusBufferMemInfo; 165 psDevInfo->psKernelEDMStatusBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelEDMStatusBufferMemInfo;
156#endif 166#endif
@@ -168,7 +178,7 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
168 178
169 179
170 180
171 eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 181 eError = OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
172 sizeof(PVRSRV_SGX_CCB_INFO), 182 sizeof(PVRSRV_SGX_CCB_INFO),
173 (IMG_VOID **)&psKernelCCBInfo, 0, 183 (IMG_VOID **)&psKernelCCBInfo, 0,
174 "SGX Circular Command Buffer Info"); 184 "SGX Circular Command Buffer Info");
@@ -198,6 +208,8 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
198 208
199 psDevInfo->ui32EDMTaskReg0 = psInitInfo->ui32EDMTaskReg0; 209 psDevInfo->ui32EDMTaskReg0 = psInitInfo->ui32EDMTaskReg0;
200 psDevInfo->ui32EDMTaskReg1 = psInitInfo->ui32EDMTaskReg1; 210 psDevInfo->ui32EDMTaskReg1 = psInitInfo->ui32EDMTaskReg1;
211 psDevInfo->ui32ClkGateCtl = psInitInfo->ui32ClkGateCtl;
212 psDevInfo->ui32ClkGateCtl2 = psInitInfo->ui32ClkGateCtl2;
201 psDevInfo->ui32ClkGateStatusReg = psInitInfo->ui32ClkGateStatusReg; 213 psDevInfo->ui32ClkGateStatusReg = psInitInfo->ui32ClkGateStatusReg;
202 psDevInfo->ui32ClkGateStatusMask = psInitInfo->ui32ClkGateStatusMask; 214 psDevInfo->ui32ClkGateStatusMask = psInitInfo->ui32ClkGateStatusMask;
203#if defined(SGX_FEATURE_MP) 215#if defined(SGX_FEATURE_MP)
@@ -277,6 +289,12 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
277 IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended(); 289 IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended();
278#endif 290#endif
279 291
292#if defined(SGX_FEATURE_MP)
293
294#else
295 SGXInitClocks(psDevInfo, PDUMP_FLAGS_CONTINUOUS);
296#endif
297
280 298
281 299
282 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "SGX initialisation script part 1\n"); 300 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "SGX initialisation script part 1\n");
@@ -289,6 +307,7 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
289 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "End of SGX initialisation script part 1\n"); 307 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "End of SGX initialisation script part 1\n");
290 308
291 309
310 psDevInfo->ui32NumResets++;
292 SGXReset(psDevInfo, bFirstTime || bHardwareRecovery, PDUMP_FLAGS_CONTINUOUS); 311 SGXReset(psDevInfo, bFirstTime || bHardwareRecovery, PDUMP_FLAGS_CONTINUOUS);
293 312
294#if defined(EUR_CR_POWER) 313#if defined(EUR_CR_POWER)
@@ -379,12 +398,12 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
379 PDUMP_FLAGS_CONTINUOUS, 398 PDUMP_FLAGS_CONTINUOUS,
380 MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo)); 399 MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
381 PDUMPREG(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_EVENT_KICK, 0), EUR_CR_EVENT_KICK_NOW_MASK); 400 PDUMPREG(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_EVENT_KICK, 0), EUR_CR_EVENT_KICK_NOW_MASK);
382#endif 401#endif
383 } 402 }
384#endif 403#endif
385 404
386#if !defined(NO_HARDWARE) 405#if !defined(NO_HARDWARE)
387 406
388 407
389 if (PollForValueKM(&psSGXHostCtl->ui32InitStatus, 408 if (PollForValueKM(&psSGXHostCtl->ui32InitStatus,
390 PVRSRV_USSE_EDM_INIT_COMPLETE, 409 PVRSRV_USSE_EDM_INIT_COMPLETE,
@@ -396,10 +415,10 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
396 PVR_DPF((PVR_DBG_ERROR, "SGXInitialise: Wait for uKernel initialisation failed")); 415 PVR_DPF((PVR_DBG_ERROR, "SGXInitialise: Wait for uKernel initialisation failed"));
397 #if !defined(FIX_HW_BRN_23281) 416 #if !defined(FIX_HW_BRN_23281)
398 PVR_DBG_BREAK; 417 PVR_DBG_BREAK;
399 #endif 418 #endif
400 return PVRSRV_ERROR_RETRY; 419 return PVRSRV_ERROR_RETRY;
401 } 420 }
402#endif 421#endif
403 422
404#if defined(PDUMP) 423#if defined(PDUMP)
405 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, 424 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
@@ -411,19 +430,19 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
411 PDUMP_POLL_OPERATOR_EQUAL, 430 PDUMP_POLL_OPERATOR_EQUAL,
412 PDUMP_FLAGS_CONTINUOUS, 431 PDUMP_FLAGS_CONTINUOUS,
413 MAKEUNIQUETAG(psSGXHostCtlMemInfo)); 432 MAKEUNIQUETAG(psSGXHostCtlMemInfo));
414#endif 433#endif
415 434
416#if defined(FIX_HW_BRN_22997) && defined(FIX_HW_BRN_23030) && defined(SGX_FEATURE_HOST_PORT) 435#if defined(FIX_HW_BRN_22997) && defined(FIX_HW_BRN_23030) && defined(SGX_FEATURE_HOST_PORT)
417 436
418 437
419 438
420 WorkaroundBRN22997ReadHostPort(psDevInfo); 439 WorkaroundBRN22997ReadHostPort(psDevInfo);
421#endif 440#endif
422 441
423 PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset == psDevInfo->psKernelCCBCtl->ui32WriteOffset); 442 PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset == psDevInfo->psKernelCCBCtl->ui32WriteOffset);
424 443
425 bFirstTime = IMG_FALSE; 444 bFirstTime = IMG_FALSE;
426 445
427 return PVRSRV_OK; 446 return PVRSRV_OK;
428} 447}
429 448
@@ -433,7 +452,7 @@ PVRSRV_ERROR SGXDeinitialise(IMG_HANDLE hDevCookie)
433 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *) hDevCookie; 452 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *) hDevCookie;
434 PVRSRV_ERROR eError; 453 PVRSRV_ERROR eError;
435 454
436 455
437 if (psDevInfo->pvRegsBaseKM == IMG_NULL) 456 if (psDevInfo->pvRegsBaseKM == IMG_NULL)
438 { 457 {
439 return PVRSRV_OK; 458 return PVRSRV_OK;
@@ -461,12 +480,16 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
461 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap = psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap; 480 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap = psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap;
462 PVRSRV_ERROR eError; 481 PVRSRV_ERROR eError;
463 482
464 483
465 PDUMPCOMMENT("SGX Core Version Information: %s", SGX_CORE_FRIENDLY_NAME); 484 PDUMPCOMMENT("SGX Core Version Information: %s", SGX_CORE_FRIENDLY_NAME);
466 485
467 #if defined(SGX_FEATURE_MP) 486 #if defined(SGX_FEATURE_MP)
487 #if !defined(SGX_FEATURE_MP_PLUS)
468 PDUMPCOMMENT("SGX Multi-processor: %d cores", SGX_FEATURE_MP_CORE_COUNT); 488 PDUMPCOMMENT("SGX Multi-processor: %d cores", SGX_FEATURE_MP_CORE_COUNT);
489 #else
490 PDUMPCOMMENT("SGX Multi-processor: %d TA cores, %d 3D cores", SGX_FEATURE_MP_CORE_COUNT_TA, SGX_FEATURE_MP_CORE_COUNT_3D);
469 #endif 491 #endif
492 #endif
470 493
471#if (SGX_CORE_REV == 0) 494#if (SGX_CORE_REV == 0)
472 PDUMPCOMMENT("SGX Core Revision Information: head RTL"); 495 PDUMPCOMMENT("SGX Core Revision Information: head RTL");
@@ -478,8 +501,8 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
478 PDUMPCOMMENT("SGX System Level Cache is present\r\n"); 501 PDUMPCOMMENT("SGX System Level Cache is present\r\n");
479 #if defined(SGX_BYPASS_SYSTEM_CACHE) 502 #if defined(SGX_BYPASS_SYSTEM_CACHE)
480 PDUMPCOMMENT("SGX System Level Cache is bypassed\r\n"); 503 PDUMPCOMMENT("SGX System Level Cache is bypassed\r\n");
481 #endif 504 #endif
482 #endif 505 #endif
483 506
484 PDUMPCOMMENT("SGX Initialisation Part 1"); 507 PDUMPCOMMENT("SGX Initialisation Part 1");
485 508
@@ -526,12 +549,16 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
526 case DEVICE_MEMORY_HEAP_SHARED: 549 case DEVICE_MEMORY_HEAP_SHARED:
527 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED: 550 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
528 { 551 {
529 hDevMemHeap = BM_CreateHeap (hKernelDevMemContext,
530 &psDeviceMemoryHeap[i]);
531 552
553 if (psDeviceMemoryHeap[i].ui32HeapSize > 0)
554 {
555 hDevMemHeap = BM_CreateHeap (hKernelDevMemContext,
556 &psDeviceMemoryHeap[i]);
557
532 558
533 559
534 psDeviceMemoryHeap[i].hDevMemHeap = hDevMemHeap; 560 psDeviceMemoryHeap[i].hDevMemHeap = hDevMemHeap;
561 }
535 break; 562 break;
536 } 563 }
537 } 564 }
@@ -554,7 +581,11 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
554} 581}
555 582
556IMG_EXPORT 583IMG_EXPORT
584#if defined (SUPPORT_SID_INTERFACE)
585PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, PVRSRV_HEAP_INFO_KM *pasHeapInfo, IMG_DEV_PHYADDR *psPDDevPAddr)
586#else
557PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo) 587PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo)
588#endif
558{ 589{
559 PVRSRV_DEVICE_NODE *psDeviceNode; 590 PVRSRV_DEVICE_NODE *psDeviceNode;
560 PVRSRV_SGXDEV_INFO *psDevInfo; 591 PVRSRV_SGXDEV_INFO *psDevInfo;
@@ -565,9 +596,15 @@ PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_S
565 psDeviceNode = (PVRSRV_DEVICE_NODE *)hDevHandle; 596 psDeviceNode = (PVRSRV_DEVICE_NODE *)hDevHandle;
566 psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; 597 psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
567 598
599#if defined (SUPPORT_SID_INTERFACE)
600 *psPDDevPAddr = psDevInfo->sKernelPDDevPAddr;
601
602 eError = PVRSRVGetDeviceMemHeapsKM(hDevHandle, pasHeapInfo);
603#else
568 psInitInfo->sPDDevPAddr = psDevInfo->sKernelPDDevPAddr; 604 psInitInfo->sPDDevPAddr = psDevInfo->sKernelPDDevPAddr;
569 605
570 eError = PVRSRVGetDeviceMemHeapsKM(hDevHandle, &psInitInfo->asHeapInfo[0]); 606 eError = PVRSRVGetDeviceMemHeapsKM(hDevHandle, &psInitInfo->asHeapInfo[0]);
607#endif
571 if (eError != PVRSRV_OK) 608 if (eError != PVRSRV_OK)
572 { 609 {
573 PVR_DPF((PVR_DBG_ERROR,"SGXGetInfoForSrvinit: PVRSRVGetDeviceMemHeapsKM failed (%d)", eError)); 610 PVR_DPF((PVR_DBG_ERROR,"SGXGetInfoForSrvinit: PVRSRVGetDeviceMemHeapsKM failed (%d)", eError));
@@ -580,7 +617,11 @@ PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_S
580IMG_EXPORT 617IMG_EXPORT
581PVRSRV_ERROR DevInitSGXPart2KM (PVRSRV_PER_PROCESS_DATA *psPerProc, 618PVRSRV_ERROR DevInitSGXPart2KM (PVRSRV_PER_PROCESS_DATA *psPerProc,
582 IMG_HANDLE hDevHandle, 619 IMG_HANDLE hDevHandle,
620#if defined (SUPPORT_SID_INTERFACE)
621 SGX_BRIDGE_INIT_INFO_KM *psInitInfo)
622#else
583 SGX_BRIDGE_INIT_INFO *psInitInfo) 623 SGX_BRIDGE_INIT_INFO *psInitInfo)
624#endif
584{ 625{
585 PVRSRV_DEVICE_NODE *psDeviceNode; 626 PVRSRV_DEVICE_NODE *psDeviceNode;
586 PVRSRV_SGXDEV_INFO *psDevInfo; 627 PVRSRV_SGXDEV_INFO *psDevInfo;
@@ -877,9 +918,12 @@ static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
877 PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Linear): 0x%08X", (IMG_UINTPTR_T)psDevInfo->pvRegsBaseKM)); 918 PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Linear): 0x%08X", (IMG_UINTPTR_T)psDevInfo->pvRegsBaseKM));
878 PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Physical): 0x%08X", psDevInfo->sRegsPhysBase.uiAddr)); 919 PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Physical): 0x%08X", psDevInfo->sRegsPhysBase.uiAddr));
879 920
880 for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT; ui32CoreNum++) 921 SGXDumpDebugReg(psDevInfo, 0, "EUR_CR_CORE_ID: ", EUR_CR_CORE_ID);
922 SGXDumpDebugReg(psDevInfo, 0, "EUR_CR_CORE_REVISION: ", EUR_CR_CORE_REVISION);
923
924 for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT_3D; ui32CoreNum++)
881 { 925 {
882 926
883 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS: ", EUR_CR_EVENT_STATUS); 927 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS: ", EUR_CR_EVENT_STATUS);
884 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS2: ", EUR_CR_EVENT_STATUS2); 928 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS2: ", EUR_CR_EVENT_STATUS2);
885 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_BIF_CTRL: ", EUR_CR_BIF_CTRL); 929 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_BIF_CTRL: ", EUR_CR_BIF_CTRL);
@@ -903,8 +947,15 @@ static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
903 { 947 {
904 948
905 949
906 IMG_UINT32 *pui32HostCtlBuffer = (IMG_UINT32 *)psDevInfo->psSGXHostCtl; 950 SGXMKIF_HOST_CTL *psSGXHostCtl = psDevInfo->psSGXHostCtl;
907 IMG_UINT32 ui32LoopCounter; 951 IMG_UINT32 *pui32HostCtlBuffer = (IMG_UINT32 *)psSGXHostCtl;
952 IMG_UINT32 ui32LoopCounter;
953
954 if (psSGXHostCtl->ui32AssertFail != 0)
955 {
956 PVR_LOG(("SGX Microkernel assert fail: 0x%08X", psSGXHostCtl->ui32AssertFail));
957 psSGXHostCtl->ui32AssertFail = 0;
958 }
908 959
909 PVR_LOG(("SGX Host control:")); 960 PVR_LOG(("SGX Host control:"));
910 961
@@ -927,7 +978,7 @@ static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
927 PVR_LOG(("SGX TA/3D control:")); 978 PVR_LOG(("SGX TA/3D control:"));
928 979
929 for (ui32LoopCounter = 0; 980 for (ui32LoopCounter = 0;
930 ui32LoopCounter < psDevInfo->psKernelSGXTA3DCtlMemInfo->ui32AllocSize / sizeof(*pui32TA3DCtlBuffer); 981 ui32LoopCounter < psDevInfo->psKernelSGXTA3DCtlMemInfo->uAllocSize / sizeof(*pui32TA3DCtlBuffer);
931 ui32LoopCounter += 4) 982 ui32LoopCounter += 4)
932 { 983 {
933 PVR_LOG(("\t(T3C-%X) 0x%08X 0x%08X 0x%08X 0x%08X", ui32LoopCounter * sizeof(*pui32TA3DCtlBuffer), 984 PVR_LOG(("\t(T3C-%X) 0x%08X 0x%08X 0x%08X 0x%08X", ui32LoopCounter * sizeof(*pui32TA3DCtlBuffer),
@@ -995,6 +1046,10 @@ static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
995 } 1046 }
996 #endif 1047 #endif
997 } 1048 }
1049 #if defined (TTRACE)
1050 PVRSRVDumpTimeTraceBuffers();
1051 #endif
1052
998} 1053}
999 1054
1000 1055
@@ -1028,36 +1083,35 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode,
1028 1083
1029 SGXDumpDebugInfo(psDeviceNode->pvDevice, IMG_TRUE); 1084 SGXDumpDebugInfo(psDeviceNode->pvDevice, IMG_TRUE);
1030 1085
1031 1086
1032 PDUMPSUSPEND(); 1087 PDUMPSUSPEND();
1033 1088
1034 1089
1035#if defined(FIX_HW_BRN_23281) 1090#if defined(FIX_HW_BRN_23281)
1036 1091
1037 for (eError = PVRSRV_ERROR_RETRY; eError == PVRSRV_ERROR_RETRY;) 1092 for (eError = PVRSRV_ERROR_RETRY; eError == PVRSRV_ERROR_RETRY;)
1038#endif 1093#endif
1039 { 1094 {
1040 eError = SGXInitialise(psDevInfo, IMG_TRUE); 1095 eError = SGXInitialise(psDevInfo, IMG_TRUE);
1041 } 1096 }
1042
1043 if (eError != PVRSRV_OK) 1097 if (eError != PVRSRV_OK)
1044 { 1098 {
1045 PVR_DPF((PVR_DBG_ERROR,"HWRecoveryResetSGX: SGXInitialise failed (%d)", eError)); 1099 PVR_DPF((PVR_DBG_ERROR,"HWRecoveryResetSGX: SGXInitialise failed (%d)", eError));
1046 } 1100 }
1047 1101
1048 1102
1049 PDUMPRESUME(); 1103 PDUMPRESUME();
1050 1104
1051 PVRSRVPowerUnlock(ui32CallerID); 1105 PVRSRVPowerUnlock(ui32CallerID);
1052 1106
1053 1107
1054 SGXScheduleProcessQueuesKM(psDeviceNode); 1108 SGXScheduleProcessQueuesKM(psDeviceNode);
1055 1109
1056 1110
1057 1111
1058 PVRSRVProcessQueues(ui32CallerID, IMG_TRUE); 1112 PVRSRVProcessQueues(IMG_TRUE);
1059} 1113}
1060#endif 1114#endif
1061 1115
1062 1116
1063#if defined(SUPPORT_HW_RECOVERY) 1117#if defined(SUPPORT_HW_RECOVERY)
@@ -1066,7 +1120,7 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1066 PVRSRV_DEVICE_NODE *psDeviceNode = pvData; 1120 PVRSRV_DEVICE_NODE *psDeviceNode = pvData;
1067 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; 1121 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1068 static IMG_UINT32 ui32EDMTasks = 0; 1122 static IMG_UINT32 ui32EDMTasks = 0;
1069 static IMG_UINT32 ui32LockupCounter = 0; 1123 static IMG_UINT32 ui32LockupCounter = 0;
1070 static IMG_UINT32 ui32NumResets = 0; 1124 static IMG_UINT32 ui32NumResets = 0;
1071#if defined(FIX_HW_BRN_31093) 1125#if defined(FIX_HW_BRN_31093)
1072 static IMG_BOOL bBRN31093Inval = IMG_FALSE; 1126 static IMG_BOOL bBRN31093Inval = IMG_FALSE;
@@ -1075,17 +1129,17 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1075 IMG_BOOL bLockup = IMG_FALSE; 1129 IMG_BOOL bLockup = IMG_FALSE;
1076 IMG_BOOL bPoweredDown; 1130 IMG_BOOL bPoweredDown;
1077 1131
1078 1132
1079 psDevInfo->ui32TimeStamp++; 1133 psDevInfo->ui32TimeStamp++;
1080 1134
1081#if defined(NO_HARDWARE) 1135#if defined(NO_HARDWARE)
1082 bPoweredDown = IMG_TRUE; 1136 bPoweredDown = IMG_TRUE;
1083#else 1137#else
1084 bPoweredDown = (SGXIsDevicePowered(psDeviceNode)) ? IMG_FALSE : IMG_TRUE; 1138 bPoweredDown = (SGXIsDevicePowered(psDeviceNode)) ? IMG_FALSE : IMG_TRUE;
1085#endif 1139#endif
1086
1087
1088 1140
1141
1142
1089 if (bPoweredDown) 1143 if (bPoweredDown)
1090 { 1144 {
1091 ui32LockupCounter = 0; 1145 ui32LockupCounter = 0;
@@ -1095,7 +1149,7 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1095 } 1149 }
1096 else 1150 else
1097 { 1151 {
1098 1152
1099 ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM, psDevInfo->ui32EDMTaskReg0); 1153 ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM, psDevInfo->ui32EDMTaskReg0);
1100 if (psDevInfo->ui32EDMTaskReg1 != 0) 1154 if (psDevInfo->ui32EDMTaskReg1 != 0)
1101 { 1155 {
@@ -1108,40 +1162,40 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1108 if (ui32LockupCounter == 3) 1162 if (ui32LockupCounter == 3)
1109 { 1163 {
1110 ui32LockupCounter = 0; 1164 ui32LockupCounter = 0;
1111 1165
1112 #if defined(FIX_HW_BRN_31093) 1166 #if defined(FIX_HW_BRN_31093)
1113 if (bBRN31093Inval == IMG_FALSE) 1167 if (bBRN31093Inval == IMG_FALSE)
1114 { 1168 {
1115 1169
1116 #if defined(FIX_HW_BRN_29997) 1170 #if defined(FIX_HW_BRN_29997)
1117 IMG_UINT32 ui32BIFCtrl; 1171 IMG_UINT32 ui32BIFCtrl;
1118 1172
1119 ui32BIFCtrl = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL); 1173 ui32BIFCtrl = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL);
1120 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl | EUR_CR_BIF_CTRL_PAUSE_MASK); 1174 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl | EUR_CR_BIF_CTRL_PAUSE_MASK);
1121 1175
1122 OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed); 1176 OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed);
1123 #endif 1177 #endif
1124 1178
1125 bBRN31093Inval = IMG_TRUE; 1179 bBRN31093Inval = IMG_TRUE;
1126 1180
1127 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, EUR_CR_BIF_CTRL_INVAL_PTE_MASK); 1181 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, EUR_CR_BIF_CTRL_INVAL_PTE_MASK);
1128 1182
1129 OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed); 1183 OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed);
1130 1184
1131 #if defined(FIX_HW_BRN_29997) 1185 #if defined(FIX_HW_BRN_29997)
1132 1186
1133 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl); 1187 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl);
1134 #endif 1188 #endif
1135 } 1189 }
1136 else 1190 else
1137 #endif 1191 #endif
1138 { 1192 {
1139 PVR_DPF((PVR_DBG_ERROR, "SGXOSTimer() detected SGX lockup (0x%x tasks)", ui32EDMTasks)); 1193 PVR_DPF((PVR_DBG_ERROR, "SGXOSTimer() detected SGX lockup (0x%x tasks)", ui32EDMTasks));
1140 1194
1141 bLockup = IMG_TRUE; 1195 bLockup = IMG_TRUE;
1142 }
1143 } 1196 }
1144 } 1197 }
1198 }
1145 else 1199 else
1146 { 1200 {
1147 #if defined(FIX_HW_BRN_31093) 1201 #if defined(FIX_HW_BRN_31093)
@@ -1157,14 +1211,14 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1157 { 1211 {
1158 SGXMKIF_HOST_CTL *psSGXHostCtl = (SGXMKIF_HOST_CTL *)psDevInfo->psSGXHostCtl; 1212 SGXMKIF_HOST_CTL *psSGXHostCtl = (SGXMKIF_HOST_CTL *)psDevInfo->psSGXHostCtl;
1159 1213
1160 1214
1161 psSGXHostCtl->ui32HostDetectedLockups ++; 1215 psSGXHostCtl->ui32HostDetectedLockups ++;
1162 1216
1163 1217
1164 HWRecoveryResetSGX(psDeviceNode, 0, KERNEL_ID); 1218 HWRecoveryResetSGX(psDeviceNode, 0, KERNEL_ID);
1165 } 1219 }
1166} 1220}
1167#endif 1221#endif
1168 1222
1169 1223
1170#if defined(SYS_USING_INTERRUPTS) 1224#if defined(SYS_USING_INTERRUPTS)
@@ -1174,18 +1228,18 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
1174 IMG_BOOL bInterruptProcessed = IMG_FALSE; 1228 IMG_BOOL bInterruptProcessed = IMG_FALSE;
1175 1229
1176 1230
1177 1231
1178 { 1232 {
1179 IMG_UINT32 ui32EventStatus, ui32EventEnable; 1233 IMG_UINT32 ui32EventStatus, ui32EventEnable;
1180 IMG_UINT32 ui32EventClear = 0; 1234 IMG_UINT32 ui32EventClear = 0;
1181#if defined(SGX_FEATURE_DATA_BREAKPOINTS) 1235#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
1182 IMG_UINT32 ui32EventStatus2, ui32EventEnable2; 1236 IMG_UINT32 ui32EventStatus2, ui32EventEnable2;
1183#endif 1237#endif
1184 IMG_UINT32 ui32EventClear2 = 0; 1238 IMG_UINT32 ui32EventClear2 = 0;
1185 PVRSRV_DEVICE_NODE *psDeviceNode; 1239 PVRSRV_DEVICE_NODE *psDeviceNode;
1186 PVRSRV_SGXDEV_INFO *psDevInfo; 1240 PVRSRV_SGXDEV_INFO *psDevInfo;
1187 1241
1188 1242
1189 if(pvData == IMG_NULL) 1243 if(pvData == IMG_NULL)
1190 { 1244 {
1191 PVR_DPF((PVR_DBG_ERROR, "SGX_ISRHandler: Invalid params\n")); 1245 PVR_DPF((PVR_DBG_ERROR, "SGX_ISRHandler: Invalid params\n"));
@@ -1198,18 +1252,18 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
1198 ui32EventStatus = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS); 1252 ui32EventStatus = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
1199 ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE); 1253 ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE);
1200 1254
1201 1255
1202 ui32EventStatus &= ui32EventEnable; 1256 ui32EventStatus &= ui32EventEnable;
1203 1257
1204#if defined(SGX_FEATURE_DATA_BREAKPOINTS) 1258#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
1205 ui32EventStatus2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2); 1259 ui32EventStatus2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
1206 ui32EventEnable2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE2); 1260 ui32EventEnable2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE2);
1207 1261
1208 1262
1209 ui32EventStatus2 &= ui32EventEnable2; 1263 ui32EventStatus2 &= ui32EventEnable2;
1210#endif 1264#endif
1211
1212 1265
1266
1213 1267
1214 if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK) 1268 if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK)
1215 { 1269 {
@@ -1226,16 +1280,16 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
1226 { 1280 {
1227 ui32EventClear2 |= EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK; 1281 ui32EventClear2 |= EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK;
1228 } 1282 }
1229#endif 1283#endif
1230 1284
1231 if (ui32EventClear || ui32EventClear2) 1285 if (ui32EventClear || ui32EventClear2)
1232 { 1286 {
1233 bInterruptProcessed = IMG_TRUE; 1287 bInterruptProcessed = IMG_TRUE;
1234 1288
1235 1289
1236 ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK; 1290 ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK;
1237 1291
1238 1292
1239 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32EventClear); 1293 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32EventClear);
1240 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2); 1294 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2);
1241 } 1295 }
@@ -1266,7 +1320,7 @@ static IMG_VOID SGX_MISRHandler (IMG_VOID *pvData)
1266 1320
1267 SGXTestActivePowerEvent(psDeviceNode, ISR_ID); 1321 SGXTestActivePowerEvent(psDeviceNode, ISR_ID);
1268} 1322}
1269#endif 1323#endif
1270 1324
1271 1325
1272 1326
@@ -1284,14 +1338,14 @@ PVRSRV_ERROR SGX_AllocMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
1284 IMG_UINT32 ui32Offset; 1338 IMG_UINT32 ui32Offset;
1285 IMG_UINT32 ui32Val; 1339 IMG_UINT32 ui32Val;
1286 1340
1287 1341
1288 for(i=0; i<10; i++) 1342 for(i=0; i<10; i++)
1289 { 1343 {
1290 if((psDevInfo->ui32MemTilingUsage & (1U << i)) == 0) 1344 if((psDevInfo->ui32MemTilingUsage & (1U << i)) == 0)
1291 { 1345 {
1292 1346
1293 psDevInfo->ui32MemTilingUsage |= 1U << i; 1347 psDevInfo->ui32MemTilingUsage |= 1U << i;
1294 1348
1295 *pui32RangeIndex = i; 1349 *pui32RangeIndex = i;
1296 goto RangeAllocated; 1350 goto RangeAllocated;
1297 } 1351 }
@@ -1304,14 +1358,14 @@ RangeAllocated:
1304 ui32Offset = EUR_CR_BIF_TILE0 + (i<<2); 1358 ui32Offset = EUR_CR_BIF_TILE0 + (i<<2);
1305 1359
1306 ui32Start = psMemInfo->sDevVAddr.uiAddr; 1360 ui32Start = psMemInfo->sDevVAddr.uiAddr;
1307 ui32End = ui32Start + psMemInfo->ui32AllocSize + SGX_MMU_PAGE_SIZE - 1; 1361 ui32End = ui32Start + psMemInfo->uAllocSize + SGX_MMU_PAGE_SIZE - 1;
1308 1362
1309 ui32Val = ((ui32TilingStride << EUR_CR_BIF_TILE0_CFG_SHIFT) & EUR_CR_BIF_TILE0_CFG_MASK) 1363 ui32Val = ((ui32TilingStride << EUR_CR_BIF_TILE0_CFG_SHIFT) & EUR_CR_BIF_TILE0_CFG_MASK)
1310 | (((ui32End>>20) << EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK) 1364 | (((ui32End>>20) << EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK)
1311 | (((ui32Start>>20) << EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK) 1365 | (((ui32Start>>20) << EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK)
1312 | (0x8 << EUR_CR_BIF_TILE0_CFG_SHIFT); 1366 | (0x8 << EUR_CR_BIF_TILE0_CFG_SHIFT);
1313 1367
1314 1368
1315 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val); 1369 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
1316 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val); 1370 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
1317 1371
@@ -1320,7 +1374,7 @@ RangeAllocated:
1320 ui32Val = (((ui32End>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MAX_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MAX_MASK) 1374 ui32Val = (((ui32End>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MAX_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MAX_MASK)
1321 | (((ui32Start>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MIN_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MIN_MASK); 1375 | (((ui32Start>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MIN_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MIN_MASK);
1322 1376
1323 1377
1324 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val); 1378 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
1325 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val); 1379 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
1326 1380
@@ -1350,14 +1404,14 @@ PVRSRV_ERROR SGX_FreeMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
1350 return PVRSRV_ERROR_INVALID_PARAMS; 1404 return PVRSRV_ERROR_INVALID_PARAMS;
1351 } 1405 }
1352 1406
1353 1407
1354 psDevInfo->ui32MemTilingUsage &= ~(1<<ui32RangeIndex); 1408 psDevInfo->ui32MemTilingUsage &= ~(1<<ui32RangeIndex);
1355 1409
1356 1410
1357 ui32Offset = EUR_CR_BIF_TILE0 + (ui32RangeIndex<<2); 1411 ui32Offset = EUR_CR_BIF_TILE0 + (ui32RangeIndex<<2);
1358 ui32Val = 0; 1412 ui32Val = 0;
1359 1413
1360 1414
1361 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val); 1415 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
1362 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val); 1416 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
1363 1417
@@ -1378,12 +1432,12 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1378 DEVICE_MEMORY_INFO *psDevMemoryInfo; 1432 DEVICE_MEMORY_INFO *psDevMemoryInfo;
1379 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap; 1433 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
1380 1434
1381 1435
1382 psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE; 1436 psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE;
1383 psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS; 1437 psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS;
1384#if defined(PDUMP) 1438#if defined(PDUMP)
1385 { 1439 {
1386 1440
1387 SGX_DEVICE_MAP *psSGXDeviceMemMap; 1441 SGX_DEVICE_MAP *psSGXDeviceMemMap;
1388 SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX, 1442 SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
1389 (IMG_VOID**)&psSGXDeviceMemMap); 1443 (IMG_VOID**)&psSGXDeviceMemMap);
@@ -1391,9 +1445,9 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1391 psDeviceNode->sDevId.pszPDumpDevName = psSGXDeviceMemMap->pszPDumpDevName; 1445 psDeviceNode->sDevId.pszPDumpDevName = psSGXDeviceMemMap->pszPDumpDevName;
1392 PVR_ASSERT(psDeviceNode->sDevId.pszPDumpDevName != IMG_NULL); 1446 PVR_ASSERT(psDeviceNode->sDevId.pszPDumpDevName != IMG_NULL);
1393 } 1447 }
1394 1448
1395 psDeviceNode->sDevId.pszPDumpRegName = SGX_PDUMPREG_NAME; 1449 psDeviceNode->sDevId.pszPDumpRegName = SGX_PDUMPREG_NAME;
1396#endif 1450#endif
1397 1451
1398 psDeviceNode->pfnInitDevice = &DevInitSGXPart1; 1452 psDeviceNode->pfnInitDevice = &DevInitSGXPart1;
1399 psDeviceNode->pfnDeInitDevice = &DevDeInitSGX; 1453 psDeviceNode->pfnDeInitDevice = &DevDeInitSGX;
@@ -1403,7 +1457,7 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1403 psDeviceNode->pfnPDumpInitDevice = &SGXResetPDump; 1457 psDeviceNode->pfnPDumpInitDevice = &SGXResetPDump;
1404 psDeviceNode->pfnMMUGetContextID = &MMU_GetPDumpContextID; 1458 psDeviceNode->pfnMMUGetContextID = &MMU_GetPDumpContextID;
1405#endif 1459#endif
1406 1460
1407 1461
1408 psDeviceNode->pfnMMUInitialise = &MMU_Initialise; 1462 psDeviceNode->pfnMMUInitialise = &MMU_Initialise;
1409 psDeviceNode->pfnMMUFinalise = &MMU_Finalise; 1463 psDeviceNode->pfnMMUFinalise = &MMU_Finalise;
@@ -1421,9 +1475,15 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1421#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 1475#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
1422 psDeviceNode->pfnMMUIsHeapShared = &MMU_IsHeapShared; 1476 psDeviceNode->pfnMMUIsHeapShared = &MMU_IsHeapShared;
1423#endif 1477#endif
1424 1478#if defined(FIX_HW_BRN_31620)
1479 psDeviceNode->pfnMMUGetCacheFlushRange = &MMU_GetCacheFlushRange;
1480 psDeviceNode->pfnMMUGetPDPhysAddr = &MMU_GetPDPhysAddr;
1481#else
1482 psDeviceNode->pfnMMUGetCacheFlushRange = IMG_NULL;
1483 psDeviceNode->pfnMMUGetPDPhysAddr = IMG_NULL;
1484#endif
1425#if defined (SYS_USING_INTERRUPTS) 1485#if defined (SYS_USING_INTERRUPTS)
1426 1486
1427 1487
1428 psDeviceNode->pfnDeviceISR = SGX_ISRHandler; 1488 psDeviceNode->pfnDeviceISR = SGX_ISRHandler;
1429 psDeviceNode->pfnDeviceMISR = SGX_MISRHandler; 1489 psDeviceNode->pfnDeviceMISR = SGX_MISRHandler;
@@ -1434,20 +1494,20 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1434 psDeviceNode->pfnFreeMemTilingRange = SGX_FreeMemTilingRange; 1494 psDeviceNode->pfnFreeMemTilingRange = SGX_FreeMemTilingRange;
1435#endif 1495#endif
1436 1496
1437 1497
1438 1498
1439 psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete; 1499 psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete;
1440 1500
1441 1501
1442 1502
1443 psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; 1503 psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
1444 1504
1445 psDevMemoryInfo->ui32AddressSpaceSizeLog2 = SGX_FEATURE_ADDRESS_SPACE_SIZE; 1505 psDevMemoryInfo->ui32AddressSpaceSizeLog2 = SGX_FEATURE_ADDRESS_SPACE_SIZE;
1446 1506
1447 1507
1448 psDevMemoryInfo->ui32Flags = 0; 1508 psDevMemoryInfo->ui32Flags = 0;
1449 1509
1450 1510
1451 if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP, 1511 if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP,
1452 sizeof(DEVICE_MEMORY_HEAP_INFO) * SGX_MAX_HEAP_ID, 1512 sizeof(DEVICE_MEMORY_HEAP_INFO) * SGX_MAX_HEAP_ID,
1453 (IMG_VOID **)&psDevMemoryInfo->psDeviceMemoryHeap, 0, 1513 (IMG_VOID **)&psDevMemoryInfo->psDeviceMemoryHeap, 0,
@@ -1460,7 +1520,10 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1460 1520
1461 psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap; 1521 psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
1462 1522
1523
1524
1463 1525
1526
1464 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID); 1527 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID);
1465 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_GENERAL_HEAP_BASE; 1528 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_GENERAL_HEAP_BASE;
1466 psDeviceMemoryHeap->ui32HeapSize = SGX_GENERAL_HEAP_SIZE; 1529 psDeviceMemoryHeap->ui32HeapSize = SGX_GENERAL_HEAP_SIZE;
@@ -1470,16 +1533,16 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1470 psDeviceMemoryHeap->pszName = "General"; 1533 psDeviceMemoryHeap->pszName = "General";
1471 psDeviceMemoryHeap->pszBSName = "General BS"; 1534 psDeviceMemoryHeap->pszBSName = "General BS";
1472 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT; 1535 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
1473 1536
1474 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE; 1537 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
1475#if !defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP) 1538#if !defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
1476 1539
1477 psDevMemoryInfo->ui32MappingHeapID = (IMG_UINT32)(psDeviceMemoryHeap - psDevMemoryInfo->psDeviceMemoryHeap); 1540 psDevMemoryInfo->ui32MappingHeapID = (IMG_UINT32)(psDeviceMemoryHeap - psDevMemoryInfo->psDeviceMemoryHeap);
1478#endif 1541#endif
1479 psDeviceMemoryHeap++; 1542 psDeviceMemoryHeap++;
1480 1543
1481 1544
1482 1545
1483 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID); 1546 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID);
1484 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_TADATA_HEAP_BASE; 1547 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_TADATA_HEAP_BASE;
1485 psDeviceMemoryHeap->ui32HeapSize = SGX_TADATA_HEAP_SIZE; 1548 psDeviceMemoryHeap->ui32HeapSize = SGX_TADATA_HEAP_SIZE;
@@ -1489,12 +1552,12 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1489 psDeviceMemoryHeap->pszName = "TA Data"; 1552 psDeviceMemoryHeap->pszName = "TA Data";
1490 psDeviceMemoryHeap->pszBSName = "TA Data BS"; 1553 psDeviceMemoryHeap->pszBSName = "TA Data BS";
1491 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT; 1554 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
1492 1555
1493 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE; 1556 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
1494 psDeviceMemoryHeap++; 1557 psDeviceMemoryHeap++;
1495 1558
1496 1559
1497 1560
1498 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID); 1561 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID);
1499 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_KERNEL_CODE_HEAP_BASE; 1562 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_KERNEL_CODE_HEAP_BASE;
1500 psDeviceMemoryHeap->ui32HeapSize = SGX_KERNEL_CODE_HEAP_SIZE; 1563 psDeviceMemoryHeap->ui32HeapSize = SGX_KERNEL_CODE_HEAP_SIZE;
@@ -1611,22 +1674,30 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1611 1674
1612 1675
1613 1676
1614 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_3DPARAMETERS_HEAP_ID); 1677 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_SHARED_3DPARAMETERS_HEAP_ID);
1615 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_3DPARAMETERS_HEAP_BASE; 1678 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_SHARED_3DPARAMETERS_HEAP_BASE;
1616 psDeviceMemoryHeap->ui32HeapSize = SGX_3DPARAMETERS_HEAP_SIZE; 1679 psDeviceMemoryHeap->ui32HeapSize = SGX_SHARED_3DPARAMETERS_HEAP_SIZE;
1617 psDeviceMemoryHeap->pszName = "3DParameters"; 1680 psDeviceMemoryHeap->pszName = "Shared 3DParameters";
1618 psDeviceMemoryHeap->pszBSName = "3DParameters BS"; 1681 psDeviceMemoryHeap->pszBSName = "Shared 3DParameters BS";
1619#if defined(SUPPORT_PERCONTEXT_PB)
1620 psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE
1621 | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1622 | PVRSRV_HAP_SINGLE_PROCESS;
1623 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
1624#else
1625 psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE 1682 psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE
1626 | PVRSRV_MEM_RAM_BACKED_ALLOCATION 1683 | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1627 | PVRSRV_HAP_MULTI_PROCESS; 1684 | PVRSRV_HAP_MULTI_PROCESS;
1628 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_SHARED_EXPORTED; 1685 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1629#endif 1686
1687
1688 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
1689 psDeviceMemoryHeap++;
1690
1691
1692 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_PERCONTEXT_3DPARAMETERS_HEAP_ID);
1693 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE;
1694 psDeviceMemoryHeap->ui32HeapSize = SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE;
1695 psDeviceMemoryHeap->pszName = "Percontext 3DParameters";
1696 psDeviceMemoryHeap->pszBSName = "Percontext 3DParameters BS";
1697 psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE
1698 | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1699 | PVRSRV_HAP_SINGLE_PROCESS;
1700 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
1630 1701
1631 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE; 1702 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
1632 psDeviceMemoryHeap++; 1703 psDeviceMemoryHeap++;
@@ -1813,7 +1884,7 @@ PVRSRV_ERROR SGXDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode)
1813 psSGXMiscInfoInt = psMemInfo->pvLinAddrKM; 1884 psSGXMiscInfoInt = psMemInfo->pvLinAddrKM;
1814 psSGXMiscInfoInt->ui32MiscInfoFlags = 0; 1885 psSGXMiscInfoInt->ui32MiscInfoFlags = 0;
1815 psSGXMiscInfoInt->ui32MiscInfoFlags |= PVRSRV_USSE_MISCINFO_GET_STRUCT_SIZES; 1886 psSGXMiscInfoInt->ui32MiscInfoFlags |= PVRSRV_USSE_MISCINFO_GET_STRUCT_SIZES;
1816 eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode); 1887 eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode, IMG_NULL);
1817 1888
1818 1889
1819 if(eError != PVRSRV_OK) 1890 if(eError != PVRSRV_OK)
@@ -1954,7 +2025,8 @@ chk_exit:
1954 2025
1955static 2026static
1956PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo, 2027PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo,
1957 PVRSRV_DEVICE_NODE *psDeviceNode) 2028 PVRSRV_DEVICE_NODE *psDeviceNode,
2029 IMG_HANDLE hDevMemContext)
1958{ 2030{
1959 PVRSRV_ERROR eError; 2031 PVRSRV_ERROR eError;
1960 SGXMKIF_COMMAND sCommandData; 2032 SGXMKIF_COMMAND sCommandData;
@@ -1988,6 +2060,7 @@ PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo,
1988 &sCommandData, 2060 &sCommandData,
1989 KERNEL_ID, 2061 KERNEL_ID,
1990 0, 2062 0,
2063 hDevMemContext,
1991 IMG_FALSE); 2064 IMG_FALSE);
1992 2065
1993 if (eError != PVRSRV_OK) 2066 if (eError != PVRSRV_OK)
@@ -2099,6 +2172,7 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2099 &sCommandData, 2172 &sCommandData,
2100 KERNEL_ID, 2173 KERNEL_ID,
2101 0, 2174 0,
2175 hDevMemContext,
2102 IMG_FALSE); 2176 IMG_FALSE);
2103 2177
2104 if (eError != PVRSRV_OK) 2178 if (eError != PVRSRV_OK)
@@ -2138,37 +2212,6 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2138 return PVRSRV_OK; 2212 return PVRSRV_OK;
2139 } 2213 }
2140 2214
2141 case SGX_MISC_INFO_REQUEST_WAIT_FOR_BREAKPOINT:
2142 {
2143
2144
2145 PDUMPCOMMENT("Wait for data breakpoint hit");
2146
2147#if defined(NO_HARDWARE) && defined(PDUMP)
2148 {
2149 PDUMPREGPOL(SGX_PDUMPREG_NAME,
2150 EUR_CR_EVENT_STATUS2,
2151 EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK,
2152 EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK);
2153
2154 PDUMPREG(SGX_PDUMPREG_NAME,
2155 EUR_CR_EVENT_HOST_CLEAR2,
2156 EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK);
2157
2158 PDUMPCOMMENT("Breakpoint detected. Wait a bit to show that pipeline stops in simulation");
2159 PDUMPIDL(2000);
2160
2161 PDUMPCOMMENT("Now we can resume");
2162 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_BREAKPOINT_TRAP, EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK | EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK);
2163 }
2164#else
2165 {
2166
2167 }
2168#endif
2169 return PVRSRV_OK;
2170 }
2171
2172 case SGX_MISC_INFO_REQUEST_POLL_BREAKPOINT: 2215 case SGX_MISC_INFO_REQUEST_POLL_BREAKPOINT:
2173 { 2216 {
2174 2217
@@ -2179,40 +2222,114 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2179 2222
2180 2223
2181#if !defined(NO_HARDWARE) 2224#if !defined(NO_HARDWARE)
2225#if defined(SGX_FEATURE_MP)
2182 IMG_BOOL bTrappedBPMaster; 2226 IMG_BOOL bTrappedBPMaster;
2183 IMG_BOOL abTrappedBPPerCore[SGX_FEATURE_MP_CORE_COUNT];
2184 IMG_UINT32 ui32CoreNum, ui32TrappedBPCoreNum; 2227 IMG_UINT32 ui32CoreNum, ui32TrappedBPCoreNum;
2228#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2229 IMG_UINT32 ui32PipeNum, ui32TrappedBPPipeNum;
2230#define NUM_PIPES_PLUS_ONE (SGX_FEATURE_PERPIPE_BKPT_REGS_NUMPIPES+1)
2231#endif
2185 IMG_BOOL bTrappedBPAny; 2232 IMG_BOOL bTrappedBPAny;
2233#endif
2234 IMG_BOOL bFoundOne;
2186 2235
2236#if defined(SGX_FEATURE_MP)
2187 ui32TrappedBPCoreNum = 0; 2237 ui32TrappedBPCoreNum = 0;
2188 bTrappedBPMaster = !!(EUR_CR_MASTER_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BREAKPOINT)); 2238 bTrappedBPMaster = !!(EUR_CR_MASTER_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BREAKPOINT));
2189 bTrappedBPAny = bTrappedBPMaster; 2239 bTrappedBPAny = bTrappedBPMaster;
2190 for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT; ui32CoreNum++) 2240#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2241 ui32TrappedBPPipeNum = 0;
2242#endif
2243 for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT_3D; ui32CoreNum++)
2191 { 2244 {
2192 abTrappedBPPerCore[ui32CoreNum] = !!(EUR_CR_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum))); 2245#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2193 if (abTrappedBPPerCore[ui32CoreNum]) 2246
2247
2248
2249#define SGX_MP_CORE_PIPE_SELECT(r,c,p) \
2250 ((SGX_MP_CORE_SELECT(EUR_CR_PARTITION_##r,c) + p*(EUR_CR_PIPE0_##r-EUR_CR_PARTITION_##r)))
2251 for (ui32PipeNum = 0; ui32PipeNum < NUM_PIPES_PLUS_ONE; ui32PipeNum++)
2252 {
2253 bFoundOne =
2254 0 != (EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK &
2255 OSReadHWReg(psDevInfo->pvRegsBaseKM,
2256 SGX_MP_CORE_PIPE_SELECT(BREAKPOINT,
2257 ui32CoreNum,
2258 ui32PipeNum)));
2259 if (bFoundOne)
2260 {
2261 bTrappedBPAny = IMG_TRUE;
2262 ui32TrappedBPCoreNum = ui32CoreNum;
2263 ui32TrappedBPPipeNum = ui32PipeNum;
2264 }
2265 }
2266#else
2267 bFoundOne = !!(EUR_CR_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum)));
2268 if (bFoundOne)
2194 { 2269 {
2195 bTrappedBPAny = IMG_TRUE; 2270 bTrappedBPAny = IMG_TRUE;
2196 ui32TrappedBPCoreNum = ui32CoreNum; 2271 ui32TrappedBPCoreNum = ui32CoreNum;
2197 } 2272 }
2273#endif
2198 } 2274 }
2199 2275
2200 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP = bTrappedBPAny; 2276 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP = bTrappedBPAny;
2277#else
2278#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2279 #error Not yet considered the case for per-pipe regs in non-mp case
2280#endif
2281 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP = 0 != (EUR_CR_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BREAKPOINT));
2282#endif
2201 2283
2202 if (psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP) 2284 if (psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP)
2203 { 2285 {
2204 IMG_UINT32 ui32Info0, ui32Info1; 2286 IMG_UINT32 ui32Info0, ui32Info1;
2205 2287
2288#if defined(SGX_FEATURE_MP)
2289#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2290 ui32Info0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0:SGX_MP_CORE_PIPE_SELECT(BREAKPOINT_TRAP_INFO0, ui32TrappedBPCoreNum, ui32TrappedBPPipeNum));
2291 ui32Info1 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1:SGX_MP_CORE_PIPE_SELECT(BREAKPOINT_TRAP_INFO1, ui32TrappedBPCoreNum, ui32TrappedBPPipeNum));
2292#else
2206 ui32Info0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0:SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP_INFO0, ui32TrappedBPCoreNum)); 2293 ui32Info0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0:SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP_INFO0, ui32TrappedBPCoreNum));
2207 ui32Info1 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1:SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP_INFO1, ui32TrappedBPCoreNum)); 2294 ui32Info1 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1:SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP_INFO1, ui32TrappedBPCoreNum));
2295#endif
2296#else
2297 ui32Info0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BREAKPOINT_TRAP_INFO0);
2298 ui32Info1 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BREAKPOINT_TRAP_INFO1);
2299#endif
2208 2300
2301#ifdef SGX_FEATURE_PERPIPE_BKPT_REGS
2302 psMiscInfo->uData.sSGXBreakpointInfo.ui32BPIndex = (ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_MASK) >> EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT;
2303 psMiscInfo->uData.sSGXBreakpointInfo.sTrappedBPDevVAddr.uiAddr = ui32Info0 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK;
2304 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPBurstLength = (ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK) >> EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT;
2305 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBPRead = !!(ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK);
2306 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPDataMaster = (ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK) >> EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT;
2307 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPTag = (ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_MASK) >> EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SHIFT;
2308#else
2209 psMiscInfo->uData.sSGXBreakpointInfo.ui32BPIndex = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT; 2309 psMiscInfo->uData.sSGXBreakpointInfo.ui32BPIndex = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT;
2210 psMiscInfo->uData.sSGXBreakpointInfo.sTrappedBPDevVAddr.uiAddr = ui32Info0 & EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK; 2310 psMiscInfo->uData.sSGXBreakpointInfo.sTrappedBPDevVAddr.uiAddr = ui32Info0 & EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK;
2211 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPBurstLength = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT; 2311 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPBurstLength = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT;
2212 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBPRead = !!(ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK); 2312 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBPRead = !!(ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK);
2213 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPDataMaster = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT; 2313 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPDataMaster = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT;
2214 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPTag = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT; 2314 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPTag = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT;
2315#endif
2316#if defined(SGX_FEATURE_MP)
2317#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2318
2319 psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum = bTrappedBPMaster?65535:(ui32TrappedBPCoreNum + (ui32TrappedBPPipeNum<<10));
2320#else
2321
2215 psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum = bTrappedBPMaster?65535:ui32TrappedBPCoreNum; 2322 psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum = bTrappedBPMaster?65535:ui32TrappedBPCoreNum;
2323#endif
2324#else
2325#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2326
2327#error non-mp perpipe regs not yet supported
2328#else
2329
2330 psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum = 65534;
2331#endif
2332#endif
2216 } 2333 }
2217#endif 2334#endif
2218 return PVRSRV_OK; 2335 return PVRSRV_OK;
@@ -2224,12 +2341,24 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2224 2341
2225 2342
2226#if !defined(NO_HARDWARE) 2343#if !defined(NO_HARDWARE)
2344#if defined(SGX_FEATURE_MP)
2227 IMG_UINT32 ui32CoreNum; 2345 IMG_UINT32 ui32CoreNum;
2228 IMG_BOOL bMaster; 2346 IMG_BOOL bMaster;
2347#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2348 IMG_UINT32 ui32PipeNum;
2349#endif
2350#endif
2229 IMG_UINT32 ui32OldSeqNum, ui32NewSeqNum; 2351 IMG_UINT32 ui32OldSeqNum, ui32NewSeqNum;
2230 2352
2353#if defined(SGX_FEATURE_MP)
2354#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2355 ui32PipeNum = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum >> 10;
2356 ui32CoreNum = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum & 1023;
2357 bMaster = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum > 32767;
2358#else
2231 ui32CoreNum = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum; 2359 ui32CoreNum = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum;
2232 bMaster = ui32CoreNum > SGX_FEATURE_MP_CORE_COUNT; 2360 bMaster = ui32CoreNum > SGX_FEATURE_MP_CORE_COUNT_3D;
2361#endif
2233 if (bMaster) 2362 if (bMaster)
2234 { 2363 {
2235 2364
@@ -2243,8 +2372,18 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2243 while (ui32OldSeqNum == ui32NewSeqNum); 2372 while (ui32OldSeqNum == ui32NewSeqNum);
2244 } 2373 }
2245 else 2374 else
2375#endif
2246 { 2376 {
2247 2377
2378#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2379 ui32OldSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_PIPE_SELECT(BREAKPOINT, ui32CoreNum, ui32PipeNum));
2380 OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_PIPE_SELECT(BREAKPOINT_TRAP, ui32CoreNum, ui32PipeNum), EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK | EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK);
2381 do
2382 {
2383 ui32NewSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_PIPE_SELECT(BREAKPOINT, ui32CoreNum, ui32PipeNum));
2384 }
2385 while (ui32OldSeqNum == ui32NewSeqNum);
2386#else
2248 ui32OldSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum)); 2387 ui32OldSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum));
2249 OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP, ui32CoreNum), EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK | EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK); 2388 OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP, ui32CoreNum), EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK | EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK);
2250 do 2389 do
@@ -2252,6 +2391,7 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2252 ui32NewSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum)); 2391 ui32NewSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum));
2253 } 2392 }
2254 while (ui32OldSeqNum == ui32NewSeqNum); 2393 while (ui32OldSeqNum == ui32NewSeqNum);
2394#endif
2255 } 2395 }
2256#endif 2396#endif
2257 return PVRSRV_OK; 2397 return PVRSRV_OK;
@@ -2291,7 +2431,7 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2291 case SGX_MISC_INFO_REQUEST_SGXREV: 2431 case SGX_MISC_INFO_REQUEST_SGXREV:
2292 { 2432 {
2293 PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures; 2433 PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
2294 eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode); 2434 eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode, hDevMemContext);
2295 if(eError != PVRSRV_OK) 2435 if(eError != PVRSRV_OK)
2296 { 2436 {
2297 PVR_DPF((PVR_DBG_ERROR, "An error occurred in SGXGetMiscInfoUkernel: %d\n", 2437 PVR_DPF((PVR_DBG_ERROR, "An error occurred in SGXGetMiscInfoUkernel: %d\n",
@@ -2481,6 +2621,7 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2481 &sCommandData, 2621 &sCommandData,
2482 KERNEL_ID, 2622 KERNEL_ID,
2483 0, 2623 0,
2624 hDevMemContext,
2484 IMG_FALSE); 2625 IMG_FALSE);
2485 return eError; 2626 return eError;
2486 } 2627 }
@@ -2535,6 +2676,8 @@ PVRSRV_ERROR SGXReadHWPerfCBKM(IMG_HANDLE hDevHandle,
2535 SGXMKIF_HWPERF_CB_ENTRY *psMKPerfEntry = &psHWPerfCB->psHWPerfCBData[psHWPerfCB->ui32Roff]; 2676 SGXMKIF_HWPERF_CB_ENTRY *psMKPerfEntry = &psHWPerfCB->psHWPerfCBData[psHWPerfCB->ui32Roff];
2536 2677
2537 psClientHWPerfEntry[i].ui32FrameNo = psMKPerfEntry->ui32FrameNo; 2678 psClientHWPerfEntry[i].ui32FrameNo = psMKPerfEntry->ui32FrameNo;
2679 psClientHWPerfEntry[i].ui32PID = psMKPerfEntry->ui32PID;
2680 psClientHWPerfEntry[i].ui32RTData = psMKPerfEntry->ui32RTData;
2538 psClientHWPerfEntry[i].ui32Type = psMKPerfEntry->ui32Type; 2681 psClientHWPerfEntry[i].ui32Type = psMKPerfEntry->ui32Type;
2539 psClientHWPerfEntry[i].ui32Ordinal = psMKPerfEntry->ui32Ordinal; 2682 psClientHWPerfEntry[i].ui32Ordinal = psMKPerfEntry->ui32Ordinal;
2540 psClientHWPerfEntry[i].ui32Info = psMKPerfEntry->ui32Info; 2683 psClientHWPerfEntry[i].ui32Info = psMKPerfEntry->ui32Info;
@@ -2545,6 +2688,10 @@ PVRSRV_ERROR SGXReadHWPerfCBKM(IMG_HANDLE hDevHandle,
2545 &psMKPerfEntry->ui32Counters[0][0], 2688 &psMKPerfEntry->ui32Counters[0][0],
2546 sizeof(psMKPerfEntry->ui32Counters)); 2689 sizeof(psMKPerfEntry->ui32Counters));
2547 2690
2691 OSMemCopy(&psClientHWPerfEntry[i].ui32MiscCounters[0][0],
2692 &psMKPerfEntry->ui32MiscCounters[0][0],
2693 sizeof(psMKPerfEntry->ui32MiscCounters));
2694
2548 psHWPerfCB->ui32Roff = (psHWPerfCB->ui32Roff + 1) & (SGXMKIF_HWPERF_CB_SIZE - 1); 2695 psHWPerfCB->ui32Roff = (psHWPerfCB->ui32Roff + 1) & (SGXMKIF_HWPERF_CB_SIZE - 1);
2549 } 2696 }
2550 2697
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 16:45:53 -0400