aboutsummaryrefslogtreecommitdiffstats
path: root/arch/x86/kernel/apic/io_apic.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/x86/kernel/apic/io_apic.c')
-rw-r--r--arch/x86/kernel/apic/io_apic.c4160
1 files changed, 4160 insertions, 0 deletions
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
new file mode 100644
index 00000000000..00e6071cefc
--- /dev/null
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -0,0 +1,4160 @@
1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/pci.h>
29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
32#include <linux/module.h>
33#include <linux/sysdev.h>
34#include <linux/msi.h>
35#include <linux/htirq.h>
36#include <linux/freezer.h>
37#include <linux/kthread.h>
38#include <linux/jiffies.h> /* time_after() */
39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
44#include <linux/hpet.h>
45
46#include <asm/idle.h>
47#include <asm/io.h>
48#include <asm/smp.h>
49#include <asm/cpu.h>
50#include <asm/desc.h>
51#include <asm/proto.h>
52#include <asm/acpi.h>
53#include <asm/dma.h>
54#include <asm/timer.h>
55#include <asm/i8259.h>
56#include <asm/nmi.h>
57#include <asm/msidef.h>
58#include <asm/hypertransport.h>
59#include <asm/setup.h>
60#include <asm/irq_remapping.h>
61#include <asm/hpet.h>
62#include <asm/uv/uv_hub.h>
63#include <asm/uv/uv_irq.h>
64
65#include <asm/apic.h>
66
67#define __apicdebuginit(type) static type __init
68
69/*
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
72 */
73int sis_apic_bug = -1;
74
75static DEFINE_SPINLOCK(ioapic_lock);
76static DEFINE_SPINLOCK(vector_lock);
77
78/*
79 * # of IRQ routing registers
80 */
81int nr_ioapic_registers[MAX_IO_APICS];
82
83/* I/O APIC entries */
84struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
85int nr_ioapics;
86
87/* MP IRQ source entries */
88struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
89
90/* # of MP IRQ source entries */
91int mp_irq_entries;
92
93#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94int mp_bus_id_to_type[MAX_MP_BUSSES];
95#endif
96
97DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
98
99int skip_ioapic_setup;
100
101void arch_disable_smp_support(void)
102{
103#ifdef CONFIG_PCI
104 noioapicquirk = 1;
105 noioapicreroute = -1;
106#endif
107 skip_ioapic_setup = 1;
108}
109
110static int __init parse_noapic(char *str)
111{
112 /* disable IO-APIC */
113 arch_disable_smp_support();
114 return 0;
115}
116early_param("noapic", parse_noapic);
117
118struct irq_pin_list;
119
120/*
121 * This is performance-critical, we want to do it O(1)
122 *
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
125 */
126
127struct irq_pin_list {
128 int apic, pin;
129 struct irq_pin_list *next;
130};
131
132static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
133{
134 struct irq_pin_list *pin;
135 int node;
136
137 node = cpu_to_node(cpu);
138
139 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
140
141 return pin;
142}
143
144struct irq_cfg {
145 struct irq_pin_list *irq_2_pin;
146 cpumask_var_t domain;
147 cpumask_var_t old_domain;
148 unsigned move_cleanup_count;
149 u8 vector;
150 u8 move_in_progress : 1;
151#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending : 1;
153#endif
154};
155
156/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157#ifdef CONFIG_SPARSE_IRQ
158static struct irq_cfg irq_cfgx[] = {
159#else
160static struct irq_cfg irq_cfgx[NR_IRQS] = {
161#endif
162 [0] = { .vector = IRQ0_VECTOR, },
163 [1] = { .vector = IRQ1_VECTOR, },
164 [2] = { .vector = IRQ2_VECTOR, },
165 [3] = { .vector = IRQ3_VECTOR, },
166 [4] = { .vector = IRQ4_VECTOR, },
167 [5] = { .vector = IRQ5_VECTOR, },
168 [6] = { .vector = IRQ6_VECTOR, },
169 [7] = { .vector = IRQ7_VECTOR, },
170 [8] = { .vector = IRQ8_VECTOR, },
171 [9] = { .vector = IRQ9_VECTOR, },
172 [10] = { .vector = IRQ10_VECTOR, },
173 [11] = { .vector = IRQ11_VECTOR, },
174 [12] = { .vector = IRQ12_VECTOR, },
175 [13] = { .vector = IRQ13_VECTOR, },
176 [14] = { .vector = IRQ14_VECTOR, },
177 [15] = { .vector = IRQ15_VECTOR, },
178};
179
180int __init arch_early_irq_init(void)
181{
182 struct irq_cfg *cfg;
183 struct irq_desc *desc;
184 int count;
185 int i;
186
187 cfg = irq_cfgx;
188 count = ARRAY_SIZE(irq_cfgx);
189
190 for (i = 0; i < count; i++) {
191 desc = irq_to_desc(i);
192 desc->chip_data = &cfg[i];
193 alloc_bootmem_cpumask_var(&cfg[i].domain);
194 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195 if (i < NR_IRQS_LEGACY)
196 cpumask_setall(cfg[i].domain);
197 }
198
199 return 0;
200}
201
202#ifdef CONFIG_SPARSE_IRQ
203static struct irq_cfg *irq_cfg(unsigned int irq)
204{
205 struct irq_cfg *cfg = NULL;
206 struct irq_desc *desc;
207
208 desc = irq_to_desc(irq);
209 if (desc)
210 cfg = desc->chip_data;
211
212 return cfg;
213}
214
215static struct irq_cfg *get_one_free_irq_cfg(int cpu)
216{
217 struct irq_cfg *cfg;
218 int node;
219
220 node = cpu_to_node(cpu);
221
222 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
223 if (cfg) {
224 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
225 kfree(cfg);
226 cfg = NULL;
227 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
228 GFP_ATOMIC, node)) {
229 free_cpumask_var(cfg->domain);
230 kfree(cfg);
231 cfg = NULL;
232 } else {
233 cpumask_clear(cfg->domain);
234 cpumask_clear(cfg->old_domain);
235 }
236 }
237
238 return cfg;
239}
240
241int arch_init_chip_data(struct irq_desc *desc, int cpu)
242{
243 struct irq_cfg *cfg;
244
245 cfg = desc->chip_data;
246 if (!cfg) {
247 desc->chip_data = get_one_free_irq_cfg(cpu);
248 if (!desc->chip_data) {
249 printk(KERN_ERR "can not alloc irq_cfg\n");
250 BUG_ON(1);
251 }
252 }
253
254 return 0;
255}
256
257#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
258
259static void
260init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
261{
262 struct irq_pin_list *old_entry, *head, *tail, *entry;
263
264 cfg->irq_2_pin = NULL;
265 old_entry = old_cfg->irq_2_pin;
266 if (!old_entry)
267 return;
268
269 entry = get_one_free_irq_2_pin(cpu);
270 if (!entry)
271 return;
272
273 entry->apic = old_entry->apic;
274 entry->pin = old_entry->pin;
275 head = entry;
276 tail = entry;
277 old_entry = old_entry->next;
278 while (old_entry) {
279 entry = get_one_free_irq_2_pin(cpu);
280 if (!entry) {
281 entry = head;
282 while (entry) {
283 head = entry->next;
284 kfree(entry);
285 entry = head;
286 }
287 /* still use the old one */
288 return;
289 }
290 entry->apic = old_entry->apic;
291 entry->pin = old_entry->pin;
292 tail->next = entry;
293 tail = entry;
294 old_entry = old_entry->next;
295 }
296
297 tail->next = NULL;
298 cfg->irq_2_pin = head;
299}
300
301static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
302{
303 struct irq_pin_list *entry, *next;
304
305 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
306 return;
307
308 entry = old_cfg->irq_2_pin;
309
310 while (entry) {
311 next = entry->next;
312 kfree(entry);
313 entry = next;
314 }
315 old_cfg->irq_2_pin = NULL;
316}
317
318void arch_init_copy_chip_data(struct irq_desc *old_desc,
319 struct irq_desc *desc, int cpu)
320{
321 struct irq_cfg *cfg;
322 struct irq_cfg *old_cfg;
323
324 cfg = get_one_free_irq_cfg(cpu);
325
326 if (!cfg)
327 return;
328
329 desc->chip_data = cfg;
330
331 old_cfg = old_desc->chip_data;
332
333 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
334
335 init_copy_irq_2_pin(old_cfg, cfg, cpu);
336}
337
338static void free_irq_cfg(struct irq_cfg *old_cfg)
339{
340 kfree(old_cfg);
341}
342
343void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
344{
345 struct irq_cfg *old_cfg, *cfg;
346
347 old_cfg = old_desc->chip_data;
348 cfg = desc->chip_data;
349
350 if (old_cfg == cfg)
351 return;
352
353 if (old_cfg) {
354 free_irq_2_pin(old_cfg, cfg);
355 free_irq_cfg(old_cfg);
356 old_desc->chip_data = NULL;
357 }
358}
359
360static void
361set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
362{
363 struct irq_cfg *cfg = desc->chip_data;
364
365 if (!cfg->move_in_progress) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc->affinity, mask))
368 cfg->move_desc_pending = 1;
369 }
370}
371#endif
372
373#else
374static struct irq_cfg *irq_cfg(unsigned int irq)
375{
376 return irq < nr_irqs ? irq_cfgx + irq : NULL;
377}
378
379#endif
380
381#ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
382static inline void
383set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
384{
385}
386#endif
387
388struct io_apic {
389 unsigned int index;
390 unsigned int unused[3];
391 unsigned int data;
392};
393
394static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
395{
396 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
397 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
398}
399
400static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
401{
402 struct io_apic __iomem *io_apic = io_apic_base(apic);
403 writel(reg, &io_apic->index);
404 return readl(&io_apic->data);
405}
406
407static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
408{
409 struct io_apic __iomem *io_apic = io_apic_base(apic);
410 writel(reg, &io_apic->index);
411 writel(value, &io_apic->data);
412}
413
414/*
415 * Re-write a value: to be used for read-modify-write
416 * cycles where the read already set up the index register.
417 *
418 * Older SiS APIC requires we rewrite the index register
419 */
420static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
421{
422 struct io_apic __iomem *io_apic = io_apic_base(apic);
423
424 if (sis_apic_bug)
425 writel(reg, &io_apic->index);
426 writel(value, &io_apic->data);
427}
428
429static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
430{
431 struct irq_pin_list *entry;
432 unsigned long flags;
433
434 spin_lock_irqsave(&ioapic_lock, flags);
435 entry = cfg->irq_2_pin;
436 for (;;) {
437 unsigned int reg;
438 int pin;
439
440 if (!entry)
441 break;
442 pin = entry->pin;
443 reg = io_apic_read(entry->apic, 0x10 + pin*2);
444 /* Is the remote IRR bit set? */
445 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
446 spin_unlock_irqrestore(&ioapic_lock, flags);
447 return true;
448 }
449 if (!entry->next)
450 break;
451 entry = entry->next;
452 }
453 spin_unlock_irqrestore(&ioapic_lock, flags);
454
455 return false;
456}
457
458union entry_union {
459 struct { u32 w1, w2; };
460 struct IO_APIC_route_entry entry;
461};
462
463static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
464{
465 union entry_union eu;
466 unsigned long flags;
467 spin_lock_irqsave(&ioapic_lock, flags);
468 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
469 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
470 spin_unlock_irqrestore(&ioapic_lock, flags);
471 return eu.entry;
472}
473
474/*
475 * When we write a new IO APIC routing entry, we need to write the high
476 * word first! If the mask bit in the low word is clear, we will enable
477 * the interrupt, and we need to make sure the entry is fully populated
478 * before that happens.
479 */
480static void
481__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
482{
483 union entry_union eu;
484 eu.entry = e;
485 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
486 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
487}
488
489void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
490{
491 unsigned long flags;
492 spin_lock_irqsave(&ioapic_lock, flags);
493 __ioapic_write_entry(apic, pin, e);
494 spin_unlock_irqrestore(&ioapic_lock, flags);
495}
496
497/*
498 * When we mask an IO APIC routing entry, we need to write the low
499 * word first, in order to set the mask bit before we change the
500 * high bits!
501 */
502static void ioapic_mask_entry(int apic, int pin)
503{
504 unsigned long flags;
505 union entry_union eu = { .entry.mask = 1 };
506
507 spin_lock_irqsave(&ioapic_lock, flags);
508 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
509 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
510 spin_unlock_irqrestore(&ioapic_lock, flags);
511}
512
513#ifdef CONFIG_SMP
514static void send_cleanup_vector(struct irq_cfg *cfg)
515{
516 cpumask_var_t cleanup_mask;
517
518 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
519 unsigned int i;
520 cfg->move_cleanup_count = 0;
521 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
522 cfg->move_cleanup_count++;
523 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
524 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
525 } else {
526 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
527 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
528 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
529 free_cpumask_var(cleanup_mask);
530 }
531 cfg->move_in_progress = 0;
532}
533
534static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
535{
536 int apic, pin;
537 struct irq_pin_list *entry;
538 u8 vector = cfg->vector;
539
540 entry = cfg->irq_2_pin;
541 for (;;) {
542 unsigned int reg;
543
544 if (!entry)
545 break;
546
547 apic = entry->apic;
548 pin = entry->pin;
549#ifdef CONFIG_INTR_REMAP
550 /*
551 * With interrupt-remapping, destination information comes
552 * from interrupt-remapping table entry.
553 */
554 if (!irq_remapped(irq))
555 io_apic_write(apic, 0x11 + pin*2, dest);
556#else
557 io_apic_write(apic, 0x11 + pin*2, dest);
558#endif
559 reg = io_apic_read(apic, 0x10 + pin*2);
560 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
561 reg |= vector;
562 io_apic_modify(apic, 0x10 + pin*2, reg);
563 if (!entry->next)
564 break;
565 entry = entry->next;
566 }
567}
568
569static int
570assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
571
572/*
573 * Either sets desc->affinity to a valid value, and returns
574 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
575 * leaves desc->affinity untouched.
576 */
577static unsigned int
578set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
579{
580 struct irq_cfg *cfg;
581 unsigned int irq;
582
583 if (!cpumask_intersects(mask, cpu_online_mask))
584 return BAD_APICID;
585
586 irq = desc->irq;
587 cfg = desc->chip_data;
588 if (assign_irq_vector(irq, cfg, mask))
589 return BAD_APICID;
590
591 cpumask_and(desc->affinity, cfg->domain, mask);
592 set_extra_move_desc(desc, mask);
593
594 return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
595}
596
597static void
598set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
599{
600 struct irq_cfg *cfg;
601 unsigned long flags;
602 unsigned int dest;
603 unsigned int irq;
604
605 irq = desc->irq;
606 cfg = desc->chip_data;
607
608 spin_lock_irqsave(&ioapic_lock, flags);
609 dest = set_desc_affinity(desc, mask);
610 if (dest != BAD_APICID) {
611 /* Only the high 8 bits are valid. */
612 dest = SET_APIC_LOGICAL_ID(dest);
613 __target_IO_APIC_irq(irq, dest, cfg);
614 }
615 spin_unlock_irqrestore(&ioapic_lock, flags);
616}
617
618static void
619set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
620{
621 struct irq_desc *desc;
622
623 desc = irq_to_desc(irq);
624
625 set_ioapic_affinity_irq_desc(desc, mask);
626}
627#endif /* CONFIG_SMP */
628
629/*
630 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
631 * shared ISA-space IRQs, so we have to support them. We are super
632 * fast in the common case, and fast for shared ISA-space IRQs.
633 */
634static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
635{
636 struct irq_pin_list *entry;
637
638 entry = cfg->irq_2_pin;
639 if (!entry) {
640 entry = get_one_free_irq_2_pin(cpu);
641 if (!entry) {
642 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
643 apic, pin);
644 return;
645 }
646 cfg->irq_2_pin = entry;
647 entry->apic = apic;
648 entry->pin = pin;
649 return;
650 }
651
652 while (entry->next) {
653 /* not again, please */
654 if (entry->apic == apic && entry->pin == pin)
655 return;
656
657 entry = entry->next;
658 }
659
660 entry->next = get_one_free_irq_2_pin(cpu);
661 entry = entry->next;
662 entry->apic = apic;
663 entry->pin = pin;
664}
665
666/*
667 * Reroute an IRQ to a different pin.
668 */
669static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
670 int oldapic, int oldpin,
671 int newapic, int newpin)
672{
673 struct irq_pin_list *entry = cfg->irq_2_pin;
674 int replaced = 0;
675
676 while (entry) {
677 if (entry->apic == oldapic && entry->pin == oldpin) {
678 entry->apic = newapic;
679 entry->pin = newpin;
680 replaced = 1;
681 /* every one is different, right? */
682 break;
683 }
684 entry = entry->next;
685 }
686
687 /* why? call replace before add? */
688 if (!replaced)
689 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
690}
691
692static inline void io_apic_modify_irq(struct irq_cfg *cfg,
693 int mask_and, int mask_or,
694 void (*final)(struct irq_pin_list *entry))
695{
696 int pin;
697 struct irq_pin_list *entry;
698
699 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
700 unsigned int reg;
701 pin = entry->pin;
702 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
703 reg &= mask_and;
704 reg |= mask_or;
705 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
706 if (final)
707 final(entry);
708 }
709}
710
711static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
712{
713 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
714}
715
716#ifdef CONFIG_X86_64
717static void io_apic_sync(struct irq_pin_list *entry)
718{
719 /*
720 * Synchronize the IO-APIC and the CPU by doing
721 * a dummy read from the IO-APIC
722 */
723 struct io_apic __iomem *io_apic;
724 io_apic = io_apic_base(entry->apic);
725 readl(&io_apic->data);
726}
727
728static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
729{
730 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
731}
732#else /* CONFIG_X86_32 */
733static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
734{
735 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
736}
737
738static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
739{
740 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
741 IO_APIC_REDIR_MASKED, NULL);
742}
743
744static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
745{
746 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
747 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
748}
749#endif /* CONFIG_X86_32 */
750
751static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
752{
753 struct irq_cfg *cfg = desc->chip_data;
754 unsigned long flags;
755
756 BUG_ON(!cfg);
757
758 spin_lock_irqsave(&ioapic_lock, flags);
759 __mask_IO_APIC_irq(cfg);
760 spin_unlock_irqrestore(&ioapic_lock, flags);
761}
762
763static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
764{
765 struct irq_cfg *cfg = desc->chip_data;
766 unsigned long flags;
767
768 spin_lock_irqsave(&ioapic_lock, flags);
769 __unmask_IO_APIC_irq(cfg);
770 spin_unlock_irqrestore(&ioapic_lock, flags);
771}
772
773static void mask_IO_APIC_irq(unsigned int irq)
774{
775 struct irq_desc *desc = irq_to_desc(irq);
776
777 mask_IO_APIC_irq_desc(desc);
778}
779static void unmask_IO_APIC_irq(unsigned int irq)
780{
781 struct irq_desc *desc = irq_to_desc(irq);
782
783 unmask_IO_APIC_irq_desc(desc);
784}
785
786static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
787{
788 struct IO_APIC_route_entry entry;
789
790 /* Check delivery_mode to be sure we're not clearing an SMI pin */
791 entry = ioapic_read_entry(apic, pin);
792 if (entry.delivery_mode == dest_SMI)
793 return;
794 /*
795 * Disable it in the IO-APIC irq-routing table:
796 */
797 ioapic_mask_entry(apic, pin);
798}
799
800static void clear_IO_APIC (void)
801{
802 int apic, pin;
803
804 for (apic = 0; apic < nr_ioapics; apic++)
805 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
806 clear_IO_APIC_pin(apic, pin);
807}
808
809#ifdef CONFIG_X86_32
810/*
811 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
812 * specific CPU-side IRQs.
813 */
814
815#define MAX_PIRQS 8
816static int pirq_entries[MAX_PIRQS] = {
817 [0 ... MAX_PIRQS - 1] = -1
818};
819
820static int __init ioapic_pirq_setup(char *str)
821{
822 int i, max;
823 int ints[MAX_PIRQS+1];
824
825 get_options(str, ARRAY_SIZE(ints), ints);
826
827 apic_printk(APIC_VERBOSE, KERN_INFO
828 "PIRQ redirection, working around broken MP-BIOS.\n");
829 max = MAX_PIRQS;
830 if (ints[0] < MAX_PIRQS)
831 max = ints[0];
832
833 for (i = 0; i < max; i++) {
834 apic_printk(APIC_VERBOSE, KERN_DEBUG
835 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
836 /*
837 * PIRQs are mapped upside down, usually.
838 */
839 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
840 }
841 return 1;
842}
843
844__setup("pirq=", ioapic_pirq_setup);
845#endif /* CONFIG_X86_32 */
846
847#ifdef CONFIG_INTR_REMAP
848/* I/O APIC RTE contents at the OS boot up */
849static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
850
851/*
852 * Saves and masks all the unmasked IO-APIC RTE's
853 */
854int save_mask_IO_APIC_setup(void)
855{
856 union IO_APIC_reg_01 reg_01;
857 unsigned long flags;
858 int apic, pin;
859
860 /*
861 * The number of IO-APIC IRQ registers (== #pins):
862 */
863 for (apic = 0; apic < nr_ioapics; apic++) {
864 spin_lock_irqsave(&ioapic_lock, flags);
865 reg_01.raw = io_apic_read(apic, 1);
866 spin_unlock_irqrestore(&ioapic_lock, flags);
867 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
868 }
869
870 for (apic = 0; apic < nr_ioapics; apic++) {
871 early_ioapic_entries[apic] =
872 kzalloc(sizeof(struct IO_APIC_route_entry) *
873 nr_ioapic_registers[apic], GFP_KERNEL);
874 if (!early_ioapic_entries[apic])
875 goto nomem;
876 }
877
878 for (apic = 0; apic < nr_ioapics; apic++)
879 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
880 struct IO_APIC_route_entry entry;
881
882 entry = early_ioapic_entries[apic][pin] =
883 ioapic_read_entry(apic, pin);
884 if (!entry.mask) {
885 entry.mask = 1;
886 ioapic_write_entry(apic, pin, entry);
887 }
888 }
889
890 return 0;
891
892nomem:
893 while (apic >= 0)
894 kfree(early_ioapic_entries[apic--]);
895 memset(early_ioapic_entries, 0,
896 ARRAY_SIZE(early_ioapic_entries));
897
898 return -ENOMEM;
899}
900
901void restore_IO_APIC_setup(void)
902{
903 int apic, pin;
904
905 for (apic = 0; apic < nr_ioapics; apic++) {
906 if (!early_ioapic_entries[apic])
907 break;
908 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
909 ioapic_write_entry(apic, pin,
910 early_ioapic_entries[apic][pin]);
911 kfree(early_ioapic_entries[apic]);
912 early_ioapic_entries[apic] = NULL;
913 }
914}
915
916void reinit_intr_remapped_IO_APIC(int intr_remapping)
917{
918 /*
919 * for now plain restore of previous settings.
920 * TBD: In the case of OS enabling interrupt-remapping,
921 * IO-APIC RTE's need to be setup to point to interrupt-remapping
922 * table entries. for now, do a plain restore, and wait for
923 * the setup_IO_APIC_irqs() to do proper initialization.
924 */
925 restore_IO_APIC_setup();
926}
927#endif
928
929/*
930 * Find the IRQ entry number of a certain pin.
931 */
932static int find_irq_entry(int apic, int pin, int type)
933{
934 int i;
935
936 for (i = 0; i < mp_irq_entries; i++)
937 if (mp_irqs[i].irqtype == type &&
938 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
939 mp_irqs[i].dstapic == MP_APIC_ALL) &&
940 mp_irqs[i].dstirq == pin)
941 return i;
942
943 return -1;
944}
945
946/*
947 * Find the pin to which IRQ[irq] (ISA) is connected
948 */
949static int __init find_isa_irq_pin(int irq, int type)
950{
951 int i;
952
953 for (i = 0; i < mp_irq_entries; i++) {
954 int lbus = mp_irqs[i].srcbus;
955
956 if (test_bit(lbus, mp_bus_not_pci) &&
957 (mp_irqs[i].irqtype == type) &&
958 (mp_irqs[i].srcbusirq == irq))
959
960 return mp_irqs[i].dstirq;
961 }
962 return -1;
963}
964
965static int __init find_isa_irq_apic(int irq, int type)
966{
967 int i;
968
969 for (i = 0; i < mp_irq_entries; i++) {
970 int lbus = mp_irqs[i].srcbus;
971
972 if (test_bit(lbus, mp_bus_not_pci) &&
973 (mp_irqs[i].irqtype == type) &&
974 (mp_irqs[i].srcbusirq == irq))
975 break;
976 }
977 if (i < mp_irq_entries) {
978 int apic;
979 for(apic = 0; apic < nr_ioapics; apic++) {
980 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
981 return apic;
982 }
983 }
984
985 return -1;
986}
987
988/*
989 * Find a specific PCI IRQ entry.
990 * Not an __init, possibly needed by modules
991 */
992static int pin_2_irq(int idx, int apic, int pin);
993
994int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
995{
996 int apic, i, best_guess = -1;
997
998 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
999 bus, slot, pin);
1000 if (test_bit(bus, mp_bus_not_pci)) {
1001 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1002 return -1;
1003 }
1004 for (i = 0; i < mp_irq_entries; i++) {
1005 int lbus = mp_irqs[i].srcbus;
1006
1007 for (apic = 0; apic < nr_ioapics; apic++)
1008 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1009 mp_irqs[i].dstapic == MP_APIC_ALL)
1010 break;
1011
1012 if (!test_bit(lbus, mp_bus_not_pci) &&
1013 !mp_irqs[i].irqtype &&
1014 (bus == lbus) &&
1015 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1016 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1017
1018 if (!(apic || IO_APIC_IRQ(irq)))
1019 continue;
1020
1021 if (pin == (mp_irqs[i].srcbusirq & 3))
1022 return irq;
1023 /*
1024 * Use the first all-but-pin matching entry as a
1025 * best-guess fuzzy result for broken mptables.
1026 */
1027 if (best_guess < 0)
1028 best_guess = irq;
1029 }
1030 }
1031 return best_guess;
1032}
1033
1034EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1035
1036#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1037/*
1038 * EISA Edge/Level control register, ELCR
1039 */
1040static int EISA_ELCR(unsigned int irq)
1041{
1042 if (irq < NR_IRQS_LEGACY) {
1043 unsigned int port = 0x4d0 + (irq >> 3);
1044 return (inb(port) >> (irq & 7)) & 1;
1045 }
1046 apic_printk(APIC_VERBOSE, KERN_INFO
1047 "Broken MPtable reports ISA irq %d\n", irq);
1048 return 0;
1049}
1050
1051#endif
1052
1053/* ISA interrupts are always polarity zero edge triggered,
1054 * when listed as conforming in the MP table. */
1055
1056#define default_ISA_trigger(idx) (0)
1057#define default_ISA_polarity(idx) (0)
1058
1059/* EISA interrupts are always polarity zero and can be edge or level
1060 * trigger depending on the ELCR value. If an interrupt is listed as
1061 * EISA conforming in the MP table, that means its trigger type must
1062 * be read in from the ELCR */
1063
1064#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1065#define default_EISA_polarity(idx) default_ISA_polarity(idx)
1066
1067/* PCI interrupts are always polarity one level triggered,
1068 * when listed as conforming in the MP table. */
1069
1070#define default_PCI_trigger(idx) (1)
1071#define default_PCI_polarity(idx) (1)
1072
1073/* MCA interrupts are always polarity zero level triggered,
1074 * when listed as conforming in the MP table. */
1075
1076#define default_MCA_trigger(idx) (1)
1077#define default_MCA_polarity(idx) default_ISA_polarity(idx)
1078
1079static int MPBIOS_polarity(int idx)
1080{
1081 int bus = mp_irqs[idx].srcbus;
1082 int polarity;
1083
1084 /*
1085 * Determine IRQ line polarity (high active or low active):
1086 */
1087 switch (mp_irqs[idx].irqflag & 3)
1088 {
1089 case 0: /* conforms, ie. bus-type dependent polarity */
1090 if (test_bit(bus, mp_bus_not_pci))
1091 polarity = default_ISA_polarity(idx);
1092 else
1093 polarity = default_PCI_polarity(idx);
1094 break;
1095 case 1: /* high active */
1096 {
1097 polarity = 0;
1098 break;
1099 }
1100 case 2: /* reserved */
1101 {
1102 printk(KERN_WARNING "broken BIOS!!\n");
1103 polarity = 1;
1104 break;
1105 }
1106 case 3: /* low active */
1107 {
1108 polarity = 1;
1109 break;
1110 }
1111 default: /* invalid */
1112 {
1113 printk(KERN_WARNING "broken BIOS!!\n");
1114 polarity = 1;
1115 break;
1116 }
1117 }
1118 return polarity;
1119}
1120
1121static int MPBIOS_trigger(int idx)
1122{
1123 int bus = mp_irqs[idx].srcbus;
1124 int trigger;
1125
1126 /*
1127 * Determine IRQ trigger mode (edge or level sensitive):
1128 */
1129 switch ((mp_irqs[idx].irqflag>>2) & 3)
1130 {
1131 case 0: /* conforms, ie. bus-type dependent */
1132 if (test_bit(bus, mp_bus_not_pci))
1133 trigger = default_ISA_trigger(idx);
1134 else
1135 trigger = default_PCI_trigger(idx);
1136#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1137 switch (mp_bus_id_to_type[bus]) {
1138 case MP_BUS_ISA: /* ISA pin */
1139 {
1140 /* set before the switch */
1141 break;
1142 }
1143 case MP_BUS_EISA: /* EISA pin */
1144 {
1145 trigger = default_EISA_trigger(idx);
1146 break;
1147 }
1148 case MP_BUS_PCI: /* PCI pin */
1149 {
1150 /* set before the switch */
1151 break;
1152 }
1153 case MP_BUS_MCA: /* MCA pin */
1154 {
1155 trigger = default_MCA_trigger(idx);
1156 break;
1157 }
1158 default:
1159 {
1160 printk(KERN_WARNING "broken BIOS!!\n");
1161 trigger = 1;
1162 break;
1163 }
1164 }
1165#endif
1166 break;
1167 case 1: /* edge */
1168 {
1169 trigger = 0;
1170 break;
1171 }
1172 case 2: /* reserved */
1173 {
1174 printk(KERN_WARNING "broken BIOS!!\n");
1175 trigger = 1;
1176 break;
1177 }
1178 case 3: /* level */
1179 {
1180 trigger = 1;
1181 break;
1182 }
1183 default: /* invalid */
1184 {
1185 printk(KERN_WARNING "broken BIOS!!\n");
1186 trigger = 0;
1187 break;
1188 }
1189 }
1190 return trigger;
1191}
1192
1193static inline int irq_polarity(int idx)
1194{
1195 return MPBIOS_polarity(idx);
1196}
1197
1198static inline int irq_trigger(int idx)
1199{
1200 return MPBIOS_trigger(idx);
1201}
1202
1203int (*ioapic_renumber_irq)(int ioapic, int irq);
1204static int pin_2_irq(int idx, int apic, int pin)
1205{
1206 int irq, i;
1207 int bus = mp_irqs[idx].srcbus;
1208
1209 /*
1210 * Debugging check, we are in big trouble if this message pops up!
1211 */
1212 if (mp_irqs[idx].dstirq != pin)
1213 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1214
1215 if (test_bit(bus, mp_bus_not_pci)) {
1216 irq = mp_irqs[idx].srcbusirq;
1217 } else {
1218 /*
1219 * PCI IRQs are mapped in order
1220 */
1221 i = irq = 0;
1222 while (i < apic)
1223 irq += nr_ioapic_registers[i++];
1224 irq += pin;
1225 /*
1226 * For MPS mode, so far only needed by ES7000 platform
1227 */
1228 if (ioapic_renumber_irq)
1229 irq = ioapic_renumber_irq(apic, irq);
1230 }
1231
1232#ifdef CONFIG_X86_32
1233 /*
1234 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1235 */
1236 if ((pin >= 16) && (pin <= 23)) {
1237 if (pirq_entries[pin-16] != -1) {
1238 if (!pirq_entries[pin-16]) {
1239 apic_printk(APIC_VERBOSE, KERN_DEBUG
1240 "disabling PIRQ%d\n", pin-16);
1241 } else {
1242 irq = pirq_entries[pin-16];
1243 apic_printk(APIC_VERBOSE, KERN_DEBUG
1244 "using PIRQ%d -> IRQ %d\n",
1245 pin-16, irq);
1246 }
1247 }
1248 }
1249#endif
1250
1251 return irq;
1252}
1253
1254void lock_vector_lock(void)
1255{
1256 /* Used to the online set of cpus does not change
1257 * during assign_irq_vector.
1258 */
1259 spin_lock(&vector_lock);
1260}
1261
1262void unlock_vector_lock(void)
1263{
1264 spin_unlock(&vector_lock);
1265}
1266
1267static int
1268__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1269{
1270 /*
1271 * NOTE! The local APIC isn't very good at handling
1272 * multiple interrupts at the same interrupt level.
1273 * As the interrupt level is determined by taking the
1274 * vector number and shifting that right by 4, we
1275 * want to spread these out a bit so that they don't
1276 * all fall in the same interrupt level.
1277 *
1278 * Also, we've got to be careful not to trash gate
1279 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1280 */
1281 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1282 unsigned int old_vector;
1283 int cpu, err;
1284 cpumask_var_t tmp_mask;
1285
1286 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1287 return -EBUSY;
1288
1289 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1290 return -ENOMEM;
1291
1292 old_vector = cfg->vector;
1293 if (old_vector) {
1294 cpumask_and(tmp_mask, mask, cpu_online_mask);
1295 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1296 if (!cpumask_empty(tmp_mask)) {
1297 free_cpumask_var(tmp_mask);
1298 return 0;
1299 }
1300 }
1301
1302 /* Only try and allocate irqs on cpus that are present */
1303 err = -ENOSPC;
1304 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1305 int new_cpu;
1306 int vector, offset;
1307
1308 apic->vector_allocation_domain(cpu, tmp_mask);
1309
1310 vector = current_vector;
1311 offset = current_offset;
1312next:
1313 vector += 8;
1314 if (vector >= first_system_vector) {
1315 /* If out of vectors on large boxen, must share them. */
1316 offset = (offset + 1) % 8;
1317 vector = FIRST_DEVICE_VECTOR + offset;
1318 }
1319 if (unlikely(current_vector == vector))
1320 continue;
1321
1322 if (test_bit(vector, used_vectors))
1323 goto next;
1324
1325 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1326 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1327 goto next;
1328 /* Found one! */
1329 current_vector = vector;
1330 current_offset = offset;
1331 if (old_vector) {
1332 cfg->move_in_progress = 1;
1333 cpumask_copy(cfg->old_domain, cfg->domain);
1334 }
1335 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1336 per_cpu(vector_irq, new_cpu)[vector] = irq;
1337 cfg->vector = vector;
1338 cpumask_copy(cfg->domain, tmp_mask);
1339 err = 0;
1340 break;
1341 }
1342 free_cpumask_var(tmp_mask);
1343 return err;
1344}
1345
1346static int
1347assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1348{
1349 int err;
1350 unsigned long flags;
1351
1352 spin_lock_irqsave(&vector_lock, flags);
1353 err = __assign_irq_vector(irq, cfg, mask);
1354 spin_unlock_irqrestore(&vector_lock, flags);
1355 return err;
1356}
1357
1358static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1359{
1360 int cpu, vector;
1361
1362 BUG_ON(!cfg->vector);
1363
1364 vector = cfg->vector;
1365 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1366 per_cpu(vector_irq, cpu)[vector] = -1;
1367
1368 cfg->vector = 0;
1369 cpumask_clear(cfg->domain);
1370
1371 if (likely(!cfg->move_in_progress))
1372 return;
1373 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1374 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1375 vector++) {
1376 if (per_cpu(vector_irq, cpu)[vector] != irq)
1377 continue;
1378 per_cpu(vector_irq, cpu)[vector] = -1;
1379 break;
1380 }
1381 }
1382 cfg->move_in_progress = 0;
1383}
1384
1385void __setup_vector_irq(int cpu)
1386{
1387 /* Initialize vector_irq on a new cpu */
1388 /* This function must be called with vector_lock held */
1389 int irq, vector;
1390 struct irq_cfg *cfg;
1391 struct irq_desc *desc;
1392
1393 /* Mark the inuse vectors */
1394 for_each_irq_desc(irq, desc) {
1395 cfg = desc->chip_data;
1396 if (!cpumask_test_cpu(cpu, cfg->domain))
1397 continue;
1398 vector = cfg->vector;
1399 per_cpu(vector_irq, cpu)[vector] = irq;
1400 }
1401 /* Mark the free vectors */
1402 for (vector = 0; vector < NR_VECTORS; ++vector) {
1403 irq = per_cpu(vector_irq, cpu)[vector];
1404 if (irq < 0)
1405 continue;
1406
1407 cfg = irq_cfg(irq);
1408 if (!cpumask_test_cpu(cpu, cfg->domain))
1409 per_cpu(vector_irq, cpu)[vector] = -1;
1410 }
1411}
1412
1413static struct irq_chip ioapic_chip;
1414#ifdef CONFIG_INTR_REMAP
1415static struct irq_chip ir_ioapic_chip;
1416#endif
1417
1418#define IOAPIC_AUTO -1
1419#define IOAPIC_EDGE 0
1420#define IOAPIC_LEVEL 1
1421
1422#ifdef CONFIG_X86_32
1423static inline int IO_APIC_irq_trigger(int irq)
1424{
1425 int apic, idx, pin;
1426
1427 for (apic = 0; apic < nr_ioapics; apic++) {
1428 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1429 idx = find_irq_entry(apic, pin, mp_INT);
1430 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1431 return irq_trigger(idx);
1432 }
1433 }
1434 /*
1435 * nonexistent IRQs are edge default
1436 */
1437 return 0;
1438}
1439#else
1440static inline int IO_APIC_irq_trigger(int irq)
1441{
1442 return 1;
1443}
1444#endif
1445
1446static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1447{
1448
1449 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1450 trigger == IOAPIC_LEVEL)
1451 desc->status |= IRQ_LEVEL;
1452 else
1453 desc->status &= ~IRQ_LEVEL;
1454
1455#ifdef CONFIG_INTR_REMAP
1456 if (irq_remapped(irq)) {
1457 desc->status |= IRQ_MOVE_PCNTXT;
1458 if (trigger)
1459 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1460 handle_fasteoi_irq,
1461 "fasteoi");
1462 else
1463 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1464 handle_edge_irq, "edge");
1465 return;
1466 }
1467#endif
1468 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1469 trigger == IOAPIC_LEVEL)
1470 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1471 handle_fasteoi_irq,
1472 "fasteoi");
1473 else
1474 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1475 handle_edge_irq, "edge");
1476}
1477
1478int setup_ioapic_entry(int apic_id, int irq,
1479 struct IO_APIC_route_entry *entry,
1480 unsigned int destination, int trigger,
1481 int polarity, int vector)
1482{
1483 /*
1484 * add it to the IO-APIC irq-routing table:
1485 */
1486 memset(entry,0,sizeof(*entry));
1487
1488#ifdef CONFIG_INTR_REMAP
1489 if (intr_remapping_enabled) {
1490 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1491 struct irte irte;
1492 struct IR_IO_APIC_route_entry *ir_entry =
1493 (struct IR_IO_APIC_route_entry *) entry;
1494 int index;
1495
1496 if (!iommu)
1497 panic("No mapping iommu for ioapic %d\n", apic_id);
1498
1499 index = alloc_irte(iommu, irq, 1);
1500 if (index < 0)
1501 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1502
1503 memset(&irte, 0, sizeof(irte));
1504
1505 irte.present = 1;
1506 irte.dst_mode = apic->irq_dest_mode;
1507 irte.trigger_mode = trigger;
1508 irte.dlvry_mode = apic->irq_delivery_mode;
1509 irte.vector = vector;
1510 irte.dest_id = IRTE_DEST(destination);
1511
1512 modify_irte(irq, &irte);
1513
1514 ir_entry->index2 = (index >> 15) & 0x1;
1515 ir_entry->zero = 0;
1516 ir_entry->format = 1;
1517 ir_entry->index = (index & 0x7fff);
1518 } else
1519#endif
1520 {
1521 entry->delivery_mode = apic->irq_delivery_mode;
1522 entry->dest_mode = apic->irq_dest_mode;
1523 entry->dest = destination;
1524 }
1525
1526 entry->mask = 0; /* enable IRQ */
1527 entry->trigger = trigger;
1528 entry->polarity = polarity;
1529 entry->vector = vector;
1530
1531 /* Mask level triggered irqs.
1532 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1533 */
1534 if (trigger)
1535 entry->mask = 1;
1536 return 0;
1537}
1538
1539static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1540 int trigger, int polarity)
1541{
1542 struct irq_cfg *cfg;
1543 struct IO_APIC_route_entry entry;
1544 unsigned int dest;
1545
1546 if (!IO_APIC_IRQ(irq))
1547 return;
1548
1549 cfg = desc->chip_data;
1550
1551 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1552 return;
1553
1554 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1555
1556 apic_printk(APIC_VERBOSE,KERN_DEBUG
1557 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1558 "IRQ %d Mode:%i Active:%i)\n",
1559 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1560 irq, trigger, polarity);
1561
1562
1563 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1564 dest, trigger, polarity, cfg->vector)) {
1565 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1566 mp_ioapics[apic_id].apicid, pin);
1567 __clear_irq_vector(irq, cfg);
1568 return;
1569 }
1570
1571 ioapic_register_intr(irq, desc, trigger);
1572 if (irq < NR_IRQS_LEGACY)
1573 disable_8259A_irq(irq);
1574
1575 ioapic_write_entry(apic_id, pin, entry);
1576}
1577
1578static void __init setup_IO_APIC_irqs(void)
1579{
1580 int apic_id, pin, idx, irq;
1581 int notcon = 0;
1582 struct irq_desc *desc;
1583 struct irq_cfg *cfg;
1584 int cpu = boot_cpu_id;
1585
1586 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1587
1588 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1589 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1590
1591 idx = find_irq_entry(apic_id, pin, mp_INT);
1592 if (idx == -1) {
1593 if (!notcon) {
1594 notcon = 1;
1595 apic_printk(APIC_VERBOSE,
1596 KERN_DEBUG " %d-%d",
1597 mp_ioapics[apic_id].apicid, pin);
1598 } else
1599 apic_printk(APIC_VERBOSE, " %d-%d",
1600 mp_ioapics[apic_id].apicid, pin);
1601 continue;
1602 }
1603 if (notcon) {
1604 apic_printk(APIC_VERBOSE,
1605 " (apicid-pin) not connected\n");
1606 notcon = 0;
1607 }
1608
1609 irq = pin_2_irq(idx, apic_id, pin);
1610
1611 /*
1612 * Skip the timer IRQ if there's a quirk handler
1613 * installed and if it returns 1:
1614 */
1615 if (apic->multi_timer_check &&
1616 apic->multi_timer_check(apic_id, irq))
1617 continue;
1618
1619 desc = irq_to_desc_alloc_cpu(irq, cpu);
1620 if (!desc) {
1621 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1622 continue;
1623 }
1624 cfg = desc->chip_data;
1625 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1626
1627 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1628 irq_trigger(idx), irq_polarity(idx));
1629 }
1630 }
1631
1632 if (notcon)
1633 apic_printk(APIC_VERBOSE,
1634 " (apicid-pin) not connected\n");
1635}
1636
1637/*
1638 * Set up the timer pin, possibly with the 8259A-master behind.
1639 */
1640static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1641 int vector)
1642{
1643 struct IO_APIC_route_entry entry;
1644
1645#ifdef CONFIG_INTR_REMAP
1646 if (intr_remapping_enabled)
1647 return;
1648#endif
1649
1650 memset(&entry, 0, sizeof(entry));
1651
1652 /*
1653 * We use logical delivery to get the timer IRQ
1654 * to the first CPU.
1655 */
1656 entry.dest_mode = apic->irq_dest_mode;
1657 entry.mask = 0; /* don't mask IRQ for edge */
1658 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1659 entry.delivery_mode = apic->irq_delivery_mode;
1660 entry.polarity = 0;
1661 entry.trigger = 0;
1662 entry.vector = vector;
1663
1664 /*
1665 * The timer IRQ doesn't have to know that behind the
1666 * scene we may have a 8259A-master in AEOI mode ...
1667 */
1668 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1669
1670 /*
1671 * Add it to the IO-APIC irq-routing table:
1672 */
1673 ioapic_write_entry(apic_id, pin, entry);
1674}
1675
1676
1677__apicdebuginit(void) print_IO_APIC(void)
1678{
1679 int apic, i;
1680 union IO_APIC_reg_00 reg_00;
1681 union IO_APIC_reg_01 reg_01;
1682 union IO_APIC_reg_02 reg_02;
1683 union IO_APIC_reg_03 reg_03;
1684 unsigned long flags;
1685 struct irq_cfg *cfg;
1686 struct irq_desc *desc;
1687 unsigned int irq;
1688
1689 if (apic_verbosity == APIC_QUIET)
1690 return;
1691
1692 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1693 for (i = 0; i < nr_ioapics; i++)
1694 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1695 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1696
1697 /*
1698 * We are a bit conservative about what we expect. We have to
1699 * know about every hardware change ASAP.
1700 */
1701 printk(KERN_INFO "testing the IO APIC.......................\n");
1702
1703 for (apic = 0; apic < nr_ioapics; apic++) {
1704
1705 spin_lock_irqsave(&ioapic_lock, flags);
1706 reg_00.raw = io_apic_read(apic, 0);
1707 reg_01.raw = io_apic_read(apic, 1);
1708 if (reg_01.bits.version >= 0x10)
1709 reg_02.raw = io_apic_read(apic, 2);
1710 if (reg_01.bits.version >= 0x20)
1711 reg_03.raw = io_apic_read(apic, 3);
1712 spin_unlock_irqrestore(&ioapic_lock, flags);
1713
1714 printk("\n");
1715 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1716 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1717 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1718 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1719 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1720
1721 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1722 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1723
1724 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1725 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1726
1727 /*
1728 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1729 * but the value of reg_02 is read as the previous read register
1730 * value, so ignore it if reg_02 == reg_01.
1731 */
1732 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1733 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1734 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1735 }
1736
1737 /*
1738 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1739 * or reg_03, but the value of reg_0[23] is read as the previous read
1740 * register value, so ignore it if reg_03 == reg_0[12].
1741 */
1742 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1743 reg_03.raw != reg_01.raw) {
1744 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1745 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1746 }
1747
1748 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1749
1750 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1751 " Stat Dmod Deli Vect: \n");
1752
1753 for (i = 0; i <= reg_01.bits.entries; i++) {
1754 struct IO_APIC_route_entry entry;
1755
1756 entry = ioapic_read_entry(apic, i);
1757
1758 printk(KERN_DEBUG " %02x %03X ",
1759 i,
1760 entry.dest
1761 );
1762
1763 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1764 entry.mask,
1765 entry.trigger,
1766 entry.irr,
1767 entry.polarity,
1768 entry.delivery_status,
1769 entry.dest_mode,
1770 entry.delivery_mode,
1771 entry.vector
1772 );
1773 }
1774 }
1775 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1776 for_each_irq_desc(irq, desc) {
1777 struct irq_pin_list *entry;
1778
1779 cfg = desc->chip_data;
1780 entry = cfg->irq_2_pin;
1781 if (!entry)
1782 continue;
1783 printk(KERN_DEBUG "IRQ%d ", irq);
1784 for (;;) {
1785 printk("-> %d:%d", entry->apic, entry->pin);
1786 if (!entry->next)
1787 break;
1788 entry = entry->next;
1789 }
1790 printk("\n");
1791 }
1792
1793 printk(KERN_INFO ".................................... done.\n");
1794
1795 return;
1796}
1797
1798__apicdebuginit(void) print_APIC_bitfield(int base)
1799{
1800 unsigned int v;
1801 int i, j;
1802
1803 if (apic_verbosity == APIC_QUIET)
1804 return;
1805
1806 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1807 for (i = 0; i < 8; i++) {
1808 v = apic_read(base + i*0x10);
1809 for (j = 0; j < 32; j++) {
1810 if (v & (1<<j))
1811 printk("1");
1812 else
1813 printk("0");
1814 }
1815 printk("\n");
1816 }
1817}
1818
1819__apicdebuginit(void) print_local_APIC(void *dummy)
1820{
1821 unsigned int v, ver, maxlvt;
1822 u64 icr;
1823
1824 if (apic_verbosity == APIC_QUIET)
1825 return;
1826
1827 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1828 smp_processor_id(), hard_smp_processor_id());
1829 v = apic_read(APIC_ID);
1830 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1831 v = apic_read(APIC_LVR);
1832 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1833 ver = GET_APIC_VERSION(v);
1834 maxlvt = lapic_get_maxlvt();
1835
1836 v = apic_read(APIC_TASKPRI);
1837 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1838
1839 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1840 if (!APIC_XAPIC(ver)) {
1841 v = apic_read(APIC_ARBPRI);
1842 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1843 v & APIC_ARBPRI_MASK);
1844 }
1845 v = apic_read(APIC_PROCPRI);
1846 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1847 }
1848
1849 /*
1850 * Remote read supported only in the 82489DX and local APIC for
1851 * Pentium processors.
1852 */
1853 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1854 v = apic_read(APIC_RRR);
1855 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1856 }
1857
1858 v = apic_read(APIC_LDR);
1859 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1860 if (!x2apic_enabled()) {
1861 v = apic_read(APIC_DFR);
1862 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1863 }
1864 v = apic_read(APIC_SPIV);
1865 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1866
1867 printk(KERN_DEBUG "... APIC ISR field:\n");
1868 print_APIC_bitfield(APIC_ISR);
1869 printk(KERN_DEBUG "... APIC TMR field:\n");
1870 print_APIC_bitfield(APIC_TMR);
1871 printk(KERN_DEBUG "... APIC IRR field:\n");
1872 print_APIC_bitfield(APIC_IRR);
1873
1874 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1875 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1876 apic_write(APIC_ESR, 0);
1877
1878 v = apic_read(APIC_ESR);
1879 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1880 }
1881
1882 icr = apic_icr_read();
1883 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1884 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1885
1886 v = apic_read(APIC_LVTT);
1887 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1888
1889 if (maxlvt > 3) { /* PC is LVT#4. */
1890 v = apic_read(APIC_LVTPC);
1891 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1892 }
1893 v = apic_read(APIC_LVT0);
1894 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1895 v = apic_read(APIC_LVT1);
1896 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1897
1898 if (maxlvt > 2) { /* ERR is LVT#3. */
1899 v = apic_read(APIC_LVTERR);
1900 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1901 }
1902
1903 v = apic_read(APIC_TMICT);
1904 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1905 v = apic_read(APIC_TMCCT);
1906 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1907 v = apic_read(APIC_TDCR);
1908 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1909 printk("\n");
1910}
1911
1912__apicdebuginit(void) print_all_local_APICs(void)
1913{
1914 int cpu;
1915
1916 preempt_disable();
1917 for_each_online_cpu(cpu)
1918 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1919 preempt_enable();
1920}
1921
1922__apicdebuginit(void) print_PIC(void)
1923{
1924 unsigned int v;
1925 unsigned long flags;
1926
1927 if (apic_verbosity == APIC_QUIET)
1928 return;
1929
1930 printk(KERN_DEBUG "\nprinting PIC contents\n");
1931
1932 spin_lock_irqsave(&i8259A_lock, flags);
1933
1934 v = inb(0xa1) << 8 | inb(0x21);
1935 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1936
1937 v = inb(0xa0) << 8 | inb(0x20);
1938 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1939
1940 outb(0x0b,0xa0);
1941 outb(0x0b,0x20);
1942 v = inb(0xa0) << 8 | inb(0x20);
1943 outb(0x0a,0xa0);
1944 outb(0x0a,0x20);
1945
1946 spin_unlock_irqrestore(&i8259A_lock, flags);
1947
1948 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1949
1950 v = inb(0x4d1) << 8 | inb(0x4d0);
1951 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1952}
1953
1954__apicdebuginit(int) print_all_ICs(void)
1955{
1956 print_PIC();
1957 print_all_local_APICs();
1958 print_IO_APIC();
1959
1960 return 0;
1961}
1962
1963fs_initcall(print_all_ICs);
1964
1965
1966/* Where if anywhere is the i8259 connect in external int mode */
1967static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1968
1969void __init enable_IO_APIC(void)
1970{
1971 union IO_APIC_reg_01 reg_01;
1972 int i8259_apic, i8259_pin;
1973 int apic;
1974 unsigned long flags;
1975
1976 /*
1977 * The number of IO-APIC IRQ registers (== #pins):
1978 */
1979 for (apic = 0; apic < nr_ioapics; apic++) {
1980 spin_lock_irqsave(&ioapic_lock, flags);
1981 reg_01.raw = io_apic_read(apic, 1);
1982 spin_unlock_irqrestore(&ioapic_lock, flags);
1983 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1984 }
1985 for(apic = 0; apic < nr_ioapics; apic++) {
1986 int pin;
1987 /* See if any of the pins is in ExtINT mode */
1988 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1989 struct IO_APIC_route_entry entry;
1990 entry = ioapic_read_entry(apic, pin);
1991
1992 /* If the interrupt line is enabled and in ExtInt mode
1993 * I have found the pin where the i8259 is connected.
1994 */
1995 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1996 ioapic_i8259.apic = apic;
1997 ioapic_i8259.pin = pin;
1998 goto found_i8259;
1999 }
2000 }
2001 }
2002 found_i8259:
2003 /* Look to see what if the MP table has reported the ExtINT */
2004 /* If we could not find the appropriate pin by looking at the ioapic
2005 * the i8259 probably is not connected the ioapic but give the
2006 * mptable a chance anyway.
2007 */
2008 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2009 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2010 /* Trust the MP table if nothing is setup in the hardware */
2011 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2012 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2013 ioapic_i8259.pin = i8259_pin;
2014 ioapic_i8259.apic = i8259_apic;
2015 }
2016 /* Complain if the MP table and the hardware disagree */
2017 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2018 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2019 {
2020 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2021 }
2022
2023 /*
2024 * Do not trust the IO-APIC being empty at bootup
2025 */
2026 clear_IO_APIC();
2027}
2028
2029/*
2030 * Not an __init, needed by the reboot code
2031 */
2032void disable_IO_APIC(void)
2033{
2034 /*
2035 * Clear the IO-APIC before rebooting:
2036 */
2037 clear_IO_APIC();
2038
2039 /*
2040 * If the i8259 is routed through an IOAPIC
2041 * Put that IOAPIC in virtual wire mode
2042 * so legacy interrupts can be delivered.
2043 */
2044 if (ioapic_i8259.pin != -1) {
2045 struct IO_APIC_route_entry entry;
2046
2047 memset(&entry, 0, sizeof(entry));
2048 entry.mask = 0; /* Enabled */
2049 entry.trigger = 0; /* Edge */
2050 entry.irr = 0;
2051 entry.polarity = 0; /* High */
2052 entry.delivery_status = 0;
2053 entry.dest_mode = 0; /* Physical */
2054 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2055 entry.vector = 0;
2056 entry.dest = read_apic_id();
2057
2058 /*
2059 * Add it to the IO-APIC irq-routing table:
2060 */
2061 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2062 }
2063
2064 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2065}
2066
2067#ifdef CONFIG_X86_32
2068/*
2069 * function to set the IO-APIC physical IDs based on the
2070 * values stored in the MPC table.
2071 *
2072 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2073 */
2074
2075static void __init setup_ioapic_ids_from_mpc(void)
2076{
2077 union IO_APIC_reg_00 reg_00;
2078 physid_mask_t phys_id_present_map;
2079 int apic_id;
2080 int i;
2081 unsigned char old_id;
2082 unsigned long flags;
2083
2084 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2085 return;
2086
2087 /*
2088 * Don't check I/O APIC IDs for xAPIC systems. They have
2089 * no meaning without the serial APIC bus.
2090 */
2091 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2092 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2093 return;
2094 /*
2095 * This is broken; anything with a real cpu count has to
2096 * circumvent this idiocy regardless.
2097 */
2098 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2099
2100 /*
2101 * Set the IOAPIC ID to the value stored in the MPC table.
2102 */
2103 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2104
2105 /* Read the register 0 value */
2106 spin_lock_irqsave(&ioapic_lock, flags);
2107 reg_00.raw = io_apic_read(apic_id, 0);
2108 spin_unlock_irqrestore(&ioapic_lock, flags);
2109
2110 old_id = mp_ioapics[apic_id].apicid;
2111
2112 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2113 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2114 apic_id, mp_ioapics[apic_id].apicid);
2115 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2116 reg_00.bits.ID);
2117 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2118 }
2119
2120 /*
2121 * Sanity check, is the ID really free? Every APIC in a
2122 * system must have a unique ID or we get lots of nice
2123 * 'stuck on smp_invalidate_needed IPI wait' messages.
2124 */
2125 if (apic->check_apicid_used(phys_id_present_map,
2126 mp_ioapics[apic_id].apicid)) {
2127 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2128 apic_id, mp_ioapics[apic_id].apicid);
2129 for (i = 0; i < get_physical_broadcast(); i++)
2130 if (!physid_isset(i, phys_id_present_map))
2131 break;
2132 if (i >= get_physical_broadcast())
2133 panic("Max APIC ID exceeded!\n");
2134 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2135 i);
2136 physid_set(i, phys_id_present_map);
2137 mp_ioapics[apic_id].apicid = i;
2138 } else {
2139 physid_mask_t tmp;
2140 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2141 apic_printk(APIC_VERBOSE, "Setting %d in the "
2142 "phys_id_present_map\n",
2143 mp_ioapics[apic_id].apicid);
2144 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2145 }
2146
2147
2148 /*
2149 * We need to adjust the IRQ routing table
2150 * if the ID changed.
2151 */
2152 if (old_id != mp_ioapics[apic_id].apicid)
2153 for (i = 0; i < mp_irq_entries; i++)
2154 if (mp_irqs[i].dstapic == old_id)
2155 mp_irqs[i].dstapic
2156 = mp_ioapics[apic_id].apicid;
2157
2158 /*
2159 * Read the right value from the MPC table and
2160 * write it into the ID register.
2161 */
2162 apic_printk(APIC_VERBOSE, KERN_INFO
2163 "...changing IO-APIC physical APIC ID to %d ...",
2164 mp_ioapics[apic_id].apicid);
2165
2166 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2167 spin_lock_irqsave(&ioapic_lock, flags);
2168 io_apic_write(apic_id, 0, reg_00.raw);
2169 spin_unlock_irqrestore(&ioapic_lock, flags);
2170
2171 /*
2172 * Sanity check
2173 */
2174 spin_lock_irqsave(&ioapic_lock, flags);
2175 reg_00.raw = io_apic_read(apic_id, 0);
2176 spin_unlock_irqrestore(&ioapic_lock, flags);
2177 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2178 printk("could not set ID!\n");
2179 else
2180 apic_printk(APIC_VERBOSE, " ok.\n");
2181 }
2182}
2183#endif
2184
2185int no_timer_check __initdata;
2186
2187static int __init notimercheck(char *s)
2188{
2189 no_timer_check = 1;
2190 return 1;
2191}
2192__setup("no_timer_check", notimercheck);
2193
2194/*
2195 * There is a nasty bug in some older SMP boards, their mptable lies
2196 * about the timer IRQ. We do the following to work around the situation:
2197 *
2198 * - timer IRQ defaults to IO-APIC IRQ
2199 * - if this function detects that timer IRQs are defunct, then we fall
2200 * back to ISA timer IRQs
2201 */
2202static int __init timer_irq_works(void)
2203{
2204 unsigned long t1 = jiffies;
2205 unsigned long flags;
2206
2207 if (no_timer_check)
2208 return 1;
2209
2210 local_save_flags(flags);
2211 local_irq_enable();
2212 /* Let ten ticks pass... */
2213 mdelay((10 * 1000) / HZ);
2214 local_irq_restore(flags);
2215
2216 /*
2217 * Expect a few ticks at least, to be sure some possible
2218 * glue logic does not lock up after one or two first
2219 * ticks in a non-ExtINT mode. Also the local APIC
2220 * might have cached one ExtINT interrupt. Finally, at
2221 * least one tick may be lost due to delays.
2222 */
2223
2224 /* jiffies wrap? */
2225 if (time_after(jiffies, t1 + 4))
2226 return 1;
2227 return 0;
2228}
2229
2230/*
2231 * In the SMP+IOAPIC case it might happen that there are an unspecified
2232 * number of pending IRQ events unhandled. These cases are very rare,
2233 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2234 * better to do it this way as thus we do not have to be aware of
2235 * 'pending' interrupts in the IRQ path, except at this point.
2236 */
2237/*
2238 * Edge triggered needs to resend any interrupt
2239 * that was delayed but this is now handled in the device
2240 * independent code.
2241 */
2242
2243/*
2244 * Starting up a edge-triggered IO-APIC interrupt is
2245 * nasty - we need to make sure that we get the edge.
2246 * If it is already asserted for some reason, we need
2247 * return 1 to indicate that is was pending.
2248 *
2249 * This is not complete - we should be able to fake
2250 * an edge even if it isn't on the 8259A...
2251 */
2252
2253static unsigned int startup_ioapic_irq(unsigned int irq)
2254{
2255 int was_pending = 0;
2256 unsigned long flags;
2257 struct irq_cfg *cfg;
2258
2259 spin_lock_irqsave(&ioapic_lock, flags);
2260 if (irq < NR_IRQS_LEGACY) {
2261 disable_8259A_irq(irq);
2262 if (i8259A_irq_pending(irq))
2263 was_pending = 1;
2264 }
2265 cfg = irq_cfg(irq);
2266 __unmask_IO_APIC_irq(cfg);
2267 spin_unlock_irqrestore(&ioapic_lock, flags);
2268
2269 return was_pending;
2270}
2271
2272#ifdef CONFIG_X86_64
2273static int ioapic_retrigger_irq(unsigned int irq)
2274{
2275
2276 struct irq_cfg *cfg = irq_cfg(irq);
2277 unsigned long flags;
2278
2279 spin_lock_irqsave(&vector_lock, flags);
2280 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2281 spin_unlock_irqrestore(&vector_lock, flags);
2282
2283 return 1;
2284}
2285#else
2286static int ioapic_retrigger_irq(unsigned int irq)
2287{
2288 apic->send_IPI_self(irq_cfg(irq)->vector);
2289
2290 return 1;
2291}
2292#endif
2293
2294/*
2295 * Level and edge triggered IO-APIC interrupts need different handling,
2296 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2297 * handled with the level-triggered descriptor, but that one has slightly
2298 * more overhead. Level-triggered interrupts cannot be handled with the
2299 * edge-triggered handler, without risking IRQ storms and other ugly
2300 * races.
2301 */
2302
2303#ifdef CONFIG_SMP
2304
2305#ifdef CONFIG_INTR_REMAP
2306static void ir_irq_migration(struct work_struct *work);
2307
2308static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2309
2310/*
2311 * Migrate the IO-APIC irq in the presence of intr-remapping.
2312 *
2313 * For edge triggered, irq migration is a simple atomic update(of vector
2314 * and cpu destination) of IRTE and flush the hardware cache.
2315 *
2316 * For level triggered, we need to modify the io-apic RTE aswell with the update
2317 * vector information, along with modifying IRTE with vector and destination.
2318 * So irq migration for level triggered is little bit more complex compared to
2319 * edge triggered migration. But the good news is, we use the same algorithm
2320 * for level triggered migration as we have today, only difference being,
2321 * we now initiate the irq migration from process context instead of the
2322 * interrupt context.
2323 *
2324 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2325 * suppression) to the IO-APIC, level triggered irq migration will also be
2326 * as simple as edge triggered migration and we can do the irq migration
2327 * with a simple atomic update to IO-APIC RTE.
2328 */
2329static void
2330migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2331{
2332 struct irq_cfg *cfg;
2333 struct irte irte;
2334 int modify_ioapic_rte;
2335 unsigned int dest;
2336 unsigned long flags;
2337 unsigned int irq;
2338
2339 if (!cpumask_intersects(mask, cpu_online_mask))
2340 return;
2341
2342 irq = desc->irq;
2343 if (get_irte(irq, &irte))
2344 return;
2345
2346 cfg = desc->chip_data;
2347 if (assign_irq_vector(irq, cfg, mask))
2348 return;
2349
2350 set_extra_move_desc(desc, mask);
2351
2352 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2353
2354 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2355 if (modify_ioapic_rte) {
2356 spin_lock_irqsave(&ioapic_lock, flags);
2357 __target_IO_APIC_irq(irq, dest, cfg);
2358 spin_unlock_irqrestore(&ioapic_lock, flags);
2359 }
2360
2361 irte.vector = cfg->vector;
2362 irte.dest_id = IRTE_DEST(dest);
2363
2364 /*
2365 * Modified the IRTE and flushes the Interrupt entry cache.
2366 */
2367 modify_irte(irq, &irte);
2368
2369 if (cfg->move_in_progress)
2370 send_cleanup_vector(cfg);
2371
2372 cpumask_copy(desc->affinity, mask);
2373}
2374
2375static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2376{
2377 int ret = -1;
2378 struct irq_cfg *cfg = desc->chip_data;
2379
2380 mask_IO_APIC_irq_desc(desc);
2381
2382 if (io_apic_level_ack_pending(cfg)) {
2383 /*
2384 * Interrupt in progress. Migrating irq now will change the
2385 * vector information in the IO-APIC RTE and that will confuse
2386 * the EOI broadcast performed by cpu.
2387 * So, delay the irq migration to the next instance.
2388 */
2389 schedule_delayed_work(&ir_migration_work, 1);
2390 goto unmask;
2391 }
2392
2393 /* everthing is clear. we have right of way */
2394 migrate_ioapic_irq_desc(desc, desc->pending_mask);
2395
2396 ret = 0;
2397 desc->status &= ~IRQ_MOVE_PENDING;
2398 cpumask_clear(desc->pending_mask);
2399
2400unmask:
2401 unmask_IO_APIC_irq_desc(desc);
2402
2403 return ret;
2404}
2405
2406static void ir_irq_migration(struct work_struct *work)
2407{
2408 unsigned int irq;
2409 struct irq_desc *desc;
2410
2411 for_each_irq_desc(irq, desc) {
2412 if (desc->status & IRQ_MOVE_PENDING) {
2413 unsigned long flags;
2414
2415 spin_lock_irqsave(&desc->lock, flags);
2416 if (!desc->chip->set_affinity ||
2417 !(desc->status & IRQ_MOVE_PENDING)) {
2418 desc->status &= ~IRQ_MOVE_PENDING;
2419 spin_unlock_irqrestore(&desc->lock, flags);
2420 continue;
2421 }
2422
2423 desc->chip->set_affinity(irq, desc->pending_mask);
2424 spin_unlock_irqrestore(&desc->lock, flags);
2425 }
2426 }
2427}
2428
2429/*
2430 * Migrates the IRQ destination in the process context.
2431 */
2432static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2433 const struct cpumask *mask)
2434{
2435 if (desc->status & IRQ_LEVEL) {
2436 desc->status |= IRQ_MOVE_PENDING;
2437 cpumask_copy(desc->pending_mask, mask);
2438 migrate_irq_remapped_level_desc(desc);
2439 return;
2440 }
2441
2442 migrate_ioapic_irq_desc(desc, mask);
2443}
2444static void set_ir_ioapic_affinity_irq(unsigned int irq,
2445 const struct cpumask *mask)
2446{
2447 struct irq_desc *desc = irq_to_desc(irq);
2448
2449 set_ir_ioapic_affinity_irq_desc(desc, mask);
2450}
2451#endif
2452
2453asmlinkage void smp_irq_move_cleanup_interrupt(void)
2454{
2455 unsigned vector, me;
2456
2457 ack_APIC_irq();
2458 exit_idle();
2459 irq_enter();
2460
2461 me = smp_processor_id();
2462 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2463 unsigned int irq;
2464 struct irq_desc *desc;
2465 struct irq_cfg *cfg;
2466 irq = __get_cpu_var(vector_irq)[vector];
2467
2468 if (irq == -1)
2469 continue;
2470
2471 desc = irq_to_desc(irq);
2472 if (!desc)
2473 continue;
2474
2475 cfg = irq_cfg(irq);
2476 spin_lock(&desc->lock);
2477 if (!cfg->move_cleanup_count)
2478 goto unlock;
2479
2480 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2481 goto unlock;
2482
2483 __get_cpu_var(vector_irq)[vector] = -1;
2484 cfg->move_cleanup_count--;
2485unlock:
2486 spin_unlock(&desc->lock);
2487 }
2488
2489 irq_exit();
2490}
2491
2492static void irq_complete_move(struct irq_desc **descp)
2493{
2494 struct irq_desc *desc = *descp;
2495 struct irq_cfg *cfg = desc->chip_data;
2496 unsigned vector, me;
2497
2498 if (likely(!cfg->move_in_progress)) {
2499#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2500 if (likely(!cfg->move_desc_pending))
2501 return;
2502
2503 /* domain has not changed, but affinity did */
2504 me = smp_processor_id();
2505 if (cpumask_test_cpu(me, desc->affinity)) {
2506 *descp = desc = move_irq_desc(desc, me);
2507 /* get the new one */
2508 cfg = desc->chip_data;
2509 cfg->move_desc_pending = 0;
2510 }
2511#endif
2512 return;
2513 }
2514
2515 vector = ~get_irq_regs()->orig_ax;
2516 me = smp_processor_id();
2517
2518 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2519#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2520 *descp = desc = move_irq_desc(desc, me);
2521 /* get the new one */
2522 cfg = desc->chip_data;
2523#endif
2524 send_cleanup_vector(cfg);
2525 }
2526}
2527#else
2528static inline void irq_complete_move(struct irq_desc **descp) {}
2529#endif
2530
2531#ifdef CONFIG_INTR_REMAP
2532static void ack_x2apic_level(unsigned int irq)
2533{
2534 ack_x2APIC_irq();
2535}
2536
2537static void ack_x2apic_edge(unsigned int irq)
2538{
2539 ack_x2APIC_irq();
2540}
2541
2542#endif
2543
2544static void ack_apic_edge(unsigned int irq)
2545{
2546 struct irq_desc *desc = irq_to_desc(irq);
2547
2548 irq_complete_move(&desc);
2549 move_native_irq(irq);
2550 ack_APIC_irq();
2551}
2552
2553atomic_t irq_mis_count;
2554
2555static void ack_apic_level(unsigned int irq)
2556{
2557 struct irq_desc *desc = irq_to_desc(irq);
2558
2559#ifdef CONFIG_X86_32
2560 unsigned long v;
2561 int i;
2562#endif
2563 struct irq_cfg *cfg;
2564 int do_unmask_irq = 0;
2565
2566 irq_complete_move(&desc);
2567#ifdef CONFIG_GENERIC_PENDING_IRQ
2568 /* If we are moving the irq we need to mask it */
2569 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2570 do_unmask_irq = 1;
2571 mask_IO_APIC_irq_desc(desc);
2572 }
2573#endif
2574
2575#ifdef CONFIG_X86_32
2576 /*
2577 * It appears there is an erratum which affects at least version 0x11
2578 * of I/O APIC (that's the 82093AA and cores integrated into various
2579 * chipsets). Under certain conditions a level-triggered interrupt is
2580 * erroneously delivered as edge-triggered one but the respective IRR
2581 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2582 * message but it will never arrive and further interrupts are blocked
2583 * from the source. The exact reason is so far unknown, but the
2584 * phenomenon was observed when two consecutive interrupt requests
2585 * from a given source get delivered to the same CPU and the source is
2586 * temporarily disabled in between.
2587 *
2588 * A workaround is to simulate an EOI message manually. We achieve it
2589 * by setting the trigger mode to edge and then to level when the edge
2590 * trigger mode gets detected in the TMR of a local APIC for a
2591 * level-triggered interrupt. We mask the source for the time of the
2592 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2593 * The idea is from Manfred Spraul. --macro
2594 */
2595 cfg = desc->chip_data;
2596 i = cfg->vector;
2597
2598 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2599#endif
2600
2601 /*
2602 * We must acknowledge the irq before we move it or the acknowledge will
2603 * not propagate properly.
2604 */
2605 ack_APIC_irq();
2606
2607 /* Now we can move and renable the irq */
2608 if (unlikely(do_unmask_irq)) {
2609 /* Only migrate the irq if the ack has been received.
2610 *
2611 * On rare occasions the broadcast level triggered ack gets
2612 * delayed going to ioapics, and if we reprogram the
2613 * vector while Remote IRR is still set the irq will never
2614 * fire again.
2615 *
2616 * To prevent this scenario we read the Remote IRR bit
2617 * of the ioapic. This has two effects.
2618 * - On any sane system the read of the ioapic will
2619 * flush writes (and acks) going to the ioapic from
2620 * this cpu.
2621 * - We get to see if the ACK has actually been delivered.
2622 *
2623 * Based on failed experiments of reprogramming the
2624 * ioapic entry from outside of irq context starting
2625 * with masking the ioapic entry and then polling until
2626 * Remote IRR was clear before reprogramming the
2627 * ioapic I don't trust the Remote IRR bit to be
2628 * completey accurate.
2629 *
2630 * However there appears to be no other way to plug
2631 * this race, so if the Remote IRR bit is not
2632 * accurate and is causing problems then it is a hardware bug
2633 * and you can go talk to the chipset vendor about it.
2634 */
2635 cfg = desc->chip_data;
2636 if (!io_apic_level_ack_pending(cfg))
2637 move_masked_irq(irq);
2638 unmask_IO_APIC_irq_desc(desc);
2639 }
2640
2641#ifdef CONFIG_X86_32
2642 if (!(v & (1 << (i & 0x1f)))) {
2643 atomic_inc(&irq_mis_count);
2644 spin_lock(&ioapic_lock);
2645 __mask_and_edge_IO_APIC_irq(cfg);
2646 __unmask_and_level_IO_APIC_irq(cfg);
2647 spin_unlock(&ioapic_lock);
2648 }
2649#endif
2650}
2651
2652static struct irq_chip ioapic_chip __read_mostly = {
2653 .name = "IO-APIC",
2654 .startup = startup_ioapic_irq,
2655 .mask = mask_IO_APIC_irq,
2656 .unmask = unmask_IO_APIC_irq,
2657 .ack = ack_apic_edge,
2658 .eoi = ack_apic_level,
2659#ifdef CONFIG_SMP
2660 .set_affinity = set_ioapic_affinity_irq,
2661#endif
2662 .retrigger = ioapic_retrigger_irq,
2663};
2664
2665#ifdef CONFIG_INTR_REMAP
2666static struct irq_chip ir_ioapic_chip __read_mostly = {
2667 .name = "IR-IO-APIC",
2668 .startup = startup_ioapic_irq,
2669 .mask = mask_IO_APIC_irq,
2670 .unmask = unmask_IO_APIC_irq,
2671 .ack = ack_x2apic_edge,
2672 .eoi = ack_x2apic_level,
2673#ifdef CONFIG_SMP
2674 .set_affinity = set_ir_ioapic_affinity_irq,
2675#endif
2676 .retrigger = ioapic_retrigger_irq,
2677};
2678#endif
2679
2680static inline void init_IO_APIC_traps(void)
2681{
2682 int irq;
2683 struct irq_desc *desc;
2684 struct irq_cfg *cfg;
2685
2686 /*
2687 * NOTE! The local APIC isn't very good at handling
2688 * multiple interrupts at the same interrupt level.
2689 * As the interrupt level is determined by taking the
2690 * vector number and shifting that right by 4, we
2691 * want to spread these out a bit so that they don't
2692 * all fall in the same interrupt level.
2693 *
2694 * Also, we've got to be careful not to trash gate
2695 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2696 */
2697 for_each_irq_desc(irq, desc) {
2698 cfg = desc->chip_data;
2699 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2700 /*
2701 * Hmm.. We don't have an entry for this,
2702 * so default to an old-fashioned 8259
2703 * interrupt if we can..
2704 */
2705 if (irq < NR_IRQS_LEGACY)
2706 make_8259A_irq(irq);
2707 else
2708 /* Strange. Oh, well.. */
2709 desc->chip = &no_irq_chip;
2710 }
2711 }
2712}
2713
2714/*
2715 * The local APIC irq-chip implementation:
2716 */
2717
2718static void mask_lapic_irq(unsigned int irq)
2719{
2720 unsigned long v;
2721
2722 v = apic_read(APIC_LVT0);
2723 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2724}
2725
2726static void unmask_lapic_irq(unsigned int irq)
2727{
2728 unsigned long v;
2729
2730 v = apic_read(APIC_LVT0);
2731 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2732}
2733
2734static void ack_lapic_irq(unsigned int irq)
2735{
2736 ack_APIC_irq();
2737}
2738
2739static struct irq_chip lapic_chip __read_mostly = {
2740 .name = "local-APIC",
2741 .mask = mask_lapic_irq,
2742 .unmask = unmask_lapic_irq,
2743 .ack = ack_lapic_irq,
2744};
2745
2746static void lapic_register_intr(int irq, struct irq_desc *desc)
2747{
2748 desc->status &= ~IRQ_LEVEL;
2749 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2750 "edge");
2751}
2752
2753static void __init setup_nmi(void)
2754{
2755 /*
2756 * Dirty trick to enable the NMI watchdog ...
2757 * We put the 8259A master into AEOI mode and
2758 * unmask on all local APICs LVT0 as NMI.
2759 *
2760 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2761 * is from Maciej W. Rozycki - so we do not have to EOI from
2762 * the NMI handler or the timer interrupt.
2763 */
2764 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2765
2766 enable_NMI_through_LVT0();
2767
2768 apic_printk(APIC_VERBOSE, " done.\n");
2769}
2770
2771/*
2772 * This looks a bit hackish but it's about the only one way of sending
2773 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2774 * not support the ExtINT mode, unfortunately. We need to send these
2775 * cycles as some i82489DX-based boards have glue logic that keeps the
2776 * 8259A interrupt line asserted until INTA. --macro
2777 */
2778static inline void __init unlock_ExtINT_logic(void)
2779{
2780 int apic, pin, i;
2781 struct IO_APIC_route_entry entry0, entry1;
2782 unsigned char save_control, save_freq_select;
2783
2784 pin = find_isa_irq_pin(8, mp_INT);
2785 if (pin == -1) {
2786 WARN_ON_ONCE(1);
2787 return;
2788 }
2789 apic = find_isa_irq_apic(8, mp_INT);
2790 if (apic == -1) {
2791 WARN_ON_ONCE(1);
2792 return;
2793 }
2794
2795 entry0 = ioapic_read_entry(apic, pin);
2796 clear_IO_APIC_pin(apic, pin);
2797
2798 memset(&entry1, 0, sizeof(entry1));
2799
2800 entry1.dest_mode = 0; /* physical delivery */
2801 entry1.mask = 0; /* unmask IRQ now */
2802 entry1.dest = hard_smp_processor_id();
2803 entry1.delivery_mode = dest_ExtINT;
2804 entry1.polarity = entry0.polarity;
2805 entry1.trigger = 0;
2806 entry1.vector = 0;
2807
2808 ioapic_write_entry(apic, pin, entry1);
2809
2810 save_control = CMOS_READ(RTC_CONTROL);
2811 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2812 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2813 RTC_FREQ_SELECT);
2814 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2815
2816 i = 100;
2817 while (i-- > 0) {
2818 mdelay(10);
2819 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2820 i -= 10;
2821 }
2822
2823 CMOS_WRITE(save_control, RTC_CONTROL);
2824 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2825 clear_IO_APIC_pin(apic, pin);
2826
2827 ioapic_write_entry(apic, pin, entry0);
2828}
2829
2830static int disable_timer_pin_1 __initdata;
2831/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2832static int __init disable_timer_pin_setup(char *arg)
2833{
2834 disable_timer_pin_1 = 1;
2835 return 0;
2836}
2837early_param("disable_timer_pin_1", disable_timer_pin_setup);
2838
2839int timer_through_8259 __initdata;
2840
2841/*
2842 * This code may look a bit paranoid, but it's supposed to cooperate with
2843 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2844 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2845 * fanatically on his truly buggy board.
2846 *
2847 * FIXME: really need to revamp this for all platforms.
2848 */
2849static inline void __init check_timer(void)
2850{
2851 struct irq_desc *desc = irq_to_desc(0);
2852 struct irq_cfg *cfg = desc->chip_data;
2853 int cpu = boot_cpu_id;
2854 int apic1, pin1, apic2, pin2;
2855 unsigned long flags;
2856 int no_pin1 = 0;
2857
2858 local_irq_save(flags);
2859
2860 /*
2861 * get/set the timer IRQ vector:
2862 */
2863 disable_8259A_irq(0);
2864 assign_irq_vector(0, cfg, apic->target_cpus());
2865
2866 /*
2867 * As IRQ0 is to be enabled in the 8259A, the virtual
2868 * wire has to be disabled in the local APIC. Also
2869 * timer interrupts need to be acknowledged manually in
2870 * the 8259A for the i82489DX when using the NMI
2871 * watchdog as that APIC treats NMIs as level-triggered.
2872 * The AEOI mode will finish them in the 8259A
2873 * automatically.
2874 */
2875 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2876 init_8259A(1);
2877#ifdef CONFIG_X86_32
2878 {
2879 unsigned int ver;
2880
2881 ver = apic_read(APIC_LVR);
2882 ver = GET_APIC_VERSION(ver);
2883 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2884 }
2885#endif
2886
2887 pin1 = find_isa_irq_pin(0, mp_INT);
2888 apic1 = find_isa_irq_apic(0, mp_INT);
2889 pin2 = ioapic_i8259.pin;
2890 apic2 = ioapic_i8259.apic;
2891
2892 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2893 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2894 cfg->vector, apic1, pin1, apic2, pin2);
2895
2896 /*
2897 * Some BIOS writers are clueless and report the ExtINTA
2898 * I/O APIC input from the cascaded 8259A as the timer
2899 * interrupt input. So just in case, if only one pin
2900 * was found above, try it both directly and through the
2901 * 8259A.
2902 */
2903 if (pin1 == -1) {
2904#ifdef CONFIG_INTR_REMAP
2905 if (intr_remapping_enabled)
2906 panic("BIOS bug: timer not connected to IO-APIC");
2907#endif
2908 pin1 = pin2;
2909 apic1 = apic2;
2910 no_pin1 = 1;
2911 } else if (pin2 == -1) {
2912 pin2 = pin1;
2913 apic2 = apic1;
2914 }
2915
2916 if (pin1 != -1) {
2917 /*
2918 * Ok, does IRQ0 through the IOAPIC work?
2919 */
2920 if (no_pin1) {
2921 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2922 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2923 } else {
2924 /* for edge trigger, setup_IO_APIC_irq already
2925 * leave it unmasked.
2926 * so only need to unmask if it is level-trigger
2927 * do we really have level trigger timer?
2928 */
2929 int idx;
2930 idx = find_irq_entry(apic1, pin1, mp_INT);
2931 if (idx != -1 && irq_trigger(idx))
2932 unmask_IO_APIC_irq_desc(desc);
2933 }
2934 if (timer_irq_works()) {
2935 if (nmi_watchdog == NMI_IO_APIC) {
2936 setup_nmi();
2937 enable_8259A_irq(0);
2938 }
2939 if (disable_timer_pin_1 > 0)
2940 clear_IO_APIC_pin(0, pin1);
2941 goto out;
2942 }
2943#ifdef CONFIG_INTR_REMAP
2944 if (intr_remapping_enabled)
2945 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2946#endif
2947 local_irq_disable();
2948 clear_IO_APIC_pin(apic1, pin1);
2949 if (!no_pin1)
2950 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2951 "8254 timer not connected to IO-APIC\n");
2952
2953 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2954 "(IRQ0) through the 8259A ...\n");
2955 apic_printk(APIC_QUIET, KERN_INFO
2956 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2957 /*
2958 * legacy devices should be connected to IO APIC #0
2959 */
2960 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2961 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2962 enable_8259A_irq(0);
2963 if (timer_irq_works()) {
2964 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2965 timer_through_8259 = 1;
2966 if (nmi_watchdog == NMI_IO_APIC) {
2967 disable_8259A_irq(0);
2968 setup_nmi();
2969 enable_8259A_irq(0);
2970 }
2971 goto out;
2972 }
2973 /*
2974 * Cleanup, just in case ...
2975 */
2976 local_irq_disable();
2977 disable_8259A_irq(0);
2978 clear_IO_APIC_pin(apic2, pin2);
2979 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2980 }
2981
2982 if (nmi_watchdog == NMI_IO_APIC) {
2983 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2984 "through the IO-APIC - disabling NMI Watchdog!\n");
2985 nmi_watchdog = NMI_NONE;
2986 }
2987#ifdef CONFIG_X86_32
2988 timer_ack = 0;
2989#endif
2990
2991 apic_printk(APIC_QUIET, KERN_INFO
2992 "...trying to set up timer as Virtual Wire IRQ...\n");
2993
2994 lapic_register_intr(0, desc);
2995 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2996 enable_8259A_irq(0);
2997
2998 if (timer_irq_works()) {
2999 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3000 goto out;
3001 }
3002 local_irq_disable();
3003 disable_8259A_irq(0);
3004 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3005 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3006
3007 apic_printk(APIC_QUIET, KERN_INFO
3008 "...trying to set up timer as ExtINT IRQ...\n");
3009
3010 init_8259A(0);
3011 make_8259A_irq(0);
3012 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3013
3014 unlock_ExtINT_logic();
3015
3016 if (timer_irq_works()) {
3017 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3018 goto out;
3019 }
3020 local_irq_disable();
3021 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3022 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3023 "report. Then try booting with the 'noapic' option.\n");
3024out:
3025 local_irq_restore(flags);
3026}
3027
3028/*
3029 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3030 * to devices. However there may be an I/O APIC pin available for
3031 * this interrupt regardless. The pin may be left unconnected, but
3032 * typically it will be reused as an ExtINT cascade interrupt for
3033 * the master 8259A. In the MPS case such a pin will normally be
3034 * reported as an ExtINT interrupt in the MP table. With ACPI
3035 * there is no provision for ExtINT interrupts, and in the absence
3036 * of an override it would be treated as an ordinary ISA I/O APIC
3037 * interrupt, that is edge-triggered and unmasked by default. We
3038 * used to do this, but it caused problems on some systems because
3039 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3040 * the same ExtINT cascade interrupt to drive the local APIC of the
3041 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3042 * the I/O APIC in all cases now. No actual device should request
3043 * it anyway. --macro
3044 */
3045#define PIC_IRQS (1 << PIC_CASCADE_IR)
3046
3047void __init setup_IO_APIC(void)
3048{
3049
3050 /*
3051 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3052 */
3053
3054 io_apic_irqs = ~PIC_IRQS;
3055
3056 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3057 /*
3058 * Set up IO-APIC IRQ routing.
3059 */
3060#ifdef CONFIG_X86_32
3061 if (!acpi_ioapic)
3062 setup_ioapic_ids_from_mpc();
3063#endif
3064 sync_Arb_IDs();
3065 setup_IO_APIC_irqs();
3066 init_IO_APIC_traps();
3067 check_timer();
3068}
3069
3070/*
3071 * Called after all the initialization is done. If we didnt find any
3072 * APIC bugs then we can allow the modify fast path
3073 */
3074
3075static int __init io_apic_bug_finalize(void)
3076{
3077 if (sis_apic_bug == -1)
3078 sis_apic_bug = 0;
3079 return 0;
3080}
3081
3082late_initcall(io_apic_bug_finalize);
3083
3084struct sysfs_ioapic_data {
3085 struct sys_device dev;
3086 struct IO_APIC_route_entry entry[0];
3087};
3088static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3089
3090static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3091{
3092 struct IO_APIC_route_entry *entry;
3093 struct sysfs_ioapic_data *data;
3094 int i;
3095
3096 data = container_of(dev, struct sysfs_ioapic_data, dev);
3097 entry = data->entry;
3098 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3099 *entry = ioapic_read_entry(dev->id, i);
3100
3101 return 0;
3102}
3103
3104static int ioapic_resume(struct sys_device *dev)
3105{
3106 struct IO_APIC_route_entry *entry;
3107 struct sysfs_ioapic_data *data;
3108 unsigned long flags;
3109 union IO_APIC_reg_00 reg_00;
3110 int i;
3111
3112 data = container_of(dev, struct sysfs_ioapic_data, dev);
3113 entry = data->entry;
3114
3115 spin_lock_irqsave(&ioapic_lock, flags);
3116 reg_00.raw = io_apic_read(dev->id, 0);
3117 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3118 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3119 io_apic_write(dev->id, 0, reg_00.raw);
3120 }
3121 spin_unlock_irqrestore(&ioapic_lock, flags);
3122 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3123 ioapic_write_entry(dev->id, i, entry[i]);
3124
3125 return 0;
3126}
3127
3128static struct sysdev_class ioapic_sysdev_class = {
3129 .name = "ioapic",
3130 .suspend = ioapic_suspend,
3131 .resume = ioapic_resume,
3132};
3133
3134static int __init ioapic_init_sysfs(void)
3135{
3136 struct sys_device * dev;
3137 int i, size, error;
3138
3139 error = sysdev_class_register(&ioapic_sysdev_class);
3140 if (error)
3141 return error;
3142
3143 for (i = 0; i < nr_ioapics; i++ ) {
3144 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3145 * sizeof(struct IO_APIC_route_entry);
3146 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3147 if (!mp_ioapic_data[i]) {
3148 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3149 continue;
3150 }
3151 dev = &mp_ioapic_data[i]->dev;
3152 dev->id = i;
3153 dev->cls = &ioapic_sysdev_class;
3154 error = sysdev_register(dev);
3155 if (error) {
3156 kfree(mp_ioapic_data[i]);
3157 mp_ioapic_data[i] = NULL;
3158 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3159 continue;
3160 }
3161 }
3162
3163 return 0;
3164}
3165
3166device_initcall(ioapic_init_sysfs);
3167
3168static int nr_irqs_gsi = NR_IRQS_LEGACY;
3169/*
3170 * Dynamic irq allocate and deallocation
3171 */
3172unsigned int create_irq_nr(unsigned int irq_want)
3173{
3174 /* Allocate an unused irq */
3175 unsigned int irq;
3176 unsigned int new;
3177 unsigned long flags;
3178 struct irq_cfg *cfg_new = NULL;
3179 int cpu = boot_cpu_id;
3180 struct irq_desc *desc_new = NULL;
3181
3182 irq = 0;
3183 if (irq_want < nr_irqs_gsi)
3184 irq_want = nr_irqs_gsi;
3185
3186 spin_lock_irqsave(&vector_lock, flags);
3187 for (new = irq_want; new < nr_irqs; new++) {
3188 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3189 if (!desc_new) {
3190 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3191 continue;
3192 }
3193 cfg_new = desc_new->chip_data;
3194
3195 if (cfg_new->vector != 0)
3196 continue;
3197 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3198 irq = new;
3199 break;
3200 }
3201 spin_unlock_irqrestore(&vector_lock, flags);
3202
3203 if (irq > 0) {
3204 dynamic_irq_init(irq);
3205 /* restore it, in case dynamic_irq_init clear it */
3206 if (desc_new)
3207 desc_new->chip_data = cfg_new;
3208 }
3209 return irq;
3210}
3211
3212int create_irq(void)
3213{
3214 unsigned int irq_want;
3215 int irq;
3216
3217 irq_want = nr_irqs_gsi;
3218 irq = create_irq_nr(irq_want);
3219
3220 if (irq == 0)
3221 irq = -1;
3222
3223 return irq;
3224}
3225
3226void destroy_irq(unsigned int irq)
3227{
3228 unsigned long flags;
3229 struct irq_cfg *cfg;
3230 struct irq_desc *desc;
3231
3232 /* store it, in case dynamic_irq_cleanup clear it */
3233 desc = irq_to_desc(irq);
3234 cfg = desc->chip_data;
3235 dynamic_irq_cleanup(irq);
3236 /* connect back irq_cfg */
3237 if (desc)
3238 desc->chip_data = cfg;
3239
3240#ifdef CONFIG_INTR_REMAP
3241 free_irte(irq);
3242#endif
3243 spin_lock_irqsave(&vector_lock, flags);
3244 __clear_irq_vector(irq, cfg);
3245 spin_unlock_irqrestore(&vector_lock, flags);
3246}
3247
3248/*
3249 * MSI message composition
3250 */
3251#ifdef CONFIG_PCI_MSI
3252static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3253{
3254 struct irq_cfg *cfg;
3255 int err;
3256 unsigned dest;
3257
3258 if (disable_apic)
3259 return -ENXIO;
3260
3261 cfg = irq_cfg(irq);
3262 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3263 if (err)
3264 return err;
3265
3266 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3267
3268#ifdef CONFIG_INTR_REMAP
3269 if (irq_remapped(irq)) {
3270 struct irte irte;
3271 int ir_index;
3272 u16 sub_handle;
3273
3274 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3275 BUG_ON(ir_index == -1);
3276
3277 memset (&irte, 0, sizeof(irte));
3278
3279 irte.present = 1;
3280 irte.dst_mode = apic->irq_dest_mode;
3281 irte.trigger_mode = 0; /* edge */
3282 irte.dlvry_mode = apic->irq_delivery_mode;
3283 irte.vector = cfg->vector;
3284 irte.dest_id = IRTE_DEST(dest);
3285
3286 modify_irte(irq, &irte);
3287
3288 msg->address_hi = MSI_ADDR_BASE_HI;
3289 msg->data = sub_handle;
3290 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3291 MSI_ADDR_IR_SHV |
3292 MSI_ADDR_IR_INDEX1(ir_index) |
3293 MSI_ADDR_IR_INDEX2(ir_index);
3294 } else
3295#endif
3296 {
3297 msg->address_hi = MSI_ADDR_BASE_HI;
3298 msg->address_lo =
3299 MSI_ADDR_BASE_LO |
3300 ((apic->irq_dest_mode == 0) ?
3301 MSI_ADDR_DEST_MODE_PHYSICAL:
3302 MSI_ADDR_DEST_MODE_LOGICAL) |
3303 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3304 MSI_ADDR_REDIRECTION_CPU:
3305 MSI_ADDR_REDIRECTION_LOWPRI) |
3306 MSI_ADDR_DEST_ID(dest);
3307
3308 msg->data =
3309 MSI_DATA_TRIGGER_EDGE |
3310 MSI_DATA_LEVEL_ASSERT |
3311 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3312 MSI_DATA_DELIVERY_FIXED:
3313 MSI_DATA_DELIVERY_LOWPRI) |
3314 MSI_DATA_VECTOR(cfg->vector);
3315 }
3316 return err;
3317}
3318
3319#ifdef CONFIG_SMP
3320static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3321{
3322 struct irq_desc *desc = irq_to_desc(irq);
3323 struct irq_cfg *cfg;
3324 struct msi_msg msg;
3325 unsigned int dest;
3326
3327 dest = set_desc_affinity(desc, mask);
3328 if (dest == BAD_APICID)
3329 return;
3330
3331 cfg = desc->chip_data;
3332
3333 read_msi_msg_desc(desc, &msg);
3334
3335 msg.data &= ~MSI_DATA_VECTOR_MASK;
3336 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3337 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3338 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3339
3340 write_msi_msg_desc(desc, &msg);
3341}
3342#ifdef CONFIG_INTR_REMAP
3343/*
3344 * Migrate the MSI irq to another cpumask. This migration is
3345 * done in the process context using interrupt-remapping hardware.
3346 */
3347static void
3348ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3349{
3350 struct irq_desc *desc = irq_to_desc(irq);
3351 struct irq_cfg *cfg = desc->chip_data;
3352 unsigned int dest;
3353 struct irte irte;
3354
3355 if (get_irte(irq, &irte))
3356 return;
3357
3358 dest = set_desc_affinity(desc, mask);
3359 if (dest == BAD_APICID)
3360 return;
3361
3362 irte.vector = cfg->vector;
3363 irte.dest_id = IRTE_DEST(dest);
3364
3365 /*
3366 * atomically update the IRTE with the new destination and vector.
3367 */
3368 modify_irte(irq, &irte);
3369
3370 /*
3371 * After this point, all the interrupts will start arriving
3372 * at the new destination. So, time to cleanup the previous
3373 * vector allocation.
3374 */
3375 if (cfg->move_in_progress)
3376 send_cleanup_vector(cfg);
3377}
3378
3379#endif
3380#endif /* CONFIG_SMP */
3381
3382/*
3383 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3384 * which implement the MSI or MSI-X Capability Structure.
3385 */
3386static struct irq_chip msi_chip = {
3387 .name = "PCI-MSI",
3388 .unmask = unmask_msi_irq,
3389 .mask = mask_msi_irq,
3390 .ack = ack_apic_edge,
3391#ifdef CONFIG_SMP
3392 .set_affinity = set_msi_irq_affinity,
3393#endif
3394 .retrigger = ioapic_retrigger_irq,
3395};
3396
3397#ifdef CONFIG_INTR_REMAP
3398static struct irq_chip msi_ir_chip = {
3399 .name = "IR-PCI-MSI",
3400 .unmask = unmask_msi_irq,
3401 .mask = mask_msi_irq,
3402 .ack = ack_x2apic_edge,
3403#ifdef CONFIG_SMP
3404 .set_affinity = ir_set_msi_irq_affinity,
3405#endif
3406 .retrigger = ioapic_retrigger_irq,
3407};
3408
3409/*
3410 * Map the PCI dev to the corresponding remapping hardware unit
3411 * and allocate 'nvec' consecutive interrupt-remapping table entries
3412 * in it.
3413 */
3414static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3415{
3416 struct intel_iommu *iommu;
3417 int index;
3418
3419 iommu = map_dev_to_ir(dev);
3420 if (!iommu) {
3421 printk(KERN_ERR
3422 "Unable to map PCI %s to iommu\n", pci_name(dev));
3423 return -ENOENT;
3424 }
3425
3426 index = alloc_irte(iommu, irq, nvec);
3427 if (index < 0) {
3428 printk(KERN_ERR
3429 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3430 pci_name(dev));
3431 return -ENOSPC;
3432 }
3433 return index;
3434}
3435#endif
3436
3437static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3438{
3439 int ret;
3440 struct msi_msg msg;
3441
3442 ret = msi_compose_msg(dev, irq, &msg);
3443 if (ret < 0)
3444 return ret;
3445
3446 set_irq_msi(irq, msidesc);
3447 write_msi_msg(irq, &msg);
3448
3449#ifdef CONFIG_INTR_REMAP
3450 if (irq_remapped(irq)) {
3451 struct irq_desc *desc = irq_to_desc(irq);
3452 /*
3453 * irq migration in process context
3454 */
3455 desc->status |= IRQ_MOVE_PCNTXT;
3456 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3457 } else
3458#endif
3459 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3460
3461 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3462
3463 return 0;
3464}
3465
3466int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3467{
3468 unsigned int irq;
3469 int ret, sub_handle;
3470 struct msi_desc *msidesc;
3471 unsigned int irq_want;
3472
3473#ifdef CONFIG_INTR_REMAP
3474 struct intel_iommu *iommu = 0;
3475 int index = 0;
3476#endif
3477
3478 irq_want = nr_irqs_gsi;
3479 sub_handle = 0;
3480 list_for_each_entry(msidesc, &dev->msi_list, list) {
3481 irq = create_irq_nr(irq_want);
3482 if (irq == 0)
3483 return -1;
3484 irq_want = irq + 1;
3485#ifdef CONFIG_INTR_REMAP
3486 if (!intr_remapping_enabled)
3487 goto no_ir;
3488
3489 if (!sub_handle) {
3490 /*
3491 * allocate the consecutive block of IRTE's
3492 * for 'nvec'
3493 */
3494 index = msi_alloc_irte(dev, irq, nvec);
3495 if (index < 0) {
3496 ret = index;
3497 goto error;
3498 }
3499 } else {
3500 iommu = map_dev_to_ir(dev);
3501 if (!iommu) {
3502 ret = -ENOENT;
3503 goto error;
3504 }
3505 /*
3506 * setup the mapping between the irq and the IRTE
3507 * base index, the sub_handle pointing to the
3508 * appropriate interrupt remap table entry.
3509 */
3510 set_irte_irq(irq, iommu, index, sub_handle);
3511 }
3512no_ir:
3513#endif
3514 ret = setup_msi_irq(dev, msidesc, irq);
3515 if (ret < 0)
3516 goto error;
3517 sub_handle++;
3518 }
3519 return 0;
3520
3521error:
3522 destroy_irq(irq);
3523 return ret;
3524}
3525
3526void arch_teardown_msi_irq(unsigned int irq)
3527{
3528 destroy_irq(irq);
3529}
3530
3531#ifdef CONFIG_DMAR
3532#ifdef CONFIG_SMP
3533static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3534{
3535 struct irq_desc *desc = irq_to_desc(irq);
3536 struct irq_cfg *cfg;
3537 struct msi_msg msg;
3538 unsigned int dest;
3539
3540 dest = set_desc_affinity(desc, mask);
3541 if (dest == BAD_APICID)
3542 return;
3543
3544 cfg = desc->chip_data;
3545
3546 dmar_msi_read(irq, &msg);
3547
3548 msg.data &= ~MSI_DATA_VECTOR_MASK;
3549 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3550 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3551 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3552
3553 dmar_msi_write(irq, &msg);
3554}
3555
3556#endif /* CONFIG_SMP */
3557
3558struct irq_chip dmar_msi_type = {
3559 .name = "DMAR_MSI",
3560 .unmask = dmar_msi_unmask,
3561 .mask = dmar_msi_mask,
3562 .ack = ack_apic_edge,
3563#ifdef CONFIG_SMP
3564 .set_affinity = dmar_msi_set_affinity,
3565#endif
3566 .retrigger = ioapic_retrigger_irq,
3567};
3568
3569int arch_setup_dmar_msi(unsigned int irq)
3570{
3571 int ret;
3572 struct msi_msg msg;
3573
3574 ret = msi_compose_msg(NULL, irq, &msg);
3575 if (ret < 0)
3576 return ret;
3577 dmar_msi_write(irq, &msg);
3578 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3579 "edge");
3580 return 0;
3581}
3582#endif
3583
3584#ifdef CONFIG_HPET_TIMER
3585
3586#ifdef CONFIG_SMP
3587static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3588{
3589 struct irq_desc *desc = irq_to_desc(irq);
3590 struct irq_cfg *cfg;
3591 struct msi_msg msg;
3592 unsigned int dest;
3593
3594 dest = set_desc_affinity(desc, mask);
3595 if (dest == BAD_APICID)
3596 return;
3597
3598 cfg = desc->chip_data;
3599
3600 hpet_msi_read(irq, &msg);
3601
3602 msg.data &= ~MSI_DATA_VECTOR_MASK;
3603 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3604 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3605 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3606
3607 hpet_msi_write(irq, &msg);
3608}
3609
3610#endif /* CONFIG_SMP */
3611
3612struct irq_chip hpet_msi_type = {
3613 .name = "HPET_MSI",
3614 .unmask = hpet_msi_unmask,
3615 .mask = hpet_msi_mask,
3616 .ack = ack_apic_edge,
3617#ifdef CONFIG_SMP
3618 .set_affinity = hpet_msi_set_affinity,
3619#endif
3620 .retrigger = ioapic_retrigger_irq,
3621};
3622
3623int arch_setup_hpet_msi(unsigned int irq)
3624{
3625 int ret;
3626 struct msi_msg msg;
3627
3628 ret = msi_compose_msg(NULL, irq, &msg);
3629 if (ret < 0)
3630 return ret;
3631
3632 hpet_msi_write(irq, &msg);
3633 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3634 "edge");
3635
3636 return 0;
3637}
3638#endif
3639
3640#endif /* CONFIG_PCI_MSI */
3641/*
3642 * Hypertransport interrupt support
3643 */
3644#ifdef CONFIG_HT_IRQ
3645
3646#ifdef CONFIG_SMP
3647
3648static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3649{
3650 struct ht_irq_msg msg;
3651 fetch_ht_irq_msg(irq, &msg);
3652
3653 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3654 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3655
3656 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3657 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3658
3659 write_ht_irq_msg(irq, &msg);
3660}
3661
3662static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3663{
3664 struct irq_desc *desc = irq_to_desc(irq);
3665 struct irq_cfg *cfg;
3666 unsigned int dest;
3667
3668 dest = set_desc_affinity(desc, mask);
3669 if (dest == BAD_APICID)
3670 return;
3671
3672 cfg = desc->chip_data;
3673
3674 target_ht_irq(irq, dest, cfg->vector);
3675}
3676
3677#endif
3678
3679static struct irq_chip ht_irq_chip = {
3680 .name = "PCI-HT",
3681 .mask = mask_ht_irq,
3682 .unmask = unmask_ht_irq,
3683 .ack = ack_apic_edge,
3684#ifdef CONFIG_SMP
3685 .set_affinity = set_ht_irq_affinity,
3686#endif
3687 .retrigger = ioapic_retrigger_irq,
3688};
3689
3690int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3691{
3692 struct irq_cfg *cfg;
3693 int err;
3694
3695 if (disable_apic)
3696 return -ENXIO;
3697
3698 cfg = irq_cfg(irq);
3699 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3700 if (!err) {
3701 struct ht_irq_msg msg;
3702 unsigned dest;
3703
3704 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3705 apic->target_cpus());
3706
3707 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3708
3709 msg.address_lo =
3710 HT_IRQ_LOW_BASE |
3711 HT_IRQ_LOW_DEST_ID(dest) |
3712 HT_IRQ_LOW_VECTOR(cfg->vector) |
3713 ((apic->irq_dest_mode == 0) ?
3714 HT_IRQ_LOW_DM_PHYSICAL :
3715 HT_IRQ_LOW_DM_LOGICAL) |
3716 HT_IRQ_LOW_RQEOI_EDGE |
3717 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3718 HT_IRQ_LOW_MT_FIXED :
3719 HT_IRQ_LOW_MT_ARBITRATED) |
3720 HT_IRQ_LOW_IRQ_MASKED;
3721
3722 write_ht_irq_msg(irq, &msg);
3723
3724 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3725 handle_edge_irq, "edge");
3726
3727 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3728 }
3729 return err;
3730}
3731#endif /* CONFIG_HT_IRQ */
3732
3733#ifdef CONFIG_X86_UV
3734/*
3735 * Re-target the irq to the specified CPU and enable the specified MMR located
3736 * on the specified blade to allow the sending of MSIs to the specified CPU.
3737 */
3738int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3739 unsigned long mmr_offset)
3740{
3741 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3742 struct irq_cfg *cfg;
3743 int mmr_pnode;
3744 unsigned long mmr_value;
3745 struct uv_IO_APIC_route_entry *entry;
3746 unsigned long flags;
3747 int err;
3748
3749 cfg = irq_cfg(irq);
3750
3751 err = assign_irq_vector(irq, cfg, eligible_cpu);
3752 if (err != 0)
3753 return err;
3754
3755 spin_lock_irqsave(&vector_lock, flags);
3756 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3757 irq_name);
3758 spin_unlock_irqrestore(&vector_lock, flags);
3759
3760 mmr_value = 0;
3761 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3762 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3763
3764 entry->vector = cfg->vector;
3765 entry->delivery_mode = apic->irq_delivery_mode;
3766 entry->dest_mode = apic->irq_dest_mode;
3767 entry->polarity = 0;
3768 entry->trigger = 0;
3769 entry->mask = 0;
3770 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3771
3772 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3773 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3774
3775 return irq;
3776}
3777
3778/*
3779 * Disable the specified MMR located on the specified blade so that MSIs are
3780 * longer allowed to be sent.
3781 */
3782void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3783{
3784 unsigned long mmr_value;
3785 struct uv_IO_APIC_route_entry *entry;
3786 int mmr_pnode;
3787
3788 mmr_value = 0;
3789 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3790 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3791
3792 entry->mask = 1;
3793
3794 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3795 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3796}
3797#endif /* CONFIG_X86_64 */
3798
3799int __init io_apic_get_redir_entries (int ioapic)
3800{
3801 union IO_APIC_reg_01 reg_01;
3802 unsigned long flags;
3803
3804 spin_lock_irqsave(&ioapic_lock, flags);
3805 reg_01.raw = io_apic_read(ioapic, 1);
3806 spin_unlock_irqrestore(&ioapic_lock, flags);
3807
3808 return reg_01.bits.entries;
3809}
3810
3811void __init probe_nr_irqs_gsi(void)
3812{
3813 int nr = 0;
3814
3815 nr = acpi_probe_gsi();
3816 if (nr > nr_irqs_gsi) {
3817 nr_irqs_gsi = nr;
3818 } else {
3819 /* for acpi=off or acpi is not compiled in */
3820 int idx;
3821
3822 nr = 0;
3823 for (idx = 0; idx < nr_ioapics; idx++)
3824 nr += io_apic_get_redir_entries(idx) + 1;
3825
3826 if (nr > nr_irqs_gsi)
3827 nr_irqs_gsi = nr;
3828 }
3829
3830 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3831}
3832
3833#ifdef CONFIG_SPARSE_IRQ
3834int __init arch_probe_nr_irqs(void)
3835{
3836 int nr;
3837
3838 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3839 nr_irqs = NR_VECTORS * nr_cpu_ids;
3840
3841 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3842#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3843 /*
3844 * for MSI and HT dyn irq
3845 */
3846 nr += nr_irqs_gsi * 16;
3847#endif
3848 if (nr < nr_irqs)
3849 nr_irqs = nr;
3850
3851 return 0;
3852}
3853#endif
3854
3855/* --------------------------------------------------------------------------
3856 ACPI-based IOAPIC Configuration
3857 -------------------------------------------------------------------------- */
3858
3859#ifdef CONFIG_ACPI
3860
3861#ifdef CONFIG_X86_32
3862int __init io_apic_get_unique_id(int ioapic, int apic_id)
3863{
3864 union IO_APIC_reg_00 reg_00;
3865 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3866 physid_mask_t tmp;
3867 unsigned long flags;
3868 int i = 0;
3869
3870 /*
3871 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3872 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3873 * supports up to 16 on one shared APIC bus.
3874 *
3875 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3876 * advantage of new APIC bus architecture.
3877 */
3878
3879 if (physids_empty(apic_id_map))
3880 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3881
3882 spin_lock_irqsave(&ioapic_lock, flags);
3883 reg_00.raw = io_apic_read(ioapic, 0);
3884 spin_unlock_irqrestore(&ioapic_lock, flags);
3885
3886 if (apic_id >= get_physical_broadcast()) {
3887 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3888 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3889 apic_id = reg_00.bits.ID;
3890 }
3891
3892 /*
3893 * Every APIC in a system must have a unique ID or we get lots of nice
3894 * 'stuck on smp_invalidate_needed IPI wait' messages.
3895 */
3896 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3897
3898 for (i = 0; i < get_physical_broadcast(); i++) {
3899 if (!apic->check_apicid_used(apic_id_map, i))
3900 break;
3901 }
3902
3903 if (i == get_physical_broadcast())
3904 panic("Max apic_id exceeded!\n");
3905
3906 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3907 "trying %d\n", ioapic, apic_id, i);
3908
3909 apic_id = i;
3910 }
3911
3912 tmp = apic->apicid_to_cpu_present(apic_id);
3913 physids_or(apic_id_map, apic_id_map, tmp);
3914
3915 if (reg_00.bits.ID != apic_id) {
3916 reg_00.bits.ID = apic_id;
3917
3918 spin_lock_irqsave(&ioapic_lock, flags);
3919 io_apic_write(ioapic, 0, reg_00.raw);
3920 reg_00.raw = io_apic_read(ioapic, 0);
3921 spin_unlock_irqrestore(&ioapic_lock, flags);
3922
3923 /* Sanity check */
3924 if (reg_00.bits.ID != apic_id) {
3925 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3926 return -1;
3927 }
3928 }
3929
3930 apic_printk(APIC_VERBOSE, KERN_INFO
3931 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3932
3933 return apic_id;
3934}
3935
3936int __init io_apic_get_version(int ioapic)
3937{
3938 union IO_APIC_reg_01 reg_01;
3939 unsigned long flags;
3940
3941 spin_lock_irqsave(&ioapic_lock, flags);
3942 reg_01.raw = io_apic_read(ioapic, 1);
3943 spin_unlock_irqrestore(&ioapic_lock, flags);
3944
3945 return reg_01.bits.version;
3946}
3947#endif
3948
3949int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3950{
3951 struct irq_desc *desc;
3952 struct irq_cfg *cfg;
3953 int cpu = boot_cpu_id;
3954
3955 if (!IO_APIC_IRQ(irq)) {
3956 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3957 ioapic);
3958 return -EINVAL;
3959 }
3960
3961 desc = irq_to_desc_alloc_cpu(irq, cpu);
3962 if (!desc) {
3963 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3964 return 0;
3965 }
3966
3967 /*
3968 * IRQs < 16 are already in the irq_2_pin[] map
3969 */
3970 if (irq >= NR_IRQS_LEGACY) {
3971 cfg = desc->chip_data;
3972 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3973 }
3974
3975 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3976
3977 return 0;
3978}
3979
3980
3981int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3982{
3983 int i;
3984
3985 if (skip_ioapic_setup)
3986 return -1;
3987
3988 for (i = 0; i < mp_irq_entries; i++)
3989 if (mp_irqs[i].irqtype == mp_INT &&
3990 mp_irqs[i].srcbusirq == bus_irq)
3991 break;
3992 if (i >= mp_irq_entries)
3993 return -1;
3994
3995 *trigger = irq_trigger(i);
3996 *polarity = irq_polarity(i);
3997 return 0;
3998}
3999
4000#endif /* CONFIG_ACPI */
4001
4002/*
4003 * This function currently is only a helper for the i386 smp boot process where
4004 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4005 * so mask in all cases should simply be apic->target_cpus()
4006 */
4007#ifdef CONFIG_SMP
4008void __init setup_ioapic_dest(void)
4009{
4010 int pin, ioapic, irq, irq_entry;
4011 struct irq_desc *desc;
4012 struct irq_cfg *cfg;
4013 const struct cpumask *mask;
4014
4015 if (skip_ioapic_setup == 1)
4016 return;
4017
4018 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4019 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4020 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4021 if (irq_entry == -1)
4022 continue;
4023 irq = pin_2_irq(irq_entry, ioapic, pin);
4024
4025 /* setup_IO_APIC_irqs could fail to get vector for some device
4026 * when you have too many devices, because at that time only boot
4027 * cpu is online.
4028 */
4029 desc = irq_to_desc(irq);
4030 cfg = desc->chip_data;
4031 if (!cfg->vector) {
4032 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4033 irq_trigger(irq_entry),
4034 irq_polarity(irq_entry));
4035 continue;
4036
4037 }
4038
4039 /*
4040 * Honour affinities which have been set in early boot
4041 */
4042 if (desc->status &
4043 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4044 mask = desc->affinity;
4045 else
4046 mask = apic->target_cpus();
4047
4048#ifdef CONFIG_INTR_REMAP
4049 if (intr_remapping_enabled)
4050 set_ir_ioapic_affinity_irq_desc(desc, mask);
4051 else
4052#endif
4053 set_ioapic_affinity_irq_desc(desc, mask);
4054 }
4055
4056 }
4057}
4058#endif
4059
4060#define IOAPIC_RESOURCE_NAME_SIZE 11
4061
4062static struct resource *ioapic_resources;
4063
4064static struct resource * __init ioapic_setup_resources(void)
4065{
4066 unsigned long n;
4067 struct resource *res;
4068 char *mem;
4069 int i;
4070
4071 if (nr_ioapics <= 0)
4072 return NULL;
4073
4074 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4075 n *= nr_ioapics;
4076
4077 mem = alloc_bootmem(n);
4078 res = (void *)mem;
4079
4080 if (mem != NULL) {
4081 mem += sizeof(struct resource) * nr_ioapics;
4082
4083 for (i = 0; i < nr_ioapics; i++) {
4084 res[i].name = mem;
4085 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4086 sprintf(mem, "IOAPIC %u", i);
4087 mem += IOAPIC_RESOURCE_NAME_SIZE;
4088 }
4089 }
4090
4091 ioapic_resources = res;
4092
4093 return res;
4094}
4095
4096void __init ioapic_init_mappings(void)
4097{
4098 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4099 struct resource *ioapic_res;
4100 int i;
4101
4102 ioapic_res = ioapic_setup_resources();
4103 for (i = 0; i < nr_ioapics; i++) {
4104 if (smp_found_config) {
4105 ioapic_phys = mp_ioapics[i].apicaddr;
4106#ifdef CONFIG_X86_32
4107 if (!ioapic_phys) {
4108 printk(KERN_ERR
4109 "WARNING: bogus zero IO-APIC "
4110 "address found in MPTABLE, "
4111 "disabling IO/APIC support!\n");
4112 smp_found_config = 0;
4113 skip_ioapic_setup = 1;
4114 goto fake_ioapic_page;
4115 }
4116#endif
4117 } else {
4118#ifdef CONFIG_X86_32
4119fake_ioapic_page:
4120#endif
4121 ioapic_phys = (unsigned long)
4122 alloc_bootmem_pages(PAGE_SIZE);
4123 ioapic_phys = __pa(ioapic_phys);
4124 }
4125 set_fixmap_nocache(idx, ioapic_phys);
4126 apic_printk(APIC_VERBOSE,
4127 "mapped IOAPIC to %08lx (%08lx)\n",
4128 __fix_to_virt(idx), ioapic_phys);
4129 idx++;
4130
4131 if (ioapic_res != NULL) {
4132 ioapic_res->start = ioapic_phys;
4133 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4134 ioapic_res++;
4135 }
4136 }
4137}
4138
4139static int __init ioapic_insert_resources(void)
4140{
4141 int i;
4142 struct resource *r = ioapic_resources;
4143
4144 if (!r) {
4145 printk(KERN_ERR
4146 "IO APIC resources could be not be allocated.\n");
4147 return -1;
4148 }
4149
4150 for (i = 0; i < nr_ioapics; i++) {
4151 insert_resource(&iomem_resource, r);
4152 r++;
4153 }
4154
4155 return 0;
4156}
4157
4158/* Insert the IO APIC resources after PCI initialization has occured to handle
4159 * IO APICS that are mapped in on a BAR in PCI space. */
4160late_initcall(ioapic_insert_resources);
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-05 10:33:04 -0500