diff options
Diffstat (limited to 'arch/blackfin/mach-bf537/include')
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 6f56907a18c..0323e6bacda 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h | |||
| @@ -1071,50 +1071,6 @@ | |||
| 1071 | #define FPE 0x10 /* Force Parity Error On Transmit */ | 1071 | #define FPE 0x10 /* Force Parity Error On Transmit */ |
| 1072 | #define FFE 0x20 /* Force Framing Error On Transmit */ | 1072 | #define FFE 0x20 /* Force Framing Error On Transmit */ |
| 1073 | 1073 | ||
| 1074 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ | ||
| 1075 | /* SPI_CTL Masks */ | ||
| 1076 | #define TIMOD 0x0003 /* Transfer Initiate Mode */ | ||
| 1077 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ | ||
| 1078 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | ||
| 1079 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | ||
| 1080 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | ||
| 1081 | #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ | ||
| 1082 | #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ | ||
| 1083 | #define PSSE 0x0010 /* Slave-Select Input Enable */ | ||
| 1084 | #define EMISO 0x0020 /* Enable MISO As Output */ | ||
| 1085 | #define SIZE 0x0100 /* Size of Words (16/8* Bits) */ | ||
| 1086 | #define LSBF 0x0200 /* LSB First */ | ||
| 1087 | #define CPHA 0x0400 /* Clock Phase */ | ||
| 1088 | #define CPOL 0x0800 /* Clock Polarity */ | ||
| 1089 | #define MSTR 0x1000 /* Master/Slave* */ | ||
| 1090 | #define WOM 0x2000 /* Write Open Drain Master */ | ||
| 1091 | #define SPE 0x4000 /* SPI Enable */ | ||
| 1092 | |||
| 1093 | /* SPI_FLG Masks */ | ||
| 1094 | #define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ | ||
| 1095 | #define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ | ||
| 1096 | #define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ | ||
| 1097 | #define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ | ||
| 1098 | #define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ | ||
| 1099 | #define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ | ||
| 1100 | #define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ | ||
| 1101 | #define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ | ||
| 1102 | #define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ | ||
| 1103 | #define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ | ||
| 1104 | #define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ | ||
| 1105 | #define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ | ||
| 1106 | #define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ | ||
| 1107 | #define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ | ||
| 1108 | |||
| 1109 | /* SPI_STAT Masks */ | ||
| 1110 | #define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ | ||
| 1111 | #define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ | ||
| 1112 | #define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ | ||
| 1113 | #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ | ||
| 1114 | #define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ | ||
| 1115 | #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ | ||
| 1116 | #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ | ||
| 1117 | |||
| 1118 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ | 1074 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ |
| 1119 | /* TIMER_ENABLE Masks */ | 1075 | /* TIMER_ENABLE Masks */ |
| 1120 | #define TIMEN0 0x0001 /* Enable Timer 0 */ | 1076 | #define TIMEN0 0x0001 /* Enable Timer 0 */ |