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-rw-r--r--arch/arm/mach-pxa/include/mach/balloon3.h10
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/irqs.h153
-rw-r--r--arch/arm/mach-pxa/include/mach/lpd270.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/lubbock.h11
-rw-r--r--arch/arm/mach-pxa/include/mach/mainstone.h17
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa25x.h32
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa27x.h27
-rw-r--r--arch/arm/mach-pxa/include/mach/mxm8x10.h21
-rw-r--r--arch/arm/mach-pxa/include/mach/pcm027.h7
-rw-r--r--arch/arm/mach-pxa/include/mach/ssp.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/uncompress.h41
-rw-r--r--arch/arm/mach-pxa/include/mach/zeus.h3
13 files changed, 169 insertions, 160 deletions
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index bfec09b1814..1a741065045 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -129,6 +129,16 @@ enum balloon3_features {
129#define CPLD_AROUTING_LOONR2INT_BIT 6 129#define CPLD_AROUTING_LOONR2INT_BIT 6
130#define CPLD_AROUTING_LOONR2EXT_BIT 7 130#define CPLD_AROUTING_LOONR2EXT_BIT 7
131 131
132/* Balloon3 Interrupts */
133#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x))
134
135#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
136#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1)
137
138#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ)
139#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
140#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD)
141
132extern int balloon3_has(enum balloon3_features feature); 142extern int balloon3_has(enum balloon3_features feature);
133 143
134#endif 144#endif
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index e741bf1bfb2..7515757d691 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -314,7 +314,6 @@ extern unsigned long get_clock_tick_rate(void);
314#define PCIBIOS_MIN_IO 0 314#define PCIBIOS_MIN_IO 0
315#define PCIBIOS_MIN_MEM 0 315#define PCIBIOS_MIN_MEM 0
316#define pcibios_assign_all_busses() 1 316#define pcibios_assign_all_busses() 1
317#define HAVE_ARCH_PCI_SET_DMA_MASK 1
318#endif 317#endif
319 318
320 319
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 3677a9af9c8..ffc8314520f 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -135,82 +135,6 @@
135#define IRQ_BOARD_END (IRQ_BOARD_START + 16) 135#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
136#endif 136#endif
137 137
138#define IRQ_SA1111_START (IRQ_BOARD_END)
139#define IRQ_GPAIN0 (IRQ_BOARD_END + 0)
140#define IRQ_GPAIN1 (IRQ_BOARD_END + 1)
141#define IRQ_GPAIN2 (IRQ_BOARD_END + 2)
142#define IRQ_GPAIN3 (IRQ_BOARD_END + 3)
143#define IRQ_GPBIN0 (IRQ_BOARD_END + 4)
144#define IRQ_GPBIN1 (IRQ_BOARD_END + 5)
145#define IRQ_GPBIN2 (IRQ_BOARD_END + 6)
146#define IRQ_GPBIN3 (IRQ_BOARD_END + 7)
147#define IRQ_GPBIN4 (IRQ_BOARD_END + 8)
148#define IRQ_GPBIN5 (IRQ_BOARD_END + 9)
149#define IRQ_GPCIN0 (IRQ_BOARD_END + 10)
150#define IRQ_GPCIN1 (IRQ_BOARD_END + 11)
151#define IRQ_GPCIN2 (IRQ_BOARD_END + 12)
152#define IRQ_GPCIN3 (IRQ_BOARD_END + 13)
153#define IRQ_GPCIN4 (IRQ_BOARD_END + 14)
154#define IRQ_GPCIN5 (IRQ_BOARD_END + 15)
155#define IRQ_GPCIN6 (IRQ_BOARD_END + 16)
156#define IRQ_GPCIN7 (IRQ_BOARD_END + 17)
157#define IRQ_MSTXINT (IRQ_BOARD_END + 18)
158#define IRQ_MSRXINT (IRQ_BOARD_END + 19)
159#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20)
160#define IRQ_TPTXINT (IRQ_BOARD_END + 21)
161#define IRQ_TPRXINT (IRQ_BOARD_END + 22)
162#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23)
163#define SSPXMTINT (IRQ_BOARD_END + 24)
164#define SSPRCVINT (IRQ_BOARD_END + 25)
165#define SSPROR (IRQ_BOARD_END + 26)
166#define AUDXMTDMADONEA (IRQ_BOARD_END + 32)
167#define AUDRCVDMADONEA (IRQ_BOARD_END + 33)
168#define AUDXMTDMADONEB (IRQ_BOARD_END + 34)
169#define AUDRCVDMADONEB (IRQ_BOARD_END + 35)
170#define AUDTFSR (IRQ_BOARD_END + 36)
171#define AUDRFSR (IRQ_BOARD_END + 37)
172#define AUDTUR (IRQ_BOARD_END + 38)
173#define AUDROR (IRQ_BOARD_END + 39)
174#define AUDDTS (IRQ_BOARD_END + 40)
175#define AUDRDD (IRQ_BOARD_END + 41)
176#define AUDSTO (IRQ_BOARD_END + 42)
177#define IRQ_USBPWR (IRQ_BOARD_END + 43)
178#define IRQ_HCIM (IRQ_BOARD_END + 44)
179#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45)
180#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46)
181#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47)
182#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48)
183#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49)
184#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50)
185#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51)
186#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52)
187#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53)
188#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54)
189
190#define IRQ_LOCOMO_START (IRQ_BOARD_END)
191#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0)
192#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1)
193#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2)
194#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3)
195#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4)
196#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5)
197#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6)
198#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7)
199#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8)
200#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9)
201#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10)
202#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11)
203#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12)
204#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13)
205#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14)
206#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15)
207#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16)
208#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17)
209#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18)
210#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19)
211#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20)
212#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21)
213
214/* 138/*
215 * Figure out the MAX IRQ number. 139 * Figure out the MAX IRQ number.
216 * 140 *
@@ -219,89 +143,16 @@
219 * Otherwise, we have the standard IRQs only. 143 * Otherwise, we have the standard IRQs only.
220 */ 144 */
221#ifdef CONFIG_SA1111 145#ifdef CONFIG_SA1111
222#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) 146#define NR_IRQS (IRQ_BOARD_END + 55)
223#elif defined(CONFIG_SHARP_LOCOMO)
224#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
225#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS) 147#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
226#define NR_IRQS (IRQ_BOARD_END) 148#define NR_IRQS (IRQ_BOARD_END)
227#else 149#else
228#define NR_IRQS (IRQ_BOARD_START) 150#define NR_IRQS (IRQ_BOARD_START)
229#endif 151#endif
230 152
231/*
232 * Board specific IRQs. Define them here.
233 * Do not surround them with ifdefs.
234 */
235#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x))
236#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
237#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
238#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
239#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3)
240#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4)
241#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5)
242#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
243#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
244
245#define LPD270_IRQ(x) (IRQ_BOARD_START + (x))
246#define LPD270_USBC_IRQ LPD270_IRQ(2)
247#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
248#define LPD270_AC97_IRQ LPD270_IRQ(4)
249
250#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
251#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
252#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
253#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
254#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3)
255#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4)
256#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5)
257#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6)
258#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7)
259#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9)
260#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
261#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11)
262#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13)
263#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
264#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
265
266/* Balloon3 Interrupts */
267#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x))
268
269#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
270#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1)
271
272#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ)
273#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
274#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD)
275
276/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
277#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0)
278#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
279#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
280#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
281
282/* phyCORE-PXA270 (PCM027) Interrupts */
283#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
284#define PCM027_BTDET_IRQ PCM027_IRQ(0)
285#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
286#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
287#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
288
289/* ITE8152 irqs */
290/* add IT8152 IRQs beyond BOARD_END */ 153/* add IT8152 IRQs beyond BOARD_END */
291#ifdef CONFIG_PCI_HOST_ITE8152 154#ifdef CONFIG_PCI_HOST_ITE8152
292#define IT8152_IRQ(x) (IRQ_BOARD_END + (x)) 155#define IT8152_LAST_IRQ (IRQ_BOARD_END + 40)
293
294/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
295#define IT8152_LD_IRQ_COUNT 9
296#define IT8152_LP_IRQ_COUNT 16
297#define IT8152_PD_IRQ_COUNT 15
298
299/* Priorities: */
300#define IT8152_PD_IRQ(i) IT8152_IRQ(i)
301#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
302#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
303
304#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
305 156
306#if NR_IRQS < (IT8152_LAST_IRQ+1) 157#if NR_IRQS < (IT8152_LAST_IRQ+1)
307#undef NR_IRQS 158#undef NR_IRQS
diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h
index f89fb715266..0e6440c8168 100644
--- a/arch/arm/mach-pxa/include/mach/lpd270.h
+++ b/arch/arm/mach-pxa/include/mach/lpd270.h
@@ -34,5 +34,9 @@
34#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ 34#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
35#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ 35#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */
36 36
37#define LPD270_IRQ(x) (IRQ_BOARD_START + (x))
38#define LPD270_USBC_IRQ LPD270_IRQ(2)
39#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
40#define LPD270_AC97_IRQ LPD270_IRQ(4)
37 41
38#endif 42#endif
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index 751b74811d0..a0d4247f08f 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -34,6 +34,17 @@
34#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) 34#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
35#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) 35#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
36 36
37/* Board specific IRQs */
38#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x))
39#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
40#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
41#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
42#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3)
43#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4)
44#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5)
45#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
46#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
47
37#ifndef __ASSEMBLY__ 48#ifndef __ASSEMBLY__
38extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); 49extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
39#endif 50#endif
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
index 3461c4302ff..86e623abd64 100644
--- a/arch/arm/mach-pxa/include/mach/mainstone.h
+++ b/arch/arm/mach-pxa/include/mach/mainstone.h
@@ -117,4 +117,21 @@
117#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ 117#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */
118#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ 118#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */
119 119
120/* board specific IRQs */
121#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
122#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
123#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
124#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
125#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3)
126#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4)
127#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5)
128#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6)
129#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7)
130#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9)
131#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
132#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11)
133#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13)
134#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
135#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
136
120#endif 137#endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index 9c787855cf2..cafadc33dfd 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -190,4 +190,36 @@
190#define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) 190#define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH)
191#endif /* CONFIG_CPU_PXA26x */ 191#endif /* CONFIG_CPU_PXA26x */
192 192
193/* commonly used pin configurations */
194#define GPIOxx_LCD_16BPP \
195 GPIO58_LCD_LDD_0, \
196 GPIO59_LCD_LDD_1, \
197 GPIO60_LCD_LDD_2, \
198 GPIO61_LCD_LDD_3, \
199 GPIO62_LCD_LDD_4, \
200 GPIO63_LCD_LDD_5, \
201 GPIO64_LCD_LDD_6, \
202 GPIO65_LCD_LDD_7, \
203 GPIO66_LCD_LDD_8, \
204 GPIO67_LCD_LDD_9, \
205 GPIO68_LCD_LDD_10, \
206 GPIO69_LCD_LDD_11, \
207 GPIO70_LCD_LDD_12, \
208 GPIO71_LCD_LDD_13, \
209 GPIO72_LCD_LDD_14, \
210 GPIO73_LCD_LDD_15
211
212#define GPIOxx_LCD_DSTN_16BPP \
213 GPIOxx_LCD_16BPP, \
214 GPIO74_LCD_FCLK, \
215 GPIO75_LCD_LCLK, \
216 GPIO76_LCD_PCLK
217
218#define GPIOxx_LCD_TFT_16BPP \
219 GPIOxx_LCD_16BPP, \
220 GPIO74_LCD_FCLK, \
221 GPIO75_LCD_LCLK, \
222 GPIO76_LCD_PCLK, \
223 GPIO77_LCD_BIAS
224
193#endif /* __ASM_ARCH_MFP_PXA25X_H */ 225#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index 6543c05f47e..ec0f0b0b674 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -434,5 +434,32 @@
434#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) 434#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2)
435#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) 435#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
436 436
437/* commonly used pin configurations */
438#define GPIOxx_LCD_16BPP \
439 GPIO58_LCD_LDD_0, \
440 GPIO59_LCD_LDD_1, \
441 GPIO60_LCD_LDD_2, \
442 GPIO61_LCD_LDD_3, \
443 GPIO62_LCD_LDD_4, \
444 GPIO63_LCD_LDD_5, \
445 GPIO64_LCD_LDD_6, \
446 GPIO65_LCD_LDD_7, \
447 GPIO66_LCD_LDD_8, \
448 GPIO67_LCD_LDD_9, \
449 GPIO68_LCD_LDD_10, \
450 GPIO69_LCD_LDD_11, \
451 GPIO70_LCD_LDD_12, \
452 GPIO71_LCD_LDD_13, \
453 GPIO72_LCD_LDD_14, \
454 GPIO73_LCD_LDD_15
455
456#define GPIOxx_LCD_TFT_16BPP \
457 GPIOxx_LCD_16BPP, \
458 GPIO74_LCD_FCLK, \
459 GPIO75_LCD_LCLK, \
460 GPIO76_LCD_PCLK, \
461 GPIO77_LCD_BIAS
462
463
437extern int keypad_set_wake(unsigned int on); 464extern int keypad_set_wake(unsigned int on);
438#endif /* __ASM_ARCH_MFP_PXA27X_H */ 465#endif /* __ASM_ARCH_MFP_PXA27X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mxm8x10.h b/arch/arm/mach-pxa/include/mach/mxm8x10.h
new file mode 100644
index 00000000000..ffa15665a41
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mxm8x10.h
@@ -0,0 +1,21 @@
1#ifndef __MACH_MXM_8X10_H
2#define __MACH_MXM_8X10_H
3
4#define MXM_8X10_ETH_PHYS 0x13000000
5
6#if defined(CONFIG_MMC)
7
8#define MXM_8X10_SD_nCD (72)
9#define MXM_8X10_SD_WP (84)
10
11extern void mxm_8x10_mmc_init(void);
12#else
13static inline void mxm_8x10_mmc_init(void) {}
14#endif
15
16extern void mxm_8x10_usb_host_init(void);
17extern void mxm_8x10_ac97_init(void);
18
19extern void mxm_8x10_barebones_init(void);
20
21#endif /* __MACH_MXM_8X10_H */
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
index 4dcd2e8baa6..04083263167 100644
--- a/arch/arm/mach-pxa/include/mach/pcm027.h
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -23,6 +23,13 @@
23 * Definitions of CPU card resources only 23 * Definitions of CPU card resources only
24 */ 24 */
25 25
26/* phyCORE-PXA270 (PCM027) Interrupts */
27#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
28#define PCM027_BTDET_IRQ PCM027_IRQ(0)
29#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
30#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
31#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
32
26/* I2C RTC */ 33/* I2C RTC */
27#define PCM027_RTC_IRQ_GPIO 0 34#define PCM027_RTC_IRQ_GPIO 0
28#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) 35#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h
index cb5cb766f0f..be1be5b6db5 100644
--- a/arch/arm/mach-pxa/include/mach/ssp.h
+++ b/arch/arm/mach-pxa/include/mach/ssp.h
@@ -46,6 +46,7 @@ struct ssp_device {
46 int drcmr_tx; 46 int drcmr_tx;
47}; 47};
48 48
49#ifdef CONFIG_PXA_SSP_LEGACY
49/* 50/*
50 * SSP initialisation flags 51 * SSP initialisation flags
51 */ 52 */
@@ -78,6 +79,7 @@ void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
78int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags); 79int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
79int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); 80int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
80void ssp_exit(struct ssp_dev *dev); 81void ssp_exit(struct ssp_dev *dev);
82#endif /* CONFIG_PXA_SSP_LEGACY */
81 83
82/** 84/**
83 * ssp_write_reg - Write to a SSP register 85 * ssp_write_reg - Write to a SSP register
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 237734b5b1b..5ef91d9d17e 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -10,20 +10,41 @@
10 */ 10 */
11 11
12#include <linux/serial_reg.h> 12#include <linux/serial_reg.h>
13#include <mach/regs-uart.h>
14#include <asm/mach-types.h> 13#include <asm/mach-types.h>
15 14
16#define __REG(x) ((volatile unsigned long *)x) 15#define FFUART_BASE (0x40100000)
16#define BTUART_BASE (0x40200000)
17#define STUART_BASE (0x40700000)
17 18
18static volatile unsigned long *UART = FFUART; 19static unsigned long uart_base = FFUART_BASE;
20static unsigned int uart_shift = 2;
21static unsigned int uart_is_pxa = 1;
22
23static inline unsigned char uart_read(int offset)
24{
25 return *(volatile unsigned char *)(uart_base + (offset << uart_shift));
26}
27
28static inline void uart_write(unsigned char val, int offset)
29{
30 *(volatile unsigned char *)(uart_base + (offset << uart_shift)) = val;
31}
32
33static inline int uart_is_enabled(void)
34{
35 /* assume enabled by default for non-PXA uarts */
36 return uart_is_pxa ? uart_read(UART_IER) & UART_IER_UUE : 1;
37}
19 38
20static inline void putc(char c) 39static inline void putc(char c)
21{ 40{
22 if (!(UART[UART_IER] & IER_UUE)) 41 if (!uart_is_enabled())
23 return; 42 return;
24 while (!(UART[UART_LSR] & LSR_TDRQ)) 43
44 while (!(uart_read(UART_LSR) & UART_LSR_THRE))
25 barrier(); 45 barrier();
26 UART[UART_TX] = c; 46
47 uart_write(c, UART_TX);
27} 48}
28 49
29/* 50/*
@@ -38,7 +59,13 @@ static inline void arch_decomp_setup(void)
38 if (machine_is_littleton() || machine_is_intelmote2() 59 if (machine_is_littleton() || machine_is_intelmote2()
39 || machine_is_csb726() || machine_is_stargate2() 60 || machine_is_csb726() || machine_is_stargate2()
40 || machine_is_cm_x300() || machine_is_balloon3()) 61 || machine_is_cm_x300() || machine_is_balloon3())
41 UART = STUART; 62 uart_base = STUART_BASE;
63
64 if (machine_is_arcom_zeus()) {
65 uart_base = 0x10000000; /* nCS4 */
66 uart_shift = 1;
67 uart_is_pxa = 0;
68 }
42} 69}
43 70
44/* 71/*
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index c387046d2f2..6e119976003 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -58,6 +58,8 @@
58#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) 58#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x))
59#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) 59#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x))
60 60
61#define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2)
62
61/* 63/*
62 * CPLD registers: 64 * CPLD registers:
63 * Only 4 registers, but spreaded over a 32MB address space. 65 * Only 4 registers, but spreaded over a 32MB address space.
@@ -68,7 +70,6 @@
68#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) 70#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000)
69#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) 71#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000)
70#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) 72#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000)
71#define ZEUS_CPLD_EXTWDOG (ZEUS_CPLD + 0x3000)
72 73
73/* CPLD register bits */ 74/* CPLD register bits */
74#define ZEUS_CPLD_CONTROL_CF_RST 0x01 75#define ZEUS_CPLD_CONTROL_CF_RST 0x01
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 03:47:52 -0500