diff options
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c19aecdb202..f3fa1c32fe9 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
| @@ -234,7 +234,6 @@ __v7_setup: | |||
| 234 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 234 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
| 235 | mov r10, #0x1f @ domains 0, 1 = manager | 235 | mov r10, #0x1f @ domains 0, 1 = manager |
| 236 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register | 236 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register |
| 237 | #endif | ||
| 238 | /* | 237 | /* |
| 239 | * Memory region attributes with SCTLR.TRE=1 | 238 | * Memory region attributes with SCTLR.TRE=1 |
| 240 | * | 239 | * |
| @@ -267,6 +266,7 @@ __v7_setup: | |||
| 267 | ldr r6, =0x40e040e0 @ NMRR | 266 | ldr r6, =0x40e040e0 @ NMRR |
| 268 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR | 267 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR |
| 269 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR | 268 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR |
| 269 | #endif | ||
| 270 | adr r5, v7_crval | 270 | adr r5, v7_crval |
| 271 | ldmia r5, {r5, r6} | 271 | ldmia r5, {r5, r6} |
| 272 | #ifdef CONFIG_CPU_ENDIAN_BE8 | 272 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
