litmus-rt-pandaboard.git/arch/x86/kernel/cpu, branch pandaboard-litmus

Merge remote-tracking branch 'oneiric-ubuntu/pandaboard' into pandaboard-litmus

2012-09-20T17:33:17+00:00

Remote branch is from Ubuntu Oneiric (tag Ubuntu-3.0.0-1215.27) with
minor patch to the TWL-RTC code. Trying to pull this into LITMUS^RT
staging (as of 9/20/2012) to get LITMUS^RT running on the PandaBoard.

Conflicts:
	Makefile
	fs/exec.c
	include/linux/fs.h
	kernel/fork.c

x86, mce, therm_throt: Don't report power limit and package level thermal throttle events in mcelog

2012-07-23T09:50:29+00:00

BugLink: http://bugs.launchpad.net/bugs/930288

Thermal throttle and power limit events are not defined as MCE errors in x86
architecture and should not generate MCE errors in mcelog.

Current kernel generates fake software defined MCE errors for these events.
This may confuse users because they may think the machine has real MCE errors
while actually only thermal throttle or power limit events happen.

To make it worse, buggy firmware on some platforms may falsely generate
the events. Therefore, kernel reports MCE errors which users think as real
hardware errors. Although the firmware bugs should be fixed, on the other hand,
kernel should not report MCE errors either.

So mcelog is not a good mechanism to report these events. To report the events, we count them in respective counters (core_power_limit_count,
package_power_limit_count, core_throttle_count, and package_throttle_count) in
/sys/devices/system/cpu/cpu#/thermal_throttle/. Users can check the counters
for each event on each CPU. Please note that all CPU's on one package report
duplicate counters. It's user application's responsibity to retrieve a package
level counter for one package.

This patch doesn't report package level power limit, core level power limit, and
package level thermal throttle events in mcelog. When the events happen, only
report them in respective counters in sysfs.

Since core level thermal throttle has been legacy code in kernel for a while and
users accepted it as MCE error in mcelog, core level thermal throttle is still
reported in mcelog. In the mean time, the event is counted in a counter in sysfs
as well.

Signed-off-by: Fenghua Yu 
Acked-by: Borislav Petkov 
Acked-by: Tony Luck 
Link: http://lkml.kernel.org/r/20111215001945.GA21009@linux-os.sc.intel.com
Signed-off-by: H. Peter Anvin 
(cherry picked from commit 29e9bf1841e4f9df13b4992a716fece7087dd237)

Acked-by: Brad Figg 
Signed-off-by: Tim Gardner

x86, cpufeature: Rename X86_FEATURE_DTS to X86_FEATURE_DTHERM

2012-07-23T09:50:28+00:00

BugLink: http://bugs.launchpad.net/bugs/1025406

commit 4ad33411308596f2f918603509729922a1ec4411 upstream.

It makes sense to label "Digital Thermal Sensor" as "DTS", but
unfortunately the string "dts" was already used for "Debug Store", and
/proc/cpuinfo is a user space ABI.

Therefore, rename this to "dtherm".

This conflict went into mainline via the hwmon tree without any x86
maintainer ack, and without any kind of hint in the subject.

    a4659053 x86/hwmon: fix initialization of coretemp

Reported-by: Jean Delvare 
Link: http://lkml.kernel.org/r/4FE34BCB.5050305@linux.intel.com
Cc: Jan Beulich 
Signed-off-by: H. Peter Anvin 
[bwh: Backported to 3.2: drop the coretemp device table change]
Signed-off-by: Ben Hutchings 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Herton Ronaldo Krzesinski

x86, MCE, AMD: Make APIC LVT thresholding interrupt optional

2012-07-03T15:29:08+00:00

BugLink: http://bugs.launchpad.net/bugs/1014712

commit f227d4306cf30e1d5b6f231e8ef9006c34f3d186 upstream.

Currently, the APIC LVT interrupt for error thresholding is implicitly
enabled. However, there are models in the F15h range which do not enable
it. Make the code machinery which sets up the APIC interrupt support
an optional setting and add an ->interrupt_capable member to the bank
representation mirroring that capability and enable the interrupt offset
programming only if it is true.

Simplify code and fixup comment style while at it.

Signed-off-by: Borislav Petkov 
Signed-off-by: Robert Richter 
Signed-off-by: Herton Ronaldo Krzesinski

x86/amd: Re-enable CPU topology extensions in case BIOS has disabled it

2012-07-03T15:28:58+00:00

BugLink: http://bugs.launchpad.net/bugs/1009087

BIOS will switch off the corresponding feature flag on family
15h models 10h-1fh non-desktop CPUs.

The topology extension CPUID leafs are required to detect which
cores belong to the same compute unit. (thread siblings mask is
set accordingly and also correct information about L1i and L2
cache sharing depends on this).

W/o this patch we wouldn't see which cores belong to the same
compute unit and also cache sharing information for L1i and L2
would be incorrect on such systems.

Signed-off-by: Andreas Herrmann 
Signed-off-by: Ingo Molnar 
(cherry picked from commit f7f286a910221ae18b21c18d9d0f4cd88965829f)

Signed-off-by: Tim Gardner 
Acked-by: Brad Figg 
Acked-by: Herton Krzesinski 
Signed-off-by: Stefan Bader

x86/mce: Fix check for processor context when machine check was taken.

2012-06-12T09:59:16+00:00

BugLink: http://bugs.launchpad.net/bugs/1008697

commit 875e26648cf9b6db9d8dc07b7959d7c61fb3f49c upstream.

Linus pointed out that there was no value is checking whether m->ip
was zero - because zero is a legimate value.  If we have a reliable
(or faked in the VM86 case) "m->cs" we can use it to tell whether we
were in user mode or kernelwhen the machine check hit.

Reported-by: Linus Torvalds 
Signed-off-by: Tony Luck 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Herton Ronaldo Krzesinski

perf/x86: Update event scheduling constraints for AMD family 15h models

2012-06-12T09:59:11+00:00

BugLink: http://bugs.launchpad.net/bugs/1008697

commit 5bcdf5e4fee3c45e1281c25e4941f2163cb28c65 upstream.

This update is for newer family 15h cpu models from 0x02 to 0x1f.

Signed-off-by: Robert Richter 
Acked-by: Peter Zijlstra 
Cc: Stephane Eranian 
Link: http://lkml.kernel.org/r/1337337642-1621-1-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Herton Ronaldo Krzesinski

x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors

2012-03-26T09:26:45+00:00

BugLink: http://bugs.launchpad.net/bugs/954576

commit 32c3233885eb10ac9cb9410f2f8cd64b8df2b2a1 upstream.

For L1 instruction cache and L2 cache the shared CPU information
is wrong. On current AMD family 15h CPUs those caches are shared
between both cores of a compute unit.

This fixes https://bugzilla.kernel.org/show_bug.cgi?id=42607

Signed-off-by: Andreas Herrmann 
Cc: Petkov Borislav 
Cc: Dave Jones 
Link: http://lkml.kernel.org/r/20120208195229.GA17523@alberich.amd.com
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman

perf/x86: Fix PEBS instruction unwind

2011-12-12T13:07:09+00:00

BugLink: http://bugs.launchpad.net/bugs/902312

commit 57d1c0c03c6b48b2b96870d831b9ce6b917f53ac upstream.

Masami spotted that we always try to decode the instruction stream as
64bit instructions when running a 64bit kernel, this doesn't work for
ia32-compat proglets.

Use TIF_IA32 to detect if we need to use the 32bit instruction
decoder.

Reported-by: Masami Hiramatsu 
Signed-off-by: Peter Zijlstra 
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Tim Gardner

perf, x86: Add model 45 SandyBridge support

2011-10-17T17:33:05+00:00

BugLink: http://bugs.launchpad.net/bugs/868628

commit a34668f6beb4ab01e07683276d6a24bab6c175e0 upstream.

Add support to Romely-EP SandyBridge.

Signed-off-by: Youquan Song 
Signed-off-by: Anhua Xu 
Signed-off-by: Lin Ming 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1312264895-2010-1-git-send-email-youquan.song@intel.com
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman