litmus-rt-pandaboard.git/arch/arm/include/asm, branch pandaboard-litmus LITMUS^RT and MC^2 V0 support for the pandaboard. Merge remote-tracking branch 'oneiric-ubuntu/pandaboard' into pandaboard-litmus 2012-09-20T17:33:17+00:00 Christopher Kenna cjk@cs.unc.edu 2012-09-20T17:33:17+00:00 5e0a4919ccb230ab449826ef91bdf38a4ed283e5 Remote branch is from Ubuntu Oneiric (tag Ubuntu-3.0.0-1215.27) with minor patch to the TWL-RTC code. Trying to pull this into LITMUS^RT staging (as of 9/20/2012) to get LITMUS^RT running on the PandaBoard. Conflicts: Makefile fs/exec.c include/linux/fs.h kernel/fork.c 
Remote branch is from Ubuntu Oneiric (tag Ubuntu-3.0.0-1215.27) with
minor patch to the TWL-RTC code. Trying to pull this into LITMUS^RT
staging (as of 9/20/2012) to get LITMUS^RT running on the PandaBoard.

Conflicts:
	Makefile
	fs/exec.c
	include/linux/fs.h
	kernel/fork.c
ARM: cache-l2x0: update workaround for PL310 errata 727915 2012-08-17T08:19:22+00:00 Colin Cross ccross@android.com 2011-09-23T17:31:21+00:00 0445c4a12f7bb34eea340033a0a60d7e7001b533 ARM errata 727915 for PL310 has been updated to include a new workaround required for PL310 r2p0 for l2x0_flush_all, which also affects l2x0_clean_all in my testing. For r2p0, clean or flush each set/way individually. For r3p0 or greater, use the debug register for cleaning and flushing. Requires exporting the cache_id, sets and ways detected in the init function for later use. Change-Id: I215055cbe5dc7e4e8184fb2befc4aff672ef0a12 Signed-off-by: Colin Cross <ccross@android.com> 
ARM errata 727915 for PL310 has been updated to include a new
workaround required for PL310 r2p0 for l2x0_flush_all, which also
affects l2x0_clean_all in my testing.  For r2p0, clean or flush
each set/way individually.  For r3p0 or greater, use the debug
register for cleaning and flushing.

Requires exporting the cache_id, sets and ways detected in the
init function for later use.

Change-Id: I215055cbe5dc7e4e8184fb2befc4aff672ef0a12
Signed-off-by: Colin Cross <ccross@android.com>
OMAP: SYSLINK: cacheflush 2012-08-17T08:19:17+00:00 Hari Kanigeri h-kanigeri2@ti.com 2010-09-15T05:35:03+00:00 13854bf25971da775dbec5545879c14ce66dd0a4 Revert "ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range" This reverts commit 702b94bff3c50542a6e4ab9a4f4cef093262fe65 Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> 
Revert "ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range"

    This reverts commit 702b94bff3c50542a6e4ab9a4f4cef093262fe65

Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
ARM: L2: Add and export outer_clean_all 2012-08-17T08:18:07+00:00 Vikram Pandita vikram.pandita@ti.com 2011-07-24T19:59:06+00:00 5495af73a0158f6642d4f9a58d6821143a93254e The Errata 588369 and 539766 demands that clean all operation be done as clean each way at a time This patch also raps the implementation under the CONFIG errata macro so that for non-errata version silicon it can be disabled Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Woodruff, Richard <r-woodruff2@ti.com> 
The Errata 588369 and 539766 demands that clean all operation be done
as clean each way at a time

This patch also raps the implementation under the CONFIG errata
macro so that for non-errata version silicon it can be disabled

Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Woodruff, Richard <r-woodruff2@ti.com>
ARM: L2X0: Add the Prefetch Control Register bits to header. 2012-08-17T08:18:04+00:00 Santosh Shilimkar santosh.shilimkar@ti.com 2011-07-24T19:57:51+00:00 71381033b87251a45319b4bd99e679c243b4e75f While at this, fix some indentation issues in cache-l2x0.h Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> 
While at this, fix some indentation issues in cache-l2x0.h

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP4460: L2X0: Temporary work-around for stability. 2012-08-17T08:18:03+00:00 Santosh Shilimkar santosh.shilimkar@ti.com 2011-07-24T19:57:49+00:00 e7bb65363f2c91636b24f4f1579151325f6e615a OMAP4460 ES1.0 seems to suffer from stability with L2 cache enabled. The root-cause analysis is ongoing but in meantime this chabe is to enable a software WA with L2 cache enabled build. The WA consist of locking certain cache ways based on their positions on the physical memory layout. Downside of this WA is that effective L2 cache size will be 512 KB instead of 1 MB. Of course this is temporary WA and needs to removed once the root cause and the right fix is found. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> 
OMAP4460 ES1.0 seems to suffer from stability with L2 cache enabled.
The root-cause analysis is ongoing but in meantime this chabe is
to enable a software WA with L2 cache enabled build. The WA consist
of locking certain cache ways based on their positions on the
physical memory layout.

Downside of this WA is that effective L2 cache size will be 512 KB
instead of 1 MB.

Of course this is temporary WA and needs to removed once the root
cause and the right fix is found.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: 7365/1: drop unused parameter from flush_cache_user_range 2012-06-12T09:59:16+00:00 Dima Zavin dima@android.com 2012-03-29T19:44:06+00:00 99a98086bb950128e611aefa8d042caf81954f00 BugLink: http://bugs.launchpad.net/bugs/1008697 commit 4542b6a0fa6b48d9ae6b41c1efeb618b7a221b2a upstream. vma isn't used and flush_cache_user_range isn't a standard macro that is used on several archs with the same prototype. In fact only unicore32 has a macro with the same name (with an identical implementation and no in-tree users). This is a part of a patch proposed by Dima Zavin (with Message-id: 1272439931-12795-1-git-send-email-dima@android.com) that didn't get accepted. Cc: Dima Zavin <dima@android.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com> 
BugLink: http://bugs.launchpad.net/bugs/1008697

commit 4542b6a0fa6b48d9ae6b41c1efeb618b7a221b2a upstream.

vma isn't used and flush_cache_user_range isn't a standard macro that
is used on several archs with the same prototype. In fact only unicore32
has a macro with the same name (with an identical implementation and no
in-tree users).

This is a part of a patch proposed by Dima Zavin (with Message-id:
1272439931-12795-1-git-send-email-dima@android.com) that didn't get
accepted.

Cc: Dima Zavin <dima@android.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
ARM: 7403/1: tls: remove covert channel via TPIDRURW 2012-05-25T16:24:38+00:00 Will Deacon will.deacon@arm.com 2012-04-27T11:45:07+00:00 7eb25b1fe17b8818cd7007bf895cc63f2b9ef663 BugLink: http://bugs.launchpad.net/bugs/996109 commit 6a1c53124aa161eb624ce7b1e40ade728186d34c upstream. TPIDRURW is a user read/write register forming part of the group of thread registers in more recent versions of the ARM architecture (~v6+). Currently, the kernel does not touch this register, which allows tasks to communicate covertly by reading and writing to the register without context-switching affecting its contents. This patch clears TPIDRURW when TPIDRURO is updated via the set_tls macro, which is called directly from __switch_to. Since the current behaviour makes the register useless to userspace as far as thread pointers are concerned, simply clearing the register (rather than saving and restoring it) will not cause any problems to userspace. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
BugLink: http://bugs.launchpad.net/bugs/996109

commit 6a1c53124aa161eb624ce7b1e40ade728186d34c upstream.

TPIDRURW is a user read/write register forming part of the group of
thread registers in more recent versions of the ARM architecture (~v6+).

Currently, the kernel does not touch this register, which allows tasks
to communicate covertly by reading and writing to the register without
context-switching affecting its contents.

This patch clears TPIDRURW when TPIDRURO is updated via the set_tls
macro, which is called directly from __switch_to. Since the current
behaviour makes the register useless to userspace as far as thread
pointers are concerned, simply clearing the register (rather than saving
and restoring it) will not cause any problems to userspace.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: 7325/1: fix v7 boot with lockdep enabled 2012-03-26T09:26:36+00:00 Rabin Vincent rabin@rab.in 2012-02-15T15:01:42+00:00 17fd8368e493ba11cec20bbf6201c4ffe6a22efb BugLink: http://bugs.launchpad.net/bugs/954576 commit 8e43a905dd574f54c5715d978318290ceafbe275 upstream. Bootup with lockdep enabled has been broken on v7 since b46c0f74657d ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). This is because v7_setup (which is called very early during boot) calls v7_flush_dcache_all, and the save_and_disable_irqs added by that patch ends up attempting to call into lockdep C code (trace_hardirqs_off()) when we are in no position to execute it (no stack, MMU off). Fix this by using a notrace variant of save_and_disable_irqs. The code already uses the notrace variant of restore_irqs. Reviewed-by: Nicolas Pitre <nico@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
BugLink: http://bugs.launchpad.net/bugs/954576

commit 8e43a905dd574f54c5715d978318290ceafbe275 upstream.

Bootup with lockdep enabled has been broken on v7 since b46c0f74657d
("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR").

This is because v7_setup (which is called very early during boot) calls
v7_flush_dcache_all, and the save_and_disable_irqs added by that patch
ends up attempting to call into lockdep C code (trace_hardirqs_off())
when we are in no position to execute it (no stack, MMU off).

Fix this by using a notrace variant of save_and_disable_irqs.  The code
already uses the notrace variant of restore_irqs.

Reviewed-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
topdown mmap support 2012-01-23T23:36:44+00:00 Rob Herring rob.herring@calxeda.com 2012-01-13T10:58:00+00:00 e57ab2a5705ddba992c14d82d915a66757da4c8a Similar to other architectures, this adds topdown mmap support in user process address space allocation policy. This allows mmap sizes greater than 2GB. This support is largely copied from MIPS and the generic implementations. The address space randomization is moved into arch_pick_mmap_layout. Tested on V-Express with ubuntu and a mmap test from here: https://bugs.launchpad.net/bugs/861296 BugLink: http://bugs.launchpad.net/bugs/861296 (cherry picked from commit 7dbaa466780a754154531b44c2086f6618cee3a8) Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com> Acked-by: Seth Forshee <seth.forshee@canonical.com> Signed-off-by: Tim Gardner <tim.gardner@canonical.com> Acked-by: Stefan Bader <stefan.bader@canonical.com> Signed-off-by: Brad Figg <brad.figg@canonical.com> 
Similar to other architectures, this adds topdown mmap support in user
process address space allocation policy. This allows mmap sizes greater
than 2GB. This support is largely copied from MIPS and the generic
implementations.

The address space randomization is moved into arch_pick_mmap_layout.

Tested on V-Express with ubuntu and a mmap test from here:
https://bugs.launchpad.net/bugs/861296

BugLink: http://bugs.launchpad.net/bugs/861296

(cherry picked from commit 7dbaa466780a754154531b44c2086f6618cee3a8)

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>
Acked-by: Seth Forshee <seth.forshee@canonical.com>
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Signed-off-by: Brad Figg <brad.figg@canonical.com>