From 298476220d1f793ca0ac6c9e5dc817e1ad3e9851 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 27 Sep 2006 14:57:44 +0900 Subject: sh: Add control register barriers. Currently when making changes to control registers, we typically need some time for changes to take effect (8 nops, generally). However, for sh4a we simply need to do an icbi.. This is a simple patch for implementing a general purpose ctrl_barrier() which functions as a control register write barrier. There's some additional documentation in the patch itself, but it's pretty self explanatory. There were also some places where we were not doing the barrier, which didn't seem to have any adverse effects on legacy parts, but certainly did on sh4a. It's safer to have the barrier in place for legacy parts as well in these cases, though this does make flush_tlb_all() more expensive (by an order of 8 nops). We can ifdef around the flush_tlb_all() case for now if it's clear that all legacy parts won't have a problem with this. Signed-off-by: Paul Mundt --- include/asm-sh/mmu_context.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'include/asm-sh/mmu_context.h') diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h index 6760d064bd0..87678ba8d6b 100644 --- a/include/asm-sh/mmu_context.h +++ b/include/asm-sh/mmu_context.h @@ -174,9 +174,7 @@ static inline void enable_mmu(void) { /* Enable MMU */ ctrl_outl(MMU_CONTROL_INIT, MMUCR); - - /* The manual suggests doing some nops after turning on the MMU */ - __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop\n\t"); + ctrl_barrier(); if (mmu_context_cache == NO_CONTEXT) mmu_context_cache = MMU_CONTEXT_FIRST_VERSION; @@ -191,7 +189,8 @@ static inline void disable_mmu(void) cr = ctrl_inl(MMUCR); cr &= ~MMU_CONTROL_INIT; ctrl_outl(cr, MMUCR); - __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop\n\t"); + + ctrl_barrier(); } #else /* -- cgit v1.2.2