From 168f1212c098727f2509fe0f66bd30d7209a8159 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 11 Oct 2007 00:22:35 +0800 Subject: Blackfin arch: rewrite our reboot code in C rewrite our reboot code in C rather than assembly to be like other architectures and to allow board maintainers to define custom behavior Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_gpio.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/blackfin/kernel/bfin_gpio.c') diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 0182ce1fc4f..d9284d7dc9f 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -80,6 +80,7 @@ * GPIO_47 PH15 PF47 */ +#include #include #include #include @@ -888,3 +889,20 @@ void gpio_direction_output(unsigned short gpio) local_irq_restore(flags); } EXPORT_SYMBOL(gpio_direction_output); + +/* If we are booting from SPI and our board lacks a strong enough pull up, + * the core can reset and execute the bootrom faster than the resistor can + * pull the signal logically high. To work around this (common) error in + * board design, we explicitly set the pin back to GPIO mode, force /CS + * high, and wait for the electrons to do their thing. + * + * This function only makes sense to be called from reset code, but it + * lives here as we need to force all the GPIO states w/out going through + * BUG() checks and such. + */ +void bfin_gpio_reset_spi0_ssel1(void) +{ + port_setup(P_SPI0_SSEL1, GPIO_USAGE); + gpio_bankb[gpio_bank(P_SPI0_SSEL1)]->data_set = gpio_bit(P_SPI0_SSEL1); + udelay(1); +} -- cgit v1.2.2