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* Linux 2.6.32-rc6Linus Torvalds2009-11-03
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* Merge branch 'for-linus' of git://github.com/at91linux/linux-2.6-at91Linus Torvalds2009-11-03
|\ | | | | | | | | | | * 'for-linus' of git://github.com/at91linux/linux-2.6-at91: at91: at91sam9g45 family: identify several chip versions avr32: add two new at91 to cpu.h definition
| * at91: at91sam9g45 family: identify several chip versionsNicolas Ferre2009-11-03
| | | | | | | | | | | | | | | | | | | | | | cpu_is_xxx() macros are identifying generic at91sam9g45 chip. This patch adds the capacity to differentiate Engineering Samples and final lots through the inclusion of at91_cpu_fully_identify() and the related chip IDs with chip version field preserved. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
| * avr32: add two new at91 to cpu.h definitionNicolas Ferre2009-11-03
| | | | | | | | | | | | | | | | | | Somme common drivers will need those at91 cpu_is_xxx() definitions. As at91sam9g10 and at91sam9g45 are on the way to linus' tree, here is the patch that adds those chips to cpu.h in AVR32 architecture. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2009-11-03
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits) MIPS: O32: Fix ppoll MIPS: Oprofile: Rename cpu_type from godson2 to loongson2 MIPS: Alchemy: Fix hang with high-frequency edge interrupts MIPS: TXx9: Fix spi-baseclk value MIPS: bcm63xx: Set the correct BCM3302 CPU name MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store MIPS: Avoid potential hazard on Context register MIPS: Octeon: Use lockless interrupt controller operations when possible. MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache MIPS: SMTC: Avoid queing multiple reschedule IPIs MIPS: GCMP: Avoid accessing registers when they are not present MIPS: GIC: Random fixes and enhancements. MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands MIPS: SPRAM: Clean up support code a little MIPS: 1004K: Enable SPRAM support. MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4 MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT. MIPS: MTI: Fix accesses to device registers on MIPS boards ...
| * MIPS: O32: Fix ppollArnaud Patard2009-11-02
| | | | | | | | | | | | | | | | sys_ppoll syscall needs to use a compat handler on 64bit kernels with o32 user-space. Signed-off-by: Arnaud Patard <apatard@mandriva.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Oprofile: Rename cpu_type from godson2 to loongson2Wu Zhangjin2009-11-02
| | | | | | | | | | | | | | | | | | | | Unify the naming method between kernel and the user-space oprofile tool. Because loongson is used instead of godson in most of the places, we agreed to use loongson instead, which will simplify future maintenance. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: Fix hang with high-frequency edge interruptsManuel Lauss2009-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The handle_edge_irq() flowhandler disables edge int sources which occur too fast (i.e. another edge comes in before the irq handler function had a chance to finish). Currently, the mask_ack() callback does not ack the edges in hardware, leading to an endless loop in the flowhandler where it tries to shut up the irq source. When I rewrote the alchemy IRQ code I wrongly assumed the mask_ack() callback was only used by the level flowhandler, hence it omitted the (at the time pointless) edge acks. Turned out I was wrong; so here is a complete mask_ack implementation for Alchemy IC, which fixes the above mentioned problem. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: TXx9: Fix spi-baseclk valueAtsushi Nemoto2009-11-02
| | | | | | | | | | | | | | | | | | | | TXx9 SPI bit rate is calculated by: fBR = fSPI / 2 / (n + 1) (fSPI is SPI master clock freq, i.e. imbusclk freq.) So use imbus_clk / 2 as a spi-baseclk. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: bcm63xx: Set the correct BCM3302 CPU nameFlorian Fainelli2009-11-02
| | | | | | | | | | | | | | | | For consistency with other BCM63xx SoC set the CPU name to "Broadcom BCM6338" when actually running on that system. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_storeZhang Le2009-11-02
| | | | | | | | | | | | | | | | | | | | Loongson 2 does not have dcache aliases when is using 16k pages. and the And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does not matter here. Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Avoid potential hazard on Context registerRalf Baechle2009-11-02
| | | | | | | | | | | | | | | | | | | | set_saved_sp reads Context register. Avoid reading stale value from earlier incomplete write. Issue found and fixed for head.S by Chris Dearman <chris@mips.com>. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Use lockless interrupt controller operations when possible.David Daney2009-11-02
| | | | | | | | | | | | | | | | Some newer Octeon chips have registers that allow lockless operation of the interrupt controller. Take advantage of them. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinityDavid Daney2009-11-02
| | | | | | | | | | | | | | | | Since the locks are used from interrupt context we need the irqsave/irqrestore versions of the locking functions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Set S-cache linesize to 64-bytes for MTI's S-cacheRalf Baechle2009-11-02
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: SMTC: Avoid queing multiple reschedule IPIsJaidev Patwardhan2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: GCMP: Avoid accessing registers when they are not presentJaidev Patwardhan2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: GIC: Random fixes and enhancements.Chris Dearman2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_startChris Dearman2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman (chris@mips.com) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operandsNigel Stephens2009-11-02
| | | | | | | | | | | | | | This patch ensures that the sign bit is always updated for NaN operands. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: SPRAM: Clean up support code a littleChris Dearman2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: 1004K: Enable SPRAM support.Ralf Baechle2009-11-02
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4Ralf Baechle2009-11-02
| | | | | | | | | | | | Based on original patch by Chris Dearman <chris@mips.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.Ralf Baechle2009-11-02
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: MTI: Fix accesses to device registers on MIPS boardsChris Dearman2009-11-02
| | | | | | | | | | | | | | | | | | This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode) Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Fix machine check exception in kmap_coherent()Kevin Cernekee2009-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On an SMP system with cache aliases, the following sequence of events may happen: 1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a temporary mapping in the fixmap region 2) copy_page() starts on CPU0 3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page() 4) CPU0 takes the interrupt, interrupting copy_page() 5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again 6) The second invocation of kmap_coherent() on CPU0 tries to use the same fixmap virtual address that was being used by copy_user_highpage() 7) CPU0 throws a machine check exception for the TLB address conflict Fixed by creating an extra set of fixmap entries for use in interrupt handlers. This prevents fixmap VA conflicts between copy_user_highpage() running in user context, and local_r4k_flush_cache_page() invoked from an SMP IPI. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: MTX-1: Fix build if CONFIG_PCI is disabled.Ralf Baechle2009-11-02
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: AR7: register watchdog device only if enabled in hw configurationFlorian Fainelli2009-11-02
| | | | | | | | | | | | | | | | | | This patch checks if the watchdog enable bit is set in the DCL register meaning that the hardware watchdog actually works and if so, register the ar7_wdt platform_device. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: BCM63xx: Prepare for watchdog supportFlorian Fainelli2009-11-02
| | | | | | | | | | | | | | | | This patch prepares the board code to register a bcm63xx_wdt platform_device that we are going to use in a subsequent patch. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: BCM63xx: Make bcm63xx_uart_register an initfuncFlorian Fainelli2009-11-02
| | | | | | | | | | | | | | | | | | This patch removes the calls to bcm63xx_uart_register in board_bcm963xx.c and make bcm63xx_uart_register an initfunc. Allows us to remove bcm63xx_dev_uart.h which was there to make checkpatch.pl happy. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: AU1000: Fix build failure for db1x00 configured for Au1100 SoCFlorian Fainelli2009-11-02
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following warning, which becomes an error due to -Werror to be turned on: CC arch/mips/alchemy/common/gpiolib-au1000.o cc1: warnings being treated as errors arch/mips/alchemy/common/gpiolib-au1000.c: In function 'au1100_gpio2_to_irq': /home/florian/dev/kernel/linux-queue/arch/mips/include/asm/mach-au1x00/gpio-au1000.h:107: warning: control reaches end of non-void function Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: BCM63xx: Fix soft-reset lockup on BCM6345Florian Fainelli2009-11-02
| | | | | | | | | | | | | | | | | | | | This patch fixes a lockup on BCM6345 where setting the PLL soft reset bit will also lock the other blocks including UART. Instead of setting only the PLL soft reset bit in the software reset register, set this bit but do not touch the others. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: TXx9: Fix error handling / Fix for noenexisting gpio_remove.Ralf Roesch2009-11-02
| | | | | | | | | | | | | | Error was introduced by commit 0385d1f3d394c6814be0b165c153fc3fc254469a. Signed-off-by: Ralf Roesch <ralf.roesch@rw-gmbh.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Add IRQF_TIMER flag for timer interruptsWu Zhangjin2009-11-02
| | | | | | | | | | | | | | | | | | | | | | As the commit 3ee4c147 shows, we need to "Add IRQF_TIMER flag for timer interrupts", Atsushi Nemoto have reported that some other timer interrupts should be considered, Here it is. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: 64-bit: Fix o32 lookup_dcookie syscallWu Zhangjin2009-11-02
| | | | | | | | | | | | | | | | | | | | An o32 aplication passes a 64-bit value in a pair of registers; a 64-bit kernel expects a 64-bit argument in a single register. Signed-off-by: Chen Jie <chenj@lemote.com> Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: VPE: Remove stray unlock_kernel.Ralf Baechle2009-11-02
| | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Josip Rodin <joy@entuzijast.net>
| * MIPS: Add IRQF_TIMER flag for timer interruptsWu Zhangjin2009-11-02
| | | | | | | | | | | | | | | | | | | | Along the lines of d6c585a4342a2ff627a29f9aea77c5ed4cd76023, add IRQF_TIMER flag for all timer interrupts This ensures that timer interrupts won't be disabled on suspend and not threaded for PREEMPT_RT. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Loongson: Remove redundant local_irq_disable()Wu Zhangjin2009-11-02
| | | | | | | | | | | | | | | | That code is executed with irq disabled already, so, remove the redundant local_irq_disable() here. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: IP27: Fix buildRalf Baechle2009-11-02
| | | | | | | | | | | | Broken by 182a85f8a119c789610a9d464f4129ded9f3c107. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Cleanup CONFIG_DEBUG_STACK_USAGE version of alloc_thread_info.Ralf Baechle2009-11-02
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Fix compile error in arch/mips/cavium-octeon/smp.cDavid Daney2009-11-02
| | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Don't write ones to reserved entryhi bits.Ralf Baechle2009-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've silently been relying on the hardware chopping off excess, reserved ASID bits for no better reason that it saving an instruction. Because we already have: #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) in <asm/mmu_context.h>. We can use a cleanup to avoid writing non-zero bits into the reserved entryhi bits. This avoid triggering some debugging assertion in the Cavium simulator. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Extend COMMAND_LINE_SIZERalf Baechle2009-11-02
| | | | | | | | | | | | Some firmware may pass well over 256 bytes these days. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'pm-fixes' of ↵Linus Torvalds2009-11-03
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspend-2.6 * 'pm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspend-2.6: PM: Remove some debug messages producing too much noise PM: Fix warning on suspend errors PM / Hibernate: Add newline to load_image() fail path PM / Hibernate: Fix error handling in save_image() PM / Hibernate: Fix blkdev refleaks PM / yenta: Split resume into early and late parts (rev. 4)
| * | PM: Remove some debug messages producing too much noisePavel Machek2009-11-03
| | | | | | | | | | | | | | | | | | | | | pm_runtime_idle() is somewhat noisy. Remove debug prints. Signed-off-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
| * | PM: Fix warning on suspend errorsRomit Dasgupta2009-11-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the point where we need to complete the power transition when device suspend fails, so that we don't print warnings about devices added to the device hierarchy after a failing suspend. [rjw: Modified changelog.] Signed-off-by: Romit Dasgupta <romit@ti.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
| * | PM / Hibernate: Add newline to load_image() fail pathJiri Slaby2009-11-03
| | | | | | | | | | | | | | | | | | | | | | | | Finish a line by \n when load_image fails in the middle of loading. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
| * | PM / Hibernate: Fix error handling in save_image()Jiri Slaby2009-11-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are too many retval variables in save_image(). Thus error return value from snapshot_read_next() may be ignored and only part of the snapshot (successfully) written. Remove 'error' variable, invert the condition in the do-while loop and convert the loop to use only 'ret' variable. Switch the rest of the function to consider only 'ret'. Also make sure we end printed line by \n if an error occurs. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
| * | PM / Hibernate: Fix blkdev refleaksJiri Slaby2009-11-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While cruising through the swsusp code I found few blkdev reference leaks of resume_bdev. swsusp_read: remove blkdev_put altogether. Some fail paths do not do that. swsusp_check: make sure we always put a reference on fail paths software_resume: all fail paths between swsusp_check and swsusp_read omit swsusp_close. Add it in those cases. And since swsusp_read doesn't drop the reference anymore, do it here unconditionally. [rjw: Fixed a small coding style issue.] Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
| * | PM / yenta: Split resume into early and late parts (rev. 4)Rafael J. Wysocki2009-11-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0c570cdeb8fdfcb354a3e9cd81bfc6a09c19de0c (PM / yenta: Fix cardbus suspend/resume regression) caused resume to fail on systems with two CardBus bridges. While the exact nature of the failure is not known at the moment, it can be worked around by splitting the yenta resume into an early part, executed during the early phase of resume, that will only resume the socket and power it up if there was a card in it during suspend, and a late part, executed during "regular" resume, that will carry out all of the remaining yenta resume operations. Fixes http://bugzilla.kernel.org/show_bug.cgi?id=14334, which is a listed regression from 2.6.31. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Dominik Brodowski <linux@dominikbrodowski.net> Reported-by: Stephen J. Gowdy <gowdy@cern.ch> Tested-by: Jose Marino <braket@hotmail.com>
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