| Commit message (Collapse) | Author | Age |
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Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Conflicts:
include/litmus/color.h
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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This is not tested and probably won't work.
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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The ARM arch_{read,write}_trylock implementations include unused
backwards branch labels, since we don't retry the locking operation
if the exclusive store fails.
This patch removes the labels.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Ticket spinlocks ensure locking fairness by introducing a FIFO-like
nature to the granting of lock acquisitions and also reducing the
thundering herd effect when spinning on a lock by allowing the cacheline
to remain in a shared state amongst the waiting CPUs. This is especially
important on systems where memory-access times are not necessarily
uniform when accessing the lock structure (for example, on a
multi-cluster platform where the lock is allocated into L1 when a CPU
releases it).
This patch implements the ticket spinlock algorithm for ARM, replacing
the simpler implementation for ARMv6+ processors.
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Try and fix the cycle counter on ARMv7 CPUs (unsuccessful).
Use the multi-core timer on the ODROID-X to count cycles.
Add lockdown register access to proc.
Add proc options to disable prefetching for L1/L2 cache.
Add test to lockdown.c to print the time to read in various WSSs.
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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This commit is dirty and will be cleaned up when blocking states are tested.
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Note: Highmem pages will need to be vmapped in the kernel, or we need to
not use HIGHMEM pages.
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Conflicts:
arch/arm/mach-omap2/board-omap4panda.c
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Conflicts:
arch/arm/mm/cache-l2x0.c
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Currently is always preempting. This needs to be configurable via proc.
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wip-mc
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Commit e6f51fb826ce98d436f445aae4eb9e9dba1f30e8 added some floating
point support for LITMUS^RT, but it used 64-bit division that ARM does
not support. Therefore, use the division functions from math64.h.
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Fighting unfixed U-Boots and other beasts that may the cache in
a locked-down state when starting the kernel, we make sure to
disable all cache lock-down when initializing the l2x0 so we
are in a known state.
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Adrian Bunk <adrian.bunk@movial.com>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reported-by: Jan Rinze <janrinze@gmail.com>
Tested-by: Robert Marklund <robert.marklund@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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Commit 774c096bf9e49 (ARM: v6/v7 cache: allow cache calls to be
optimized) got dropped when the merge conflicts for moving the contents
of the files in commit 753790e713d (ARM: move cache/processor/fault
glue to separate include files) was fixed up in merge bd1274dc005
(Merge branch 'v6v7' into devel).
This puts the change back.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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This commit is broken as it allows locking tasks to early release.
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While working on an ODROID-X (Samsung Exynos4412 ARM Cortex-A9), I
experienced non-determinism when reading and writing values to the
LITMUS^RT control page. Writes to the control page from user- (kernel-)
space where not always reflected in kernel- (user-) space.
Neither restricting the task to run on a single CPU nor inserting
general memory barriers (with mb()) fixed the problem. Mapping the
control page as uncachable in both kernel and user space did fix the
problem, which is what this patch does.
Also, since vunmap() cannot be called from an interrupt context, I had
to add a workqueue that unmaps and frees the control page when it is no
longer needed. (On my system, exit_litmus() was called from interrupt
context while the kernel reaped the task_struct.)
Conflicts:
include/litmus/rt_param.h
litmus/litmus.c
Does not make the color control page uncachable yet!
Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>
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