diff options
Diffstat (limited to 'include/asm-powerpc/reg.h')
-rw-r--r-- | include/asm-powerpc/reg.h | 69 |
1 files changed, 44 insertions, 25 deletions
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index bd467bf5cf5..cf73475a0c6 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h | |||
@@ -93,8 +93,8 @@ | |||
93 | #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ | 93 | #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ |
94 | 94 | ||
95 | #ifdef CONFIG_PPC64 | 95 | #ifdef CONFIG_PPC64 |
96 | #define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF | 96 | #define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV |
97 | #define MSR_KERNEL MSR_ | MSR_SF | MSR_HV | 97 | #define MSR_KERNEL MSR_ | MSR_SF |
98 | 98 | ||
99 | #define MSR_USER32 MSR_ | MSR_PR | MSR_EE | 99 | #define MSR_USER32 MSR_ | MSR_PR | MSR_EE |
100 | #define MSR_USER64 MSR_USER32 | MSR_SF | 100 | #define MSR_USER64 MSR_USER32 | MSR_SF |
@@ -153,7 +153,7 @@ | |||
153 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ | 153 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ |
154 | #define DABR_TRANSLATION (1UL << 2) | 154 | #define DABR_TRANSLATION (1UL << 2) |
155 | #define SPRN_DAR 0x013 /* Data Address Register */ | 155 | #define SPRN_DAR 0x013 /* Data Address Register */ |
156 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ | 156 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ |
157 | #define DSISR_NOHPTE 0x40000000 /* no translation found */ | 157 | #define DSISR_NOHPTE 0x40000000 /* no translation found */ |
158 | #define DSISR_PROTFAULT 0x08000000 /* protection fault */ | 158 | #define DSISR_PROTFAULT 0x08000000 /* protection fault */ |
159 | #define DSISR_ISSTORE 0x02000000 /* access was a store */ | 159 | #define DSISR_ISSTORE 0x02000000 /* access was a store */ |
@@ -258,16 +258,16 @@ | |||
258 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ | 258 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ |
259 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ | 259 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ |
260 | #define SPRN_HID5 0x3F6 /* 970 HID5 */ | 260 | #define SPRN_HID5 0x3F6 /* 970 HID5 */ |
261 | #define SPRN_HID6 0x3F9 /* BE HID 6 */ | 261 | #define SPRN_HID6 0x3F9 /* BE HID 6 */ |
262 | #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ | 262 | #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ |
263 | #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ | 263 | #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ |
264 | #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ | 264 | #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ |
265 | #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ | 265 | #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ |
266 | #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ | 266 | #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ |
267 | #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ | 267 | #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ |
268 | #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ | 268 | #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ |
269 | #define SPRN_TSC 0x3FD /* Thread switch control on others */ | 269 | #define SPRN_TSC 0x3FD /* Thread switch control on others */ |
270 | #define SPRN_TST 0x3FC /* Thread switch timeout on others */ | 270 | #define SPRN_TST 0x3FC /* Thread switch timeout on others */ |
271 | #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) | 271 | #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) |
272 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ | 272 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ |
273 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ | 273 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ |
@@ -362,7 +362,7 @@ | |||
362 | #endif | 362 | #endif |
363 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ | 363 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ |
364 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ | 364 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ |
365 | #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ | 365 | #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ |
366 | #define SPRN_PVR 0x11F /* Processor Version Register */ | 366 | #define SPRN_PVR 0x11F /* Processor Version Register */ |
367 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ | 367 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ |
368 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ | 368 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ |
@@ -386,6 +386,8 @@ | |||
386 | #define SRR1_WAKEMT 0x00280000 /* mtctrl */ | 386 | #define SRR1_WAKEMT 0x00280000 /* mtctrl */ |
387 | #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ | 387 | #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ |
388 | #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ | 388 | #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ |
389 | #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ | ||
390 | #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ | ||
389 | 391 | ||
390 | #ifndef SPRN_SVR | 392 | #ifndef SPRN_SVR |
391 | #define SPRN_SVR 0x11E /* System Version Register */ | 393 | #define SPRN_SVR 0x11E /* System Version Register */ |
@@ -443,6 +445,10 @@ | |||
443 | #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ | 445 | #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ |
444 | #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ | 446 | #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ |
445 | #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ | 447 | #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ |
448 | #define POWER6_MMCRA_SIHV 0x0000040000000000ULL | ||
449 | #define POWER6_MMCRA_SIPR 0x0000020000000000ULL | ||
450 | #define POWER6_MMCRA_THRM 0x00000020UL | ||
451 | #define POWER6_MMCRA_OTHER 0x0000000EUL | ||
446 | #define SPRN_PMC1 787 | 452 | #define SPRN_PMC1 787 |
447 | #define SPRN_PMC2 788 | 453 | #define SPRN_PMC2 788 |
448 | #define SPRN_PMC3 789 | 454 | #define SPRN_PMC3 789 |
@@ -495,6 +501,19 @@ | |||
495 | #define MMCR0_PMC2_LOADMISSTIME 0x5 | 501 | #define MMCR0_PMC2_LOADMISSTIME 0x5 |
496 | #endif | 502 | #endif |
497 | 503 | ||
504 | /* | ||
505 | * An mtfsf instruction with the L bit set. On CPUs that support this a | ||
506 | * full 64bits of FPSCR is restored and on other CPUs it is ignored. | ||
507 | * | ||
508 | * Until binutils gets the new form of mtfsf, hardwire the instruction. | ||
509 | */ | ||
510 | #ifdef CONFIG_PPC64 | ||
511 | #define MTFSF_L(REG) \ | ||
512 | .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) | ||
513 | #else | ||
514 | #define MTFSF_L(REG) mtfsf 0xff, (REG) | ||
515 | #endif | ||
516 | |||
498 | /* Processor Version Register (PVR) field extraction */ | 517 | /* Processor Version Register (PVR) field extraction */ |
499 | 518 | ||
500 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ | 519 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ |
@@ -559,20 +578,20 @@ | |||
559 | 578 | ||
560 | /* 64-bit processors */ | 579 | /* 64-bit processors */ |
561 | /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */ | 580 | /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */ |
562 | #define PV_NORTHSTAR 0x0033 | 581 | #define PV_NORTHSTAR 0x0033 |
563 | #define PV_PULSAR 0x0034 | 582 | #define PV_PULSAR 0x0034 |
564 | #define PV_POWER4 0x0035 | 583 | #define PV_POWER4 0x0035 |
565 | #define PV_ICESTAR 0x0036 | 584 | #define PV_ICESTAR 0x0036 |
566 | #define PV_SSTAR 0x0037 | 585 | #define PV_SSTAR 0x0037 |
567 | #define PV_POWER4p 0x0038 | 586 | #define PV_POWER4p 0x0038 |
568 | #define PV_970 0x0039 | 587 | #define PV_970 0x0039 |
569 | #define PV_POWER5 0x003A | 588 | #define PV_POWER5 0x003A |
570 | #define PV_POWER5p 0x003B | 589 | #define PV_POWER5p 0x003B |
571 | #define PV_970FX 0x003C | 590 | #define PV_970FX 0x003C |
572 | #define PV_630 0x0040 | 591 | #define PV_630 0x0040 |
573 | #define PV_630p 0x0041 | 592 | #define PV_630p 0x0041 |
574 | #define PV_970MP 0x0044 | 593 | #define PV_970MP 0x0044 |
575 | #define PV_BE 0x0070 | 594 | #define PV_BE 0x0070 |
576 | 595 | ||
577 | /* | 596 | /* |
578 | * Number of entries in the SLB. If this ever changes we should handle | 597 | * Number of entries in the SLB. If this ever changes we should handle |