diff options
Diffstat (limited to 'include/asm-powerpc/qe.h')
-rw-r--r-- | include/asm-powerpc/qe.h | 82 |
1 files changed, 52 insertions, 30 deletions
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index c3be6e2e149..edee15d269e 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h | |||
@@ -16,6 +16,8 @@ | |||
16 | #define _ASM_POWERPC_QE_H | 16 | #define _ASM_POWERPC_QE_H |
17 | #ifdef __KERNEL__ | 17 | #ifdef __KERNEL__ |
18 | 18 | ||
19 | #include <linux/spinlock.h> | ||
20 | #include <asm/cpm.h> | ||
19 | #include <asm/immap_qe.h> | 21 | #include <asm/immap_qe.h> |
20 | 22 | ||
21 | #define QE_NUM_OF_SNUM 28 | 23 | #define QE_NUM_OF_SNUM 28 |
@@ -74,10 +76,38 @@ enum qe_clock { | |||
74 | QE_CLK_DUMMY | 76 | QE_CLK_DUMMY |
75 | }; | 77 | }; |
76 | 78 | ||
79 | static inline bool qe_clock_is_brg(enum qe_clock clk) | ||
80 | { | ||
81 | return clk >= QE_BRG1 && clk <= QE_BRG16; | ||
82 | } | ||
83 | |||
84 | extern spinlock_t cmxgcr_lock; | ||
85 | |||
77 | /* Export QE common operations */ | 86 | /* Export QE common operations */ |
78 | extern void qe_reset(void); | 87 | extern void __init qe_reset(void); |
88 | |||
89 | /* QE PIO */ | ||
90 | #define QE_PIO_PINS 32 | ||
91 | |||
92 | struct qe_pio_regs { | ||
93 | __be32 cpodr; /* Open drain register */ | ||
94 | __be32 cpdata; /* Data register */ | ||
95 | __be32 cpdir1; /* Direction register */ | ||
96 | __be32 cpdir2; /* Direction register */ | ||
97 | __be32 cppar1; /* Pin assignment register */ | ||
98 | __be32 cppar2; /* Pin assignment register */ | ||
99 | #ifdef CONFIG_PPC_85xx | ||
100 | u8 pad[8]; | ||
101 | #endif | ||
102 | }; | ||
103 | |||
79 | extern int par_io_init(struct device_node *np); | 104 | extern int par_io_init(struct device_node *np); |
80 | extern int par_io_of_config(struct device_node *np); | 105 | extern int par_io_of_config(struct device_node *np); |
106 | #define QE_PIO_DIR_IN 2 | ||
107 | #define QE_PIO_DIR_OUT 1 | ||
108 | extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, | ||
109 | int dir, int open_drain, int assignment, | ||
110 | int has_irq); | ||
81 | extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, | 111 | extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, |
82 | int assignment, int has_irq); | 112 | int assignment, int has_irq); |
83 | extern int par_io_data_set(u8 port, u8 pin, u8 val); | 113 | extern int par_io_data_set(u8 port, u8 pin, u8 val); |
@@ -89,20 +119,13 @@ unsigned int qe_get_brg_clk(void); | |||
89 | int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); | 119 | int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); |
90 | int qe_get_snum(void); | 120 | int qe_get_snum(void); |
91 | void qe_put_snum(u8 snum); | 121 | void qe_put_snum(u8 snum); |
92 | unsigned long qe_muram_alloc(int size, int align); | 122 | /* we actually use cpm_muram implementation, define this for convenience */ |
93 | int qe_muram_free(unsigned long offset); | 123 | #define qe_muram_init cpm_muram_init |
94 | unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); | 124 | #define qe_muram_alloc cpm_muram_alloc |
95 | void qe_muram_dump(void); | 125 | #define qe_muram_alloc_fixed cpm_muram_alloc_fixed |
96 | 126 | #define qe_muram_free cpm_muram_free | |
97 | static inline void __iomem *qe_muram_addr(unsigned long offset) | 127 | #define qe_muram_addr cpm_muram_addr |
98 | { | 128 | #define qe_muram_offset cpm_muram_offset |
99 | return (void __iomem *)&qe_immr->muram[offset]; | ||
100 | } | ||
101 | |||
102 | static inline unsigned long qe_muram_offset(void __iomem *addr) | ||
103 | { | ||
104 | return addr - (void __iomem *)qe_immr->muram; | ||
105 | } | ||
106 | 129 | ||
107 | /* Structure that defines QE firmware binary files. | 130 | /* Structure that defines QE firmware binary files. |
108 | * | 131 | * |
@@ -156,6 +179,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware); | |||
156 | /* Obtain information on the uploaded firmware */ | 179 | /* Obtain information on the uploaded firmware */ |
157 | struct qe_firmware_info *qe_get_firmware_info(void); | 180 | struct qe_firmware_info *qe_get_firmware_info(void); |
158 | 181 | ||
182 | /* QE USB */ | ||
183 | int qe_usb_clock_set(enum qe_clock clk, int rate); | ||
184 | |||
159 | /* Buffer descriptors */ | 185 | /* Buffer descriptors */ |
160 | struct qe_bd { | 186 | struct qe_bd { |
161 | __be16 status; | 187 | __be16 status; |
@@ -166,20 +192,6 @@ struct qe_bd { | |||
166 | #define BD_STATUS_MASK 0xffff0000 | 192 | #define BD_STATUS_MASK 0xffff0000 |
167 | #define BD_LENGTH_MASK 0x0000ffff | 193 | #define BD_LENGTH_MASK 0x0000ffff |
168 | 194 | ||
169 | #define BD_SC_EMPTY 0x8000 /* Receive is empty */ | ||
170 | #define BD_SC_READY 0x8000 /* Transmit is ready */ | ||
171 | #define BD_SC_WRAP 0x2000 /* Last buffer descriptor */ | ||
172 | #define BD_SC_INTRPT 0x1000 /* Interrupt on change */ | ||
173 | #define BD_SC_LAST 0x0800 /* Last buffer in frame */ | ||
174 | #define BD_SC_CM 0x0200 /* Continous mode */ | ||
175 | #define BD_SC_ID 0x0100 /* Rec'd too many idles */ | ||
176 | #define BD_SC_P 0x0100 /* xmt preamble */ | ||
177 | #define BD_SC_BR 0x0020 /* Break received */ | ||
178 | #define BD_SC_FR 0x0010 /* Framing error */ | ||
179 | #define BD_SC_PR 0x0008 /* Parity error */ | ||
180 | #define BD_SC_OV 0x0002 /* Overrun */ | ||
181 | #define BD_SC_CD 0x0001 /* ?? */ | ||
182 | |||
183 | /* Alignment */ | 195 | /* Alignment */ |
184 | #define QE_INTR_TABLE_ALIGN 16 /* ??? */ | 196 | #define QE_INTR_TABLE_ALIGN 16 /* ??? */ |
185 | #define QE_ALIGNMENT_OF_BD 8 | 197 | #define QE_ALIGNMENT_OF_BD 8 |
@@ -254,6 +266,16 @@ enum comm_dir { | |||
254 | #define QE_CMXGCR_MII_ENET_MNG 0x00007000 | 266 | #define QE_CMXGCR_MII_ENET_MNG 0x00007000 |
255 | #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 | 267 | #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 |
256 | #define QE_CMXGCR_USBCS 0x0000000f | 268 | #define QE_CMXGCR_USBCS 0x0000000f |
269 | #define QE_CMXGCR_USBCS_CLK3 0x1 | ||
270 | #define QE_CMXGCR_USBCS_CLK5 0x2 | ||
271 | #define QE_CMXGCR_USBCS_CLK7 0x3 | ||
272 | #define QE_CMXGCR_USBCS_CLK9 0x4 | ||
273 | #define QE_CMXGCR_USBCS_CLK13 0x5 | ||
274 | #define QE_CMXGCR_USBCS_CLK17 0x6 | ||
275 | #define QE_CMXGCR_USBCS_CLK19 0x7 | ||
276 | #define QE_CMXGCR_USBCS_CLK21 0x8 | ||
277 | #define QE_CMXGCR_USBCS_BRG9 0x9 | ||
278 | #define QE_CMXGCR_USBCS_BRG10 0xa | ||
257 | 279 | ||
258 | /* QE CECR Commands. | 280 | /* QE CECR Commands. |
259 | */ | 281 | */ |
@@ -283,7 +305,7 @@ enum comm_dir { | |||
283 | #define QE_HPAC_START_TX 0x0000060b | 305 | #define QE_HPAC_START_TX 0x0000060b |
284 | #define QE_HPAC_START_RX 0x0000070b | 306 | #define QE_HPAC_START_RX 0x0000070b |
285 | #define QE_USB_STOP_TX 0x0000000a | 307 | #define QE_USB_STOP_TX 0x0000000a |
286 | #define QE_USB_RESTART_TX 0x0000000b | 308 | #define QE_USB_RESTART_TX 0x0000000c |
287 | #define QE_QMC_STOP_TX 0x0000000c | 309 | #define QE_QMC_STOP_TX 0x0000000c |
288 | #define QE_QMC_STOP_RX 0x0000000d | 310 | #define QE_QMC_STOP_RX 0x0000000d |
289 | #define QE_SS7_SU_FIL_RESET 0x0000000e | 311 | #define QE_SS7_SU_FIL_RESET 0x0000000e |