diff options
Diffstat (limited to 'include/asm-powerpc/cputable.h')
-rw-r--r-- | include/asm-powerpc/cputable.h | 132 |
1 files changed, 59 insertions, 73 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 9fcf0162d85..1ba3c998361 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
@@ -24,6 +24,9 @@ | |||
24 | #define PPC_FEATURE_ICACHE_SNOOP 0x00002000 | 24 | #define PPC_FEATURE_ICACHE_SNOOP 0x00002000 |
25 | #define PPC_FEATURE_ARCH_2_05 0x00001000 | 25 | #define PPC_FEATURE_ARCH_2_05 0x00001000 |
26 | 26 | ||
27 | #define PPC_FEATURE_TRUE_LE 0x00000002 | ||
28 | #define PPC_FEATURE_PPC_LE 0x00000001 | ||
29 | |||
27 | #ifdef __KERNEL__ | 30 | #ifdef __KERNEL__ |
28 | #ifndef __ASSEMBLY__ | 31 | #ifndef __ASSEMBLY__ |
29 | 32 | ||
@@ -69,6 +72,13 @@ struct cpu_spec { | |||
69 | /* Processor specific oprofile operations */ | 72 | /* Processor specific oprofile operations */ |
70 | enum powerpc_oprofile_type oprofile_type; | 73 | enum powerpc_oprofile_type oprofile_type; |
71 | 74 | ||
75 | /* Bit locations inside the mmcra change */ | ||
76 | unsigned long oprofile_mmcra_sihv; | ||
77 | unsigned long oprofile_mmcra_sipr; | ||
78 | |||
79 | /* Bits to clear during an oprofile exception */ | ||
80 | unsigned long oprofile_mmcra_clear; | ||
81 | |||
72 | /* Name of processor class, for the ELF AT_PLATFORM entry */ | 82 | /* Name of processor class, for the ELF AT_PLATFORM entry */ |
73 | char *platform; | 83 | char *platform; |
74 | }; | 84 | }; |
@@ -104,41 +114,33 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
104 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | 114 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) |
105 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) | 115 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) |
106 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) | 116 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) |
117 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) | ||
118 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) | ||
107 | 119 | ||
120 | /* | ||
121 | * Add the 64-bit processor unique features in the top half of the word; | ||
122 | * on 32-bit, make the names available but defined to be 0. | ||
123 | */ | ||
108 | #ifdef __powerpc64__ | 124 | #ifdef __powerpc64__ |
109 | /* Add the 64b processor unique features in the top half of the word */ | 125 | #define LONG_ASM_CONST(x) ASM_CONST(x) |
110 | #define CPU_FTR_SLB ASM_CONST(0x0000000100000000) | ||
111 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000) | ||
112 | #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000) | ||
113 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000) | ||
114 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) | ||
115 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) | ||
116 | #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000) | ||
117 | #define CPU_FTR_SMT ASM_CONST(0x0000010000000000) | ||
118 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) | ||
119 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) | ||
120 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) | ||
121 | #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000) | ||
122 | #define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000) | ||
123 | #define CPU_FTR_PURR ASM_CONST(0x0000400000000000) | ||
124 | #else | 126 | #else |
125 | /* ensure on 32b processors the flags are available for compiling but | 127 | #define LONG_ASM_CONST(x) 0 |
126 | * don't do anything */ | ||
127 | #define CPU_FTR_SLB ASM_CONST(0x0) | ||
128 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0) | ||
129 | #define CPU_FTR_TLBIEL ASM_CONST(0x0) | ||
130 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0) | ||
131 | #define CPU_FTR_IABR ASM_CONST(0x0) | ||
132 | #define CPU_FTR_MMCRA ASM_CONST(0x0) | ||
133 | #define CPU_FTR_CTRL ASM_CONST(0x0) | ||
134 | #define CPU_FTR_SMT ASM_CONST(0x0) | ||
135 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0) | ||
136 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0) | ||
137 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0) | ||
138 | #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0) | ||
139 | #define CPU_FTR_PURR ASM_CONST(0x0) | ||
140 | #endif | 128 | #endif |
141 | 129 | ||
130 | #define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000) | ||
131 | #define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000) | ||
132 | #define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000) | ||
133 | #define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000) | ||
134 | #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000) | ||
135 | #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) | ||
136 | #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) | ||
137 | #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) | ||
138 | #define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000) | ||
139 | #define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000) | ||
140 | #define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000) | ||
141 | #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) | ||
142 | #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) | ||
143 | |||
142 | #ifndef __ASSEMBLY__ | 144 | #ifndef __ASSEMBLY__ |
143 | 145 | ||
144 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ | 146 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ |
@@ -192,92 +194,95 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
192 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) | 194 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) |
193 | #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 195 | #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
194 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | 196 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
195 | CPU_FTR_MAYBE_CAN_NAP) | 197 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
196 | #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 198 | #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
197 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE) | 199 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \ |
200 | CPU_FTR_PPC_LE) | ||
198 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 201 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
199 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 202 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
200 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) | 203 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
201 | #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 204 | #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
202 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 205 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
203 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) | 206 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
207 | CPU_FTR_PPC_LE) | ||
204 | #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 208 | #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
205 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 209 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
206 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) | 210 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
211 | CPU_FTR_PPC_LE) | ||
207 | #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 212 | #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
208 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 213 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
209 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 214 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
210 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) | 215 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) |
211 | #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 216 | #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
212 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 217 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
213 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 218 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
214 | CPU_FTR_NO_DPM) | 219 | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) |
215 | #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 220 | #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
216 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 221 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
217 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 222 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
218 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS) | 223 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
219 | #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | 224 | #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
220 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \ | 225 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \ |
221 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 226 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
222 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS) | 227 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
223 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 228 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
224 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 229 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
225 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 230 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ |
226 | CPU_FTR_MAYBE_CAN_NAP) | 231 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
227 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 232 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
228 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 233 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
229 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 234 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ |
230 | CPU_FTR_MAYBE_CAN_NAP) | 235 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
231 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 236 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
232 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 237 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
233 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 238 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
234 | CPU_FTR_NEED_COHERENT) | 239 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
235 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 240 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
236 | CPU_FTR_USE_TB | \ | 241 | CPU_FTR_USE_TB | \ |
237 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 242 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
238 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 243 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
239 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 244 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
240 | CPU_FTR_NEED_COHERENT) | 245 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
241 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 246 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
242 | CPU_FTR_USE_TB | \ | 247 | CPU_FTR_USE_TB | \ |
243 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 248 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
244 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 249 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
245 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT) | 250 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
246 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 251 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
247 | CPU_FTR_USE_TB | \ | 252 | CPU_FTR_USE_TB | \ |
248 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ | 253 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
249 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ | 254 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ |
250 | CPU_FTR_NEED_COHERENT) | 255 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
251 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 256 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
252 | CPU_FTR_USE_TB | \ | 257 | CPU_FTR_USE_TB | \ |
253 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 258 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
254 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 259 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
255 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 260 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
256 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS) | 261 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
257 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 262 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
258 | CPU_FTR_USE_TB | \ | 263 | CPU_FTR_USE_TB | \ |
259 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 264 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
260 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 265 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
261 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 266 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
262 | CPU_FTR_NEED_COHERENT) | 267 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
263 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 268 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
264 | CPU_FTR_USE_TB | \ | 269 | CPU_FTR_USE_TB | \ |
265 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 270 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
266 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 271 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
267 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 272 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
268 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC) | 273 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) |
269 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 274 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
270 | CPU_FTR_USE_TB | \ | 275 | CPU_FTR_USE_TB | \ |
271 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 276 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
272 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 277 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
273 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 278 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
274 | CPU_FTR_NEED_COHERENT) | 279 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
275 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 280 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
276 | CPU_FTR_USE_TB | \ | 281 | CPU_FTR_USE_TB | \ |
277 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 282 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
278 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 283 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
279 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 284 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
280 | CPU_FTR_NEED_COHERENT) | 285 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
281 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 286 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
282 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) | 287 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) |
283 | #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | 288 | #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
@@ -287,13 +292,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
287 | CPU_FTR_COMMON) | 292 | CPU_FTR_COMMON) |
288 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 293 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
289 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) | 294 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) |
290 | #define CPU_FTRS_POWER3_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | ||
291 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) | ||
292 | #define CPU_FTRS_POWER4_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | ||
293 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN) | ||
294 | #define CPU_FTRS_970_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | ||
295 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | \ | ||
296 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN) | ||
297 | #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) | 295 | #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) |
298 | #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 296 | #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
299 | CPU_FTR_NODSISRALIGN) | 297 | CPU_FTR_NODSISRALIGN) |
@@ -307,7 +305,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
307 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) | 305 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) |
308 | #ifdef __powerpc64__ | 306 | #ifdef __powerpc64__ |
309 | #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 307 | #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
310 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR) | 308 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) |
311 | #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 309 | #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
312 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ | 310 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ |
313 | CPU_FTR_MMCRA | CPU_FTR_CTRL) | 311 | CPU_FTR_MMCRA | CPU_FTR_CTRL) |
@@ -320,16 +318,16 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
320 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 318 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
321 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 319 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
322 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 320 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
323 | CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR) | 321 | CPU_FTR_PURR) |
324 | #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 322 | #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
325 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 323 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
326 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 324 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
327 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 325 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
328 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE) | 326 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE) |
329 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 327 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
330 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 328 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
331 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 329 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
332 | CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO) | 330 | CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE) |
333 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 331 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
334 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) | 332 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) |
335 | #endif | 333 | #endif |
@@ -354,12 +352,6 @@ enum { | |||
354 | #else | 352 | #else |
355 | CPU_FTRS_GENERIC_32 | | 353 | CPU_FTRS_GENERIC_32 | |
356 | #endif | 354 | #endif |
357 | #ifdef CONFIG_PPC64BRIDGE | ||
358 | CPU_FTRS_POWER3_32 | | ||
359 | #endif | ||
360 | #ifdef CONFIG_POWER4 | ||
361 | CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 | | ||
362 | #endif | ||
363 | #ifdef CONFIG_8xx | 355 | #ifdef CONFIG_8xx |
364 | CPU_FTRS_8XX | | 356 | CPU_FTRS_8XX | |
365 | #endif | 357 | #endif |
@@ -399,12 +391,6 @@ enum { | |||
399 | #else | 391 | #else |
400 | CPU_FTRS_GENERIC_32 & | 392 | CPU_FTRS_GENERIC_32 & |
401 | #endif | 393 | #endif |
402 | #ifdef CONFIG_PPC64BRIDGE | ||
403 | CPU_FTRS_POWER3_32 & | ||
404 | #endif | ||
405 | #ifdef CONFIG_POWER4 | ||
406 | CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 & | ||
407 | #endif | ||
408 | #ifdef CONFIG_8xx | 394 | #ifdef CONFIG_8xx |
409 | CPU_FTRS_8XX & | 395 | CPU_FTRS_8XX & |
410 | #endif | 396 | #endif |