diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/wireless/ath5k/ath5k.h | 16 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/base.c | 74 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/debug.c | 19 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/debug.h | 6 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/hw.c | 141 |
5 files changed, 126 insertions, 130 deletions
diff --git a/drivers/net/wireless/ath5k/ath5k.h b/drivers/net/wireless/ath5k/ath5k.h index 2af7982f6f0..b21830771ea 100644 --- a/drivers/net/wireless/ath5k/ath5k.h +++ b/drivers/net/wireless/ath5k/ath5k.h | |||
@@ -505,6 +505,7 @@ struct ath5k_beacon_state { | |||
505 | 505 | ||
506 | /* | 506 | /* |
507 | * Atheros hardware descriptor | 507 | * Atheros hardware descriptor |
508 | * This is read and written to by the hardware | ||
508 | */ | 509 | */ |
509 | struct ath5k_desc { | 510 | struct ath5k_desc { |
510 | u32 ds_link; /* physical address of the next descriptor */ | 511 | u32 ds_link; /* physical address of the next descriptor */ |
@@ -515,15 +516,6 @@ struct ath5k_desc { | |||
515 | struct ath5k_hw_5212_tx_desc ds_tx5212; | 516 | struct ath5k_hw_5212_tx_desc ds_tx5212; |
516 | struct ath5k_hw_all_rx_desc ds_rx; | 517 | struct ath5k_hw_all_rx_desc ds_rx; |
517 | } ud; | 518 | } ud; |
518 | |||
519 | union { | ||
520 | struct ath5k_rx_status rx; | ||
521 | struct ath5k_tx_status tx; | ||
522 | } ds_us; | ||
523 | |||
524 | #define ds_rxstat ds_us.rx | ||
525 | #define ds_txstat ds_us.tx | ||
526 | |||
527 | } __packed; | 519 | } __packed; |
528 | 520 | ||
529 | #define AR5K_RXDESC_INTREQ 0x0020 | 521 | #define AR5K_RXDESC_INTREQ 0x0020 |
@@ -1043,8 +1035,10 @@ struct ath5k_hw { | |||
1043 | int (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *, | 1035 | int (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *, |
1044 | unsigned int, unsigned int, unsigned int, unsigned int, | 1036 | unsigned int, unsigned int, unsigned int, unsigned int, |
1045 | unsigned int, unsigned int); | 1037 | unsigned int, unsigned int); |
1046 | int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *); | 1038 | int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, |
1047 | int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *); | 1039 | struct ath5k_tx_status *); |
1040 | int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, | ||
1041 | struct ath5k_rx_status *); | ||
1048 | }; | 1042 | }; |
1049 | 1043 | ||
1050 | /* | 1044 | /* |
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c index fc4db8834c3..73e7e613a3c 100644 --- a/drivers/net/wireless/ath5k/base.c +++ b/drivers/net/wireless/ath5k/base.c | |||
@@ -283,7 +283,8 @@ static int ath5k_rx_start(struct ath5k_softc *sc); | |||
283 | static void ath5k_rx_stop(struct ath5k_softc *sc); | 283 | static void ath5k_rx_stop(struct ath5k_softc *sc); |
284 | static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc, | 284 | static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc, |
285 | struct ath5k_desc *ds, | 285 | struct ath5k_desc *ds, |
286 | struct sk_buff *skb); | 286 | struct sk_buff *skb, |
287 | struct ath5k_rx_status *rs); | ||
287 | static void ath5k_tasklet_rx(unsigned long data); | 288 | static void ath5k_tasklet_rx(unsigned long data); |
288 | /* Tx handling */ | 289 | /* Tx handling */ |
289 | static void ath5k_tx_processq(struct ath5k_softc *sc, | 290 | static void ath5k_tx_processq(struct ath5k_softc *sc, |
@@ -1563,8 +1564,7 @@ ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq) | |||
1563 | */ | 1564 | */ |
1564 | spin_lock_bh(&txq->lock); | 1565 | spin_lock_bh(&txq->lock); |
1565 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | 1566 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { |
1566 | ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah, | 1567 | ath5k_debug_printtxbuf(sc, bf); |
1567 | bf->desc)); | ||
1568 | 1568 | ||
1569 | ath5k_txbuf_free(sc, bf); | 1569 | ath5k_txbuf_free(sc, bf); |
1570 | 1570 | ||
@@ -1689,20 +1689,20 @@ ath5k_rx_stop(struct ath5k_softc *sc) | |||
1689 | 1689 | ||
1690 | static unsigned int | 1690 | static unsigned int |
1691 | ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds, | 1691 | ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds, |
1692 | struct sk_buff *skb) | 1692 | struct sk_buff *skb, struct ath5k_rx_status *rs) |
1693 | { | 1693 | { |
1694 | struct ieee80211_hdr *hdr = (void *)skb->data; | 1694 | struct ieee80211_hdr *hdr = (void *)skb->data; |
1695 | unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb); | 1695 | unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb); |
1696 | 1696 | ||
1697 | if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && | 1697 | if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && |
1698 | ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID) | 1698 | rs->rs_keyix != AR5K_RXKEYIX_INVALID) |
1699 | return RX_FLAG_DECRYPTED; | 1699 | return RX_FLAG_DECRYPTED; |
1700 | 1700 | ||
1701 | /* Apparently when a default key is used to decrypt the packet | 1701 | /* Apparently when a default key is used to decrypt the packet |
1702 | the hw does not set the index used to decrypt. In such cases | 1702 | the hw does not set the index used to decrypt. In such cases |
1703 | get the index from the packet. */ | 1703 | get the index from the packet. */ |
1704 | if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && | 1704 | if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && |
1705 | !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && | 1705 | !(rs->rs_status & AR5K_RXERR_DECRYPT) && |
1706 | skb->len >= hlen + 4) { | 1706 | skb->len >= hlen + 4) { |
1707 | keyix = skb->data[hlen + 3] >> 6; | 1707 | keyix = skb->data[hlen + 3] >> 6; |
1708 | 1708 | ||
@@ -1745,12 +1745,11 @@ static void | |||
1745 | ath5k_tasklet_rx(unsigned long data) | 1745 | ath5k_tasklet_rx(unsigned long data) |
1746 | { | 1746 | { |
1747 | struct ieee80211_rx_status rxs = {}; | 1747 | struct ieee80211_rx_status rxs = {}; |
1748 | struct ath5k_rx_status rs = {}; | ||
1748 | struct sk_buff *skb; | 1749 | struct sk_buff *skb; |
1749 | struct ath5k_softc *sc = (void *)data; | 1750 | struct ath5k_softc *sc = (void *)data; |
1750 | struct ath5k_buf *bf; | 1751 | struct ath5k_buf *bf; |
1751 | struct ath5k_desc *ds; | 1752 | struct ath5k_desc *ds; |
1752 | u16 len; | ||
1753 | u8 stat; | ||
1754 | int ret; | 1753 | int ret; |
1755 | int hdrlen; | 1754 | int hdrlen; |
1756 | int pad; | 1755 | int pad; |
@@ -1773,7 +1772,7 @@ ath5k_tasklet_rx(unsigned long data) | |||
1773 | if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */ | 1772 | if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */ |
1774 | break; | 1773 | break; |
1775 | 1774 | ||
1776 | ret = sc->ah->ah_proc_rx_desc(sc->ah, ds); | 1775 | ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); |
1777 | if (unlikely(ret == -EINPROGRESS)) | 1776 | if (unlikely(ret == -EINPROGRESS)) |
1778 | break; | 1777 | break; |
1779 | else if (unlikely(ret)) { | 1778 | else if (unlikely(ret)) { |
@@ -1782,16 +1781,15 @@ ath5k_tasklet_rx(unsigned long data) | |||
1782 | return; | 1781 | return; |
1783 | } | 1782 | } |
1784 | 1783 | ||
1785 | if (unlikely(ds->ds_rxstat.rs_more)) { | 1784 | if (unlikely(rs.rs_more)) { |
1786 | ATH5K_WARN(sc, "unsupported jumbo\n"); | 1785 | ATH5K_WARN(sc, "unsupported jumbo\n"); |
1787 | goto next; | 1786 | goto next; |
1788 | } | 1787 | } |
1789 | 1788 | ||
1790 | stat = ds->ds_rxstat.rs_status; | 1789 | if (unlikely(rs.rs_status)) { |
1791 | if (unlikely(stat)) { | 1790 | if (rs.rs_status & AR5K_RXERR_PHY) |
1792 | if (stat & AR5K_RXERR_PHY) | ||
1793 | goto next; | 1791 | goto next; |
1794 | if (stat & AR5K_RXERR_DECRYPT) { | 1792 | if (rs.rs_status & AR5K_RXERR_DECRYPT) { |
1795 | /* | 1793 | /* |
1796 | * Decrypt error. If the error occurred | 1794 | * Decrypt error. If the error occurred |
1797 | * because there was no hardware key, then | 1795 | * because there was no hardware key, then |
@@ -1802,30 +1800,29 @@ ath5k_tasklet_rx(unsigned long data) | |||
1802 | * | 1800 | * |
1803 | * XXX do key cache faulting | 1801 | * XXX do key cache faulting |
1804 | */ | 1802 | */ |
1805 | if (ds->ds_rxstat.rs_keyix == | 1803 | if (rs.rs_keyix == AR5K_RXKEYIX_INVALID && |
1806 | AR5K_RXKEYIX_INVALID && | 1804 | !(rs.rs_status & AR5K_RXERR_CRC)) |
1807 | !(stat & AR5K_RXERR_CRC)) | ||
1808 | goto accept; | 1805 | goto accept; |
1809 | } | 1806 | } |
1810 | if (stat & AR5K_RXERR_MIC) { | 1807 | if (rs.rs_status & AR5K_RXERR_MIC) { |
1811 | rxs.flag |= RX_FLAG_MMIC_ERROR; | 1808 | rxs.flag |= RX_FLAG_MMIC_ERROR; |
1812 | goto accept; | 1809 | goto accept; |
1813 | } | 1810 | } |
1814 | 1811 | ||
1815 | /* let crypto-error packets fall through in MNTR */ | 1812 | /* let crypto-error packets fall through in MNTR */ |
1816 | if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || | 1813 | if ((rs.rs_status & |
1814 | ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || | ||
1817 | sc->opmode != IEEE80211_IF_TYPE_MNTR) | 1815 | sc->opmode != IEEE80211_IF_TYPE_MNTR) |
1818 | goto next; | 1816 | goto next; |
1819 | } | 1817 | } |
1820 | accept: | 1818 | accept: |
1821 | len = ds->ds_rxstat.rs_datalen; | 1819 | pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, |
1822 | pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len, | 1820 | rs.rs_datalen, PCI_DMA_FROMDEVICE); |
1823 | PCI_DMA_FROMDEVICE); | ||
1824 | pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, | 1821 | pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, |
1825 | PCI_DMA_FROMDEVICE); | 1822 | PCI_DMA_FROMDEVICE); |
1826 | bf->skb = NULL; | 1823 | bf->skb = NULL; |
1827 | 1824 | ||
1828 | skb_put(skb, len); | 1825 | skb_put(skb, rs.rs_datalen); |
1829 | 1826 | ||
1830 | /* | 1827 | /* |
1831 | * the hardware adds a padding to 4 byte boundaries between | 1828 | * the hardware adds a padding to 4 byte boundaries between |
@@ -1848,7 +1845,7 @@ accept: | |||
1848 | * 32768usec (about 32ms). it might be necessary to move this to | 1845 | * 32768usec (about 32ms). it might be necessary to move this to |
1849 | * the interrupt handler, like it is done in madwifi. | 1846 | * the interrupt handler, like it is done in madwifi. |
1850 | */ | 1847 | */ |
1851 | rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp); | 1848 | rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp); |
1852 | rxs.flag |= RX_FLAG_TSFT; | 1849 | rxs.flag |= RX_FLAG_TSFT; |
1853 | 1850 | ||
1854 | rxs.freq = sc->curchan->center_freq; | 1851 | rxs.freq = sc->curchan->center_freq; |
@@ -1862,17 +1859,16 @@ accept: | |||
1862 | /* noise floor in dBm, from the last noise calibration */ | 1859 | /* noise floor in dBm, from the last noise calibration */ |
1863 | rxs.noise = sc->ah->ah_noise_floor; | 1860 | rxs.noise = sc->ah->ah_noise_floor; |
1864 | /* signal level in dBm */ | 1861 | /* signal level in dBm */ |
1865 | rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi; | 1862 | rxs.ssi = rxs.noise + rs.rs_rssi; |
1866 | /* | 1863 | /* |
1867 | * "signal" is actually displayed as Link Quality by iwconfig | 1864 | * "signal" is actually displayed as Link Quality by iwconfig |
1868 | * we provide a percentage based on rssi (assuming max rssi 64) | 1865 | * we provide a percentage based on rssi (assuming max rssi 64) |
1869 | */ | 1866 | */ |
1870 | rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64; | 1867 | rxs.signal = rs.rs_rssi * 100 / 64; |
1871 | 1868 | ||
1872 | rxs.antenna = ds->ds_rxstat.rs_antenna; | 1869 | rxs.antenna = rs.rs_antenna; |
1873 | rxs.rate_idx = ath5k_hw_to_driver_rix(sc, | 1870 | rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate); |
1874 | ds->ds_rxstat.rs_rate); | 1871 | rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs); |
1875 | rxs.flag |= ath5k_rx_decrypted(sc, ds, skb); | ||
1876 | 1872 | ||
1877 | ath5k_debug_dump_skb(sc, skb, "RX ", 0); | 1873 | ath5k_debug_dump_skb(sc, skb, "RX ", 0); |
1878 | 1874 | ||
@@ -1881,7 +1877,7 @@ accept: | |||
1881 | ath5k_check_ibss_hw_merge(sc, skb); | 1877 | ath5k_check_ibss_hw_merge(sc, skb); |
1882 | 1878 | ||
1883 | __ieee80211_rx(sc->hw, skb, &rxs); | 1879 | __ieee80211_rx(sc->hw, skb, &rxs); |
1884 | sc->led_rxrate = ds->ds_rxstat.rs_rate; | 1880 | sc->led_rxrate = rs.rs_rate; |
1885 | ath5k_led_event(sc, ATH_LED_RX); | 1881 | ath5k_led_event(sc, ATH_LED_RX); |
1886 | next: | 1882 | next: |
1887 | list_move_tail(&bf->list, &sc->rxbuf); | 1883 | list_move_tail(&bf->list, &sc->rxbuf); |
@@ -1900,6 +1896,7 @@ static void | |||
1900 | ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) | 1896 | ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) |
1901 | { | 1897 | { |
1902 | struct ieee80211_tx_status txs = {}; | 1898 | struct ieee80211_tx_status txs = {}; |
1899 | struct ath5k_tx_status ts = {}; | ||
1903 | struct ath5k_buf *bf, *bf0; | 1900 | struct ath5k_buf *bf, *bf0; |
1904 | struct ath5k_desc *ds; | 1901 | struct ath5k_desc *ds; |
1905 | struct sk_buff *skb; | 1902 | struct sk_buff *skb; |
@@ -1912,7 +1909,7 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) | |||
1912 | /* TODO only one segment */ | 1909 | /* TODO only one segment */ |
1913 | pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, | 1910 | pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, |
1914 | sc->desc_len, PCI_DMA_FROMDEVICE); | 1911 | sc->desc_len, PCI_DMA_FROMDEVICE); |
1915 | ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); | 1912 | ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); |
1916 | if (unlikely(ret == -EINPROGRESS)) | 1913 | if (unlikely(ret == -EINPROGRESS)) |
1917 | break; | 1914 | break; |
1918 | else if (unlikely(ret)) { | 1915 | else if (unlikely(ret)) { |
@@ -1927,17 +1924,16 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) | |||
1927 | PCI_DMA_TODEVICE); | 1924 | PCI_DMA_TODEVICE); |
1928 | 1925 | ||
1929 | txs.control = bf->ctl; | 1926 | txs.control = bf->ctl; |
1930 | txs.retry_count = ds->ds_txstat.ts_shortretry + | 1927 | txs.retry_count = ts.ts_shortretry + ts.ts_longretry / 6; |
1931 | ds->ds_txstat.ts_longretry / 6; | 1928 | if (unlikely(ts.ts_status)) { |
1932 | if (unlikely(ds->ds_txstat.ts_status)) { | ||
1933 | sc->ll_stats.dot11ACKFailureCount++; | 1929 | sc->ll_stats.dot11ACKFailureCount++; |
1934 | if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) | 1930 | if (ts.ts_status & AR5K_TXERR_XRETRY) |
1935 | txs.excessive_retries = 1; | 1931 | txs.excessive_retries = 1; |
1936 | else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) | 1932 | else if (ts.ts_status & AR5K_TXERR_FILT) |
1937 | txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; | 1933 | txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; |
1938 | } else { | 1934 | } else { |
1939 | txs.flags |= IEEE80211_TX_STATUS_ACK; | 1935 | txs.flags |= IEEE80211_TX_STATUS_ACK; |
1940 | txs.ack_signal = ds->ds_txstat.ts_rssi; | 1936 | txs.ack_signal = ts.ts_rssi; |
1941 | } | 1937 | } |
1942 | 1938 | ||
1943 | ieee80211_tx_status(sc->hw, skb, &txs); | 1939 | ieee80211_tx_status(sc->hw, skb, &txs); |
diff --git a/drivers/net/wireless/ath5k/debug.c b/drivers/net/wireless/ath5k/debug.c index 93014944f43..d3eb9e88c84 100644 --- a/drivers/net/wireless/ath5k/debug.c +++ b/drivers/net/wireless/ath5k/debug.c | |||
@@ -497,7 +497,8 @@ ath5k_debug_dump_bands(struct ath5k_softc *sc) | |||
497 | } | 497 | } |
498 | 498 | ||
499 | static inline void | 499 | static inline void |
500 | ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done) | 500 | ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done, |
501 | struct ath5k_rx_status *rs) | ||
501 | { | 502 | { |
502 | struct ath5k_desc *ds = bf->desc; | 503 | struct ath5k_desc *ds = bf->desc; |
503 | struct ath5k_hw_all_rx_desc *rd = &ds->ud.ds_rx; | 504 | struct ath5k_hw_all_rx_desc *rd = &ds->ud.ds_rx; |
@@ -507,7 +508,7 @@ ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done) | |||
507 | ds->ds_link, ds->ds_data, | 508 | ds->ds_link, ds->ds_data, |
508 | rd->rx_ctl.rx_control_0, rd->rx_ctl.rx_control_1, | 509 | rd->rx_ctl.rx_control_0, rd->rx_ctl.rx_control_1, |
509 | rd->u.rx_stat.rx_status_0, rd->u.rx_stat.rx_status_0, | 510 | rd->u.rx_stat.rx_status_0, rd->u.rx_stat.rx_status_0, |
510 | !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); | 511 | !done ? ' ' : (rs->rs_status == 0) ? '*' : '!'); |
511 | } | 512 | } |
512 | 513 | ||
513 | void | 514 | void |
@@ -515,6 +516,7 @@ ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah) | |||
515 | { | 516 | { |
516 | struct ath5k_desc *ds; | 517 | struct ath5k_desc *ds; |
517 | struct ath5k_buf *bf; | 518 | struct ath5k_buf *bf; |
519 | struct ath5k_rx_status rs = {}; | ||
518 | int status; | 520 | int status; |
519 | 521 | ||
520 | if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET))) | 522 | if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET))) |
@@ -526,9 +528,9 @@ ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah) | |||
526 | spin_lock_bh(&sc->rxbuflock); | 528 | spin_lock_bh(&sc->rxbuflock); |
527 | list_for_each_entry(bf, &sc->rxbuf, list) { | 529 | list_for_each_entry(bf, &sc->rxbuf, list) { |
528 | ds = bf->desc; | 530 | ds = bf->desc; |
529 | status = ah->ah_proc_rx_desc(ah, ds); | 531 | status = ah->ah_proc_rx_desc(ah, ds, &rs); |
530 | if (!status) | 532 | if (!status) |
531 | ath5k_debug_printrxbuf(bf, status == 0); | 533 | ath5k_debug_printrxbuf(bf, status == 0, &rs); |
532 | } | 534 | } |
533 | spin_unlock_bh(&sc->rxbuflock); | 535 | spin_unlock_bh(&sc->rxbuflock); |
534 | } | 536 | } |
@@ -552,21 +554,24 @@ ath5k_debug_dump_skb(struct ath5k_softc *sc, | |||
552 | } | 554 | } |
553 | 555 | ||
554 | void | 556 | void |
555 | ath5k_debug_printtxbuf(struct ath5k_softc *sc, | 557 | ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf) |
556 | struct ath5k_buf *bf, int done) | ||
557 | { | 558 | { |
558 | struct ath5k_desc *ds = bf->desc; | 559 | struct ath5k_desc *ds = bf->desc; |
559 | struct ath5k_hw_5212_tx_desc *td = &ds->ud.ds_tx5212; | 560 | struct ath5k_hw_5212_tx_desc *td = &ds->ud.ds_tx5212; |
561 | struct ath5k_tx_status ts = {}; | ||
562 | int done; | ||
560 | 563 | ||
561 | if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET))) | 564 | if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET))) |
562 | return; | 565 | return; |
563 | 566 | ||
567 | done = sc->ah->ah_proc_tx_desc(sc->ah, bf->desc, &ts); | ||
568 | |||
564 | printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x " | 569 | printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x " |
565 | "%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link, | 570 | "%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link, |
566 | ds->ds_data, td->tx_ctl.tx_control_0, td->tx_ctl.tx_control_1, | 571 | ds->ds_data, td->tx_ctl.tx_control_0, td->tx_ctl.tx_control_1, |
567 | td->tx_ctl.tx_control_2, td->tx_ctl.tx_control_3, | 572 | td->tx_ctl.tx_control_2, td->tx_ctl.tx_control_3, |
568 | td->tx_stat.tx_status_0, td->tx_stat.tx_status_1, | 573 | td->tx_stat.tx_status_0, td->tx_stat.tx_status_1, |
569 | !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); | 574 | done ? ' ' : (ts.ts_status == 0) ? '*' : '!'); |
570 | } | 575 | } |
571 | 576 | ||
572 | #endif /* ifdef CONFIG_ATH5K_DEBUG */ | 577 | #endif /* ifdef CONFIG_ATH5K_DEBUG */ |
diff --git a/drivers/net/wireless/ath5k/debug.h b/drivers/net/wireless/ath5k/debug.h index 8c0b5c57c76..2cf8d18b10e 100644 --- a/drivers/net/wireless/ath5k/debug.h +++ b/drivers/net/wireless/ath5k/debug.h | |||
@@ -160,8 +160,7 @@ ath5k_debug_dump_skb(struct ath5k_softc *sc, | |||
160 | struct sk_buff *skb, const char *prefix, int tx); | 160 | struct sk_buff *skb, const char *prefix, int tx); |
161 | 161 | ||
162 | void | 162 | void |
163 | ath5k_debug_printtxbuf(struct ath5k_softc *sc, | 163 | ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf); |
164 | struct ath5k_buf *bf, int done); | ||
165 | 164 | ||
166 | #else /* no debugging */ | 165 | #else /* no debugging */ |
167 | 166 | ||
@@ -199,8 +198,7 @@ ath5k_debug_dump_skb(struct ath5k_softc *sc, | |||
199 | struct sk_buff *skb, const char *prefix, int tx) {} | 198 | struct sk_buff *skb, const char *prefix, int tx) {} |
200 | 199 | ||
201 | static inline void | 200 | static inline void |
202 | ath5k_debug_printtxbuf(struct ath5k_softc *sc, | 201 | ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf) {} |
203 | struct ath5k_buf *bf, int done) {} | ||
204 | 202 | ||
205 | #endif /* ifdef CONFIG_ATH5K_DEBUG */ | 203 | #endif /* ifdef CONFIG_ATH5K_DEBUG */ |
206 | 204 | ||
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c index f88adf52a1b..a4e312d4226 100644 --- a/drivers/net/wireless/ath5k/hw.c +++ b/drivers/net/wireless/ath5k/hw.c | |||
@@ -48,14 +48,18 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *, | |||
48 | static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *, | 48 | static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *, |
49 | unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, | 49 | unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, |
50 | unsigned int); | 50 | unsigned int); |
51 | static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *); | 51 | static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *, |
52 | struct ath5k_tx_status *); | ||
52 | static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *, | 53 | static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *, |
53 | unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, | 54 | unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, |
54 | unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, | 55 | unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, |
55 | unsigned int, unsigned int); | 56 | unsigned int, unsigned int); |
56 | static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *); | 57 | static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *, |
57 | static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *, struct ath5k_desc *); | 58 | struct ath5k_tx_status *); |
58 | static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *, struct ath5k_desc *); | 59 | static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *, struct ath5k_desc *, |
60 | struct ath5k_rx_status *); | ||
61 | static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *, struct ath5k_desc *, | ||
62 | struct ath5k_rx_status *); | ||
59 | static int ath5k_hw_get_capabilities(struct ath5k_hw *); | 63 | static int ath5k_hw_get_capabilities(struct ath5k_hw *); |
60 | 64 | ||
61 | static int ath5k_eeprom_init(struct ath5k_hw *); | 65 | static int ath5k_eeprom_init(struct ath5k_hw *); |
@@ -3798,7 +3802,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, | |||
3798 | * Proccess the tx status descriptor on 5210/5211 | 3802 | * Proccess the tx status descriptor on 5210/5211 |
3799 | */ | 3803 | */ |
3800 | static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah, | 3804 | static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah, |
3801 | struct ath5k_desc *desc) | 3805 | struct ath5k_desc *desc, struct ath5k_tx_status *ts) |
3802 | { | 3806 | { |
3803 | struct ath5k_hw_2w_tx_ctl *tx_ctl; | 3807 | struct ath5k_hw_2w_tx_ctl *tx_ctl; |
3804 | struct ath5k_hw_tx_status *tx_status; | 3808 | struct ath5k_hw_tx_status *tx_status; |
@@ -3815,32 +3819,32 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah, | |||
3815 | /* | 3819 | /* |
3816 | * Get descriptor status | 3820 | * Get descriptor status |
3817 | */ | 3821 | */ |
3818 | desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, | 3822 | ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, |
3819 | AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); | 3823 | AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); |
3820 | desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, | 3824 | ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, |
3821 | AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); | 3825 | AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); |
3822 | desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, | 3826 | ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, |
3823 | AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); | 3827 | AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); |
3824 | /*TODO: desc->ds_us.tx.ts_virtcol + test*/ | 3828 | /*TODO: ts->ts_virtcol + test*/ |
3825 | desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, | 3829 | ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, |
3826 | AR5K_DESC_TX_STATUS1_SEQ_NUM); | 3830 | AR5K_DESC_TX_STATUS1_SEQ_NUM); |
3827 | desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, | 3831 | ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, |
3828 | AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); | 3832 | AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); |
3829 | desc->ds_us.tx.ts_antenna = 1; | 3833 | ts->ts_antenna = 1; |
3830 | desc->ds_us.tx.ts_status = 0; | 3834 | ts->ts_status = 0; |
3831 | desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0, | 3835 | ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0, |
3832 | AR5K_2W_TX_DESC_CTL0_XMIT_RATE); | 3836 | AR5K_2W_TX_DESC_CTL0_XMIT_RATE); |
3833 | 3837 | ||
3834 | if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ | 3838 | if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ |
3835 | if (tx_status->tx_status_0 & | 3839 | if (tx_status->tx_status_0 & |
3836 | AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) | 3840 | AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) |
3837 | desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; | 3841 | ts->ts_status |= AR5K_TXERR_XRETRY; |
3838 | 3842 | ||
3839 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) | 3843 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) |
3840 | desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; | 3844 | ts->ts_status |= AR5K_TXERR_FIFO; |
3841 | 3845 | ||
3842 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) | 3846 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) |
3843 | desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; | 3847 | ts->ts_status |= AR5K_TXERR_FILT; |
3844 | } | 3848 | } |
3845 | 3849 | ||
3846 | return 0; | 3850 | return 0; |
@@ -3850,7 +3854,7 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah, | |||
3850 | * Proccess a tx descriptor on 5212 | 3854 | * Proccess a tx descriptor on 5212 |
3851 | */ | 3855 | */ |
3852 | static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah, | 3856 | static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah, |
3853 | struct ath5k_desc *desc) | 3857 | struct ath5k_desc *desc, struct ath5k_tx_status *ts) |
3854 | { | 3858 | { |
3855 | struct ath5k_hw_4w_tx_ctl *tx_ctl; | 3859 | struct ath5k_hw_4w_tx_ctl *tx_ctl; |
3856 | struct ath5k_hw_tx_status *tx_status; | 3860 | struct ath5k_hw_tx_status *tx_status; |
@@ -3867,42 +3871,42 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah, | |||
3867 | /* | 3871 | /* |
3868 | * Get descriptor status | 3872 | * Get descriptor status |
3869 | */ | 3873 | */ |
3870 | desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, | 3874 | ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, |
3871 | AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); | 3875 | AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); |
3872 | desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, | 3876 | ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, |
3873 | AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); | 3877 | AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); |
3874 | desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, | 3878 | ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, |
3875 | AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); | 3879 | AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); |
3876 | desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, | 3880 | ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, |
3877 | AR5K_DESC_TX_STATUS1_SEQ_NUM); | 3881 | AR5K_DESC_TX_STATUS1_SEQ_NUM); |
3878 | desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, | 3882 | ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, |
3879 | AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); | 3883 | AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); |
3880 | desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & | 3884 | ts->ts_antenna = (tx_status->tx_status_1 & |
3881 | AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; | 3885 | AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; |
3882 | desc->ds_us.tx.ts_status = 0; | 3886 | ts->ts_status = 0; |
3883 | 3887 | ||
3884 | switch (AR5K_REG_MS(tx_status->tx_status_1, | 3888 | switch (AR5K_REG_MS(tx_status->tx_status_1, |
3885 | AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { | 3889 | AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { |
3886 | case 0: | 3890 | case 0: |
3887 | desc->ds_us.tx.ts_rate = tx_ctl->tx_control_3 & | 3891 | ts->ts_rate = tx_ctl->tx_control_3 & |
3888 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; | 3892 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; |
3889 | break; | 3893 | break; |
3890 | case 1: | 3894 | case 1: |
3891 | desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3, | 3895 | ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3, |
3892 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); | 3896 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); |
3893 | desc->ds_us.tx.ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2, | 3897 | ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2, |
3894 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); | 3898 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); |
3895 | break; | 3899 | break; |
3896 | case 2: | 3900 | case 2: |
3897 | desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3, | 3901 | ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3, |
3898 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); | 3902 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); |
3899 | desc->ds_us.tx.ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2, | 3903 | ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2, |
3900 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); | 3904 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); |
3901 | break; | 3905 | break; |
3902 | case 3: | 3906 | case 3: |
3903 | desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3, | 3907 | ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3, |
3904 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); | 3908 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); |
3905 | desc->ds_us.tx.ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2, | 3909 | ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2, |
3906 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); | 3910 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); |
3907 | break; | 3911 | break; |
3908 | } | 3912 | } |
@@ -3910,13 +3914,13 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah, | |||
3910 | if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ | 3914 | if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ |
3911 | if (tx_status->tx_status_0 & | 3915 | if (tx_status->tx_status_0 & |
3912 | AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) | 3916 | AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) |
3913 | desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; | 3917 | ts->ts_status |= AR5K_TXERR_XRETRY; |
3914 | 3918 | ||
3915 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) | 3919 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) |
3916 | desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; | 3920 | ts->ts_status |= AR5K_TXERR_FIFO; |
3917 | 3921 | ||
3918 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) | 3922 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) |
3919 | desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; | 3923 | ts->ts_status |= AR5K_TXERR_FILT; |
3920 | } | 3924 | } |
3921 | 3925 | ||
3922 | return 0; | 3926 | return 0; |
@@ -3961,7 +3965,7 @@ int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, | |||
3961 | * Proccess the rx status descriptor on 5210/5211 | 3965 | * Proccess the rx status descriptor on 5210/5211 |
3962 | */ | 3966 | */ |
3963 | static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah, | 3967 | static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah, |
3964 | struct ath5k_desc *desc) | 3968 | struct ath5k_desc *desc, struct ath5k_rx_status *rs) |
3965 | { | 3969 | { |
3966 | struct ath5k_hw_rx_status *rx_status; | 3970 | struct ath5k_hw_rx_status *rx_status; |
3967 | 3971 | ||
@@ -3975,28 +3979,29 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah, | |||
3975 | /* | 3979 | /* |
3976 | * Frame receive status | 3980 | * Frame receive status |
3977 | */ | 3981 | */ |
3978 | desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & | 3982 | rs->rs_datalen = rx_status->rx_status_0 & |
3979 | AR5K_5210_RX_DESC_STATUS0_DATA_LEN; | 3983 | AR5K_5210_RX_DESC_STATUS0_DATA_LEN; |
3980 | desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, | 3984 | rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, |
3981 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL); | 3985 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL); |
3982 | desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, | 3986 | rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, |
3983 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE); | 3987 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE); |
3984 | desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & | 3988 | rs->rs_antenna = rx_status->rx_status_0 & |
3985 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA; | 3989 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA; |
3986 | desc->ds_us.rx.rs_more = rx_status->rx_status_0 & | 3990 | rs->rs_more = rx_status->rx_status_0 & |
3987 | AR5K_5210_RX_DESC_STATUS0_MORE; | 3991 | AR5K_5210_RX_DESC_STATUS0_MORE; |
3988 | desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, | 3992 | /* TODO: this timestamp is 13 bit, later on we assume 15 bit */ |
3993 | rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, | ||
3989 | AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); | 3994 | AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); |
3990 | desc->ds_us.rx.rs_status = 0; | 3995 | rs->rs_status = 0; |
3991 | 3996 | ||
3992 | /* | 3997 | /* |
3993 | * Key table status | 3998 | * Key table status |
3994 | */ | 3999 | */ |
3995 | if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID) | 4000 | if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID) |
3996 | desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, | 4001 | rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, |
3997 | AR5K_5210_RX_DESC_STATUS1_KEY_INDEX); | 4002 | AR5K_5210_RX_DESC_STATUS1_KEY_INDEX); |
3998 | else | 4003 | else |
3999 | desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; | 4004 | rs->rs_keyix = AR5K_RXKEYIX_INVALID; |
4000 | 4005 | ||
4001 | /* | 4006 | /* |
4002 | * Receive/descriptor errors | 4007 | * Receive/descriptor errors |
@@ -4005,23 +4010,22 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah, | |||
4005 | AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { | 4010 | AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { |
4006 | if (rx_status->rx_status_1 & | 4011 | if (rx_status->rx_status_1 & |
4007 | AR5K_5210_RX_DESC_STATUS1_CRC_ERROR) | 4012 | AR5K_5210_RX_DESC_STATUS1_CRC_ERROR) |
4008 | desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; | 4013 | rs->rs_status |= AR5K_RXERR_CRC; |
4009 | 4014 | ||
4010 | if (rx_status->rx_status_1 & | 4015 | if (rx_status->rx_status_1 & |
4011 | AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN) | 4016 | AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN) |
4012 | desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO; | 4017 | rs->rs_status |= AR5K_RXERR_FIFO; |
4013 | 4018 | ||
4014 | if (rx_status->rx_status_1 & | 4019 | if (rx_status->rx_status_1 & |
4015 | AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) { | 4020 | AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) { |
4016 | desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; | 4021 | rs->rs_status |= AR5K_RXERR_PHY; |
4017 | desc->ds_us.rx.rs_phyerr = | 4022 | rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1, |
4018 | AR5K_REG_MS(rx_status->rx_status_1, | 4023 | AR5K_5210_RX_DESC_STATUS1_PHY_ERROR); |
4019 | AR5K_5210_RX_DESC_STATUS1_PHY_ERROR); | ||
4020 | } | 4024 | } |
4021 | 4025 | ||
4022 | if (rx_status->rx_status_1 & | 4026 | if (rx_status->rx_status_1 & |
4023 | AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) | 4027 | AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) |
4024 | desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; | 4028 | rs->rs_status |= AR5K_RXERR_DECRYPT; |
4025 | } | 4029 | } |
4026 | 4030 | ||
4027 | return 0; | 4031 | return 0; |
@@ -4031,7 +4035,7 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah, | |||
4031 | * Proccess the rx status descriptor on 5212 | 4035 | * Proccess the rx status descriptor on 5212 |
4032 | */ | 4036 | */ |
4033 | static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, | 4037 | static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, |
4034 | struct ath5k_desc *desc) | 4038 | struct ath5k_desc *desc, struct ath5k_rx_status *rs) |
4035 | { | 4039 | { |
4036 | struct ath5k_hw_rx_status *rx_status; | 4040 | struct ath5k_hw_rx_status *rx_status; |
4037 | struct ath5k_hw_rx_error *rx_err; | 4041 | struct ath5k_hw_rx_error *rx_err; |
@@ -4050,28 +4054,28 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, | |||
4050 | /* | 4054 | /* |
4051 | * Frame receive status | 4055 | * Frame receive status |
4052 | */ | 4056 | */ |
4053 | desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & | 4057 | rs->rs_datalen = rx_status->rx_status_0 & |
4054 | AR5K_5212_RX_DESC_STATUS0_DATA_LEN; | 4058 | AR5K_5212_RX_DESC_STATUS0_DATA_LEN; |
4055 | desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, | 4059 | rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, |
4056 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL); | 4060 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL); |
4057 | desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, | 4061 | rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, |
4058 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE); | 4062 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE); |
4059 | desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & | 4063 | rs->rs_antenna = rx_status->rx_status_0 & |
4060 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA; | 4064 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA; |
4061 | desc->ds_us.rx.rs_more = rx_status->rx_status_0 & | 4065 | rs->rs_more = rx_status->rx_status_0 & |
4062 | AR5K_5212_RX_DESC_STATUS0_MORE; | 4066 | AR5K_5212_RX_DESC_STATUS0_MORE; |
4063 | desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, | 4067 | rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, |
4064 | AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); | 4068 | AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); |
4065 | desc->ds_us.rx.rs_status = 0; | 4069 | rs->rs_status = 0; |
4066 | 4070 | ||
4067 | /* | 4071 | /* |
4068 | * Key table status | 4072 | * Key table status |
4069 | */ | 4073 | */ |
4070 | if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID) | 4074 | if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID) |
4071 | desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, | 4075 | rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, |
4072 | AR5K_5212_RX_DESC_STATUS1_KEY_INDEX); | 4076 | AR5K_5212_RX_DESC_STATUS1_KEY_INDEX); |
4073 | else | 4077 | else |
4074 | desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; | 4078 | rs->rs_keyix = AR5K_RXKEYIX_INVALID; |
4075 | 4079 | ||
4076 | /* | 4080 | /* |
4077 | * Receive/descriptor errors | 4081 | * Receive/descriptor errors |
@@ -4080,23 +4084,22 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, | |||
4080 | AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { | 4084 | AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { |
4081 | if (rx_status->rx_status_1 & | 4085 | if (rx_status->rx_status_1 & |
4082 | AR5K_5212_RX_DESC_STATUS1_CRC_ERROR) | 4086 | AR5K_5212_RX_DESC_STATUS1_CRC_ERROR) |
4083 | desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; | 4087 | rs->rs_status |= AR5K_RXERR_CRC; |
4084 | 4088 | ||
4085 | if (rx_status->rx_status_1 & | 4089 | if (rx_status->rx_status_1 & |
4086 | AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) { | 4090 | AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) { |
4087 | desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; | 4091 | rs->rs_status |= AR5K_RXERR_PHY; |
4088 | desc->ds_us.rx.rs_phyerr = | 4092 | rs->rs_phyerr = AR5K_REG_MS(rx_err->rx_error_1, |
4089 | AR5K_REG_MS(rx_err->rx_error_1, | 4093 | AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE); |
4090 | AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE); | ||
4091 | } | 4094 | } |
4092 | 4095 | ||
4093 | if (rx_status->rx_status_1 & | 4096 | if (rx_status->rx_status_1 & |
4094 | AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) | 4097 | AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) |
4095 | desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; | 4098 | rs->rs_status |= AR5K_RXERR_DECRYPT; |
4096 | 4099 | ||
4097 | if (rx_status->rx_status_1 & | 4100 | if (rx_status->rx_status_1 & |
4098 | AR5K_5212_RX_DESC_STATUS1_MIC_ERROR) | 4101 | AR5K_5212_RX_DESC_STATUS1_MIC_ERROR) |
4099 | desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; | 4102 | rs->rs_status |= AR5K_RXERR_MIC; |
4100 | } | 4103 | } |
4101 | 4104 | ||
4102 | return 0; | 4105 | return 0; |