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-rw-r--r--drivers/ata/Kconfig334
-rw-r--r--drivers/ata/Makefile41
-rw-r--r--drivers/ata/ata_generic.c252
-rw-r--r--drivers/ata/ata_piix.c436
-rw-r--r--drivers/ata/pata_ali.c679
-rw-r--r--drivers/ata/pata_amd.c707
-rw-r--r--drivers/ata/pata_artop.c518
-rw-r--r--drivers/ata/pata_atiixp.c306
-rw-r--r--drivers/ata/pata_cmd64x.c505
-rw-r--r--drivers/ata/pata_cs5520.c336
-rw-r--r--drivers/ata/pata_cs5530.c387
-rw-r--r--drivers/ata/pata_cs5535.c291
-rw-r--r--drivers/ata/pata_cypress.c227
-rw-r--r--drivers/ata/pata_efar.c342
-rw-r--r--drivers/ata/pata_hpt366.c478
-rw-r--r--drivers/ata/pata_hpt37x.c1257
-rw-r--r--drivers/ata/pata_hpt3x2n.c597
-rw-r--r--drivers/ata/pata_hpt3x3.c226
-rw-r--r--drivers/ata/pata_isapnp.c156
-rw-r--r--drivers/ata/pata_it8172.c288
-rw-r--r--drivers/ata/pata_it821x.c847
-rw-r--r--drivers/ata/pata_jmicron.c266
-rw-r--r--drivers/ata/pata_legacy.c949
-rw-r--r--drivers/ata/pata_mpiix.c313
-rw-r--r--drivers/ata/pata_netcell.c175
-rw-r--r--drivers/ata/pata_ns87410.c236
-rw-r--r--drivers/ata/pata_oldpiix.c339
-rw-r--r--drivers/ata/pata_opti.c292
-rw-r--r--drivers/ata/pata_optidma.c547
-rw-r--r--drivers/ata/pata_pcmcia.c393
-rw-r--r--drivers/ata/pata_pdc2027x.c869
-rw-r--r--drivers/ata/pata_pdc202xx_old.c423
-rw-r--r--drivers/ata/pata_qdi.c403
-rw-r--r--drivers/ata/pata_radisys.c335
-rw-r--r--drivers/ata/pata_rz1000.c205
-rw-r--r--drivers/ata/pata_sc1200.c287
-rw-r--r--drivers/ata/pata_serverworks.c587
-rw-r--r--drivers/ata/pata_sil680.c381
-rw-r--r--drivers/ata/pata_sis.c1030
-rw-r--r--drivers/ata/pata_sl82c105.c388
-rw-r--r--drivers/ata/pata_triflex.c285
-rw-r--r--drivers/ata/pata_via.c568
42 files changed, 18371 insertions, 110 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 13027d56b7f..cbda988692e 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -145,6 +145,340 @@ config SATA_INTEL_COMBINED
145 depends on IDE=y && !BLK_DEV_IDE_SATA && (SATA_AHCI || ATA_PIIX) 145 depends on IDE=y && !BLK_DEV_IDE_SATA && (SATA_AHCI || ATA_PIIX)
146 default y 146 default y
147 147
148config PATA_ALI
149 tristate "ALi PATA support (Experimental)"
150 depends on PCI && EXPERIMENTAL
151 help
152 This option enables support for the ALi ATA interfaces
153 found on the many ALi chipsets.
154
155 If unsure, say N.
156
157config PATA_AMD
158 tristate "AMD/NVidia PATA support (Experimental)"
159 depends on PCI
160 help
161 This option enables support for the AMD and NVidia PATA
162 interfaces found on the chipsets for Athlon/Athlon64.
163
164 If unsure, say N.
165
166config PATA_ARTOP
167 tristate "ARTOP 6210/6260 PATA support (Experimental)"
168 depends on PCI && EXPERIMENTAL
169 help
170 This option enables support for ARTOP PATA controllers.
171
172 If unsure, say N.
173
174config PATA_ATIIXP
175 tristate "ATI PATA support (Experimental)"
176 depends on PCI && EXPERIMENTAL
177 help
178 This option enables support for the ATI ATA interfaces
179 found on the many ATI chipsets.
180
181 If unsure, say N.
182
183config PATA_CMD64X
184 tristate "CMD64x PATA support (Very Experimental)"
185 depends on PCI&& EXPERIMENTAL
186 help
187 This option enables support for the CMD64x series chips
188 except for the CMD640.
189
190 If unsure, say N.
191
192config PATA_CS5520
193 tristate "CS5510/5520 PATA support"
194 depends on PCI
195 help
196 This option enables support for the Cyrix 5510/5520
197 companion chip used with the MediaGX/Geode processor family.
198
199 If unsure, say N.
200
201config PATA_CS5530
202 tristate "CS5530 PATA support (Experimental)"
203 depends on PCI && EXPERIMENTAL
204 help
205 This option enables support for the Cyrix/NatSemi/AMD CS5530
206 companion chip used with the MediaGX/Geode processor family.
207
208 If unsure, say N.
209
210config PATA_CS5535
211 tristate "CS5535 PATA support (Experimental)"
212 depends on PCI && X86 && !X86_64 && EXPERIMENTAL
213 help
214 This option enables support for the NatSemi/AMD CS5535
215 companion chip used with the Geode processor family.
216
217 If unsure, say N.
218
219config PATA_CYPRESS
220 tristate "Cypress CY82C693 PATA support (Very Experimental)"
221 depends on PCI && EXPERIMENTAL
222 help
223 This option enables support for the Cypress/Contaq CY82C693
224 chipset found in some Alpha systems
225
226 If unsure, say N.
227
228config PATA_EFAR
229 tristate "EFAR SLC90E66 support"
230 depends on PCI
231 help
232 This option enables support for the EFAR SLC90E66
233 IDE controller found on some older machines.
234
235 If unsure, say N.
236
237config ATA_GENERIC
238 tristate "Generic ATA support"
239 depends on PCI
240 help
241 This option enables support for generic BIOS configured
242 ATA controllers via the new ATA layer
243
244 If unsure, say N.
245
246config PATA_HPT366
247 tristate "HPT 366/368 PATA support (Very Experimental)"
248 depends on PCI && EXPERIMENTAL
249 help
250 This option enables support for the HPT 366 and 368
251 PATA controllers via the new ATA layer.
252
253 If unsure, say N.
254
255config PATA_HPT37X
256 tristate "HPT 370/370A/371/372/374/302 PATA support (Very Experimental)"
257 depends on PCI && EXPERIMENTAL
258 help
259 This option enables support for the majority of the later HPT
260 PATA controllers via the new ATA layer.
261
262 If unsure, say N.
263
264config PATA_HPT3X2N
265 tristate "HPT 372N/302N PATA support (Very Experimental)"
266 depends on PCI && EXPERIMENTAL
267 help
268 This option enables support for the N variant HPT PATA
269 controllers via the new ATA layer
270
271 If unsure, say N.
272
273config PATA_HPT3X3
274 tristate "HPT 343/363 PATA support (Experimental)"
275 depends on PCI
276 help
277 This option enables support for the HPT 343/363
278 PATA controllers via the new ATA layer
279
280 If unsure, say N.
281
282config PATA_ISAPNP
283 tristate "ISA Plug and Play PATA support (Very Experimental)"
284 depends on EXPERIMENTAL && ISAPNP
285 help
286 This option enables support for ISA plug & play ATA
287 controllers such as those found on old soundcards.
288
289 If unsure, say N.
290
291config PATA_IT8172
292 tristate "IT8172 PATA support (Very Experimental)"
293 depends on PCI && EXPERIMENTAL
294 help
295 This option enables support for the ITE 8172 PATA controller
296 via the new ATA layer.
297
298 If unsure, say N.
299
300config PATA_IT821X
301 tristate "IT821x PATA support (Experimental)"
302 depends on PCI && EXPERIMENTAL
303 help
304 This option enables support for the ITE 8211 and 8212
305 PATA controllers via the new ATA layer, including RAID
306 mode.
307
308 If unsure, say N.
309
310config PATA_LEGACY
311 tristate "Legacy ISA PATA support (Experimental)"
312 depends on PCI && EXPERIMENTAL
313 help
314 This option enables support for ISA/VLB bus legacy PATA
315 ports and allows them to be accessed via the new ATA layer.
316
317 If unsure, say N.
318
319config PATA_TRIFLEX
320 tristate "Compaq Triflex PATA support"
321 depends on PCI
322 help
323 Enable support for the Compaq 'Triflex' IDE controller as found
324 on many Compaq Pentium-Pro systems, via the new ATA layer.
325
326 If unsure, say N.
327
328config PATA_MPIIX
329 tristate "Intel PATA MPIIX support"
330 depends on PCI
331 help
332 This option enables support for MPIIX PATA support.
333
334 If unsure, say N.
335
336config PATA_OLDPIIX
337 tristate "Intel PATA old PIIX support (Experimental)"
338 depends on PCI && EXPERIMENTAL
339 help
340 This option enables support for old(?) PIIX PATA support.
341
342 If unsure, say N.
343
344config PATA_NETCELL
345 tristate "NETCELL Revolution RAID support"
346 depends on PCI
347 help
348 This option enables support for the Netcell Revolution RAID
349 PATA controller.
350
351 If unsure, say N.
352
353config PATA_NS87410
354 tristate "Nat Semi NS87410 PATA support (Experimental)"
355 depends on PCI && EXPERIMENTAL
356 help
357 This option enables support for the National Semiconductor
358 NS87410 PCI-IDE controller.
359
360 If unsure, say N.
361
362config PATA_OPTI
363 tristate "OPTI621/6215 PATA support (Very Experimental)"
364 depends on PCI && EXPERIMENTAL
365 help
366 This option enables full PIO support for the early Opti ATA
367 controllers found on some old motherboards.
368
369 If unsure, say N.
370
371config PATA_OPTIDMA
372 tristate "OPTI FireStar PATA support (Veyr Experimental)"
373 depends on PCI && EXPERIMENTAL
374 help
375 This option enables DMA/PIO support for the later OPTi
376 controllers found on some old motherboards and in some
377 latops
378
379 If unsure, say N.
380
381config PATA_PCMCIA
382 tristate "PCMCIA PATA support"
383 depends on PCMCIA
384 help
385 This option enables support for PCMCIA ATA interfaces, including
386 compact flash card adapters via the new ATA layer.
387
388 If unsure, say N.
389
390config PATA_PDC_OLD
391 tristate "Older Promise PATA controller support (Very Experimental)"
392 depends on PCI && EXPERIMENTAL
393 help
394 This option enables support for the Promise 20246, 20262, 20263,
395 20265 and 20267 adapters.
396
397 If unsure, say N.
398
399config PATA_QDI
400 tristate "QDI VLB PATA support"
401 help
402 Support for QDI 6500 and 6580 PATA controllers on VESA local bus.
403
404config PATA_RADISYS
405 tristate "RADISYS 82600 PATA support (Very experimental)"
406 depends on PCI && EXPERIMENTAL
407 help
408 This option enables support for the RADISYS 82600
409 PATA controllers via the new ATA layer
410
411 If unsure, say N.
412
413config PATA_RZ1000
414 tristate "PC Tech RZ1000 PATA support"
415 depends on PCI
416 help
417 This option enables basic support for the PC Tech RZ1000/1
418 PATA controllers via the new ATA layer
419
420 If unsure, say N.
421
422config PATA_SC1200
423 tristate "SC1200 PATA support (Raving Lunatic)"
424 depends on PCI && EXPERIMENTAL
425 help
426 This option enables support for the NatSemi/AMD SC1200 SoC
427 companion chip used with the Geode processor family.
428
429 If unsure, say N.
430
431config PATA_SERVERWORKS
432 tristate "SERVERWORKS OSB4/CSB5/CSB6/HT1000 PATA support (Experimental)"
433 depends on PCI && EXPERIMENTAL
434 help
435 This option enables support for the Serverworks OSB4/CSB5/CSB6 and
436 HT1000 PATA controllers, via the new ATA layer.
437
438 If unsure, say N.
439
440config PATA_PDC2027X
441 tristate "Promise PATA 2027x support"
442 depends on PCI
443 help
444 This option enables support for Promise PATA pdc20268 to pdc20277 host adapters.
445
446 If unsure, say N.
447
448config PATA_SIL680
449 tristate "CMD / Silicon Image 680 PATA support"
450 depends on PCI
451 help
452 This option enables support for CMD / Silicon Image 680 PATA.
453
454 If unsure, say N.
455
456config PATA_SIS
457 tristate "SiS PATA support (Experimental)"
458 depends on PCI && EXPERIMENTAL
459 help
460 This option enables support for SiS PATA controllers
461
462 If unsure, say N.
463
464config PATA_VIA
465 tristate "VIA PATA support"
466 depends on PCI
467 help
468 This option enables support for the VIA PATA interfaces
469 found on the many VIA chipsets.
470
471 If unsure, say N.
472
473config PATA_WINBOND
474 tristate "Winbond SL82C105 PATA support"
475 depends on PCI
476 help
477 This option enables support for SL82C105 PATA devices found in the
478 Netwinder and some other systems
479
480 If unsure, say N.
481
148endif 482endif
149endmenu 483endmenu
150 484
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index e260e3fe65c..b183a04aeaf 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -17,5 +17,46 @@ obj-$(CONFIG_SATA_ULI) += sata_uli.o
17obj-$(CONFIG_SATA_MV) += sata_mv.o 17obj-$(CONFIG_SATA_MV) += sata_mv.o
18obj-$(CONFIG_PDC_ADMA) += pdc_adma.o 18obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
19 19
20obj-$(CONFIG_PATA_ALI) += pata_ali.o
21obj-$(CONFIG_PATA_AMD) += pata_amd.o
22obj-$(CONFIG_PATA_ARTOP) += pata_artop.o
23obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o
24obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o
25obj-$(CONFIG_PATA_CS5520) += pata_cs5520.o
26obj-$(CONFIG_PATA_CS5530) += pata_cs5530.o
27obj-$(CONFIG_PATA_CS5535) += pata_cs5535.o
28obj-$(CONFIG_PATA_CYPRESS) += pata_cypress.o
29obj-$(CONFIG_PATA_EFAR) += pata_efar.o
30obj-$(CONFIG_PATA_HPT366) += pata_hpt366.o
31obj-$(CONFIG_PATA_HPT37X) += pata_hpt37x.o
32obj-$(CONFIG_PATA_HPT3X2N) += pata_hpt3x2n.o
33obj-$(CONFIG_PATA_HPT3X3) += pata_hpt3x3.o
34obj-$(CONFIG_PATA_ISAPNP) += pata_isapnp.o
35obj-$(CONFIG_PATA_IT8172) += pata_it8172.o
36obj-$(CONFIG_PATA_IT821X) += pata_it821x.o
37obj-$(CONFIG_PATA_NETCELL) += pata_netcell.o
38obj-$(CONFIG_PATA_NS87410) += pata_ns87410.o
39obj-$(CONFIG_PATA_OPTI) += pata_opti.o
40obj-$(CONFIG_PATA_OPTIDMA) += pata_optidma.o
41obj-$(CONFIG_PATA_MPIIX) += pata_mpiix.o
42obj-$(CONFIG_PATA_OLDPIIX) += pata_oldpiix.o
43obj-$(CONFIG_PATA_PCMCIA) += pata_pcmcia.o
44obj-$(CONFIG_PATA_PDC2027X) += pata_pdc2027x.o
45obj-$(CONFIG_PATA_PDC_OLD) += pata_pdc202xx_old.o
46obj-$(CONFIG_PATA_QDI) += pata_qdi.o
47obj-$(CONFIG_PATA_RADISYS) += pata_radisys.o
48obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
49obj-$(CONFIG_PATA_SC1200) += pata_sc1200.o
50obj-$(CONFIG_PATA_SERVERWORKS) += pata_serverworks.o
51obj-$(CONFIG_PATA_SIL680) += pata_sil680.o
52obj-$(CONFIG_PATA_VIA) += pata_via.o
53obj-$(CONFIG_PATA_WINBOND) += pata_sl82c105.o
54obj-$(CONFIG_PATA_SIS) += pata_sis.o
55obj-$(CONFIG_PATA_TRIFLEX) += pata_triflex.o
56# Should be last but one libata driver
57obj-$(CONFIG_ATA_GENERIC) += ata_generic.o
58# Should be last libata driver
59obj-$(CONFIG_PATA_LEGACY) += pata_legacy.o
60
20libata-objs := libata-core.o libata-scsi.o libata-sff.o libata-eh.o 61libata-objs := libata-core.o libata-scsi.o libata-sff.o libata-eh.o
21 62
diff --git a/drivers/ata/ata_generic.c b/drivers/ata/ata_generic.c
new file mode 100644
index 00000000000..20b191dcf7e
--- /dev/null
+++ b/drivers/ata/ata_generic.c
@@ -0,0 +1,252 @@
1/*
2 * ata_generic.c - Generic PATA/SATA controller driver.
3 * Copyright 2005 Red Hat Inc <alan@redhat.com>, all rights reserved.
4 *
5 * Elements from ide/pci/generic.c
6 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
7 * Portions (C) Copyright 2002 Red Hat Inc <alan@redhat.com>
8 *
9 * May be copied or modified under the terms of the GNU General Public License
10 *
11 * Driver for PCI IDE interfaces implementing the standard bus mastering
12 * interface functionality. This assumes the BIOS did the drive set up and
13 * tuning for us. By default we do not grab all IDE class devices as they
14 * may have other drivers or need fixups to avoid problems. Instead we keep
15 * a default list of stuff without documentation/driver that appears to
16 * work.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <scsi/scsi_host.h>
26#include <linux/libata.h>
27
28#define DRV_NAME "ata_generic"
29#define DRV_VERSION "0.2.6"
30
31/*
32 * A generic parallel ATA driver using libata
33 */
34
35/**
36 * generic_pre_reset - probe begin
37 * @ap: ATA port
38 *
39 * Set up cable type and use generic probe init
40 */
41
42static int generic_pre_reset(struct ata_port *ap)
43{
44 ap->cbl = ATA_CBL_PATA80;
45 return ata_std_prereset(ap);
46}
47
48
49/**
50 * generic_error_handler - Probe specified port on PATA host controller
51 * @ap: Port to probe
52 * @classes:
53 *
54 * LOCKING:
55 * None (inherited from caller).
56 */
57
58
59static void generic_error_handler(struct ata_port *ap)
60{
61 ata_bmdma_drive_eh(ap, generic_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
62}
63
64/**
65 * generic_set_mode - mode setting
66 * @ap: interface to set up
67 *
68 * Use a non standard set_mode function. We don't want to be tuned.
69 * The BIOS configured everything. Our job is not to fiddle. We
70 * read the dma enabled bits from the PCI configuration of the device
71 * and respect them.
72 */
73
74static void generic_set_mode(struct ata_port *ap)
75{
76 int dma_enabled = 0;
77 int i;
78
79 /* Bits 5 and 6 indicate if DMA is active on master/slave */
80 if (ap->ioaddr.bmdma_addr)
81 dma_enabled = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
82
83 for (i = 0; i < ATA_MAX_DEVICES; i++) {
84 struct ata_device *dev = &ap->device[i];
85 if (ata_dev_enabled(dev)) {
86 /* We don't really care */
87 dev->pio_mode = XFER_PIO_0;
88 dev->dma_mode = XFER_MW_DMA_0;
89 /* We do need the right mode information for DMA or PIO
90 and this comes from the current configuration flags */
91 if (dma_enabled & (1 << (5 + i))) {
92 dev->xfer_mode = XFER_MW_DMA_0;
93 dev->xfer_shift = ATA_SHIFT_MWDMA;
94 dev->flags &= ~ATA_DFLAG_PIO;
95 } else {
96 dev->xfer_mode = XFER_PIO_0;
97 dev->xfer_shift = ATA_SHIFT_PIO;
98 dev->flags |= ATA_DFLAG_PIO;
99 }
100 }
101 }
102}
103
104static struct scsi_host_template generic_sht = {
105 .module = THIS_MODULE,
106 .name = DRV_NAME,
107 .ioctl = ata_scsi_ioctl,
108 .queuecommand = ata_scsi_queuecmd,
109 .can_queue = ATA_DEF_QUEUE,
110 .this_id = ATA_SHT_THIS_ID,
111 .sg_tablesize = LIBATA_MAX_PRD,
112 .max_sectors = ATA_MAX_SECTORS,
113 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
114 .emulated = ATA_SHT_EMULATED,
115 .use_clustering = ATA_SHT_USE_CLUSTERING,
116 .proc_name = DRV_NAME,
117 .dma_boundary = ATA_DMA_BOUNDARY,
118 .slave_configure = ata_scsi_slave_config,
119 .bios_param = ata_std_bios_param,
120};
121
122static struct ata_port_operations generic_port_ops = {
123 .set_mode = generic_set_mode,
124
125 .port_disable = ata_port_disable,
126 .tf_load = ata_tf_load,
127 .tf_read = ata_tf_read,
128 .check_status = ata_check_status,
129 .exec_command = ata_exec_command,
130 .dev_select = ata_std_dev_select,
131
132 .bmdma_setup = ata_bmdma_setup,
133 .bmdma_start = ata_bmdma_start,
134 .bmdma_stop = ata_bmdma_stop,
135 .bmdma_status = ata_bmdma_status,
136
137 .data_xfer = ata_pio_data_xfer,
138
139 .freeze = ata_bmdma_freeze,
140 .thaw = ata_bmdma_thaw,
141 .error_handler = generic_error_handler,
142 .post_internal_cmd = ata_bmdma_post_internal_cmd,
143
144 .qc_prep = ata_qc_prep,
145 .qc_issue = ata_qc_issue_prot,
146 .eng_timeout = ata_eng_timeout,
147 .irq_handler = ata_interrupt,
148 .irq_clear = ata_bmdma_irq_clear,
149
150 .port_start = ata_port_start,
151 .port_stop = ata_port_stop,
152 .host_stop = ata_host_stop
153};
154
155static int all_generic_ide; /* Set to claim all devices */
156
157/**
158 * ata_generic_init - attach generic IDE
159 * @dev: PCI device found
160 * @id: match entry
161 *
162 * Called each time a matching IDE interface is found. We check if the
163 * interface is one we wish to claim and if so we perform any chip
164 * specific hacks then let the ATA layer do the heavy lifting.
165 */
166
167static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
168{
169 u16 command;
170 static struct ata_port_info info = {
171 .sht = &generic_sht,
172 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
173 .pio_mask = 0x1f,
174 .mwdma_mask = 0x07,
175 .udma_mask = 0x3f,
176 .port_ops = &generic_port_ops
177 };
178 static struct ata_port_info *port_info[2] = { &info, &info };
179
180 /* Don't use the generic entry unless instructed to do so */
181 if (id->driver_data == 1 && all_generic_ide == 0)
182 return -ENODEV;
183
184 /* Devices that need care */
185 if (dev->vendor == PCI_VENDOR_ID_UMC &&
186 dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
187 (!(PCI_FUNC(dev->devfn) & 1)))
188 return -ENODEV;
189
190 if (dev->vendor == PCI_VENDOR_ID_OPTI &&
191 dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
192 (!(PCI_FUNC(dev->devfn) & 1)))
193 return -ENODEV;
194
195 /* Don't re-enable devices in generic mode or we will break some
196 motherboards with disabled and unused IDE controllers */
197 pci_read_config_word(dev, PCI_COMMAND, &command);
198 if (!(command & PCI_COMMAND_IO))
199 return -ENODEV;
200
201 if (dev->vendor == PCI_VENDOR_ID_AL)
202 ata_pci_clear_simplex(dev);
203
204 return ata_pci_init_one(dev, port_info, 2);
205}
206
207static struct pci_device_id ata_generic[] = {
208 { PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
209 { PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
210 { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F), },
211 { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A), },
212 { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF), },
213 { PCI_DEVICE(PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), },
214 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561), },
215 { PCI_DEVICE(PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558), },
216 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO), },
217 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
218 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), },
219 /* Must come last. If you add entries adjust this table appropriately */
220 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL, 1},
221 { 0, },
222};
223
224static struct pci_driver ata_generic_pci_driver = {
225 .name = DRV_NAME,
226 .id_table = ata_generic,
227 .probe = ata_generic_init_one,
228 .remove = ata_pci_remove_one
229};
230
231static int __init ata_generic_init(void)
232{
233 return pci_module_init(&ata_generic_pci_driver);
234}
235
236
237static void __exit ata_generic_exit(void)
238{
239 pci_unregister_driver(&ata_generic_pci_driver);
240}
241
242
243MODULE_AUTHOR("Alan Cox");
244MODULE_DESCRIPTION("low-level driver for generic ATA");
245MODULE_LICENSE("GPL");
246MODULE_DEVICE_TABLE(pci, ata_generic);
247MODULE_VERSION(DRV_VERSION);
248
249module_init(ata_generic_init);
250module_exit(ata_generic_exit);
251
252module_param(all_generic_ide, int, 0);
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 22b2dba90b9..12b3a42fb35 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -93,7 +93,7 @@
93#include <linux/libata.h> 93#include <linux/libata.h>
94 94
95#define DRV_NAME "ata_piix" 95#define DRV_NAME "ata_piix"
96#define DRV_VERSION "2.00" 96#define DRV_VERSION "2.00ac6"
97 97
98enum { 98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
@@ -116,15 +116,18 @@ enum {
116 PIIX_80C_SEC = (1 << 7) | (1 << 6), 116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117 117
118 /* controller IDs */ 118 /* controller IDs */
119 piix4_pata = 0, 119 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
120 ich5_pata = 1, 120 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
121 ich5_sata = 2, 121 ich_pata_66 = 2, /* ICH up to 66 Mhz */
122 esb_sata = 3, 122 ich_pata_100 = 3, /* ICH up to UDMA 100 */
123 ich6_sata = 4, 123 ich_pata_133 = 4, /* ICH up to UDMA 133 */
124 ich6_sata_ahci = 5, 124 ich5_sata = 5,
125 ich6m_sata_ahci = 6, 125 esb_sata = 6,
126 ich8_sata_ahci = 7, 126 ich6_sata = 7,
127 127 ich6_sata_ahci = 8,
128 ich6m_sata_ahci = 9,
129 ich8_sata_ahci = 10,
130
128 /* constants for mapping table */ 131 /* constants for mapping table */
129 P0 = 0, /* port 0 */ 132 P0 = 0, /* port 0 */
130 P1 = 1, /* port 1 */ 133 P1 = 1, /* port 1 */
@@ -152,19 +155,54 @@ struct piix_host_priv {
152static int piix_init_one (struct pci_dev *pdev, 155static int piix_init_one (struct pci_dev *pdev,
153 const struct pci_device_id *ent); 156 const struct pci_device_id *ent);
154static void piix_host_stop(struct ata_host *host); 157static void piix_host_stop(struct ata_host *host);
155static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
156static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
157static void piix_pata_error_handler(struct ata_port *ap); 158static void piix_pata_error_handler(struct ata_port *ap);
159static void ich_pata_error_handler(struct ata_port *ap);
158static void piix_sata_error_handler(struct ata_port *ap); 160static void piix_sata_error_handler(struct ata_port *ap);
161static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
162static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
163static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
159 164
160static unsigned int in_module_init = 1; 165static unsigned int in_module_init = 1;
161 166
162static const struct pci_device_id piix_pci_tbl[] = { 167static const struct pci_device_id piix_pci_tbl[] = {
163#ifdef ATA_ENABLE_PATA 168#ifdef ATA_ENABLE_PATA
164 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata }, 169 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
165 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, 170 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
166 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, 171 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
167 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, 172 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
173 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
174 /* Intel PIIX4 */
175 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
176 /* Intel PIIX4 */
177 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178 /* Intel PIIX */
179 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 /* Intel ICH (i810, i815, i840) UDMA 66*/
181 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
182 /* Intel ICH0 : UDMA 33*/
183 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
184 /* Intel ICH2M */
185 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
186 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
187 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* Intel ICH3M */
189 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190 /* Intel ICH3 (E7500/1) UDMA 100 */
191 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
193 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH5 */
196 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
197 /* C-ICH (i810E2) */
198 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
200 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* ICH6 (and 6) (i915) UDMA 100 */
202 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* ICH7/7-R (i945, i975) UDMA 100*/
204 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
205 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
168#endif 206#endif
169 207
170 /* NOTE: The following PCI ids must be kept in sync with the 208 /* NOTE: The following PCI ids must be kept in sync with the
@@ -263,6 +301,39 @@ static const struct ata_port_operations piix_pata_ops = {
263 .host_stop = piix_host_stop, 301 .host_stop = piix_host_stop,
264}; 302};
265 303
304static const struct ata_port_operations ich_pata_ops = {
305 .port_disable = ata_port_disable,
306 .set_piomode = piix_set_piomode,
307 .set_dmamode = ich_set_dmamode,
308 .mode_filter = ata_pci_default_filter,
309
310 .tf_load = ata_tf_load,
311 .tf_read = ata_tf_read,
312 .check_status = ata_check_status,
313 .exec_command = ata_exec_command,
314 .dev_select = ata_std_dev_select,
315
316 .bmdma_setup = ata_bmdma_setup,
317 .bmdma_start = ata_bmdma_start,
318 .bmdma_stop = ata_bmdma_stop,
319 .bmdma_status = ata_bmdma_status,
320 .qc_prep = ata_qc_prep,
321 .qc_issue = ata_qc_issue_prot,
322 .data_xfer = ata_pio_data_xfer,
323
324 .freeze = ata_bmdma_freeze,
325 .thaw = ata_bmdma_thaw,
326 .error_handler = ich_pata_error_handler,
327 .post_internal_cmd = ata_bmdma_post_internal_cmd,
328
329 .irq_handler = ata_interrupt,
330 .irq_clear = ata_bmdma_irq_clear,
331
332 .port_start = ata_port_start,
333 .port_stop = ata_port_stop,
334 .host_stop = ata_host_stop,
335};
336
266static const struct ata_port_operations piix_sata_ops = { 337static const struct ata_port_operations piix_sata_ops = {
267 .port_disable = ata_port_disable, 338 .port_disable = ata_port_disable,
268 339
@@ -359,35 +430,56 @@ static const struct piix_map_db *piix_map_db_table[] = {
359}; 430};
360 431
361static struct ata_port_info piix_port_info[] = { 432static struct ata_port_info piix_port_info[] = {
362 /* piix4_pata */ 433 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
363 { 434 {
364 .sht = &piix_sht, 435 .sht = &piix_sht,
365 .flags = ATA_FLAG_SLAVE_POSS, 436 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
366 .pio_mask = 0x1f, /* pio0-4 */ 437 .pio_mask = 0x1f, /* pio0-4 */
367#if 0 438 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
368 .mwdma_mask = 0x06, /* mwdma1-2 */
369#else
370 .mwdma_mask = 0x00, /* mwdma broken */
371#endif
372 .udma_mask = ATA_UDMA_MASK_40C, 439 .udma_mask = ATA_UDMA_MASK_40C,
373 .port_ops = &piix_pata_ops, 440 .port_ops = &piix_pata_ops,
374 }, 441 },
375 442
376 /* ich5_pata */ 443 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
444 {
445 .sht = &piix_sht,
446 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
447 .pio_mask = 0x1f, /* pio 0-4 */
448 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
449 .udma_mask = ATA_UDMA2, /* UDMA33 */
450 .port_ops = &ich_pata_ops,
451 },
452 /* ich_pata_66: 2 ICH controllers up to 66MHz */
377 { 453 {
378 .sht = &piix_sht, 454 .sht = &piix_sht,
379 .flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR, 455 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
456 .pio_mask = 0x1f, /* pio 0-4 */
457 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
458 .udma_mask = ATA_UDMA4,
459 .port_ops = &ich_pata_ops,
460 },
461
462 /* ich_pata_100: 3 */
463 {
464 .sht = &piix_sht,
465 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
380 .pio_mask = 0x1f, /* pio0-4 */ 466 .pio_mask = 0x1f, /* pio0-4 */
381#if 0
382 .mwdma_mask = 0x06, /* mwdma1-2 */ 467 .mwdma_mask = 0x06, /* mwdma1-2 */
383#else 468 .udma_mask = ATA_UDMA5, /* udma0-5 */
384 .mwdma_mask = 0x00, /* mwdma broken */ 469 .port_ops = &ich_pata_ops,
385#endif
386 .udma_mask = 0x3f, /* udma0-5 */
387 .port_ops = &piix_pata_ops,
388 }, 470 },
389 471
390 /* ich5_sata */ 472 /* ich_pata_133: 4 ICH with full UDMA6 */
473 {
474 .sht = &piix_sht,
475 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
476 .pio_mask = 0x1f, /* pio 0-4 */
477 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
478 .udma_mask = ATA_UDMA6, /* UDMA133 */
479 .port_ops = &ich_pata_ops,
480 },
481
482 /* ich5_sata: 5 */
391 { 483 {
392 .sht = &piix_sht, 484 .sht = &piix_sht,
393 .flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR | 485 .flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR |
@@ -398,7 +490,7 @@ static struct ata_port_info piix_port_info[] = {
398 .port_ops = &piix_sata_ops, 490 .port_ops = &piix_sata_ops,
399 }, 491 },
400 492
401 /* i6300esb_sata */ 493 /* i6300esb_sata: 6 */
402 { 494 {
403 .sht = &piix_sht, 495 .sht = &piix_sht,
404 .flags = ATA_FLAG_SATA | 496 .flags = ATA_FLAG_SATA |
@@ -409,7 +501,7 @@ static struct ata_port_info piix_port_info[] = {
409 .port_ops = &piix_sata_ops, 501 .port_ops = &piix_sata_ops,
410 }, 502 },
411 503
412 /* ich6_sata */ 504 /* ich6_sata: 7 */
413 { 505 {
414 .sht = &piix_sht, 506 .sht = &piix_sht,
415 .flags = ATA_FLAG_SATA | 507 .flags = ATA_FLAG_SATA |
@@ -420,7 +512,7 @@ static struct ata_port_info piix_port_info[] = {
420 .port_ops = &piix_sata_ops, 512 .port_ops = &piix_sata_ops,
421 }, 513 },
422 514
423 /* ich6_sata_ahci */ 515 /* ich6_sata_ahci:8 */
424 { 516 {
425 .sht = &piix_sht, 517 .sht = &piix_sht,
426 .flags = ATA_FLAG_SATA | 518 .flags = ATA_FLAG_SATA |
@@ -432,7 +524,7 @@ static struct ata_port_info piix_port_info[] = {
432 .port_ops = &piix_sata_ops, 524 .port_ops = &piix_sata_ops,
433 }, 525 },
434 526
435 /* ich6m_sata_ahci */ 527 /* ich6m_sata_ahci: 9 */
436 { 528 {
437 .sht = &piix_sht, 529 .sht = &piix_sht,
438 .flags = ATA_FLAG_SATA | 530 .flags = ATA_FLAG_SATA |
@@ -455,6 +547,7 @@ static struct ata_port_info piix_port_info[] = {
455 .udma_mask = 0x7f, /* udma0-6 */ 547 .udma_mask = 0x7f, /* udma0-6 */
456 .port_ops = &piix_sata_ops, 548 .port_ops = &piix_sata_ops,
457 }, 549 },
550
458}; 551};
459 552
460static struct pci_bits piix_enable_bits[] = { 553static struct pci_bits piix_enable_bits[] = {
@@ -483,7 +576,8 @@ MODULE_PARM_DESC(force_pcs, "force honoring or ignoring PCS to work around "
483 * LOCKING: 576 * LOCKING:
484 * None (inherited from caller). 577 * None (inherited from caller).
485 */ 578 */
486static void piix_pata_cbl_detect(struct ata_port *ap) 579
580static void ich_pata_cbl_detect(struct ata_port *ap)
487{ 581{
488 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 582 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
489 u8 tmp, mask; 583 u8 tmp, mask;
@@ -503,14 +597,12 @@ static void piix_pata_cbl_detect(struct ata_port *ap)
503 597
504cbl40: 598cbl40:
505 ap->cbl = ATA_CBL_PATA40; 599 ap->cbl = ATA_CBL_PATA40;
506 ap->udma_mask &= ATA_UDMA_MASK_40C;
507} 600}
508 601
509/** 602/**
510 * piix_pata_prereset - prereset for PATA host controller 603 * piix_pata_prereset - prereset for PATA host controller
511 * @ap: Target port 604 * @ap: Target port
512 * 605 *
513 * Prereset including cable detection.
514 * 606 *
515 * LOCKING: 607 * LOCKING:
516 * None (inherited from caller). 608 * None (inherited from caller).
@@ -524,9 +616,7 @@ static int piix_pata_prereset(struct ata_port *ap)
524 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK; 616 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
525 return 0; 617 return 0;
526 } 618 }
527 619 ap->cbl = ATA_CBL_PATA40;
528 piix_pata_cbl_detect(ap);
529
530 return ata_std_prereset(ap); 620 return ata_std_prereset(ap);
531} 621}
532 622
@@ -536,6 +626,36 @@ static void piix_pata_error_handler(struct ata_port *ap)
536 ata_std_postreset); 626 ata_std_postreset);
537} 627}
538 628
629
630/**
631 * ich_pata_prereset - prereset for PATA host controller
632 * @ap: Target port
633 *
634 *
635 * LOCKING:
636 * None (inherited from caller).
637 */
638static int ich_pata_prereset(struct ata_port *ap)
639{
640 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
641
642 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
643 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
644 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
645 return 0;
646 }
647
648 ich_pata_cbl_detect(ap);
649
650 return ata_std_prereset(ap);
651}
652
653static void ich_pata_error_handler(struct ata_port *ap)
654{
655 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
656 ata_std_postreset);
657}
658
539/** 659/**
540 * piix_sata_present_mask - determine present mask for SATA host controller 660 * piix_sata_present_mask - determine present mask for SATA host controller
541 * @ap: Target port 661 * @ap: Target port
@@ -637,6 +757,13 @@ static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
637 unsigned int slave_port = 0x44; 757 unsigned int slave_port = 0x44;
638 u16 master_data; 758 u16 master_data;
639 u8 slave_data; 759 u8 slave_data;
760 u8 udma_enable;
761 int control = 0;
762
763 /*
764 * See Intel Document 298600-004 for the timing programing rules
765 * for ICH controllers.
766 */
640 767
641 static const /* ISP RTC */ 768 static const /* ISP RTC */
642 u8 timings[][2] = { { 0, 0 }, 769 u8 timings[][2] = { { 0, 0 },
@@ -645,20 +772,30 @@ static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
645 { 2, 1 }, 772 { 2, 1 },
646 { 2, 3 }, }; 773 { 2, 3 }, };
647 774
775 if (pio >= 2)
776 control |= 1; /* TIME1 enable */
777 if (ata_pio_need_iordy(adev))
778 control |= 2; /* IE enable */
779
780 /* Intel specifies that the PPE functionality is for disk only */
781 if (adev->class == ATA_DEV_ATA)
782 control |= 4; /* PPE enable */
783
648 pci_read_config_word(dev, master_port, &master_data); 784 pci_read_config_word(dev, master_port, &master_data);
649 if (is_slave) { 785 if (is_slave) {
786 /* Enable SITRE (seperate slave timing register) */
650 master_data |= 0x4000; 787 master_data |= 0x4000;
651 /* enable PPE, IE and TIME */ 788 /* enable PPE1, IE1 and TIME1 as needed */
652 master_data |= 0x0070; 789 master_data |= (control << 4);
653 pci_read_config_byte(dev, slave_port, &slave_data); 790 pci_read_config_byte(dev, slave_port, &slave_data);
654 slave_data &= (ap->port_no ? 0x0f : 0xf0); 791 slave_data &= (ap->port_no ? 0x0f : 0xf0);
655 slave_data |= 792 /* Load the timing nibble for this slave */
656 (timings[pio][0] << 2) | 793 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
657 (timings[pio][1] << (ap->port_no ? 4 : 0));
658 } else { 794 } else {
795 /* Master keeps the bits in a different format */
659 master_data &= 0xccf8; 796 master_data &= 0xccf8;
660 /* enable PPE, IE and TIME */ 797 /* Enable PPE, IE and TIME as appropriate */
661 master_data |= 0x0007; 798 master_data |= control;
662 master_data |= 799 master_data |=
663 (timings[pio][0] << 12) | 800 (timings[pio][0] << 12) |
664 (timings[pio][1] << 8); 801 (timings[pio][1] << 8);
@@ -666,13 +803,23 @@ static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
666 pci_write_config_word(dev, master_port, master_data); 803 pci_write_config_word(dev, master_port, master_data);
667 if (is_slave) 804 if (is_slave)
668 pci_write_config_byte(dev, slave_port, slave_data); 805 pci_write_config_byte(dev, slave_port, slave_data);
806
807 /* Ensure the UDMA bit is off - it will be turned back on if
808 UDMA is selected */
809
810 if (ap->udma_mask) {
811 pci_read_config_byte(dev, 0x48, &udma_enable);
812 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
813 pci_write_config_byte(dev, 0x48, udma_enable);
814 }
669} 815}
670 816
671/** 817/**
672 * piix_set_dmamode - Initialize host controller PATA PIO timings 818 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
673 * @ap: Port whose timings we are configuring 819 * @ap: Port whose timings we are configuring
674 * @adev: um 820 * @adev: Drive in question
675 * @udma: udma mode, 0 - 6 821 * @udma: udma mode, 0 - 6
822 * @is_ich: set if the chip is an ICH device
676 * 823 *
677 * Set UDMA mode for device, in host controller PCI config space. 824 * Set UDMA mode for device, in host controller PCI config space.
678 * 825 *
@@ -680,70 +827,140 @@ static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
680 * None (inherited from caller). 827 * None (inherited from caller).
681 */ 828 */
682 829
683static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) 830static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
684{ 831{
685 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
686 struct pci_dev *dev = to_pci_dev(ap->host->dev); 832 struct pci_dev *dev = to_pci_dev(ap->host->dev);
687 u8 maslave = ap->port_no ? 0x42 : 0x40; 833 u8 master_port = ap->port_no ? 0x42 : 0x40;
688 u8 speed = udma; 834 u16 master_data;
689 unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno; 835 u8 speed = adev->dma_mode;
690 int a_speed = 3 << (drive_dn * 4); 836 int devid = adev->devno + 2 * ap->port_no;
691 int u_flag = 1 << drive_dn; 837 u8 udma_enable;
692 int v_flag = 0x01 << drive_dn; 838
693 int w_flag = 0x10 << drive_dn; 839 static const /* ISP RTC */
694 int u_speed = 0; 840 u8 timings[][2] = { { 0, 0 },
695 int sitre; 841 { 0, 0 },
696 u16 reg4042, reg4a; 842 { 1, 0 },
697 u8 reg48, reg54, reg55; 843 { 2, 1 },
698 844 { 2, 3 }, };
699 pci_read_config_word(dev, maslave, &reg4042); 845
700 DPRINTK("reg4042 = 0x%04x\n", reg4042); 846 pci_read_config_word(dev, master_port, &master_data);
701 sitre = (reg4042 & 0x4000) ? 1 : 0; 847 pci_read_config_byte(dev, 0x48, &udma_enable);
702 pci_read_config_byte(dev, 0x48, &reg48);
703 pci_read_config_word(dev, 0x4a, &reg4a);
704 pci_read_config_byte(dev, 0x54, &reg54);
705 pci_read_config_byte(dev, 0x55, &reg55);
706
707 switch(speed) {
708 case XFER_UDMA_4:
709 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
710 case XFER_UDMA_6:
711 case XFER_UDMA_5:
712 case XFER_UDMA_3:
713 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
714 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
715 case XFER_MW_DMA_2:
716 case XFER_MW_DMA_1: break;
717 default:
718 BUG();
719 return;
720 }
721 848
722 if (speed >= XFER_UDMA_0) { 849 if (speed >= XFER_UDMA_0) {
723 if (!(reg48 & u_flag)) 850 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
724 pci_write_config_byte(dev, 0x48, reg48 | u_flag); 851 u16 udma_timing;
725 if (speed == XFER_UDMA_5) { 852 u16 ideconf;
726 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); 853 int u_clock, u_speed;
727 } else { 854
728 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); 855 /*
856 * UDMA is handled by a combination of clock switching and
857 * selection of dividers
858 *
859 * Handy rule: Odd modes are UDMATIMx 01, even are 02
860 * except UDMA0 which is 00
861 */
862 u_speed = min(2 - (udma & 1), udma);
863 if (udma == 5)
864 u_clock = 0x1000; /* 100Mhz */
865 else if (udma > 2)
866 u_clock = 1; /* 66Mhz */
867 else
868 u_clock = 0; /* 33Mhz */
869
870 udma_enable |= (1 << devid);
871
872 /* Load the CT/RP selection */
873 pci_read_config_word(dev, 0x4A, &udma_timing);
874 udma_timing &= ~(3 << (4 * devid));
875 udma_timing |= u_speed << (4 * devid);
876 pci_write_config_word(dev, 0x4A, udma_timing);
877
878 if (isich) {
879 /* Select a 33/66/100Mhz clock */
880 pci_read_config_word(dev, 0x54, &ideconf);
881 ideconf &= ~(0x1001 << devid);
882 ideconf |= u_clock << devid;
883 /* For ICH or later we should set bit 10 for better
884 performance (WR_PingPong_En) */
885 pci_write_config_word(dev, 0x54, ideconf);
729 } 886 }
730 if ((reg4a & a_speed) != u_speed)
731 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
732 if (speed > XFER_UDMA_2) {
733 if (!(reg54 & v_flag))
734 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
735 } else
736 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
737 } else { 887 } else {
738 if (reg48 & u_flag) 888 /*
739 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); 889 * MWDMA is driven by the PIO timings. We must also enable
740 if (reg4a & a_speed) 890 * IORDY unconditionally along with TIME1. PPE has already
741 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); 891 * been set when the PIO timing was set.
742 if (reg54 & v_flag) 892 */
743 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); 893 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
744 if (reg55 & w_flag) 894 unsigned int control;
745 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); 895 u8 slave_data;
896 const unsigned int needed_pio[3] = {
897 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
898 };
899 int pio = needed_pio[mwdma] - XFER_PIO_0;
900
901 control = 3; /* IORDY|TIME1 */
902
903 /* If the drive MWDMA is faster than it can do PIO then
904 we must force PIO into PIO0 */
905
906 if (adev->pio_mode < needed_pio[mwdma])
907 /* Enable DMA timing only */
908 control |= 8; /* PIO cycles in PIO0 */
909
910 if (adev->devno) { /* Slave */
911 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
912 master_data |= control << 4;
913 pci_read_config_byte(dev, 0x44, &slave_data);
914 slave_data &= (0x0F + 0xE1 * ap->port_no);
915 /* Load the matching timing */
916 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
917 pci_write_config_byte(dev, 0x44, slave_data);
918 } else { /* Master */
919 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
920 and master timing bits */
921 master_data |= control;
922 master_data |=
923 (timings[pio][0] << 12) |
924 (timings[pio][1] << 8);
925 }
926 udma_enable &= ~(1 << devid);
927 pci_write_config_word(dev, master_port, master_data);
746 } 928 }
929 /* Don't scribble on 0x48 if the controller does not support UDMA */
930 if (ap->udma_mask)
931 pci_write_config_byte(dev, 0x48, udma_enable);
932}
933
934/**
935 * piix_set_dmamode - Initialize host controller PATA DMA timings
936 * @ap: Port whose timings we are configuring
937 * @adev: um
938 *
939 * Set MW/UDMA mode for device, in host controller PCI config space.
940 *
941 * LOCKING:
942 * None (inherited from caller).
943 */
944
945static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
946{
947 do_pata_set_dmamode(ap, adev, 0);
948}
949
950/**
951 * ich_set_dmamode - Initialize host controller PATA DMA timings
952 * @ap: Port whose timings we are configuring
953 * @adev: um
954 *
955 * Set MW/UDMA mode for device, in host controller PCI config space.
956 *
957 * LOCKING:
958 * None (inherited from caller).
959 */
960
961static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
962{
963 do_pata_set_dmamode(ap, adev, 1);
747} 964}
748 965
749#define AHCI_PCI_BAR 5 966#define AHCI_PCI_BAR 5
@@ -872,7 +1089,7 @@ static void __devinit piix_init_sata_map(struct pci_dev *pdev,
872 1089
873 case IDE: 1090 case IDE:
874 WARN_ON((i & 1) || map[i + 1] != IDE); 1091 WARN_ON((i & 1) || map[i + 1] != IDE);
875 pinfo[i / 2] = piix_port_info[ich5_pata]; 1092 pinfo[i / 2] = piix_port_info[ich_pata_100];
876 pinfo[i / 2].private_data = hpriv; 1093 pinfo[i / 2].private_data = hpriv;
877 i++; 1094 i++;
878 printk(" IDE IDE"); 1095 printk(" IDE IDE");
@@ -1007,4 +1224,3 @@ static void __exit piix_exit(void)
1007 1224
1008module_init(piix_init); 1225module_init(piix_init);
1009module_exit(piix_exit); 1226module_exit(piix_exit);
1010
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c
new file mode 100644
index 00000000000..0e0415ecfce
--- /dev/null
+++ b/drivers/ata/pata_ali.c
@@ -0,0 +1,679 @@
1/*
2 * pata_ali.c - ALI 15x3 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based in part upon
7 * linux/drivers/ide/pci/alim15x3.c Version 0.17 2003/01/02
8 *
9 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
10 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
11 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
12 *
13 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
14 * May be copied or modified under the terms of the GNU General Public License
15 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
16 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
17 *
18 * Documentation
19 * Chipset documentation available under NDA only
20 *
21 * TODO/CHECK
22 * Cannot have ATAPI on both master & slave for rev < c2 (???) but
23 * otherwise should do atapi DMA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/dmi.h>
35
36#define DRV_NAME "pata_ali"
37#define DRV_VERSION "0.6.5"
38
39/*
40 * Cable special cases
41 */
42
43static struct dmi_system_id cable_dmi_table[] = {
44 {
45 .ident = "HP Pavilion N5430",
46 .matches = {
47 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
48 DMI_MATCH(DMI_BOARD_NAME, "OmniBook N32N-736"),
49 },
50 },
51 { }
52};
53
54static int ali_cable_override(struct pci_dev *pdev)
55{
56 /* Fujitsu P2000 */
57 if (pdev->subsystem_vendor == 0x10CF && pdev->subsystem_device == 0x10AF)
58 return 1;
59 /* Systems by DMI */
60 if (dmi_check_system(cable_dmi_table))
61 return 1;
62 return 0;
63}
64
65/**
66 * ali_c2_cable_detect - cable detection
67 * @ap: ATA port
68 *
69 * Perform cable detection for C2 and later revisions
70 */
71
72static int ali_c2_cable_detect(struct ata_port *ap)
73{
74 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
75 u8 ata66;
76
77 /* Certain laptops use short but suitable cables and don't
78 implement the detect logic */
79
80 if (ali_cable_override(pdev))
81 return ATA_CBL_PATA80;
82
83 /* Host view cable detect 0x4A bit 0 primary bit 1 secondary
84 Bit set for 40 pin */
85 pci_read_config_byte(pdev, 0x4A, &ata66);
86 if (ata66 & (1 << ap->port_no))
87 return ATA_CBL_PATA40;
88 else
89 return ATA_CBL_PATA80;
90}
91
92/**
93 * ali_early_error_handler - reset for eary chip
94 * @ap: ATA port
95 *
96 * Handle the reset callback for the later chips with cable detect
97 */
98
99static int ali_c2_pre_reset(struct ata_port *ap)
100{
101 ap->cbl = ali_c2_cable_detect(ap);
102 return ata_std_prereset(ap);
103}
104
105static void ali_c2_error_handler(struct ata_port *ap)
106{
107 ata_bmdma_drive_eh(ap, ali_c2_pre_reset,
108 ata_std_softreset, NULL,
109 ata_std_postreset);
110}
111
112/**
113 * ali_early_cable_detect - cable detection
114 * @ap: ATA port
115 *
116 * Perform cable detection for older chipsets. This turns out to be
117 * rather easy to implement
118 */
119
120static int ali_early_cable_detect(struct ata_port *ap)
121{
122 return ATA_CBL_PATA40;
123}
124
125/**
126 * ali_early_probe_init - reset for early chip
127 * @ap: ATA port
128 *
129 * Handle the reset callback for the early (pre cable detect) chips.
130 */
131
132static int ali_early_pre_reset(struct ata_port *ap)
133{
134 ap->cbl = ali_early_cable_detect(ap);
135 return ata_std_prereset(ap);
136}
137
138static void ali_early_error_handler(struct ata_port *ap)
139{
140 return ata_bmdma_drive_eh(ap, ali_early_pre_reset,
141 ata_std_softreset, NULL,
142 ata_std_postreset);
143}
144
145/**
146 * ali_20_filter - filter for earlier ALI DMA
147 * @ap: ALi ATA port
148 * @adev: attached device
149 *
150 * Ensure that we do not do DMA on CD devices. We may be able to
151 * fix that later on. Also ensure we do not do UDMA on WDC drives
152 */
153
154static unsigned long ali_20_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
155{
156 char model_num[40];
157 /* No DMA on anything but a disk for now */
158 if (adev->class != ATA_DEV_ATA)
159 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
160 ata_id_string(adev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
161 if (strstr(model_num, "WDC"))
162 return mask &= ~ATA_MASK_UDMA;
163 return ata_pci_default_filter(ap, adev, mask);
164}
165
166/**
167 * ali_fifo_control - FIFO manager
168 * @ap: ALi channel to control
169 * @adev: device for FIFO control
170 * @on: 0 for off 1 for on
171 *
172 * Enable or disable the FIFO on a given device. Because of the way the
173 * ALi FIFO works it provides a boost on ATA disk but can be confused by
174 * ATAPI and we must therefore manage it.
175 */
176
177static void ali_fifo_control(struct ata_port *ap, struct ata_device *adev, int on)
178{
179 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
180 int pio_fifo = 0x54 + ap->port_no;
181 u8 fifo;
182 int shift = 4 * adev->devno;
183
184 /* ATA - FIFO on set nibble to 0x05, ATAPI - FIFO off, set nibble to
185 0x00. Not all the docs agree but the behaviour we now use is the
186 one stated in the BIOS Programming Guide */
187
188 pci_read_config_byte(pdev, pio_fifo, &fifo);
189 fifo &= ~(0x0F << shift);
190 if (on)
191 fifo |= (on << shift);
192 pci_write_config_byte(pdev, pio_fifo, fifo);
193}
194
195/**
196 * ali_program_modes - load mode registers
197 * @ap: ALi channel to load
198 * @adev: Device the timing is for
199 * @cmd: Command timing
200 * @data: Data timing
201 * @ultra: UDMA timing or zero for off
202 *
203 * Loads the timing registers for cmd/data and disable UDMA if
204 * ultra is zero. If ultra is set then load and enable the UDMA
205 * timing but do not touch the command/data timing.
206 */
207
208static void ali_program_modes(struct ata_port *ap, struct ata_device *adev, struct ata_timing *t, u8 ultra)
209{
210 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
211 int cas = 0x58 + 4 * ap->port_no; /* Command timing */
212 int cbt = 0x59 + 4 * ap->port_no; /* Command timing */
213 int drwt = 0x5A + 4 * ap->port_no + adev->devno; /* R/W timing */
214 int udmat = 0x56 + ap->port_no; /* UDMA timing */
215 int shift = 4 * adev->devno;
216 u8 udma;
217
218 if (t != NULL) {
219 t->setup = FIT(t->setup, 1, 8) & 7;
220 t->act8b = FIT(t->act8b, 1, 8) & 7;
221 t->rec8b = FIT(t->rec8b, 1, 16) & 15;
222 t->active = FIT(t->active, 1, 8) & 7;
223 t->recover = FIT(t->recover, 1, 16) & 15;
224
225 pci_write_config_byte(pdev, cas, t->setup);
226 pci_write_config_byte(pdev, cbt, (t->act8b << 4) | t->rec8b);
227 pci_write_config_byte(pdev, drwt, (t->active << 4) | t->recover);
228 }
229
230 /* Set up the UDMA enable */
231 pci_read_config_byte(pdev, udmat, &udma);
232 udma &= ~(0x0F << shift);
233 udma |= ultra << shift;
234 pci_write_config_byte(pdev, udmat, udma);
235}
236
237/**
238 * ali_set_piomode - set initial PIO mode data
239 * @ap: ATA interface
240 * @adev: ATA device
241 *
242 * Program the ALi registers for PIO mode. FIXME: add timings for
243 * PIO5.
244 */
245
246static void ali_set_piomode(struct ata_port *ap, struct ata_device *adev)
247{
248 struct ata_device *pair = ata_dev_pair(adev);
249 struct ata_timing t;
250 unsigned long T = 1000000000 / 33333; /* PCI clock based */
251
252 ata_timing_compute(adev, adev->pio_mode, &t, T, 1);
253 if (pair) {
254 struct ata_timing p;
255 ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
256 ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
257 if (pair->dma_mode) {
258 ata_timing_compute(pair, pair->dma_mode, &p, T, 1);
259 ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
260 }
261 }
262
263 /* PIO FIFO is only permitted on ATA disk */
264 if (adev->class != ATA_DEV_ATA)
265 ali_fifo_control(ap, adev, 0x00);
266 ali_program_modes(ap, adev, &t, 0);
267 if (adev->class == ATA_DEV_ATA)
268 ali_fifo_control(ap, adev, 0x05);
269
270}
271
272/**
273 * ali_set_dmamode - set initial DMA mode data
274 * @ap: ATA interface
275 * @adev: ATA device
276 *
277 * FIXME: MWDMA timings
278 */
279
280static void ali_set_dmamode(struct ata_port *ap, struct ata_device *adev)
281{
282 static u8 udma_timing[7] = { 0xC, 0xB, 0xA, 0x9, 0x8, 0xF, 0xD };
283 struct ata_device *pair = ata_dev_pair(adev);
284 struct ata_timing t;
285 unsigned long T = 1000000000 / 33333; /* PCI clock based */
286 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
287
288
289 if (adev->class == ATA_DEV_ATA)
290 ali_fifo_control(ap, adev, 0x08);
291
292 if (adev->dma_mode >= XFER_UDMA_0) {
293 ali_program_modes(ap, adev, NULL, udma_timing[adev->dma_mode - XFER_UDMA_0]);
294 if (adev->dma_mode >= XFER_UDMA_3) {
295 u8 reg4b;
296 pci_read_config_byte(pdev, 0x4B, &reg4b);
297 reg4b |= 1;
298 pci_write_config_byte(pdev, 0x4B, reg4b);
299 }
300 } else {
301 ata_timing_compute(adev, adev->dma_mode, &t, T, 1);
302 if (pair) {
303 struct ata_timing p;
304 ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
305 ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
306 if (pair->dma_mode) {
307 ata_timing_compute(pair, pair->dma_mode, &p, T, 1);
308 ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
309 }
310 }
311 ali_program_modes(ap, adev, &t, 0);
312 }
313}
314
315/**
316 * ali_lock_sectors - Keep older devices to 255 sector mode
317 * @ap: ATA port
318 * @adev: Device
319 *
320 * Called during the bus probe for each device that is found. We use
321 * this call to lock the sector count of the device to 255 or less on
322 * older ALi controllers. If we didn't do this then large I/O's would
323 * require LBA48 commands which the older ALi requires are issued by
324 * slower PIO methods
325 */
326
327static void ali_lock_sectors(struct ata_port *ap, struct ata_device *adev)
328{
329 adev->max_sectors = 255;
330}
331
332static struct scsi_host_template ali_sht = {
333 .module = THIS_MODULE,
334 .name = DRV_NAME,
335 .ioctl = ata_scsi_ioctl,
336 .queuecommand = ata_scsi_queuecmd,
337 .can_queue = ATA_DEF_QUEUE,
338 .this_id = ATA_SHT_THIS_ID,
339 .sg_tablesize = LIBATA_MAX_PRD,
340 /* Keep LBA28 counts so large I/O's don't turn LBA48 and PIO
341 with older controllers. Not locked so will grow on C5 or later */
342 .max_sectors = 255,
343 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
344 .emulated = ATA_SHT_EMULATED,
345 .use_clustering = ATA_SHT_USE_CLUSTERING,
346 .proc_name = DRV_NAME,
347 .dma_boundary = ATA_DMA_BOUNDARY,
348 .slave_configure = ata_scsi_slave_config,
349 .bios_param = ata_std_bios_param,
350};
351
352/*
353 * Port operations for PIO only ALi
354 */
355
356static struct ata_port_operations ali_early_port_ops = {
357 .port_disable = ata_port_disable,
358 .set_piomode = ali_set_piomode,
359 .tf_load = ata_tf_load,
360 .tf_read = ata_tf_read,
361 .check_status = ata_check_status,
362 .exec_command = ata_exec_command,
363 .dev_select = ata_std_dev_select,
364
365 .freeze = ata_bmdma_freeze,
366 .thaw = ata_bmdma_thaw,
367 .error_handler = ali_early_error_handler,
368 .post_internal_cmd = ata_bmdma_post_internal_cmd,
369
370 .qc_prep = ata_qc_prep,
371 .qc_issue = ata_qc_issue_prot,
372 .eng_timeout = ata_eng_timeout,
373 .data_xfer = ata_pio_data_xfer,
374
375 .irq_handler = ata_interrupt,
376 .irq_clear = ata_bmdma_irq_clear,
377
378 .port_start = ata_port_start,
379 .port_stop = ata_port_stop,
380 .host_stop = ata_host_stop
381};
382
383/*
384 * Port operations for DMA capable ALi without cable
385 * detect
386 */
387static struct ata_port_operations ali_20_port_ops = {
388 .port_disable = ata_port_disable,
389
390 .set_piomode = ali_set_piomode,
391 .set_dmamode = ali_set_dmamode,
392 .mode_filter = ali_20_filter,
393
394 .tf_load = ata_tf_load,
395 .tf_read = ata_tf_read,
396 .check_status = ata_check_status,
397 .exec_command = ata_exec_command,
398 .dev_select = ata_std_dev_select,
399 .dev_config = ali_lock_sectors,
400
401 .freeze = ata_bmdma_freeze,
402 .thaw = ata_bmdma_thaw,
403 .error_handler = ali_early_error_handler,
404 .post_internal_cmd = ata_bmdma_post_internal_cmd,
405
406 .bmdma_setup = ata_bmdma_setup,
407 .bmdma_start = ata_bmdma_start,
408 .bmdma_stop = ata_bmdma_stop,
409 .bmdma_status = ata_bmdma_status,
410
411 .qc_prep = ata_qc_prep,
412 .qc_issue = ata_qc_issue_prot,
413 .eng_timeout = ata_eng_timeout,
414 .data_xfer = ata_pio_data_xfer,
415
416 .irq_handler = ata_interrupt,
417 .irq_clear = ata_bmdma_irq_clear,
418
419 .port_start = ata_port_start,
420 .port_stop = ata_port_stop,
421 .host_stop = ata_host_stop
422};
423
424/*
425 * Port operations for DMA capable ALi with cable detect
426 */
427static struct ata_port_operations ali_c2_port_ops = {
428 .port_disable = ata_port_disable,
429 .set_piomode = ali_set_piomode,
430 .set_dmamode = ali_set_dmamode,
431 .mode_filter = ata_pci_default_filter,
432 .tf_load = ata_tf_load,
433 .tf_read = ata_tf_read,
434 .check_status = ata_check_status,
435 .exec_command = ata_exec_command,
436 .dev_select = ata_std_dev_select,
437 .dev_config = ali_lock_sectors,
438
439 .freeze = ata_bmdma_freeze,
440 .thaw = ata_bmdma_thaw,
441 .error_handler = ali_c2_error_handler,
442 .post_internal_cmd = ata_bmdma_post_internal_cmd,
443
444 .bmdma_setup = ata_bmdma_setup,
445 .bmdma_start = ata_bmdma_start,
446 .bmdma_stop = ata_bmdma_stop,
447 .bmdma_status = ata_bmdma_status,
448
449 .qc_prep = ata_qc_prep,
450 .qc_issue = ata_qc_issue_prot,
451 .eng_timeout = ata_eng_timeout,
452 .data_xfer = ata_pio_data_xfer,
453
454 .irq_handler = ata_interrupt,
455 .irq_clear = ata_bmdma_irq_clear,
456
457 .port_start = ata_port_start,
458 .port_stop = ata_port_stop,
459 .host_stop = ata_host_stop
460};
461
462/*
463 * Port operations for DMA capable ALi with cable detect and LBA48
464 */
465static struct ata_port_operations ali_c5_port_ops = {
466 .port_disable = ata_port_disable,
467 .set_piomode = ali_set_piomode,
468 .set_dmamode = ali_set_dmamode,
469 .mode_filter = ata_pci_default_filter,
470 .tf_load = ata_tf_load,
471 .tf_read = ata_tf_read,
472 .check_status = ata_check_status,
473 .exec_command = ata_exec_command,
474 .dev_select = ata_std_dev_select,
475
476 .freeze = ata_bmdma_freeze,
477 .thaw = ata_bmdma_thaw,
478 .error_handler = ali_c2_error_handler,
479 .post_internal_cmd = ata_bmdma_post_internal_cmd,
480
481 .bmdma_setup = ata_bmdma_setup,
482 .bmdma_start = ata_bmdma_start,
483 .bmdma_stop = ata_bmdma_stop,
484 .bmdma_status = ata_bmdma_status,
485
486 .qc_prep = ata_qc_prep,
487 .qc_issue = ata_qc_issue_prot,
488 .eng_timeout = ata_eng_timeout,
489 .data_xfer = ata_pio_data_xfer,
490
491 .irq_handler = ata_interrupt,
492 .irq_clear = ata_bmdma_irq_clear,
493
494 .port_start = ata_port_start,
495 .port_stop = ata_port_stop,
496 .host_stop = ata_host_stop
497};
498
499/**
500 * ali_init_one - discovery callback
501 * @pdev: PCI device ID
502 * @id: PCI table info
503 *
504 * An ALi IDE interface has been discovered. Figure out what revision
505 * and perform configuration work before handing it to the ATA layer
506 */
507
508static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
509{
510 static struct ata_port_info info_early = {
511 .sht = &ali_sht,
512 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
513 .pio_mask = 0x1f,
514 .port_ops = &ali_early_port_ops
515 };
516 /* Revision 0x20 added DMA */
517 static struct ata_port_info info_20 = {
518 .sht = &ali_sht,
519 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
520 .pio_mask = 0x1f,
521 .mwdma_mask = 0x07,
522 .port_ops = &ali_20_port_ops
523 };
524 /* Revision 0x20 with support logic added UDMA */
525 static struct ata_port_info info_20_udma = {
526 .sht = &ali_sht,
527 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
528 .pio_mask = 0x1f,
529 .mwdma_mask = 0x07,
530 .udma_mask = 0x07, /* UDMA33 */
531 .port_ops = &ali_20_port_ops
532 };
533 /* Revision 0xC2 adds UDMA66 */
534 static struct ata_port_info info_c2 = {
535 .sht = &ali_sht,
536 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
537 .pio_mask = 0x1f,
538 .mwdma_mask = 0x07,
539 .udma_mask = 0x1f,
540 .port_ops = &ali_c2_port_ops
541 };
542 /* Revision 0xC3 is UDMA100 */
543 static struct ata_port_info info_c3 = {
544 .sht = &ali_sht,
545 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
546 .pio_mask = 0x1f,
547 .mwdma_mask = 0x07,
548 .udma_mask = 0x3f,
549 .port_ops = &ali_c2_port_ops
550 };
551 /* Revision 0xC4 is UDMA133 */
552 static struct ata_port_info info_c4 = {
553 .sht = &ali_sht,
554 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
555 .pio_mask = 0x1f,
556 .mwdma_mask = 0x07,
557 .udma_mask = 0x7f,
558 .port_ops = &ali_c2_port_ops
559 };
560 /* Revision 0xC5 is UDMA133 with LBA48 DMA */
561 static struct ata_port_info info_c5 = {
562 .sht = &ali_sht,
563 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
564 .pio_mask = 0x1f,
565 .mwdma_mask = 0x07,
566 .udma_mask = 0x7f,
567 .port_ops = &ali_c5_port_ops
568 };
569
570 static struct ata_port_info *port_info[2];
571 u8 rev, tmp;
572 struct pci_dev *north, *isa_bridge;
573
574 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
575
576 /*
577 * The chipset revision selects the driver operations and
578 * mode data.
579 */
580
581 if (rev < 0x20) {
582 port_info[0] = port_info[1] = &info_early;
583 } else if (rev < 0xC2) {
584 /* 1543-E/F, 1543C-C, 1543C-D, 1543C-E */
585 pci_read_config_byte(pdev, 0x4B, &tmp);
586 /* Clear CD-ROM DMA write bit */
587 tmp &= 0x7F;
588 pci_write_config_byte(pdev, 0x4B, tmp);
589 port_info[0] = port_info[1] = &info_20;
590 } else if (rev == 0xC2) {
591 port_info[0] = port_info[1] = &info_c2;
592 } else if (rev == 0xC3) {
593 port_info[0] = port_info[1] = &info_c3;
594 } else if (rev == 0xC4) {
595 port_info[0] = port_info[1] = &info_c4;
596 } else
597 port_info[0] = port_info[1] = &info_c5;
598
599 if (rev >= 0xC2) {
600 /* Enable cable detection logic */
601 pci_read_config_byte(pdev, 0x4B, &tmp);
602 pci_write_config_byte(pdev, 0x4B, tmp | 0x08);
603 }
604
605 north = pci_get_slot(pdev->bus, PCI_DEVFN(0,0));
606 isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
607
608 if (north && north->vendor == PCI_VENDOR_ID_AL) {
609 /* Configure the ALi bridge logic. For non ALi rely on BIOS.
610 Set the south bridge enable bit */
611 pci_read_config_byte(isa_bridge, 0x79, &tmp);
612 if (rev == 0xC2)
613 pci_write_config_byte(isa_bridge, 0x79, tmp | 0x04);
614 else if (rev > 0xC2)
615 pci_write_config_byte(isa_bridge, 0x79, tmp | 0x02);
616 }
617
618 if (rev >= 0x20) {
619 if (rev < 0xC2) {
620 /* Are we paired with a UDMA capable chip */
621 pci_read_config_byte(isa_bridge, 0x5E, &tmp);
622 if ((tmp & 0x1E) == 0x12)
623 port_info[0] = port_info[1] = &info_20_udma;
624 }
625 /*
626 * CD_ROM DMA on (0x53 bit 0). Enable this even if we want
627 * to use PIO. 0x53 bit 1 (rev 20 only) - enable FIFO control
628 * via 0x54/55.
629 */
630 pci_read_config_byte(pdev, 0x53, &tmp);
631 if (rev <= 0x20)
632 tmp &= ~0x02;
633 if (rev == 0xc7)
634 tmp |= 0x03;
635 else
636 tmp |= 0x01; /* CD_ROM enable for DMA */
637 pci_write_config_byte(pdev, 0x53, tmp);
638 }
639
640 pci_dev_put(isa_bridge);
641 pci_dev_put(north);
642
643 ata_pci_clear_simplex(pdev);
644 return ata_pci_init_one(pdev, port_info, 2);
645}
646
647static struct pci_device_id ali[] = {
648 { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228), },
649 { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229), },
650 { 0, },
651};
652
653static struct pci_driver ali_pci_driver = {
654 .name = DRV_NAME,
655 .id_table = ali,
656 .probe = ali_init_one,
657 .remove = ata_pci_remove_one
658};
659
660static int __init ali_init(void)
661{
662 return pci_register_driver(&ali_pci_driver);
663}
664
665
666static void __exit ali_exit(void)
667{
668 pci_unregister_driver(&ali_pci_driver);
669}
670
671
672MODULE_AUTHOR("Alan Cox");
673MODULE_DESCRIPTION("low-level driver for ALi PATA");
674MODULE_LICENSE("GPL");
675MODULE_DEVICE_TABLE(pci, ali);
676MODULE_VERSION(DRV_VERSION);
677
678module_init(ali_init);
679module_exit(ali_exit);
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
new file mode 100644
index 00000000000..6ab568428a1
--- /dev/null
+++ b/drivers/ata/pata_amd.c
@@ -0,0 +1,707 @@
1/*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
9 *
10 * TODO:
11 * Variable system clock when/if it makes sense
12 * Power management on ports
13 *
14 *
15 * Documentation publically available.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_amd"
28#define DRV_VERSION "0.2.2"
29
30/**
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
37 *
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
42 */
43
44static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
45{
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
48 };
49
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
54 int T, UT;
55 const int amd_clock = 33333; /* KHz. */
56 u8 t;
57
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
60
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
63 return;
64 }
65
66 if (peer) {
67 /* This may be over conservative */
68 if (peer->dma_mode) {
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
71 }
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 }
75
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
78
79 /*
80 * Now do the setup work
81 */
82
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
87
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
91
92 /* Drive timing */
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
95
96 switch (clock) {
97 case 1:
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
99 break;
100
101 case 2:
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
103 break;
104
105 case 3:
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
107 break;
108
109 case 4:
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
111 break;
112
113 default:
114 return;
115 }
116
117 /* UDMA timing */
118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
119}
120
121/**
122 * amd_probe_init - cable detection
123 * @ap: ATA port
124 *
125 * Perform cable detection. The BIOS stores this in PCI config
126 * space for us.
127 */
128
129static int amd_pre_reset(struct ata_port *ap)
130{
131 static const u32 bitmask[2] = {0x03, 0xC0};
132 static const struct pci_bits amd_enable_bits[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
135 };
136
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
138 u8 ata66;
139
140 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) {
141 ata_port_disable(ap);
142 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
143 return 0;
144 }
145
146 pci_read_config_byte(pdev, 0x42, &ata66);
147 if (ata66 & bitmask[ap->port_no])
148 ap->cbl = ATA_CBL_PATA80;
149 else
150 ap->cbl = ATA_CBL_PATA40;
151 return ata_std_prereset(ap);
152
153}
154
155static void amd_error_handler(struct ata_port *ap)
156{
157 return ata_bmdma_drive_eh(ap, amd_pre_reset,
158 ata_std_softreset, NULL,
159 ata_std_postreset);
160}
161
162static int amd_early_pre_reset(struct ata_port *ap)
163{
164 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
165 static struct pci_bits amd_enable_bits[] = {
166 { 0x40, 1, 0x02, 0x02 },
167 { 0x40, 1, 0x01, 0x01 }
168 };
169
170 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) {
171 ata_port_disable(ap);
172 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
173 return 0;
174 }
175 /* No host side cable detection */
176 ap->cbl = ATA_CBL_PATA80;
177 return ata_std_prereset(ap);
178
179}
180
181static void amd_early_error_handler(struct ata_port *ap)
182{
183 ata_bmdma_drive_eh(ap, amd_early_pre_reset,
184 ata_std_softreset, NULL,
185 ata_std_postreset);
186}
187
188/**
189 * amd33_set_piomode - set initial PIO mode data
190 * @ap: ATA interface
191 * @adev: ATA device
192 *
193 * Program the AMD registers for PIO mode.
194 */
195
196static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
197{
198 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
199}
200
201static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
202{
203 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
204}
205
206static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
207{
208 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
209}
210
211static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
212{
213 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
214}
215
216/**
217 * amd33_set_dmamode - set initial DMA mode data
218 * @ap: ATA interface
219 * @adev: ATA device
220 *
221 * Program the MWDMA/UDMA modes for the AMD and Nvidia
222 * chipset.
223 */
224
225static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
226{
227 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
228}
229
230static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
231{
232 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
233}
234
235static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
236{
237 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
238}
239
240static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
241{
242 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
243}
244
245
246/**
247 * nv_probe_init - cable detection
248 * @ap: ATA port
249 *
250 * Perform cable detection. The BIOS stores this in PCI config
251 * space for us.
252 */
253
254static int nv_pre_reset(struct ata_port *ap) {
255 static const u8 bitmask[2] = {0x03, 0xC0};
256
257 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
258 u8 ata66;
259 u16 udma;
260
261 pci_read_config_byte(pdev, 0x52, &ata66);
262 if (ata66 & bitmask[ap->port_no])
263 ap->cbl = ATA_CBL_PATA80;
264 else
265 ap->cbl = ATA_CBL_PATA40;
266
267 /* We now have to double check because the Nvidia boxes BIOS
268 doesn't always set the cable bits but does set mode bits */
269
270 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
271 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
272 ap->cbl = ATA_CBL_PATA80;
273 return ata_std_prereset(ap);
274}
275
276static void nv_error_handler(struct ata_port *ap)
277{
278 ata_bmdma_drive_eh(ap, nv_pre_reset,
279 ata_std_softreset, NULL,
280 ata_std_postreset);
281}
282/**
283 * nv100_set_piomode - set initial PIO mode data
284 * @ap: ATA interface
285 * @adev: ATA device
286 *
287 * Program the AMD registers for PIO mode.
288 */
289
290static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
291{
292 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
293}
294
295static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
296{
297 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
298}
299
300/**
301 * nv100_set_dmamode - set initial DMA mode data
302 * @ap: ATA interface
303 * @adev: ATA device
304 *
305 * Program the MWDMA/UDMA modes for the AMD and Nvidia
306 * chipset.
307 */
308
309static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
310{
311 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
312}
313
314static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
315{
316 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
317}
318
319static struct scsi_host_template amd_sht = {
320 .module = THIS_MODULE,
321 .name = DRV_NAME,
322 .ioctl = ata_scsi_ioctl,
323 .queuecommand = ata_scsi_queuecmd,
324 .can_queue = ATA_DEF_QUEUE,
325 .this_id = ATA_SHT_THIS_ID,
326 .sg_tablesize = LIBATA_MAX_PRD,
327 .max_sectors = ATA_MAX_SECTORS,
328 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
329 .emulated = ATA_SHT_EMULATED,
330 .use_clustering = ATA_SHT_USE_CLUSTERING,
331 .proc_name = DRV_NAME,
332 .dma_boundary = ATA_DMA_BOUNDARY,
333 .slave_configure = ata_scsi_slave_config,
334 .bios_param = ata_std_bios_param,
335};
336
337static struct ata_port_operations amd33_port_ops = {
338 .port_disable = ata_port_disable,
339 .set_piomode = amd33_set_piomode,
340 .set_dmamode = amd33_set_dmamode,
341 .mode_filter = ata_pci_default_filter,
342 .tf_load = ata_tf_load,
343 .tf_read = ata_tf_read,
344 .check_status = ata_check_status,
345 .exec_command = ata_exec_command,
346 .dev_select = ata_std_dev_select,
347
348 .freeze = ata_bmdma_freeze,
349 .thaw = ata_bmdma_thaw,
350 .error_handler = amd_early_error_handler,
351 .post_internal_cmd = ata_bmdma_post_internal_cmd,
352
353 .bmdma_setup = ata_bmdma_setup,
354 .bmdma_start = ata_bmdma_start,
355 .bmdma_stop = ata_bmdma_stop,
356 .bmdma_status = ata_bmdma_status,
357
358 .qc_prep = ata_qc_prep,
359 .qc_issue = ata_qc_issue_prot,
360 .eng_timeout = ata_eng_timeout,
361 .data_xfer = ata_pio_data_xfer,
362
363 .irq_handler = ata_interrupt,
364 .irq_clear = ata_bmdma_irq_clear,
365
366 .port_start = ata_port_start,
367 .port_stop = ata_port_stop,
368 .host_stop = ata_host_stop
369};
370
371static struct ata_port_operations amd66_port_ops = {
372 .port_disable = ata_port_disable,
373 .set_piomode = amd66_set_piomode,
374 .set_dmamode = amd66_set_dmamode,
375 .mode_filter = ata_pci_default_filter,
376 .tf_load = ata_tf_load,
377 .tf_read = ata_tf_read,
378 .check_status = ata_check_status,
379 .exec_command = ata_exec_command,
380 .dev_select = ata_std_dev_select,
381
382 .freeze = ata_bmdma_freeze,
383 .thaw = ata_bmdma_thaw,
384 .error_handler = amd_early_error_handler,
385 .post_internal_cmd = ata_bmdma_post_internal_cmd,
386
387 .bmdma_setup = ata_bmdma_setup,
388 .bmdma_start = ata_bmdma_start,
389 .bmdma_stop = ata_bmdma_stop,
390 .bmdma_status = ata_bmdma_status,
391
392 .qc_prep = ata_qc_prep,
393 .qc_issue = ata_qc_issue_prot,
394 .eng_timeout = ata_eng_timeout,
395 .data_xfer = ata_pio_data_xfer,
396
397 .irq_handler = ata_interrupt,
398 .irq_clear = ata_bmdma_irq_clear,
399
400 .port_start = ata_port_start,
401 .port_stop = ata_port_stop,
402 .host_stop = ata_host_stop
403};
404
405static struct ata_port_operations amd100_port_ops = {
406 .port_disable = ata_port_disable,
407 .set_piomode = amd100_set_piomode,
408 .set_dmamode = amd100_set_dmamode,
409 .mode_filter = ata_pci_default_filter,
410 .tf_load = ata_tf_load,
411 .tf_read = ata_tf_read,
412 .check_status = ata_check_status,
413 .exec_command = ata_exec_command,
414 .dev_select = ata_std_dev_select,
415
416 .freeze = ata_bmdma_freeze,
417 .thaw = ata_bmdma_thaw,
418 .error_handler = amd_error_handler,
419 .post_internal_cmd = ata_bmdma_post_internal_cmd,
420
421 .bmdma_setup = ata_bmdma_setup,
422 .bmdma_start = ata_bmdma_start,
423 .bmdma_stop = ata_bmdma_stop,
424 .bmdma_status = ata_bmdma_status,
425
426 .qc_prep = ata_qc_prep,
427 .qc_issue = ata_qc_issue_prot,
428 .eng_timeout = ata_eng_timeout,
429 .data_xfer = ata_pio_data_xfer,
430
431 .irq_handler = ata_interrupt,
432 .irq_clear = ata_bmdma_irq_clear,
433
434 .port_start = ata_port_start,
435 .port_stop = ata_port_stop,
436 .host_stop = ata_host_stop
437};
438
439static struct ata_port_operations amd133_port_ops = {
440 .port_disable = ata_port_disable,
441 .set_piomode = amd133_set_piomode,
442 .set_dmamode = amd133_set_dmamode,
443 .mode_filter = ata_pci_default_filter,
444 .tf_load = ata_tf_load,
445 .tf_read = ata_tf_read,
446 .check_status = ata_check_status,
447 .exec_command = ata_exec_command,
448 .dev_select = ata_std_dev_select,
449
450 .freeze = ata_bmdma_freeze,
451 .thaw = ata_bmdma_thaw,
452 .error_handler = amd_error_handler,
453 .post_internal_cmd = ata_bmdma_post_internal_cmd,
454
455 .bmdma_setup = ata_bmdma_setup,
456 .bmdma_start = ata_bmdma_start,
457 .bmdma_stop = ata_bmdma_stop,
458 .bmdma_status = ata_bmdma_status,
459
460 .qc_prep = ata_qc_prep,
461 .qc_issue = ata_qc_issue_prot,
462 .eng_timeout = ata_eng_timeout,
463 .data_xfer = ata_pio_data_xfer,
464
465 .irq_handler = ata_interrupt,
466 .irq_clear = ata_bmdma_irq_clear,
467
468 .port_start = ata_port_start,
469 .port_stop = ata_port_stop,
470 .host_stop = ata_host_stop
471};
472
473static struct ata_port_operations nv100_port_ops = {
474 .port_disable = ata_port_disable,
475 .set_piomode = nv100_set_piomode,
476 .set_dmamode = nv100_set_dmamode,
477 .mode_filter = ata_pci_default_filter,
478 .tf_load = ata_tf_load,
479 .tf_read = ata_tf_read,
480 .check_status = ata_check_status,
481 .exec_command = ata_exec_command,
482 .dev_select = ata_std_dev_select,
483
484 .freeze = ata_bmdma_freeze,
485 .thaw = ata_bmdma_thaw,
486 .error_handler = nv_error_handler,
487 .post_internal_cmd = ata_bmdma_post_internal_cmd,
488
489 .bmdma_setup = ata_bmdma_setup,
490 .bmdma_start = ata_bmdma_start,
491 .bmdma_stop = ata_bmdma_stop,
492 .bmdma_status = ata_bmdma_status,
493
494 .qc_prep = ata_qc_prep,
495 .qc_issue = ata_qc_issue_prot,
496 .eng_timeout = ata_eng_timeout,
497 .data_xfer = ata_pio_data_xfer,
498
499 .irq_handler = ata_interrupt,
500 .irq_clear = ata_bmdma_irq_clear,
501
502 .port_start = ata_port_start,
503 .port_stop = ata_port_stop,
504 .host_stop = ata_host_stop
505};
506
507static struct ata_port_operations nv133_port_ops = {
508 .port_disable = ata_port_disable,
509 .set_piomode = nv133_set_piomode,
510 .set_dmamode = nv133_set_dmamode,
511 .mode_filter = ata_pci_default_filter,
512 .tf_load = ata_tf_load,
513 .tf_read = ata_tf_read,
514 .check_status = ata_check_status,
515 .exec_command = ata_exec_command,
516 .dev_select = ata_std_dev_select,
517
518 .freeze = ata_bmdma_freeze,
519 .thaw = ata_bmdma_thaw,
520 .error_handler = nv_error_handler,
521 .post_internal_cmd = ata_bmdma_post_internal_cmd,
522
523 .bmdma_setup = ata_bmdma_setup,
524 .bmdma_start = ata_bmdma_start,
525 .bmdma_stop = ata_bmdma_stop,
526 .bmdma_status = ata_bmdma_status,
527
528 .qc_prep = ata_qc_prep,
529 .qc_issue = ata_qc_issue_prot,
530 .eng_timeout = ata_eng_timeout,
531 .data_xfer = ata_pio_data_xfer,
532
533 .irq_handler = ata_interrupt,
534 .irq_clear = ata_bmdma_irq_clear,
535
536 .port_start = ata_port_start,
537 .port_stop = ata_port_stop,
538 .host_stop = ata_host_stop
539};
540
541static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
542{
543 static struct ata_port_info info[10] = {
544 { /* 0: AMD 7401 */
545 .sht = &amd_sht,
546 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
547 .pio_mask = 0x1f,
548 .mwdma_mask = 0x07, /* No SWDMA */
549 .udma_mask = 0x07, /* UDMA 33 */
550 .port_ops = &amd33_port_ops
551 },
552 { /* 1: Early AMD7409 - no swdma */
553 .sht = &amd_sht,
554 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
555 .pio_mask = 0x1f,
556 .mwdma_mask = 0x07,
557 .udma_mask = 0x1f, /* UDMA 66 */
558 .port_ops = &amd66_port_ops
559 },
560 { /* 2: AMD 7409, no swdma errata */
561 .sht = &amd_sht,
562 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
563 .pio_mask = 0x1f,
564 .mwdma_mask = 0x07,
565 .udma_mask = 0x1f, /* UDMA 66 */
566 .port_ops = &amd66_port_ops
567 },
568 { /* 3: AMD 7411 */
569 .sht = &amd_sht,
570 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
571 .pio_mask = 0x1f,
572 .mwdma_mask = 0x07,
573 .udma_mask = 0x3f, /* UDMA 100 */
574 .port_ops = &amd100_port_ops
575 },
576 { /* 4: AMD 7441 */
577 .sht = &amd_sht,
578 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
579 .pio_mask = 0x1f,
580 .mwdma_mask = 0x07,
581 .udma_mask = 0x3f, /* UDMA 100 */
582 .port_ops = &amd100_port_ops
583 },
584 { /* 5: AMD 8111*/
585 .sht = &amd_sht,
586 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
587 .pio_mask = 0x1f,
588 .mwdma_mask = 0x07,
589 .udma_mask = 0x7f, /* UDMA 133, no swdma */
590 .port_ops = &amd133_port_ops
591 },
592 { /* 6: AMD 8111 UDMA 100 (Serenade) */
593 .sht = &amd_sht,
594 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
595 .pio_mask = 0x1f,
596 .mwdma_mask = 0x07,
597 .udma_mask = 0x3f, /* UDMA 100, no swdma */
598 .port_ops = &amd133_port_ops
599 },
600 { /* 7: Nvidia Nforce */
601 .sht = &amd_sht,
602 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
603 .pio_mask = 0x1f,
604 .mwdma_mask = 0x07,
605 .udma_mask = 0x3f, /* UDMA 100 */
606 .port_ops = &nv100_port_ops
607 },
608 { /* 8: Nvidia Nforce2 and later */
609 .sht = &amd_sht,
610 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
611 .pio_mask = 0x1f,
612 .mwdma_mask = 0x07,
613 .udma_mask = 0x7f, /* UDMA 133, no swdma */
614 .port_ops = &nv133_port_ops
615 },
616 { /* 9: AMD CS5536 (Geode companion) */
617 .sht = &amd_sht,
618 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
619 .pio_mask = 0x1f,
620 .mwdma_mask = 0x07,
621 .udma_mask = 0x3f, /* UDMA 100 */
622 .port_ops = &amd100_port_ops
623 }
624 };
625 static struct ata_port_info *port_info[2];
626 static int printed_version;
627 int type = id->driver_data;
628 u8 rev;
629 u8 fifo;
630
631 if (!printed_version++)
632 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
633
634 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
635 pci_read_config_byte(pdev, 0x41, &fifo);
636
637 /* Check for AMD7409 without swdma errata and if found adjust type */
638 if (type == 1 && rev > 0x7)
639 type = 2;
640
641 /* Check for AMD7411 */
642 if (type == 3)
643 /* FIFO is broken */
644 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
645 else
646 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
647
648 /* Serenade ? */
649 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
650 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
651 type = 6; /* UDMA 100 only */
652
653 if (type < 3)
654 ata_pci_clear_simplex(pdev);
655
656 /* And fire it up */
657
658 port_info[0] = port_info[1] = &info[type];
659 return ata_pci_init_one(pdev, port_info, 2);
660}
661
662static const struct pci_device_id amd[] = {
663 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
664 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
665 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
666 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
667 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
668 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
669 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
670 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
671 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
672 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
673 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
674 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
675 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
676 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
677 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
678 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
679 { 0, },
680};
681
682static struct pci_driver amd_pci_driver = {
683 .name = DRV_NAME,
684 .id_table = amd,
685 .probe = amd_init_one,
686 .remove = ata_pci_remove_one
687};
688
689static int __init amd_init(void)
690{
691 return pci_register_driver(&amd_pci_driver);
692}
693
694static void __exit amd_exit(void)
695{
696 pci_unregister_driver(&amd_pci_driver);
697}
698
699
700MODULE_AUTHOR("Alan Cox");
701MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
702MODULE_LICENSE("GPL");
703MODULE_DEVICE_TABLE(pci, amd);
704MODULE_VERSION(DRV_VERSION);
705
706module_init(amd_init);
707module_exit(amd_exit);
diff --git a/drivers/ata/pata_artop.c b/drivers/ata/pata_artop.c
new file mode 100644
index 00000000000..d6ef3bf1bac
--- /dev/null
+++ b/drivers/ata/pata_artop.c
@@ -0,0 +1,518 @@
1/*
2 * pata_artop.c - ARTOP ATA controller driver
3 *
4 * (C) 2006 Red Hat <alan@redhat.com>
5 *
6 * Based in part on drivers/ide/pci/aec62xx.c
7 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
8 * 865/865R fixes for Macintosh card version from a patch to the old
9 * driver by Thibaut VARENE <varenet@parisc-linux.org>
10 * When setting the PCI latency we must set 0x80 or higher for burst
11 * performance Alessandro Zummo <alessandro.zummo@towertech.it>
12 *
13 * TODO
14 * 850 serialization once the core supports it
15 * Investigate no_dsc on 850R
16 * Clock detect
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/device.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28#include <linux/ata.h>
29
30#define DRV_NAME "pata_artop"
31#define DRV_VERSION "0.4.1"
32
33/*
34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
35 * get PCI bus speed functionality we leave this as 0. Its a variable
36 * for when we get the functionality and also for folks wanting to
37 * test stuff.
38 */
39
40static int clock = 0;
41
42static int artop6210_pre_reset(struct ata_port *ap)
43{
44 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
45 const struct pci_bits artop_enable_bits[] = {
46 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
47 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
48 };
49
50 if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) {
51 ata_port_disable(ap);
52 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
53 return 0;
54 }
55 ap->cbl = ATA_CBL_PATA40;
56 return ata_std_prereset(ap);
57}
58
59/**
60 * artop6210_error_handler - Probe specified port on PATA host controller
61 * @ap: Port to probe
62 *
63 * LOCKING:
64 * None (inherited from caller).
65 */
66
67static void artop6210_error_handler(struct ata_port *ap)
68{
69 ata_bmdma_drive_eh(ap, artop6210_pre_reset,
70 ata_std_softreset, NULL,
71 ata_std_postreset);
72}
73
74/**
75 * artop6260_pre_reset - check for 40/80 pin
76 * @ap: Port
77 *
78 * The ARTOP hardware reports the cable detect bits in register 0x49.
79 * Nothing complicated needed here.
80 */
81
82static int artop6260_pre_reset(struct ata_port *ap)
83{
84 static const struct pci_bits artop_enable_bits[] = {
85 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
86 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
87 };
88
89 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
90 u8 tmp;
91
92 /* Odd numbered device ids are the units with enable bits (the -R cards) */
93 if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) {
94 ata_port_disable(ap);
95 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
96 return 0;
97 }
98 pci_read_config_byte(pdev, 0x49, &tmp);
99 if (tmp & (1 >> ap->port_no))
100 ap->cbl = ATA_CBL_PATA40;
101 else
102 ap->cbl = ATA_CBL_PATA80;
103 return ata_std_prereset(ap);
104}
105
106/**
107 * artop6260_error_handler - Probe specified port on PATA host controller
108 * @ap: Port to probe
109 *
110 * LOCKING:
111 * None (inherited from caller).
112 */
113
114static void artop6260_error_handler(struct ata_port *ap)
115{
116 ata_bmdma_drive_eh(ap, artop6260_pre_reset,
117 ata_std_softreset, NULL,
118 ata_std_postreset);
119}
120
121/**
122 * artop6210_load_piomode - Load a set of PATA PIO timings
123 * @ap: Port whose timings we are configuring
124 * @adev: Device
125 * @pio: PIO mode
126 *
127 * Set PIO mode for device, in host controller PCI config space. This
128 * is used both to set PIO timings in PIO mode and also to set the
129 * matching PIO clocking for UDMA, as well as the MWDMA timings.
130 *
131 * LOCKING:
132 * None (inherited from caller).
133 */
134
135static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
136{
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
138 int dn = adev->devno + 2 * ap->port_no;
139 const u16 timing[2][5] = {
140 { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
141 { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
142
143 };
144 /* Load the PIO timing active/recovery bits */
145 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
146}
147
148/**
149 * artop6210_set_piomode - Initialize host controller PATA PIO timings
150 * @ap: Port whose timings we are configuring
151 * @adev: Device we are configuring
152 *
153 * Set PIO mode for device, in host controller PCI config space. For
154 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
155 * the event UDMA is used the later call to set_dmamode will set the
156 * bits as required.
157 *
158 * LOCKING:
159 * None (inherited from caller).
160 */
161
162static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
163{
164 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
165 int dn = adev->devno + 2 * ap->port_no;
166 u8 ultra;
167
168 artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
169
170 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
171 pci_read_config_byte(pdev, 0x54, &ultra);
172 ultra &= ~(3 << (2 * dn));
173 pci_write_config_byte(pdev, 0x54, ultra);
174}
175
176/**
177 * artop6260_load_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
179 * @adev: Device we are configuring
180 * @pio: PIO mode
181 *
182 * Set PIO mode for device, in host controller PCI config space. The
183 * ARTOP6260 and relatives store the timing data differently.
184 *
185 * LOCKING:
186 * None (inherited from caller).
187 */
188
189static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
190{
191 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
192 int dn = adev->devno + 2 * ap->port_no;
193 const u8 timing[2][5] = {
194 { 0x00, 0x0A, 0x08, 0x33, 0x31 },
195 { 0x70, 0x7A, 0x78, 0x43, 0x41 }
196
197 };
198 /* Load the PIO timing active/recovery bits */
199 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
200}
201
202/**
203 * artop6260_set_piomode - Initialize host controller PATA PIO timings
204 * @ap: Port whose timings we are configuring
205 * @adev: Device we are configuring
206 *
207 * Set PIO mode for device, in host controller PCI config space. For
208 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
209 * the event UDMA is used the later call to set_dmamode will set the
210 * bits as required.
211 *
212 * LOCKING:
213 * None (inherited from caller).
214 */
215
216static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
217{
218 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
219 u8 ultra;
220
221 artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
222
223 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
224 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
225 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
226 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
227}
228
229/**
230 * artop6210_set_dmamode - Initialize host controller PATA PIO timings
231 * @ap: Port whose timings we are configuring
232 * @adev: um
233 *
234 * Set DMA mode for device, in host controller PCI config space.
235 *
236 * LOCKING:
237 * None (inherited from caller).
238 */
239
240static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
241{
242 unsigned int pio;
243 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
244 int dn = adev->devno + 2 * ap->port_no;
245 u8 ultra;
246
247 if (adev->dma_mode == XFER_MW_DMA_0)
248 pio = 1;
249 else
250 pio = 4;
251
252 /* Load the PIO timing active/recovery bits */
253 artop6210_load_piomode(ap, adev, pio);
254
255 pci_read_config_byte(pdev, 0x54, &ultra);
256 ultra &= ~(3 << (2 * dn));
257
258 /* Add ultra DMA bits if in UDMA mode */
259 if (adev->dma_mode >= XFER_UDMA_0) {
260 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
261 if (mode == 0)
262 mode = 1;
263 ultra |= (mode << (2 * dn));
264 }
265 pci_write_config_byte(pdev, 0x54, ultra);
266}
267
268/**
269 * artop6260_set_dmamode - Initialize host controller PATA PIO timings
270 * @ap: Port whose timings we are configuring
271 * @adev: Device we are configuring
272 *
273 * Set DMA mode for device, in host controller PCI config space. The
274 * ARTOP6260 and relatives store the timing data differently.
275 *
276 * LOCKING:
277 * None (inherited from caller).
278 */
279
280static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
281{
282 unsigned int pio = adev->pio_mode - XFER_PIO_0;
283 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
284 u8 ultra;
285
286 if (adev->dma_mode == XFER_MW_DMA_0)
287 pio = 1;
288 else
289 pio = 4;
290
291 /* Load the PIO timing active/recovery bits */
292 artop6260_load_piomode(ap, adev, pio);
293
294 /* Add ultra DMA bits if in UDMA mode */
295 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
296 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
297 if (adev->dma_mode >= XFER_UDMA_0) {
298 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
299 if (mode == 0)
300 mode = 1;
301 ultra |= (mode << (4 * adev->devno));
302 }
303 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
304}
305
306static struct scsi_host_template artop_sht = {
307 .module = THIS_MODULE,
308 .name = DRV_NAME,
309 .ioctl = ata_scsi_ioctl,
310 .queuecommand = ata_scsi_queuecmd,
311 .can_queue = ATA_DEF_QUEUE,
312 .this_id = ATA_SHT_THIS_ID,
313 .sg_tablesize = LIBATA_MAX_PRD,
314 .max_sectors = ATA_MAX_SECTORS,
315 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
316 .emulated = ATA_SHT_EMULATED,
317 .use_clustering = ATA_SHT_USE_CLUSTERING,
318 .proc_name = DRV_NAME,
319 .dma_boundary = ATA_DMA_BOUNDARY,
320 .slave_configure = ata_scsi_slave_config,
321 .bios_param = ata_std_bios_param,
322};
323
324static const struct ata_port_operations artop6210_ops = {
325 .port_disable = ata_port_disable,
326 .set_piomode = artop6210_set_piomode,
327 .set_dmamode = artop6210_set_dmamode,
328 .mode_filter = ata_pci_default_filter,
329
330 .tf_load = ata_tf_load,
331 .tf_read = ata_tf_read,
332 .check_status = ata_check_status,
333 .exec_command = ata_exec_command,
334 .dev_select = ata_std_dev_select,
335
336 .freeze = ata_bmdma_freeze,
337 .thaw = ata_bmdma_thaw,
338 .error_handler = artop6210_error_handler,
339 .post_internal_cmd = ata_bmdma_post_internal_cmd,
340
341 .bmdma_setup = ata_bmdma_setup,
342 .bmdma_start = ata_bmdma_start,
343 .bmdma_stop = ata_bmdma_stop,
344 .bmdma_status = ata_bmdma_status,
345 .qc_prep = ata_qc_prep,
346 .qc_issue = ata_qc_issue_prot,
347 .eng_timeout = ata_eng_timeout,
348 .data_xfer = ata_pio_data_xfer,
349
350 .irq_handler = ata_interrupt,
351 .irq_clear = ata_bmdma_irq_clear,
352
353 .port_start = ata_port_start,
354 .port_stop = ata_port_stop,
355 .host_stop = ata_host_stop,
356};
357
358static const struct ata_port_operations artop6260_ops = {
359 .port_disable = ata_port_disable,
360 .set_piomode = artop6260_set_piomode,
361 .set_dmamode = artop6260_set_dmamode,
362
363 .tf_load = ata_tf_load,
364 .tf_read = ata_tf_read,
365 .check_status = ata_check_status,
366 .exec_command = ata_exec_command,
367 .dev_select = ata_std_dev_select,
368
369 .freeze = ata_bmdma_freeze,
370 .thaw = ata_bmdma_thaw,
371 .error_handler = artop6260_error_handler,
372 .post_internal_cmd = ata_bmdma_post_internal_cmd,
373
374 .bmdma_setup = ata_bmdma_setup,
375 .bmdma_start = ata_bmdma_start,
376 .bmdma_stop = ata_bmdma_stop,
377 .bmdma_status = ata_bmdma_status,
378 .qc_prep = ata_qc_prep,
379 .qc_issue = ata_qc_issue_prot,
380 .data_xfer = ata_pio_data_xfer,
381
382 .eng_timeout = ata_eng_timeout,
383
384 .irq_handler = ata_interrupt,
385 .irq_clear = ata_bmdma_irq_clear,
386
387 .port_start = ata_port_start,
388 .port_stop = ata_port_stop,
389 .host_stop = ata_host_stop,
390};
391
392
393/**
394 * artop_init_one - Register ARTOP ATA PCI device with kernel services
395 * @pdev: PCI device to register
396 * @ent: Entry in artop_pci_tbl matching with @pdev
397 *
398 * Called from kernel PCI layer.
399 *
400 * LOCKING:
401 * Inherited from PCI layer (may sleep).
402 *
403 * RETURNS:
404 * Zero on success, or -ERRNO value.
405 */
406
407static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
408{
409 static int printed_version;
410 static struct ata_port_info info_6210 = {
411 .sht = &artop_sht,
412 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
413 .pio_mask = 0x1f, /* pio0-4 */
414 .mwdma_mask = 0x07, /* mwdma0-2 */
415 .udma_mask = ATA_UDMA2,
416 .port_ops = &artop6210_ops,
417 };
418 static struct ata_port_info info_626x = {
419 .sht = &artop_sht,
420 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
421 .pio_mask = 0x1f, /* pio0-4 */
422 .mwdma_mask = 0x07, /* mwdma0-2 */
423 .udma_mask = ATA_UDMA4,
424 .port_ops = &artop6260_ops,
425 };
426 static struct ata_port_info info_626x_fast = {
427 .sht = &artop_sht,
428 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
429 .pio_mask = 0x1f, /* pio0-4 */
430 .mwdma_mask = 0x07, /* mwdma0-2 */
431 .udma_mask = ATA_UDMA5,
432 .port_ops = &artop6260_ops,
433 };
434 struct ata_port_info *port_info[2];
435 struct ata_port_info *info;
436 int ports = 2;
437
438 if (!printed_version++)
439 dev_printk(KERN_DEBUG, &pdev->dev,
440 "version " DRV_VERSION "\n");
441
442 if (id->driver_data == 0) { /* 6210 variant */
443 info = &info_6210;
444 /* BIOS may have left us in UDMA, clear it before libata probe */
445 pci_write_config_byte(pdev, 0x54, 0);
446 /* For the moment (also lacks dsc) */
447 printk(KERN_WARNING "ARTOP 6210 requires serialize functionality not yet supported by libata.\n");
448 printk(KERN_WARNING "Secondary ATA ports will not be activated.\n");
449 ports = 1;
450 }
451 else if (id->driver_data == 1) /* 6260 */
452 info = &info_626x;
453 else if (id->driver_data == 2) { /* 6260 or 6260 + fast */
454 unsigned long io = pci_resource_start(pdev, 4);
455 u8 reg;
456
457 info = &info_626x;
458 if (inb(io) & 0x10)
459 info = &info_626x_fast;
460 /* Mac systems come up with some registers not set as we
461 will need them */
462
463 /* Clear reset & test bits */
464 pci_read_config_byte(pdev, 0x49, &reg);
465 pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
466
467 /* PCI latency must be > 0x80 for burst mode, tweak it
468 * if required.
469 */
470 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
471 if (reg <= 0x80)
472 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
473
474 /* Enable IRQ output and burst mode */
475 pci_read_config_byte(pdev, 0x4a, &reg);
476 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
477
478 }
479 port_info[0] = port_info[1] = info;
480 return ata_pci_init_one(pdev, port_info, ports);
481}
482
483static const struct pci_device_id artop_pci_tbl[] = {
484 { 0x1191, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
485 { 0x1191, 0x0006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
486 { 0x1191, 0x0007, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
487 { 0x1191, 0x0008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
488 { 0x1191, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
489 { } /* terminate list */
490};
491
492static struct pci_driver artop_pci_driver = {
493 .name = DRV_NAME,
494 .id_table = artop_pci_tbl,
495 .probe = artop_init_one,
496 .remove = ata_pci_remove_one,
497};
498
499static int __init artop_init(void)
500{
501 return pci_register_driver(&artop_pci_driver);
502}
503
504static void __exit artop_exit(void)
505{
506 pci_unregister_driver(&artop_pci_driver);
507}
508
509
510module_init(artop_init);
511module_exit(artop_exit);
512
513MODULE_AUTHOR("Alan Cox");
514MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
515MODULE_LICENSE("GPL");
516MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
517MODULE_VERSION(DRV_VERSION);
518
diff --git a/drivers/ata/pata_atiixp.c b/drivers/ata/pata_atiixp.c
new file mode 100644
index 00000000000..3f78a1e54a7
--- /dev/null
+++ b/drivers/ata/pata_atiixp.c
@@ -0,0 +1,306 @@
1/*
2 * pata_atiixp.c - ATI PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on
7 *
8 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
9 *
10 * Copyright (C) 2003 ATI Inc. <hyu@ati.com>
11 * Copyright (C) 2004 Bartlomiej Zolnierkiewicz
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/blkdev.h>
20#include <linux/delay.h>
21#include <scsi/scsi_host.h>
22#include <linux/libata.h>
23
24#define DRV_NAME "pata_atiixp"
25#define DRV_VERSION "0.4.2"
26
27enum {
28 ATIIXP_IDE_PIO_TIMING = 0x40,
29 ATIIXP_IDE_MWDMA_TIMING = 0x44,
30 ATIIXP_IDE_PIO_CONTROL = 0x48,
31 ATIIXP_IDE_PIO_MODE = 0x4a,
32 ATIIXP_IDE_UDMA_CONTROL = 0x54,
33 ATIIXP_IDE_UDMA_MODE = 0x56
34};
35
36static int atiixp_pre_reset(struct ata_port *ap)
37{
38 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
39 static struct pci_bits atiixp_enable_bits[] = {
40 { 0x48, 1, 0x01, 0x00 },
41 { 0x48, 1, 0x08, 0x00 }
42 };
43
44 if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no])) {
45 ata_port_disable(ap);
46 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
47 return 0;
48 }
49 ap->cbl = ATA_CBL_PATA80;
50 return ata_std_prereset(ap);
51}
52
53static void atiixp_error_handler(struct ata_port *ap)
54{
55 ata_bmdma_drive_eh(ap, atiixp_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
56}
57
58/**
59 * atiixp_set_pio_timing - set initial PIO mode data
60 * @ap: ATA interface
61 * @adev: ATA device
62 *
63 * Called by both the pio and dma setup functions to set the controller
64 * timings for PIO transfers. We must load both the mode number and
65 * timing values into the controller.
66 */
67
68static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
69{
70 static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
71
72 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
73 int dn = 2 * ap->port_no + adev->devno;
74
75 /* Check this is correct - the order is odd in both drivers */
76 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
77 u16 pio_mode_data, pio_timing_data;
78
79 pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
80 pio_mode_data &= ~(0x7 << (4 * dn));
81 pio_mode_data |= pio << (4 * dn);
82 pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
83
84 pci_read_config_word(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
85 pio_mode_data &= ~(0xFF << timing_shift);
86 pio_mode_data |= (pio_timings[pio] << timing_shift);
87 pci_write_config_word(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
88}
89
90/**
91 * atiixp_set_piomode - set initial PIO mode data
92 * @ap: ATA interface
93 * @adev: ATA device
94 *
95 * Called to do the PIO mode setup. We use a shared helper for this
96 * as the DMA setup must also adjust the PIO timing information.
97 */
98
99static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
100{
101 atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
102}
103
104/**
105 * atiixp_set_dmamode - set initial DMA mode data
106 * @ap: ATA interface
107 * @adev: ATA device
108 *
109 * Called to do the DMA mode setup. We use timing tables for most
110 * modes but must tune an appropriate PIO mode to match.
111 */
112
113static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
114{
115 static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
116
117 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
118 int dma = adev->dma_mode;
119 int dn = 2 * ap->port_no + adev->devno;
120 int wanted_pio;
121
122 if (adev->dma_mode >= XFER_UDMA_0) {
123 u16 udma_mode_data;
124
125 dma -= XFER_UDMA_0;
126
127 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
128 udma_mode_data &= ~(0x7 << (4 * dn));
129 udma_mode_data |= dma << (4 * dn);
130 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
131 } else {
132 u16 mwdma_timing_data;
133 /* Check this is correct - the order is odd in both drivers */
134 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
135
136 dma -= XFER_MW_DMA_0;
137
138 pci_read_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, &mwdma_timing_data);
139 mwdma_timing_data &= ~(0xFF << timing_shift);
140 mwdma_timing_data |= (mwdma_timings[dma] << timing_shift);
141 pci_write_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, mwdma_timing_data);
142 }
143 /*
144 * We must now look at the PIO mode situation. We may need to
145 * adjust the PIO mode to keep the timings acceptable
146 */
147 if (adev->dma_mode >= XFER_MW_DMA_2)
148 wanted_pio = 4;
149 else if (adev->dma_mode == XFER_MW_DMA_1)
150 wanted_pio = 3;
151 else if (adev->dma_mode == XFER_MW_DMA_0)
152 wanted_pio = 0;
153 else BUG();
154
155 if (adev->pio_mode != wanted_pio)
156 atiixp_set_pio_timing(ap, adev, wanted_pio);
157}
158
159/**
160 * atiixp_bmdma_start - DMA start callback
161 * @qc: Command in progress
162 *
163 * When DMA begins we need to ensure that the UDMA control
164 * register for the channel is correctly set.
165 */
166
167static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
168{
169 struct ata_port *ap = qc->ap;
170 struct ata_device *adev = qc->dev;
171
172 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
173 int dn = (2 * ap->port_no) + adev->devno;
174 u16 tmp16;
175
176 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
177 if (adev->dma_mode >= XFER_UDMA_0)
178 tmp16 |= (1 << dn);
179 else
180 tmp16 &= ~(1 << dn);
181 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
182 ata_bmdma_start(qc);
183}
184
185/**
186 * atiixp_dma_stop - DMA stop callback
187 * @qc: Command in progress
188 *
189 * DMA has completed. Clear the UDMA flag as the next operations will
190 * be PIO ones not UDMA data transfer.
191 */
192
193static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
194{
195 struct ata_port *ap = qc->ap;
196 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
197 int dn = (2 * ap->port_no) + qc->dev->devno;
198 u16 tmp16;
199
200 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
201 tmp16 &= ~(1 << dn);
202 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
203 ata_bmdma_stop(qc);
204}
205
206static struct scsi_host_template atiixp_sht = {
207 .module = THIS_MODULE,
208 .name = DRV_NAME,
209 .ioctl = ata_scsi_ioctl,
210 .queuecommand = ata_scsi_queuecmd,
211 .can_queue = ATA_DEF_QUEUE,
212 .this_id = ATA_SHT_THIS_ID,
213 .sg_tablesize = LIBATA_MAX_PRD,
214 .max_sectors = ATA_MAX_SECTORS,
215 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
216 .emulated = ATA_SHT_EMULATED,
217 .use_clustering = ATA_SHT_USE_CLUSTERING,
218 .proc_name = DRV_NAME,
219 .dma_boundary = ATA_DMA_BOUNDARY,
220 .slave_configure = ata_scsi_slave_config,
221 .bios_param = ata_std_bios_param,
222};
223
224static struct ata_port_operations atiixp_port_ops = {
225 .port_disable = ata_port_disable,
226 .set_piomode = atiixp_set_piomode,
227 .set_dmamode = atiixp_set_dmamode,
228 .mode_filter = ata_pci_default_filter,
229 .tf_load = ata_tf_load,
230 .tf_read = ata_tf_read,
231 .check_status = ata_check_status,
232 .exec_command = ata_exec_command,
233 .dev_select = ata_std_dev_select,
234
235 .freeze = ata_bmdma_freeze,
236 .thaw = ata_bmdma_thaw,
237 .error_handler = atiixp_error_handler,
238 .post_internal_cmd = ata_bmdma_post_internal_cmd,
239
240 .bmdma_setup = ata_bmdma_setup,
241 .bmdma_start = atiixp_bmdma_start,
242 .bmdma_stop = atiixp_bmdma_stop,
243 .bmdma_status = ata_bmdma_status,
244
245 .qc_prep = ata_qc_prep,
246 .qc_issue = ata_qc_issue_prot,
247 .eng_timeout = ata_eng_timeout,
248 .data_xfer = ata_pio_data_xfer,
249
250 .irq_handler = ata_interrupt,
251 .irq_clear = ata_bmdma_irq_clear,
252
253 .port_start = ata_port_start,
254 .port_stop = ata_port_stop,
255 .host_stop = ata_host_stop
256};
257
258static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
259{
260 static struct ata_port_info info = {
261 .sht = &atiixp_sht,
262 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
263 .pio_mask = 0x1f,
264 .mwdma_mask = 0x06, /* No MWDMA0 support */
265 .udma_mask = 0x3F,
266 .port_ops = &atiixp_port_ops
267 };
268 static struct ata_port_info *port_info[2] = { &info, &info };
269 return ata_pci_init_one(dev, port_info, 2);
270}
271
272static struct pci_device_id atiixp[] = {
273 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
274 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
275 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
276 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
277 { 0, },
278};
279
280static struct pci_driver atiixp_pci_driver = {
281 .name = DRV_NAME,
282 .id_table = atiixp,
283 .probe = atiixp_init_one,
284 .remove = ata_pci_remove_one
285};
286
287static int __init atiixp_init(void)
288{
289 return pci_register_driver(&atiixp_pci_driver);
290}
291
292
293static void __exit atiixp_exit(void)
294{
295 pci_unregister_driver(&atiixp_pci_driver);
296}
297
298
299MODULE_AUTHOR("Alan Cox");
300MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
301MODULE_LICENSE("GPL");
302MODULE_DEVICE_TABLE(pci, atiixp);
303MODULE_VERSION(DRV_VERSION);
304
305module_init(atiixp_init);
306module_exit(atiixp_exit);
diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c
new file mode 100644
index 00000000000..03284611a72
--- /dev/null
+++ b/drivers/ata/pata_cmd64x.c
@@ -0,0 +1,505 @@
1/*
2 * pata_cmd64x.c - ATI PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based upon
7 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
8 *
9 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
10 * Note, this driver is not used at all on other systems because
11 * there the "BIOS" has done all of the following already.
12 * Due to massive hardware bugs, UltraDMA is only supported
13 * on the 646U2 and not on the 646U.
14 *
15 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
16 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
17 *
18 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
19 *
20 * TODO
21 * Testing work
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include <scsi/scsi_host.h>
31#include <linux/libata.h>
32
33#define DRV_NAME "pata_cmd64x"
34#define DRV_VERSION "0.2.1"
35
36/*
37 * CMD64x specific registers definition.
38 */
39
40enum {
41 CFR = 0x50,
42 CFR_INTR_CH0 = 0x02,
43 CNTRL = 0x51,
44 CNTRL_DIS_RA0 = 0x40,
45 CNTRL_DIS_RA1 = 0x80,
46 CNTRL_ENA_2ND = 0x08,
47 CMDTIM = 0x52,
48 ARTTIM0 = 0x53,
49 DRWTIM0 = 0x54,
50 ARTTIM1 = 0x55,
51 DRWTIM1 = 0x56,
52 ARTTIM23 = 0x57,
53 ARTTIM23_DIS_RA2 = 0x04,
54 ARTTIM23_DIS_RA3 = 0x08,
55 ARTTIM23_INTR_CH1 = 0x10,
56 ARTTIM2 = 0x57,
57 ARTTIM3 = 0x57,
58 DRWTIM23 = 0x58,
59 DRWTIM2 = 0x58,
60 BRST = 0x59,
61 DRWTIM3 = 0x5b,
62 BMIDECR0 = 0x70,
63 MRDMODE = 0x71,
64 MRDMODE_INTR_CH0 = 0x04,
65 MRDMODE_INTR_CH1 = 0x08,
66 MRDMODE_BLK_CH0 = 0x10,
67 MRDMODE_BLK_CH1 = 0x20,
68 BMIDESR0 = 0x72,
69 UDIDETCR0 = 0x73,
70 DTPR0 = 0x74,
71 BMIDECR1 = 0x78,
72 BMIDECSR = 0x79,
73 BMIDESR1 = 0x7A,
74 UDIDETCR1 = 0x7B,
75 DTPR1 = 0x7C
76};
77
78static int cmd64x_pre_reset(struct ata_port *ap)
79{
80 ap->cbl = ATA_CBL_PATA40;
81 return ata_std_prereset(ap);
82}
83
84static int cmd648_pre_reset(struct ata_port *ap)
85{
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87 u8 r;
88
89 /* Check cable detect bits */
90 pci_read_config_byte(pdev, BMIDECSR, &r);
91 if (r & (1 << ap->port_no))
92 ap->cbl = ATA_CBL_PATA80;
93 else
94 ap->cbl = ATA_CBL_PATA40;
95
96 return ata_std_prereset(ap);
97}
98
99static void cmd64x_error_handler(struct ata_port *ap)
100{
101 return ata_bmdma_drive_eh(ap, cmd64x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
102}
103
104static void cmd648_error_handler(struct ata_port *ap)
105{
106 ata_bmdma_drive_eh(ap, cmd648_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
107}
108
109/**
110 * cmd64x_set_piomode - set initial PIO mode data
111 * @ap: ATA interface
112 * @adev: ATA device
113 *
114 * Called to do the PIO mode setup.
115 */
116
117static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
118{
119 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
120 struct ata_timing t;
121 const unsigned long T = 1000000 / 33;
122 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
123
124 u8 reg;
125
126 /* Port layout is not logical so use a table */
127 const u8 arttim_port[2][2] = {
128 { ARTTIM0, ARTTIM1 },
129 { ARTTIM23, ARTTIM23 }
130 };
131 const u8 drwtim_port[2][2] = {
132 { DRWTIM0, DRWTIM1 },
133 { DRWTIM2, DRWTIM3 }
134 };
135
136 int arttim = arttim_port[ap->port_no][adev->devno];
137 int drwtim = drwtim_port[ap->port_no][adev->devno];
138
139
140 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
141 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
142 return;
143 }
144 if (ap->port_no) {
145 /* Slave has shared address setup */
146 struct ata_device *pair = ata_dev_pair(adev);
147
148 if (pair) {
149 struct ata_timing tp;
150 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
151 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
152 }
153 }
154
155 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
156 t.active, t.recover, t.setup);
157 if (t.recover > 16) {
158 t.active += t.recover - 16;
159 t.recover = 16;
160 }
161 if (t.active > 16)
162 t.active = 16;
163
164 /* Now convert the clocks into values we can actually stuff into
165 the chip */
166
167 if (t.recover > 1)
168 t.recover--;
169 else
170 t.recover = 15;
171
172 if (t.setup > 4)
173 t.setup = 0xC0;
174 else
175 t.setup = setup_data[t.setup];
176
177 t.active &= 0x0F; /* 0 = 16 */
178
179 /* Load setup timing */
180 pci_read_config_byte(pdev, arttim, &reg);
181 reg &= 0x3F;
182 reg |= t.setup;
183 pci_write_config_byte(pdev, arttim, reg);
184
185 /* Load active/recovery */
186 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
187}
188
189/**
190 * cmd64x_set_dmamode - set initial DMA mode data
191 * @ap: ATA interface
192 * @adev: ATA device
193 *
194 * Called to do the DMA mode setup.
195 */
196
197static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
198{
199 static const u8 udma_data[] = {
200 0x31, 0x21, 0x11, 0x25, 0x15, 0x05
201 };
202 static const u8 mwdma_data[] = {
203 0x30, 0x20, 0x10
204 };
205
206 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
207 u8 regU, regD;
208
209 int pciU = UDIDETCR0 + 8 * ap->port_no;
210 int pciD = BMIDESR0 + 8 * ap->port_no;
211 int shift = 2 * adev->devno;
212
213 pci_read_config_byte(pdev, pciD, &regD);
214 pci_read_config_byte(pdev, pciU, &regU);
215
216 regD &= ~(0x20 << shift);
217 regU &= ~(0x35 << shift);
218
219 if (adev->dma_mode >= XFER_UDMA_0)
220 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
221 else
222 regD |= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;
223
224 regD |= 0x20 << adev->devno;
225
226 pci_write_config_byte(pdev, pciU, regU);
227 pci_write_config_byte(pdev, pciD, regD);
228}
229
230/**
231 * cmd648_dma_stop - DMA stop callback
232 * @qc: Command in progress
233 *
234 * DMA has completed.
235 */
236
237static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
238{
239 struct ata_port *ap = qc->ap;
240 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
241 u8 dma_intr;
242 int dma_reg = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
243 int dma_mask = ap->port_no ? ARTTIM2 : CFR;
244
245 ata_bmdma_stop(qc);
246
247 pci_read_config_byte(pdev, dma_reg, &dma_intr);
248 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
249}
250
251/**
252 * cmd646r1_dma_stop - DMA stop callback
253 * @qc: Command in progress
254 *
255 * Stub for now while investigating the r1 quirk in the old driver.
256 */
257
258static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
259{
260 ata_bmdma_stop(qc);
261}
262
263static struct scsi_host_template cmd64x_sht = {
264 .module = THIS_MODULE,
265 .name = DRV_NAME,
266 .ioctl = ata_scsi_ioctl,
267 .queuecommand = ata_scsi_queuecmd,
268 .can_queue = ATA_DEF_QUEUE,
269 .this_id = ATA_SHT_THIS_ID,
270 .sg_tablesize = LIBATA_MAX_PRD,
271 .max_sectors = ATA_MAX_SECTORS,
272 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
273 .emulated = ATA_SHT_EMULATED,
274 .use_clustering = ATA_SHT_USE_CLUSTERING,
275 .proc_name = DRV_NAME,
276 .dma_boundary = ATA_DMA_BOUNDARY,
277 .slave_configure = ata_scsi_slave_config,
278 .bios_param = ata_std_bios_param,
279};
280
281static struct ata_port_operations cmd64x_port_ops = {
282 .port_disable = ata_port_disable,
283 .set_piomode = cmd64x_set_piomode,
284 .set_dmamode = cmd64x_set_dmamode,
285 .mode_filter = ata_pci_default_filter,
286 .tf_load = ata_tf_load,
287 .tf_read = ata_tf_read,
288 .check_status = ata_check_status,
289 .exec_command = ata_exec_command,
290 .dev_select = ata_std_dev_select,
291
292 .freeze = ata_bmdma_freeze,
293 .thaw = ata_bmdma_thaw,
294 .error_handler = cmd64x_error_handler,
295 .post_internal_cmd = ata_bmdma_post_internal_cmd,
296
297 .bmdma_setup = ata_bmdma_setup,
298 .bmdma_start = ata_bmdma_start,
299 .bmdma_stop = ata_bmdma_stop,
300 .bmdma_status = ata_bmdma_status,
301
302 .qc_prep = ata_qc_prep,
303 .qc_issue = ata_qc_issue_prot,
304 .eng_timeout = ata_eng_timeout,
305 .data_xfer = ata_pio_data_xfer,
306
307 .irq_handler = ata_interrupt,
308 .irq_clear = ata_bmdma_irq_clear,
309
310 .port_start = ata_port_start,
311 .port_stop = ata_port_stop,
312 .host_stop = ata_host_stop
313};
314
315static struct ata_port_operations cmd646r1_port_ops = {
316 .port_disable = ata_port_disable,
317 .set_piomode = cmd64x_set_piomode,
318 .set_dmamode = cmd64x_set_dmamode,
319 .mode_filter = ata_pci_default_filter,
320 .tf_load = ata_tf_load,
321 .tf_read = ata_tf_read,
322 .check_status = ata_check_status,
323 .exec_command = ata_exec_command,
324 .dev_select = ata_std_dev_select,
325
326 .freeze = ata_bmdma_freeze,
327 .thaw = ata_bmdma_thaw,
328 .error_handler = cmd64x_error_handler,
329 .post_internal_cmd = ata_bmdma_post_internal_cmd,
330
331 .bmdma_setup = ata_bmdma_setup,
332 .bmdma_start = ata_bmdma_start,
333 .bmdma_stop = cmd646r1_bmdma_stop,
334 .bmdma_status = ata_bmdma_status,
335
336 .qc_prep = ata_qc_prep,
337 .qc_issue = ata_qc_issue_prot,
338 .eng_timeout = ata_eng_timeout,
339 .data_xfer = ata_pio_data_xfer,
340
341 .irq_handler = ata_interrupt,
342 .irq_clear = ata_bmdma_irq_clear,
343
344 .port_start = ata_port_start,
345 .port_stop = ata_port_stop,
346 .host_stop = ata_host_stop
347};
348
349static struct ata_port_operations cmd648_port_ops = {
350 .port_disable = ata_port_disable,
351 .set_piomode = cmd64x_set_piomode,
352 .set_dmamode = cmd64x_set_dmamode,
353 .mode_filter = ata_pci_default_filter,
354 .tf_load = ata_tf_load,
355 .tf_read = ata_tf_read,
356 .check_status = ata_check_status,
357 .exec_command = ata_exec_command,
358 .dev_select = ata_std_dev_select,
359
360 .freeze = ata_bmdma_freeze,
361 .thaw = ata_bmdma_thaw,
362 .error_handler = cmd648_error_handler,
363 .post_internal_cmd = ata_bmdma_post_internal_cmd,
364
365 .bmdma_setup = ata_bmdma_setup,
366 .bmdma_start = ata_bmdma_start,
367 .bmdma_stop = cmd648_bmdma_stop,
368 .bmdma_status = ata_bmdma_status,
369
370 .qc_prep = ata_qc_prep,
371 .qc_issue = ata_qc_issue_prot,
372 .eng_timeout = ata_eng_timeout,
373 .data_xfer = ata_pio_data_xfer,
374
375 .irq_handler = ata_interrupt,
376 .irq_clear = ata_bmdma_irq_clear,
377
378 .port_start = ata_port_start,
379 .port_stop = ata_port_stop,
380 .host_stop = ata_host_stop
381};
382
383static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
384{
385 u32 class_rev;
386
387 static struct ata_port_info cmd_info[6] = {
388 { /* CMD 643 - no UDMA */
389 .sht = &cmd64x_sht,
390 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
391 .pio_mask = 0x1f,
392 .mwdma_mask = 0x07,
393 .port_ops = &cmd64x_port_ops
394 },
395 { /* CMD 646 with broken UDMA */
396 .sht = &cmd64x_sht,
397 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
398 .pio_mask = 0x1f,
399 .mwdma_mask = 0x07,
400 .port_ops = &cmd64x_port_ops
401 },
402 { /* CMD 646 with working UDMA */
403 .sht = &cmd64x_sht,
404 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
405 .pio_mask = 0x1f,
406 .mwdma_mask = 0x07,
407 .udma_mask = ATA_UDMA1,
408 .port_ops = &cmd64x_port_ops
409 },
410 { /* CMD 646 rev 1 */
411 .sht = &cmd64x_sht,
412 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
413 .pio_mask = 0x1f,
414 .mwdma_mask = 0x07,
415 .port_ops = &cmd646r1_port_ops
416 },
417 { /* CMD 648 */
418 .sht = &cmd64x_sht,
419 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
420 .pio_mask = 0x1f,
421 .mwdma_mask = 0x07,
422 .udma_mask = ATA_UDMA2,
423 .port_ops = &cmd648_port_ops
424 },
425 { /* CMD 649 */
426 .sht = &cmd64x_sht,
427 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
428 .pio_mask = 0x1f,
429 .mwdma_mask = 0x07,
430 .udma_mask = ATA_UDMA3,
431 .port_ops = &cmd648_port_ops
432 }
433 };
434 static struct ata_port_info *port_info[2], *info;
435 u8 mrdmode;
436
437 info = &cmd_info[id->driver_data];
438
439 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
440 class_rev &= 0xFF;
441
442 if (id->driver_data == 0) /* 643 */
443 ata_pci_clear_simplex(pdev);
444
445 if (pdev->device == PCI_DEVICE_ID_CMD_646) {
446 /* Does UDMA work ? */
447 if (class_rev > 4)
448 info = &cmd_info[2];
449 /* Early rev with other problems ? */
450 else if (class_rev == 1)
451 info = &cmd_info[3];
452 }
453
454 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
455 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
456 mrdmode &= ~ 0x30; /* IRQ set up */
457 mrdmode |= 0x02; /* Memory read line enable */
458 pci_write_config_byte(pdev, MRDMODE, mrdmode);
459
460 /* Force PIO 0 here.. */
461
462 /* PPC specific fixup copied from old driver */
463#ifdef CONFIG_PPC
464 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
465#endif
466
467 port_info[0] = port_info[1] = info;
468 return ata_pci_init_one(pdev, port_info, 2);
469}
470
471static struct pci_device_id cmd64x[] = {
472 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
473 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
474 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
475 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
476 { 0, },
477};
478
479static struct pci_driver cmd64x_pci_driver = {
480 .name = DRV_NAME,
481 .id_table = cmd64x,
482 .probe = cmd64x_init_one,
483 .remove = ata_pci_remove_one
484};
485
486static int __init cmd64x_init(void)
487{
488 return pci_register_driver(&cmd64x_pci_driver);
489}
490
491
492static void __exit cmd64x_exit(void)
493{
494 pci_unregister_driver(&cmd64x_pci_driver);
495}
496
497
498MODULE_AUTHOR("Alan Cox");
499MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
500MODULE_LICENSE("GPL");
501MODULE_DEVICE_TABLE(pci, cmd64x);
502MODULE_VERSION(DRV_VERSION);
503
504module_init(cmd64x_init);
505module_exit(cmd64x_exit);
diff --git a/drivers/ata/pata_cs5520.c b/drivers/ata/pata_cs5520.c
new file mode 100644
index 00000000000..792ce482851
--- /dev/null
+++ b/drivers/ata/pata_cs5520.c
@@ -0,0 +1,336 @@
1/*
2 * IDE tuning and bus mastering support for the CS5510/CS5520
3 * chipsets
4 *
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
8 *
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information. Also to confuse matters
12 * further we can do DMA on PIO only drives.
13 *
14 * DMA on the 5510 also requires we disable_hlt() during DMA on early
15 * revisions.
16 *
17 * *** This driver is strictly experimental ***
18 *
19 * (c) Copyright Red Hat Inc 2002
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2, or (at your option) any
24 * later version.
25 *
26 * This program is distributed in the hope that it will be useful, but
27 * WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
29 * General Public License for more details.
30 *
31 * Documentation:
32 * Not publically available.
33 */
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <scsi/scsi_host.h>
41#include <linux/libata.h>
42
43#define DRV_NAME "pata_cs5520"
44#define DRV_VERSION "0.6.2"
45
46struct pio_clocks
47{
48 int address;
49 int assert;
50 int recovery;
51};
52
53static const struct pio_clocks cs5520_pio_clocks[]={
54 {3, 6, 11},
55 {2, 5, 6},
56 {1, 4, 3},
57 {1, 3, 2},
58 {1, 2, 1}
59};
60
61/**
62 * cs5520_set_timings - program PIO timings
63 * @ap: ATA port
64 * @adev: ATA device
65 *
66 * Program the PIO mode timings for the controller according to the pio
67 * clocking table.
68 */
69
70static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
71{
72 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
73 int slave = adev->devno;
74
75 pio -= XFER_PIO_0;
76
77 /* Channel command timing */
78 pci_write_config_byte(pdev, 0x62 + ap->port_no,
79 (cs5520_pio_clocks[pio].recovery << 4) |
80 (cs5520_pio_clocks[pio].assert));
81 /* FIXME: should these use address ? */
82 /* Read command timing */
83 pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave,
84 (cs5520_pio_clocks[pio].recovery << 4) |
85 (cs5520_pio_clocks[pio].assert));
86 /* Write command timing */
87 pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave,
88 (cs5520_pio_clocks[pio].recovery << 4) |
89 (cs5520_pio_clocks[pio].assert));
90}
91
92/**
93 * cs5520_enable_dma - turn on DMA bits
94 *
95 * Turn on the DMA bits for this disk. Needed because the BIOS probably
96 * has not done the work for us. Belongs in the core SATA code.
97 */
98
99static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev)
100{
101 /* Set the DMA enable/disable flag */
102 u8 reg = inb(ap->ioaddr.bmdma_addr + 0x02);
103 reg |= 1<<(adev->devno + 5);
104 outb(reg, ap->ioaddr.bmdma_addr + 0x02);
105}
106
107/**
108 * cs5520_set_dmamode - program DMA timings
109 * @ap: ATA port
110 * @adev: ATA device
111 *
112 * Program the DMA mode timings for the controller according to the pio
113 * clocking table. Note that this device sets the DMA timings to PIO
114 * mode values. This may seem bizarre but the 5520 architecture talks
115 * PIO mode to the disk and DMA mode to the controller so the underlying
116 * transfers are PIO timed.
117 */
118
119static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev)
120{
121 static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
122 cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
123 cs5520_enable_dma(ap, adev);
124}
125
126/**
127 * cs5520_set_piomode - program PIO timings
128 * @ap: ATA port
129 * @adev: ATA device
130 *
131 * Program the PIO mode timings for the controller according to the pio
132 * clocking table. We know pio_mode will equal dma_mode because of the
133 * CS5520 architecture. At least once we turned DMA on and wrote a
134 * mode setter.
135 */
136
137static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
138{
139 cs5520_set_timings(ap, adev, adev->pio_mode);
140}
141
142
143static int cs5520_pre_reset(struct ata_port *ap)
144{
145 ap->cbl = ATA_CBL_PATA40;
146 return ata_std_prereset(ap);
147}
148
149static void cs5520_error_handler(struct ata_port *ap)
150{
151 return ata_bmdma_drive_eh(ap, cs5520_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
152}
153
154static struct scsi_host_template cs5520_sht = {
155 .module = THIS_MODULE,
156 .name = DRV_NAME,
157 .ioctl = ata_scsi_ioctl,
158 .queuecommand = ata_scsi_queuecmd,
159 .can_queue = ATA_DEF_QUEUE,
160 .this_id = ATA_SHT_THIS_ID,
161 .sg_tablesize = LIBATA_MAX_PRD,
162 .max_sectors = ATA_MAX_SECTORS,
163 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
164 .emulated = ATA_SHT_EMULATED,
165 .use_clustering = ATA_SHT_USE_CLUSTERING,
166 .proc_name = DRV_NAME,
167 .dma_boundary = ATA_DMA_BOUNDARY,
168 .slave_configure = ata_scsi_slave_config,
169 .bios_param = ata_std_bios_param,
170};
171
172static struct ata_port_operations cs5520_port_ops = {
173 .port_disable = ata_port_disable,
174 .set_piomode = cs5520_set_piomode,
175 .set_dmamode = cs5520_set_dmamode,
176
177 .tf_load = ata_tf_load,
178 .tf_read = ata_tf_read,
179 .check_status = ata_check_status,
180 .exec_command = ata_exec_command,
181 .dev_select = ata_std_dev_select,
182
183 .freeze = ata_bmdma_freeze,
184 .thaw = ata_bmdma_thaw,
185 .error_handler = cs5520_error_handler,
186 .post_internal_cmd = ata_bmdma_post_internal_cmd,
187
188 .bmdma_setup = ata_bmdma_setup,
189 .bmdma_start = ata_bmdma_start,
190 .bmdma_stop = ata_bmdma_stop,
191 .bmdma_status = ata_bmdma_status,
192 .qc_prep = ata_qc_prep,
193 .qc_issue = ata_qc_issue_prot,
194 .data_xfer = ata_pio_data_xfer,
195
196 .eng_timeout = ata_eng_timeout,
197
198 .irq_handler = ata_interrupt,
199 .irq_clear = ata_bmdma_irq_clear,
200
201 .port_start = ata_port_start,
202 .port_stop = ata_port_stop,
203 .host_stop = ata_host_stop,
204};
205
206static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
207{
208 u8 pcicfg;
209 static struct ata_probe_ent probe[2];
210 int ports = 0;
211
212 /* IDE port enable bits */
213 pci_read_config_byte(dev, 0x60, &pcicfg);
214
215 /* Check if the ATA ports are enabled */
216 if ((pcicfg & 3) == 0)
217 return -ENODEV;
218
219 if ((pcicfg & 0x40) == 0) {
220 printk(KERN_WARNING DRV_NAME ": DMA mode disabled. Enabling.\n");
221 pci_write_config_byte(dev, 0x60, pcicfg | 0x40);
222 }
223
224 /* Perform set up for DMA */
225 if (pci_enable_device_bars(dev, 1<<2)) {
226 printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
227 return -ENODEV;
228 }
229 pci_set_master(dev);
230 if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
231 printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
232 return -ENODEV;
233 }
234 if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) {
235 printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
236 return -ENODEV;
237 }
238
239 /* We have to do our own plumbing as the PCI setup for this
240 chipset is non-standard so we can't punt to the libata code */
241
242 INIT_LIST_HEAD(&probe[0].node);
243 probe[0].dev = pci_dev_to_dev(dev);
244 probe[0].port_ops = &cs5520_port_ops;
245 probe[0].sht = &cs5520_sht;
246 probe[0].pio_mask = 0x1F;
247 probe[0].mwdma_mask = id->driver_data;
248 probe[0].irq = 14;
249 probe[0].irq_flags = 0;
250 probe[0].port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
251 probe[0].n_ports = 1;
252 probe[0].port[0].cmd_addr = 0x1F0;
253 probe[0].port[0].ctl_addr = 0x3F6;
254 probe[0].port[0].altstatus_addr = 0x3F6;
255 probe[0].port[0].bmdma_addr = pci_resource_start(dev, 2);
256
257 /* The secondary lurks at different addresses but is otherwise
258 the same beastie */
259
260 probe[1] = probe[0];
261 INIT_LIST_HEAD(&probe[1].node);
262 probe[1].irq = 15;
263 probe[1].port[0].cmd_addr = 0x170;
264 probe[1].port[0].ctl_addr = 0x376;
265 probe[1].port[0].altstatus_addr = 0x376;
266 probe[1].port[0].bmdma_addr = pci_resource_start(dev, 2) + 8;
267
268 /* Let libata fill in the port details */
269 ata_std_ports(&probe[0].port[0]);
270 ata_std_ports(&probe[1].port[0]);
271
272 /* Now add the ports that are active */
273 if (pcicfg & 1)
274 ports += ata_device_add(&probe[0]);
275 if (pcicfg & 2)
276 ports += ata_device_add(&probe[1]);
277 if (ports)
278 return 0;
279 return -ENODEV;
280}
281
282/**
283 * cs5520_remove_one - device unload
284 * @pdev: PCI device being removed
285 *
286 * Handle an unplug/unload event for a PCI device. Unload the
287 * PCI driver but do not use the default handler as we manage
288 * resources ourself and *MUST NOT* disable the device as it has
289 * other functions.
290 */
291
292static void __devexit cs5520_remove_one(struct pci_dev *pdev)
293{
294 struct device *dev = pci_dev_to_dev(pdev);
295 struct ata_host *host = dev_get_drvdata(dev);
296
297 ata_host_remove(host);
298 dev_set_drvdata(dev, NULL);
299}
300
301/* For now keep DMA off. We can set it for all but A rev CS5510 once the
302 core ATA code can handle it */
303
304static struct pci_device_id pata_cs5520[] = {
305 { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
306 { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
307 { 0, },
308};
309
310static struct pci_driver cs5520_pci_driver = {
311 .name = DRV_NAME,
312 .id_table = pata_cs5520,
313 .probe = cs5520_init_one,
314 .remove = cs5520_remove_one
315};
316
317
318static int __init cs5520_init(void)
319{
320 return pci_register_driver(&cs5520_pci_driver);
321}
322
323static void __exit cs5520_exit(void)
324{
325 pci_unregister_driver(&cs5520_pci_driver);
326}
327
328MODULE_AUTHOR("Alan Cox");
329MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
330MODULE_LICENSE("GPL");
331MODULE_DEVICE_TABLE(pci, pata_cs5520);
332MODULE_VERSION(DRV_VERSION);
333
334module_init(cs5520_init);
335module_exit(cs5520_exit);
336
diff --git a/drivers/ata/pata_cs5530.c b/drivers/ata/pata_cs5530.c
new file mode 100644
index 00000000000..f3d8a3bc1e7
--- /dev/null
+++ b/drivers/ata/pata_cs5530.c
@@ -0,0 +1,387 @@
1/*
2 * pata-cs5530.c - CS5530 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon cs5530.c by Mark Lord.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * Loosely based on the piix & svwks drivers.
22 *
23 * Documentation:
24 * Available from AMD web site.
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/delay.h>
33#include <scsi/scsi_host.h>
34#include <linux/libata.h>
35#include <linux/dmi.h>
36
37#define DRV_NAME "pata_cs5530"
38#define DRV_VERSION "0.6"
39
40/**
41 * cs5530_set_piomode - PIO setup
42 * @ap: ATA interface
43 * @adev: device on the interface
44 *
45 * Set our PIO requirements. This is fairly simple on the CS5530
46 * chips.
47 */
48
49static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
50{
51 static const unsigned int cs5530_pio_timings[2][5] = {
52 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
53 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
54 };
55 unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no;
56 u32 tuning;
57 int format;
58
59 /* Find out which table to use */
60 tuning = inl(base + 0x04);
61 format = (tuning & 0x80000000UL) ? 1 : 0;
62
63 /* Now load the right timing register */
64 if (adev->devno)
65 base += 0x08;
66
67 outl(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
68}
69
70/**
71 * cs5530_set_dmamode - DMA timing setup
72 * @ap: ATA interface
73 * @adev: Device being configured
74 *
75 * We cannot mix MWDMA and UDMA without reloading timings each switch
76 * master to slave. We track the last DMA setup in order to minimise
77 * reloads.
78 */
79
80static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
81{
82 unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no;
83 u32 tuning, timing = 0;
84 u8 reg;
85
86 /* Find out which table to use */
87 tuning = inl(base + 0x04);
88
89 switch(adev->dma_mode) {
90 case XFER_UDMA_0:
91 timing = 0x00921250;break;
92 case XFER_UDMA_1:
93 timing = 0x00911140;break;
94 case XFER_UDMA_2:
95 timing = 0x00911030;break;
96 case XFER_MW_DMA_0:
97 timing = 0x00077771;break;
98 case XFER_MW_DMA_1:
99 timing = 0x00012121;break;
100 case XFER_MW_DMA_2:
101 timing = 0x00002020;break;
102 default:
103 BUG();
104 }
105 /* Merge in the PIO format bit */
106 timing |= (tuning & 0x80000000UL);
107 if (adev->devno == 0) /* Master */
108 outl(timing, base + 0x04);
109 else {
110 if (timing & 0x00100000)
111 tuning |= 0x00100000; /* UDMA for both */
112 else
113 tuning &= ~0x00100000; /* MWDMA for both */
114 outl(tuning, base + 0x04);
115 outl(timing, base + 0x0C);
116 }
117
118 /* Set the DMA capable bit in the BMDMA area */
119 reg = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
120 reg |= (1 << (5 + adev->devno));
121 outb(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
122
123 /* Remember the last DMA setup we did */
124
125 ap->private_data = adev;
126}
127
128/**
129 * cs5530_qc_issue_prot - command issue
130 * @qc: command pending
131 *
132 * Called when the libata layer is about to issue a command. We wrap
133 * this interface so that we can load the correct ATA timings if
134 * neccessary. Specifically we have a problem that there is only
135 * one MWDMA/UDMA bit.
136 */
137
138static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc)
139{
140 struct ata_port *ap = qc->ap;
141 struct ata_device *adev = qc->dev;
142 struct ata_device *prev = ap->private_data;
143
144 /* See if the DMA settings could be wrong */
145 if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
146 /* Maybe, but do the channels match MWDMA/UDMA ? */
147 if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) ||
148 (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
149 /* Switch the mode bits */
150 cs5530_set_dmamode(ap, adev);
151 }
152
153 return ata_qc_issue_prot(qc);
154}
155
156static int cs5530_pre_reset(struct ata_port *ap)
157{
158 ap->cbl = ATA_CBL_PATA40;
159 return ata_std_prereset(ap);
160}
161
162static void cs5530_error_handler(struct ata_port *ap)
163{
164 return ata_bmdma_drive_eh(ap, cs5530_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
165}
166
167
168static struct scsi_host_template cs5530_sht = {
169 .module = THIS_MODULE,
170 .name = DRV_NAME,
171 .ioctl = ata_scsi_ioctl,
172 .queuecommand = ata_scsi_queuecmd,
173 .can_queue = ATA_DEF_QUEUE,
174 .this_id = ATA_SHT_THIS_ID,
175 .sg_tablesize = LIBATA_MAX_PRD,
176 .max_sectors = ATA_MAX_SECTORS,
177 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
178 .emulated = ATA_SHT_EMULATED,
179 .use_clustering = ATA_SHT_USE_CLUSTERING,
180 .proc_name = DRV_NAME,
181 .dma_boundary = ATA_DMA_BOUNDARY,
182 .slave_configure = ata_scsi_slave_config,
183 .bios_param = ata_std_bios_param,
184};
185
186static struct ata_port_operations cs5530_port_ops = {
187 .port_disable = ata_port_disable,
188 .set_piomode = cs5530_set_piomode,
189 .set_dmamode = cs5530_set_dmamode,
190 .mode_filter = ata_pci_default_filter,
191
192 .tf_load = ata_tf_load,
193 .tf_read = ata_tf_read,
194 .check_status = ata_check_status,
195 .exec_command = ata_exec_command,
196 .dev_select = ata_std_dev_select,
197
198 .bmdma_setup = ata_bmdma_setup,
199 .bmdma_start = ata_bmdma_start,
200 .bmdma_stop = ata_bmdma_stop,
201 .bmdma_status = ata_bmdma_status,
202
203 .freeze = ata_bmdma_freeze,
204 .thaw = ata_bmdma_thaw,
205 .error_handler = cs5530_error_handler,
206 .post_internal_cmd = ata_bmdma_post_internal_cmd,
207
208 .qc_prep = ata_qc_prep,
209 .qc_issue = cs5530_qc_issue_prot,
210 .eng_timeout = ata_eng_timeout,
211 .data_xfer = ata_pio_data_xfer,
212
213 .irq_handler = ata_interrupt,
214 .irq_clear = ata_bmdma_irq_clear,
215
216 .port_start = ata_port_start,
217 .port_stop = ata_port_stop,
218 .host_stop = ata_host_stop
219};
220
221static struct dmi_system_id palmax_dmi_table[] = {
222 {
223 .ident = "Palmax PD1100",
224 .matches = {
225 DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
226 DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
227 },
228 },
229 { }
230};
231
232static int cs5530_is_palmax(void)
233{
234 if (dmi_check_system(palmax_dmi_table)) {
235 printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
236 return 1;
237 }
238 return 0;
239}
240
241/**
242 * cs5530_init_one - Initialise a CS5530
243 * @dev: PCI device
244 * @id: Entry in match table
245 *
246 * Install a driver for the newly found CS5530 companion chip. Most of
247 * this is just housekeeping. We have to set the chip up correctly and
248 * turn off various bits of emulation magic.
249 */
250
251static int cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
252{
253 int compiler_warning_pointless_fix;
254 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
255 static struct ata_port_info info = {
256 .sht = &cs5530_sht,
257 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
258 .pio_mask = 0x1f,
259 .mwdma_mask = 0x07,
260 .udma_mask = 0x07,
261 .port_ops = &cs5530_port_ops
262 };
263 /* The docking connector doesn't do UDMA, and it seems not MWDMA */
264 static struct ata_port_info info_palmax_secondary = {
265 .sht = &cs5530_sht,
266 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
267 .pio_mask = 0x1f,
268 .port_ops = &cs5530_port_ops
269 };
270 static struct ata_port_info *port_info[2] = { &info, &info };
271
272 dev = NULL;
273 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
274 switch (dev->device) {
275 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
276 master_0 = pci_dev_get(dev);
277 break;
278 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
279 cs5530_0 = pci_dev_get(dev);
280 break;
281 }
282 }
283 if (!master_0) {
284 printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
285 goto fail_put;
286 }
287 if (!cs5530_0) {
288 printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
289 goto fail_put;
290 }
291
292 pci_set_master(cs5530_0);
293 compiler_warning_pointless_fix = pci_set_mwi(cs5530_0);
294
295 /*
296 * Set PCI CacheLineSize to 16-bytes:
297 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
298 *
299 * Note: This value is constant because the 5530 is only a Geode companion
300 */
301
302 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
303
304 /*
305 * Disable trapping of UDMA register accesses (Win98 hack):
306 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
307 */
308
309 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
310
311 /*
312 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
313 * The other settings are what is necessary to get the register
314 * into a sane state for IDE DMA operation.
315 */
316
317 pci_write_config_byte(master_0, 0x40, 0x1e);
318
319 /*
320 * Set max PCI burst size (16-bytes seems to work best):
321 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
322 * all others: clear bit-1 at 0x41, and do:
323 * 128bytes: OR 0x00 at 0x41
324 * 256bytes: OR 0x04 at 0x41
325 * 512bytes: OR 0x08 at 0x41
326 * 1024bytes: OR 0x0c at 0x41
327 */
328
329 pci_write_config_byte(master_0, 0x41, 0x14);
330
331 /*
332 * These settings are necessary to get the chip
333 * into a sane state for IDE DMA operation.
334 */
335
336 pci_write_config_byte(master_0, 0x42, 0x00);
337 pci_write_config_byte(master_0, 0x43, 0xc1);
338
339 pci_dev_put(master_0);
340 pci_dev_put(cs5530_0);
341
342 if (cs5530_is_palmax())
343 port_info[1] = &info_palmax_secondary;
344
345 /* Now kick off ATA set up */
346 return ata_pci_init_one(dev, port_info, 2);
347
348fail_put:
349 if (master_0)
350 pci_dev_put(master_0);
351 if (cs5530_0)
352 pci_dev_put(cs5530_0);
353 return -ENODEV;
354}
355
356static struct pci_device_id cs5530[] = {
357 { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
358 { 0, },
359};
360
361static struct pci_driver cs5530_pci_driver = {
362 .name = DRV_NAME,
363 .id_table = cs5530,
364 .probe = cs5530_init_one,
365 .remove = ata_pci_remove_one
366};
367
368static int __init cs5530_init(void)
369{
370 return pci_register_driver(&cs5530_pci_driver);
371}
372
373
374static void __exit cs5530_exit(void)
375{
376 pci_unregister_driver(&cs5530_pci_driver);
377}
378
379
380MODULE_AUTHOR("Alan Cox");
381MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
382MODULE_LICENSE("GPL");
383MODULE_DEVICE_TABLE(pci, cs5530);
384MODULE_VERSION(DRV_VERSION);
385
386module_init(cs5530_init);
387module_exit(cs5530_exit);
diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c
new file mode 100644
index 00000000000..69d6b425872
--- /dev/null
+++ b/drivers/ata/pata_cs5535.c
@@ -0,0 +1,291 @@
1/*
2 * pata-cs5535.c - CS5535 PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
7 * made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de
8 * and Alexander Kiausch <alex.kiausch@t-online.de>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 * Loosely based on the piix & svwks drivers.
24 *
25 * Documentation:
26 * Available from AMD web site.
27 * TODO
28 * Review errata to see if serializing is neccessary
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/init.h>
35#include <linux/blkdev.h>
36#include <linux/delay.h>
37#include <scsi/scsi_host.h>
38#include <linux/libata.h>
39#include <asm/msr.h>
40
41#define DRV_NAME "cs5535"
42#define DRV_VERSION "0.2.10"
43
44/*
45 * The Geode (Aka Athlon GX now) uses an internal MSR based
46 * bus system for control. Demented but there you go.
47 */
48
49#define MSR_ATAC_BASE 0x51300000
50#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
51#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
52#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
53#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
54#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
55#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
56#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
57#define ATAC_RESET (MSR_ATAC_BASE+0x10)
58#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
59#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
60#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
61#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
62#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
63
64#define ATAC_BM0_CMD_PRIM 0x00
65#define ATAC_BM0_STS_PRIM 0x02
66#define ATAC_BM0_PRD 0x04
67
68#define CS5535_CABLE_DETECT 0x48
69
70#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 )
71
72/**
73 * cs5535_pre_reset - detect cable type
74 * @ap: Port to detect on
75 *
76 * Perform cable detection for ATA66 capable cable. Return a libata
77 * cable type.
78 */
79
80static int cs5535_pre_reset(struct ata_port *ap)
81{
82 u8 cable;
83 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
84
85 pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
86 if (cable & 1)
87 ap->cbl = ATA_CBL_PATA80;
88 else
89 ap->cbl = ATA_CBL_PATA40;
90 return ata_std_prereset(ap);
91}
92
93/**
94 * cs5535_error_handler - reset/probe
95 * @ap: Port to reset
96 *
97 * Reset and configure a port
98 */
99
100static void cs5535_error_handler(struct ata_port *ap)
101{
102 ata_bmdma_drive_eh(ap, cs5535_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
103}
104
105/**
106 * cs5535_set_piomode - PIO setup
107 * @ap: ATA interface
108 * @adev: device on the interface
109 *
110 * Set our PIO requirements. The CS5535 is pretty clean about all this
111 */
112
113static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
114{
115 static const u16 pio_timings[5] = {
116 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
117 };
118 static const u16 pio_cmd_timings[5] = {
119 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
120 };
121 u32 reg, dummy;
122 struct ata_device *pair = ata_dev_pair(adev);
123
124 int mode = adev->pio_mode - XFER_PIO_0;
125 int cmdmode = mode;
126
127 /* Command timing has to be for the lowest of the pair of devices */
128 if (pair) {
129 int pairmode = pair->pio_mode - XFER_PIO_0;
130 cmdmode = min(mode, pairmode);
131 /* Write the other drive timing register if it changed */
132 if (cmdmode < pairmode)
133 wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
134 pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0);
135 }
136 /* Write the drive timing register */
137 wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
138 pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0);
139
140 /* Set the PIO "format 1" bit in the DMA timing register */
141 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
142 wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
143}
144
145/**
146 * cs5535_set_dmamode - DMA timing setup
147 * @ap: ATA interface
148 * @adev: Device being configured
149 *
150 */
151
152static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
153{
154 static const u32 udma_timings[5] = {
155 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
156 };
157 static const u32 mwdma_timings[3] = {
158 0x7F0FFFF3, 0x7F035352, 0x7F024241
159 };
160 u32 reg, dummy;
161 int mode = adev->dma_mode;
162
163 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
164 reg &= 0x80000000UL;
165 if (mode >= XFER_UDMA_0)
166 reg |= udma_timings[mode - XFER_UDMA_0];
167 else
168 reg |= mwdma_timings[mode - XFER_MW_DMA_0];
169 wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
170}
171
172static struct scsi_host_template cs5535_sht = {
173 .module = THIS_MODULE,
174 .name = DRV_NAME,
175 .ioctl = ata_scsi_ioctl,
176 .queuecommand = ata_scsi_queuecmd,
177 .can_queue = ATA_DEF_QUEUE,
178 .this_id = ATA_SHT_THIS_ID,
179 .sg_tablesize = LIBATA_MAX_PRD,
180 .max_sectors = ATA_MAX_SECTORS,
181 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
182 .emulated = ATA_SHT_EMULATED,
183 .use_clustering = ATA_SHT_USE_CLUSTERING,
184 .proc_name = DRV_NAME,
185 .dma_boundary = ATA_DMA_BOUNDARY,
186 .slave_configure = ata_scsi_slave_config,
187 .bios_param = ata_std_bios_param,
188};
189
190static struct ata_port_operations cs5535_port_ops = {
191 .port_disable = ata_port_disable,
192 .set_piomode = cs5535_set_piomode,
193 .set_dmamode = cs5535_set_dmamode,
194 .mode_filter = ata_pci_default_filter,
195
196 .tf_load = ata_tf_load,
197 .tf_read = ata_tf_read,
198 .check_status = ata_check_status,
199 .exec_command = ata_exec_command,
200 .dev_select = ata_std_dev_select,
201
202 .freeze = ata_bmdma_freeze,
203 .thaw = ata_bmdma_thaw,
204 .error_handler = cs5535_error_handler,
205 .post_internal_cmd = ata_bmdma_post_internal_cmd,
206
207 .bmdma_setup = ata_bmdma_setup,
208 .bmdma_start = ata_bmdma_start,
209 .bmdma_stop = ata_bmdma_stop,
210 .bmdma_status = ata_bmdma_status,
211
212 .qc_prep = ata_qc_prep,
213 .qc_issue = ata_qc_issue_prot,
214 .eng_timeout = ata_eng_timeout,
215 .data_xfer = ata_pio_data_xfer,
216
217 .irq_handler = ata_interrupt,
218 .irq_clear = ata_bmdma_irq_clear,
219
220 .port_start = ata_port_start,
221 .port_stop = ata_port_stop,
222 .host_stop = ata_host_stop
223};
224
225/**
226 * cs5535_init_one - Initialise a CS5530
227 * @dev: PCI device
228 * @id: Entry in match table
229 *
230 * Install a driver for the newly found CS5530 companion chip. Most of
231 * this is just housekeeping. We have to set the chip up correctly and
232 * turn off various bits of emulation magic.
233 */
234
235static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
236{
237 static struct ata_port_info info = {
238 .sht = &cs5535_sht,
239 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
240 .pio_mask = 0x1f,
241 .mwdma_mask = 0x07,
242 .udma_mask = 0x1f,
243 .port_ops = &cs5535_port_ops
244 };
245 struct ata_port_info *ports[1] = { &info };
246
247 u32 timings, dummy;
248
249 /* Check the BIOS set the initial timing clock. If not set the
250 timings for PIO0 */
251 rdmsr(ATAC_CH0D0_PIO, timings, dummy);
252 if (CS5535_BAD_PIO(timings))
253 wrmsr(ATAC_CH0D0_PIO, 0xF7F4F7F4UL, 0);
254 rdmsr(ATAC_CH0D1_PIO, timings, dummy);
255 if (CS5535_BAD_PIO(timings))
256 wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
257 return ata_pci_init_one(dev, ports, 1);
258}
259
260static struct pci_device_id cs5535[] = {
261 { PCI_DEVICE(PCI_VENDOR_ID_NS, 0x002D), },
262 { 0, },
263};
264
265static struct pci_driver cs5535_pci_driver = {
266 .name = DRV_NAME,
267 .id_table = cs5535,
268 .probe = cs5535_init_one,
269 .remove = ata_pci_remove_one
270};
271
272static int __init cs5535_init(void)
273{
274 return pci_register_driver(&cs5535_pci_driver);
275}
276
277
278static void __exit cs5535_exit(void)
279{
280 pci_unregister_driver(&cs5535_pci_driver);
281}
282
283
284MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
285MODULE_DESCRIPTION("low-level driver for the NS/AMD 5530");
286MODULE_LICENSE("GPL");
287MODULE_DEVICE_TABLE(pci, cs5535);
288MODULE_VERSION(DRV_VERSION);
289
290module_init(cs5535_init);
291module_exit(cs5535_exit);
diff --git a/drivers/ata/pata_cypress.c b/drivers/ata/pata_cypress.c
new file mode 100644
index 00000000000..322043d8cf7
--- /dev/null
+++ b/drivers/ata/pata_cypress.c
@@ -0,0 +1,227 @@
1/*
2 * pata_cypress.c - Cypress PATA for new ATA layer
3 * (C) 2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based heavily on
7 * linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002
8 *
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/init.h>
15#include <linux/blkdev.h>
16#include <linux/delay.h>
17#include <scsi/scsi_host.h>
18#include <linux/libata.h>
19
20#define DRV_NAME "pata_cypress"
21#define DRV_VERSION "0.1.2"
22
23/* here are the offset definitions for the registers */
24
25enum {
26 CY82_IDE_CMDREG = 0x04,
27 CY82_IDE_ADDRSETUP = 0x48,
28 CY82_IDE_MASTER_IOR = 0x4C,
29 CY82_IDE_MASTER_IOW = 0x4D,
30 CY82_IDE_SLAVE_IOR = 0x4E,
31 CY82_IDE_SLAVE_IOW = 0x4F,
32 CY82_IDE_MASTER_8BIT = 0x50,
33 CY82_IDE_SLAVE_8BIT = 0x51,
34
35 CY82_INDEX_PORT = 0x22,
36 CY82_DATA_PORT = 0x23,
37
38 CY82_INDEX_CTRLREG1 = 0x01,
39 CY82_INDEX_CHANNEL0 = 0x30,
40 CY82_INDEX_CHANNEL1 = 0x31,
41 CY82_INDEX_TIMEOUT = 0x32
42};
43
44static int cy82c693_pre_reset(struct ata_port *ap)
45{
46 ap->cbl = ATA_CBL_PATA40;
47 return ata_std_prereset(ap);
48}
49
50static void cy82c693_error_handler(struct ata_port *ap)
51{
52 ata_bmdma_drive_eh(ap, cy82c693_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
53}
54
55/**
56 * cy82c693_set_piomode - set initial PIO mode data
57 * @ap: ATA interface
58 * @adev: ATA device
59 *
60 * Called to do the PIO mode setup.
61 */
62
63static void cy82c693_set_piomode(struct ata_port *ap, struct ata_device *adev)
64{
65 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
66 struct ata_timing t;
67 const unsigned long T = 1000000 / 33;
68 short time_16, time_8;
69 u32 addr;
70
71 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) {
72 printk(KERN_ERR DRV_NAME ": mome computation failed.\n");
73 return;
74 }
75
76 time_16 = FIT(t.recover, 0, 15) | (FIT(t.active, 0, 15) << 4);
77 time_8 = FIT(t.act8b, 0, 15) | (FIT(t.rec8b, 0, 15) << 4);
78
79 if (adev->devno == 0) {
80 pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
81
82 addr &= ~0x0F; /* Mask bits */
83 addr |= FIT(t.setup, 0, 15);
84
85 pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
86 pci_write_config_byte(pdev, CY82_IDE_MASTER_IOR, time_16);
87 pci_write_config_byte(pdev, CY82_IDE_MASTER_IOW, time_16);
88 pci_write_config_byte(pdev, CY82_IDE_MASTER_8BIT, time_8);
89 } else {
90 pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
91
92 addr &= ~0xF0; /* Mask bits */
93 addr |= (FIT(t.setup, 0, 15) << 4);
94
95 pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
96 pci_write_config_byte(pdev, CY82_IDE_SLAVE_IOR, time_16);
97 pci_write_config_byte(pdev, CY82_IDE_SLAVE_IOW, time_16);
98 pci_write_config_byte(pdev, CY82_IDE_SLAVE_8BIT, time_8);
99 }
100}
101
102/**
103 * cy82c693_set_dmamode - set initial DMA mode data
104 * @ap: ATA interface
105 * @adev: ATA device
106 *
107 * Called to do the DMA mode setup.
108 */
109
110static void cy82c693_set_dmamode(struct ata_port *ap, struct ata_device *adev)
111{
112 int reg = CY82_INDEX_CHANNEL0 + ap->port_no;
113
114 /* Be afraid, be very afraid. Magic registers in low I/O space */
115 outb(reg, 0x22);
116 outb(adev->dma_mode - XFER_MW_DMA_0, 0x23);
117
118 /* 0x50 gives the best behaviour on the Alpha's using this chip */
119 outb(CY82_INDEX_TIMEOUT, 0x22);
120 outb(0x50, 0x23);
121}
122
123static struct scsi_host_template cy82c693_sht = {
124 .module = THIS_MODULE,
125 .name = DRV_NAME,
126 .ioctl = ata_scsi_ioctl,
127 .queuecommand = ata_scsi_queuecmd,
128 .can_queue = ATA_DEF_QUEUE,
129 .this_id = ATA_SHT_THIS_ID,
130 .sg_tablesize = LIBATA_MAX_PRD,
131 .max_sectors = ATA_MAX_SECTORS,
132 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
133 .emulated = ATA_SHT_EMULATED,
134 .use_clustering = ATA_SHT_USE_CLUSTERING,
135 .proc_name = DRV_NAME,
136 .dma_boundary = ATA_DMA_BOUNDARY,
137 .slave_configure = ata_scsi_slave_config,
138 .bios_param = ata_std_bios_param,
139};
140
141static struct ata_port_operations cy82c693_port_ops = {
142 .port_disable = ata_port_disable,
143 .set_piomode = cy82c693_set_piomode,
144 .set_dmamode = cy82c693_set_dmamode,
145 .mode_filter = ata_pci_default_filter,
146
147 .tf_load = ata_tf_load,
148 .tf_read = ata_tf_read,
149 .check_status = ata_check_status,
150 .exec_command = ata_exec_command,
151 .dev_select = ata_std_dev_select,
152
153 .freeze = ata_bmdma_freeze,
154 .thaw = ata_bmdma_thaw,
155 .error_handler = cy82c693_error_handler,
156 .post_internal_cmd = ata_bmdma_post_internal_cmd,
157
158 .bmdma_setup = ata_bmdma_setup,
159 .bmdma_start = ata_bmdma_start,
160 .bmdma_stop = ata_bmdma_stop,
161 .bmdma_status = ata_bmdma_status,
162
163 .qc_prep = ata_qc_prep,
164 .qc_issue = ata_qc_issue_prot,
165 .eng_timeout = ata_eng_timeout,
166 .data_xfer = ata_pio_data_xfer,
167
168 .irq_handler = ata_interrupt,
169 .irq_clear = ata_bmdma_irq_clear,
170
171 .port_start = ata_port_start,
172 .port_stop = ata_port_stop,
173 .host_stop = ata_host_stop
174};
175
176static int cy82c693_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
177{
178 static struct ata_port_info info = {
179 .sht = &cy82c693_sht,
180 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
181 .pio_mask = 0x1f,
182 .mwdma_mask = 0x07,
183 .port_ops = &cy82c693_port_ops
184 };
185 static struct ata_port_info *port_info[1] = { &info };
186
187 /* Devfn 1 is the ATA primary. The secondary is magic and on devfn2. For the
188 moment we don't handle the secondary. FIXME */
189
190 if (PCI_FUNC(pdev->devfn) != 1)
191 return -ENODEV;
192
193 return ata_pci_init_one(pdev, port_info, 1);
194}
195
196static struct pci_device_id cy82c693[] = {
197 { PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
198 { 0, },
199};
200
201static struct pci_driver cy82c693_pci_driver = {
202 .name = DRV_NAME,
203 .id_table = cy82c693,
204 .probe = cy82c693_init_one,
205 .remove = ata_pci_remove_one
206};
207
208static int __init cy82c693_init(void)
209{
210 return pci_register_driver(&cy82c693_pci_driver);
211}
212
213
214static void __exit cy82c693_exit(void)
215{
216 pci_unregister_driver(&cy82c693_pci_driver);
217}
218
219
220MODULE_AUTHOR("Alan Cox");
221MODULE_DESCRIPTION("low-level driver for the CY82C693 PATA controller");
222MODULE_LICENSE("GPL");
223MODULE_DEVICE_TABLE(pci, cy82c693);
224MODULE_VERSION(DRV_VERSION);
225
226module_init(cy82c693_init);
227module_exit(cy82c693_exit);
diff --git a/drivers/ata/pata_efar.c b/drivers/ata/pata_efar.c
new file mode 100644
index 00000000000..c30bc181304
--- /dev/null
+++ b/drivers/ata/pata_efar.c
@@ -0,0 +1,342 @@
1/*
2 * pata_efar.c - EFAR PIIX clone controller driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
7 *
8 * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
9 * Intel ICH controllers the EFAR widened the UDMA mode register bits
10 * and doesn't require the funky clock selection.
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/blkdev.h>
18#include <linux/delay.h>
19#include <linux/device.h>
20#include <scsi/scsi_host.h>
21#include <linux/libata.h>
22#include <linux/ata.h>
23
24#define DRV_NAME "pata_efar"
25#define DRV_VERSION "0.4.1"
26
27/**
28 * efar_pre_reset - check for 40/80 pin
29 * @ap: Port
30 *
31 * Perform cable detection for the EFAR ATA interface. This is
32 * different to the PIIX arrangement
33 */
34
35static int efar_pre_reset(struct ata_port *ap)
36{
37 static const struct pci_bits efar_enable_bits[] = {
38 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
39 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
40 };
41
42 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
43 u8 tmp;
44
45 if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no])) {
46 ata_port_disable(ap);
47 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
48 return 0;
49 }
50 pci_read_config_byte(pdev, 0x47, &tmp);
51 if (tmp & (2 >> ap->port_no))
52 ap->cbl = ATA_CBL_PATA40;
53 else
54 ap->cbl = ATA_CBL_PATA80;
55 return ata_std_prereset(ap);
56}
57
58/**
59 * efar_probe_reset - Probe specified port on PATA host controller
60 * @ap: Port to probe
61 *
62 * LOCKING:
63 * None (inherited from caller).
64 */
65
66static void efar_error_handler(struct ata_port *ap)
67{
68 ata_bmdma_drive_eh(ap, efar_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
69}
70
71/**
72 * efar_set_piomode - Initialize host controller PATA PIO timings
73 * @ap: Port whose timings we are configuring
74 * @adev: um
75 *
76 * Set PIO mode for device, in host controller PCI config space.
77 *
78 * LOCKING:
79 * None (inherited from caller).
80 */
81
82static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
83{
84 unsigned int pio = adev->pio_mode - XFER_PIO_0;
85 struct pci_dev *dev = to_pci_dev(ap->host->dev);
86 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
87 u16 idetm_data;
88 int control = 0;
89
90 /*
91 * See Intel Document 298600-004 for the timing programing rules
92 * for PIIX/ICH. The EFAR is a clone so very similar
93 */
94
95 static const /* ISP RTC */
96 u8 timings[][2] = { { 0, 0 },
97 { 0, 0 },
98 { 1, 0 },
99 { 2, 1 },
100 { 2, 3 }, };
101
102 if (pio > 2)
103 control |= 1; /* TIME1 enable */
104 if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
105 control |= 2; /* IE enable */
106 /* Intel specifies that the PPE functionality is for disk only */
107 if (adev->class == ATA_DEV_ATA)
108 control |= 4; /* PPE enable */
109
110 pci_read_config_word(dev, idetm_port, &idetm_data);
111
112 /* Enable PPE, IE and TIME as appropriate */
113
114 if (adev->devno == 0) {
115 idetm_data &= 0xCCF0;
116 idetm_data |= control;
117 idetm_data |= (timings[pio][0] << 12) |
118 (timings[pio][1] << 8);
119 } else {
120 int shift = 4 * ap->port_no;
121 u8 slave_data;
122
123 idetm_data &= 0xCC0F;
124 idetm_data |= (control << 4);
125
126 /* Slave timing in seperate register */
127 pci_read_config_byte(dev, 0x44, &slave_data);
128 slave_data &= 0x0F << shift;
129 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
130 pci_write_config_byte(dev, 0x44, slave_data);
131 }
132
133 idetm_data |= 0x4000; /* Ensure SITRE is enabled */
134 pci_write_config_word(dev, idetm_port, idetm_data);
135}
136
137/**
138 * efar_set_dmamode - Initialize host controller PATA DMA timings
139 * @ap: Port whose timings we are configuring
140 * @adev: Device to program
141 *
142 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
143 *
144 * LOCKING:
145 * None (inherited from caller).
146 */
147
148static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
149{
150 struct pci_dev *dev = to_pci_dev(ap->host->dev);
151 u8 master_port = ap->port_no ? 0x42 : 0x40;
152 u16 master_data;
153 u8 speed = adev->dma_mode;
154 int devid = adev->devno + 2 * ap->port_no;
155 u8 udma_enable;
156
157 static const /* ISP RTC */
158 u8 timings[][2] = { { 0, 0 },
159 { 0, 0 },
160 { 1, 0 },
161 { 2, 1 },
162 { 2, 3 }, };
163
164 pci_read_config_word(dev, master_port, &master_data);
165 pci_read_config_byte(dev, 0x48, &udma_enable);
166
167 if (speed >= XFER_UDMA_0) {
168 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
169 u16 udma_timing;
170
171 udma_enable |= (1 << devid);
172
173 /* Load the UDMA mode number */
174 pci_read_config_word(dev, 0x4A, &udma_timing);
175 udma_timing &= ~(7 << (4 * devid));
176 udma_timing |= udma << (4 * devid);
177 pci_write_config_word(dev, 0x4A, udma_timing);
178 } else {
179 /*
180 * MWDMA is driven by the PIO timings. We must also enable
181 * IORDY unconditionally along with TIME1. PPE has already
182 * been set when the PIO timing was set.
183 */
184 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
185 unsigned int control;
186 u8 slave_data;
187 const unsigned int needed_pio[3] = {
188 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
189 };
190 int pio = needed_pio[mwdma] - XFER_PIO_0;
191
192 control = 3; /* IORDY|TIME1 */
193
194 /* If the drive MWDMA is faster than it can do PIO then
195 we must force PIO into PIO0 */
196
197 if (adev->pio_mode < needed_pio[mwdma])
198 /* Enable DMA timing only */
199 control |= 8; /* PIO cycles in PIO0 */
200
201 if (adev->devno) { /* Slave */
202 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
203 master_data |= control << 4;
204 pci_read_config_byte(dev, 0x44, &slave_data);
205 slave_data &= (0x0F + 0xE1 * ap->port_no);
206 /* Load the matching timing */
207 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
208 pci_write_config_byte(dev, 0x44, slave_data);
209 } else { /* Master */
210 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
211 and master timing bits */
212 master_data |= control;
213 master_data |=
214 (timings[pio][0] << 12) |
215 (timings[pio][1] << 8);
216 }
217 udma_enable &= ~(1 << devid);
218 pci_write_config_word(dev, master_port, master_data);
219 }
220 pci_write_config_byte(dev, 0x48, udma_enable);
221}
222
223static struct scsi_host_template efar_sht = {
224 .module = THIS_MODULE,
225 .name = DRV_NAME,
226 .ioctl = ata_scsi_ioctl,
227 .queuecommand = ata_scsi_queuecmd,
228 .can_queue = ATA_DEF_QUEUE,
229 .this_id = ATA_SHT_THIS_ID,
230 .sg_tablesize = LIBATA_MAX_PRD,
231 .max_sectors = ATA_MAX_SECTORS,
232 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
233 .emulated = ATA_SHT_EMULATED,
234 .use_clustering = ATA_SHT_USE_CLUSTERING,
235 .proc_name = DRV_NAME,
236 .dma_boundary = ATA_DMA_BOUNDARY,
237 .slave_configure = ata_scsi_slave_config,
238 .bios_param = ata_std_bios_param,
239};
240
241static const struct ata_port_operations efar_ops = {
242 .port_disable = ata_port_disable,
243 .set_piomode = efar_set_piomode,
244 .set_dmamode = efar_set_dmamode,
245 .mode_filter = ata_pci_default_filter,
246
247 .tf_load = ata_tf_load,
248 .tf_read = ata_tf_read,
249 .check_status = ata_check_status,
250 .exec_command = ata_exec_command,
251 .dev_select = ata_std_dev_select,
252
253 .freeze = ata_bmdma_freeze,
254 .thaw = ata_bmdma_thaw,
255 .error_handler = efar_error_handler,
256 .post_internal_cmd = ata_bmdma_post_internal_cmd,
257
258 .bmdma_setup = ata_bmdma_setup,
259 .bmdma_start = ata_bmdma_start,
260 .bmdma_stop = ata_bmdma_stop,
261 .bmdma_status = ata_bmdma_status,
262 .qc_prep = ata_qc_prep,
263 .qc_issue = ata_qc_issue_prot,
264 .data_xfer = ata_pio_data_xfer,
265
266 .eng_timeout = ata_eng_timeout,
267
268 .irq_handler = ata_interrupt,
269 .irq_clear = ata_bmdma_irq_clear,
270
271 .port_start = ata_port_start,
272 .port_stop = ata_port_stop,
273 .host_stop = ata_host_stop,
274};
275
276
277/**
278 * efar_init_one - Register EFAR ATA PCI device with kernel services
279 * @pdev: PCI device to register
280 * @ent: Entry in efar_pci_tbl matching with @pdev
281 *
282 * Called from kernel PCI layer.
283 *
284 * LOCKING:
285 * Inherited from PCI layer (may sleep).
286 *
287 * RETURNS:
288 * Zero on success, or -ERRNO value.
289 */
290
291static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
292{
293 static int printed_version;
294 static struct ata_port_info info = {
295 .sht = &efar_sht,
296 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
297 .pio_mask = 0x1f, /* pio0-4 */
298 .mwdma_mask = 0x07, /* mwdma1-2 */
299 .udma_mask = 0x0f, /* UDMA 66 */
300 .port_ops = &efar_ops,
301 };
302 static struct ata_port_info *port_info[2] = { &info, &info };
303
304 if (!printed_version++)
305 dev_printk(KERN_DEBUG, &pdev->dev,
306 "version " DRV_VERSION "\n");
307
308 return ata_pci_init_one(pdev, port_info, 2);
309}
310
311static const struct pci_device_id efar_pci_tbl[] = {
312 { 0x1055, 0x9130, PCI_ANY_ID, PCI_ANY_ID, },
313 { } /* terminate list */
314};
315
316static struct pci_driver efar_pci_driver = {
317 .name = DRV_NAME,
318 .id_table = efar_pci_tbl,
319 .probe = efar_init_one,
320 .remove = ata_pci_remove_one,
321};
322
323static int __init efar_init(void)
324{
325 return pci_register_driver(&efar_pci_driver);
326}
327
328static void __exit efar_exit(void)
329{
330 pci_unregister_driver(&efar_pci_driver);
331}
332
333
334module_init(efar_init);
335module_exit(efar_exit);
336
337MODULE_AUTHOR("Alan Cox");
338MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
339MODULE_LICENSE("GPL");
340MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
341MODULE_VERSION(DRV_VERSION);
342
diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c
new file mode 100644
index 00000000000..e54a0c51681
--- /dev/null
+++ b/drivers/ata/pata_hpt366.c
@@ -0,0 +1,478 @@
1/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
14 * Maybe PLL mode
15 * Look into engine reset on timeout errors. Should not be
16 * required.
17 */
18
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28
29#define DRV_NAME "pata_hpt366"
30#define DRV_VERSION "0.5"
31
32struct hpt_clock {
33 u8 xfer_speed;
34 u32 timing;
35};
36
37/* key for bus clock timings
38 * bit
39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 * DMA. cycles = value + 1
41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 * DMA. cycles = value + 1
43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 * register access.
45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
46 * register access.
47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 * during task file register access.
49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 * xfer.
51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 * register access.
53 * 28 UDMA enable
54 * 29 DMA enable
55 * 30 PIO_MST enable. if set, the chip is in bus master mode during
56 * PIO.
57 * 31 FIFO enable.
58 */
59
60static const struct hpt_clock hpt366_40[] = {
61 { XFER_UDMA_4, 0x900fd943 },
62 { XFER_UDMA_3, 0x900ad943 },
63 { XFER_UDMA_2, 0x900bd943 },
64 { XFER_UDMA_1, 0x9008d943 },
65 { XFER_UDMA_0, 0x9008d943 },
66
67 { XFER_MW_DMA_2, 0xa008d943 },
68 { XFER_MW_DMA_1, 0xa010d955 },
69 { XFER_MW_DMA_0, 0xa010d9fc },
70
71 { XFER_PIO_4, 0xc008d963 },
72 { XFER_PIO_3, 0xc010d974 },
73 { XFER_PIO_2, 0xc010d997 },
74 { XFER_PIO_1, 0xc010d9c7 },
75 { XFER_PIO_0, 0xc018d9d9 },
76 { 0, 0x0120d9d9 }
77};
78
79static const struct hpt_clock hpt366_33[] = {
80 { XFER_UDMA_4, 0x90c9a731 },
81 { XFER_UDMA_3, 0x90cfa731 },
82 { XFER_UDMA_2, 0x90caa731 },
83 { XFER_UDMA_1, 0x90cba731 },
84 { XFER_UDMA_0, 0x90c8a731 },
85
86 { XFER_MW_DMA_2, 0xa0c8a731 },
87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88 { XFER_MW_DMA_0, 0xa0c8a797 },
89
90 { XFER_PIO_4, 0xc0c8a731 },
91 { XFER_PIO_3, 0xc0c8a742 },
92 { XFER_PIO_2, 0xc0d0a753 },
93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
95 { 0, 0x0120a7a7 }
96};
97
98static const struct hpt_clock hpt366_25[] = {
99 { XFER_UDMA_4, 0x90c98521 },
100 { XFER_UDMA_3, 0x90cf8521 },
101 { XFER_UDMA_2, 0x90cf8521 },
102 { XFER_UDMA_1, 0x90cb8521 },
103 { XFER_UDMA_0, 0x90cb8521 },
104
105 { XFER_MW_DMA_2, 0xa0ca8521 },
106 { XFER_MW_DMA_1, 0xa0ca8532 },
107 { XFER_MW_DMA_0, 0xa0ca8575 },
108
109 { XFER_PIO_4, 0xc0ca8521 },
110 { XFER_PIO_3, 0xc0ca8532 },
111 { XFER_PIO_2, 0xc0ca8542 },
112 { XFER_PIO_1, 0xc0d08572 },
113 { XFER_PIO_0, 0xc0d08585 },
114 { 0, 0x01208585 }
115};
116
117static const char *bad_ata33[] = {
118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121 "Maxtor 90510D4",
122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125 NULL
126};
127
128static const char *bad_ata66_4[] = {
129 "IBM-DTLA-307075",
130 "IBM-DTLA-307060",
131 "IBM-DTLA-307045",
132 "IBM-DTLA-307030",
133 "IBM-DTLA-307020",
134 "IBM-DTLA-307015",
135 "IBM-DTLA-305040",
136 "IBM-DTLA-305030",
137 "IBM-DTLA-305020",
138 "IC35L010AVER07-0",
139 "IC35L020AVER07-0",
140 "IC35L030AVER07-0",
141 "IC35L040AVER07-0",
142 "IC35L060AVER07-0",
143 "WDC AC310200R",
144 NULL
145};
146
147static const char *bad_ata66_3[] = {
148 "WDC AC310200R",
149 NULL
150};
151
152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
153{
154 unsigned char model_num[40];
155 char *s;
156 unsigned int len;
157 int i = 0;
158
159 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
160 s = &model_num[0];
161 len = strnlen(s, sizeof(model_num));
162
163 /* ATAPI specifies that empty space is blank-filled; remove blanks */
164 while ((len > 0) && (s[len - 1] == ' ')) {
165 len--;
166 s[len] = 0;
167 }
168
169 while(list[i] != NULL) {
170 if (!strncmp(list[i], s, len)) {
171 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
172 modestr, list[i]);
173 return 1;
174 }
175 i++;
176 }
177 return 0;
178}
179
180/**
181 * hpt366_filter - mode selection filter
182 * @ap: ATA interface
183 * @adev: ATA device
184 *
185 * Block UDMA on devices that cause trouble with this controller.
186 */
187
188static unsigned long hpt366_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
189{
190 if (adev->class == ATA_DEV_ATA) {
191 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
192 mask &= ~ATA_MASK_UDMA;
193 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
194 mask &= ~(0x07 << ATA_SHIFT_UDMA);
195 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
196 mask &= ~(0x0F << ATA_SHIFT_UDMA);
197 }
198 return ata_pci_default_filter(ap, adev, mask);
199}
200
201/**
202 * hpt36x_find_mode - reset the hpt36x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
209
210static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
211{
212 struct hpt_clock *clocks = ap->host->private_data;
213
214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221}
222
223static int hpt36x_pre_reset(struct ata_port *ap)
224{
225 u8 ata66;
226 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
227
228 pci_read_config_byte(pdev, 0x5A, &ata66);
229 if (ata66 & (1 << ap->port_no))
230 ap->cbl = ATA_CBL_PATA40;
231 else
232 ap->cbl = ATA_CBL_PATA80;
233 return ata_std_prereset(ap);
234}
235
236/**
237 * hpt36x_error_handler - reset the hpt36x bus
238 * @ap: ATA port to reset
239 *
240 * Perform the reset handling for the 366/368
241 */
242
243static void hpt36x_error_handler(struct ata_port *ap)
244{
245 ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
246}
247
248/**
249 * hpt366_set_piomode - PIO setup
250 * @ap: ATA interface
251 * @adev: device on the interface
252 *
253 * Perform PIO mode setup.
254 */
255
256static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
257{
258 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
259 u32 addr1, addr2;
260 u32 reg;
261 u32 mode;
262 u8 fast;
263
264 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
265 addr2 = 0x51 + 4 * ap->port_no;
266
267 /* Fast interrupt prediction disable, hold off interrupt disable */
268 pci_read_config_byte(pdev, addr2, &fast);
269 if (fast & 0x80) {
270 fast &= ~0x80;
271 pci_write_config_byte(pdev, addr2, fast);
272 }
273
274 pci_read_config_dword(pdev, addr1, &reg);
275 mode = hpt36x_find_mode(ap, adev->pio_mode);
276 mode &= ~0x8000000; /* No FIFO in PIO */
277 mode &= ~0x30070000; /* Leave config bits alone */
278 reg &= 0x30070000; /* Strip timing bits */
279 pci_write_config_dword(pdev, addr1, reg | mode);
280}
281
282/**
283 * hpt366_set_dmamode - DMA timing setup
284 * @ap: ATA interface
285 * @adev: Device being configured
286 *
287 * Set up the channel for MWDMA or UDMA modes. Much the same as with
288 * PIO, load the mode number and then set MWDMA or UDMA flag.
289 */
290
291static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
292{
293 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
294 u32 addr1, addr2;
295 u32 reg;
296 u32 mode;
297 u8 fast;
298
299 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
300 addr2 = 0x51 + 4 * ap->port_no;
301
302 /* Fast interrupt prediction disable, hold off interrupt disable */
303 pci_read_config_byte(pdev, addr2, &fast);
304 if (fast & 0x80) {
305 fast &= ~0x80;
306 pci_write_config_byte(pdev, addr2, fast);
307 }
308
309 pci_read_config_dword(pdev, addr1, &reg);
310 mode = hpt36x_find_mode(ap, adev->dma_mode);
311 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
312 mode &= ~0xC0000000; /* Leave config bits alone */
313 reg &= 0xC0000000; /* Strip timing bits */
314 pci_write_config_dword(pdev, addr1, reg | mode);
315}
316
317static struct scsi_host_template hpt36x_sht = {
318 .module = THIS_MODULE,
319 .name = DRV_NAME,
320 .ioctl = ata_scsi_ioctl,
321 .queuecommand = ata_scsi_queuecmd,
322 .can_queue = ATA_DEF_QUEUE,
323 .this_id = ATA_SHT_THIS_ID,
324 .sg_tablesize = LIBATA_MAX_PRD,
325 .max_sectors = ATA_MAX_SECTORS,
326 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
327 .emulated = ATA_SHT_EMULATED,
328 .use_clustering = ATA_SHT_USE_CLUSTERING,
329 .proc_name = DRV_NAME,
330 .dma_boundary = ATA_DMA_BOUNDARY,
331 .slave_configure = ata_scsi_slave_config,
332 .bios_param = ata_std_bios_param,
333};
334
335/*
336 * Configuration for HPT366/68
337 */
338
339static struct ata_port_operations hpt366_port_ops = {
340 .port_disable = ata_port_disable,
341 .set_piomode = hpt366_set_piomode,
342 .set_dmamode = hpt366_set_dmamode,
343 .mode_filter = hpt366_filter,
344
345 .tf_load = ata_tf_load,
346 .tf_read = ata_tf_read,
347 .check_status = ata_check_status,
348 .exec_command = ata_exec_command,
349 .dev_select = ata_std_dev_select,
350
351 .freeze = ata_bmdma_freeze,
352 .thaw = ata_bmdma_thaw,
353 .error_handler = hpt36x_error_handler,
354 .post_internal_cmd = ata_bmdma_post_internal_cmd,
355
356 .bmdma_setup = ata_bmdma_setup,
357 .bmdma_start = ata_bmdma_start,
358 .bmdma_stop = ata_bmdma_stop,
359 .bmdma_status = ata_bmdma_status,
360
361 .qc_prep = ata_qc_prep,
362 .qc_issue = ata_qc_issue_prot,
363 .eng_timeout = ata_eng_timeout,
364 .data_xfer = ata_pio_data_xfer,
365
366 .irq_handler = ata_interrupt,
367 .irq_clear = ata_bmdma_irq_clear,
368
369 .port_start = ata_port_start,
370 .port_stop = ata_port_stop,
371 .host_stop = ata_host_stop
372};
373
374/**
375 * hpt36x_init_one - Initialise an HPT366/368
376 * @dev: PCI device
377 * @id: Entry in match table
378 *
379 * Initialise an HPT36x device. There are some interesting complications
380 * here. Firstly the chip may report 366 and be one of several variants.
381 * Secondly all the timings depend on the clock for the chip which we must
382 * detect and look up
383 *
384 * This is the known chip mappings. It may be missing a couple of later
385 * releases.
386 *
387 * Chip version PCI Rev Notes
388 * HPT366 4 (HPT366) 0 UDMA66
389 * HPT366 4 (HPT366) 1 UDMA66
390 * HPT368 4 (HPT366) 2 UDMA66
391 * HPT37x/30x 4 (HPT366) 3+ Other driver
392 *
393 */
394
395static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
396{
397 static struct ata_port_info info_hpt366 = {
398 .sht = &hpt36x_sht,
399 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
400 .pio_mask = 0x1f,
401 .mwdma_mask = 0x07,
402 .udma_mask = 0x1f,
403 .port_ops = &hpt366_port_ops
404 };
405 struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366};
406
407 u32 class_rev;
408 u32 reg1;
409 u8 drive_fast;
410
411 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
412 class_rev &= 0xFF;
413
414 /* May be a later chip in disguise. Check */
415 /* Newer chips are not in the HPT36x driver. Ignore them */
416 if (class_rev > 2)
417 return -ENODEV;
418
419 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
420 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
421 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
422 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
423
424 pci_read_config_byte(dev, 0x51, &drive_fast);
425 if (drive_fast & 0x80)
426 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
427
428 pci_read_config_dword(dev, 0x40, &reg1);
429
430 /* PCI clocking determines the ATA timing values to use */
431 /* info_hpt366 is safe against re-entry so we can scribble on it */
432 switch(reg1 & 0x700) {
433 case 5:
434 info_hpt366.private_data = &hpt366_40;
435 break;
436 case 9:
437 info_hpt366.private_data = &hpt366_25;
438 break;
439 default:
440 info_hpt366.private_data = &hpt366_33;
441 break;
442 }
443 /* Now kick off ATA set up */
444 return ata_pci_init_one(dev, port_info, 2);
445}
446
447static struct pci_device_id hpt36x[] = {
448 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366), },
449 { 0, },
450};
451
452static struct pci_driver hpt36x_pci_driver = {
453 .name = DRV_NAME,
454 .id_table = hpt36x,
455 .probe = hpt36x_init_one,
456 .remove = ata_pci_remove_one
457};
458
459static int __init hpt36x_init(void)
460{
461 return pci_register_driver(&hpt36x_pci_driver);
462}
463
464
465static void __exit hpt36x_exit(void)
466{
467 pci_unregister_driver(&hpt36x_pci_driver);
468}
469
470
471MODULE_AUTHOR("Alan Cox");
472MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
473MODULE_LICENSE("GPL");
474MODULE_DEVICE_TABLE(pci, hpt36x);
475MODULE_VERSION(DRV_VERSION);
476
477module_init(hpt36x_init);
478module_exit(hpt36x_exit);
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
new file mode 100644
index 00000000000..7c3da53f1e0
--- /dev/null
+++ b/drivers/ata/pata_hpt37x.c
@@ -0,0 +1,1257 @@
1/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 * TODO
13 * PLL mode
14 * Look into engine reset on timeout errors. Should not be
15 * required.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt37x"
28#define DRV_VERSION "0.5"
29
30struct hpt_clock {
31 u8 xfer_speed;
32 u32 timing;
33};
34
35struct hpt_chip {
36 const char *name;
37 unsigned int base;
38 struct hpt_clock const *clocks[4];
39};
40
41/* key for bus clock timings
42 * bit
43 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
44 * DMA. cycles = value + 1
45 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
46 * DMA. cycles = value + 1
47 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
48 * register access.
49 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
50 * register access.
51 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
52 * during task file register access.
53 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
54 * xfer.
55 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
56 * register access.
57 * 28 UDMA enable
58 * 29 DMA enable
59 * 30 PIO_MST enable. if set, the chip is in bus master mode during
60 * PIO.
61 * 31 FIFO enable.
62 */
63
64/* from highpoint documentation. these are old values */
65static const struct hpt_clock hpt370_timings_33[] = {
66/* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
67 { XFER_UDMA_5, 0x16454e31 },
68 { XFER_UDMA_4, 0x16454e31 },
69 { XFER_UDMA_3, 0x166d4e31 },
70 { XFER_UDMA_2, 0x16494e31 },
71 { XFER_UDMA_1, 0x164d4e31 },
72 { XFER_UDMA_0, 0x16514e31 },
73
74 { XFER_MW_DMA_2, 0x26514e21 },
75 { XFER_MW_DMA_1, 0x26514e33 },
76 { XFER_MW_DMA_0, 0x26514e97 },
77
78 { XFER_PIO_4, 0x06514e21 },
79 { XFER_PIO_3, 0x06514e22 },
80 { XFER_PIO_2, 0x06514e33 },
81 { XFER_PIO_1, 0x06914e43 },
82 { XFER_PIO_0, 0x06914e57 },
83 { 0, 0x06514e57 }
84};
85
86static const struct hpt_clock hpt370_timings_66[] = {
87 { XFER_UDMA_5, 0x14846231 },
88 { XFER_UDMA_4, 0x14886231 },
89 { XFER_UDMA_3, 0x148c6231 },
90 { XFER_UDMA_2, 0x148c6231 },
91 { XFER_UDMA_1, 0x14906231 },
92 { XFER_UDMA_0, 0x14986231 },
93
94 { XFER_MW_DMA_2, 0x26514e21 },
95 { XFER_MW_DMA_1, 0x26514e33 },
96 { XFER_MW_DMA_0, 0x26514e97 },
97
98 { XFER_PIO_4, 0x06514e21 },
99 { XFER_PIO_3, 0x06514e22 },
100 { XFER_PIO_2, 0x06514e33 },
101 { XFER_PIO_1, 0x06914e43 },
102 { XFER_PIO_0, 0x06914e57 },
103 { 0, 0x06514e57 }
104};
105
106/* these are the current (4 sep 2001) timings from highpoint */
107static const struct hpt_clock hpt370a_timings_33[] = {
108 { XFER_UDMA_5, 0x12446231 },
109 { XFER_UDMA_4, 0x12446231 },
110 { XFER_UDMA_3, 0x126c6231 },
111 { XFER_UDMA_2, 0x12486231 },
112 { XFER_UDMA_1, 0x124c6233 },
113 { XFER_UDMA_0, 0x12506297 },
114
115 { XFER_MW_DMA_2, 0x22406c31 },
116 { XFER_MW_DMA_1, 0x22406c33 },
117 { XFER_MW_DMA_0, 0x22406c97 },
118
119 { XFER_PIO_4, 0x06414e31 },
120 { XFER_PIO_3, 0x06414e42 },
121 { XFER_PIO_2, 0x06414e53 },
122 { XFER_PIO_1, 0x06814e93 },
123 { XFER_PIO_0, 0x06814ea7 },
124 { 0, 0x06814ea7 }
125};
126
127/* 2x 33MHz timings */
128static const struct hpt_clock hpt370a_timings_66[] = {
129 { XFER_UDMA_5, 0x1488e673 },
130 { XFER_UDMA_4, 0x1488e673 },
131 { XFER_UDMA_3, 0x1498e673 },
132 { XFER_UDMA_2, 0x1490e673 },
133 { XFER_UDMA_1, 0x1498e677 },
134 { XFER_UDMA_0, 0x14a0e73f },
135
136 { XFER_MW_DMA_2, 0x2480fa73 },
137 { XFER_MW_DMA_1, 0x2480fa77 },
138 { XFER_MW_DMA_0, 0x2480fb3f },
139
140 { XFER_PIO_4, 0x0c82be73 },
141 { XFER_PIO_3, 0x0c82be95 },
142 { XFER_PIO_2, 0x0c82beb7 },
143 { XFER_PIO_1, 0x0d02bf37 },
144 { XFER_PIO_0, 0x0d02bf5f },
145 { 0, 0x0d02bf5f }
146};
147
148static const struct hpt_clock hpt370a_timings_50[] = {
149 { XFER_UDMA_5, 0x12848242 },
150 { XFER_UDMA_4, 0x12ac8242 },
151 { XFER_UDMA_3, 0x128c8242 },
152 { XFER_UDMA_2, 0x120c8242 },
153 { XFER_UDMA_1, 0x12148254 },
154 { XFER_UDMA_0, 0x121882ea },
155
156 { XFER_MW_DMA_2, 0x22808242 },
157 { XFER_MW_DMA_1, 0x22808254 },
158 { XFER_MW_DMA_0, 0x228082ea },
159
160 { XFER_PIO_4, 0x0a81f442 },
161 { XFER_PIO_3, 0x0a81f443 },
162 { XFER_PIO_2, 0x0a81f454 },
163 { XFER_PIO_1, 0x0ac1f465 },
164 { XFER_PIO_0, 0x0ac1f48a },
165 { 0, 0x0ac1f48a }
166};
167
168static const struct hpt_clock hpt372_timings_33[] = {
169 { XFER_UDMA_6, 0x1c81dc62 },
170 { XFER_UDMA_5, 0x1c6ddc62 },
171 { XFER_UDMA_4, 0x1c8ddc62 },
172 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
173 { XFER_UDMA_2, 0x1c91dc62 },
174 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
175 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
176
177 { XFER_MW_DMA_2, 0x2c829262 },
178 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
179 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
180
181 { XFER_PIO_4, 0x0c829c62 },
182 { XFER_PIO_3, 0x0c829c84 },
183 { XFER_PIO_2, 0x0c829ca6 },
184 { XFER_PIO_1, 0x0d029d26 },
185 { XFER_PIO_0, 0x0d029d5e },
186 { 0, 0x0d029d5e }
187};
188
189static const struct hpt_clock hpt372_timings_50[] = {
190 { XFER_UDMA_5, 0x12848242 },
191 { XFER_UDMA_4, 0x12ac8242 },
192 { XFER_UDMA_3, 0x128c8242 },
193 { XFER_UDMA_2, 0x120c8242 },
194 { XFER_UDMA_1, 0x12148254 },
195 { XFER_UDMA_0, 0x121882ea },
196
197 { XFER_MW_DMA_2, 0x22808242 },
198 { XFER_MW_DMA_1, 0x22808254 },
199 { XFER_MW_DMA_0, 0x228082ea },
200
201 { XFER_PIO_4, 0x0a81f442 },
202 { XFER_PIO_3, 0x0a81f443 },
203 { XFER_PIO_2, 0x0a81f454 },
204 { XFER_PIO_1, 0x0ac1f465 },
205 { XFER_PIO_0, 0x0ac1f48a },
206 { 0, 0x0a81f443 }
207};
208
209static const struct hpt_clock hpt372_timings_66[] = {
210 { XFER_UDMA_6, 0x1c869c62 },
211 { XFER_UDMA_5, 0x1cae9c62 },
212 { XFER_UDMA_4, 0x1c8a9c62 },
213 { XFER_UDMA_3, 0x1c8e9c62 },
214 { XFER_UDMA_2, 0x1c929c62 },
215 { XFER_UDMA_1, 0x1c9a9c62 },
216 { XFER_UDMA_0, 0x1c829c62 },
217
218 { XFER_MW_DMA_2, 0x2c829c62 },
219 { XFER_MW_DMA_1, 0x2c829c66 },
220 { XFER_MW_DMA_0, 0x2c829d2e },
221
222 { XFER_PIO_4, 0x0c829c62 },
223 { XFER_PIO_3, 0x0c829c84 },
224 { XFER_PIO_2, 0x0c829ca6 },
225 { XFER_PIO_1, 0x0d029d26 },
226 { XFER_PIO_0, 0x0d029d5e },
227 { 0, 0x0d029d26 }
228};
229
230static const struct hpt_clock hpt374_timings_33[] = {
231 { XFER_UDMA_6, 0x12808242 },
232 { XFER_UDMA_5, 0x12848242 },
233 { XFER_UDMA_4, 0x12ac8242 },
234 { XFER_UDMA_3, 0x128c8242 },
235 { XFER_UDMA_2, 0x120c8242 },
236 { XFER_UDMA_1, 0x12148254 },
237 { XFER_UDMA_0, 0x121882ea },
238
239 { XFER_MW_DMA_2, 0x22808242 },
240 { XFER_MW_DMA_1, 0x22808254 },
241 { XFER_MW_DMA_0, 0x228082ea },
242
243 { XFER_PIO_4, 0x0a81f442 },
244 { XFER_PIO_3, 0x0a81f443 },
245 { XFER_PIO_2, 0x0a81f454 },
246 { XFER_PIO_1, 0x0ac1f465 },
247 { XFER_PIO_0, 0x0ac1f48a },
248 { 0, 0x06814e93 }
249};
250
251static const struct hpt_chip hpt370 = {
252 "HPT370",
253 48,
254 {
255 hpt370_timings_33,
256 NULL,
257 NULL,
258 hpt370_timings_66
259 }
260};
261
262static const struct hpt_chip hpt370a = {
263 "HPT370A",
264 48,
265 {
266 hpt370a_timings_33,
267 NULL,
268 hpt370a_timings_50,
269 hpt370a_timings_66
270 }
271};
272
273static const struct hpt_chip hpt372 = {
274 "HPT372",
275 55,
276 {
277 hpt372_timings_33,
278 NULL,
279 hpt372_timings_50,
280 hpt372_timings_66
281 }
282};
283
284static const struct hpt_chip hpt302 = {
285 "HPT302",
286 66,
287 {
288 hpt372_timings_33,
289 NULL,
290 hpt372_timings_50,
291 hpt372_timings_66
292 }
293};
294
295static const struct hpt_chip hpt371 = {
296 "HPT371",
297 66,
298 {
299 hpt372_timings_33,
300 NULL,
301 hpt372_timings_50,
302 hpt372_timings_66
303 }
304};
305
306static const struct hpt_chip hpt372a = {
307 "HPT372A",
308 66,
309 {
310 hpt372_timings_33,
311 NULL,
312 hpt372_timings_50,
313 hpt372_timings_66
314 }
315};
316
317static const struct hpt_chip hpt374 = {
318 "HPT374",
319 48,
320 {
321 hpt374_timings_33,
322 NULL,
323 NULL,
324 NULL
325 }
326};
327
328/**
329 * hpt37x_find_mode - reset the hpt37x bus
330 * @ap: ATA port
331 * @speed: transfer mode
332 *
333 * Return the 32bit register programming information for this channel
334 * that matches the speed provided.
335 */
336
337static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
338{
339 struct hpt_clock *clocks = ap->host->private_data;
340
341 while(clocks->xfer_speed) {
342 if (clocks->xfer_speed == speed)
343 return clocks->timing;
344 clocks++;
345 }
346 BUG();
347 return 0xffffffffU; /* silence compiler warning */
348}
349
350static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
351{
352 unsigned char model_num[40];
353 char *s;
354 unsigned int len;
355 int i = 0;
356
357 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
358 sizeof(model_num));
359 s = &model_num[0];
360 len = strnlen(s, sizeof(model_num));
361
362 /* ATAPI specifies that empty space is blank-filled; remove blanks */
363 while ((len > 0) && (s[len - 1] == ' ')) {
364 len--;
365 s[len] = 0;
366 }
367
368 while(list[i] != NULL) {
369 if (!strncmp(list[i], s, len)) {
370 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
371 modestr, list[i]);
372 return 1;
373 }
374 i++;
375 }
376 return 0;
377}
378
379static const char *bad_ata33[] = {
380 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
381 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
382 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
383 "Maxtor 90510D4",
384 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
385 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
386 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
387 NULL
388};
389
390static const char *bad_ata100_5[] = {
391 "IBM-DTLA-307075",
392 "IBM-DTLA-307060",
393 "IBM-DTLA-307045",
394 "IBM-DTLA-307030",
395 "IBM-DTLA-307020",
396 "IBM-DTLA-307015",
397 "IBM-DTLA-305040",
398 "IBM-DTLA-305030",
399 "IBM-DTLA-305020",
400 "IC35L010AVER07-0",
401 "IC35L020AVER07-0",
402 "IC35L030AVER07-0",
403 "IC35L040AVER07-0",
404 "IC35L060AVER07-0",
405 "WDC AC310200R",
406 NULL
407};
408
409/**
410 * hpt370_filter - mode selection filter
411 * @ap: ATA interface
412 * @adev: ATA device
413 *
414 * Block UDMA on devices that cause trouble with this controller.
415 */
416
417static unsigned long hpt370_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
418{
419 if (adev->class != ATA_DEV_ATA) {
420 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
421 mask &= ~ATA_MASK_UDMA;
422 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
423 mask &= ~(0x1F << ATA_SHIFT_UDMA);
424 }
425 return ata_pci_default_filter(ap, adev, mask);
426}
427
428/**
429 * hpt370a_filter - mode selection filter
430 * @ap: ATA interface
431 * @adev: ATA device
432 *
433 * Block UDMA on devices that cause trouble with this controller.
434 */
435
436static unsigned long hpt370a_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
437{
438 if (adev->class != ATA_DEV_ATA) {
439 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
440 mask &= ~ (0x1F << ATA_SHIFT_UDMA);
441 }
442 return ata_pci_default_filter(ap, adev, mask);
443}
444
445/**
446 * hpt37x_pre_reset - reset the hpt37x bus
447 * @ap: ATA port to reset
448 *
449 * Perform the initial reset handling for the 370/372 and 374 func 0
450 */
451
452static int hpt37x_pre_reset(struct ata_port *ap)
453{
454 u8 scr2, ata66;
455 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
456
457 pci_read_config_byte(pdev, 0x5B, &scr2);
458 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
459 /* Cable register now active */
460 pci_read_config_byte(pdev, 0x5A, &ata66);
461 /* Restore state */
462 pci_write_config_byte(pdev, 0x5B, scr2);
463
464 if (ata66 & (1 << ap->port_no))
465 ap->cbl = ATA_CBL_PATA40;
466 else
467 ap->cbl = ATA_CBL_PATA80;
468
469 /* Reset the state machine */
470 pci_write_config_byte(pdev, 0x50, 0x37);
471 pci_write_config_byte(pdev, 0x54, 0x37);
472 udelay(100);
473
474 return ata_std_prereset(ap);
475}
476
477/**
478 * hpt37x_error_handler - reset the hpt374
479 * @ap: ATA port to reset
480 *
481 * Perform probe for HPT37x, except for HPT374 channel 2
482 */
483
484static void hpt37x_error_handler(struct ata_port *ap)
485{
486 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
487}
488
489static int hpt374_pre_reset(struct ata_port *ap)
490{
491 u16 mcr3, mcr6;
492 u8 ata66;
493
494 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
495 /* Do the extra channel work */
496 pci_read_config_word(pdev, 0x52, &mcr3);
497 pci_read_config_word(pdev, 0x56, &mcr6);
498 /* Set bit 15 of 0x52 to enable TCBLID as input
499 Set bit 15 of 0x56 to enable FCBLID as input
500 */
501 pci_write_config_word(pdev, 0x52, mcr3 | 0x8000);
502 pci_write_config_word(pdev, 0x56, mcr6 | 0x8000);
503 pci_read_config_byte(pdev, 0x5A, &ata66);
504 /* Reset TCBLID/FCBLID to output */
505 pci_write_config_word(pdev, 0x52, mcr3);
506 pci_write_config_word(pdev, 0x56, mcr6);
507
508 if (ata66 & (1 << ap->port_no))
509 ap->cbl = ATA_CBL_PATA40;
510 else
511 ap->cbl = ATA_CBL_PATA80;
512
513 /* Reset the state machine */
514 pci_write_config_byte(pdev, 0x50, 0x37);
515 pci_write_config_byte(pdev, 0x54, 0x37);
516 udelay(100);
517
518 return ata_std_prereset(ap);
519}
520
521/**
522 * hpt374_error_handler - reset the hpt374
523 * @classes:
524 *
525 * The 374 cable detect is a little different due to the extra
526 * channels. The function 0 channels work like usual but function 1
527 * is special
528 */
529
530static void hpt374_error_handler(struct ata_port *ap)
531{
532 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
533
534 if (!(PCI_FUNC(pdev->devfn) & 1))
535 hpt37x_error_handler(ap);
536 else
537 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
538}
539
540/**
541 * hpt370_set_piomode - PIO setup
542 * @ap: ATA interface
543 * @adev: device on the interface
544 *
545 * Perform PIO mode setup.
546 */
547
548static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
549{
550 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
551 u32 addr1, addr2;
552 u32 reg;
553 u32 mode;
554 u8 fast;
555
556 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
557 addr2 = 0x51 + 4 * ap->port_no;
558
559 /* Fast interrupt prediction disable, hold off interrupt disable */
560 pci_read_config_byte(pdev, addr2, &fast);
561 fast &= ~0x02;
562 fast |= 0x01;
563 pci_write_config_byte(pdev, addr2, fast);
564
565 pci_read_config_dword(pdev, addr1, &reg);
566 mode = hpt37x_find_mode(ap, adev->pio_mode);
567 mode &= ~0x8000000; /* No FIFO in PIO */
568 mode &= ~0x30070000; /* Leave config bits alone */
569 reg &= 0x30070000; /* Strip timing bits */
570 pci_write_config_dword(pdev, addr1, reg | mode);
571}
572
573/**
574 * hpt370_set_dmamode - DMA timing setup
575 * @ap: ATA interface
576 * @adev: Device being configured
577 *
578 * Set up the channel for MWDMA or UDMA modes. Much the same as with
579 * PIO, load the mode number and then set MWDMA or UDMA flag.
580 */
581
582static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
583{
584 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
585 u32 addr1, addr2;
586 u32 reg;
587 u32 mode;
588 u8 fast;
589
590 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
591 addr2 = 0x51 + 4 * ap->port_no;
592
593 /* Fast interrupt prediction disable, hold off interrupt disable */
594 pci_read_config_byte(pdev, addr2, &fast);
595 fast &= ~0x02;
596 fast |= 0x01;
597 pci_write_config_byte(pdev, addr2, fast);
598
599 pci_read_config_dword(pdev, addr1, &reg);
600 mode = hpt37x_find_mode(ap, adev->dma_mode);
601 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
602 mode &= ~0xC0000000; /* Leave config bits alone */
603 reg &= 0xC0000000; /* Strip timing bits */
604 pci_write_config_dword(pdev, addr1, reg | mode);
605}
606
607/**
608 * hpt370_bmdma_start - DMA engine begin
609 * @qc: ATA command
610 *
611 * The 370 and 370A want us to reset the DMA engine each time we
612 * use it. The 372 and later are fine.
613 */
614
615static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
616{
617 struct ata_port *ap = qc->ap;
618 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
619 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
620 udelay(10);
621 ata_bmdma_start(qc);
622}
623
624/**
625 * hpt370_bmdma_end - DMA engine stop
626 * @qc: ATA command
627 *
628 * Work around the HPT370 DMA engine.
629 */
630
631static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
632{
633 struct ata_port *ap = qc->ap;
634 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
635 u8 dma_stat = inb(ap->ioaddr.bmdma_addr + 2);
636 u8 dma_cmd;
637 unsigned long bmdma = ap->ioaddr.bmdma_addr;
638
639 if (dma_stat & 0x01) {
640 udelay(20);
641 dma_stat = inb(bmdma + 2);
642 }
643 if (dma_stat & 0x01) {
644 /* Clear the engine */
645 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
646 udelay(10);
647 /* Stop DMA */
648 dma_cmd = inb(bmdma );
649 outb(dma_cmd & 0xFE, bmdma);
650 /* Clear Error */
651 dma_stat = inb(bmdma + 2);
652 outb(dma_stat | 0x06 , bmdma + 2);
653 /* Clear the engine */
654 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
655 udelay(10);
656 }
657 ata_bmdma_stop(qc);
658}
659
660/**
661 * hpt372_set_piomode - PIO setup
662 * @ap: ATA interface
663 * @adev: device on the interface
664 *
665 * Perform PIO mode setup.
666 */
667
668static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
669{
670 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
671 u32 addr1, addr2;
672 u32 reg;
673 u32 mode;
674 u8 fast;
675
676 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
677 addr2 = 0x51 + 4 * ap->port_no;
678
679 /* Fast interrupt prediction disable, hold off interrupt disable */
680 pci_read_config_byte(pdev, addr2, &fast);
681 fast &= ~0x07;
682 pci_write_config_byte(pdev, addr2, fast);
683
684 pci_read_config_dword(pdev, addr1, &reg);
685 mode = hpt37x_find_mode(ap, adev->pio_mode);
686
687 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
688 mode &= ~0x80000000; /* No FIFO in PIO */
689 mode &= ~0x30070000; /* Leave config bits alone */
690 reg &= 0x30070000; /* Strip timing bits */
691 pci_write_config_dword(pdev, addr1, reg | mode);
692}
693
694/**
695 * hpt372_set_dmamode - DMA timing setup
696 * @ap: ATA interface
697 * @adev: Device being configured
698 *
699 * Set up the channel for MWDMA or UDMA modes. Much the same as with
700 * PIO, load the mode number and then set MWDMA or UDMA flag.
701 */
702
703static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
704{
705 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
706 u32 addr1, addr2;
707 u32 reg;
708 u32 mode;
709 u8 fast;
710
711 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
712 addr2 = 0x51 + 4 * ap->port_no;
713
714 /* Fast interrupt prediction disable, hold off interrupt disable */
715 pci_read_config_byte(pdev, addr2, &fast);
716 fast &= ~0x07;
717 pci_write_config_byte(pdev, addr2, fast);
718
719 pci_read_config_dword(pdev, addr1, &reg);
720 mode = hpt37x_find_mode(ap, adev->dma_mode);
721 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
722 mode &= ~0xC0000000; /* Leave config bits alone */
723 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
724 reg &= 0xC0000000; /* Strip timing bits */
725 pci_write_config_dword(pdev, addr1, reg | mode);
726}
727
728/**
729 * hpt37x_bmdma_end - DMA engine stop
730 * @qc: ATA command
731 *
732 * Clean up after the HPT372 and later DMA engine
733 */
734
735static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
736{
737 struct ata_port *ap = qc->ap;
738 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
739 int mscreg = 0x50 + 2 * ap->port_no;
740 u8 bwsr_stat, msc_stat;
741
742 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
743 pci_read_config_byte(pdev, mscreg, &msc_stat);
744 if (bwsr_stat & (1 << ap->port_no))
745 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
746 ata_bmdma_stop(qc);
747}
748
749
750static struct scsi_host_template hpt37x_sht = {
751 .module = THIS_MODULE,
752 .name = DRV_NAME,
753 .ioctl = ata_scsi_ioctl,
754 .queuecommand = ata_scsi_queuecmd,
755 .can_queue = ATA_DEF_QUEUE,
756 .this_id = ATA_SHT_THIS_ID,
757 .sg_tablesize = LIBATA_MAX_PRD,
758 .max_sectors = ATA_MAX_SECTORS,
759 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
760 .emulated = ATA_SHT_EMULATED,
761 .use_clustering = ATA_SHT_USE_CLUSTERING,
762 .proc_name = DRV_NAME,
763 .dma_boundary = ATA_DMA_BOUNDARY,
764 .slave_configure = ata_scsi_slave_config,
765 .bios_param = ata_std_bios_param,
766};
767
768/*
769 * Configuration for HPT370
770 */
771
772static struct ata_port_operations hpt370_port_ops = {
773 .port_disable = ata_port_disable,
774 .set_piomode = hpt370_set_piomode,
775 .set_dmamode = hpt370_set_dmamode,
776 .mode_filter = hpt370_filter,
777
778 .tf_load = ata_tf_load,
779 .tf_read = ata_tf_read,
780 .check_status = ata_check_status,
781 .exec_command = ata_exec_command,
782 .dev_select = ata_std_dev_select,
783
784 .freeze = ata_bmdma_freeze,
785 .thaw = ata_bmdma_thaw,
786 .error_handler = hpt37x_error_handler,
787 .post_internal_cmd = ata_bmdma_post_internal_cmd,
788
789 .bmdma_setup = ata_bmdma_setup,
790 .bmdma_start = hpt370_bmdma_start,
791 .bmdma_stop = hpt370_bmdma_stop,
792 .bmdma_status = ata_bmdma_status,
793
794 .qc_prep = ata_qc_prep,
795 .qc_issue = ata_qc_issue_prot,
796 .eng_timeout = ata_eng_timeout,
797 .data_xfer = ata_pio_data_xfer,
798
799 .irq_handler = ata_interrupt,
800 .irq_clear = ata_bmdma_irq_clear,
801
802 .port_start = ata_port_start,
803 .port_stop = ata_port_stop,
804 .host_stop = ata_host_stop
805};
806
807/*
808 * Configuration for HPT370A. Close to 370 but less filters
809 */
810
811static struct ata_port_operations hpt370a_port_ops = {
812 .port_disable = ata_port_disable,
813 .set_piomode = hpt370_set_piomode,
814 .set_dmamode = hpt370_set_dmamode,
815 .mode_filter = hpt370a_filter,
816
817 .tf_load = ata_tf_load,
818 .tf_read = ata_tf_read,
819 .check_status = ata_check_status,
820 .exec_command = ata_exec_command,
821 .dev_select = ata_std_dev_select,
822
823 .freeze = ata_bmdma_freeze,
824 .thaw = ata_bmdma_thaw,
825 .error_handler = hpt37x_error_handler,
826 .post_internal_cmd = ata_bmdma_post_internal_cmd,
827
828 .bmdma_setup = ata_bmdma_setup,
829 .bmdma_start = hpt370_bmdma_start,
830 .bmdma_stop = hpt370_bmdma_stop,
831 .bmdma_status = ata_bmdma_status,
832
833 .qc_prep = ata_qc_prep,
834 .qc_issue = ata_qc_issue_prot,
835 .eng_timeout = ata_eng_timeout,
836 .data_xfer = ata_pio_data_xfer,
837
838 .irq_handler = ata_interrupt,
839 .irq_clear = ata_bmdma_irq_clear,
840
841 .port_start = ata_port_start,
842 .port_stop = ata_port_stop,
843 .host_stop = ata_host_stop
844};
845
846/*
847 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
848 * and DMA mode setting functionality.
849 */
850
851static struct ata_port_operations hpt372_port_ops = {
852 .port_disable = ata_port_disable,
853 .set_piomode = hpt372_set_piomode,
854 .set_dmamode = hpt372_set_dmamode,
855 .mode_filter = ata_pci_default_filter,
856
857 .tf_load = ata_tf_load,
858 .tf_read = ata_tf_read,
859 .check_status = ata_check_status,
860 .exec_command = ata_exec_command,
861 .dev_select = ata_std_dev_select,
862
863 .freeze = ata_bmdma_freeze,
864 .thaw = ata_bmdma_thaw,
865 .error_handler = hpt37x_error_handler,
866 .post_internal_cmd = ata_bmdma_post_internal_cmd,
867
868 .bmdma_setup = ata_bmdma_setup,
869 .bmdma_start = ata_bmdma_start,
870 .bmdma_stop = hpt37x_bmdma_stop,
871 .bmdma_status = ata_bmdma_status,
872
873 .qc_prep = ata_qc_prep,
874 .qc_issue = ata_qc_issue_prot,
875 .eng_timeout = ata_eng_timeout,
876 .data_xfer = ata_pio_data_xfer,
877
878 .irq_handler = ata_interrupt,
879 .irq_clear = ata_bmdma_irq_clear,
880
881 .port_start = ata_port_start,
882 .port_stop = ata_port_stop,
883 .host_stop = ata_host_stop
884};
885
886/*
887 * Configuration for HPT374. Mode setting works like 372 and friends
888 * but we have a different cable detection procedure.
889 */
890
891static struct ata_port_operations hpt374_port_ops = {
892 .port_disable = ata_port_disable,
893 .set_piomode = hpt372_set_piomode,
894 .set_dmamode = hpt372_set_dmamode,
895 .mode_filter = ata_pci_default_filter,
896
897 .tf_load = ata_tf_load,
898 .tf_read = ata_tf_read,
899 .check_status = ata_check_status,
900 .exec_command = ata_exec_command,
901 .dev_select = ata_std_dev_select,
902
903 .freeze = ata_bmdma_freeze,
904 .thaw = ata_bmdma_thaw,
905 .error_handler = hpt374_error_handler,
906 .post_internal_cmd = ata_bmdma_post_internal_cmd,
907
908 .bmdma_setup = ata_bmdma_setup,
909 .bmdma_start = ata_bmdma_start,
910 .bmdma_stop = hpt37x_bmdma_stop,
911 .bmdma_status = ata_bmdma_status,
912
913 .qc_prep = ata_qc_prep,
914 .qc_issue = ata_qc_issue_prot,
915 .eng_timeout = ata_eng_timeout,
916 .data_xfer = ata_pio_data_xfer,
917
918 .irq_handler = ata_interrupt,
919 .irq_clear = ata_bmdma_irq_clear,
920
921 .port_start = ata_port_start,
922 .port_stop = ata_port_stop,
923 .host_stop = ata_host_stop
924};
925
926/**
927 * htp37x_clock_slot - Turn timing to PC clock entry
928 * @freq: Reported frequency timing
929 * @base: Base timing
930 *
931 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
932 * and 3 for 66Mhz)
933 */
934
935static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
936{
937 unsigned int f = (base * freq) / 192; /* Mhz */
938 if (f < 40)
939 return 0; /* 33Mhz slot */
940 if (f < 45)
941 return 1; /* 40Mhz slot */
942 if (f < 55)
943 return 2; /* 50Mhz slot */
944 return 3; /* 60Mhz slot */
945}
946
947/**
948 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
949 * @dev: PCI device
950 *
951 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
952 * succeeds
953 */
954
955static int hpt37x_calibrate_dpll(struct pci_dev *dev)
956{
957 u8 reg5b;
958 u32 reg5c;
959 int tries;
960
961 for(tries = 0; tries < 0x5000; tries++) {
962 udelay(50);
963 pci_read_config_byte(dev, 0x5b, &reg5b);
964 if (reg5b & 0x80) {
965 /* See if it stays set */
966 for(tries = 0; tries < 0x1000; tries ++) {
967 pci_read_config_byte(dev, 0x5b, &reg5b);
968 /* Failed ? */
969 if ((reg5b & 0x80) == 0)
970 return 0;
971 }
972 /* Turn off tuning, we have the DPLL set */
973 pci_read_config_dword(dev, 0x5c, &reg5c);
974 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
975 return 1;
976 }
977 }
978 /* Never went stable */
979 return 0;
980}
981/**
982 * hpt37x_init_one - Initialise an HPT37X/302
983 * @dev: PCI device
984 * @id: Entry in match table
985 *
986 * Initialise an HPT37x device. There are some interesting complications
987 * here. Firstly the chip may report 366 and be one of several variants.
988 * Secondly all the timings depend on the clock for the chip which we must
989 * detect and look up
990 *
991 * This is the known chip mappings. It may be missing a couple of later
992 * releases.
993 *
994 * Chip version PCI Rev Notes
995 * HPT366 4 (HPT366) 0 Other driver
996 * HPT366 4 (HPT366) 1 Other driver
997 * HPT368 4 (HPT366) 2 Other driver
998 * HPT370 4 (HPT366) 3 UDMA100
999 * HPT370A 4 (HPT366) 4 UDMA100
1000 * HPT372 4 (HPT366) 5 UDMA133 (1)
1001 * HPT372N 4 (HPT366) 6 Other driver
1002 * HPT372A 5 (HPT372) 1 UDMA133 (1)
1003 * HPT372N 5 (HPT372) 2 Other driver
1004 * HPT302 6 (HPT302) 1 UDMA133
1005 * HPT302N 6 (HPT302) 2 Other driver
1006 * HPT371 7 (HPT371) * UDMA133
1007 * HPT374 8 (HPT374) * UDMA133 4 channel
1008 * HPT372N 9 (HPT372N) * Other driver
1009 *
1010 * (1) UDMA133 support depends on the bus clock
1011 */
1012
1013static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1014{
1015 /* HPT370 - UDMA100 */
1016 static struct ata_port_info info_hpt370 = {
1017 .sht = &hpt37x_sht,
1018 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1019 .pio_mask = 0x1f,
1020 .mwdma_mask = 0x07,
1021 .udma_mask = 0x3f,
1022 .port_ops = &hpt370_port_ops
1023 };
1024 /* HPT370A - UDMA100 */
1025 static struct ata_port_info info_hpt370a = {
1026 .sht = &hpt37x_sht,
1027 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1028 .pio_mask = 0x1f,
1029 .mwdma_mask = 0x07,
1030 .udma_mask = 0x3f,
1031 .port_ops = &hpt370a_port_ops
1032 };
1033 /* HPT371, 372 and friends - UDMA133 */
1034 static struct ata_port_info info_hpt372 = {
1035 .sht = &hpt37x_sht,
1036 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1037 .pio_mask = 0x1f,
1038 .mwdma_mask = 0x07,
1039 .udma_mask = 0x7f,
1040 .port_ops = &hpt372_port_ops
1041 };
1042 /* HPT371, 372 and friends - UDMA100 at 50MHz clock */
1043 static struct ata_port_info info_hpt372_50 = {
1044 .sht = &hpt37x_sht,
1045 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1046 .pio_mask = 0x1f,
1047 .mwdma_mask = 0x07,
1048 .udma_mask = 0x3f,
1049 .port_ops = &hpt372_port_ops
1050 };
1051 /* HPT374 - UDMA133 */
1052 static struct ata_port_info info_hpt374 = {
1053 .sht = &hpt37x_sht,
1054 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1055 .pio_mask = 0x1f,
1056 .mwdma_mask = 0x07,
1057 .udma_mask = 0x7f,
1058 .port_ops = &hpt374_port_ops
1059 };
1060
1061 static const int MHz[4] = { 33, 40, 50, 66 };
1062
1063 struct ata_port_info *port_info[2];
1064 struct ata_port_info *port;
1065
1066 u8 irqmask;
1067 u32 class_rev;
1068 u32 freq;
1069
1070 const struct hpt_chip *chip_table;
1071 int clock_slot;
1072
1073 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1074 class_rev &= 0xFF;
1075
1076 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
1077 /* May be a later chip in disguise. Check */
1078 /* Older chips are in the HPT366 driver. Ignore them */
1079 if (class_rev < 3)
1080 return -ENODEV;
1081 /* N series chips have their own driver. Ignore */
1082 if (class_rev == 6)
1083 return -ENODEV;
1084
1085 switch(class_rev) {
1086 case 3:
1087 port = &info_hpt370;
1088 chip_table = &hpt370;
1089 break;
1090 case 4:
1091 port = &info_hpt370a;
1092 chip_table = &hpt370a;
1093 break;
1094 case 5:
1095 port = &info_hpt372;
1096 chip_table = &hpt372;
1097 break;
1098 default:
1099 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
1100 return -ENODEV;
1101 }
1102 } else {
1103 switch(dev->device) {
1104 case PCI_DEVICE_ID_TTI_HPT372:
1105 /* 372N if rev >= 2*/
1106 if (class_rev >= 2)
1107 return -ENODEV;
1108 port = &info_hpt372;
1109 chip_table = &hpt372a;
1110 break;
1111 case PCI_DEVICE_ID_TTI_HPT302:
1112 /* 302N if rev > 1 */
1113 if (class_rev > 1)
1114 return -ENODEV;
1115 port = &info_hpt372;
1116 /* Check this */
1117 chip_table = &hpt302;
1118 break;
1119 case PCI_DEVICE_ID_TTI_HPT371:
1120 port = &info_hpt372;
1121 chip_table = &hpt371;
1122 break;
1123 case PCI_DEVICE_ID_TTI_HPT374:
1124 chip_table = &hpt374;
1125 port = &info_hpt374;
1126 break;
1127 default:
1128 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
1129 return -ENODEV;
1130 }
1131 }
1132 /* Ok so this is a chip we support */
1133
1134 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1135 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1136 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1137 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1138
1139 pci_read_config_byte(dev, 0x5A, &irqmask);
1140 irqmask &= ~0x10;
1141 pci_write_config_byte(dev, 0x5a, irqmask);
1142
1143 /*
1144 * default to pci clock. make sure MA15/16 are set to output
1145 * to prevent drives having problems with 40-pin cables. Needed
1146 * for some drives such as IBM-DTLA which will not enter ready
1147 * state on reset when PDIAG is a input.
1148 */
1149
1150 pci_write_config_byte(dev, 0x5b, 0x23);
1151
1152 pci_read_config_dword(dev, 0x70, &freq);
1153 if ((freq >> 12) != 0xABCDE) {
1154 int i;
1155 u8 sr;
1156 u32 total = 0;
1157
1158 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
1159
1160 /* This is the process the HPT371 BIOS is reported to use */
1161 for(i = 0; i < 128; i++) {
1162 pci_read_config_byte(dev, 0x78, &sr);
1163 total += sr;
1164 udelay(15);
1165 }
1166 freq = total / 128;
1167 }
1168 freq &= 0x1FF;
1169
1170 /*
1171 * Turn the frequency check into a band and then find a timing
1172 * table to match it.
1173 */
1174
1175 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
1176 if (chip_table->clocks[clock_slot] == NULL) {
1177 /*
1178 * We need to try PLL mode instead
1179 */
1180 unsigned int f_low = (MHz[clock_slot] * chip_table->base) / 192;
1181 unsigned int f_high = f_low + 2;
1182 int adjust;
1183
1184 for(adjust = 0; adjust < 8; adjust++) {
1185 if (hpt37x_calibrate_dpll(dev))
1186 break;
1187 /* See if it'll settle at a fractionally different clock */
1188 if ((adjust & 3) == 3) {
1189 f_low --;
1190 f_high ++;
1191 }
1192 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
1193 }
1194 if (adjust == 8) {
1195 printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");
1196 return -ENODEV;
1197 }
1198 /* Check if this works for all cases */
1199 port->private_data = (void *)hpt370_timings_66;
1200
1201 printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]);
1202 } else {
1203 port->private_data = (void *)chip_table->clocks[clock_slot];
1204 /*
1205 * Perform a final fixup. The 371 and 372 clock determines
1206 * if UDMA133 is available.
1207 */
1208
1209 if (clock_slot == 2 && chip_table == &hpt372) { /* 50Mhz */
1210 printk(KERN_WARNING "pata_hpt37x: No UDMA133 support available with 50MHz bus clock.\n");
1211 if (port == &info_hpt372)
1212 port = &info_hpt372_50;
1213 else BUG();
1214 }
1215 printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]);
1216 }
1217 port_info[0] = port_info[1] = port;
1218 /* Now kick off ATA set up */
1219 return ata_pci_init_one(dev, port_info, 2);
1220}
1221
1222static struct pci_device_id hpt37x[] = {
1223 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366), },
1224 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371), },
1225 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372), },
1226 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374), },
1227 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302), },
1228 { 0, },
1229};
1230
1231static struct pci_driver hpt37x_pci_driver = {
1232 .name = DRV_NAME,
1233 .id_table = hpt37x,
1234 .probe = hpt37x_init_one,
1235 .remove = ata_pci_remove_one
1236};
1237
1238static int __init hpt37x_init(void)
1239{
1240 return pci_register_driver(&hpt37x_pci_driver);
1241}
1242
1243
1244static void __exit hpt37x_exit(void)
1245{
1246 pci_unregister_driver(&hpt37x_pci_driver);
1247}
1248
1249
1250MODULE_AUTHOR("Alan Cox");
1251MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1252MODULE_LICENSE("GPL");
1253MODULE_DEVICE_TABLE(pci, hpt37x);
1254MODULE_VERSION(DRV_VERSION);
1255
1256module_init(hpt37x_init);
1257module_exit(hpt37x_exit);
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
new file mode 100644
index 00000000000..40fcda62c7a
--- /dev/null
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -0,0 +1,597 @@
1/*
2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
14 * 371N
15 * Work out best PLL policy
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt3x2n"
28#define DRV_VERSION "0.3"
29
30enum {
31 HPT_PCI_FAST = (1 << 31),
32 PCI66 = (1 << 1),
33 USE_DPLL = (1 << 0)
34};
35
36struct hpt_clock {
37 u8 xfer_speed;
38 u32 timing;
39};
40
41struct hpt_chip {
42 const char *name;
43 struct hpt_clock *clocks[3];
44};
45
46/* key for bus clock timings
47 * bit
48 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
49 * DMA. cycles = value + 1
50 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
51 * DMA. cycles = value + 1
52 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
53 * register access.
54 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
55 * register access.
56 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
57 * during task file register access.
58 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
59 * xfer.
60 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
61 * register access.
62 * 28 UDMA enable
63 * 29 DMA enable
64 * 30 PIO_MST enable. if set, the chip is in bus master mode during
65 * PIO.
66 * 31 FIFO enable.
67 */
68
69/* 66MHz DPLL clocks */
70
71static struct hpt_clock hpt3x2n_clocks[] = {
72 { XFER_UDMA_7, 0x1c869c62 },
73 { XFER_UDMA_6, 0x1c869c62 },
74 { XFER_UDMA_5, 0x1c8a9c62 },
75 { XFER_UDMA_4, 0x1c8a9c62 },
76 { XFER_UDMA_3, 0x1c8e9c62 },
77 { XFER_UDMA_2, 0x1c929c62 },
78 { XFER_UDMA_1, 0x1c9a9c62 },
79 { XFER_UDMA_0, 0x1c829c62 },
80
81 { XFER_MW_DMA_2, 0x2c829c62 },
82 { XFER_MW_DMA_1, 0x2c829c66 },
83 { XFER_MW_DMA_0, 0x2c829d2c },
84
85 { XFER_PIO_4, 0x0c829c62 },
86 { XFER_PIO_3, 0x0c829c84 },
87 { XFER_PIO_2, 0x0c829ca6 },
88 { XFER_PIO_1, 0x0d029d26 },
89 { XFER_PIO_0, 0x0d029d5e },
90 { 0, 0x0d029d5e }
91};
92
93/**
94 * hpt3x2n_find_mode - reset the hpt3x2n bus
95 * @ap: ATA port
96 * @speed: transfer mode
97 *
98 * Return the 32bit register programming information for this channel
99 * that matches the speed provided. For the moment the clocks table
100 * is hard coded but easy to change. This will be needed if we use
101 * different DPLLs
102 */
103
104static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
105{
106 struct hpt_clock *clocks = hpt3x2n_clocks;
107
108 while(clocks->xfer_speed) {
109 if (clocks->xfer_speed == speed)
110 return clocks->timing;
111 clocks++;
112 }
113 BUG();
114 return 0xffffffffU; /* silence compiler warning */
115}
116
117/**
118 * hpt3x2n_pre_reset - reset the hpt3x2n bus
119 * @ap: ATA port to reset
120 *
121 * Perform the initial reset handling for the 3x2n series controllers.
122 * Reset the hardware and state machine, obtain the cable type.
123 */
124
125static int hpt3xn_pre_reset(struct ata_port *ap)
126{
127 u8 scr2, ata66;
128 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
129
130 pci_read_config_byte(pdev, 0x5B, &scr2);
131 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
132 /* Cable register now active */
133 pci_read_config_byte(pdev, 0x5A, &ata66);
134 /* Restore state */
135 pci_write_config_byte(pdev, 0x5B, scr2);
136
137 if (ata66 & (1 << ap->port_no))
138 ap->cbl = ATA_CBL_PATA40;
139 else
140 ap->cbl = ATA_CBL_PATA80;
141
142 /* Reset the state machine */
143 pci_write_config_byte(pdev, 0x50, 0x37);
144 pci_write_config_byte(pdev, 0x54, 0x37);
145 udelay(100);
146
147 return ata_std_prereset(ap);
148}
149
150/**
151 * hpt3x2n_error_handler - probe the hpt3x2n bus
152 * @ap: ATA port to reset
153 *
154 * Perform the probe reset handling for the 3x2N
155 */
156
157static void hpt3x2n_error_handler(struct ata_port *ap)
158{
159 ata_bmdma_drive_eh(ap, hpt3xn_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
160}
161
162/**
163 * hpt3x2n_set_piomode - PIO setup
164 * @ap: ATA interface
165 * @adev: device on the interface
166 *
167 * Perform PIO mode setup.
168 */
169
170static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
171{
172 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
173 u32 addr1, addr2;
174 u32 reg;
175 u32 mode;
176 u8 fast;
177
178 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
179 addr2 = 0x51 + 4 * ap->port_no;
180
181 /* Fast interrupt prediction disable, hold off interrupt disable */
182 pci_read_config_byte(pdev, addr2, &fast);
183 fast &= ~0x07;
184 pci_write_config_byte(pdev, addr2, fast);
185
186 pci_read_config_dword(pdev, addr1, &reg);
187 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
188 mode &= ~0x8000000; /* No FIFO in PIO */
189 mode &= ~0x30070000; /* Leave config bits alone */
190 reg &= 0x30070000; /* Strip timing bits */
191 pci_write_config_dword(pdev, addr1, reg | mode);
192}
193
194/**
195 * hpt3x2n_set_dmamode - DMA timing setup
196 * @ap: ATA interface
197 * @adev: Device being configured
198 *
199 * Set up the channel for MWDMA or UDMA modes. Much the same as with
200 * PIO, load the mode number and then set MWDMA or UDMA flag.
201 */
202
203static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
204{
205 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
206 u32 addr1, addr2;
207 u32 reg;
208 u32 mode;
209 u8 fast;
210
211 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
212 addr2 = 0x51 + 4 * ap->port_no;
213
214 /* Fast interrupt prediction disable, hold off interrupt disable */
215 pci_read_config_byte(pdev, addr2, &fast);
216 fast &= ~0x07;
217 pci_write_config_byte(pdev, addr2, fast);
218
219 pci_read_config_dword(pdev, addr1, &reg);
220 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
221 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
222 mode &= ~0xC0000000; /* Leave config bits alone */
223 reg &= 0xC0000000; /* Strip timing bits */
224 pci_write_config_dword(pdev, addr1, reg | mode);
225}
226
227/**
228 * hpt3x2n_bmdma_end - DMA engine stop
229 * @qc: ATA command
230 *
231 * Clean up after the HPT3x2n and later DMA engine
232 */
233
234static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
235{
236 struct ata_port *ap = qc->ap;
237 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
238 int mscreg = 0x50 + 2 * ap->port_no;
239 u8 bwsr_stat, msc_stat;
240
241 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
242 pci_read_config_byte(pdev, mscreg, &msc_stat);
243 if (bwsr_stat & (1 << ap->port_no))
244 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
245 ata_bmdma_stop(qc);
246}
247
248/**
249 * hpt3x2n_set_clock - clock control
250 * @ap: ATA port
251 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
252 *
253 * Switch the ATA bus clock between the PLL and PCI clock sources
254 * while correctly isolating the bus and resetting internal logic
255 *
256 * We must use the DPLL for
257 * - writing
258 * - second channel UDMA7 (SATA ports) or higher
259 * - 66MHz PCI
260 *
261 * or we will underclock the device and get reduced performance.
262 */
263
264static void hpt3x2n_set_clock(struct ata_port *ap, int source)
265{
266 unsigned long bmdma = ap->ioaddr.bmdma_addr;
267
268 /* Tristate the bus */
269 outb(0x80, bmdma+0x73);
270 outb(0x80, bmdma+0x77);
271
272 /* Switch clock and reset channels */
273 outb(source, bmdma+0x7B);
274 outb(0xC0, bmdma+0x79);
275
276 /* Reset state machines */
277 outb(0x37, bmdma+0x70);
278 outb(0x37, bmdma+0x74);
279
280 /* Complete reset */
281 outb(0x00, bmdma+0x79);
282
283 /* Reconnect channels to bus */
284 outb(0x00, bmdma+0x73);
285 outb(0x00, bmdma+0x77);
286}
287
288/* Check if our partner interface is busy */
289
290static int hpt3x2n_pair_idle(struct ata_port *ap)
291{
292 struct ata_host *host = ap->host;
293 struct ata_port *pair = host->ports[ap->port_no ^ 1];
294
295 if (pair->hsm_task_state == HSM_ST_IDLE)
296 return 1;
297 return 0;
298}
299
300static int hpt3x2n_use_dpll(struct ata_port *ap, int reading)
301{
302 long flags = (long)ap->host->private_data;
303 /* See if we should use the DPLL */
304 if (reading == 0)
305 return USE_DPLL; /* Needed for write */
306 if (flags & PCI66)
307 return USE_DPLL; /* Needed at 66Mhz */
308 return 0;
309}
310
311static unsigned int hpt3x2n_qc_issue_prot(struct ata_queued_cmd *qc)
312{
313 struct ata_taskfile *tf = &qc->tf;
314 struct ata_port *ap = qc->ap;
315 int flags = (long)ap->host->private_data;
316
317 if (hpt3x2n_pair_idle(ap)) {
318 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
319 if ((flags & USE_DPLL) != dpll) {
320 if (dpll == 1)
321 hpt3x2n_set_clock(ap, 0x21);
322 else
323 hpt3x2n_set_clock(ap, 0x23);
324 }
325 }
326 return ata_qc_issue_prot(qc);
327}
328
329static struct scsi_host_template hpt3x2n_sht = {
330 .module = THIS_MODULE,
331 .name = DRV_NAME,
332 .ioctl = ata_scsi_ioctl,
333 .queuecommand = ata_scsi_queuecmd,
334 .can_queue = ATA_DEF_QUEUE,
335 .this_id = ATA_SHT_THIS_ID,
336 .sg_tablesize = LIBATA_MAX_PRD,
337 .max_sectors = ATA_MAX_SECTORS,
338 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
339 .emulated = ATA_SHT_EMULATED,
340 .use_clustering = ATA_SHT_USE_CLUSTERING,
341 .proc_name = DRV_NAME,
342 .dma_boundary = ATA_DMA_BOUNDARY,
343 .slave_configure = ata_scsi_slave_config,
344 .bios_param = ata_std_bios_param,
345};
346
347/*
348 * Configuration for HPT3x2n.
349 */
350
351static struct ata_port_operations hpt3x2n_port_ops = {
352 .port_disable = ata_port_disable,
353 .set_piomode = hpt3x2n_set_piomode,
354 .set_dmamode = hpt3x2n_set_dmamode,
355 .mode_filter = ata_pci_default_filter,
356
357 .tf_load = ata_tf_load,
358 .tf_read = ata_tf_read,
359 .check_status = ata_check_status,
360 .exec_command = ata_exec_command,
361 .dev_select = ata_std_dev_select,
362
363 .freeze = ata_bmdma_freeze,
364 .thaw = ata_bmdma_thaw,
365 .error_handler = hpt3x2n_error_handler,
366 .post_internal_cmd = ata_bmdma_post_internal_cmd,
367
368 .bmdma_setup = ata_bmdma_setup,
369 .bmdma_start = ata_bmdma_start,
370 .bmdma_stop = hpt3x2n_bmdma_stop,
371 .bmdma_status = ata_bmdma_status,
372
373 .qc_prep = ata_qc_prep,
374 .qc_issue = hpt3x2n_qc_issue_prot,
375 .eng_timeout = ata_eng_timeout,
376 .data_xfer = ata_pio_data_xfer,
377
378 .irq_handler = ata_interrupt,
379 .irq_clear = ata_bmdma_irq_clear,
380
381 .port_start = ata_port_start,
382 .port_stop = ata_port_stop,
383 .host_stop = ata_host_stop
384};
385
386/**
387 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
388 * @dev: PCI device
389 *
390 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
391 * succeeds
392 */
393
394static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
395{
396 u8 reg5b;
397 u32 reg5c;
398 int tries;
399
400 for(tries = 0; tries < 0x5000; tries++) {
401 udelay(50);
402 pci_read_config_byte(dev, 0x5b, &reg5b);
403 if (reg5b & 0x80) {
404 /* See if it stays set */
405 for(tries = 0; tries < 0x1000; tries ++) {
406 pci_read_config_byte(dev, 0x5b, &reg5b);
407 /* Failed ? */
408 if ((reg5b & 0x80) == 0)
409 return 0;
410 }
411 /* Turn off tuning, we have the DPLL set */
412 pci_read_config_dword(dev, 0x5c, &reg5c);
413 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
414 return 1;
415 }
416 }
417 /* Never went stable */
418 return 0;
419}
420
421static int hpt3x2n_pci_clock(struct pci_dev *pdev)
422{
423 unsigned long freq;
424 u32 fcnt;
425
426 pci_read_config_dword(pdev, 0x70/*CHECKME*/, &fcnt);
427 if ((fcnt >> 12) != 0xABCDE) {
428 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
429 return 33; /* Not BIOS set */
430 }
431 fcnt &= 0x1FF;
432
433 freq = (fcnt * 77) / 192;
434
435 /* Clamp to bands */
436 if (freq < 40)
437 return 33;
438 if (freq < 45)
439 return 40;
440 if (freq < 55)
441 return 50;
442 return 66;
443}
444
445/**
446 * hpt3x2n_init_one - Initialise an HPT37X/302
447 * @dev: PCI device
448 * @id: Entry in match table
449 *
450 * Initialise an HPT3x2n device. There are some interesting complications
451 * here. Firstly the chip may report 366 and be one of several variants.
452 * Secondly all the timings depend on the clock for the chip which we must
453 * detect and look up
454 *
455 * This is the known chip mappings. It may be missing a couple of later
456 * releases.
457 *
458 * Chip version PCI Rev Notes
459 * HPT372 4 (HPT366) 5 Other driver
460 * HPT372N 4 (HPT366) 6 UDMA133
461 * HPT372 5 (HPT372) 1 Other driver
462 * HPT372N 5 (HPT372) 2 UDMA133
463 * HPT302 6 (HPT302) * Other driver
464 * HPT302N 6 (HPT302) > 1 UDMA133
465 * HPT371 7 (HPT371) * Other driver
466 * HPT371N 7 (HPT371) > 1 UDMA133
467 * HPT374 8 (HPT374) * Other driver
468 * HPT372N 9 (HPT372N) * UDMA133
469 *
470 * (1) UDMA133 support depends on the bus clock
471 *
472 * To pin down HPT371N
473 */
474
475static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
476{
477 /* HPT372N and friends - UDMA133 */
478 static struct ata_port_info info = {
479 .sht = &hpt3x2n_sht,
480 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
481 .pio_mask = 0x1f,
482 .mwdma_mask = 0x07,
483 .udma_mask = 0x7f,
484 .port_ops = &hpt3x2n_port_ops
485 };
486 struct ata_port_info *port_info[2];
487 struct ata_port_info *port = &info;
488
489 u8 irqmask;
490 u32 class_rev;
491
492 unsigned int pci_mhz;
493 unsigned int f_low, f_high;
494 int adjust;
495
496 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
497 class_rev &= 0xFF;
498
499 switch(dev->device) {
500 case PCI_DEVICE_ID_TTI_HPT366:
501 if (class_rev < 6)
502 return -ENODEV;
503 break;
504 case PCI_DEVICE_ID_TTI_HPT372:
505 /* 372N if rev >= 1*/
506 if (class_rev == 0)
507 return -ENODEV;
508 break;
509 case PCI_DEVICE_ID_TTI_HPT302:
510 if (class_rev < 2)
511 return -ENODEV;
512 break;
513 case PCI_DEVICE_ID_TTI_HPT372N:
514 break;
515 default:
516 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
517 return -ENODEV;
518 }
519
520 /* Ok so this is a chip we support */
521
522 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
523 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
524 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
525 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
526
527 pci_read_config_byte(dev, 0x5A, &irqmask);
528 irqmask &= ~0x10;
529 pci_write_config_byte(dev, 0x5a, irqmask);
530
531 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
532 50 for UDMA100. Right now we always use 66 */
533
534 pci_mhz = hpt3x2n_pci_clock(dev);
535
536 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
537 f_high = f_low + 2; /* Tolerance */
538
539 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
540 /* PLL clock */
541 pci_write_config_byte(dev, 0x5B, 0x21);
542
543 /* Unlike the 37x we don't try jiggling the frequency */
544 for(adjust = 0; adjust < 8; adjust++) {
545 if (hpt3xn_calibrate_dpll(dev))
546 break;
547 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
548 }
549 if (adjust == 8)
550 printk(KERN_WARNING "hpt3xn: DPLL did not stabilize.\n");
551
552 /* Set our private data up. We only need a few flags so we use
553 it directly */
554 port->private_data = NULL;
555 if (pci_mhz > 60)
556 port->private_data = (void *)PCI66;
557
558 /* Now kick off ATA set up */
559 port_info[0] = port_info[1] = port;
560 return ata_pci_init_one(dev, port_info, 2);
561}
562
563static struct pci_device_id hpt3x2n[] = {
564 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366), },
565 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372), },
566 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302), },
567 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N), },
568 { 0, },
569};
570
571static struct pci_driver hpt3x2n_pci_driver = {
572 .name = DRV_NAME,
573 .id_table = hpt3x2n,
574 .probe = hpt3x2n_init_one,
575 .remove = ata_pci_remove_one
576};
577
578static int __init hpt3x2n_init(void)
579{
580 return pci_register_driver(&hpt3x2n_pci_driver);
581}
582
583
584static void __exit hpt3x2n_exit(void)
585{
586 pci_unregister_driver(&hpt3x2n_pci_driver);
587}
588
589
590MODULE_AUTHOR("Alan Cox");
591MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
592MODULE_LICENSE("GPL");
593MODULE_DEVICE_TABLE(pci, hpt3x2n);
594MODULE_VERSION(DRV_VERSION);
595
596module_init(hpt3x2n_init);
597module_exit(hpt3x2n_exit);
diff --git a/drivers/ata/pata_hpt3x3.c b/drivers/ata/pata_hpt3x3.c
new file mode 100644
index 00000000000..c93406ebf6e
--- /dev/null
+++ b/drivers/ata/pata_hpt3x3.c
@@ -0,0 +1,226 @@
1/*
2 * pata_hpt3x3 - HPT3x3 driver
3 * (c) Copyright 2005-2006 Red Hat
4 *
5 * Was pata_hpt34x but the naming was confusing as it supported the
6 * 343 and 363 so it has been renamed.
7 *
8 * Based on:
9 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 *
12 * May be copied or modified under the terms of the GNU General Public
13 * License
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/blkdev.h>
21#include <linux/delay.h>
22#include <scsi/scsi_host.h>
23#include <linux/libata.h>
24
25#define DRV_NAME "pata_hpt3x3"
26#define DRV_VERSION "0.4.1"
27
28static int hpt3x3_probe_init(struct ata_port *ap)
29{
30 ap->cbl = ATA_CBL_PATA40;
31 return ata_std_prereset(ap);
32}
33
34/**
35 * hpt3x3_probe_reset - reset the hpt3x3 bus
36 * @ap: ATA port to reset
37 *
38 * Perform the housekeeping when doing an ATA bus reeset. We just
39 * need to force the cable type.
40 */
41
42static void hpt3x3_error_handler(struct ata_port *ap)
43{
44 return ata_bmdma_drive_eh(ap, hpt3x3_probe_init, ata_std_softreset, NULL, ata_std_postreset);
45}
46
47/**
48 * hpt3x3_set_piomode - PIO setup
49 * @ap: ATA interface
50 * @adev: device on the interface
51 *
52 * Set our PIO requirements. This is fairly simple on the HPT3x3 as
53 * all we have to do is clear the MWDMA and UDMA bits then load the
54 * mode number.
55 */
56
57static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
58{
59 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
60 u32 r1, r2;
61 int dn = 2 * ap->port_no + adev->devno;
62
63 pci_read_config_dword(pdev, 0x44, &r1);
64 pci_read_config_dword(pdev, 0x48, &r2);
65 /* Load the PIO timing number */
66 r1 &= ~(7 << (3 * dn));
67 r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
68 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
69
70 pci_write_config_dword(pdev, 0x44, r1);
71 pci_write_config_dword(pdev, 0x48, r2);
72}
73
74/**
75 * hpt3x3_set_dmamode - DMA timing setup
76 * @ap: ATA interface
77 * @adev: Device being configured
78 *
79 * Set up the channel for MWDMA or UDMA modes. Much the same as with
80 * PIO, load the mode number and then set MWDMA or UDMA flag.
81 */
82
83static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
84{
85 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
86 u32 r1, r2;
87 int dn = 2 * ap->port_no + adev->devno;
88 int mode_num = adev->dma_mode & 0x0F;
89
90 pci_read_config_dword(pdev, 0x44, &r1);
91 pci_read_config_dword(pdev, 0x48, &r2);
92 /* Load the timing number */
93 r1 &= ~(7 << (3 * dn));
94 r1 |= (mode_num << (3 * dn));
95 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
96
97 if (adev->dma_mode >= XFER_UDMA_0)
98 r2 |= 0x01 << dn; /* Ultra mode */
99 else
100 r2 |= 0x10 << dn; /* MWDMA */
101
102 pci_write_config_dword(pdev, 0x44, r1);
103 pci_write_config_dword(pdev, 0x48, r2);
104}
105
106static struct scsi_host_template hpt3x3_sht = {
107 .module = THIS_MODULE,
108 .name = DRV_NAME,
109 .ioctl = ata_scsi_ioctl,
110 .queuecommand = ata_scsi_queuecmd,
111 .can_queue = ATA_DEF_QUEUE,
112 .this_id = ATA_SHT_THIS_ID,
113 .sg_tablesize = LIBATA_MAX_PRD,
114 .max_sectors = ATA_MAX_SECTORS,
115 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
116 .emulated = ATA_SHT_EMULATED,
117 .use_clustering = ATA_SHT_USE_CLUSTERING,
118 .proc_name = DRV_NAME,
119 .dma_boundary = ATA_DMA_BOUNDARY,
120 .slave_configure = ata_scsi_slave_config,
121 .bios_param = ata_std_bios_param,
122};
123
124static struct ata_port_operations hpt3x3_port_ops = {
125 .port_disable = ata_port_disable,
126 .set_piomode = hpt3x3_set_piomode,
127 .set_dmamode = hpt3x3_set_dmamode,
128 .mode_filter = ata_pci_default_filter,
129
130 .tf_load = ata_tf_load,
131 .tf_read = ata_tf_read,
132 .check_status = ata_check_status,
133 .exec_command = ata_exec_command,
134 .dev_select = ata_std_dev_select,
135
136 .freeze = ata_bmdma_freeze,
137 .thaw = ata_bmdma_thaw,
138 .error_handler = hpt3x3_error_handler,
139 .post_internal_cmd = ata_bmdma_post_internal_cmd,
140
141 .bmdma_setup = ata_bmdma_setup,
142 .bmdma_start = ata_bmdma_start,
143 .bmdma_stop = ata_bmdma_stop,
144 .bmdma_status = ata_bmdma_status,
145
146 .qc_prep = ata_qc_prep,
147 .qc_issue = ata_qc_issue_prot,
148 .eng_timeout = ata_eng_timeout,
149 .data_xfer = ata_pio_data_xfer,
150
151 .irq_handler = ata_interrupt,
152 .irq_clear = ata_bmdma_irq_clear,
153
154 .port_start = ata_port_start,
155 .port_stop = ata_port_stop,
156 .host_stop = ata_host_stop
157};
158
159/**
160 * hpt3x3_init_one - Initialise an HPT343/363
161 * @dev: PCI device
162 * @id: Entry in match table
163 *
164 * Perform basic initialisation. The chip has a quirk that it won't
165 * function unless it is at XX00. The old ATA driver touched this up
166 * but we leave it for pci quirks to do properly.
167 */
168
169static int hpt3x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
170{
171 static struct ata_port_info info = {
172 .sht = &hpt3x3_sht,
173 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
174 .pio_mask = 0x1f,
175 .mwdma_mask = 0x07,
176 .udma_mask = 0x07,
177 .port_ops = &hpt3x3_port_ops
178 };
179 static struct ata_port_info *port_info[2] = { &info, &info };
180 u16 cmd;
181
182 /* Initialize the board */
183 pci_write_config_word(dev, 0x80, 0x00);
184 /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
185 pci_read_config_word(dev, PCI_COMMAND, &cmd);
186 if (cmd & PCI_COMMAND_MEMORY)
187 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
188 else
189 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
190
191 /* Now kick off ATA set up */
192 return ata_pci_init_one(dev, port_info, 2);
193}
194
195static struct pci_device_id hpt3x3[] = {
196 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343), },
197 { 0, },
198};
199
200static struct pci_driver hpt3x3_pci_driver = {
201 .name = DRV_NAME,
202 .id_table = hpt3x3,
203 .probe = hpt3x3_init_one,
204 .remove = ata_pci_remove_one
205};
206
207static int __init hpt3x3_init(void)
208{
209 return pci_register_driver(&hpt3x3_pci_driver);
210}
211
212
213static void __exit hpt3x3_exit(void)
214{
215 pci_unregister_driver(&hpt3x3_pci_driver);
216}
217
218
219MODULE_AUTHOR("Alan Cox");
220MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
221MODULE_LICENSE("GPL");
222MODULE_DEVICE_TABLE(pci, hpt3x3);
223MODULE_VERSION(DRV_VERSION);
224
225module_init(hpt3x3_init);
226module_exit(hpt3x3_exit);
diff --git a/drivers/ata/pata_isapnp.c b/drivers/ata/pata_isapnp.c
new file mode 100644
index 00000000000..73948c8b727
--- /dev/null
+++ b/drivers/ata/pata_isapnp.c
@@ -0,0 +1,156 @@
1
2/*
3 * pata-isapnp.c - ISA PnP PATA controller driver.
4 * Copyright 2005/2006 Red Hat Inc <alan@redhat.com>, all rights reserved.
5 *
6 * Based in part on ide-pnp.c by Andrey Panin <pazke@donpac.ru>
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/isapnp.h>
12#include <linux/init.h>
13#include <linux/blkdev.h>
14#include <linux/delay.h>
15#include <scsi/scsi_host.h>
16#include <linux/ata.h>
17#include <linux/libata.h>
18
19#define DRV_NAME "pata_isapnp"
20#define DRV_VERSION "0.1.5"
21
22static struct scsi_host_template isapnp_sht = {
23 .module = THIS_MODULE,
24 .name = DRV_NAME,
25 .ioctl = ata_scsi_ioctl,
26 .queuecommand = ata_scsi_queuecmd,
27 .can_queue = ATA_DEF_QUEUE,
28 .this_id = ATA_SHT_THIS_ID,
29 .sg_tablesize = LIBATA_MAX_PRD,
30 .max_sectors = ATA_MAX_SECTORS,
31 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
32 .emulated = ATA_SHT_EMULATED,
33 .use_clustering = ATA_SHT_USE_CLUSTERING,
34 .proc_name = DRV_NAME,
35 .dma_boundary = ATA_DMA_BOUNDARY,
36 .slave_configure = ata_scsi_slave_config,
37 .bios_param = ata_std_bios_param,
38};
39
40static struct ata_port_operations isapnp_port_ops = {
41 .port_disable = ata_port_disable,
42 .tf_load = ata_tf_load,
43 .tf_read = ata_tf_read,
44 .check_status = ata_check_status,
45 .exec_command = ata_exec_command,
46 .dev_select = ata_std_dev_select,
47
48 .freeze = ata_bmdma_freeze,
49 .thaw = ata_bmdma_thaw,
50 .error_handler = ata_bmdma_error_handler,
51 .post_internal_cmd = ata_bmdma_post_internal_cmd,
52
53 .qc_prep = ata_qc_prep,
54 .qc_issue = ata_qc_issue_prot,
55 .eng_timeout = ata_eng_timeout,
56 .data_xfer = ata_pio_data_xfer,
57
58 .irq_handler = ata_interrupt,
59 .irq_clear = ata_bmdma_irq_clear,
60
61 .port_start = ata_port_start,
62 .port_stop = ata_port_stop,
63 .host_stop = ata_host_stop
64};
65
66/**
67 * isapnp_init_one - attach an isapnp interface
68 * @idev: PnP device
69 * @dev_id: matching detect line
70 *
71 * Register an ISA bus IDE interface. Such interfaces are PIO 0 and
72 * non shared IRQ.
73 */
74
75static int isapnp_init_one(struct pnp_dev *idev, const struct pnp_device_id *dev_id)
76{
77 struct ata_probe_ent ae;
78
79 if (pnp_port_valid(idev, 0) == 0)
80 return -ENODEV;
81
82 /* FIXME: Should selected polled PIO here not fail */
83 if (pnp_irq_valid(idev, 0) == 0)
84 return -ENODEV;
85
86 memset(&ae, 0, sizeof(struct ata_probe_ent));
87 INIT_LIST_HEAD(&ae.node);
88 ae.dev = &idev->dev;
89 ae.port_ops = &isapnp_port_ops;
90 ae.sht = &isapnp_sht;
91 ae.n_ports = 1;
92 ae.pio_mask = 1; /* ISA so PIO 0 cycles */
93 ae.irq = pnp_irq(idev, 0);
94 ae.irq_flags = 0;
95 ae.port_flags = ATA_FLAG_SLAVE_POSS;
96 ae.port[0].cmd_addr = pnp_port_start(idev, 0);
97
98 if (pnp_port_valid(idev, 1) == 0) {
99 ae.port[0].altstatus_addr = pnp_port_start(idev, 1);
100 ae.port[0].ctl_addr = pnp_port_start(idev, 1);
101 ae.port_flags |= ATA_FLAG_SRST;
102 }
103 ata_std_ports(&ae.port[0]);
104
105 if (ata_device_add(&ae) == 0)
106 return -ENODEV;
107 return 0;
108}
109
110/**
111 * isapnp_remove_one - unplug an isapnp interface
112 * @idev: PnP device
113 *
114 * Remove a previously configured PnP ATA port. Called only on module
115 * unload events as the core does not currently deal with ISAPnP docking.
116 */
117
118static void isapnp_remove_one(struct pnp_dev *idev)
119{
120 struct device *dev = &idev->dev;
121 struct ata_host *host = dev_get_drvdata(dev);
122
123 ata_host_remove(host);
124 dev_set_drvdata(dev, NULL);
125}
126
127static struct pnp_device_id isapnp_devices[] = {
128 /* Generic ESDI/IDE/ATA compatible hard disk controller */
129 {.id = "PNP0600", .driver_data = 0},
130 {.id = ""}
131};
132
133static struct pnp_driver isapnp_driver = {
134 .name = DRV_NAME,
135 .id_table = isapnp_devices,
136 .probe = isapnp_init_one,
137 .remove = isapnp_remove_one,
138};
139
140static int __init isapnp_init(void)
141{
142 return pnp_register_driver(&isapnp_driver);
143}
144
145static void __exit isapnp_exit(void)
146{
147 pnp_unregister_driver(&isapnp_driver);
148}
149
150MODULE_AUTHOR("Alan Cox");
151MODULE_DESCRIPTION("low-level driver for ISA PnP ATA");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
155module_init(isapnp_init);
156module_exit(isapnp_exit);
diff --git a/drivers/ata/pata_it8172.c b/drivers/ata/pata_it8172.c
new file mode 100644
index 00000000000..f8367191fc7
--- /dev/null
+++ b/drivers/ata/pata_it8172.c
@@ -0,0 +1,288 @@
1/*
2 * pata_it8172.c - IT8172 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based heavily on
7 *
8 * BRIEF MODULE DESCRIPTION
9 * IT8172 IDE controller support
10 *
11 * Copyright 2000 MontaVista Software Inc.
12 * Author: MontaVista Software, Inc.
13 * stevel@mvista.com or source@mvista.com
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 *
35 * TODO
36 * Check for errata
37 * See if we really need to force native mode
38 * PIO timings (also lacking in original)
39 */
40
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/pci.h>
44#include <linux/init.h>
45#include <linux/blkdev.h>
46#include <linux/delay.h>
47#include <scsi/scsi_host.h>
48#include <linux/libata.h>
49
50#define DRV_NAME "pata_it8172"
51#define DRV_VERSION "0.3.1"
52
53static int it8172_pre_reset(struct ata_port *ap)
54{
55 static const struct pci_bits it8172_enable_bits[] = {
56 { 0x00, 0, 0x00, 0x00 },
57 { 0x40, 1, 0x00, 0x01 }
58 };
59
60 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
61
62 if (ap->port_no && !pci_test_config_bits(pdev, &it8172_enable_bits[ap->port_no])) {
63 ata_port_disable(ap);
64 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
65 return 0;
66 }
67 ap->cbl = ATA_CBL_PATA40;
68 return ata_std_prereset(ap);
69}
70
71static void it8172_error_handler(struct ata_port *ap)
72{
73 ata_bmdma_drive_eh(ap, it8172_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
74}
75
76/**
77 * it8172_set_pio_timing - set initial PIO mode data
78 * @ap: ATA interface
79 * @adev: ATA device
80 *
81 * Called by both the pio and dma setup functions to set the controller
82 * timings for PIO transfers. We must load both the mode number and
83 * timing values into the controller.
84 */
85
86static void it8172_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
87{
88 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
89 u16 reg40;
90
91 pci_read_config_word(pdev, 0x40, &reg40);
92
93 /*
94 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
95 * are being left at the default values of 8 PCI clocks (242 nsec
96 * for a 33 MHz clock). These can be safely shortened at higher
97 * PIO modes. The DIOR/DIOW pulse width and recovery times only
98 * apply to PIO modes, not to the DMA modes.
99 */
100
101 /*
102 * Enable port 0x44. The IT8172G spec is confused; it calls
103 * this register the "Slave IDE Timing Register", but in fact,
104 * it controls timing for both master and slave drives.
105 */
106
107 reg40 |= 0x4000;
108 if (adev->devno) {
109 reg40 &= 0xC006;
110 if (pio > 1)
111 /* Enable prefetch and IORDY sample-point */
112 reg40 |= 0x0060;
113 } else {
114 reg40 &= 0xC060;
115 if (pio > 1)
116 /* Enable prefetch and IORDY sample-point */
117 reg40 |= 0x0006;
118 }
119 /* Write back the enables */
120 pci_write_config_word(pdev, 0x40, reg40);
121}
122
123/**
124 * it8172_set_piomode - set initial PIO mode data
125 * @ap: ATA interface
126 * @adev: ATA device
127 *
128 * Called to do the PIO mode setup. We use a shared helper for this
129 * as the DMA setup must also adjust the PIO timing information.
130 */
131
132static void it8172_set_piomode(struct ata_port *ap, struct ata_device *adev)
133{
134 it8172_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
135}
136
137/**
138 * it8172_set_dmamode - set initial DMA mode data
139 * @ap: ATA interface
140 * @adev: ATA device
141 *
142 * Called to do the DMA mode setup. We must tune an appropriate PIO
143 * mode to match.
144 */
145
146static void it8172_set_dmamode(struct ata_port *ap, struct ata_device *adev)
147{
148 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
149 int dn = (2 * ap->port_no) + adev->devno;
150 u8 reg48, reg4a;
151 int pio;
152
153 static const int pio_map[] = { 1, 3, 4};
154 /*
155 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
156 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
157 * transfers on some drives, even though both numbers meet the minimum
158 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
159 * So the faster times are just commented out here. The good news is
160 * that the slower cycle time has very little affect on transfer
161 * performance.
162 */
163
164 pci_read_config_byte(pdev, 0x48, &reg48);
165 pci_read_config_byte(pdev, 0x4A, &reg4a);
166
167 reg4a &= ~(3 << (4 * dn));
168
169 if (adev->dma_mode >= XFER_UDMA_0) {
170 reg48 |= 1 << dn;
171#ifdef UDMA_TIMING_SET
172 reg4a |= ((adev->dma_mode - XFER_UDMA_0) << (4 * dn));
173#endif
174 pio = 4;
175 } else {
176 pio = pio_map[adev->dma_mode - XFER_MW_DMA_0];
177 reg48 &= ~ (1 << dn);
178 }
179 pci_write_config_byte(pdev, 0x48, reg48);
180 pci_write_config_byte(pdev, 0x4A, reg4a);
181 it8172_set_pio_timing(ap, adev, pio);
182
183}
184
185static struct scsi_host_template it8172_sht = {
186 .module = THIS_MODULE,
187 .name = DRV_NAME,
188 .ioctl = ata_scsi_ioctl,
189 .queuecommand = ata_scsi_queuecmd,
190 .can_queue = ATA_DEF_QUEUE,
191 .this_id = ATA_SHT_THIS_ID,
192 .sg_tablesize = LIBATA_MAX_PRD,
193 .max_sectors = ATA_MAX_SECTORS,
194 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
195 .emulated = ATA_SHT_EMULATED,
196 .use_clustering = ATA_SHT_USE_CLUSTERING,
197 .proc_name = DRV_NAME,
198 .dma_boundary = ATA_DMA_BOUNDARY,
199 .slave_configure = ata_scsi_slave_config,
200 .bios_param = ata_std_bios_param,
201};
202
203static struct ata_port_operations it8172_port_ops = {
204 .port_disable = ata_port_disable,
205 .set_piomode = it8172_set_piomode,
206 .set_dmamode = it8172_set_dmamode,
207 .mode_filter = ata_pci_default_filter,
208
209 .tf_load = ata_tf_load,
210 .tf_read = ata_tf_read,
211 .check_status = ata_check_status,
212 .exec_command = ata_exec_command,
213 .dev_select = ata_std_dev_select,
214
215 .freeze = ata_bmdma_freeze,
216 .thaw = ata_bmdma_thaw,
217 .error_handler = it8172_error_handler,
218 .post_internal_cmd = ata_bmdma_post_internal_cmd,
219
220 .bmdma_setup = ata_bmdma_setup,
221 .bmdma_start = ata_bmdma_start,
222 .bmdma_stop = ata_bmdma_stop,
223 .bmdma_status = ata_bmdma_status,
224
225 .qc_prep = ata_qc_prep,
226 .qc_issue = ata_qc_issue_prot,
227 .eng_timeout = ata_eng_timeout,
228 .data_xfer = ata_pio_data_xfer,
229
230 .irq_handler = ata_interrupt,
231 .irq_clear = ata_bmdma_irq_clear,
232
233 .port_start = ata_port_start,
234 .port_stop = ata_port_stop,
235 .host_stop = ata_host_stop
236};
237
238static int it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
239{
240 static struct ata_port_info info = {
241 .sht = &it8172_sht,
242 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
243 .pio_mask = 0x1f,
244 .mwdma_mask = 0x06, /* No MWDMA0 support */
245 .udma_mask = 0x7,
246 .port_ops = &it8172_port_ops
247 };
248 static struct ata_port_info *port_info[2] = { &info, &info };
249
250 if ((!(PCI_FUNC(dev->devfn) & 1) ||
251 (!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
252 return -ENODEV; /* IT8172 is more than an IDE controller */
253
254 return ata_pci_init_one(dev, port_info, 2);
255}
256
257static struct pci_device_id it8172[] = {
258 { PCI_DEVICE(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G), },
259 { 0, },
260};
261
262static struct pci_driver it8172_pci_driver = {
263 .name = DRV_NAME,
264 .id_table = it8172,
265 .probe = it8172_init_one,
266 .remove = ata_pci_remove_one
267};
268
269static int __init it8172_init(void)
270{
271 return pci_register_driver(&it8172_pci_driver);
272}
273
274
275static void __exit it8172_exit(void)
276{
277 pci_unregister_driver(&it8172_pci_driver);
278}
279
280
281MODULE_AUTHOR("Alan Cox");
282MODULE_DESCRIPTION("low-level driver for ITE IT8172");
283MODULE_LICENSE("GPL");
284MODULE_DEVICE_TABLE(pci, it8172);
285MODULE_VERSION(DRV_VERSION);
286
287module_init(it8172_init);
288module_exit(it8172_exit);
diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c
new file mode 100644
index 00000000000..c8a7798f8ce
--- /dev/null
+++ b/drivers/ata/pata_it821x.c
@@ -0,0 +1,847 @@
1/*
2 * ata-it821x.c - IT821x PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * it821x.c
9 *
10 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
11 *
12 * Copyright (C) 2004 Red Hat <alan@redhat.com>
13 *
14 * May be copied or modified under the terms of the GNU General Public License
15 * Based in part on the ITE vendor provided SCSI driver.
16 *
17 * Documentation available from
18 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
19 * Some other documents are NDA.
20 *
21 * The ITE8212 isn't exactly a standard IDE controller. It has two
22 * modes. In pass through mode then it is an IDE controller. In its smart
23 * mode its actually quite a capable hardware raid controller disguised
24 * as an IDE controller. Smart mode only understands DMA read/write and
25 * identify, none of the fancier commands apply. The IT8211 is identical
26 * in other respects but lacks the raid mode.
27 *
28 * Errata:
29 * o Rev 0x10 also requires master/slave hold the same DMA timings and
30 * cannot do ATAPI MWDMA.
31 * o The identify data for raid volumes lacks CHS info (technically ok)
32 * but also fails to set the LBA28 and other bits. We fix these in
33 * the IDE probe quirk code.
34 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
35 * raid then the controller firmware dies
36 * o Smart mode without RAID doesn't clear all the necessary identify
37 * bits to reduce the command set to the one used
38 *
39 * This has a few impacts on the driver
40 * - In pass through mode we do all the work you would expect
41 * - In smart mode the clocking set up is done by the controller generally
42 * but we must watch the other limits and filter.
43 * - There are a few extra vendor commands that actually talk to the
44 * controller but only work PIO with no IRQ.
45 *
46 * Vendor areas of the identify block in smart mode are used for the
47 * timing and policy set up. Each HDD in raid mode also has a serial
48 * block on the disk. The hardware extra commands are get/set chip status,
49 * rebuild, get rebuild status.
50 *
51 * In Linux the driver supports pass through mode as if the device was
52 * just another IDE controller. If the smart mode is running then
53 * volumes are managed by the controller firmware and each IDE "disk"
54 * is a raid volume. Even more cute - the controller can do automated
55 * hotplug and rebuild.
56 *
57 * The pass through controller itself is a little demented. It has a
58 * flaw that it has a single set of PIO/MWDMA timings per channel so
59 * non UDMA devices restrict each others performance. It also has a
60 * single clock source per channel so mixed UDMA100/133 performance
61 * isn't perfect and we have to pick a clock. Thankfully none of this
62 * matters in smart mode. ATAPI DMA is not currently supported.
63 *
64 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
65 *
66 * TODO
67 * - ATAPI and other speed filtering
68 * - Command filter in smart mode
69 * - RAID configuration ioctls
70 */
71
72#include <linux/kernel.h>
73#include <linux/module.h>
74#include <linux/pci.h>
75#include <linux/init.h>
76#include <linux/blkdev.h>
77#include <linux/delay.h>
78#include <scsi/scsi_host.h>
79#include <linux/libata.h>
80
81
82#define DRV_NAME "pata_it821x"
83#define DRV_VERSION "0.3.2"
84
85struct it821x_dev
86{
87 unsigned int smart:1, /* Are we in smart raid mode */
88 timing10:1; /* Rev 0x10 */
89 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
90 u8 want[2][2]; /* Mode/Pri log for master slave */
91 /* We need these for switching the clock when DMA goes on/off
92 The high byte is the 66Mhz timing */
93 u16 pio[2]; /* Cached PIO values */
94 u16 mwdma[2]; /* Cached MWDMA values */
95 u16 udma[2]; /* Cached UDMA values (per drive) */
96 u16 last_device; /* Master or slave loaded ? */
97};
98
99#define ATA_66 0
100#define ATA_50 1
101#define ATA_ANY 2
102
103#define UDMA_OFF 0
104#define MWDMA_OFF 0
105
106/*
107 * We allow users to force the card into non raid mode without
108 * flashing the alternative BIOS. This is also neccessary right now
109 * for embedded platforms that cannot run a PC BIOS but are using this
110 * device.
111 */
112
113static int it8212_noraid;
114
115/**
116 * it821x_pre_reset - probe
117 * @ap: ATA port
118 *
119 * Set the cable type
120 */
121
122static int it821x_pre_reset(struct ata_port *ap)
123{
124 ap->cbl = ATA_CBL_PATA80;
125 return ata_std_prereset(ap);
126}
127
128/**
129 * it821x_error_handler - probe/reset
130 * @ap: ATA port
131 *
132 * Set the cable type and trigger a probe
133 */
134
135static void it821x_error_handler(struct ata_port *ap)
136{
137 return ata_bmdma_drive_eh(ap, it821x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
138}
139
140/**
141 * it821x_program - program the PIO/MWDMA registers
142 * @ap: ATA port
143 * @adev: Device to program
144 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
145 *
146 * Program the PIO/MWDMA timing for this channel according to the
147 * current clock. These share the same register so are managed by
148 * the DMA start/stop sequence as with the old driver.
149 */
150
151static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing)
152{
153 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
154 struct it821x_dev *itdev = ap->private_data;
155 int channel = ap->port_no;
156 u8 conf;
157
158 /* Program PIO/MWDMA timing bits */
159 if (itdev->clock_mode == ATA_66)
160 conf = timing >> 8;
161 else
162 conf = timing & 0xFF;
163 pci_write_config_byte(pdev, 0x54 + 4 * channel, conf);
164}
165
166
167/**
168 * it821x_program_udma - program the UDMA registers
169 * @ap: ATA port
170 * @adev: ATA device to update
171 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
172 *
173 * Program the UDMA timing for this drive according to the
174 * current clock. Handles the dual clocks and also knows about
175 * the errata on the 0x10 revision. The UDMA errata is partly handled
176 * here and partly in start_dma.
177 */
178
179static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing)
180{
181 struct it821x_dev *itdev = ap->private_data;
182 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
183 int channel = ap->port_no;
184 int unit = adev->devno;
185 u8 conf;
186
187 /* Program UDMA timing bits */
188 if (itdev->clock_mode == ATA_66)
189 conf = timing >> 8;
190 else
191 conf = timing & 0xFF;
192 if (itdev->timing10 == 0)
193 pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf);
194 else {
195 /* Early revision must be programmed for both together */
196 pci_write_config_byte(pdev, 0x56 + 4 * channel, conf);
197 pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf);
198 }
199}
200
201/**
202 * it821x_clock_strategy
203 * @ap: ATA interface
204 * @adev: ATA device being updated
205 *
206 * Select between the 50 and 66Mhz base clocks to get the best
207 * results for this interface.
208 */
209
210static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev)
211{
212 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
213 struct it821x_dev *itdev = ap->private_data;
214 u8 unit = adev->devno;
215 struct ata_device *pair = ata_dev_pair(adev);
216
217 int clock, altclock;
218 u8 v;
219 int sel = 0;
220
221 /* Look for the most wanted clocking */
222 if (itdev->want[0][0] > itdev->want[1][0]) {
223 clock = itdev->want[0][1];
224 altclock = itdev->want[1][1];
225 } else {
226 clock = itdev->want[1][1];
227 altclock = itdev->want[0][1];
228 }
229
230 /* Master doesn't care does the slave ? */
231 if (clock == ATA_ANY)
232 clock = altclock;
233
234 /* Nobody cares - keep the same clock */
235 if (clock == ATA_ANY)
236 return;
237 /* No change */
238 if (clock == itdev->clock_mode)
239 return;
240
241 /* Load this into the controller */
242 if (clock == ATA_66)
243 itdev->clock_mode = ATA_66;
244 else {
245 itdev->clock_mode = ATA_50;
246 sel = 1;
247 }
248 pci_read_config_byte(pdev, 0x50, &v);
249 v &= ~(1 << (1 + ap->port_no));
250 v |= sel << (1 + ap->port_no);
251 pci_write_config_byte(pdev, 0x50, v);
252
253 /*
254 * Reprogram the UDMA/PIO of the pair drive for the switch
255 * MWDMA will be dealt with by the dma switcher
256 */
257 if (pair && itdev->udma[1-unit] != UDMA_OFF) {
258 it821x_program_udma(ap, pair, itdev->udma[1-unit]);
259 it821x_program(ap, pair, itdev->pio[1-unit]);
260 }
261 /*
262 * Reprogram the UDMA/PIO of our drive for the switch.
263 * MWDMA will be dealt with by the dma switcher
264 */
265 if (itdev->udma[unit] != UDMA_OFF) {
266 it821x_program_udma(ap, adev, itdev->udma[unit]);
267 it821x_program(ap, adev, itdev->pio[unit]);
268 }
269}
270
271/**
272 * it821x_passthru_set_piomode - set PIO mode data
273 * @ap: ATA interface
274 * @adev: ATA device
275 *
276 * Configure for PIO mode. This is complicated as the register is
277 * shared by PIO and MWDMA and for both channels.
278 */
279
280static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev)
281{
282 /* Spec says 89 ref driver uses 88 */
283 static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
284 static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
285
286 struct it821x_dev *itdev = ap->private_data;
287 int unit = adev->devno;
288 int mode_wanted = adev->pio_mode - XFER_PIO_0;
289
290 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
291 itdev->want[unit][1] = pio_want[mode_wanted];
292 itdev->want[unit][0] = 1; /* PIO is lowest priority */
293 itdev->pio[unit] = pio[mode_wanted];
294 it821x_clock_strategy(ap, adev);
295 it821x_program(ap, adev, itdev->pio[unit]);
296}
297
298/**
299 * it821x_passthru_set_dmamode - set initial DMA mode data
300 * @ap: ATA interface
301 * @adev: ATA device
302 *
303 * Set up the DMA modes. The actions taken depend heavily on the mode
304 * to use. If UDMA is used as is hopefully the usual case then the
305 * timing register is private and we need only consider the clock. If
306 * we are using MWDMA then we have to manage the setting ourself as
307 * we switch devices and mode.
308 */
309
310static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev)
311{
312 static const u16 dma[] = { 0x8866, 0x3222, 0x3121 };
313 static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
314 static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
315 static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
316
317 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
318 struct it821x_dev *itdev = ap->private_data;
319 int channel = ap->port_no;
320 int unit = adev->devno;
321 u8 conf;
322
323 if (adev->dma_mode >= XFER_UDMA_0) {
324 int mode_wanted = adev->dma_mode - XFER_UDMA_0;
325
326 itdev->want[unit][1] = udma_want[mode_wanted];
327 itdev->want[unit][0] = 3; /* UDMA is high priority */
328 itdev->mwdma[unit] = MWDMA_OFF;
329 itdev->udma[unit] = udma[mode_wanted];
330 if (mode_wanted >= 5)
331 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
332
333 /* UDMA on. Again revision 0x10 must do the pair */
334 pci_read_config_byte(pdev, 0x50, &conf);
335 if (itdev->timing10)
336 conf &= channel ? 0x9F: 0xE7;
337 else
338 conf &= ~ (1 << (3 + 2 * channel + unit));
339 pci_write_config_byte(pdev, 0x50, conf);
340 it821x_clock_strategy(ap, adev);
341 it821x_program_udma(ap, adev, itdev->udma[unit]);
342 } else {
343 int mode_wanted = adev->dma_mode - XFER_MW_DMA_0;
344
345 itdev->want[unit][1] = mwdma_want[mode_wanted];
346 itdev->want[unit][0] = 2; /* MWDMA is low priority */
347 itdev->mwdma[unit] = dma[mode_wanted];
348 itdev->udma[unit] = UDMA_OFF;
349
350 /* UDMA bits off - Revision 0x10 do them in pairs */
351 pci_read_config_byte(pdev, 0x50, &conf);
352 if (itdev->timing10)
353 conf |= channel ? 0x60: 0x18;
354 else
355 conf |= 1 << (3 + 2 * channel + unit);
356 pci_write_config_byte(pdev, 0x50, conf);
357 it821x_clock_strategy(ap, adev);
358 }
359}
360
361/**
362 * it821x_passthru_dma_start - DMA start callback
363 * @qc: Command in progress
364 *
365 * Usually drivers set the DMA timing at the point the set_dmamode call
366 * is made. IT821x however requires we load new timings on the
367 * transitions in some cases.
368 */
369
370static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc)
371{
372 struct ata_port *ap = qc->ap;
373 struct ata_device *adev = qc->dev;
374 struct it821x_dev *itdev = ap->private_data;
375 int unit = adev->devno;
376
377 if (itdev->mwdma[unit] != MWDMA_OFF)
378 it821x_program(ap, adev, itdev->mwdma[unit]);
379 else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10)
380 it821x_program_udma(ap, adev, itdev->udma[unit]);
381 ata_bmdma_start(qc);
382}
383
384/**
385 * it821x_passthru_dma_stop - DMA stop callback
386 * @qc: ATA command
387 *
388 * We loaded new timings in dma_start, as a result we need to restore
389 * the PIO timings in dma_stop so that the next command issue gets the
390 * right clock values.
391 */
392
393static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc)
394{
395 struct ata_port *ap = qc->ap;
396 struct ata_device *adev = qc->dev;
397 struct it821x_dev *itdev = ap->private_data;
398 int unit = adev->devno;
399
400 ata_bmdma_stop(qc);
401 if (itdev->mwdma[unit] != MWDMA_OFF)
402 it821x_program(ap, adev, itdev->pio[unit]);
403}
404
405
406/**
407 * it821x_passthru_dev_select - Select master/slave
408 * @ap: ATA port
409 * @device: Device number (not pointer)
410 *
411 * Device selection hook. If neccessary perform clock switching
412 */
413
414static void it821x_passthru_dev_select(struct ata_port *ap,
415 unsigned int device)
416{
417 struct it821x_dev *itdev = ap->private_data;
418 if (itdev && device != itdev->last_device) {
419 struct ata_device *adev = &ap->device[device];
420 it821x_program(ap, adev, itdev->pio[adev->devno]);
421 itdev->last_device = device;
422 }
423 ata_std_dev_select(ap, device);
424}
425
426/**
427 * it821x_smart_qc_issue_prot - wrap qc issue prot
428 * @qc: command
429 *
430 * Wrap the command issue sequence for the IT821x. We need to
431 * perform out own device selection timing loads before the
432 * usual happenings kick off
433 */
434
435static unsigned int it821x_smart_qc_issue_prot(struct ata_queued_cmd *qc)
436{
437 switch(qc->tf.command)
438 {
439 /* Commands the firmware supports */
440 case ATA_CMD_READ:
441 case ATA_CMD_READ_EXT:
442 case ATA_CMD_WRITE:
443 case ATA_CMD_WRITE_EXT:
444 case ATA_CMD_PIO_READ:
445 case ATA_CMD_PIO_READ_EXT:
446 case ATA_CMD_PIO_WRITE:
447 case ATA_CMD_PIO_WRITE_EXT:
448 case ATA_CMD_READ_MULTI:
449 case ATA_CMD_READ_MULTI_EXT:
450 case ATA_CMD_WRITE_MULTI:
451 case ATA_CMD_WRITE_MULTI_EXT:
452 case ATA_CMD_ID_ATA:
453 /* Arguably should just no-op this one */
454 case ATA_CMD_SET_FEATURES:
455 return ata_qc_issue_prot(qc);
456 }
457 printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command);
458 return AC_ERR_INVALID;
459}
460
461/**
462 * it821x_passthru_qc_issue_prot - wrap qc issue prot
463 * @qc: command
464 *
465 * Wrap the command issue sequence for the IT821x. We need to
466 * perform out own device selection timing loads before the
467 * usual happenings kick off
468 */
469
470static unsigned int it821x_passthru_qc_issue_prot(struct ata_queued_cmd *qc)
471{
472 it821x_passthru_dev_select(qc->ap, qc->dev->devno);
473 return ata_qc_issue_prot(qc);
474}
475
476/**
477 * it821x_smart_set_mode - mode setting
478 * @ap: interface to set up
479 *
480 * Use a non standard set_mode function. We don't want to be tuned.
481 * The BIOS configured everything. Our job is not to fiddle. We
482 * read the dma enabled bits from the PCI configuration of the device
483 * and respect them.
484 */
485
486static void it821x_smart_set_mode(struct ata_port *ap)
487{
488 int dma_enabled = 0;
489 int i;
490
491 /* Bits 5 and 6 indicate if DMA is active on master/slave */
492 /* It is possible that BMDMA isn't allocated */
493 if (ap->ioaddr.bmdma_addr)
494 dma_enabled = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
495
496 for (i = 0; i < ATA_MAX_DEVICES; i++) {
497 struct ata_device *dev = &ap->device[i];
498 if (ata_dev_enabled(dev)) {
499 /* We don't really care */
500 dev->pio_mode = XFER_PIO_0;
501 dev->dma_mode = XFER_MW_DMA_0;
502 /* We do need the right mode information for DMA or PIO
503 and this comes from the current configuration flags */
504 if (dma_enabled & (1 << (5 + i))) {
505 dev->xfer_mode = XFER_MW_DMA_0;
506 dev->xfer_shift = ATA_SHIFT_MWDMA;
507 dev->flags &= ~ATA_DFLAG_PIO;
508 } else {
509 dev->xfer_mode = XFER_PIO_0;
510 dev->xfer_shift = ATA_SHIFT_PIO;
511 dev->flags |= ATA_DFLAG_PIO;
512 }
513 }
514 }
515}
516
517/**
518 * it821x_dev_config - Called each device identify
519 * @ap: ATA port
520 * @adev: Device that has just been identified
521 *
522 * Perform the initial setup needed for each device that is chip
523 * special. In our case we need to lock the sector count to avoid
524 * blowing the brains out of the firmware with large LBA48 requests
525 *
526 * FIXME: When FUA appears we need to block FUA too. And SMART and
527 * basically we need to filter commands for this chip.
528 */
529
530static void it821x_dev_config(struct ata_port *ap, struct ata_device *adev)
531{
532 unsigned char model_num[40];
533 char *s;
534 unsigned int len;
535
536 /* This block ought to be a library routine as it is in several
537 drivers now */
538
539 ata_id_string(adev->id, model_num, ATA_ID_PROD_OFS,
540 sizeof(model_num));
541 s = &model_num[0];
542 len = strnlen(s, sizeof(model_num));
543
544 /* ATAPI specifies that empty space is blank-filled; remove blanks */
545 while ((len > 0) && (s[len - 1] == ' ')) {
546 len--;
547 s[len] = 0;
548 }
549
550 if (adev->max_sectors > 255)
551 adev->max_sectors = 255;
552
553 if (strstr(model_num, "Integrated Technology Express")) {
554 /* RAID mode */
555 printk(KERN_INFO "IT821x %sRAID%d volume",
556 adev->id[147]?"Bootable ":"",
557 adev->id[129]);
558 if (adev->id[129] != 1)
559 printk("(%dK stripe)", adev->id[146]);
560 printk(".\n");
561 }
562}
563
564
565/**
566 * it821x_check_atapi_dma - ATAPI DMA handler
567 * @qc: Command we are about to issue
568 *
569 * Decide if this ATAPI command can be issued by DMA on this
570 * controller. Return 0 if it can be.
571 */
572
573static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
574{
575 struct ata_port *ap = qc->ap;
576 struct it821x_dev *itdev = ap->private_data;
577
578 /* No ATAPI DMA in smart mode */
579 if (itdev->smart)
580 return -EOPNOTSUPP;
581 /* No ATAPI DMA on rev 10 */
582 if (itdev->timing10)
583 return -EOPNOTSUPP;
584 /* Cool */
585 return 0;
586}
587
588
589/**
590 * it821x_port_start - port setup
591 * @ap: ATA port being set up
592 *
593 * The it821x needs to maintain private data structures and also to
594 * use the standard PCI interface which lacks support for this
595 * functionality. We instead set up the private data on the port
596 * start hook, and tear it down on port stop
597 */
598
599static int it821x_port_start(struct ata_port *ap)
600{
601 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
602 struct it821x_dev *itdev;
603 u8 conf;
604
605 int ret = ata_port_start(ap);
606 if (ret < 0)
607 return ret;
608
609 ap->private_data = kmalloc(sizeof(struct it821x_dev), GFP_KERNEL);
610 if (ap->private_data == NULL) {
611 ata_port_stop(ap);
612 return -ENOMEM;
613 }
614
615 itdev = ap->private_data;
616 memset(itdev, 0, sizeof(struct it821x_dev));
617
618 pci_read_config_byte(pdev, 0x50, &conf);
619
620 if (conf & 1) {
621 itdev->smart = 1;
622 /* Long I/O's although allowed in LBA48 space cause the
623 onboard firmware to enter the twighlight zone */
624 /* No ATAPI DMA in this mode either */
625 }
626 /* Pull the current clocks from 0x50 */
627 if (conf & (1 << (1 + ap->port_no)))
628 itdev->clock_mode = ATA_50;
629 else
630 itdev->clock_mode = ATA_66;
631
632 itdev->want[0][1] = ATA_ANY;
633 itdev->want[1][1] = ATA_ANY;
634 itdev->last_device = -1;
635
636 pci_read_config_byte(pdev, PCI_REVISION_ID, &conf);
637 if (conf == 0x10) {
638 itdev->timing10 = 1;
639 /* Need to disable ATAPI DMA for this case */
640 if (!itdev->smart)
641 printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n");
642 }
643
644 return 0;
645}
646
647/**
648 * it821x_port_stop - port shutdown
649 * @ap: ATA port being removed
650 *
651 * Release the private objects we added in it821x_port_start
652 */
653
654static void it821x_port_stop(struct ata_port *ap) {
655 kfree(ap->private_data);
656 ap->private_data = NULL; /* We want an OOPS if we reuse this
657 too late! */
658 ata_port_stop(ap);
659}
660
661static struct scsi_host_template it821x_sht = {
662 .module = THIS_MODULE,
663 .name = DRV_NAME,
664 .ioctl = ata_scsi_ioctl,
665 .queuecommand = ata_scsi_queuecmd,
666 .can_queue = ATA_DEF_QUEUE,
667 .this_id = ATA_SHT_THIS_ID,
668 .sg_tablesize = LIBATA_MAX_PRD,
669 /* 255 sectors to begin with. This is locked in smart mode but not
670 in pass through */
671 .max_sectors = 255,
672 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
673 .emulated = ATA_SHT_EMULATED,
674 .use_clustering = ATA_SHT_USE_CLUSTERING,
675 .proc_name = DRV_NAME,
676 .dma_boundary = ATA_DMA_BOUNDARY,
677 .slave_configure = ata_scsi_slave_config,
678 .bios_param = ata_std_bios_param,
679};
680
681static struct ata_port_operations it821x_smart_port_ops = {
682 .set_mode = it821x_smart_set_mode,
683 .port_disable = ata_port_disable,
684 .tf_load = ata_tf_load,
685 .tf_read = ata_tf_read,
686 .mode_filter = ata_pci_default_filter,
687
688 .check_status = ata_check_status,
689 .check_atapi_dma= it821x_check_atapi_dma,
690 .exec_command = ata_exec_command,
691 .dev_select = ata_std_dev_select,
692 .dev_config = it821x_dev_config,
693
694 .freeze = ata_bmdma_freeze,
695 .thaw = ata_bmdma_thaw,
696 .error_handler = it821x_error_handler,
697 .post_internal_cmd = ata_bmdma_post_internal_cmd,
698
699 .bmdma_setup = ata_bmdma_setup,
700 .bmdma_start = ata_bmdma_start,
701 .bmdma_stop = ata_bmdma_stop,
702 .bmdma_status = ata_bmdma_status,
703
704 .qc_prep = ata_qc_prep,
705 .qc_issue = it821x_smart_qc_issue_prot,
706 .eng_timeout = ata_eng_timeout,
707 .data_xfer = ata_pio_data_xfer,
708
709 .irq_handler = ata_interrupt,
710 .irq_clear = ata_bmdma_irq_clear,
711
712 .port_start = it821x_port_start,
713 .port_stop = it821x_port_stop,
714 .host_stop = ata_host_stop
715};
716
717static struct ata_port_operations it821x_passthru_port_ops = {
718 .port_disable = ata_port_disable,
719 .set_piomode = it821x_passthru_set_piomode,
720 .set_dmamode = it821x_passthru_set_dmamode,
721 .mode_filter = ata_pci_default_filter,
722
723 .tf_load = ata_tf_load,
724 .tf_read = ata_tf_read,
725 .check_status = ata_check_status,
726 .exec_command = ata_exec_command,
727 .check_atapi_dma= it821x_check_atapi_dma,
728 .dev_select = it821x_passthru_dev_select,
729
730 .freeze = ata_bmdma_freeze,
731 .thaw = ata_bmdma_thaw,
732 .error_handler = it821x_error_handler,
733 .post_internal_cmd = ata_bmdma_post_internal_cmd,
734
735 .bmdma_setup = ata_bmdma_setup,
736 .bmdma_start = it821x_passthru_bmdma_start,
737 .bmdma_stop = it821x_passthru_bmdma_stop,
738 .bmdma_status = ata_bmdma_status,
739
740 .qc_prep = ata_qc_prep,
741 .qc_issue = it821x_passthru_qc_issue_prot,
742 .eng_timeout = ata_eng_timeout,
743 .data_xfer = ata_pio_data_xfer,
744
745 .irq_clear = ata_bmdma_irq_clear,
746 .irq_handler = ata_interrupt,
747
748 .port_start = it821x_port_start,
749 .port_stop = it821x_port_stop,
750 .host_stop = ata_host_stop
751};
752
753static void __devinit it821x_disable_raid(struct pci_dev *pdev)
754{
755 /* Reset local CPU, and set BIOS not ready */
756 pci_write_config_byte(pdev, 0x5E, 0x01);
757
758 /* Set to bypass mode, and reset PCI bus */
759 pci_write_config_byte(pdev, 0x50, 0x00);
760 pci_write_config_word(pdev, PCI_COMMAND,
761 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
762 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
763 pci_write_config_word(pdev, 0x40, 0xA0F3);
764
765 pci_write_config_dword(pdev,0x4C, 0x02040204);
766 pci_write_config_byte(pdev, 0x42, 0x36);
767 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
768}
769
770
771static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
772{
773 u8 conf;
774
775 static struct ata_port_info info_smart = {
776 .sht = &it821x_sht,
777 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
778 .pio_mask = 0x1f,
779 .mwdma_mask = 0x07,
780 .port_ops = &it821x_smart_port_ops
781 };
782 static struct ata_port_info info_passthru = {
783 .sht = &it821x_sht,
784 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
785 .pio_mask = 0x1f,
786 .mwdma_mask = 0x07,
787 .udma_mask = 0x7f,
788 .port_ops = &it821x_passthru_port_ops
789 };
790 static struct ata_port_info *port_info[2];
791
792 static char *mode[2] = { "pass through", "smart" };
793
794 /* Force the card into bypass mode if so requested */
795 if (it8212_noraid) {
796 printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n");
797 it821x_disable_raid(pdev);
798 }
799 pci_read_config_byte(pdev, 0x50, &conf);
800 conf &= 1;
801
802 printk(KERN_INFO DRV_NAME ": controller in %s mode.\n", mode[conf]);
803 if (conf == 0)
804 port_info[0] = port_info[1] = &info_passthru;
805 else
806 port_info[0] = port_info[1] = &info_smart;
807
808 return ata_pci_init_one(pdev, port_info, 2);
809}
810
811static struct pci_device_id it821x[] = {
812 { PCI_DEVICE(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8211), },
813 { PCI_DEVICE(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212), },
814 { 0, },
815};
816
817static struct pci_driver it821x_pci_driver = {
818 .name = DRV_NAME,
819 .id_table = it821x,
820 .probe = it821x_init_one,
821 .remove = ata_pci_remove_one
822};
823
824static int __init it821x_init(void)
825{
826 return pci_register_driver(&it821x_pci_driver);
827}
828
829
830static void __exit it821x_exit(void)
831{
832 pci_unregister_driver(&it821x_pci_driver);
833}
834
835
836MODULE_AUTHOR("Alan Cox");
837MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller");
838MODULE_LICENSE("GPL");
839MODULE_DEVICE_TABLE(pci, it821x);
840MODULE_VERSION(DRV_VERSION);
841
842
843module_param_named(noraid, it8212_noraid, int, S_IRUGO);
844MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode");
845
846module_init(it821x_init);
847module_exit(it821x_exit);
diff --git a/drivers/ata/pata_jmicron.c b/drivers/ata/pata_jmicron.c
new file mode 100644
index 00000000000..6832a643a9e
--- /dev/null
+++ b/drivers/ata/pata_jmicron.c
@@ -0,0 +1,266 @@
1/*
2 * pata_jmicron.c - JMicron ATA driver for non AHCI mode. This drives the
3 * PATA port of the controller. The SATA ports are
4 * driven by AHCI in the usual configuration although
5 * this driver can handle other setups if we need it.
6 *
7 * (c) 2006 Red Hat <alan@redhat.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/init.h>
14#include <linux/blkdev.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <scsi/scsi_host.h>
18#include <linux/libata.h>
19#include <linux/ata.h>
20
21#define DRV_NAME "pata_jmicron"
22#define DRV_VERSION "0.1.2"
23
24typedef enum {
25 PORT_PATA0 = 0,
26 PORT_PATA1 = 1,
27 PORT_SATA = 2,
28} port_type;
29
30/**
31 * jmicron_pre_reset - check for 40/80 pin
32 * @ap: Port
33 *
34 * Perform the PATA port setup we need.
35
36 * On the Jmicron 361/363 there is a single PATA port that can be mapped
37 * either as primary or secondary (or neither). We don't do any policy
38 * and setup here. We assume that has been done by init_one and the
39 * BIOS.
40 */
41
42static int jmicron_pre_reset(struct ata_port *ap)
43{
44 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
45 u32 control;
46 u32 control5;
47 int port_mask = 1<< (4 * ap->port_no);
48 int port = ap->port_no;
49 port_type port_map[2];
50
51 /* Check if our port is enabled */
52 pci_read_config_dword(pdev, 0x40, &control);
53 if ((control & port_mask) == 0)
54 return 0;
55
56 /* There are two basic mappings. One has the two SATA ports merged
57 as master/slave and the secondary as PATA, the other has only the
58 SATA port mapped */
59 if (control & (1 << 23)) {
60 port_map[0] = PORT_SATA;
61 port_map[1] = PORT_PATA0;
62 } else {
63 port_map[0] = PORT_SATA;
64 port_map[1] = PORT_SATA;
65 }
66
67 /* The 365/366 may have this bit set to map the second PATA port
68 as the internal primary channel */
69 pci_read_config_dword(pdev, 0x80, &control5);
70 if (control5 & (1<<24))
71 port_map[0] = PORT_PATA1;
72
73 /* The two ports may then be logically swapped by the firmware */
74 if (control & (1 << 22))
75 port = port ^ 1;
76
77 /*
78 * Now we know which physical port we are talking about we can
79 * actually do our cable checking etc. Thankfully we don't need
80 * to do the plumbing for other cases.
81 */
82 switch (port_map[port])
83 {
84 case PORT_PATA0:
85 if (control & (1 << 5))
86 return 0;
87 if (control & (1 << 3)) /* 40/80 pin primary */
88 ap->cbl = ATA_CBL_PATA40;
89 else
90 ap->cbl = ATA_CBL_PATA80;
91 break;
92 case PORT_PATA1:
93 /* Bit 21 is set if the port is enabled */
94 if ((control5 & (1 << 21)) == 0)
95 return 0;
96 if (control5 & (1 << 19)) /* 40/80 pin secondary */
97 ap->cbl = ATA_CBL_PATA40;
98 else
99 ap->cbl = ATA_CBL_PATA80;
100 break;
101 case PORT_SATA:
102 ap->cbl = ATA_CBL_SATA;
103 break;
104 }
105 return ata_std_prereset(ap);
106}
107
108/**
109 * jmicron_error_handler - Setup and error handler
110 * @ap: Port to handle
111 *
112 * LOCKING:
113 * None (inherited from caller).
114 */
115
116static void jmicron_error_handler(struct ata_port *ap)
117{
118 return ata_bmdma_drive_eh(ap, jmicron_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
119}
120
121/* No PIO or DMA methods needed for this device */
122
123static struct scsi_host_template jmicron_sht = {
124 .module = THIS_MODULE,
125 .name = DRV_NAME,
126 .ioctl = ata_scsi_ioctl,
127 .queuecommand = ata_scsi_queuecmd,
128 .can_queue = ATA_DEF_QUEUE,
129 .this_id = ATA_SHT_THIS_ID,
130 .sg_tablesize = LIBATA_MAX_PRD,
131 /* Special handling needed if you have sector or LBA48 limits */
132 .max_sectors = ATA_MAX_SECTORS,
133 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
134 .emulated = ATA_SHT_EMULATED,
135 .use_clustering = ATA_SHT_USE_CLUSTERING,
136 .proc_name = DRV_NAME,
137 .dma_boundary = ATA_DMA_BOUNDARY,
138 .slave_configure = ata_scsi_slave_config,
139 /* Use standard CHS mapping rules */
140 .bios_param = ata_std_bios_param,
141};
142
143static const struct ata_port_operations jmicron_ops = {
144 .port_disable = ata_port_disable,
145
146 /* Task file is PCI ATA format, use helpers */
147 .tf_load = ata_tf_load,
148 .tf_read = ata_tf_read,
149 .check_status = ata_check_status,
150 .exec_command = ata_exec_command,
151 .dev_select = ata_std_dev_select,
152
153 .freeze = ata_bmdma_freeze,
154 .thaw = ata_bmdma_thaw,
155 .error_handler = jmicron_error_handler,
156 .post_internal_cmd = ata_bmdma_post_internal_cmd,
157
158 /* BMDMA handling is PCI ATA format, use helpers */
159 .bmdma_setup = ata_bmdma_setup,
160 .bmdma_start = ata_bmdma_start,
161 .bmdma_stop = ata_bmdma_stop,
162 .bmdma_status = ata_bmdma_status,
163 .qc_prep = ata_qc_prep,
164 .qc_issue = ata_qc_issue_prot,
165 .data_xfer = ata_pio_data_xfer,
166
167 /* Timeout handling. Special recovery hooks here */
168 .eng_timeout = ata_eng_timeout,
169 .irq_handler = ata_interrupt,
170 .irq_clear = ata_bmdma_irq_clear,
171
172 /* Generic PATA PCI ATA helpers */
173 .port_start = ata_port_start,
174 .port_stop = ata_port_stop,
175 .host_stop = ata_host_stop,
176};
177
178
179/**
180 * jmicron_init_one - Register Jmicron ATA PCI device with kernel services
181 * @pdev: PCI device to register
182 * @ent: Entry in jmicron_pci_tbl matching with @pdev
183 *
184 * Called from kernel PCI layer.
185 *
186 * LOCKING:
187 * Inherited from PCI layer (may sleep).
188 *
189 * RETURNS:
190 * Zero on success, or -ERRNO value.
191 */
192
193static int jmicron_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
194{
195 static struct ata_port_info info = {
196 .sht = &jmicron_sht,
197 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
198
199 .pio_mask = 0x1f,
200 .mwdma_mask = 0x07,
201 .udma_mask = 0x3f,
202
203 .port_ops = &jmicron_ops,
204 };
205 struct ata_port_info *port_info[2] = { &info, &info };
206
207 u32 reg;
208
209 if (id->driver_data != 368) {
210 /* Put the controller into AHCI mode in case the AHCI driver
211 has not yet been loaded. This can be done with either
212 function present */
213
214 /* FIXME: We may want a way to override this in future */
215 pci_write_config_byte(pdev, 0x41, 0xa1);
216 }
217
218 /* PATA controller is fn 1, AHCI is fn 0 */
219 if (PCI_FUNC(pdev->devfn) != 1)
220 return -ENODEV;
221
222 if ( id->driver_data == 365 || id->driver_data == 366) {
223 /* The 365/66 have two PATA channels, redirect the second */
224 pci_read_config_dword(pdev, 0x80, &reg);
225 reg |= (1 << 24); /* IDE1 to PATA IDE secondary */
226 pci_write_config_dword(pdev, 0x80, reg);
227 }
228
229 return ata_pci_init_one(pdev, port_info, 2);
230}
231
232static const struct pci_device_id jmicron_pci_tbl[] = {
233 { PCI_DEVICE(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361), 361},
234 { PCI_DEVICE(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363), 363},
235 { PCI_DEVICE(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365), 365},
236 { PCI_DEVICE(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366), 366},
237 { PCI_DEVICE(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368), 368},
238 { } /* terminate list */
239};
240
241static struct pci_driver jmicron_pci_driver = {
242 .name = DRV_NAME,
243 .id_table = jmicron_pci_tbl,
244 .probe = jmicron_init_one,
245 .remove = ata_pci_remove_one,
246};
247
248static int __init jmicron_init(void)
249{
250 return pci_register_driver(&jmicron_pci_driver);
251}
252
253static void __exit jmicron_exit(void)
254{
255 pci_unregister_driver(&jmicron_pci_driver);
256}
257
258module_init(jmicron_init);
259module_exit(jmicron_exit);
260
261MODULE_AUTHOR("Alan Cox");
262MODULE_DESCRIPTION("SCSI low-level driver for Jmicron PATA ports");
263MODULE_LICENSE("GPL");
264MODULE_DEVICE_TABLE(pci, jmicron_pci_tbl);
265MODULE_VERSION(DRV_VERSION);
266
diff --git a/drivers/ata/pata_legacy.c b/drivers/ata/pata_legacy.c
new file mode 100644
index 00000000000..eb510660b42
--- /dev/null
+++ b/drivers/ata/pata_legacy.c
@@ -0,0 +1,949 @@
1/*
2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * An ATA driver for the legacy ATA ports.
20 *
21 * Data Sources:
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
23 * HT6560 series:
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
28 *
29 * Unsupported but docs exist:
30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
31 * Winbond W83759A
32 *
33 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
34 * on PC class systems. There are three hybrid devices that are exceptions
35 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
36 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
37 *
38 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
39 * opti82c465mv/promise 20230c/20630
40 *
41 * Use the autospeed and pio_mask options with:
42 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
43 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
44 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
45 * Winbond W83759A, Promise PDC20230-B
46 *
47 * For now use autospeed and pio_mask as above with the W83759A. This may
48 * change.
49 *
50 * TODO
51 * Merge existing pata_qdi driver
52 *
53 */
54
55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <scsi/scsi_host.h>
62#include <linux/ata.h>
63#include <linux/libata.h>
64#include <linux/platform_device.h>
65
66#define DRV_NAME "pata_legacy"
67#define DRV_VERSION "0.5.3"
68
69#define NR_HOST 6
70
71static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
72static int legacy_irq[NR_HOST] = { 15, 14, 11, 10, 8, 12 };
73
74struct legacy_data {
75 unsigned long timing;
76 u8 clock[2];
77 u8 last;
78 int fast;
79 struct platform_device *platform_dev;
80
81};
82
83static struct legacy_data legacy_data[NR_HOST];
84static struct ata_host *legacy_host[NR_HOST];
85static int nr_legacy_host;
86
87
88static int probe_all; /* Set to check all ISA port ranges */
89static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */
90static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */
91static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */
92static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */
93static int autospeed; /* Chip present which snoops speed changes */
94static int pio_mask = 0x1F; /* PIO range for autospeed devices */
95
96/**
97 * legacy_set_mode - mode setting
98 * @ap: IDE interface
99 *
100 * Use a non standard set_mode function. We don't want to be tuned.
101 *
102 * The BIOS configured everything. Our job is not to fiddle. Just use
103 * whatever PIO the hardware is using and leave it at that. When we
104 * get some kind of nice user driven API for control then we can
105 * expand on this as per hdparm in the base kernel.
106 */
107
108static void legacy_set_mode(struct ata_port *ap)
109{
110 int i;
111
112 for (i = 0; i < ATA_MAX_DEVICES; i++) {
113 struct ata_device *dev = &ap->device[i];
114 if (ata_dev_enabled(dev)) {
115 dev->pio_mode = XFER_PIO_0;
116 dev->xfer_mode = XFER_PIO_0;
117 dev->xfer_shift = ATA_SHIFT_PIO;
118 dev->flags |= ATA_DFLAG_PIO;
119 }
120 }
121}
122
123static struct scsi_host_template legacy_sht = {
124 .module = THIS_MODULE,
125 .name = DRV_NAME,
126 .ioctl = ata_scsi_ioctl,
127 .queuecommand = ata_scsi_queuecmd,
128 .can_queue = ATA_DEF_QUEUE,
129 .this_id = ATA_SHT_THIS_ID,
130 .sg_tablesize = LIBATA_MAX_PRD,
131 .max_sectors = ATA_MAX_SECTORS,
132 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
133 .emulated = ATA_SHT_EMULATED,
134 .use_clustering = ATA_SHT_USE_CLUSTERING,
135 .proc_name = DRV_NAME,
136 .dma_boundary = ATA_DMA_BOUNDARY,
137 .slave_configure = ata_scsi_slave_config,
138 .bios_param = ata_std_bios_param,
139};
140
141/*
142 * These ops are used if the user indicates the hardware
143 * snoops the commands to decide on the mode and handles the
144 * mode selection "magically" itself. Several legacy controllers
145 * do this. The mode range can be set if it is not 0x1F by setting
146 * pio_mask as well.
147 */
148
149static struct ata_port_operations simple_port_ops = {
150 .port_disable = ata_port_disable,
151 .tf_load = ata_tf_load,
152 .tf_read = ata_tf_read,
153 .check_status = ata_check_status,
154 .exec_command = ata_exec_command,
155 .dev_select = ata_std_dev_select,
156
157 .freeze = ata_bmdma_freeze,
158 .thaw = ata_bmdma_thaw,
159 .error_handler = ata_bmdma_error_handler,
160 .post_internal_cmd = ata_bmdma_post_internal_cmd,
161
162 .qc_prep = ata_qc_prep,
163 .qc_issue = ata_qc_issue_prot,
164 .eng_timeout = ata_eng_timeout,
165 .data_xfer = ata_pio_data_xfer_noirq,
166
167 .irq_handler = ata_interrupt,
168 .irq_clear = ata_bmdma_irq_clear,
169
170 .port_start = ata_port_start,
171 .port_stop = ata_port_stop,
172 .host_stop = ata_host_stop
173};
174
175static struct ata_port_operations legacy_port_ops = {
176 .set_mode = legacy_set_mode,
177
178 .port_disable = ata_port_disable,
179 .tf_load = ata_tf_load,
180 .tf_read = ata_tf_read,
181 .check_status = ata_check_status,
182 .exec_command = ata_exec_command,
183 .dev_select = ata_std_dev_select,
184
185 .error_handler = ata_bmdma_error_handler,
186
187 .qc_prep = ata_qc_prep,
188 .qc_issue = ata_qc_issue_prot,
189 .eng_timeout = ata_eng_timeout,
190 .data_xfer = ata_pio_data_xfer_noirq,
191
192 .irq_handler = ata_interrupt,
193 .irq_clear = ata_bmdma_irq_clear,
194
195 .port_start = ata_port_start,
196 .port_stop = ata_port_stop,
197 .host_stop = ata_host_stop
198};
199
200/*
201 * Promise 20230C and 20620 support
202 *
203 * This controller supports PIO0 to PIO2. We set PIO timings conservatively to
204 * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to
205 * controller and PIO'd to the host and not supported.
206 */
207
208static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
209{
210 int tries = 5;
211 int pio = adev->pio_mode - XFER_PIO_0;
212 u8 rt;
213 unsigned long flags;
214
215 /* Safe as UP only. Force I/Os to occur together */
216
217 local_irq_save(flags);
218
219 /* Unlock the control interface */
220 do
221 {
222 inb(0x1F5);
223 outb(inb(0x1F2) | 0x80, 0x1F2);
224 inb(0x1F2);
225 inb(0x3F6);
226 inb(0x3F6);
227 inb(0x1F2);
228 inb(0x1F2);
229 }
230 while((inb(0x1F2) & 0x80) && --tries);
231
232 local_irq_restore(flags);
233
234 outb(inb(0x1F4) & 0x07, 0x1F4);
235
236 rt = inb(0x1F3);
237 rt &= 0x07 << (3 * adev->devno);
238 if (pio)
239 rt |= (1 + 3 * pio) << (3 * adev->devno);
240
241 udelay(100);
242 outb(inb(0x1F2) | 0x01, 0x1F2);
243 udelay(100);
244 inb(0x1F5);
245
246}
247
248static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
249{
250 struct ata_port *ap = adev->ap;
251 int slop = buflen & 3;
252 unsigned long flags;
253
254 if (ata_id_has_dword_io(adev->id)) {
255 local_irq_save(flags);
256
257 /* Perform the 32bit I/O synchronization sequence */
258 inb(ap->ioaddr.nsect_addr);
259 inb(ap->ioaddr.nsect_addr);
260 inb(ap->ioaddr.nsect_addr);
261
262 /* Now the data */
263
264 if (write_data)
265 outsl(ap->ioaddr.data_addr, buf, buflen >> 2);
266 else
267 insl(ap->ioaddr.data_addr, buf, buflen >> 2);
268
269 if (unlikely(slop)) {
270 u32 pad;
271 if (write_data) {
272 memcpy(&pad, buf + buflen - slop, slop);
273 outl(le32_to_cpu(pad), ap->ioaddr.data_addr);
274 } else {
275 pad = cpu_to_le16(inl(ap->ioaddr.data_addr));
276 memcpy(buf + buflen - slop, &pad, slop);
277 }
278 }
279 local_irq_restore(flags);
280 }
281 else
282 ata_pio_data_xfer_noirq(adev, buf, buflen, write_data);
283}
284
285static struct ata_port_operations pdc20230_port_ops = {
286 .set_piomode = pdc20230_set_piomode,
287
288 .port_disable = ata_port_disable,
289 .tf_load = ata_tf_load,
290 .tf_read = ata_tf_read,
291 .check_status = ata_check_status,
292 .exec_command = ata_exec_command,
293 .dev_select = ata_std_dev_select,
294
295 .error_handler = ata_bmdma_error_handler,
296
297 .qc_prep = ata_qc_prep,
298 .qc_issue = ata_qc_issue_prot,
299 .eng_timeout = ata_eng_timeout,
300 .data_xfer = pdc_data_xfer_vlb,
301
302 .irq_handler = ata_interrupt,
303 .irq_clear = ata_bmdma_irq_clear,
304
305 .port_start = ata_port_start,
306 .port_stop = ata_port_stop,
307 .host_stop = ata_host_stop
308};
309
310/*
311 * Holtek 6560A support
312 *
313 * This controller supports PIO0 to PIO2 (no IORDY even though higher timings
314 * can be loaded).
315 */
316
317static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
318{
319 u8 active, recover;
320 struct ata_timing t;
321
322 /* Get the timing data in cycles. For now play safe at 50Mhz */
323 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
324
325 active = FIT(t.active, 2, 15);
326 recover = FIT(t.recover, 4, 15);
327
328 inb(0x3E6);
329 inb(0x3E6);
330 inb(0x3E6);
331 inb(0x3E6);
332
333 outb(recover << 4 | active, ap->ioaddr.device_addr);
334 inb(ap->ioaddr.status_addr);
335}
336
337static struct ata_port_operations ht6560a_port_ops = {
338 .set_piomode = ht6560a_set_piomode,
339
340 .port_disable = ata_port_disable,
341 .tf_load = ata_tf_load,
342 .tf_read = ata_tf_read,
343 .check_status = ata_check_status,
344 .exec_command = ata_exec_command,
345 .dev_select = ata_std_dev_select,
346
347 .error_handler = ata_bmdma_error_handler,
348
349 .qc_prep = ata_qc_prep,
350 .qc_issue = ata_qc_issue_prot,
351 .eng_timeout = ata_eng_timeout,
352 .data_xfer = ata_pio_data_xfer, /* Check vlb/noirq */
353
354 .irq_handler = ata_interrupt,
355 .irq_clear = ata_bmdma_irq_clear,
356
357 .port_start = ata_port_start,
358 .port_stop = ata_port_stop,
359 .host_stop = ata_host_stop
360};
361
362/*
363 * Holtek 6560B support
364 *
365 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting
366 * unless we see an ATAPI device in which case we force it off.
367 *
368 * FIXME: need to implement 2nd channel support.
369 */
370
371static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
372{
373 u8 active, recover;
374 struct ata_timing t;
375
376 /* Get the timing data in cycles. For now play safe at 50Mhz */
377 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
378
379 active = FIT(t.active, 2, 15);
380 recover = FIT(t.recover, 2, 16);
381 recover &= 0x15;
382
383 inb(0x3E6);
384 inb(0x3E6);
385 inb(0x3E6);
386 inb(0x3E6);
387
388 outb(recover << 4 | active, ap->ioaddr.device_addr);
389
390 if (adev->class != ATA_DEV_ATA) {
391 u8 rconf = inb(0x3E6);
392 if (rconf & 0x24) {
393 rconf &= ~ 0x24;
394 outb(rconf, 0x3E6);
395 }
396 }
397 inb(ap->ioaddr.status_addr);
398}
399
400static struct ata_port_operations ht6560b_port_ops = {
401 .set_piomode = ht6560b_set_piomode,
402
403 .port_disable = ata_port_disable,
404 .tf_load = ata_tf_load,
405 .tf_read = ata_tf_read,
406 .check_status = ata_check_status,
407 .exec_command = ata_exec_command,
408 .dev_select = ata_std_dev_select,
409
410 .error_handler = ata_bmdma_error_handler,
411
412 .qc_prep = ata_qc_prep,
413 .qc_issue = ata_qc_issue_prot,
414 .eng_timeout = ata_eng_timeout,
415 .data_xfer = ata_pio_data_xfer, /* FIXME: Check 32bit and noirq */
416
417 .irq_handler = ata_interrupt,
418 .irq_clear = ata_bmdma_irq_clear,
419
420 .port_start = ata_port_start,
421 .port_stop = ata_port_stop,
422 .host_stop = ata_host_stop
423};
424
425/*
426 * Opti core chipset helpers
427 */
428
429/**
430 * opti_syscfg - read OPTI chipset configuration
431 * @reg: Configuration register to read
432 *
433 * Returns the value of an OPTI system board configuration register.
434 */
435
436static u8 opti_syscfg(u8 reg)
437{
438 unsigned long flags;
439 u8 r;
440
441 /* Uniprocessor chipset and must force cycles adjancent */
442 local_irq_save(flags);
443 outb(reg, 0x22);
444 r = inb(0x24);
445 local_irq_restore(flags);
446 return r;
447}
448
449/*
450 * Opti 82C611A
451 *
452 * This controller supports PIO0 to PIO3.
453 */
454
455static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev)
456{
457 u8 active, recover, setup;
458 struct ata_timing t;
459 struct ata_device *pair = ata_dev_pair(adev);
460 int clock;
461 int khz[4] = { 50000, 40000, 33000, 25000 };
462 u8 rc;
463
464 /* Enter configuration mode */
465 inw(ap->ioaddr.error_addr);
466 inw(ap->ioaddr.error_addr);
467 outb(3, ap->ioaddr.nsect_addr);
468
469 /* Read VLB clock strapping */
470 clock = 1000000000 / khz[inb(ap->ioaddr.lbah_addr) & 0x03];
471
472 /* Get the timing data in cycles */
473 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
474
475 /* Setup timing is shared */
476 if (pair) {
477 struct ata_timing tp;
478 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
479
480 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
481 }
482
483 active = FIT(t.active, 2, 17) - 2;
484 recover = FIT(t.recover, 1, 16) - 1;
485 setup = FIT(t.setup, 1, 4) - 1;
486
487 /* Select the right timing bank for write timing */
488 rc = inb(ap->ioaddr.lbal_addr);
489 rc &= 0x7F;
490 rc |= (adev->devno << 7);
491 outb(rc, ap->ioaddr.lbal_addr);
492
493 /* Write the timings */
494 outb(active << 4 | recover, ap->ioaddr.error_addr);
495
496 /* Select the right bank for read timings, also
497 load the shared timings for address */
498 rc = inb(ap->ioaddr.device_addr);
499 rc &= 0xC0;
500 rc |= adev->devno; /* Index select */
501 rc |= (setup << 4) | 0x04;
502 outb(rc, ap->ioaddr.device_addr);
503
504 /* Load the read timings */
505 outb(active << 4 | recover, ap->ioaddr.data_addr);
506
507 /* Ensure the timing register mode is right */
508 rc = inb (ap->ioaddr.lbal_addr);
509 rc &= 0x73;
510 rc |= 0x84;
511 outb(rc, ap->ioaddr.lbal_addr);
512
513 /* Exit command mode */
514 outb(0x83, ap->ioaddr.nsect_addr);
515}
516
517
518static struct ata_port_operations opti82c611a_port_ops = {
519 .set_piomode = opti82c611a_set_piomode,
520
521 .port_disable = ata_port_disable,
522 .tf_load = ata_tf_load,
523 .tf_read = ata_tf_read,
524 .check_status = ata_check_status,
525 .exec_command = ata_exec_command,
526 .dev_select = ata_std_dev_select,
527
528 .error_handler = ata_bmdma_error_handler,
529
530 .qc_prep = ata_qc_prep,
531 .qc_issue = ata_qc_issue_prot,
532 .eng_timeout = ata_eng_timeout,
533 .data_xfer = ata_pio_data_xfer,
534
535 .irq_handler = ata_interrupt,
536 .irq_clear = ata_bmdma_irq_clear,
537
538 .port_start = ata_port_start,
539 .port_stop = ata_port_stop,
540 .host_stop = ata_host_stop
541};
542
543/*
544 * Opti 82C465MV
545 *
546 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
547 * version is dual channel but doesn't have a lot of unique registers.
548 */
549
550static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
551{
552 u8 active, recover, setup;
553 struct ata_timing t;
554 struct ata_device *pair = ata_dev_pair(adev);
555 int clock;
556 int khz[4] = { 50000, 40000, 33000, 25000 };
557 u8 rc;
558 u8 sysclk;
559
560 /* Get the clock */
561 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
562
563 /* Enter configuration mode */
564 inw(ap->ioaddr.error_addr);
565 inw(ap->ioaddr.error_addr);
566 outb(3, ap->ioaddr.nsect_addr);
567
568 /* Read VLB clock strapping */
569 clock = 1000000000 / khz[sysclk];
570
571 /* Get the timing data in cycles */
572 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
573
574 /* Setup timing is shared */
575 if (pair) {
576 struct ata_timing tp;
577 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
578
579 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
580 }
581
582 active = FIT(t.active, 2, 17) - 2;
583 recover = FIT(t.recover, 1, 16) - 1;
584 setup = FIT(t.setup, 1, 4) - 1;
585
586 /* Select the right timing bank for write timing */
587 rc = inb(ap->ioaddr.lbal_addr);
588 rc &= 0x7F;
589 rc |= (adev->devno << 7);
590 outb(rc, ap->ioaddr.lbal_addr);
591
592 /* Write the timings */
593 outb(active << 4 | recover, ap->ioaddr.error_addr);
594
595 /* Select the right bank for read timings, also
596 load the shared timings for address */
597 rc = inb(ap->ioaddr.device_addr);
598 rc &= 0xC0;
599 rc |= adev->devno; /* Index select */
600 rc |= (setup << 4) | 0x04;
601 outb(rc, ap->ioaddr.device_addr);
602
603 /* Load the read timings */
604 outb(active << 4 | recover, ap->ioaddr.data_addr);
605
606 /* Ensure the timing register mode is right */
607 rc = inb (ap->ioaddr.lbal_addr);
608 rc &= 0x73;
609 rc |= 0x84;
610 outb(rc, ap->ioaddr.lbal_addr);
611
612 /* Exit command mode */
613 outb(0x83, ap->ioaddr.nsect_addr);
614
615 /* We need to know this for quad device on the MVB */
616 ap->host->private_data = ap;
617}
618
619/**
620 * opt82c465mv_qc_issue_prot - command issue
621 * @qc: command pending
622 *
623 * Called when the libata layer is about to issue a command. We wrap
624 * this interface so that we can load the correct ATA timings. The
625 * MVB has a single set of timing registers and these are shared
626 * across channels. As there are two registers we really ought to
627 * track the last two used values as a sort of register window. For
628 * now we just reload on a channel switch. On the single channel
629 * setup this condition never fires so we do nothing extra.
630 *
631 * FIXME: dual channel needs ->serialize support
632 */
633
634static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
635{
636 struct ata_port *ap = qc->ap;
637 struct ata_device *adev = qc->dev;
638
639 /* If timings are set and for the wrong channel (2nd test is
640 due to a libata shortcoming and will eventually go I hope) */
641 if (ap->host->private_data != ap->host
642 && ap->host->private_data != NULL)
643 opti82c46x_set_piomode(ap, adev);
644
645 return ata_qc_issue_prot(qc);
646}
647
648static struct ata_port_operations opti82c46x_port_ops = {
649 .set_piomode = opti82c46x_set_piomode,
650
651 .port_disable = ata_port_disable,
652 .tf_load = ata_tf_load,
653 .tf_read = ata_tf_read,
654 .check_status = ata_check_status,
655 .exec_command = ata_exec_command,
656 .dev_select = ata_std_dev_select,
657
658 .error_handler = ata_bmdma_error_handler,
659
660 .qc_prep = ata_qc_prep,
661 .qc_issue = opti82c46x_qc_issue_prot,
662 .eng_timeout = ata_eng_timeout,
663 .data_xfer = ata_pio_data_xfer,
664
665 .irq_handler = ata_interrupt,
666 .irq_clear = ata_bmdma_irq_clear,
667
668 .port_start = ata_port_start,
669 .port_stop = ata_port_stop,
670 .host_stop = ata_host_stop
671};
672
673
674/**
675 * legacy_init_one - attach a legacy interface
676 * @port: port number
677 * @io: I/O port start
678 * @ctrl: control port
679 * @irq: interrupt line
680 *
681 * Register an ISA bus IDE interface. Such interfaces are PIO and we
682 * assume do not support IRQ sharing.
683 */
684
685static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq)
686{
687 struct legacy_data *ld = &legacy_data[nr_legacy_host];
688 struct ata_probe_ent ae;
689 struct platform_device *pdev;
690 int ret = -EBUSY;
691 struct ata_port_operations *ops = &legacy_port_ops;
692 int pio_modes = pio_mask;
693 u32 mask = (1 << port);
694
695 if (request_region(io, 8, "pata_legacy") == NULL)
696 return -EBUSY;
697 if (request_region(ctrl, 1, "pata_legacy") == NULL)
698 goto fail_io;
699
700 pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0);
701 if (pdev == NULL)
702 goto fail_dev;
703
704 if (ht6560a & mask) {
705 ops = &ht6560a_port_ops;
706 pio_modes = 0x07;
707 }
708 if (ht6560b & mask) {
709 ops = &ht6560b_port_ops;
710 pio_modes = 0x1F;
711 }
712 if (opti82c611a & mask) {
713 ops = &opti82c611a_port_ops;
714 pio_modes = 0x0F;
715 }
716 if (opti82c46x & mask) {
717 ops = &opti82c46x_port_ops;
718 pio_modes = 0x0F;
719 }
720
721 /* Probe for automatically detectable controllers */
722
723 if (io == 0x1F0 && ops == &legacy_port_ops) {
724 unsigned long flags;
725
726 local_irq_save(flags);
727
728 /* Probes */
729 inb(0x1F5);
730 outb(inb(0x1F2) | 0x80, 0x1F2);
731 inb(0x1F2);
732 inb(0x3F6);
733 inb(0x3F6);
734 inb(0x1F2);
735 inb(0x1F2);
736
737 if ((inb(0x1F2) & 0x80) == 0) {
738 /* PDC20230c or 20630 ? */
739 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n");
740 pio_modes = 0x07;
741 ops = &pdc20230_port_ops;
742 udelay(100);
743 inb(0x1F5);
744 } else {
745 outb(0x55, 0x1F2);
746 inb(0x1F2);
747 inb(0x1F2);
748 if (inb(0x1F2) == 0x00) {
749 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n");
750 }
751 }
752 local_irq_restore(flags);
753 }
754
755
756 /* Chip does mode setting by command snooping */
757 if (ops == &legacy_port_ops && (autospeed & mask))
758 ops = &simple_port_ops;
759 memset(&ae, 0, sizeof(struct ata_probe_ent));
760 INIT_LIST_HEAD(&ae.node);
761 ae.dev = &pdev->dev;
762 ae.port_ops = ops;
763 ae.sht = &legacy_sht;
764 ae.n_ports = 1;
765 ae.pio_mask = pio_modes;
766 ae.irq = irq;
767 ae.irq_flags = 0;
768 ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
769 ae.port[0].cmd_addr = io;
770 ae.port[0].altstatus_addr = ctrl;
771 ae.port[0].ctl_addr = ctrl;
772 ata_std_ports(&ae.port[0]);
773 ae.private_data = ld;
774
775 ret = ata_device_add(&ae);
776 if (ret == 0) {
777 ret = -ENODEV;
778 goto fail;
779 }
780 legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev);
781 ld->platform_dev = pdev;
782 return 0;
783
784fail:
785 platform_device_unregister(pdev);
786fail_dev:
787 release_region(ctrl, 1);
788fail_io:
789 release_region(io, 8);
790 return ret;
791}
792
793/**
794 * legacy_check_special_cases - ATA special cases
795 * @p: PCI device to check
796 * @master: set this if we find an ATA master
797 * @master: set this if we find an ATA secondary
798 *
799 * A small number of vendors implemented early PCI ATA interfaces on bridge logic
800 * without the ATA interface being PCI visible. Where we have a matching PCI driver
801 * we must skip the relevant device here. If we don't know about it then the legacy
802 * driver is the right driver anyway.
803 */
804
805static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary)
806{
807 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
808 if (p->vendor == 0x1078 && p->device == 0x0000) {
809 *primary = *secondary = 1;
810 return;
811 }
812 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
813 if (p->vendor == 0x1078 && p->device == 0x0002) {
814 *primary = *secondary = 1;
815 return;
816 }
817 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
818 if (p->vendor == 0x8086 && p->device == 0x1234) {
819 u16 r;
820 pci_read_config_word(p, 0x6C, &r);
821 if (r & 0x8000) { /* ATA port enabled */
822 if (r & 0x4000)
823 *secondary = 1;
824 else
825 *primary = 1;
826 }
827 return;
828 }
829}
830
831
832/**
833 * legacy_init - attach legacy interfaces
834 *
835 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
836 * Right now we do not scan the ide0 and ide1 address but should do so
837 * for non PCI systems or systems with no PCI IDE legacy mode devices.
838 * If you fix that note there are special cases to consider like VLB
839 * drivers and CS5510/20.
840 */
841
842static __init int legacy_init(void)
843{
844 int i;
845 int ct = 0;
846 int primary = 0;
847 int secondary = 0;
848 int last_port = NR_HOST;
849
850 struct pci_dev *p = NULL;
851
852 for_each_pci_dev(p) {
853 int r;
854 /* Check for any overlap of the system ATA mappings. Native mode controllers
855 stuck on these addresses or some devices in 'raid' mode won't be found by
856 the storage class test */
857 for (r = 0; r < 6; r++) {
858 if (pci_resource_start(p, r) == 0x1f0)
859 primary = 1;
860 if (pci_resource_start(p, r) == 0x170)
861 secondary = 1;
862 }
863 /* Check for special cases */
864 legacy_check_special_cases(p, &primary, &secondary);
865
866 /* If PCI bus is present then don't probe for tertiary legacy ports */
867 if (probe_all == 0)
868 last_port = 2;
869 }
870
871 /* If an OPTI 82C46X is present find out where the channels are */
872 if (opti82c46x) {
873 static const char *optis[4] = {
874 "3/463MV", "5MV",
875 "5MVA", "5MVB"
876 };
877 u8 chans = 1;
878 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
879
880 opti82c46x = 3; /* Assume master and slave first */
881 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
882 if (ctrl == 3)
883 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
884 ctrl = opti_syscfg(0xAC);
885 /* Check enabled and this port is the 465MV port. On the
886 MVB we may have two channels */
887 if (ctrl & 8) {
888 if (ctrl & 4)
889 opti82c46x = 2; /* Slave */
890 else
891 opti82c46x = 1; /* Master */
892 if (chans == 2)
893 opti82c46x = 3; /* Master and Slave */
894 } /* Slave only */
895 else if (chans == 1)
896 opti82c46x = 1;
897 }
898
899 for (i = 0; i < last_port; i++) {
900 /* Skip primary if we have seen a PCI one */
901 if (i == 0 && primary == 1)
902 continue;
903 /* Skip secondary if we have seen a PCI one */
904 if (i == 1 && secondary == 1)
905 continue;
906 if (legacy_init_one(i, legacy_port[i],
907 legacy_port[i] + 0x0206,
908 legacy_irq[i]) == 0)
909 ct++;
910 }
911 if (ct != 0)
912 return 0;
913 return -ENODEV;
914}
915
916static __exit void legacy_exit(void)
917{
918 int i;
919
920 for (i = 0; i < nr_legacy_host; i++) {
921 struct legacy_data *ld = &legacy_data[i];
922 struct ata_port *ap =legacy_host[i]->ports[0];
923 unsigned long io = ap->ioaddr.cmd_addr;
924 unsigned long ctrl = ap->ioaddr.ctl_addr;
925 ata_host_remove(legacy_host[i]);
926 platform_device_unregister(ld->platform_dev);
927 if (ld->timing)
928 release_region(ld->timing, 2);
929 release_region(io, 8);
930 release_region(ctrl, 1);
931 }
932}
933
934MODULE_AUTHOR("Alan Cox");
935MODULE_DESCRIPTION("low-level driver for legacy ATA");
936MODULE_LICENSE("GPL");
937MODULE_VERSION(DRV_VERSION);
938
939module_param(probe_all, int, 0);
940module_param(autospeed, int, 0);
941module_param(ht6560a, int, 0);
942module_param(ht6560b, int, 0);
943module_param(opti82c611a, int, 0);
944module_param(opti82c46x, int, 0);
945module_param(pio_mask, int, 0);
946
947module_init(legacy_init);
948module_exit(legacy_exit);
949
diff --git a/drivers/ata/pata_mpiix.c b/drivers/ata/pata_mpiix.c
new file mode 100644
index 00000000000..1958c4ed09a
--- /dev/null
+++ b/drivers/ata/pata_mpiix.c
@@ -0,0 +1,313 @@
1/*
2 * pata_mpiix.c - Intel MPIIX PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * The MPIIX is different enough to the PIIX4 and friends that we give it
7 * a separate driver. The old ide/pci code handles this by just not tuning
8 * MPIIX at all.
9 *
10 * The MPIIX also differs in another important way from the majority of PIIX
11 * devices. The chip is a bridge (pardon the pun) between the old world of
12 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
13 * IDE controller is not decoded in PCI space and the chip does not claim to
14 * be IDE class PCI. This requires slightly non-standard probe logic compared
15 * with PCI IDE and also that we do not disable the device when our driver is
16 * unloaded (as it has many other functions).
17 *
18 * The driver conciously keeps this logic internally to avoid pushing quirky
19 * PATA history into the clean libata layer.
20 *
21 * Thinkpad specific note: If you boot an MPIIX using thinkpad with a PCMCIA
22 * hard disk present this driver will not detect it. This is not a bug. In this
23 * configuration the secondary port of the MPIIX is disabled and the addresses
24 * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
25 * to operate.
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/init.h>
32#include <linux/blkdev.h>
33#include <linux/delay.h>
34#include <scsi/scsi_host.h>
35#include <linux/libata.h>
36
37#define DRV_NAME "pata_mpiix"
38#define DRV_VERSION "0.7.1"
39
40enum {
41 IDETIM = 0x6C, /* IDE control register */
42 IORDY = (1 << 1),
43 PPE = (1 << 2),
44 FTIM = (1 << 0),
45 ENABLED = (1 << 15),
46 SECONDARY = (1 << 14)
47};
48
49static int mpiix_pre_reset(struct ata_port *ap)
50{
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
52 static const struct pci_bits mpiix_enable_bits[] = {
53 { 0x6D, 1, 0x80, 0x80 },
54 { 0x6F, 1, 0x80, 0x80 }
55 };
56
57 if (!pci_test_config_bits(pdev, &mpiix_enable_bits[ap->port_no])) {
58 ata_port_disable(ap);
59 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
60 return 0;
61 }
62 ap->cbl = ATA_CBL_PATA40;
63 return ata_std_prereset(ap);
64}
65
66/**
67 * mpiix_error_handler - probe reset
68 * @ap: ATA port
69 *
70 * Perform the ATA probe and bus reset sequence plus specific handling
71 * for this hardware. The MPIIX has the enable bits in a different place
72 * to PIIX4 and friends. As a pure PIO device it has no cable detect
73 */
74
75static void mpiix_error_handler(struct ata_port *ap)
76{
77 ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
78}
79
80/**
81 * mpiix_set_piomode - set initial PIO mode data
82 * @ap: ATA interface
83 * @adev: ATA device
84 *
85 * Called to do the PIO mode setup. The MPIIX allows us to program the
86 * IORDY sample point (2-5 clocks), recovery 1-4 clocks and whether
87 * prefetching or iordy are used.
88 *
89 * This would get very ugly because we can only program timing for one
90 * device at a time, the other gets PIO0. Fortunately libata calls
91 * our qc_issue_prot command before a command is issued so we can
92 * flip the timings back and forth to reduce the pain.
93 */
94
95static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
96{
97 int control = 0;
98 int pio = adev->pio_mode - XFER_PIO_0;
99 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
100 u16 idetim;
101 static const /* ISP RTC */
102 u8 timings[][2] = { { 0, 0 },
103 { 0, 0 },
104 { 1, 0 },
105 { 2, 1 },
106 { 2, 3 }, };
107
108 pci_read_config_word(pdev, IDETIM, &idetim);
109 /* Mask the IORDY/TIME/PPE0 bank for this device */
110 if (adev->class == ATA_DEV_ATA)
111 control |= PPE; /* PPE enable for disk */
112 if (ata_pio_need_iordy(adev))
113 control |= IORDY; /* IORDY */
114 if (pio > 0)
115 control |= FTIM; /* This drive is on the fast timing bank */
116
117 /* Mask out timing and clear both TIME bank selects */
118 idetim &= 0xCCEE;
119 idetim &= ~(0x07 << (2 * adev->devno));
120 idetim |= (control << (2 * adev->devno));
121
122 idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
123 pci_write_config_word(pdev, IDETIM, idetim);
124
125 /* We use ap->private_data as a pointer to the device currently
126 loaded for timing */
127 ap->private_data = adev;
128}
129
130/**
131 * mpiix_qc_issue_prot - command issue
132 * @qc: command pending
133 *
134 * Called when the libata layer is about to issue a command. We wrap
135 * this interface so that we can load the correct ATA timings if
136 * neccessary. Our logic also clears TIME0/TIME1 for the other device so
137 * that, even if we get this wrong, cycles to the other device will
138 * be made PIO0.
139 */
140
141static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
142{
143 struct ata_port *ap = qc->ap;
144 struct ata_device *adev = qc->dev;
145
146 /* If modes have been configured and the channel data is not loaded
147 then load it. We have to check if pio_mode is set as the core code
148 does not set adev->pio_mode to XFER_PIO_0 while probing as would be
149 logical */
150
151 if (adev->pio_mode && adev != ap->private_data)
152 mpiix_set_piomode(ap, adev);
153
154 return ata_qc_issue_prot(qc);
155}
156
157static struct scsi_host_template mpiix_sht = {
158 .module = THIS_MODULE,
159 .name = DRV_NAME,
160 .ioctl = ata_scsi_ioctl,
161 .queuecommand = ata_scsi_queuecmd,
162 .can_queue = ATA_DEF_QUEUE,
163 .this_id = ATA_SHT_THIS_ID,
164 .sg_tablesize = LIBATA_MAX_PRD,
165 .max_sectors = ATA_MAX_SECTORS,
166 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
167 .emulated = ATA_SHT_EMULATED,
168 .use_clustering = ATA_SHT_USE_CLUSTERING,
169 .proc_name = DRV_NAME,
170 .dma_boundary = ATA_DMA_BOUNDARY,
171 .slave_configure = ata_scsi_slave_config,
172 .bios_param = ata_std_bios_param,
173};
174
175static struct ata_port_operations mpiix_port_ops = {
176 .port_disable = ata_port_disable,
177 .set_piomode = mpiix_set_piomode,
178
179 .tf_load = ata_tf_load,
180 .tf_read = ata_tf_read,
181 .check_status = ata_check_status,
182 .exec_command = ata_exec_command,
183 .dev_select = ata_std_dev_select,
184
185 .freeze = ata_bmdma_freeze,
186 .thaw = ata_bmdma_thaw,
187 .error_handler = mpiix_error_handler,
188 .post_internal_cmd = ata_bmdma_post_internal_cmd,
189
190 .qc_prep = ata_qc_prep,
191 .qc_issue = mpiix_qc_issue_prot,
192 .data_xfer = ata_pio_data_xfer,
193
194 .irq_handler = ata_interrupt,
195 .irq_clear = ata_bmdma_irq_clear,
196
197 .port_start = ata_port_start,
198 .port_stop = ata_port_stop,
199 .host_stop = ata_host_stop
200};
201
202static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
203{
204 /* Single threaded by the PCI probe logic */
205 static struct ata_probe_ent probe[2];
206 static int printed_version;
207 u16 idetim;
208 int enabled;
209
210 if (!printed_version++)
211 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
212
213 /* MPIIX has many functions which can be turned on or off according
214 to other devices present. Make sure IDE is enabled before we try
215 and use it */
216
217 pci_read_config_word(dev, IDETIM, &idetim);
218 if (!(idetim & ENABLED))
219 return -ENODEV;
220
221 /* We do our own plumbing to avoid leaking special cases for whacko
222 ancient hardware into the core code. There are two issues to
223 worry about. #1 The chip is a bridge so if in legacy mode and
224 without BARs set fools the setup. #2 If you pci_disable_device
225 the MPIIX your box goes castors up */
226
227 INIT_LIST_HEAD(&probe[0].node);
228 probe[0].dev = pci_dev_to_dev(dev);
229 probe[0].port_ops = &mpiix_port_ops;
230 probe[0].sht = &mpiix_sht;
231 probe[0].pio_mask = 0x1F;
232 probe[0].irq = 14;
233 probe[0].irq_flags = SA_SHIRQ;
234 probe[0].port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
235 probe[0].n_ports = 1;
236 probe[0].port[0].cmd_addr = 0x1F0;
237 probe[0].port[0].ctl_addr = 0x3F6;
238 probe[0].port[0].altstatus_addr = 0x3F6;
239
240 /* The secondary lurks at different addresses but is otherwise
241 the same beastie */
242
243 INIT_LIST_HEAD(&probe[1].node);
244 probe[1] = probe[0];
245 probe[1].irq = 15;
246 probe[1].port[0].cmd_addr = 0x170;
247 probe[1].port[0].ctl_addr = 0x376;
248 probe[1].port[0].altstatus_addr = 0x376;
249
250 /* Let libata fill in the port details */
251 ata_std_ports(&probe[0].port[0]);
252 ata_std_ports(&probe[1].port[0]);
253
254 /* Now add the port that is active */
255 enabled = (idetim & SECONDARY) ? 1 : 0;
256
257 if (ata_device_add(&probe[enabled]))
258 return 0;
259 return -ENODEV;
260}
261
262/**
263 * mpiix_remove_one - device unload
264 * @pdev: PCI device being removed
265 *
266 * Handle an unplug/unload event for a PCI device. Unload the
267 * PCI driver but do not use the default handler as we *MUST NOT*
268 * disable the device as it has other functions.
269 */
270
271static void __devexit mpiix_remove_one(struct pci_dev *pdev)
272{
273 struct device *dev = pci_dev_to_dev(pdev);
274 struct ata_host *host = dev_get_drvdata(dev);
275
276 ata_host_remove(host);
277 dev_set_drvdata(dev, NULL);
278}
279
280
281
282static const struct pci_device_id mpiix[] = {
283 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
284 { 0, },
285};
286
287static struct pci_driver mpiix_pci_driver = {
288 .name = DRV_NAME,
289 .id_table = mpiix,
290 .probe = mpiix_init_one,
291 .remove = mpiix_remove_one
292};
293
294static int __init mpiix_init(void)
295{
296 return pci_register_driver(&mpiix_pci_driver);
297}
298
299
300static void __exit mpiix_exit(void)
301{
302 pci_unregister_driver(&mpiix_pci_driver);
303}
304
305
306MODULE_AUTHOR("Alan Cox");
307MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
308MODULE_LICENSE("GPL");
309MODULE_DEVICE_TABLE(pci, mpiix);
310MODULE_VERSION(DRV_VERSION);
311
312module_init(mpiix_init);
313module_exit(mpiix_exit);
diff --git a/drivers/ata/pata_netcell.c b/drivers/ata/pata_netcell.c
new file mode 100644
index 00000000000..e3a85778cd4
--- /dev/null
+++ b/drivers/ata/pata_netcell.c
@@ -0,0 +1,175 @@
1/*
2 * pata_netcell.c - Netcell PATA driver
3 *
4 * (c) 2006 Red Hat <alan@redhat.com>
5 */
6
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/pci.h>
10#include <linux/init.h>
11#include <linux/blkdev.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <scsi/scsi_host.h>
15#include <linux/libata.h>
16#include <linux/ata.h>
17
18#define DRV_NAME "pata_netcell"
19#define DRV_VERSION "0.1.5"
20
21/**
22 * netcell_probe_init - check for 40/80 pin
23 * @ap: Port
24 *
25 * Cables are handled by the RAID controller. Report 80 pin.
26 */
27
28static int netcell_pre_reset(struct ata_port *ap)
29{
30 ap->cbl = ATA_CBL_PATA80;
31 return ata_std_prereset(ap);
32}
33
34/**
35 * netcell_probe_reset - Probe specified port on PATA host controller
36 * @ap: Port to probe
37 *
38 * LOCKING:
39 * None (inherited from caller).
40 */
41
42static void netcell_error_handler(struct ata_port *ap)
43{
44 return ata_bmdma_drive_eh(ap, netcell_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
45}
46
47/* No PIO or DMA methods needed for this device */
48
49static struct scsi_host_template netcell_sht = {
50 .module = THIS_MODULE,
51 .name = DRV_NAME,
52 .ioctl = ata_scsi_ioctl,
53 .queuecommand = ata_scsi_queuecmd,
54 .can_queue = ATA_DEF_QUEUE,
55 .this_id = ATA_SHT_THIS_ID,
56 .sg_tablesize = LIBATA_MAX_PRD,
57 /* Special handling needed if you have sector or LBA48 limits */
58 .max_sectors = ATA_MAX_SECTORS,
59 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
60 .emulated = ATA_SHT_EMULATED,
61 .use_clustering = ATA_SHT_USE_CLUSTERING,
62 .proc_name = DRV_NAME,
63 .dma_boundary = ATA_DMA_BOUNDARY,
64 .slave_configure = ata_scsi_slave_config,
65 /* Use standard CHS mapping rules */
66 .bios_param = ata_std_bios_param,
67};
68
69static const struct ata_port_operations netcell_ops = {
70 .port_disable = ata_port_disable,
71
72 /* Task file is PCI ATA format, use helpers */
73 .tf_load = ata_tf_load,
74 .tf_read = ata_tf_read,
75 .check_status = ata_check_status,
76 .exec_command = ata_exec_command,
77 .dev_select = ata_std_dev_select,
78
79 .freeze = ata_bmdma_freeze,
80 .thaw = ata_bmdma_thaw,
81 .error_handler = netcell_error_handler,
82 .post_internal_cmd = ata_bmdma_post_internal_cmd,
83
84 /* BMDMA handling is PCI ATA format, use helpers */
85 .bmdma_setup = ata_bmdma_setup,
86 .bmdma_start = ata_bmdma_start,
87 .bmdma_stop = ata_bmdma_stop,
88 .bmdma_status = ata_bmdma_status,
89 .qc_prep = ata_qc_prep,
90 .qc_issue = ata_qc_issue_prot,
91 .data_xfer = ata_pio_data_xfer,
92
93 /* Timeout handling. Special recovery hooks here */
94 .eng_timeout = ata_eng_timeout,
95 .irq_handler = ata_interrupt,
96 .irq_clear = ata_bmdma_irq_clear,
97
98 /* Generic PATA PCI ATA helpers */
99 .port_start = ata_port_start,
100 .port_stop = ata_port_stop,
101 .host_stop = ata_host_stop,
102};
103
104
105/**
106 * netcell_init_one - Register Netcell ATA PCI device with kernel services
107 * @pdev: PCI device to register
108 * @ent: Entry in netcell_pci_tbl matching with @pdev
109 *
110 * Called from kernel PCI layer.
111 *
112 * LOCKING:
113 * Inherited from PCI layer (may sleep).
114 *
115 * RETURNS:
116 * Zero on success, or -ERRNO value.
117 */
118
119static int netcell_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
120{
121 static int printed_version;
122 static struct ata_port_info info = {
123 .sht = &netcell_sht,
124 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
125 /* Actually we don't really care about these as the
126 firmware deals with it */
127 .pio_mask = 0x1f, /* pio0-4 */
128 .mwdma_mask = 0x07, /* mwdma0-2 */
129 .udma_mask = 0x3f, /* UDMA 133 */
130 .port_ops = &netcell_ops,
131 };
132 static struct ata_port_info *port_info[2] = { &info, &info };
133
134 if (!printed_version++)
135 dev_printk(KERN_DEBUG, &pdev->dev,
136 "version " DRV_VERSION "\n");
137
138 /* Any chip specific setup/optimisation/messages here */
139 ata_pci_clear_simplex(pdev);
140
141 /* And let the library code do the work */
142 return ata_pci_init_one(pdev, port_info, 2);
143}
144
145static const struct pci_device_id netcell_pci_tbl[] = {
146 { PCI_DEVICE(PCI_VENDOR_ID_NETCELL, PCI_DEVICE_ID_REVOLUTION), },
147 { } /* terminate list */
148};
149
150static struct pci_driver netcell_pci_driver = {
151 .name = DRV_NAME,
152 .id_table = netcell_pci_tbl,
153 .probe = netcell_init_one,
154 .remove = ata_pci_remove_one,
155};
156
157static int __init netcell_init(void)
158{
159 return pci_register_driver(&netcell_pci_driver);
160}
161
162static void __exit netcell_exit(void)
163{
164 pci_unregister_driver(&netcell_pci_driver);
165}
166
167module_init(netcell_init);
168module_exit(netcell_exit);
169
170MODULE_AUTHOR("Alan Cox");
171MODULE_DESCRIPTION("SCSI low-level driver for Netcell PATA RAID");
172MODULE_LICENSE("GPL");
173MODULE_DEVICE_TABLE(pci, netcell_pci_tbl);
174MODULE_VERSION(DRV_VERSION);
175
diff --git a/drivers/ata/pata_ns87410.c b/drivers/ata/pata_ns87410.c
new file mode 100644
index 00000000000..93d6646d295
--- /dev/null
+++ b/drivers/ata/pata_ns87410.c
@@ -0,0 +1,236 @@
1/*
2 * pata_ns87410.c - National Semiconductor 87410 PATA for new ATA layer
3 * (C) 2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/blkdev.h>
26#include <linux/delay.h>
27#include <scsi/scsi_host.h>
28#include <linux/libata.h>
29
30#define DRV_NAME "pata_ns87410"
31#define DRV_VERSION "0.4.2"
32
33/**
34 * ns87410_pre_reset - probe begin
35 * @ap: ATA port
36 *
37 * Set up cable type and use generic probe init
38 */
39
40static int ns87410_pre_reset(struct ata_port *ap)
41{
42 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
43 static const struct pci_bits ns87410_enable_bits[] = {
44 { 0x43, 1, 0x08, 0x08 },
45 { 0x47, 1, 0x08, 0x08 }
46 };
47
48 if (!pci_test_config_bits(pdev, &ns87410_enable_bits[ap->port_no])) {
49 ata_port_disable(ap);
50 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
51 return 0;
52 }
53 ap->cbl = ATA_CBL_PATA40;
54 return ata_std_prereset(ap);
55}
56
57/**
58 * ns87410_error_handler - probe reset
59 * @ap: ATA port
60 *
61 * Perform the ATA probe and bus reset sequence plus specific handling
62 * for this hardware. The MPIIX has the enable bits in a different place
63 * to PIIX4 and friends. As a pure PIO device it has no cable detect
64 */
65
66static void ns87410_error_handler(struct ata_port *ap)
67{
68 ata_bmdma_drive_eh(ap, ns87410_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
69}
70
71/**
72 * ns87410_set_piomode - set initial PIO mode data
73 * @ap: ATA interface
74 * @adev: ATA device
75 *
76 * Program timing data. This is kept per channel not per device,
77 * and only affects the data port.
78 */
79
80static void ns87410_set_piomode(struct ata_port *ap, struct ata_device *adev)
81{
82 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
83 int port = 0x40 + 4 * ap->port_no;
84 u8 idetcr, idefr;
85 struct ata_timing at;
86
87 static const u8 activebits[15] = {
88 0, 1, 2, 3, 4,
89 5, 5, 6, 6, 6,
90 6, 7, 7, 7, 7
91 };
92
93 static const u8 recoverbits[12] = {
94 0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 7, 7
95 };
96
97 pci_read_config_byte(pdev, port + 3, &idefr);
98
99 if (ata_pio_need_iordy(adev))
100 idefr |= 0x04; /* IORDY enable */
101 else
102 idefr &= ~0x04;
103
104 if (ata_timing_compute(adev, adev->pio_mode, &at, 30303, 1) < 0) {
105 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", adev->pio_mode);
106 return;
107 }
108
109 at.active = FIT(at.active, 2, 16) - 2;
110 at.setup = FIT(at.setup, 1, 4) - 1;
111 at.recover = FIT(at.recover, 1, 12) - 1;
112
113 idetcr = (at.setup << 6) | (recoverbits[at.recover] << 3) | activebits[at.active];
114
115 pci_write_config_byte(pdev, port, idetcr);
116 pci_write_config_byte(pdev, port + 3, idefr);
117 /* We use ap->private_data as a pointer to the device currently
118 loaded for timing */
119 ap->private_data = adev;
120}
121
122/**
123 * ns87410_qc_issue_prot - command issue
124 * @qc: command pending
125 *
126 * Called when the libata layer is about to issue a command. We wrap
127 * this interface so that we can load the correct ATA timings if
128 * neccessary.
129 */
130
131static unsigned int ns87410_qc_issue_prot(struct ata_queued_cmd *qc)
132{
133 struct ata_port *ap = qc->ap;
134 struct ata_device *adev = qc->dev;
135
136 /* If modes have been configured and the channel data is not loaded
137 then load it. We have to check if pio_mode is set as the core code
138 does not set adev->pio_mode to XFER_PIO_0 while probing as would be
139 logical */
140
141 if (adev->pio_mode && adev != ap->private_data)
142 ns87410_set_piomode(ap, adev);
143
144 return ata_qc_issue_prot(qc);
145}
146
147static struct scsi_host_template ns87410_sht = {
148 .module = THIS_MODULE,
149 .name = DRV_NAME,
150 .ioctl = ata_scsi_ioctl,
151 .queuecommand = ata_scsi_queuecmd,
152 .can_queue = ATA_DEF_QUEUE,
153 .this_id = ATA_SHT_THIS_ID,
154 .sg_tablesize = LIBATA_MAX_PRD,
155 .max_sectors = ATA_MAX_SECTORS,
156 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
157 .emulated = ATA_SHT_EMULATED,
158 .use_clustering = ATA_SHT_USE_CLUSTERING,
159 .proc_name = DRV_NAME,
160 .dma_boundary = ATA_DMA_BOUNDARY,
161 .slave_configure = ata_scsi_slave_config,
162 .bios_param = ata_std_bios_param,
163};
164
165static struct ata_port_operations ns87410_port_ops = {
166 .port_disable = ata_port_disable,
167 .set_piomode = ns87410_set_piomode,
168
169 .tf_load = ata_tf_load,
170 .tf_read = ata_tf_read,
171 .check_status = ata_check_status,
172 .exec_command = ata_exec_command,
173 .dev_select = ata_std_dev_select,
174
175 .freeze = ata_bmdma_freeze,
176 .thaw = ata_bmdma_thaw,
177 .error_handler = ns87410_error_handler,
178 .post_internal_cmd = ata_bmdma_post_internal_cmd,
179
180 .qc_prep = ata_qc_prep,
181 .qc_issue = ns87410_qc_issue_prot,
182 .eng_timeout = ata_eng_timeout,
183 .data_xfer = ata_pio_data_xfer,
184
185 .irq_handler = ata_interrupt,
186 .irq_clear = ata_bmdma_irq_clear,
187
188 .port_start = ata_port_start,
189 .port_stop = ata_port_stop,
190 .host_stop = ata_host_stop
191};
192
193static int ns87410_init_one(struct pci_dev *dev, const struct pci_device_id *id)
194{
195 static struct ata_port_info info = {
196 .sht = &ns87410_sht,
197 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
198 .pio_mask = 0x0F,
199 .port_ops = &ns87410_port_ops
200 };
201 static struct ata_port_info *port_info[2] = {&info, &info};
202 return ata_pci_init_one(dev, port_info, 2);
203}
204
205static const struct pci_device_id ns87410[] = {
206 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410), },
207 { 0, },
208};
209
210static struct pci_driver ns87410_pci_driver = {
211 .name = DRV_NAME,
212 .id_table = ns87410,
213 .probe = ns87410_init_one,
214 .remove = ata_pci_remove_one
215};
216
217static int __init ns87410_init(void)
218{
219 return pci_register_driver(&ns87410_pci_driver);
220}
221
222
223static void __exit ns87410_exit(void)
224{
225 pci_unregister_driver(&ns87410_pci_driver);
226}
227
228
229MODULE_AUTHOR("Alan Cox");
230MODULE_DESCRIPTION("low-level driver for Nat Semi 87410");
231MODULE_LICENSE("GPL");
232MODULE_DEVICE_TABLE(pci, ns87410);
233MODULE_VERSION(DRV_VERSION);
234
235module_init(ns87410_init);
236module_exit(ns87410_exit);
diff --git a/drivers/ata/pata_oldpiix.c b/drivers/ata/pata_oldpiix.c
new file mode 100644
index 00000000000..04c618a2664
--- /dev/null
+++ b/drivers/ata/pata_oldpiix.c
@@ -0,0 +1,339 @@
1/*
2 * pata_oldpiix.c - Intel PATA/SATA controllers
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
7 *
8 * Early PIIX differs significantly from the later PIIX as it lacks
9 * SITRE and the slave timing registers. This means that you have to
10 * set timing per channel, or be clever. Libata tells us whenever it
11 * does drive selection and we use this to reload the timings.
12 *
13 * Because of these behaviour differences PIIX gets its own driver module.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/blkdev.h>
21#include <linux/delay.h>
22#include <linux/device.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25#include <linux/ata.h>
26
27#define DRV_NAME "pata_oldpiix"
28#define DRV_VERSION "0.5.1"
29
30/**
31 * oldpiix_pre_reset - probe begin
32 * @ap: ATA port
33 *
34 * Set up cable type and use generic probe init
35 */
36
37static int oldpiix_pre_reset(struct ata_port *ap)
38{
39 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
40 static const struct pci_bits oldpiix_enable_bits[] = {
41 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
42 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
43 };
44
45 if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no])) {
46 ata_port_disable(ap);
47 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
48 return 0;
49 }
50 ap->cbl = ATA_CBL_PATA40;
51 return ata_std_prereset(ap);
52}
53
54/**
55 * oldpiix_pata_error_handler - Probe specified port on PATA host controller
56 * @ap: Port to probe
57 * @classes:
58 *
59 * LOCKING:
60 * None (inherited from caller).
61 */
62
63static void oldpiix_pata_error_handler(struct ata_port *ap)
64{
65 ata_bmdma_drive_eh(ap, oldpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
66}
67
68/**
69 * oldpiix_set_piomode - Initialize host controller PATA PIO timings
70 * @ap: Port whose timings we are configuring
71 * @adev: um
72 *
73 * Set PIO mode for device, in host controller PCI config space.
74 *
75 * LOCKING:
76 * None (inherited from caller).
77 */
78
79static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
80{
81 unsigned int pio = adev->pio_mode - XFER_PIO_0;
82 struct pci_dev *dev = to_pci_dev(ap->host->dev);
83 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
84 u16 idetm_data;
85 int control = 0;
86
87 /*
88 * See Intel Document 298600-004 for the timing programing rules
89 * for PIIX/ICH. Note that the early PIIX does not have the slave
90 * timing port at 0x44.
91 */
92
93 static const /* ISP RTC */
94 u8 timings[][2] = { { 0, 0 },
95 { 0, 0 },
96 { 1, 0 },
97 { 2, 1 },
98 { 2, 3 }, };
99
100 if (pio > 2)
101 control |= 1; /* TIME1 enable */
102 if (ata_pio_need_iordy(adev))
103 control |= 2; /* IE IORDY */
104
105 /* Intel specifies that the PPE functionality is for disk only */
106 if (adev->class == ATA_DEV_ATA)
107 control |= 4; /* PPE enable */
108
109 pci_read_config_word(dev, idetm_port, &idetm_data);
110
111 /* Enable PPE, IE and TIME as appropriate. Clear the other
112 drive timing bits */
113 if (adev->devno == 0) {
114 idetm_data &= 0xCCE0;
115 idetm_data |= control;
116 } else {
117 idetm_data &= 0xCC0E;
118 idetm_data |= (control << 4);
119 }
120 idetm_data |= (timings[pio][0] << 12) |
121 (timings[pio][1] << 8);
122 pci_write_config_word(dev, idetm_port, idetm_data);
123
124 /* Track which port is configured */
125 ap->private_data = adev;
126}
127
128/**
129 * oldpiix_set_dmamode - Initialize host controller PATA DMA timings
130 * @ap: Port whose timings we are configuring
131 * @adev: Device to program
132 * @isich: True if the device is an ICH and has IOCFG registers
133 *
134 * Set MWDMA mode for device, in host controller PCI config space.
135 *
136 * LOCKING:
137 * None (inherited from caller).
138 */
139
140static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
141{
142 struct pci_dev *dev = to_pci_dev(ap->host->dev);
143 u8 idetm_port = ap->port_no ? 0x42 : 0x40;
144 u16 idetm_data;
145
146 static const /* ISP RTC */
147 u8 timings[][2] = { { 0, 0 },
148 { 0, 0 },
149 { 1, 0 },
150 { 2, 1 },
151 { 2, 3 }, };
152
153 /*
154 * MWDMA is driven by the PIO timings. We must also enable
155 * IORDY unconditionally along with TIME1. PPE has already
156 * been set when the PIO timing was set.
157 */
158
159 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
160 unsigned int control;
161 const unsigned int needed_pio[3] = {
162 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
163 };
164 int pio = needed_pio[mwdma] - XFER_PIO_0;
165
166 pci_read_config_word(dev, idetm_port, &idetm_data);
167
168 control = 3; /* IORDY|TIME0 */
169 /* Intel specifies that the PPE functionality is for disk only */
170 if (adev->class == ATA_DEV_ATA)
171 control |= 4; /* PPE enable */
172
173 /* If the drive MWDMA is faster than it can do PIO then
174 we must force PIO into PIO0 */
175
176 if (adev->pio_mode < needed_pio[mwdma])
177 /* Enable DMA timing only */
178 control |= 8; /* PIO cycles in PIO0 */
179
180 /* Mask out the relevant control and timing bits we will load. Also
181 clear the other drive TIME register as a precaution */
182 if (adev->devno == 0) {
183 idetm_data &= 0xCCE0;
184 idetm_data |= control;
185 } else {
186 idetm_data &= 0xCC0E;
187 idetm_data |= (control << 4);
188 }
189 idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
190 pci_write_config_word(dev, idetm_port, idetm_data);
191
192 /* Track which port is configured */
193 ap->private_data = adev;
194}
195
196/**
197 * oldpiix_qc_issue_prot - command issue
198 * @qc: command pending
199 *
200 * Called when the libata layer is about to issue a command. We wrap
201 * this interface so that we can load the correct ATA timings if
202 * neccessary. Our logic also clears TIME0/TIME1 for the other device so
203 * that, even if we get this wrong, cycles to the other device will
204 * be made PIO0.
205 */
206
207static unsigned int oldpiix_qc_issue_prot(struct ata_queued_cmd *qc)
208{
209 struct ata_port *ap = qc->ap;
210 struct ata_device *adev = qc->dev;
211
212 if (adev != ap->private_data) {
213 if (adev->dma_mode)
214 oldpiix_set_dmamode(ap, adev);
215 else if (adev->pio_mode)
216 oldpiix_set_piomode(ap, adev);
217 }
218 return ata_qc_issue_prot(qc);
219}
220
221
222static struct scsi_host_template oldpiix_sht = {
223 .module = THIS_MODULE,
224 .name = DRV_NAME,
225 .ioctl = ata_scsi_ioctl,
226 .queuecommand = ata_scsi_queuecmd,
227 .can_queue = ATA_DEF_QUEUE,
228 .this_id = ATA_SHT_THIS_ID,
229 .sg_tablesize = LIBATA_MAX_PRD,
230 .max_sectors = ATA_MAX_SECTORS,
231 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
232 .emulated = ATA_SHT_EMULATED,
233 .use_clustering = ATA_SHT_USE_CLUSTERING,
234 .proc_name = DRV_NAME,
235 .dma_boundary = ATA_DMA_BOUNDARY,
236 .slave_configure = ata_scsi_slave_config,
237 .bios_param = ata_std_bios_param,
238};
239
240static const struct ata_port_operations oldpiix_pata_ops = {
241 .port_disable = ata_port_disable,
242 .set_piomode = oldpiix_set_piomode,
243 .set_dmamode = oldpiix_set_dmamode,
244 .mode_filter = ata_pci_default_filter,
245
246 .tf_load = ata_tf_load,
247 .tf_read = ata_tf_read,
248 .check_status = ata_check_status,
249 .exec_command = ata_exec_command,
250 .dev_select = ata_std_dev_select,
251
252 .freeze = ata_bmdma_freeze,
253 .thaw = ata_bmdma_thaw,
254 .error_handler = oldpiix_pata_error_handler,
255 .post_internal_cmd = ata_bmdma_post_internal_cmd,
256
257 .bmdma_setup = ata_bmdma_setup,
258 .bmdma_start = ata_bmdma_start,
259 .bmdma_stop = ata_bmdma_stop,
260 .bmdma_status = ata_bmdma_status,
261 .qc_prep = ata_qc_prep,
262 .qc_issue = oldpiix_qc_issue_prot,
263 .data_xfer = ata_pio_data_xfer,
264
265 .irq_handler = ata_interrupt,
266 .irq_clear = ata_bmdma_irq_clear,
267
268 .port_start = ata_port_start,
269 .port_stop = ata_port_stop,
270 .host_stop = ata_host_stop,
271};
272
273
274/**
275 * oldpiix_init_one - Register PIIX ATA PCI device with kernel services
276 * @pdev: PCI device to register
277 * @ent: Entry in oldpiix_pci_tbl matching with @pdev
278 *
279 * Called from kernel PCI layer. We probe for combined mode (sigh),
280 * and then hand over control to libata, for it to do the rest.
281 *
282 * LOCKING:
283 * Inherited from PCI layer (may sleep).
284 *
285 * RETURNS:
286 * Zero on success, or -ERRNO value.
287 */
288
289static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
290{
291 static int printed_version;
292 static struct ata_port_info info = {
293 .sht = &oldpiix_sht,
294 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
295 .pio_mask = 0x1f, /* pio0-4 */
296 .mwdma_mask = 0x07, /* mwdma1-2 */
297 .port_ops = &oldpiix_pata_ops,
298 };
299 static struct ata_port_info *port_info[2] = { &info, &info };
300
301 if (!printed_version++)
302 dev_printk(KERN_DEBUG, &pdev->dev,
303 "version " DRV_VERSION "\n");
304
305 return ata_pci_init_one(pdev, port_info, 2);
306}
307
308static const struct pci_device_id oldpiix_pci_tbl[] = {
309 { PCI_DEVICE(0x8086, 0x1230), },
310 { } /* terminate list */
311};
312
313static struct pci_driver oldpiix_pci_driver = {
314 .name = DRV_NAME,
315 .id_table = oldpiix_pci_tbl,
316 .probe = oldpiix_init_one,
317 .remove = ata_pci_remove_one,
318};
319
320static int __init oldpiix_init(void)
321{
322 return pci_register_driver(&oldpiix_pci_driver);
323}
324
325static void __exit oldpiix_exit(void)
326{
327 pci_unregister_driver(&oldpiix_pci_driver);
328}
329
330
331module_init(oldpiix_init);
332module_exit(oldpiix_exit);
333
334MODULE_AUTHOR("Alan Cox");
335MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
336MODULE_LICENSE("GPL");
337MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
338MODULE_VERSION(DRV_VERSION);
339
diff --git a/drivers/ata/pata_opti.c b/drivers/ata/pata_opti.c
new file mode 100644
index 00000000000..c3d01325e0e
--- /dev/null
+++ b/drivers/ata/pata_opti.c
@@ -0,0 +1,292 @@
1/*
2 * pata_opti.c - ATI PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on
7 * linux/drivers/ide/pci/opti621.c Version 0.7 Sept 10, 2002
8 *
9 * Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
10 *
11 * Authors:
12 * Jaromir Koutek <miri@punknet.cz>,
13 * Jan Harkes <jaharkes@cwi.nl>,
14 * Mark Lord <mlord@pobox.com>
15 * Some parts of code are from ali14xx.c and from rz1000.c.
16 *
17 * Also consulted the FreeBSD prototype driver by Kevin Day to try
18 * and resolve some confusions. Further documentation can be found in
19 * Ralf Brown's interrupt list
20 *
21 * If you have other variants of the Opti range (Viper/Vendetta) please
22 * try this driver with those PCI idents and report back. For the later
23 * chips see the pata_optidma driver
24 *
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/delay.h>
33#include <scsi/scsi_host.h>
34#include <linux/libata.h>
35
36#define DRV_NAME "pata_opti"
37#define DRV_VERSION "0.2.4"
38
39enum {
40 READ_REG = 0, /* index of Read cycle timing register */
41 WRITE_REG = 1, /* index of Write cycle timing register */
42 CNTRL_REG = 3, /* index of Control register */
43 STRAP_REG = 5, /* index of Strap register */
44 MISC_REG = 6 /* index of Miscellaneous register */
45};
46
47/**
48 * opti_pre_reset - probe begin
49 * @ap: ATA port
50 *
51 * Set up cable type and use generic probe init
52 */
53
54static int opti_pre_reset(struct ata_port *ap)
55{
56 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
57 static const struct pci_bits opti_enable_bits[] = {
58 { 0x45, 1, 0x80, 0x00 },
59 { 0x40, 1, 0x08, 0x00 }
60 };
61
62 if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no])) {
63 ata_port_disable(ap);
64 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
65 return 0;
66 }
67 ap->cbl = ATA_CBL_PATA40;
68 return ata_std_prereset(ap);
69}
70
71/**
72 * opti_probe_reset - probe reset
73 * @ap: ATA port
74 *
75 * Perform the ATA probe and bus reset sequence plus specific handling
76 * for this hardware. The Opti needs little handling - we have no UDMA66
77 * capability that needs cable detection. All we must do is check the port
78 * is enabled.
79 */
80
81static void opti_error_handler(struct ata_port *ap)
82{
83 ata_bmdma_drive_eh(ap, opti_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
84}
85
86/**
87 * opti_write_reg - control register setup
88 * @ap: ATA port
89 * @value: value
90 * @reg: control register number
91 *
92 * The Opti uses magic 'trapdoor' register accesses to do configuration
93 * rather than using PCI space as other controllers do. The double inw
94 * on the error register activates configuration mode. We can then write
95 * the control register
96 */
97
98static void opti_write_reg(struct ata_port *ap, u8 val, int reg)
99{
100 unsigned long regio = ap->ioaddr.cmd_addr;
101
102 /* These 3 unlock the control register access */
103 inw(regio + 1);
104 inw(regio + 1);
105 outb(3, regio + 2);
106
107 /* Do the I/O */
108 outb(val, regio + reg);
109
110 /* Relock */
111 outb(0x83, regio + 2);
112}
113
114#if 0
115/**
116 * opti_read_reg - control register read
117 * @ap: ATA port
118 * @reg: control register number
119 *
120 * The Opti uses magic 'trapdoor' register accesses to do configuration
121 * rather than using PCI space as other controllers do. The double inw
122 * on the error register activates configuration mode. We can then read
123 * the control register
124 */
125
126static u8 opti_read_reg(struct ata_port *ap, int reg)
127{
128 unsigned long regio = ap->ioaddr.cmd_addr;
129 u8 ret;
130 inw(regio + 1);
131 inw(regio + 1);
132 outb(3, regio + 2);
133 ret = inb(regio + reg);
134 outb(0x83, regio + 2);
135}
136#endif
137
138/**
139 * opti_set_piomode - set initial PIO mode data
140 * @ap: ATA interface
141 * @adev: ATA device
142 *
143 * Called to do the PIO mode setup. Timing numbers are taken from
144 * the FreeBSD driver then pre computed to keep the code clean. There
145 * are two tables depending on the hardware clock speed.
146 */
147
148static void opti_set_piomode(struct ata_port *ap, struct ata_device *adev)
149{
150 struct ata_device *pair = ata_dev_pair(adev);
151 int clock;
152 int pio = adev->pio_mode - XFER_PIO_0;
153 unsigned long regio = ap->ioaddr.cmd_addr;
154 u8 addr;
155
156 /* Address table precomputed with prefetch off and a DCLK of 2 */
157 static const u8 addr_timing[2][5] = {
158 { 0x30, 0x20, 0x20, 0x10, 0x10 },
159 { 0x20, 0x20, 0x10, 0x10, 0x10 }
160 };
161 static const u8 data_rec_timing[2][5] = {
162 { 0x6B, 0x56, 0x42, 0x32, 0x31 },
163 { 0x58, 0x44, 0x32, 0x22, 0x21 }
164 };
165
166 outb(0xff, regio + 5);
167 clock = inw(regio + 5) & 1;
168
169 /*
170 * As with many controllers the address setup time is shared
171 * and must suit both devices if present.
172 */
173
174 addr = addr_timing[clock][pio];
175 if (pair) {
176 /* Hardware constraint */
177 u8 pair_addr = addr_timing[clock][pair->pio_mode - XFER_PIO_0];
178 if (pair_addr > addr)
179 addr = pair_addr;
180 }
181
182 /* Commence primary programming sequence */
183 opti_write_reg(ap, adev->devno, MISC_REG);
184 opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG);
185 opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG);
186 opti_write_reg(ap, addr, MISC_REG);
187
188 /* Programming sequence complete, override strapping */
189 opti_write_reg(ap, 0x85, CNTRL_REG);
190}
191
192static struct scsi_host_template opti_sht = {
193 .module = THIS_MODULE,
194 .name = DRV_NAME,
195 .ioctl = ata_scsi_ioctl,
196 .queuecommand = ata_scsi_queuecmd,
197 .can_queue = ATA_DEF_QUEUE,
198 .this_id = ATA_SHT_THIS_ID,
199 .sg_tablesize = LIBATA_MAX_PRD,
200 .max_sectors = ATA_MAX_SECTORS,
201 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
202 .emulated = ATA_SHT_EMULATED,
203 .use_clustering = ATA_SHT_USE_CLUSTERING,
204 .proc_name = DRV_NAME,
205 .dma_boundary = ATA_DMA_BOUNDARY,
206 .slave_configure = ata_scsi_slave_config,
207 .bios_param = ata_std_bios_param,
208};
209
210static struct ata_port_operations opti_port_ops = {
211 .port_disable = ata_port_disable,
212 .set_piomode = opti_set_piomode,
213/* .set_dmamode = opti_set_dmamode, */
214 .tf_load = ata_tf_load,
215 .tf_read = ata_tf_read,
216 .check_status = ata_check_status,
217 .exec_command = ata_exec_command,
218 .dev_select = ata_std_dev_select,
219
220 .freeze = ata_bmdma_freeze,
221 .thaw = ata_bmdma_thaw,
222 .error_handler = opti_error_handler,
223 .post_internal_cmd = ata_bmdma_post_internal_cmd,
224
225 .bmdma_setup = ata_bmdma_setup,
226 .bmdma_start = ata_bmdma_start,
227 .bmdma_stop = ata_bmdma_stop,
228 .bmdma_status = ata_bmdma_status,
229
230 .qc_prep = ata_qc_prep,
231 .qc_issue = ata_qc_issue_prot,
232 .eng_timeout = ata_eng_timeout,
233 .data_xfer = ata_pio_data_xfer,
234
235 .irq_handler = ata_interrupt,
236 .irq_clear = ata_bmdma_irq_clear,
237
238 .port_start = ata_port_start,
239 .port_stop = ata_port_stop,
240 .host_stop = ata_host_stop
241};
242
243static int opti_init_one(struct pci_dev *dev, const struct pci_device_id *id)
244{
245 static struct ata_port_info info = {
246 .sht = &opti_sht,
247 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
248 .pio_mask = 0x1f,
249 .port_ops = &opti_port_ops
250 };
251 static struct ata_port_info *port_info[2] = { &info, &info };
252 static int printed_version;
253
254 if (!printed_version++)
255 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
256
257 return ata_pci_init_one(dev, port_info, 2);
258}
259
260static const struct pci_device_id opti[] = {
261 { PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
262 { PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
263 { 0, },
264};
265
266static struct pci_driver opti_pci_driver = {
267 .name = DRV_NAME,
268 .id_table = opti,
269 .probe = opti_init_one,
270 .remove = ata_pci_remove_one
271};
272
273static int __init opti_init(void)
274{
275 return pci_register_driver(&opti_pci_driver);
276}
277
278
279static void __exit opti_exit(void)
280{
281 pci_unregister_driver(&opti_pci_driver);
282}
283
284
285MODULE_AUTHOR("Alan Cox");
286MODULE_DESCRIPTION("low-level driver for Opti 621/621X");
287MODULE_LICENSE("GPL");
288MODULE_DEVICE_TABLE(pci, opti);
289MODULE_VERSION(DRV_VERSION);
290
291module_init(opti_init);
292module_exit(opti_exit);
diff --git a/drivers/ata/pata_optidma.c b/drivers/ata/pata_optidma.c
new file mode 100644
index 00000000000..800aea7b944
--- /dev/null
+++ b/drivers/ata/pata_optidma.c
@@ -0,0 +1,547 @@
1/*
2 * pata_optidma.c - Opti DMA PATA for new ATA layer
3 * (C) 2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * The Opti DMA controllers are related to the older PIO PCI controllers
7 * and indeed the VLB ones. The main differences are that the timing
8 * numbers are now based off PCI clocks not VLB and differ, and that
9 * MWDMA is supported.
10 *
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
12 *
13 * These devices support virtual DMA for read (aka the CS5520). Later
14 * chips support UDMA33, but only if the rest of the board logic does,
15 * so you have to get this right. We don't support the virtual DMA
16 * but we do handle UDMA.
17 *
18 * Bits that are worth knowing
19 * Most control registers are shadowed into I/O registers
20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10
22 * UDMA requires a 66MHz FSB
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34
35#define DRV_NAME "pata_optidma"
36#define DRV_VERSION "0.2.1"
37
38enum {
39 READ_REG = 0, /* index of Read cycle timing register */
40 WRITE_REG = 1, /* index of Write cycle timing register */
41 CNTRL_REG = 3, /* index of Control register */
42 STRAP_REG = 5, /* index of Strap register */
43 MISC_REG = 6 /* index of Miscellaneous register */
44};
45
46static int pci_clock; /* 0 = 33 1 = 25 */
47
48/**
49 * optidma_pre_reset - probe begin
50 * @ap: ATA port
51 *
52 * Set up cable type and use generic probe init
53 */
54
55static int optidma_pre_reset(struct ata_port *ap)
56{
57 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
58 static const struct pci_bits optidma_enable_bits = {
59 0x40, 1, 0x08, 0x00
60 };
61
62 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) {
63 ata_port_disable(ap);
64 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
65 return 0;
66 }
67 ap->cbl = ATA_CBL_PATA40;
68 return ata_std_prereset(ap);
69}
70
71/**
72 * optidma_probe_reset - probe reset
73 * @ap: ATA port
74 *
75 * Perform the ATA probe and bus reset sequence plus specific handling
76 * for this hardware. The Opti needs little handling - we have no UDMA66
77 * capability that needs cable detection. All we must do is check the port
78 * is enabled.
79 */
80
81static void optidma_error_handler(struct ata_port *ap)
82{
83 ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
84}
85
86/**
87 * optidma_unlock - unlock control registers
88 * @ap: ATA port
89 *
90 * Unlock the control register block for this adapter. Registers must not
91 * be unlocked in a situation where libata might look at them.
92 */
93
94static void optidma_unlock(struct ata_port *ap)
95{
96 unsigned long regio = ap->ioaddr.cmd_addr;
97
98 /* These 3 unlock the control register access */
99 inw(regio + 1);
100 inw(regio + 1);
101 outb(3, regio + 2);
102}
103
104/**
105 * optidma_lock - issue temporary relock
106 * @ap: ATA port
107 *
108 * Re-lock the configuration register settings.
109 */
110
111static void optidma_lock(struct ata_port *ap)
112{
113 unsigned long regio = ap->ioaddr.cmd_addr;
114
115 /* Relock */
116 outb(0x83, regio + 2);
117}
118
119/**
120 * optidma_set_mode - set mode data
121 * @ap: ATA interface
122 * @adev: ATA device
123 * @mode: Mode to set
124 *
125 * Called to do the DMA or PIO mode setup. Timing numbers are all
126 * pre computed to keep the code clean. There are two tables depending
127 * on the hardware clock speed.
128 *
129 * WARNING: While we do this the IDE registers vanish. If we take an
130 * IRQ here we depend on the host set locking to avoid catastrophe.
131 */
132
133static void optidma_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
134{
135 struct ata_device *pair = ata_dev_pair(adev);
136 int pio = adev->pio_mode - XFER_PIO_0;
137 int dma = adev->dma_mode - XFER_MW_DMA_0;
138 unsigned long regio = ap->ioaddr.cmd_addr;
139 u8 addr;
140
141 /* Address table precomputed with a DCLK of 2 */
142 static const u8 addr_timing[2][5] = {
143 { 0x30, 0x20, 0x20, 0x10, 0x10 },
144 { 0x20, 0x20, 0x10, 0x10, 0x10 }
145 };
146 static const u8 data_rec_timing[2][5] = {
147 { 0x59, 0x46, 0x30, 0x20, 0x20 },
148 { 0x46, 0x32, 0x20, 0x20, 0x10 }
149 };
150 static const u8 dma_data_rec_timing[2][3] = {
151 { 0x76, 0x20, 0x20 },
152 { 0x54, 0x20, 0x10 }
153 };
154
155 /* Switch from IDE to control mode */
156 optidma_unlock(ap);
157
158
159 /*
160 * As with many controllers the address setup time is shared
161 * and must suit both devices if present. FIXME: Check if we
162 * need to look at slowest of PIO/DMA mode of either device
163 */
164
165 if (mode >= XFER_MW_DMA_0)
166 addr = 0;
167 else
168 addr = addr_timing[pci_clock][pio];
169
170 if (pair) {
171 u8 pair_addr;
172 /* Hardware constraint */
173 if (pair->dma_mode)
174 pair_addr = 0;
175 else
176 pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
177 if (pair_addr > addr)
178 addr = pair_addr;
179 }
180
181 /* Commence primary programming sequence */
182 /* First we load the device number into the timing select */
183 outb(adev->devno, regio + MISC_REG);
184 /* Now we load the data timings into read data/write data */
185 if (mode < XFER_MW_DMA_0) {
186 outb(data_rec_timing[pci_clock][pio], regio + READ_REG);
187 outb(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
188 } else if (mode < XFER_UDMA_0) {
189 outb(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
190 outb(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
191 }
192 /* Finally we load the address setup into the misc register */
193 outb(addr | adev->devno, regio + MISC_REG);
194
195 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
196 outb(0x85, regio + CNTRL_REG);
197
198 /* Switch back to IDE mode */
199 optidma_lock(ap);
200
201 /* Note: at this point our programming is incomplete. We are
202 not supposed to program PCI 0x43 "things we hacked onto the chip"
203 until we've done both sets of PIO/DMA timings */
204}
205
206/**
207 * optiplus_set_mode - DMA setup for Firestar Plus
208 * @ap: ATA port
209 * @adev: device
210 * @mode: desired mode
211 *
212 * The Firestar plus has additional UDMA functionality for UDMA0-2 and
213 * requires we do some additional work. Because the base work we must do
214 * is mostly shared we wrap the Firestar setup functionality in this
215 * one
216 */
217
218static void optiplus_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
219{
220 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
221 u8 udcfg;
222 u8 udslave;
223 int dev2 = 2 * adev->devno;
224 int unit = 2 * ap->port_no + adev->devno;
225 int udma = mode - XFER_UDMA_0;
226
227 pci_read_config_byte(pdev, 0x44, &udcfg);
228 if (mode <= XFER_UDMA_0) {
229 udcfg &= ~(1 << unit);
230 optidma_set_mode(ap, adev, adev->dma_mode);
231 } else {
232 udcfg |= (1 << unit);
233 if (ap->port_no) {
234 pci_read_config_byte(pdev, 0x45, &udslave);
235 udslave &= ~(0x03 << dev2);
236 udslave |= (udma << dev2);
237 pci_write_config_byte(pdev, 0x45, udslave);
238 } else {
239 udcfg &= ~(0x30 << dev2);
240 udcfg |= (udma << dev2);
241 }
242 }
243 pci_write_config_byte(pdev, 0x44, udcfg);
244}
245
246/**
247 * optidma_set_pio_mode - PIO setup callback
248 * @ap: ATA port
249 * @adev: Device
250 *
251 * The libata core provides separate functions for handling PIO and
252 * DMA programming. The architecture of the Firestar makes it easier
253 * for us to have a common function so we provide wrappers
254 */
255
256static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
257{
258 optidma_set_mode(ap, adev, adev->pio_mode);
259}
260
261/**
262 * optidma_set_dma_mode - DMA setup callback
263 * @ap: ATA port
264 * @adev: Device
265 *
266 * The libata core provides separate functions for handling PIO and
267 * DMA programming. The architecture of the Firestar makes it easier
268 * for us to have a common function so we provide wrappers
269 */
270
271static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
272{
273 optidma_set_mode(ap, adev, adev->dma_mode);
274}
275
276/**
277 * optiplus_set_pio_mode - PIO setup callback
278 * @ap: ATA port
279 * @adev: Device
280 *
281 * The libata core provides separate functions for handling PIO and
282 * DMA programming. The architecture of the Firestar makes it easier
283 * for us to have a common function so we provide wrappers
284 */
285
286static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
287{
288 optiplus_set_mode(ap, adev, adev->pio_mode);
289}
290
291/**
292 * optiplus_set_dma_mode - DMA setup callback
293 * @ap: ATA port
294 * @adev: Device
295 *
296 * The libata core provides separate functions for handling PIO and
297 * DMA programming. The architecture of the Firestar makes it easier
298 * for us to have a common function so we provide wrappers
299 */
300
301static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
302{
303 optiplus_set_mode(ap, adev, adev->dma_mode);
304}
305
306/**
307 * optidma_make_bits - PCI setup helper
308 * @adev: ATA device
309 *
310 * Turn the ATA device setup into PCI configuration bits
311 * for register 0x43 and return the two bits needed.
312 */
313
314static u8 optidma_make_bits43(struct ata_device *adev)
315{
316 static const u8 bits43[5] = {
317 0, 0, 0, 1, 2
318 };
319 if (!ata_dev_enabled(adev))
320 return 0;
321 if (adev->dma_mode)
322 return adev->dma_mode - XFER_MW_DMA_0;
323 return bits43[adev->pio_mode - XFER_PIO_0];
324}
325
326/**
327 * optidma_post_set_mode - finalize PCI setup
328 * @ap: port to set up
329 *
330 * Finalise the configuration by writing the nibble of extra bits
331 * of data into the chip.
332 */
333
334static void optidma_post_set_mode(struct ata_port *ap)
335{
336 u8 r;
337 int nybble = 4 * ap->port_no;
338 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
339
340 pci_read_config_byte(pdev, 0x43, &r);
341
342 r &= (0x0F << nybble);
343 r |= (optidma_make_bits43(&ap->device[0]) +
344 (optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
345
346 pci_write_config_byte(pdev, 0x43, r);
347}
348
349static struct scsi_host_template optidma_sht = {
350 .module = THIS_MODULE,
351 .name = DRV_NAME,
352 .ioctl = ata_scsi_ioctl,
353 .queuecommand = ata_scsi_queuecmd,
354 .can_queue = ATA_DEF_QUEUE,
355 .this_id = ATA_SHT_THIS_ID,
356 .sg_tablesize = LIBATA_MAX_PRD,
357 .max_sectors = ATA_MAX_SECTORS,
358 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
359 .emulated = ATA_SHT_EMULATED,
360 .use_clustering = ATA_SHT_USE_CLUSTERING,
361 .proc_name = DRV_NAME,
362 .dma_boundary = ATA_DMA_BOUNDARY,
363 .slave_configure = ata_scsi_slave_config,
364 .bios_param = ata_std_bios_param,
365};
366
367static struct ata_port_operations optidma_port_ops = {
368 .port_disable = ata_port_disable,
369 .set_piomode = optidma_set_pio_mode,
370 .set_dmamode = optidma_set_dma_mode,
371
372 .tf_load = ata_tf_load,
373 .tf_read = ata_tf_read,
374 .check_status = ata_check_status,
375 .exec_command = ata_exec_command,
376 .dev_select = ata_std_dev_select,
377
378 .freeze = ata_bmdma_freeze,
379 .thaw = ata_bmdma_thaw,
380 .post_internal_cmd = ata_bmdma_post_internal_cmd,
381 .error_handler = optidma_error_handler,
382 .post_set_mode = optidma_post_set_mode,
383
384 .bmdma_setup = ata_bmdma_setup,
385 .bmdma_start = ata_bmdma_start,
386 .bmdma_stop = ata_bmdma_stop,
387 .bmdma_status = ata_bmdma_status,
388
389 .qc_prep = ata_qc_prep,
390 .qc_issue = ata_qc_issue_prot,
391 .eng_timeout = ata_eng_timeout,
392 .data_xfer = ata_pio_data_xfer,
393
394 .irq_handler = ata_interrupt,
395 .irq_clear = ata_bmdma_irq_clear,
396
397 .port_start = ata_port_start,
398 .port_stop = ata_port_stop,
399 .host_stop = ata_host_stop
400};
401
402static struct ata_port_operations optiplus_port_ops = {
403 .port_disable = ata_port_disable,
404 .set_piomode = optiplus_set_pio_mode,
405 .set_dmamode = optiplus_set_dma_mode,
406
407 .tf_load = ata_tf_load,
408 .tf_read = ata_tf_read,
409 .check_status = ata_check_status,
410 .exec_command = ata_exec_command,
411 .dev_select = ata_std_dev_select,
412
413 .freeze = ata_bmdma_freeze,
414 .thaw = ata_bmdma_thaw,
415 .post_internal_cmd = ata_bmdma_post_internal_cmd,
416 .error_handler = optidma_error_handler,
417 .post_set_mode = optidma_post_set_mode,
418
419 .bmdma_setup = ata_bmdma_setup,
420 .bmdma_start = ata_bmdma_start,
421 .bmdma_stop = ata_bmdma_stop,
422 .bmdma_status = ata_bmdma_status,
423
424 .qc_prep = ata_qc_prep,
425 .qc_issue = ata_qc_issue_prot,
426 .eng_timeout = ata_eng_timeout,
427 .data_xfer = ata_pio_data_xfer,
428
429 .irq_handler = ata_interrupt,
430 .irq_clear = ata_bmdma_irq_clear,
431
432 .port_start = ata_port_start,
433 .port_stop = ata_port_stop,
434 .host_stop = ata_host_stop
435};
436
437/**
438 * optiplus_with_udma - Look for UDMA capable setup
439 * @pdev; ATA controller
440 */
441
442static int optiplus_with_udma(struct pci_dev *pdev)
443{
444 u8 r;
445 int ret = 0;
446 int ioport = 0x22;
447 struct pci_dev *dev1;
448
449 /* Find function 1 */
450 dev1 = pci_get_device(0x1045, 0xC701, NULL);
451 if(dev1 == NULL)
452 return 0;
453
454 /* Rev must be >= 0x10 */
455 pci_read_config_byte(dev1, 0x08, &r);
456 if (r < 0x10)
457 goto done_nomsg;
458 /* Read the chipset system configuration to check our mode */
459 pci_read_config_byte(dev1, 0x5F, &r);
460 ioport |= (r << 8);
461 outb(0x10, ioport);
462 /* Must be 66Mhz sync */
463 if ((inb(ioport + 2) & 1) == 0)
464 goto done;
465
466 /* Check the ATA arbitration/timing is suitable */
467 pci_read_config_byte(pdev, 0x42, &r);
468 if ((r & 0x36) != 0x36)
469 goto done;
470 pci_read_config_byte(dev1, 0x52, &r);
471 if (r & 0x80) /* IDEDIR disabled */
472 ret = 1;
473done:
474 printk(KERN_WARNING "UDMA not supported in this configuration.\n");
475done_nomsg: /* Wrong chip revision */
476 pci_dev_put(dev1);
477 return ret;
478}
479
480static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
481{
482 static struct ata_port_info info_82c700 = {
483 .sht = &optidma_sht,
484 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
485 .pio_mask = 0x1f,
486 .mwdma_mask = 0x07,
487 .port_ops = &optidma_port_ops
488 };
489 static struct ata_port_info info_82c700_udma = {
490 .sht = &optidma_sht,
491 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
492 .pio_mask = 0x1f,
493 .mwdma_mask = 0x07,
494 .udma_mask = 0x07,
495 .port_ops = &optiplus_port_ops
496 };
497 static struct ata_port_info *port_info[2];
498 struct ata_port_info *info = &info_82c700;
499 static int printed_version;
500
501 if (!printed_version++)
502 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
503
504 /* Fixed location chipset magic */
505 inw(0x1F1);
506 inw(0x1F1);
507 pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
508
509 if (optiplus_with_udma(dev))
510 info = &info_82c700_udma;
511
512 port_info[0] = port_info[1] = info;
513 return ata_pci_init_one(dev, port_info, 2);
514}
515
516static const struct pci_device_id optidma[] = {
517 { PCI_DEVICE(0x1045, 0xD568), }, /* Opti 82C700 */
518 { 0, },
519};
520
521static struct pci_driver optidma_pci_driver = {
522 .name = DRV_NAME,
523 .id_table = optidma,
524 .probe = optidma_init_one,
525 .remove = ata_pci_remove_one
526};
527
528static int __init optidma_init(void)
529{
530 return pci_register_driver(&optidma_pci_driver);
531}
532
533
534static void __exit optidma_exit(void)
535{
536 pci_unregister_driver(&optidma_pci_driver);
537}
538
539
540MODULE_AUTHOR("Alan Cox");
541MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
542MODULE_LICENSE("GPL");
543MODULE_DEVICE_TABLE(pci, optidma);
544MODULE_VERSION(DRV_VERSION);
545
546module_init(optidma_init);
547module_exit(optidma_exit);
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
new file mode 100644
index 00000000000..2abe0a3bbb9
--- /dev/null
+++ b/drivers/ata/pata_pcmcia.c
@@ -0,0 +1,393 @@
1/*
2 * pata_pcmcia.c - PCMCIA PATA controller driver.
3 * Copyright 2005-2006 Red Hat Inc <alan@redhat.com>, all rights reserved.
4 * PCMCIA ident update Copyright 2006 Marcin Juszkiewicz
5 * <openembedded@hrw.one.pl>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; see the file COPYING. If not, write to
19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 * Heavily based upon ide-cs.c
22 * The initial developer of the original code is David A. Hinds
23 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
24 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <scsi/scsi_host.h>
33#include <linux/ata.h>
34#include <linux/libata.h>
35
36#include <pcmcia/cs_types.h>
37#include <pcmcia/cs.h>
38#include <pcmcia/cistpl.h>
39#include <pcmcia/ds.h>
40#include <pcmcia/cisreg.h>
41#include <pcmcia/ciscode.h>
42
43
44#define DRV_NAME "pata_pcmcia"
45#define DRV_VERSION "0.2.9"
46
47/*
48 * Private data structure to glue stuff together
49 */
50
51struct ata_pcmcia_info {
52 struct pcmcia_device *pdev;
53 int ndev;
54 dev_node_t node;
55};
56
57static struct scsi_host_template pcmcia_sht = {
58 .module = THIS_MODULE,
59 .name = DRV_NAME,
60 .ioctl = ata_scsi_ioctl,
61 .queuecommand = ata_scsi_queuecmd,
62 .can_queue = ATA_DEF_QUEUE,
63 .this_id = ATA_SHT_THIS_ID,
64 .sg_tablesize = LIBATA_MAX_PRD,
65 .max_sectors = ATA_MAX_SECTORS,
66 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
67 .emulated = ATA_SHT_EMULATED,
68 .use_clustering = ATA_SHT_USE_CLUSTERING,
69 .proc_name = DRV_NAME,
70 .dma_boundary = ATA_DMA_BOUNDARY,
71 .slave_configure = ata_scsi_slave_config,
72 .bios_param = ata_std_bios_param,
73};
74
75static struct ata_port_operations pcmcia_port_ops = {
76 .port_disable = ata_port_disable,
77 .tf_load = ata_tf_load,
78 .tf_read = ata_tf_read,
79 .check_status = ata_check_status,
80 .exec_command = ata_exec_command,
81 .dev_select = ata_std_dev_select,
82
83 .freeze = ata_bmdma_freeze,
84 .thaw = ata_bmdma_thaw,
85 .error_handler = ata_bmdma_error_handler,
86 .post_internal_cmd = ata_bmdma_post_internal_cmd,
87
88 .qc_prep = ata_qc_prep,
89 .qc_issue = ata_qc_issue_prot,
90 .eng_timeout = ata_eng_timeout,
91 .data_xfer = ata_pio_data_xfer_noirq,
92
93 .irq_handler = ata_interrupt,
94 .irq_clear = ata_bmdma_irq_clear,
95
96 .port_start = ata_port_start,
97 .port_stop = ata_port_stop,
98 .host_stop = ata_host_stop
99};
100
101#define CS_CHECK(fn, ret) \
102do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
103
104/**
105 * pcmcia_init_one - attach a PCMCIA interface
106 * @pdev: pcmcia device
107 *
108 * Register a PCMCIA IDE interface. Such interfaces are PIO 0 and
109 * shared IRQ.
110 */
111
112static int pcmcia_init_one(struct pcmcia_device *pdev)
113{
114 struct ata_probe_ent ae;
115 struct ata_pcmcia_info *info;
116 tuple_t tuple;
117 struct {
118 unsigned short buf[128];
119 cisparse_t parse;
120 config_info_t conf;
121 cistpl_cftable_entry_t dflt;
122 } *stk = NULL;
123 cistpl_cftable_entry_t *cfg;
124 int pass, last_ret = 0, last_fn = 0, is_kme = 0, ret = -ENOMEM;
125 unsigned long io_base, ctl_base;
126
127 info = kzalloc(sizeof(*info), GFP_KERNEL);
128 if (info == NULL)
129 return -ENOMEM;
130
131 /* Glue stuff together. FIXME: We may be able to get rid of info with care */
132 info->pdev = pdev;
133 pdev->priv = info;
134
135 /* Set up attributes in order to probe card and get resources */
136 pdev->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
137 pdev->io.Attributes2 = IO_DATA_PATH_WIDTH_8;
138 pdev->io.IOAddrLines = 3;
139 pdev->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING;
140 pdev->irq.IRQInfo1 = IRQ_LEVEL_ID;
141 pdev->conf.Attributes = CONF_ENABLE_IRQ;
142 pdev->conf.IntType = INT_MEMORY_AND_IO;
143
144 /* Allocate resoure probing structures */
145
146 stk = kzalloc(sizeof(*stk), GFP_KERNEL);
147 if (!stk)
148 goto out1;
149
150 cfg = &stk->parse.cftable_entry;
151
152 /* Tuples we are walking */
153 tuple.TupleData = (cisdata_t *)&stk->buf;
154 tuple.TupleOffset = 0;
155 tuple.TupleDataMax = 255;
156 tuple.Attributes = 0;
157 tuple.DesiredTuple = CISTPL_CONFIG;
158
159 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(pdev, &tuple));
160 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(pdev, &tuple));
161 CS_CHECK(ParseTuple, pcmcia_parse_tuple(pdev, &tuple, &stk->parse));
162 pdev->conf.ConfigBase = stk->parse.config.base;
163 pdev->conf.Present = stk->parse.config.rmask[0];
164
165 /* See if we have a manufacturer identifier. Use it to set is_kme for
166 vendor quirks */
167 tuple.DesiredTuple = CISTPL_MANFID;
168 if (!pcmcia_get_first_tuple(pdev, &tuple) && !pcmcia_get_tuple_data(pdev, &tuple) && !pcmcia_parse_tuple(pdev, &tuple, &stk->parse))
169 is_kme = ((stk->parse.manfid.manf == MANFID_KME) && ((stk->parse.manfid.card == PRODID_KME_KXLC005_A) || (stk->parse.manfid.card == PRODID_KME_KXLC005_B)));
170
171 /* Not sure if this is right... look up the current Vcc */
172 CS_CHECK(GetConfigurationInfo, pcmcia_get_configuration_info(pdev, &stk->conf));
173/* link->conf.Vcc = stk->conf.Vcc; */
174
175 pass = io_base = ctl_base = 0;
176 tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
177 tuple.Attributes = 0;
178 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(pdev, &tuple));
179
180 /* Now munch the resources looking for a suitable set */
181 while (1) {
182 if (pcmcia_get_tuple_data(pdev, &tuple) != 0)
183 goto next_entry;
184 if (pcmcia_parse_tuple(pdev, &tuple, &stk->parse) != 0)
185 goto next_entry;
186 /* Check for matching Vcc, unless we're desperate */
187 if (!pass) {
188 if (cfg->vcc.present & (1 << CISTPL_POWER_VNOM)) {
189 if (stk->conf.Vcc != cfg->vcc.param[CISTPL_POWER_VNOM] / 10000)
190 goto next_entry;
191 } else if (stk->dflt.vcc.present & (1 << CISTPL_POWER_VNOM)) {
192 if (stk->conf.Vcc != stk->dflt.vcc.param[CISTPL_POWER_VNOM] / 10000)
193 goto next_entry;
194 }
195 }
196
197 if (cfg->vpp1.present & (1 << CISTPL_POWER_VNOM))
198 pdev->conf.Vpp = cfg->vpp1.param[CISTPL_POWER_VNOM] / 10000;
199 else if (stk->dflt.vpp1.present & (1 << CISTPL_POWER_VNOM))
200 pdev->conf.Vpp = stk->dflt.vpp1.param[CISTPL_POWER_VNOM] / 10000;
201
202 if ((cfg->io.nwin > 0) || (stk->dflt.io.nwin > 0)) {
203 cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &stk->dflt.io;
204 pdev->conf.ConfigIndex = cfg->index;
205 pdev->io.BasePort1 = io->win[0].base;
206 pdev->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
207 if (!(io->flags & CISTPL_IO_16BIT))
208 pdev->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
209 if (io->nwin == 2) {
210 pdev->io.NumPorts1 = 8;
211 pdev->io.BasePort2 = io->win[1].base;
212 pdev->io.NumPorts2 = (is_kme) ? 2 : 1;
213 if (pcmcia_request_io(pdev, &pdev->io) != 0)
214 goto next_entry;
215 io_base = pdev->io.BasePort1;
216 ctl_base = pdev->io.BasePort2;
217 } else if ((io->nwin == 1) && (io->win[0].len >= 16)) {
218 pdev->io.NumPorts1 = io->win[0].len;
219 pdev->io.NumPorts2 = 0;
220 if (pcmcia_request_io(pdev, &pdev->io) != 0)
221 goto next_entry;
222 io_base = pdev->io.BasePort1;
223 ctl_base = pdev->io.BasePort1 + 0x0e;
224 } else goto next_entry;
225 /* If we've got this far, we're done */
226 break;
227 }
228next_entry:
229 if (cfg->flags & CISTPL_CFTABLE_DEFAULT)
230 memcpy(&stk->dflt, cfg, sizeof(stk->dflt));
231 if (pass) {
232 CS_CHECK(GetNextTuple, pcmcia_get_next_tuple(pdev, &tuple));
233 } else if (pcmcia_get_next_tuple(pdev, &tuple) != 0) {
234 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(pdev, &tuple));
235 memset(&stk->dflt, 0, sizeof(stk->dflt));
236 pass++;
237 }
238 }
239
240 CS_CHECK(RequestIRQ, pcmcia_request_irq(pdev, &pdev->irq));
241 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(pdev, &pdev->conf));
242
243 /* Success. Disable the IRQ nIEN line, do quirks */
244 outb(0x02, ctl_base);
245 if (is_kme)
246 outb(0x81, ctl_base + 0x01);
247
248 /* FIXME: Could be more ports at base + 0x10 but we only deal with
249 one right now */
250 if (pdev->io.NumPorts1 >= 0x20)
251 printk(KERN_WARNING DRV_NAME ": second channel not yet supported.\n");
252
253 /*
254 * Having done the PCMCIA plumbing the ATA side is relatively
255 * sane.
256 */
257
258 memset(&ae, 0, sizeof(struct ata_probe_ent));
259 INIT_LIST_HEAD(&ae.node);
260 ae.dev = &pdev->dev;
261 ae.port_ops = &pcmcia_port_ops;
262 ae.sht = &pcmcia_sht;
263 ae.n_ports = 1;
264 ae.pio_mask = 1; /* ISA so PIO 0 cycles */
265 ae.irq = pdev->irq.AssignedIRQ;
266 ae.irq_flags = SA_SHIRQ;
267 ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
268 ae.port[0].cmd_addr = io_base;
269 ae.port[0].altstatus_addr = ctl_base;
270 ae.port[0].ctl_addr = ctl_base;
271 ata_std_ports(&ae.port[0]);
272
273 if (ata_device_add(&ae) == 0)
274 goto failed;
275
276 info->ndev = 1;
277 kfree(stk);
278 return 0;
279
280cs_failed:
281 cs_error(pdev, last_fn, last_ret);
282failed:
283 kfree(stk);
284 info->ndev = 0;
285 pcmcia_disable_device(pdev);
286out1:
287 kfree(info);
288 return ret;
289}
290
291/**
292 * pcmcia_remove_one - unplug an pcmcia interface
293 * @pdev: pcmcia device
294 *
295 * A PCMCIA ATA device has been unplugged. Perform the needed
296 * cleanup. Also called on module unload for any active devices.
297 */
298
299static void pcmcia_remove_one(struct pcmcia_device *pdev)
300{
301 struct ata_pcmcia_info *info = pdev->priv;
302 struct device *dev = &pdev->dev;
303
304 if (info != NULL) {
305 /* If we have attached the device to the ATA layer, detach it */
306 if (info->ndev) {
307 struct ata_host *host = dev_get_drvdata(dev);
308 ata_host_remove(host);
309 dev_set_drvdata(dev, NULL);
310 }
311 info->ndev = 0;
312 pdev->priv = NULL;
313 }
314 pcmcia_disable_device(pdev);
315 kfree(info);
316}
317
318static struct pcmcia_device_id pcmcia_devices[] = {
319 PCMCIA_DEVICE_FUNC_ID(4),
320 PCMCIA_DEVICE_MANF_CARD(0x0007, 0x0000), /* Hitachi */
321 PCMCIA_DEVICE_MANF_CARD(0x0032, 0x0704),
322 PCMCIA_DEVICE_MANF_CARD(0x0045, 0x0401),
323 PCMCIA_DEVICE_MANF_CARD(0x0098, 0x0000), /* Toshiba */
324 PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x002d),
325 PCMCIA_DEVICE_MANF_CARD(0x00ce, 0x0000), /* Samsung */
326 PCMCIA_DEVICE_MANF_CARD(0x0319, 0x0000), /* Hitachi */
327 PCMCIA_DEVICE_MANF_CARD(0x2080, 0x0001),
328 PCMCIA_DEVICE_MANF_CARD(0x4e01, 0x0200), /* Lexar */
329 PCMCIA_DEVICE_PROD_ID123("Caravelle", "PSC-IDE ", "PSC000", 0x8c36137c, 0xd0693ab8, 0x2768a9f0),
330 PCMCIA_DEVICE_PROD_ID123("CDROM", "IDE", "MCD-601p", 0x1b9179ca, 0xede88951, 0x0d902f74),
331 PCMCIA_DEVICE_PROD_ID123("PCMCIA", "IDE CARD", "F1", 0x281f1c5d, 0x1907960c, 0xf7fde8b9),
332 PCMCIA_DEVICE_PROD_ID12("ARGOSY", "CD-ROM", 0x78f308dc, 0x66536591),
333 PCMCIA_DEVICE_PROD_ID12("ARGOSY", "PnPIDE", 0x78f308dc, 0x0c694728),
334 PCMCIA_DEVICE_PROD_ID12("CNF CD-M", "CD-ROM", 0x7d93b852, 0x66536591),
335 PCMCIA_DEVICE_PROD_ID12("Creative Technology Ltd.", "PCMCIA CD-ROM Interface Card", 0xff8c8a45, 0xfe8020c4),
336 PCMCIA_DEVICE_PROD_ID12("Digital Equipment Corporation.", "Digital Mobile Media CD-ROM", 0x17692a66, 0xef1dcbde),
337 PCMCIA_DEVICE_PROD_ID12("EXP", "CD+GAME", 0x6f58c983, 0x63c13aaf),
338 PCMCIA_DEVICE_PROD_ID12("EXP ", "CD-ROM", 0x0a5c52fd, 0x66536591),
339 PCMCIA_DEVICE_PROD_ID12("EXP ", "PnPIDE", 0x0a5c52fd, 0x0c694728),
340 PCMCIA_DEVICE_PROD_ID12("FREECOM", "PCCARD-IDE", 0x5714cbf7, 0x48e0ab8e),
341 PCMCIA_DEVICE_PROD_ID12("HITACHI", "FLASH", 0xf4f43949, 0x9eb86aae),
342 PCMCIA_DEVICE_PROD_ID12("HITACHI", "microdrive", 0xf4f43949, 0xa6d76178),
343 PCMCIA_DEVICE_PROD_ID12("IBM", "microdrive", 0xb569a6e5, 0xa6d76178),
344 PCMCIA_DEVICE_PROD_ID12("IBM", "IBM17JSSFP20", 0xb569a6e5, 0xf2508753),
345 PCMCIA_DEVICE_PROD_ID12("IO DATA", "CBIDE2 ", 0x547e66dc, 0x8671043b),
346 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149),
347 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674),
348 PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b),
349 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c),
350 PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
351 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
352 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "PnPIDE", 0x281f1c5d, 0x0c694728),
353 PCMCIA_DEVICE_PROD_ID12("SHUTTLE TECHNOLOGY LTD.", "PCCARD-IDE/ATAPI Adapter", 0x4a3f0ba0, 0x322560e1),
354 PCMCIA_DEVICE_PROD_ID12("SEAGATE", "ST1", 0x87c1b330, 0xe1f30883),
355 PCMCIA_DEVICE_PROD_ID12("SAMSUNG", "04/05/06", 0x43d74cb4, 0x6a22777d),
356 PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6),
357 PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
358 PCMCIA_DEVICE_PROD_ID12("WIT", "IDE16", 0x244e5994, 0x3e232852),
359 PCMCIA_DEVICE_PROD_ID1("STI Flash", 0xe4a13209),
360 PCMCIA_DEVICE_PROD_ID12("STI", "Flash 5.0", 0xbf2df18d, 0x8cb57a0e),
361 PCMCIA_MFC_DEVICE_PROD_ID12(1, "SanDisk", "ConnectPlus", 0x7a954bd9, 0x74be00c6),
362 PCMCIA_DEVICE_NULL,
363};
364
365MODULE_DEVICE_TABLE(pcmcia, pcmcia_devices);
366
367static struct pcmcia_driver pcmcia_driver = {
368 .owner = THIS_MODULE,
369 .drv = {
370 .name = DRV_NAME,
371 },
372 .id_table = pcmcia_devices,
373 .probe = pcmcia_init_one,
374 .remove = pcmcia_remove_one,
375};
376
377static int __init pcmcia_init(void)
378{
379 return pcmcia_register_driver(&pcmcia_driver);
380}
381
382static void __exit pcmcia_exit(void)
383{
384 pcmcia_unregister_driver(&pcmcia_driver);
385}
386
387MODULE_AUTHOR("Alan Cox");
388MODULE_DESCRIPTION("low-level driver for PCMCIA ATA");
389MODULE_LICENSE("GPL");
390MODULE_VERSION(DRV_VERSION);
391
392module_init(pcmcia_init);
393module_exit(pcmcia_exit);
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
new file mode 100644
index 00000000000..56b8c1ee293
--- /dev/null
+++ b/drivers/ata/pata_pdc2027x.c
@@ -0,0 +1,869 @@
1/*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi.h>
33#include <scsi/scsi_host.h>
34#include <scsi/scsi_cmnd.h>
35#include <linux/libata.h>
36#include <asm/io.h>
37
38#define DRV_NAME "pata_pdc2027x"
39#define DRV_VERSION "0.74-ac3"
40#undef PDC_DEBUG
41
42#ifdef PDC_DEBUG
43#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
44#else
45#define PDPRINTK(fmt, args...)
46#endif
47
48enum {
49 PDC_UDMA_100 = 0,
50 PDC_UDMA_133 = 1,
51
52 PDC_100_MHZ = 100000000,
53 PDC_133_MHZ = 133333333,
54
55 PDC_SYS_CTL = 0x1100,
56 PDC_ATA_CTL = 0x1104,
57 PDC_GLOBAL_CTL = 0x1108,
58 PDC_CTCR0 = 0x110C,
59 PDC_CTCR1 = 0x1110,
60 PDC_BYTE_COUNT = 0x1120,
61 PDC_PLL_CTL = 0x1202,
62};
63
64static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
65static void pdc2027x_remove_one(struct pci_dev *pdev);
66static void pdc2027x_error_handler(struct ata_port *ap);
67static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
69static void pdc2027x_post_set_mode(struct ata_port *ap);
70static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
71
72/*
73 * ATA Timing Tables based on 133MHz controller clock.
74 * These tables are only used when the controller is in 133MHz clock.
75 * If the controller is in 100MHz clock, the ASIC hardware will
76 * set the timing registers automatically when "set feature" command
77 * is issued to the device. However, if the controller clock is 133MHz,
78 * the following tables must be used.
79 */
80static struct pdc2027x_pio_timing {
81 u8 value0, value1, value2;
82} pdc2027x_pio_timing_tbl [] = {
83 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
84 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
85 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
86 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
87 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
88};
89
90static struct pdc2027x_mdma_timing {
91 u8 value0, value1;
92} pdc2027x_mdma_timing_tbl [] = {
93 { 0xdf, 0x5f }, /* MDMA mode 0 */
94 { 0x6b, 0x27 }, /* MDMA mode 1 */
95 { 0x69, 0x25 }, /* MDMA mode 2 */
96};
97
98static struct pdc2027x_udma_timing {
99 u8 value0, value1, value2;
100} pdc2027x_udma_timing_tbl [] = {
101 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
102 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
103 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
104 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
105 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
106 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
107 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
108};
109
110static const struct pci_device_id pdc2027x_pci_tbl[] = {
111 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
112 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
113 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
114 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
115 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
116 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
117 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
118 { } /* terminate list */
119};
120
121static struct pci_driver pdc2027x_pci_driver = {
122 .name = DRV_NAME,
123 .id_table = pdc2027x_pci_tbl,
124 .probe = pdc2027x_init_one,
125 .remove = __devexit_p(pdc2027x_remove_one),
126};
127
128static struct scsi_host_template pdc2027x_sht = {
129 .module = THIS_MODULE,
130 .name = DRV_NAME,
131 .ioctl = ata_scsi_ioctl,
132 .queuecommand = ata_scsi_queuecmd,
133 .can_queue = ATA_DEF_QUEUE,
134 .this_id = ATA_SHT_THIS_ID,
135 .sg_tablesize = LIBATA_MAX_PRD,
136 .max_sectors = ATA_MAX_SECTORS,
137 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
138 .emulated = ATA_SHT_EMULATED,
139 .use_clustering = ATA_SHT_USE_CLUSTERING,
140 .proc_name = DRV_NAME,
141 .dma_boundary = ATA_DMA_BOUNDARY,
142 .slave_configure = ata_scsi_slave_config,
143 .bios_param = ata_std_bios_param,
144};
145
146static struct ata_port_operations pdc2027x_pata100_ops = {
147 .port_disable = ata_port_disable,
148
149 .tf_load = ata_tf_load,
150 .tf_read = ata_tf_read,
151 .check_status = ata_check_status,
152 .exec_command = ata_exec_command,
153 .dev_select = ata_std_dev_select,
154
155 .check_atapi_dma = pdc2027x_check_atapi_dma,
156 .bmdma_setup = ata_bmdma_setup,
157 .bmdma_start = ata_bmdma_start,
158 .bmdma_stop = ata_bmdma_stop,
159 .bmdma_status = ata_bmdma_status,
160 .qc_prep = ata_qc_prep,
161 .qc_issue = ata_qc_issue_prot,
162 .data_xfer = ata_mmio_data_xfer,
163
164 .freeze = ata_bmdma_freeze,
165 .thaw = ata_bmdma_thaw,
166 .error_handler = pdc2027x_error_handler,
167 .post_internal_cmd = ata_bmdma_post_internal_cmd,
168
169 .irq_handler = ata_interrupt,
170 .irq_clear = ata_bmdma_irq_clear,
171
172 .port_start = ata_port_start,
173 .port_stop = ata_port_stop,
174 .host_stop = ata_pci_host_stop,
175};
176
177static struct ata_port_operations pdc2027x_pata133_ops = {
178 .port_disable = ata_port_disable,
179 .set_piomode = pdc2027x_set_piomode,
180 .set_dmamode = pdc2027x_set_dmamode,
181 .post_set_mode = pdc2027x_post_set_mode,
182
183 .tf_load = ata_tf_load,
184 .tf_read = ata_tf_read,
185 .check_status = ata_check_status,
186 .exec_command = ata_exec_command,
187 .dev_select = ata_std_dev_select,
188
189 .check_atapi_dma = pdc2027x_check_atapi_dma,
190 .bmdma_setup = ata_bmdma_setup,
191 .bmdma_start = ata_bmdma_start,
192 .bmdma_stop = ata_bmdma_stop,
193 .bmdma_status = ata_bmdma_status,
194 .qc_prep = ata_qc_prep,
195 .qc_issue = ata_qc_issue_prot,
196 .data_xfer = ata_mmio_data_xfer,
197
198 .freeze = ata_bmdma_freeze,
199 .thaw = ata_bmdma_thaw,
200 .error_handler = pdc2027x_error_handler,
201 .post_internal_cmd = ata_bmdma_post_internal_cmd,
202
203 .irq_handler = ata_interrupt,
204 .irq_clear = ata_bmdma_irq_clear,
205
206 .port_start = ata_port_start,
207 .port_stop = ata_port_stop,
208 .host_stop = ata_pci_host_stop,
209};
210
211static struct ata_port_info pdc2027x_port_info[] = {
212 /* PDC_UDMA_100 */
213 {
214 .sht = &pdc2027x_sht,
215 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
216 ATA_FLAG_MMIO,
217 .pio_mask = 0x1f, /* pio0-4 */
218 .mwdma_mask = 0x07, /* mwdma0-2 */
219 .udma_mask = ATA_UDMA5, /* udma0-5 */
220 .port_ops = &pdc2027x_pata100_ops,
221 },
222 /* PDC_UDMA_133 */
223 {
224 .sht = &pdc2027x_sht,
225 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
226 ATA_FLAG_MMIO,
227 .pio_mask = 0x1f, /* pio0-4 */
228 .mwdma_mask = 0x07, /* mwdma0-2 */
229 .udma_mask = ATA_UDMA6, /* udma0-6 */
230 .port_ops = &pdc2027x_pata133_ops,
231 },
232};
233
234MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
235MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
236MODULE_LICENSE("GPL");
237MODULE_VERSION(DRV_VERSION);
238MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
239
240/**
241 * port_mmio - Get the MMIO address of PDC2027x extended registers
242 * @ap: Port
243 * @offset: offset from mmio base
244 */
245static inline void* port_mmio(struct ata_port *ap, unsigned int offset)
246{
247 return ap->host->mmio_base + ap->port_no * 0x100 + offset;
248}
249
250/**
251 * dev_mmio - Get the MMIO address of PDC2027x extended registers
252 * @ap: Port
253 * @adev: device
254 * @offset: offset from mmio base
255 */
256static inline void* dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
257{
258 u8 adj = (adev->devno) ? 0x08 : 0x00;
259 return port_mmio(ap, offset) + adj;
260}
261
262/**
263 * pdc2027x_pata_cbl_detect - Probe host controller cable detect info
264 * @ap: Port for which cable detect info is desired
265 *
266 * Read 80c cable indicator from Promise extended register.
267 * This register is latched when the system is reset.
268 *
269 * LOCKING:
270 * None (inherited from caller).
271 */
272static void pdc2027x_cbl_detect(struct ata_port *ap)
273{
274 u32 cgcr;
275
276 /* check cable detect results */
277 cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
278 if (cgcr & (1 << 26))
279 goto cbl40;
280
281 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
282
283 ap->cbl = ATA_CBL_PATA80;
284 return;
285
286cbl40:
287 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
288 ap->cbl = ATA_CBL_PATA40;
289 ap->udma_mask &= ATA_UDMA_MASK_40C;
290}
291
292/**
293 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
294 * @ap: Port to check
295 */
296static inline int pdc2027x_port_enabled(struct ata_port *ap)
297{
298 return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
299}
300
301/**
302 * pdc2027x_prereset - prereset for PATA host controller
303 * @ap: Target port
304 *
305 * Probeinit including cable detection.
306 *
307 * LOCKING:
308 * None (inherited from caller).
309 */
310
311static int pdc2027x_prereset(struct ata_port *ap)
312{
313 /* Check whether port enabled */
314 if (!pdc2027x_port_enabled(ap)) {
315 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
316 return 0;
317 }
318 pdc2027x_cbl_detect(ap);
319 return ata_std_prereset(ap);
320}
321
322/**
323 * pdc2027x_error_handler - Perform reset on PATA port and classify
324 * @ap: Port to reset
325 *
326 * Reset PATA phy and classify attached devices.
327 *
328 * LOCKING:
329 * None (inherited from caller).
330 */
331
332static void pdc2027x_error_handler(struct ata_port *ap)
333{
334 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
335}
336
337/**
338 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
339 * @ap: Port to configure
340 * @adev: um
341 * @pio: PIO mode, 0 - 4
342 *
343 * Set PIO mode for device.
344 *
345 * LOCKING:
346 * None (inherited from caller).
347 */
348
349static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
350{
351 unsigned int pio = adev->pio_mode - XFER_PIO_0;
352 u32 ctcr0, ctcr1;
353
354 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
355
356 /* Sanity check */
357 if (pio > 4) {
358 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
359 return;
360
361 }
362
363 /* Set the PIO timing registers using value table for 133MHz */
364 PDPRINTK("Set pio regs... \n");
365
366 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
367 ctcr0 &= 0xffff0000;
368 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
369 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
370 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
371
372 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
373 ctcr1 &= 0x00ffffff;
374 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
375 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
376
377 PDPRINTK("Set pio regs done\n");
378
379 PDPRINTK("Set to pio mode[%u] \n", pio);
380}
381
382/**
383 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
384 * @ap: Port to configure
385 * @adev: um
386 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
387 *
388 * Set UDMA mode for device.
389 *
390 * LOCKING:
391 * None (inherited from caller).
392 */
393static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
394{
395 unsigned int dma_mode = adev->dma_mode;
396 u32 ctcr0, ctcr1;
397
398 if ((dma_mode >= XFER_UDMA_0) &&
399 (dma_mode <= XFER_UDMA_6)) {
400 /* Set the UDMA timing registers with value table for 133MHz */
401 unsigned int udma_mode = dma_mode & 0x07;
402
403 if (dma_mode == XFER_UDMA_2) {
404 /*
405 * Turn off tHOLD.
406 * If tHOLD is '1', the hardware will add half clock for data hold time.
407 * This code segment seems to be no effect. tHOLD will be overwritten below.
408 */
409 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
410 writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
411 }
412
413 PDPRINTK("Set udma regs... \n");
414
415 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
416 ctcr1 &= 0xff000000;
417 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
418 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
419 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
420 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
421
422 PDPRINTK("Set udma regs done\n");
423
424 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
425
426 } else if ((dma_mode >= XFER_MW_DMA_0) &&
427 (dma_mode <= XFER_MW_DMA_2)) {
428 /* Set the MDMA timing registers with value table for 133MHz */
429 unsigned int mdma_mode = dma_mode & 0x07;
430
431 PDPRINTK("Set mdma regs... \n");
432 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
433
434 ctcr0 &= 0x0000ffff;
435 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
436 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
437
438 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
439 PDPRINTK("Set mdma regs done\n");
440
441 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
442 } else {
443 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
444 }
445}
446
447/**
448 * pdc2027x_post_set_mode - Set the timing registers back to correct values.
449 * @ap: Port to configure
450 *
451 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
452 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
453 * This function overwrites the possibly incorrect values set by the hardware to be correct.
454 */
455static void pdc2027x_post_set_mode(struct ata_port *ap)
456{
457 int i;
458
459 for (i = 0; i < ATA_MAX_DEVICES; i++) {
460 struct ata_device *dev = &ap->device[i];
461
462 if (ata_dev_enabled(dev)) {
463
464 pdc2027x_set_piomode(ap, dev);
465
466 /*
467 * Enable prefetch if the device support PIO only.
468 */
469 if (dev->xfer_shift == ATA_SHIFT_PIO) {
470 u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
471 ctcr1 |= (1 << 25);
472 writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
473
474 PDPRINTK("Turn on prefetch\n");
475 } else {
476 pdc2027x_set_dmamode(ap, dev);
477 }
478 }
479 }
480}
481
482/**
483 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
484 * @qc: Metadata associated with taskfile to check
485 *
486 * LOCKING:
487 * None (inherited from caller).
488 *
489 * RETURNS: 0 when ATAPI DMA can be used
490 * 1 otherwise
491 */
492static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
493{
494 struct scsi_cmnd *cmd = qc->scsicmd;
495 u8 *scsicmd = cmd->cmnd;
496 int rc = 1; /* atapi dma off by default */
497
498 /*
499 * This workaround is from Promise's GPL driver.
500 * If ATAPI DMA is used for commands not in the
501 * following white list, say MODE_SENSE and REQUEST_SENSE,
502 * pdc2027x might hit the irq lost problem.
503 */
504 switch (scsicmd[0]) {
505 case READ_10:
506 case WRITE_10:
507 case READ_12:
508 case WRITE_12:
509 case READ_6:
510 case WRITE_6:
511 case 0xad: /* READ_DVD_STRUCTURE */
512 case 0xbe: /* READ_CD */
513 /* ATAPI DMA is ok */
514 rc = 0;
515 break;
516 default:
517 ;
518 }
519
520 return rc;
521}
522
523/**
524 * pdc_read_counter - Read the ctr counter
525 * @probe_ent: for the port address
526 */
527
528static long pdc_read_counter(struct ata_probe_ent *probe_ent)
529{
530 long counter;
531 int retry = 1;
532 u32 bccrl, bccrh, bccrlv, bccrhv;
533
534retry:
535 bccrl = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff;
536 bccrh = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
537 rmb();
538
539 /* Read the counter values again for verification */
540 bccrlv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff;
541 bccrhv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
542 rmb();
543
544 counter = (bccrh << 15) | bccrl;
545
546 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
547 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
548
549 /*
550 * The 30-bit decreasing counter are read by 2 pieces.
551 * Incorrect value may be read when both bccrh and bccrl are changing.
552 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
553 */
554 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
555 retry--;
556 PDPRINTK("rereading counter\n");
557 goto retry;
558 }
559
560 return counter;
561}
562
563/**
564 * adjust_pll - Adjust the PLL input clock in Hz.
565 *
566 * @pdc_controller: controller specific information
567 * @probe_ent: For the port address
568 * @pll_clock: The input of PLL in HZ
569 */
570static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx)
571{
572
573 u16 pll_ctl;
574 long pll_clock_khz = pll_clock / 1000;
575 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
576 long ratio = pout_required / pll_clock_khz;
577 int F, R;
578
579 /* Sanity check */
580 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
581 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
582 return;
583 }
584
585#ifdef PDC_DEBUG
586 PDPRINTK("pout_required is %ld\n", pout_required);
587
588 /* Show the current clock value of PLL control register
589 * (maybe already configured by the firmware)
590 */
591 pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL);
592
593 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
594#endif
595
596 /*
597 * Calculate the ratio of F, R and OD
598 * POUT = (F + 2) / (( R + 2) * NO)
599 */
600 if (ratio < 8600L) { /* 8.6x */
601 /* Using NO = 0x01, R = 0x0D */
602 R = 0x0d;
603 } else if (ratio < 12900L) { /* 12.9x */
604 /* Using NO = 0x01, R = 0x08 */
605 R = 0x08;
606 } else if (ratio < 16100L) { /* 16.1x */
607 /* Using NO = 0x01, R = 0x06 */
608 R = 0x06;
609 } else if (ratio < 64000L) { /* 64x */
610 R = 0x00;
611 } else {
612 /* Invalid ratio */
613 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
614 return;
615 }
616
617 F = (ratio * (R+2)) / 1000 - 2;
618
619 if (unlikely(F < 0 || F > 127)) {
620 /* Invalid F */
621 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
622 return;
623 }
624
625 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
626
627 pll_ctl = (R << 8) | F;
628
629 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
630
631 writew(pll_ctl, probe_ent->mmio_base + PDC_PLL_CTL);
632 readw(probe_ent->mmio_base + PDC_PLL_CTL); /* flush */
633
634 /* Wait the PLL circuit to be stable */
635 mdelay(30);
636
637#ifdef PDC_DEBUG
638 /*
639 * Show the current clock value of PLL control register
640 * (maybe configured by the firmware)
641 */
642 pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL);
643
644 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
645#endif
646
647 return;
648}
649
650/**
651 * detect_pll_input_clock - Detect the PLL input clock in Hz.
652 * @probe_ent: for the port address
653 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
654 * Half of the PCI clock.
655 */
656static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
657{
658 u32 scr;
659 long start_count, end_count;
660 long pll_clock;
661
662 /* Read current counter value */
663 start_count = pdc_read_counter(probe_ent);
664
665 /* Start the test mode */
666 scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
667 PDPRINTK("scr[%X]\n", scr);
668 writel(scr | (0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL);
669 readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
670
671 /* Let the counter run for 100 ms. */
672 mdelay(100);
673
674 /* Read the counter values again */
675 end_count = pdc_read_counter(probe_ent);
676
677 /* Stop the test mode */
678 scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
679 PDPRINTK("scr[%X]\n", scr);
680 writel(scr & ~(0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL);
681 readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
682
683 /* calculate the input clock in Hz */
684 pll_clock = (start_count - end_count) * 10;
685
686 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
687 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
688
689 return pll_clock;
690}
691
692/**
693 * pdc_hardware_init - Initialize the hardware.
694 * @pdev: instance of pci_dev found
695 * @pdc_controller: controller specific information
696 * @pe: for the port address
697 */
698static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx)
699{
700 long pll_clock;
701
702 /*
703 * Detect PLL input clock rate.
704 * On some system, where PCI bus is running at non-standard clock rate.
705 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
706 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
707 */
708 pll_clock = pdc_detect_pll_input_clock(pe);
709
710 if (pll_clock < 0) /* counter overflow? Try again. */
711 pll_clock = pdc_detect_pll_input_clock(pe);
712
713 dev_printk(KERN_INFO, &pdev->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
714
715 /* Adjust PLL control register */
716 pdc_adjust_pll(pe, pll_clock, board_idx);
717
718 return 0;
719}
720
721/**
722 * pdc_ata_setup_port - setup the mmio address
723 * @port: ata ioports to setup
724 * @base: base address
725 */
726static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
727{
728 port->cmd_addr =
729 port->data_addr = base;
730 port->feature_addr =
731 port->error_addr = base + 0x05;
732 port->nsect_addr = base + 0x0a;
733 port->lbal_addr = base + 0x0f;
734 port->lbam_addr = base + 0x10;
735 port->lbah_addr = base + 0x15;
736 port->device_addr = base + 0x1a;
737 port->command_addr =
738 port->status_addr = base + 0x1f;
739 port->altstatus_addr =
740 port->ctl_addr = base + 0x81a;
741}
742
743/**
744 * pdc2027x_init_one - PCI probe function
745 * Called when an instance of PCI adapter is inserted.
746 * This function checks whether the hardware is supported,
747 * initialize hardware and register an instance of ata_host to
748 * libata by providing struct ata_probe_ent and ata_device_add().
749 * (implements struct pci_driver.probe() )
750 *
751 * @pdev: instance of pci_dev found
752 * @ent: matching entry in the id_tbl[]
753 */
754static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
755{
756 static int printed_version;
757 unsigned int board_idx = (unsigned int) ent->driver_data;
758
759 struct ata_probe_ent *probe_ent = NULL;
760 unsigned long base;
761 void *mmio_base;
762 int rc;
763
764 if (!printed_version++)
765 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
766
767 rc = pci_enable_device(pdev);
768 if (rc)
769 return rc;
770
771 rc = pci_request_regions(pdev, DRV_NAME);
772 if (rc)
773 goto err_out;
774
775 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
776 if (rc)
777 goto err_out_regions;
778
779 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
780 if (rc)
781 goto err_out_regions;
782
783 /* Prepare the probe entry */
784 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
785 if (probe_ent == NULL) {
786 rc = -ENOMEM;
787 goto err_out_regions;
788 }
789
790 probe_ent->dev = pci_dev_to_dev(pdev);
791 INIT_LIST_HEAD(&probe_ent->node);
792
793 mmio_base = pci_iomap(pdev, 5, 0);
794 if (!mmio_base) {
795 rc = -ENOMEM;
796 goto err_out_free_ent;
797 }
798
799 base = (unsigned long) mmio_base;
800
801 probe_ent->sht = pdc2027x_port_info[board_idx].sht;
802 probe_ent->port_flags = pdc2027x_port_info[board_idx].flags;
803 probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask;
804 probe_ent->mwdma_mask = pdc2027x_port_info[board_idx].mwdma_mask;
805 probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask;
806 probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops;
807
808 probe_ent->irq = pdev->irq;
809 probe_ent->irq_flags = SA_SHIRQ;
810 probe_ent->mmio_base = mmio_base;
811
812 pdc_ata_setup_port(&probe_ent->port[0], base + 0x17c0);
813 probe_ent->port[0].bmdma_addr = base + 0x1000;
814 pdc_ata_setup_port(&probe_ent->port[1], base + 0x15c0);
815 probe_ent->port[1].bmdma_addr = base + 0x1008;
816
817 probe_ent->n_ports = 2;
818
819 pci_set_master(pdev);
820 //pci_enable_intx(pdev);
821
822 /* initialize adapter */
823 if (pdc_hardware_init(pdev, probe_ent, board_idx) != 0)
824 goto err_out_free_ent;
825
826 ata_device_add(probe_ent);
827 kfree(probe_ent);
828
829 return 0;
830
831err_out_free_ent:
832 kfree(probe_ent);
833err_out_regions:
834 pci_release_regions(pdev);
835err_out:
836 pci_disable_device(pdev);
837 return rc;
838}
839
840/**
841 * pdc2027x_remove_one - Called to remove a single instance of the
842 * adapter.
843 *
844 * @dev: The PCI device to remove.
845 * FIXME: module load/unload not working yet
846 */
847static void __devexit pdc2027x_remove_one(struct pci_dev *pdev)
848{
849 ata_pci_remove_one(pdev);
850}
851
852/**
853 * pdc2027x_init - Called after this module is loaded into the kernel.
854 */
855static int __init pdc2027x_init(void)
856{
857 return pci_module_init(&pdc2027x_pci_driver);
858}
859
860/**
861 * pdc2027x_exit - Called before this module unloaded from the kernel
862 */
863static void __exit pdc2027x_exit(void)
864{
865 pci_unregister_driver(&pdc2027x_pci_driver);
866}
867
868module_init(pdc2027x_init);
869module_exit(pdc2027x_exit);
diff --git a/drivers/ata/pata_pdc202xx_old.c b/drivers/ata/pata_pdc202xx_old.c
new file mode 100644
index 00000000000..6cb52b0e769
--- /dev/null
+++ b/drivers/ata/pata_pdc202xx_old.c
@@ -0,0 +1,423 @@
1/*
2 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
7 *
8 * First cut with LBA48/ATAPI
9 *
10 * TODO:
11 * Channel interlock/reset on both required ?
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/pci.h>
17#include <linux/init.h>
18#include <linux/blkdev.h>
19#include <linux/delay.h>
20#include <scsi/scsi_host.h>
21#include <linux/libata.h>
22
23#define DRV_NAME "pata_pdc202xx_old"
24#define DRV_VERSION "0.2.1"
25
26/**
27 * pdc2024x_pre_reset - probe begin
28 * @ap: ATA port
29 *
30 * Set up cable type and use generic probe init
31 */
32
33static int pdc2024x_pre_reset(struct ata_port *ap)
34{
35 ap->cbl = ATA_CBL_PATA40;
36 return ata_std_prereset(ap);
37}
38
39
40static void pdc2024x_error_handler(struct ata_port *ap)
41{
42 ata_bmdma_drive_eh(ap, pdc2024x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
43}
44
45
46static int pdc2026x_pre_reset(struct ata_port *ap)
47{
48 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
49 u16 cis;
50
51 pci_read_config_word(pdev, 0x50, &cis);
52 if (cis & (1 << (10 + ap->port_no)))
53 ap->cbl = ATA_CBL_PATA80;
54 else
55 ap->cbl = ATA_CBL_PATA40;
56
57 return ata_std_prereset(ap);
58}
59
60static void pdc2026x_error_handler(struct ata_port *ap)
61{
62 ata_bmdma_drive_eh(ap, pdc2026x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
63}
64
65/**
66 * pdc_configure_piomode - set chip PIO timing
67 * @ap: ATA interface
68 * @adev: ATA device
69 * @pio: PIO mode
70 *
71 * Called to do the PIO mode setup. Our timing registers are shared
72 * so a configure_dmamode call will undo any work we do here and vice
73 * versa
74 */
75
76static void pdc_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
77{
78 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
79 int port = 0x60 + 4 * ap->port_no + 2 * adev->devno;
80 static u16 pio_timing[5] = {
81 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
82 };
83 u8 r_ap, r_bp;
84
85 pci_read_config_byte(pdev, port, &r_ap);
86 pci_read_config_byte(pdev, port + 1, &r_bp);
87 r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
88 r_bp &= ~0x07;
89 r_ap |= (pio_timing[pio] >> 8);
90 r_bp |= (pio_timing[pio] & 0xFF);
91
92 if (ata_pio_need_iordy(adev))
93 r_ap |= 0x20; /* IORDY enable */
94 if (adev->class == ATA_DEV_ATA)
95 r_ap |= 0x10; /* FIFO enable */
96 pci_write_config_byte(pdev, port, r_ap);
97 pci_write_config_byte(pdev, port + 1, r_bp);
98}
99
100/**
101 * pdc_set_piomode - set initial PIO mode data
102 * @ap: ATA interface
103 * @adev: ATA device
104 *
105 * Called to do the PIO mode setup. Our timing registers are shared
106 * but we want to set the PIO timing by default.
107 */
108
109static void pdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
110{
111 pdc_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
112}
113
114/**
115 * pdc_configure_dmamode - set DMA mode in chip
116 * @ap: ATA interface
117 * @adev: ATA device
118 *
119 * Load DMA cycle times into the chip ready for a DMA transfer
120 * to occur.
121 */
122
123static void pdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
124{
125 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
126 int port = 0x60 + 4 * ap->port_no + 2 * adev->devno;
127 static u8 udma_timing[6][2] = {
128 { 0x60, 0x03 }, /* 33 Mhz Clock */
129 { 0x40, 0x02 },
130 { 0x20, 0x01 },
131 { 0x40, 0x02 }, /* 66 Mhz Clock */
132 { 0x20, 0x01 },
133 { 0x20, 0x01 }
134 };
135 u8 r_bp, r_cp;
136
137 pci_read_config_byte(pdev, port + 1, &r_bp);
138 pci_read_config_byte(pdev, port + 2, &r_cp);
139
140 r_bp &= ~0xF0;
141 r_cp &= ~0x0F;
142
143 if (adev->dma_mode >= XFER_UDMA_0) {
144 int speed = adev->dma_mode - XFER_UDMA_0;
145 r_bp |= udma_timing[speed][0];
146 r_cp |= udma_timing[speed][1];
147
148 } else {
149 int speed = adev->dma_mode - XFER_MW_DMA_0;
150 r_bp |= 0x60;
151 r_cp |= (5 - speed);
152 }
153 pci_write_config_byte(pdev, port + 1, r_bp);
154 pci_write_config_byte(pdev, port + 2, r_cp);
155
156}
157
158/**
159 * pdc2026x_bmdma_start - DMA engine begin
160 * @qc: ATA command
161 *
162 * In UDMA3 or higher we have to clock switch for the duration of the
163 * DMA transfer sequence.
164 */
165
166static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
167{
168 struct ata_port *ap = qc->ap;
169 struct ata_device *adev = qc->dev;
170 struct ata_taskfile *tf = &qc->tf;
171 int sel66 = ap->port_no ? 0x08: 0x02;
172
173 unsigned long master = ap->host->ports[0]->ioaddr.bmdma_addr;
174 unsigned long clock = master + 0x11;
175 unsigned long atapi_reg = master + 0x20 + (4 * ap->port_no);
176
177 u32 len;
178
179 /* Check we keep host level locking here */
180 if (adev->dma_mode >= XFER_UDMA_2)
181 outb(inb(clock) | sel66, clock);
182 else
183 outb(inb(clock) & ~sel66, clock);
184
185 /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
186 and move to qc_issue ? */
187 pdc_set_dmamode(ap, qc->dev);
188
189 /* Cases the state machine will not complete correctly without help */
190 if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATA_PROT_ATAPI_DMA)
191 {
192 if (tf->flags & ATA_TFLAG_LBA48)
193 len = qc->nsect * 512;
194 else
195 len = qc->nbytes;
196
197 if (tf->flags & ATA_TFLAG_WRITE)
198 len |= 0x06000000;
199 else
200 len |= 0x05000000;
201
202 outl(len, atapi_reg);
203 }
204
205 /* Activate DMA */
206 ata_bmdma_start(qc);
207}
208
209/**
210 * pdc2026x_bmdma_end - DMA engine stop
211 * @qc: ATA command
212 *
213 * After a DMA completes we need to put the clock back to 33MHz for
214 * PIO timings.
215 */
216
217static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
218{
219 struct ata_port *ap = qc->ap;
220 struct ata_device *adev = qc->dev;
221 struct ata_taskfile *tf = &qc->tf;
222
223 int sel66 = ap->port_no ? 0x08: 0x02;
224 /* The clock bits are in the same register for both channels */
225 unsigned long master = ap->host->ports[0]->ioaddr.bmdma_addr;
226 unsigned long clock = master + 0x11;
227 unsigned long atapi_reg = master + 0x20 + (4 * ap->port_no);
228
229 /* Cases the state machine will not complete correctly */
230 if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
231 outl(0, atapi_reg);
232 outb(inb(clock) & ~sel66, clock);
233 }
234 /* Check we keep host level locking here */
235 /* Flip back to 33Mhz for PIO */
236 if (adev->dma_mode >= XFER_UDMA_2)
237 outb(inb(clock) & ~sel66, clock);
238
239 ata_bmdma_stop(qc);
240}
241
242/**
243 * pdc2026x_dev_config - device setup hook
244 * @ap: ATA port
245 * @adev: newly found device
246 *
247 * Perform chip specific early setup. We need to lock the transfer
248 * sizes to 8bit to avoid making the state engine on the 2026x cards
249 * barf.
250 */
251
252static void pdc2026x_dev_config(struct ata_port *ap, struct ata_device *adev)
253{
254 adev->max_sectors = 256;
255}
256
257static struct scsi_host_template pdc_sht = {
258 .module = THIS_MODULE,
259 .name = DRV_NAME,
260 .ioctl = ata_scsi_ioctl,
261 .queuecommand = ata_scsi_queuecmd,
262 .can_queue = ATA_DEF_QUEUE,
263 .this_id = ATA_SHT_THIS_ID,
264 .sg_tablesize = LIBATA_MAX_PRD,
265 .max_sectors = ATA_MAX_SECTORS,
266 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
267 .emulated = ATA_SHT_EMULATED,
268 .use_clustering = ATA_SHT_USE_CLUSTERING,
269 .proc_name = DRV_NAME,
270 .dma_boundary = ATA_DMA_BOUNDARY,
271 .slave_configure = ata_scsi_slave_config,
272 .bios_param = ata_std_bios_param,
273};
274
275static struct ata_port_operations pdc2024x_port_ops = {
276 .port_disable = ata_port_disable,
277 .set_piomode = pdc_set_piomode,
278 .set_dmamode = pdc_set_dmamode,
279 .mode_filter = ata_pci_default_filter,
280 .tf_load = ata_tf_load,
281 .tf_read = ata_tf_read,
282 .check_status = ata_check_status,
283 .exec_command = ata_exec_command,
284 .dev_select = ata_std_dev_select,
285
286 .freeze = ata_bmdma_freeze,
287 .thaw = ata_bmdma_thaw,
288 .error_handler = pdc2024x_error_handler,
289 .post_internal_cmd = ata_bmdma_post_internal_cmd,
290
291 .bmdma_setup = ata_bmdma_setup,
292 .bmdma_start = ata_bmdma_start,
293 .bmdma_stop = ata_bmdma_stop,
294 .bmdma_status = ata_bmdma_status,
295
296 .qc_prep = ata_qc_prep,
297 .qc_issue = ata_qc_issue_prot,
298 .data_xfer = ata_pio_data_xfer,
299
300 .irq_handler = ata_interrupt,
301 .irq_clear = ata_bmdma_irq_clear,
302
303 .port_start = ata_port_start,
304 .port_stop = ata_port_stop,
305 .host_stop = ata_host_stop
306};
307
308static struct ata_port_operations pdc2026x_port_ops = {
309 .port_disable = ata_port_disable,
310 .set_piomode = pdc_set_piomode,
311 .set_dmamode = pdc_set_dmamode,
312 .mode_filter = ata_pci_default_filter,
313 .tf_load = ata_tf_load,
314 .tf_read = ata_tf_read,
315 .check_status = ata_check_status,
316 .exec_command = ata_exec_command,
317 .dev_select = ata_std_dev_select,
318 .dev_config = pdc2026x_dev_config,
319
320 .freeze = ata_bmdma_freeze,
321 .thaw = ata_bmdma_thaw,
322 .error_handler = pdc2026x_error_handler,
323 .post_internal_cmd = ata_bmdma_post_internal_cmd,
324
325 .bmdma_setup = ata_bmdma_setup,
326 .bmdma_start = pdc2026x_bmdma_start,
327 .bmdma_stop = pdc2026x_bmdma_stop,
328 .bmdma_status = ata_bmdma_status,
329
330 .qc_prep = ata_qc_prep,
331 .qc_issue = ata_qc_issue_prot,
332 .data_xfer = ata_pio_data_xfer,
333
334 .irq_handler = ata_interrupt,
335 .irq_clear = ata_bmdma_irq_clear,
336
337 .port_start = ata_port_start,
338 .port_stop = ata_port_stop,
339 .host_stop = ata_host_stop
340};
341
342static int pdc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
343{
344 static struct ata_port_info info[3] = {
345 {
346 .sht = &pdc_sht,
347 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
348 .pio_mask = 0x1f,
349 .mwdma_mask = 0x07,
350 .udma_mask = ATA_UDMA2,
351 .port_ops = &pdc2024x_port_ops
352 },
353 {
354 .sht = &pdc_sht,
355 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
356 .pio_mask = 0x1f,
357 .mwdma_mask = 0x07,
358 .udma_mask = ATA_UDMA4,
359 .port_ops = &pdc2026x_port_ops
360 },
361 {
362 .sht = &pdc_sht,
363 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
364 .pio_mask = 0x1f,
365 .mwdma_mask = 0x07,
366 .udma_mask = ATA_UDMA5,
367 .port_ops = &pdc2026x_port_ops
368 }
369
370 };
371 static struct ata_port_info *port_info[2];
372
373 port_info[0] = port_info[1] = &info[id->driver_data];
374
375 if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
376 struct pci_dev *bridge = dev->bus->self;
377 /* Don't grab anything behind a Promise I2O RAID */
378 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
379 if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
380 return -ENODEV;
381 if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
382 return -ENODEV;
383 }
384 }
385 return ata_pci_init_one(dev, port_info, 2);
386}
387
388static struct pci_device_id pdc[] = {
389 { PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0},
390 { PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1},
391 { PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1},
392 { PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2},
393 { PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2},
394 { 0, },
395};
396
397static struct pci_driver pdc_pci_driver = {
398 .name = DRV_NAME,
399 .id_table = pdc,
400 .probe = pdc_init_one,
401 .remove = ata_pci_remove_one
402};
403
404static int __init pdc_init(void)
405{
406 return pci_register_driver(&pdc_pci_driver);
407}
408
409
410static void __exit pdc_exit(void)
411{
412 pci_unregister_driver(&pdc_pci_driver);
413}
414
415
416MODULE_AUTHOR("Alan Cox");
417MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
418MODULE_LICENSE("GPL");
419MODULE_DEVICE_TABLE(pci, pdc);
420MODULE_VERSION(DRV_VERSION);
421
422module_init(pdc_init);
423module_exit(pdc_exit);
diff --git a/drivers/ata/pata_qdi.c b/drivers/ata/pata_qdi.c
new file mode 100644
index 00000000000..ededb40e084
--- /dev/null
+++ b/drivers/ata/pata_qdi.c
@@ -0,0 +1,403 @@
1/*
2 * pata_qdi.c - QDI VLB ATA controllers
3 * (C) 2006 Red Hat <alan@redhat.com>
4 *
5 * This driver mostly exists as a proof of concept for non PCI devices under
6 * libata. While the QDI6580 was 'neat' in 1993 it is no longer terribly
7 * useful.
8 *
9 * Tuning code written from the documentation at
10 * http://www.ryston.cz/petr/vlb/qd6500.html
11 * http://www.ryston.cz/petr/vlb/qd6580.html
12 *
13 * Probe code based on drivers/ide/legacy/qd65xx.c
14 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
15 * Samuel Thibault <samuel.thibault@fnac.net>
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26#include <linux/platform_device.h>
27
28#define DRV_NAME "pata_qdi"
29#define DRV_VERSION "0.2.4"
30
31#define NR_HOST 4 /* Two 6580s */
32
33struct qdi_data {
34 unsigned long timing;
35 u8 clock[2];
36 u8 last;
37 int fast;
38 struct platform_device *platform_dev;
39
40};
41
42static struct ata_host *qdi_host[NR_HOST];
43static struct qdi_data qdi_data[NR_HOST];
44static int nr_qdi_host;
45
46#ifdef MODULE
47static int probe_qdi = 1;
48#else
49static int probe_qdi;
50#endif
51
52static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
53{
54 struct ata_timing t;
55 struct qdi_data *qdi = ap->host->private_data;
56 int active, recovery;
57 u8 timing;
58
59 /* Get the timing data in cycles */
60 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
61
62 if (qdi->fast) {
63 active = 8 - FIT(t.active, 1, 8);
64 recovery = 18 - FIT(t.recover, 3, 18);
65 } else {
66 active = 9 - FIT(t.active, 2, 9);
67 recovery = 15 - FIT(t.recover, 0, 15);
68 }
69 timing = (recovery << 4) | active | 0x08;
70
71 qdi->clock[adev->devno] = timing;
72
73 outb(timing, qdi->timing);
74}
75
76static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
77{
78 struct ata_timing t;
79 struct qdi_data *qdi = ap->host->private_data;
80 int active, recovery;
81 u8 timing;
82
83 /* Get the timing data in cycles */
84 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
85
86 if (qdi->fast) {
87 active = 8 - FIT(t.active, 1, 8);
88 recovery = 18 - FIT(t.recover, 3, 18);
89 } else {
90 active = 9 - FIT(t.active, 2, 9);
91 recovery = 15 - FIT(t.recover, 0, 15);
92 }
93 timing = (recovery << 4) | active | 0x08;
94
95 qdi->clock[adev->devno] = timing;
96
97 outb(timing, qdi->timing);
98
99 /* Clear the FIFO */
100 if (adev->class != ATA_DEV_ATA)
101 outb(0x5F, (qdi->timing & 0xFFF0) + 3);
102}
103
104/**
105 * qdi_qc_issue_prot - command issue
106 * @qc: command pending
107 *
108 * Called when the libata layer is about to issue a command. We wrap
109 * this interface so that we can load the correct ATA timings.
110 */
111
112static unsigned int qdi_qc_issue_prot(struct ata_queued_cmd *qc)
113{
114 struct ata_port *ap = qc->ap;
115 struct ata_device *adev = qc->dev;
116 struct qdi_data *qdi = ap->host->private_data;
117
118 if (qdi->clock[adev->devno] != qdi->last) {
119 if (adev->pio_mode) {
120 qdi->last = qdi->clock[adev->devno];
121 outb(qdi->clock[adev->devno], qdi->timing);
122 }
123 }
124 return ata_qc_issue_prot(qc);
125}
126
127static void qdi_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
128{
129 struct ata_port *ap = adev->ap;
130 int slop = buflen & 3;
131
132 if (ata_id_has_dword_io(adev->id)) {
133 if (write_data)
134 outsl(ap->ioaddr.data_addr, buf, buflen >> 2);
135 else
136 insl(ap->ioaddr.data_addr, buf, buflen >> 2);
137
138 if (unlikely(slop)) {
139 u32 pad;
140 if (write_data) {
141 memcpy(&pad, buf + buflen - slop, slop);
142 outl(le32_to_cpu(pad), ap->ioaddr.data_addr);
143 } else {
144 pad = cpu_to_le16(inl(ap->ioaddr.data_addr));
145 memcpy(buf + buflen - slop, &pad, slop);
146 }
147 }
148 } else
149 ata_pio_data_xfer(adev, buf, buflen, write_data);
150}
151
152static struct scsi_host_template qdi_sht = {
153 .module = THIS_MODULE,
154 .name = DRV_NAME,
155 .ioctl = ata_scsi_ioctl,
156 .queuecommand = ata_scsi_queuecmd,
157 .can_queue = ATA_DEF_QUEUE,
158 .this_id = ATA_SHT_THIS_ID,
159 .sg_tablesize = LIBATA_MAX_PRD,
160 .max_sectors = ATA_MAX_SECTORS,
161 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
162 .emulated = ATA_SHT_EMULATED,
163 .use_clustering = ATA_SHT_USE_CLUSTERING,
164 .proc_name = DRV_NAME,
165 .dma_boundary = ATA_DMA_BOUNDARY,
166 .slave_configure = ata_scsi_slave_config,
167 .bios_param = ata_std_bios_param,
168};
169
170static struct ata_port_operations qdi6500_port_ops = {
171 .port_disable = ata_port_disable,
172 .set_piomode = qdi6500_set_piomode,
173
174 .tf_load = ata_tf_load,
175 .tf_read = ata_tf_read,
176 .check_status = ata_check_status,
177 .exec_command = ata_exec_command,
178 .dev_select = ata_std_dev_select,
179
180 .freeze = ata_bmdma_freeze,
181 .thaw = ata_bmdma_thaw,
182 .error_handler = ata_bmdma_error_handler,
183 .post_internal_cmd = ata_bmdma_post_internal_cmd,
184
185 .qc_prep = ata_qc_prep,
186 .qc_issue = qdi_qc_issue_prot,
187 .eng_timeout = ata_eng_timeout,
188 .data_xfer = qdi_data_xfer,
189
190 .irq_handler = ata_interrupt,
191 .irq_clear = ata_bmdma_irq_clear,
192
193 .port_start = ata_port_start,
194 .port_stop = ata_port_stop,
195 .host_stop = ata_host_stop
196};
197
198static struct ata_port_operations qdi6580_port_ops = {
199 .port_disable = ata_port_disable,
200 .set_piomode = qdi6580_set_piomode,
201
202 .tf_load = ata_tf_load,
203 .tf_read = ata_tf_read,
204 .check_status = ata_check_status,
205 .exec_command = ata_exec_command,
206 .dev_select = ata_std_dev_select,
207
208 .freeze = ata_bmdma_freeze,
209 .thaw = ata_bmdma_thaw,
210 .error_handler = ata_bmdma_error_handler,
211 .post_internal_cmd = ata_bmdma_post_internal_cmd,
212
213 .qc_prep = ata_qc_prep,
214 .qc_issue = qdi_qc_issue_prot,
215 .eng_timeout = ata_eng_timeout,
216 .data_xfer = qdi_data_xfer,
217
218 .irq_handler = ata_interrupt,
219 .irq_clear = ata_bmdma_irq_clear,
220
221 .port_start = ata_port_start,
222 .port_stop = ata_port_stop,
223 .host_stop = ata_host_stop
224};
225
226/**
227 * qdi_init_one - attach a qdi interface
228 * @type: Type to display
229 * @io: I/O port start
230 * @irq: interrupt line
231 * @fast: True if on a > 33Mhz VLB
232 *
233 * Register an ISA bus IDE interface. Such interfaces are PIO and we
234 * assume do not support IRQ sharing.
235 */
236
237static __init int qdi_init_one(unsigned long port, int type, unsigned long io, int irq, int fast)
238{
239 struct ata_probe_ent ae;
240 struct platform_device *pdev;
241 int ret;
242
243 unsigned long ctrl = io + 0x206;
244
245 /*
246 * Fill in a probe structure first of all
247 */
248
249 pdev = platform_device_register_simple(DRV_NAME, nr_qdi_host, NULL, 0);
250 if (pdev == NULL)
251 return -ENOMEM;
252
253 memset(&ae, 0, sizeof(struct ata_probe_ent));
254 INIT_LIST_HEAD(&ae.node);
255 ae.dev = &pdev->dev;
256
257 if (type == 6580) {
258 ae.port_ops = &qdi6580_port_ops;
259 ae.pio_mask = 0x1F;
260 } else {
261 ae.port_ops = &qdi6500_port_ops;
262 ae.pio_mask = 0x07; /* Actually PIO3 !IORDY is possible */
263 }
264
265 ae.sht = &qdi_sht;
266 ae.n_ports = 1;
267 ae.irq = irq;
268 ae.irq_flags = 0;
269 ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
270 ae.port[0].cmd_addr = io;
271 ae.port[0].altstatus_addr = ctrl;
272 ae.port[0].ctl_addr = ctrl;
273 ata_std_ports(&ae.port[0]);
274
275 /*
276 * Hook in a private data structure per channel
277 */
278 ae.private_data = &qdi_data[nr_qdi_host];
279
280 qdi_data[nr_qdi_host].timing = port;
281 qdi_data[nr_qdi_host].fast = fast;
282 qdi_data[nr_qdi_host].platform_dev = pdev;
283
284 printk(KERN_INFO DRV_NAME": qd%d at 0x%lx.\n", type, io);
285 ret = ata_device_add(&ae);
286 if (ret == 0) {
287 platform_device_unregister(pdev);
288 return -ENODEV;
289 }
290
291 qdi_host[nr_qdi_host++] = dev_get_drvdata(&pdev->dev);
292 return 0;
293}
294
295/**
296 * qdi_init - attach qdi interfaces
297 *
298 * Attach qdi IDE interfaces by scanning the ports it may occupy.
299 */
300
301static __init int qdi_init(void)
302{
303 unsigned long flags;
304 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
305 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
306 static const int ide_irq[2] = { 14, 15 };
307
308 int ct = 0;
309 int i;
310
311 if (probe_qdi == 0)
312 return -ENODEV;
313
314 /*
315 * Check each possible QD65xx base address
316 */
317
318 for (i = 0; i < 2; i++) {
319 unsigned long port = qd_port[i];
320 u8 r, res;
321
322
323 if (request_region(port, 2, "pata_qdi")) {
324 /* Check for a card */
325 local_irq_save(flags);
326 r = inb_p(port);
327 outb_p(0x19, port);
328 res = inb_p(port);
329 outb_p(r, port);
330 local_irq_restore(flags);
331
332 /* Fail */
333 if (res == 0x19)
334 {
335 release_region(port, 2);
336 continue;
337 }
338
339 /* Passes the presence test */
340 r = inb_p(port + 1); /* Check port agrees with port set */
341 if ((r & 2) >> 1 != i) {
342 release_region(port, 2);
343 continue;
344 }
345
346 /* Check card type */
347 if ((r & 0xF0) == 0xC0) {
348 /* QD6500: single channel */
349 if (r & 8) {
350 /* Disabled ? */
351 release_region(port, 2);
352 continue;
353 }
354 ct += qdi_init_one(port, 6500, ide_port[r & 0x01], ide_irq[r & 0x01], r & 0x04);
355 }
356 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
357 /* QD6580: dual channel */
358 if (!request_region(port + 2 , 2, "pata_qdi"))
359 {
360 release_region(port, 2);
361 continue;
362 }
363 res = inb(port + 3);
364 if (res & 1) {
365 /* Single channel mode */
366 ct += qdi_init_one(port, 6580, ide_port[r & 0x01], ide_irq[r & 0x01], r & 0x04);
367 } else {
368 /* Dual channel mode */
369 ct += qdi_init_one(port, 6580, 0x1F0, 14, r & 0x04);
370 ct += qdi_init_one(port + 2, 6580, 0x170, 15, r & 0x04);
371 }
372 }
373 }
374 }
375 if (ct != 0)
376 return 0;
377 return -ENODEV;
378}
379
380static __exit void qdi_exit(void)
381{
382 int i;
383
384 for (i = 0; i < nr_qdi_host; i++) {
385 ata_host_remove(qdi_host[i]);
386 /* Free the control resource. The 6580 dual channel has the resources
387 * claimed as a pair of 2 byte resources so we need no special cases...
388 */
389 release_region(qdi_data[i].timing, 2);
390 platform_device_unregister(qdi_data[i].platform_dev);
391 }
392}
393
394MODULE_AUTHOR("Alan Cox");
395MODULE_DESCRIPTION("low-level driver for qdi ATA");
396MODULE_LICENSE("GPL");
397MODULE_VERSION(DRV_VERSION);
398
399module_init(qdi_init);
400module_exit(qdi_exit);
401
402module_param(probe_qdi, int, 0);
403
diff --git a/drivers/ata/pata_radisys.c b/drivers/ata/pata_radisys.c
new file mode 100644
index 00000000000..6f7d0527265
--- /dev/null
+++ b/drivers/ata/pata_radisys.c
@@ -0,0 +1,335 @@
1/*
2 * pata_radisys.c - Intel PATA/SATA controllers
3 *
4 * (C) 2006 Red Hat <alan@redhat.com>
5 *
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
7 *
8 * A PIIX relative, this device has a single ATA channel and no
9 * slave timings, SITRE or PPE. In that sense it is a close relative
10 * of the original PIIX. It does however support UDMA 33/66 per channel
11 * although no other modes/timings. Also lacking is 32bit I/O on the ATA
12 * port.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/blkdev.h>
20#include <linux/delay.h>
21#include <linux/device.h>
22#include <scsi/scsi_host.h>
23#include <linux/libata.h>
24#include <linux/ata.h>
25
26#define DRV_NAME "pata_radisys"
27#define DRV_VERSION "0.4.1"
28
29/**
30 * radisys_probe_init - probe begin
31 * @ap: ATA port
32 *
33 * Set up cable type and use generic probe init
34 */
35
36static int radisys_pre_reset(struct ata_port *ap)
37{
38 ap->cbl = ATA_CBL_PATA80;
39 return ata_std_prereset(ap);
40}
41
42
43/**
44 * radisys_pata_error_handler - Probe specified port on PATA host controller
45 * @ap: Port to probe
46 * @classes:
47 *
48 * LOCKING:
49 * None (inherited from caller).
50 */
51
52static void radisys_pata_error_handler(struct ata_port *ap)
53{
54 ata_bmdma_drive_eh(ap, radisys_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
55}
56
57/**
58 * radisys_set_piomode - Initialize host controller PATA PIO timings
59 * @ap: Port whose timings we are configuring
60 * @adev: um
61 *
62 * Set PIO mode for device, in host controller PCI config space.
63 *
64 * LOCKING:
65 * None (inherited from caller).
66 */
67
68static void radisys_set_piomode (struct ata_port *ap, struct ata_device *adev)
69{
70 unsigned int pio = adev->pio_mode - XFER_PIO_0;
71 struct pci_dev *dev = to_pci_dev(ap->host->dev);
72 u16 idetm_data;
73 int control = 0;
74
75 /*
76 * See Intel Document 298600-004 for the timing programing rules
77 * for PIIX/ICH. Note that the early PIIX does not have the slave
78 * timing port at 0x44. The Radisys is a relative of the PIIX
79 * but not the same so be careful.
80 */
81
82 static const /* ISP RTC */
83 u8 timings[][2] = { { 0, 0 }, /* Check me */
84 { 0, 0 },
85 { 1, 1 },
86 { 2, 2 },
87 { 3, 3 }, };
88
89 if (pio > 0)
90 control |= 1; /* TIME1 enable */
91 if (ata_pio_need_iordy(adev))
92 control |= 2; /* IE IORDY */
93
94 pci_read_config_word(dev, 0x40, &idetm_data);
95
96 /* Enable IE and TIME as appropriate. Clear the other
97 drive timing bits */
98 idetm_data &= 0xCCCC;
99 idetm_data |= (control << (4 * adev->devno));
100 idetm_data |= (timings[pio][0] << 12) |
101 (timings[pio][1] << 8);
102 pci_write_config_word(dev, 0x40, idetm_data);
103
104 /* Track which port is configured */
105 ap->private_data = adev;
106}
107
108/**
109 * radisys_set_dmamode - Initialize host controller PATA DMA timings
110 * @ap: Port whose timings we are configuring
111 * @adev: Device to program
112 * @isich: True if the device is an ICH and has IOCFG registers
113 *
114 * Set MWDMA mode for device, in host controller PCI config space.
115 *
116 * LOCKING:
117 * None (inherited from caller).
118 */
119
120static void radisys_set_dmamode (struct ata_port *ap, struct ata_device *adev)
121{
122 struct pci_dev *dev = to_pci_dev(ap->host->dev);
123 u16 idetm_data;
124 u8 udma_enable;
125
126 static const /* ISP RTC */
127 u8 timings[][2] = { { 0, 0 },
128 { 0, 0 },
129 { 1, 1 },
130 { 2, 2 },
131 { 3, 3 }, };
132
133 /*
134 * MWDMA is driven by the PIO timings. We must also enable
135 * IORDY unconditionally.
136 */
137
138 pci_read_config_word(dev, 0x40, &idetm_data);
139 pci_read_config_byte(dev, 0x48, &udma_enable);
140
141 if (adev->dma_mode < XFER_UDMA_0) {
142 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
143 const unsigned int needed_pio[3] = {
144 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
145 };
146 int pio = needed_pio[mwdma] - XFER_PIO_0;
147 int control = 3; /* IORDY|TIME0 */
148
149 /* If the drive MWDMA is faster than it can do PIO then
150 we must force PIO0 for PIO cycles. */
151
152 if (adev->pio_mode < needed_pio[mwdma])
153 control = 1;
154
155 /* Mask out the relevant control and timing bits we will load. Also
156 clear the other drive TIME register as a precaution */
157
158 idetm_data &= 0xCCCC;
159 idetm_data |= control << (4 * adev->devno);
160 idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
161
162 udma_enable &= ~(1 << adev->devno);
163 } else {
164 u8 udma_mode;
165
166 /* UDMA66 on: UDMA 33 and 66 are switchable via register 0x4A */
167
168 pci_read_config_byte(dev, 0x4A, &udma_mode);
169
170 if (adev->xfer_mode == XFER_UDMA_2)
171 udma_mode &= ~ (1 << adev->devno);
172 else /* UDMA 4 */
173 udma_mode |= (1 << adev->devno);
174
175 pci_write_config_byte(dev, 0x4A, udma_mode);
176
177 udma_enable |= (1 << adev->devno);
178 }
179 pci_write_config_word(dev, 0x40, idetm_data);
180 pci_write_config_byte(dev, 0x48, udma_enable);
181
182 /* Track which port is configured */
183 ap->private_data = adev;
184}
185
186/**
187 * radisys_qc_issue_prot - command issue
188 * @qc: command pending
189 *
190 * Called when the libata layer is about to issue a command. We wrap
191 * this interface so that we can load the correct ATA timings if
192 * neccessary. Our logic also clears TIME0/TIME1 for the other device so
193 * that, even if we get this wrong, cycles to the other device will
194 * be made PIO0.
195 */
196
197static unsigned int radisys_qc_issue_prot(struct ata_queued_cmd *qc)
198{
199 struct ata_port *ap = qc->ap;
200 struct ata_device *adev = qc->dev;
201
202 if (adev != ap->private_data) {
203 /* UDMA timing is not shared */
204 if (adev->dma_mode < XFER_UDMA_0) {
205 if (adev->dma_mode)
206 radisys_set_dmamode(ap, adev);
207 else if (adev->pio_mode)
208 radisys_set_piomode(ap, adev);
209 }
210 }
211 return ata_qc_issue_prot(qc);
212}
213
214
215static struct scsi_host_template radisys_sht = {
216 .module = THIS_MODULE,
217 .name = DRV_NAME,
218 .ioctl = ata_scsi_ioctl,
219 .queuecommand = ata_scsi_queuecmd,
220 .can_queue = ATA_DEF_QUEUE,
221 .this_id = ATA_SHT_THIS_ID,
222 .sg_tablesize = LIBATA_MAX_PRD,
223 .max_sectors = ATA_MAX_SECTORS,
224 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
225 .emulated = ATA_SHT_EMULATED,
226 .use_clustering = ATA_SHT_USE_CLUSTERING,
227 .proc_name = DRV_NAME,
228 .dma_boundary = ATA_DMA_BOUNDARY,
229 .slave_configure = ata_scsi_slave_config,
230 .bios_param = ata_std_bios_param,
231};
232
233static const struct ata_port_operations radisys_pata_ops = {
234 .port_disable = ata_port_disable,
235 .set_piomode = radisys_set_piomode,
236 .set_dmamode = radisys_set_dmamode,
237 .mode_filter = ata_pci_default_filter,
238
239 .tf_load = ata_tf_load,
240 .tf_read = ata_tf_read,
241 .check_status = ata_check_status,
242 .exec_command = ata_exec_command,
243 .dev_select = ata_std_dev_select,
244
245 .freeze = ata_bmdma_freeze,
246 .thaw = ata_bmdma_thaw,
247 .error_handler = radisys_pata_error_handler,
248 .post_internal_cmd = ata_bmdma_post_internal_cmd,
249
250 .bmdma_setup = ata_bmdma_setup,
251 .bmdma_start = ata_bmdma_start,
252 .bmdma_stop = ata_bmdma_stop,
253 .bmdma_status = ata_bmdma_status,
254 .qc_prep = ata_qc_prep,
255 .qc_issue = radisys_qc_issue_prot,
256 .data_xfer = ata_pio_data_xfer,
257
258 .eng_timeout = ata_eng_timeout,
259
260 .irq_handler = ata_interrupt,
261 .irq_clear = ata_bmdma_irq_clear,
262
263 .port_start = ata_port_start,
264 .port_stop = ata_port_stop,
265 .host_stop = ata_host_stop,
266};
267
268
269/**
270 * radisys_init_one - Register PIIX ATA PCI device with kernel services
271 * @pdev: PCI device to register
272 * @ent: Entry in radisys_pci_tbl matching with @pdev
273 *
274 * Called from kernel PCI layer. We probe for combined mode (sigh),
275 * and then hand over control to libata, for it to do the rest.
276 *
277 * LOCKING:
278 * Inherited from PCI layer (may sleep).
279 *
280 * RETURNS:
281 * Zero on success, or -ERRNO value.
282 */
283
284static int radisys_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
285{
286 static int printed_version;
287 static struct ata_port_info info = {
288 .sht = &radisys_sht,
289 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
290 .pio_mask = 0x1f, /* pio0-4 */
291 .mwdma_mask = 0x07, /* mwdma1-2 */
292 .udma_mask = 0x14, /* UDMA33/66 only */
293 .port_ops = &radisys_pata_ops,
294 };
295 static struct ata_port_info *port_info[2] = { &info, &info };
296
297 if (!printed_version++)
298 dev_printk(KERN_DEBUG, &pdev->dev,
299 "version " DRV_VERSION "\n");
300
301 return ata_pci_init_one(pdev, port_info, 2);
302}
303
304static const struct pci_device_id radisys_pci_tbl[] = {
305 { 0x1331, 0x8201, PCI_ANY_ID, PCI_ANY_ID, },
306 { } /* terminate list */
307};
308
309static struct pci_driver radisys_pci_driver = {
310 .name = DRV_NAME,
311 .id_table = radisys_pci_tbl,
312 .probe = radisys_init_one,
313 .remove = ata_pci_remove_one,
314};
315
316static int __init radisys_init(void)
317{
318 return pci_register_driver(&radisys_pci_driver);
319}
320
321static void __exit radisys_exit(void)
322{
323 pci_unregister_driver(&radisys_pci_driver);
324}
325
326
327module_init(radisys_init);
328module_exit(radisys_exit);
329
330MODULE_AUTHOR("Alan Cox");
331MODULE_DESCRIPTION("SCSI low-level driver for Radisys R82600 controllers");
332MODULE_LICENSE("GPL");
333MODULE_DEVICE_TABLE(pci, radisys_pci_tbl);
334MODULE_VERSION(DRV_VERSION);
335
diff --git a/drivers/ata/pata_rz1000.c b/drivers/ata/pata_rz1000.c
new file mode 100644
index 00000000000..3c6d84fd431
--- /dev/null
+++ b/drivers/ata/pata_rz1000.c
@@ -0,0 +1,205 @@
1/*
2 * RZ1000/1001 driver based upon
3 *
4 * linux/drivers/ide/pci/rz1000.c Version 0.06 January 12, 2003
5 * Copyright (C) 1995-1998 Linus Torvalds & author (see below)
6 * Principal Author: mlord@pobox.com (Mark Lord)
7 *
8 * See linux/MAINTAINERS for address of current maintainer.
9 *
10 * This file provides support for disabling the buggy read-ahead
11 * mode of the RZ1000 IDE chipset, commonly used on Intel motherboards.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/pci.h>
17#include <linux/init.h>
18#include <linux/blkdev.h>
19#include <linux/delay.h>
20#include <scsi/scsi_host.h>
21#include <linux/libata.h>
22
23#define DRV_NAME "pata_rz1000"
24#define DRV_VERSION "0.2.2"
25
26
27/**
28 * rz1000_prereset - probe begin
29 * @ap: ATA port
30 *
31 * Set up cable type and use generics
32 */
33
34static int rz1000_prereset(struct ata_port *ap)
35{
36 ap->cbl = ATA_CBL_PATA40;
37 return ata_std_prereset(ap);
38}
39
40/**
41 * rz1000_error_handler - probe reset
42 * @ap: ATA port
43 *
44 * Perform the ATA standard reset sequence
45 */
46
47static void rz1000_error_handler(struct ata_port *ap)
48{
49 ata_bmdma_drive_eh(ap, rz1000_prereset, ata_std_softreset, NULL, ata_std_postreset);
50}
51
52/**
53 * rz1000_set_mode - mode setting function
54 * @ap: ATA interface
55 *
56 * Use a non standard set_mode function. We don't want to be tuned. We
57 * would prefer to be BIOS generic but for the fact our hardware is
58 * whacked out.
59 */
60
61static void rz1000_set_mode(struct ata_port *ap)
62{
63 int i;
64
65 for (i = 0; i < ATA_MAX_DEVICES; i++) {
66 struct ata_device *dev = &ap->device[i];
67 if (ata_dev_enabled(dev)) {
68 /* We don't really care */
69 dev->pio_mode = XFER_PIO_0;
70 dev->xfer_mode = XFER_PIO_0;
71 dev->xfer_shift = ATA_SHIFT_PIO;
72 dev->flags |= ATA_DFLAG_PIO;
73 }
74 }
75}
76
77
78static struct scsi_host_template rz1000_sht = {
79 .module = THIS_MODULE,
80 .name = DRV_NAME,
81 .ioctl = ata_scsi_ioctl,
82 .queuecommand = ata_scsi_queuecmd,
83 .can_queue = ATA_DEF_QUEUE,
84 .this_id = ATA_SHT_THIS_ID,
85 .sg_tablesize = LIBATA_MAX_PRD,
86 .max_sectors = ATA_MAX_SECTORS,
87 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
88 .emulated = ATA_SHT_EMULATED,
89 .use_clustering = ATA_SHT_USE_CLUSTERING,
90 .proc_name = DRV_NAME,
91 .dma_boundary = ATA_DMA_BOUNDARY,
92 .slave_configure = ata_scsi_slave_config,
93 .bios_param = ata_std_bios_param,
94};
95
96static struct ata_port_operations rz1000_port_ops = {
97 .set_mode = rz1000_set_mode,
98
99 .port_disable = ata_port_disable,
100 .tf_load = ata_tf_load,
101 .tf_read = ata_tf_read,
102 .check_status = ata_check_status,
103 .exec_command = ata_exec_command,
104 .dev_select = ata_std_dev_select,
105
106 .error_handler = rz1000_error_handler,
107
108 .bmdma_setup = ata_bmdma_setup,
109 .bmdma_start = ata_bmdma_start,
110 .bmdma_stop = ata_bmdma_stop,
111 .bmdma_status = ata_bmdma_status,
112
113 .qc_prep = ata_qc_prep,
114 .qc_issue = ata_qc_issue_prot,
115 .eng_timeout = ata_eng_timeout,
116 .data_xfer = ata_pio_data_xfer,
117
118 .freeze = ata_bmdma_freeze,
119 .thaw = ata_bmdma_thaw,
120 .error_handler = rz1000_error_handler,
121 .post_internal_cmd = ata_bmdma_post_internal_cmd,
122
123 .irq_handler = ata_interrupt,
124 .irq_clear = ata_bmdma_irq_clear,
125
126 .port_start = ata_port_start,
127 .port_stop = ata_port_stop,
128 .host_stop = ata_host_stop
129};
130
131/**
132 * rz1000_init_one - Register RZ1000 ATA PCI device with kernel services
133 * @pdev: PCI device to register
134 * @ent: Entry in rz1000_pci_tbl matching with @pdev
135 *
136 * Configure an RZ1000 interface. This doesn't require much special
137 * handling except that we *MUST* kill the chipset readahead or the
138 * user may experience data corruption.
139 */
140
141static int rz1000_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
142{
143 static int printed_version;
144 struct ata_port_info *port_info[2];
145 u16 reg;
146 static struct ata_port_info info = {
147 .sht = &rz1000_sht,
148 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
149 .pio_mask = 0x1f,
150 .port_ops = &rz1000_port_ops
151 };
152
153 if (!printed_version++)
154 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
155
156 /* Be exceptionally paranoid as we must be sure to apply the fix */
157 if (pci_read_config_word(pdev, 0x40, &reg) != 0)
158 goto fail;
159 reg &= 0xDFFF;
160 if (pci_write_config_word(pdev, 0x40, reg) != 0)
161 goto fail;
162 printk(KERN_INFO DRV_NAME ": disabled chipset readahead.\n");
163
164 port_info[0] = &info;
165 port_info[1] = &info;
166 return ata_pci_init_one(pdev, port_info, 2);
167fail:
168 printk(KERN_ERR DRV_NAME ": failed to disable read-ahead on chipset..\n");
169 /* Not safe to use so skip */
170 return -ENODEV;
171}
172
173static struct pci_device_id pata_rz1000[] = {
174 { PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000), },
175 { PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001), },
176 { 0, },
177};
178
179static struct pci_driver rz1000_pci_driver = {
180 .name = DRV_NAME,
181 .id_table = pata_rz1000,
182 .probe = rz1000_init_one,
183 .remove = ata_pci_remove_one
184};
185
186
187static int __init rz1000_init(void)
188{
189 return pci_register_driver(&rz1000_pci_driver);
190}
191
192static void __exit rz1000_exit(void)
193{
194 pci_unregister_driver(&rz1000_pci_driver);
195}
196
197MODULE_AUTHOR("Alan Cox");
198MODULE_DESCRIPTION("low-level driver for RZ1000 PCI ATA");
199MODULE_LICENSE("GPL");
200MODULE_DEVICE_TABLE(pci, pata_rz1000);
201MODULE_VERSION(DRV_VERSION);
202
203module_init(rz1000_init);
204module_exit(rz1000_exit);
205
diff --git a/drivers/ata/pata_sc1200.c b/drivers/ata/pata_sc1200.c
new file mode 100644
index 00000000000..9b42b9a5242
--- /dev/null
+++ b/drivers/ata/pata_sc1200.c
@@ -0,0 +1,287 @@
1/*
2 * New ATA layer SC1200 driver Alan Cox <alan@redhat.com>
3 *
4 * TODO: Mode selection filtering
5 * TODO: Can't enable second channel until ATA core has serialize
6 * TODO: Needs custom DMA cleanup code
7 *
8 * Based very heavily on
9 *
10 * linux/drivers/ide/pci/sc1200.c Version 0.91 28-Jan-2003
11 *
12 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
13 * May be copied or modified under the terms of the GNU General Public License
14 *
15 * Development of this chipset driver was funded
16 * by the nice folks at National Semiconductor.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 *
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/blkdev.h>
38#include <linux/delay.h>
39#include <scsi/scsi_host.h>
40#include <linux/libata.h>
41
42#define DRV_NAME "sc1200"
43#define DRV_VERSION "0.2.3"
44
45#define SC1200_REV_A 0x00
46#define SC1200_REV_B1 0x01
47#define SC1200_REV_B3 0x02
48#define SC1200_REV_C1 0x03
49#define SC1200_REV_D1 0x04
50
51/**
52 * sc1200_clock - PCI clock
53 *
54 * Return the PCI bus clocking for the SC1200 chipset configuration
55 * in use. We return 0 for 33MHz 1 for 48MHz and 2 for 66Mhz
56 */
57
58static int sc1200_clock(void)
59{
60 /* Magic registers that give us the chipset data */
61 u8 chip_id = inb(0x903C);
62 u8 silicon_rev = inb(0x903D);
63 u16 pci_clock;
64
65 if (chip_id == 0x04 && silicon_rev < SC1200_REV_B1)
66 return 0; /* 33 MHz mode */
67
68 /* Clock generator configuration 0x901E its 8/9 are the PCI clocking
69 0/3 is 33Mhz 1 is 48 2 is 66 */
70
71 pci_clock = inw(0x901E);
72 pci_clock >>= 8;
73 pci_clock &= 0x03;
74 if (pci_clock == 3)
75 pci_clock = 0;
76 return pci_clock;
77}
78
79/**
80 * sc1200_set_piomode - PIO setup
81 * @ap: ATA interface
82 * @adev: device on the interface
83 *
84 * Set our PIO requirements. This is fairly simple on the SC1200
85 */
86
87static void sc1200_set_piomode(struct ata_port *ap, struct ata_device *adev)
88{
89 static const u32 pio_timings[4][5] = {
90 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
91 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
92 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
93 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131} // format1, 66Mhz
94 };
95
96 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
97 u32 format;
98 unsigned int reg = 0x40 + 0x10 * ap->port_no;
99 int mode = adev->pio_mode - XFER_PIO_0;
100
101 pci_read_config_dword(pdev, reg + 4, &format);
102 format >>= 31;
103 format += sc1200_clock();
104 pci_write_config_dword(pdev, reg + 8 * adev->devno,
105 pio_timings[format][mode]);
106}
107
108/**
109 * sc1200_set_dmamode - DMA timing setup
110 * @ap: ATA interface
111 * @adev: Device being configured
112 *
113 * We cannot mix MWDMA and UDMA without reloading timings each switch
114 * master to slave.
115 */
116
117static void sc1200_set_dmamode(struct ata_port *ap, struct ata_device *adev)
118{
119 static const u32 udma_timing[3][3] = {
120 { 0x00921250, 0x00911140, 0x00911030 },
121 { 0x00932470, 0x00922260, 0x00922140 },
122 { 0x009436A1, 0x00933481, 0x00923261 }
123 };
124
125 static const u32 mwdma_timing[3][3] = {
126 { 0x00077771, 0x00012121, 0x00002020 },
127 { 0x000BBBB2, 0x00024241, 0x00013131 },
128 { 0x000FFFF3, 0x00035352, 0x00015151 }
129 };
130
131 int clock = sc1200_clock();
132 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
133 unsigned int reg = 0x40 + 0x10 * ap->port_no;
134 int mode = adev->dma_mode;
135 u32 format;
136
137 if (mode >= XFER_UDMA_0)
138 format = udma_timing[clock][mode - XFER_UDMA_0];
139 else
140 format = mwdma_timing[clock][mode - XFER_MW_DMA_0];
141
142 if (adev->devno == 0) {
143 u32 timings;
144
145 pci_read_config_dword(pdev, reg + 4, &timings);
146 timings &= 0x80000000UL;
147 timings |= format;
148 pci_write_config_dword(pdev, reg + 4, timings);
149 } else
150 pci_write_config_dword(pdev, reg + 12, format);
151}
152
153/**
154 * sc1200_qc_issue_prot - command issue
155 * @qc: command pending
156 *
157 * Called when the libata layer is about to issue a command. We wrap
158 * this interface so that we can load the correct ATA timings if
159 * neccessary. Specifically we have a problem that there is only
160 * one MWDMA/UDMA bit.
161 */
162
163static unsigned int sc1200_qc_issue_prot(struct ata_queued_cmd *qc)
164{
165 struct ata_port *ap = qc->ap;
166 struct ata_device *adev = qc->dev;
167 struct ata_device *prev = ap->private_data;
168
169 /* See if the DMA settings could be wrong */
170 if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
171 /* Maybe, but do the channels match MWDMA/UDMA ? */
172 if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) ||
173 (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
174 /* Switch the mode bits */
175 sc1200_set_dmamode(ap, adev);
176 }
177
178 return ata_qc_issue_prot(qc);
179}
180
181static struct scsi_host_template sc1200_sht = {
182 .module = THIS_MODULE,
183 .name = DRV_NAME,
184 .ioctl = ata_scsi_ioctl,
185 .queuecommand = ata_scsi_queuecmd,
186 .can_queue = ATA_DEF_QUEUE,
187 .this_id = ATA_SHT_THIS_ID,
188 .sg_tablesize = LIBATA_MAX_PRD,
189 .max_sectors = ATA_MAX_SECTORS,
190 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
191 .emulated = ATA_SHT_EMULATED,
192 .use_clustering = ATA_SHT_USE_CLUSTERING,
193 .proc_name = DRV_NAME,
194 .dma_boundary = ATA_DMA_BOUNDARY,
195 .slave_configure = ata_scsi_slave_config,
196 .bios_param = ata_std_bios_param,
197};
198
199static struct ata_port_operations sc1200_port_ops = {
200 .port_disable = ata_port_disable,
201 .set_piomode = sc1200_set_piomode,
202 .set_dmamode = sc1200_set_dmamode,
203 .mode_filter = ata_pci_default_filter,
204
205 .tf_load = ata_tf_load,
206 .tf_read = ata_tf_read,
207 .check_status = ata_check_status,
208 .exec_command = ata_exec_command,
209 .dev_select = ata_std_dev_select,
210
211 .error_handler = ata_bmdma_error_handler,
212
213 .bmdma_setup = ata_bmdma_setup,
214 .bmdma_start = ata_bmdma_start,
215 .bmdma_stop = ata_bmdma_stop,
216 .bmdma_status = ata_bmdma_status,
217
218 .qc_prep = ata_qc_prep,
219 .qc_issue = sc1200_qc_issue_prot,
220 .eng_timeout = ata_eng_timeout,
221 .data_xfer = ata_pio_data_xfer,
222
223 .irq_handler = ata_interrupt,
224 .irq_clear = ata_bmdma_irq_clear,
225
226 .port_start = ata_port_start,
227 .port_stop = ata_port_stop,
228 .host_stop = ata_host_stop
229};
230
231/**
232 * sc1200_init_one - Initialise an SC1200
233 * @dev: PCI device
234 * @id: Entry in match table
235 *
236 * Just throw the needed data at the libata helper and it does all
237 * our work.
238 */
239
240static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
241{
242 static struct ata_port_info info = {
243 .sht = &sc1200_sht,
244 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
245 .pio_mask = 0x1f,
246 .mwdma_mask = 0x07,
247 .udma_mask = 0x07,
248 .port_ops = &sc1200_port_ops
249 };
250 static struct ata_port_info *port_info[2] = { &info, &info };
251
252 /* Can't enable port 2 yet, see top comments */
253 return ata_pci_init_one(dev, port_info, 1);
254}
255
256static struct pci_device_id sc1200[] = {
257 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE), },
258 { 0, },
259};
260
261static struct pci_driver sc1200_pci_driver = {
262 .name = DRV_NAME,
263 .id_table = sc1200,
264 .probe = sc1200_init_one,
265 .remove = ata_pci_remove_one
266};
267
268static int __init sc1200_init(void)
269{
270 return pci_register_driver(&sc1200_pci_driver);
271}
272
273
274static void __exit sc1200_exit(void)
275{
276 pci_unregister_driver(&sc1200_pci_driver);
277}
278
279
280MODULE_AUTHOR("Alan Cox, Mark Lord");
281MODULE_DESCRIPTION("low-level driver for the NS/AMD SC1200");
282MODULE_LICENSE("GPL");
283MODULE_DEVICE_TABLE(pci, sc1200);
284MODULE_VERSION(DRV_VERSION);
285
286module_init(sc1200_init);
287module_exit(sc1200_exit);
diff --git a/drivers/ata/pata_serverworks.c b/drivers/ata/pata_serverworks.c
new file mode 100644
index 00000000000..3ec30036c97
--- /dev/null
+++ b/drivers/ata/pata_serverworks.c
@@ -0,0 +1,587 @@
1/*
2 * ata-serverworks.c - Serverworks PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * serverworks.c
9 *
10 * Copyright (C) 1998-2000 Michel Aubry
11 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
12 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
13 * Portions copyright (c) 2001 Sun Microsystems
14 *
15 *
16 * RCC/ServerWorks IDE driver for Linux
17 *
18 * OSB4: `Open South Bridge' IDE Interface (fn 1)
19 * supports UDMA mode 2 (33 MB/s)
20 *
21 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
22 * all revisions support UDMA mode 4 (66 MB/s)
23 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
24 *
25 * *** The CSB5 does not provide ANY register ***
26 * *** to detect 80-conductor cable presence. ***
27 *
28 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
29 *
30 * Documentation:
31 * Available under NDA only. Errata info very hard to get.
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <scsi/scsi_host.h>
41#include <linux/libata.h>
42
43#define DRV_NAME "pata_serverworks"
44#define DRV_VERSION "0.3.6"
45
46#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
47#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48
49/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
50 * can overrun their FIFOs when used with the CSB5 */
51
52static const char *csb_bad_ata100[] = {
53 "ST320011A",
54 "ST340016A",
55 "ST360021A",
56 "ST380021A",
57 NULL
58};
59
60/**
61 * dell_cable - Dell serverworks cable detection
62 * @ap: ATA port to do cable detect
63 *
64 * Dell hide the 40/80 pin select for their interfaces in the top two
65 * bits of the subsystem ID.
66 */
67
68static int dell_cable(struct ata_port *ap) {
69 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
70
71 if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
72 return ATA_CBL_PATA80;
73 return ATA_CBL_PATA40;
74}
75
76/**
77 * sun_cable - Sun Cobalt 'Alpine' cable detection
78 * @ap: ATA port to do cable select
79 *
80 * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
81 * subsystem ID the same as dell. We could use one function but we may
82 * need to extend the Dell one in future
83 */
84
85static int sun_cable(struct ata_port *ap) {
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87
88 if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
89 return ATA_CBL_PATA80;
90 return ATA_CBL_PATA40;
91}
92
93/**
94 * osb4_cable - OSB4 cable detect
95 * @ap: ATA port to check
96 *
97 * The OSB4 isn't UDMA66 capable so this is easy
98 */
99
100static int osb4_cable(struct ata_port *ap) {
101 return ATA_CBL_PATA40;
102}
103
104/**
105 * csb4_cable - CSB5/6 cable detect
106 * @ap: ATA port to check
107 *
108 * Serverworks default arrangement is to use the drive side detection
109 * only.
110 */
111
112static int csb_cable(struct ata_port *ap) {
113 return ATA_CBL_PATA80;
114}
115
116struct sv_cable_table {
117 int device;
118 int subvendor;
119 int (*cable_detect)(struct ata_port *ap);
120};
121
122/*
123 * Note that we don't copy the old serverworks code because the old
124 * code contains obvious mistakes
125 */
126
127static struct sv_cable_table cable_detect[] = {
128 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
129 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
130 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable },
131 { PCI_DEVICE_ID_SERVERWORKS_OSB4, PCI_ANY_ID, osb4_cable },
132 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
133 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
134 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
135 { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
136 { }
137};
138
139/**
140 * serverworks_pre_reset - cable detection
141 * @ap: ATA port
142 *
143 * Perform cable detection according to the device and subvendor
144 * identifications
145 */
146
147static int serverworks_pre_reset(struct ata_port *ap) {
148 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
149 struct sv_cable_table *cb = cable_detect;
150
151 while(cb->device) {
152 if (cb->device == pdev->device &&
153 (cb->subvendor == pdev->subsystem_vendor ||
154 cb->subvendor == PCI_ANY_ID)) {
155 ap->cbl = cb->cable_detect(ap);
156 return ata_std_prereset(ap);
157 }
158 cb++;
159 }
160
161 BUG();
162 return -1; /* kill compiler warning */
163}
164
165static void serverworks_error_handler(struct ata_port *ap)
166{
167 return ata_bmdma_drive_eh(ap, serverworks_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
168}
169
170/**
171 * serverworks_is_csb - Check for CSB or OSB
172 * @pdev: PCI device to check
173 *
174 * Returns true if the device being checked is known to be a CSB
175 * series device.
176 */
177
178static u8 serverworks_is_csb(struct pci_dev *pdev)
179{
180 switch (pdev->device) {
181 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
182 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
183 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
184 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
185 return 1;
186 default:
187 break;
188 }
189 return 0;
190}
191
192/**
193 * serverworks_osb4_filter - mode selection filter
194 * @ap: ATA interface
195 * @adev: ATA device
196 *
197 * Filter the offered modes for the device to apply controller
198 * specific rules. OSB4 requires no UDMA for disks due to a FIFO
199 * bug we hit.
200 */
201
202static unsigned long serverworks_osb4_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
203{
204 if (adev->class == ATA_DEV_ATA)
205 mask &= ~ATA_MASK_UDMA;
206 return ata_pci_default_filter(ap, adev, mask);
207}
208
209
210/**
211 * serverworks_csb_filter - mode selection filter
212 * @ap: ATA interface
213 * @adev: ATA device
214 *
215 * Check the blacklist and disable UDMA5 if matched
216 */
217
218static unsigned long serverworks_csb_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
219{
220 const char *p;
221 char model_num[40];
222 int len, i;
223
224 /* Disk, UDMA */
225 if (adev->class != ATA_DEV_ATA)
226 return ata_pci_default_filter(ap, adev, mask);
227
228 /* Actually do need to check */
229 ata_id_string(adev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
230 /* Precuationary - why not do this in the libata core ?? */
231
232 len = strlen(model_num);
233 while ((len > 0) && (model_num[len - 1] == ' ')) {
234 len--;
235 model_num[len] = 0;
236 }
237
238 for(i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
239 if (!strncmp(p, model_num, len))
240 mask &= ~(0x1F << ATA_SHIFT_UDMA);
241 }
242 return ata_pci_default_filter(ap, adev, mask);
243}
244
245
246/**
247 * serverworks_set_piomode - set initial PIO mode data
248 * @ap: ATA interface
249 * @adev: ATA device
250 *
251 * Program the OSB4/CSB5 timing registers for PIO. The PIO register
252 * load is done as a simple lookup.
253 */
254static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
255{
256 static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
257 int offset = 1 + (2 * ap->port_no) - adev->devno;
258 int devbits = (2 * ap->port_no + adev->devno) * 4;
259 u16 csb5_pio;
260 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
261 int pio = adev->pio_mode - XFER_PIO_0;
262
263 pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
264
265 /* The OSB4 just requires the timing but the CSB series want the
266 mode number as well */
267 if (serverworks_is_csb(pdev)) {
268 pci_read_config_word(pdev, 0x4A, &csb5_pio);
269 csb5_pio &= ~(0x0F << devbits);
270 pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits));
271 }
272}
273
274/**
275 * serverworks_set_dmamode - set initial DMA mode data
276 * @ap: ATA interface
277 * @adev: ATA device
278 *
279 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
280 * chipset. The MWDMA mode values are pulled from a lookup table
281 * while the chipset uses mode number for UDMA.
282 */
283
284static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
285{
286 static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
287 int offset = 1 + 2 * ap->port_no - adev->devno;
288 int devbits = (2 * ap->port_no + adev->devno);
289 u8 ultra;
290 u8 ultra_cfg;
291 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
292
293 pci_read_config_byte(pdev, 0x54, &ultra_cfg);
294
295 if (adev->dma_mode >= XFER_UDMA_0) {
296 pci_write_config_byte(pdev, 0x44 + offset, 0x20);
297
298 pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
299 ultra &= ~(0x0F << (ap->port_no * 4));
300 ultra |= (adev->dma_mode - XFER_UDMA_0)
301 << (ap->port_no * 4);
302 pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
303
304 ultra_cfg |= (1 << devbits);
305 } else {
306 pci_write_config_byte(pdev, 0x44 + offset,
307 dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
308 ultra_cfg &= ~(1 << devbits);
309 }
310 pci_write_config_byte(pdev, 0x54, ultra_cfg);
311}
312
313static struct scsi_host_template serverworks_sht = {
314 .module = THIS_MODULE,
315 .name = DRV_NAME,
316 .ioctl = ata_scsi_ioctl,
317 .queuecommand = ata_scsi_queuecmd,
318 .can_queue = ATA_DEF_QUEUE,
319 .this_id = ATA_SHT_THIS_ID,
320 .sg_tablesize = LIBATA_MAX_PRD,
321 .max_sectors = ATA_MAX_SECTORS,
322 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
323 .emulated = ATA_SHT_EMULATED,
324 .use_clustering = ATA_SHT_USE_CLUSTERING,
325 .proc_name = DRV_NAME,
326 .dma_boundary = ATA_DMA_BOUNDARY,
327 .slave_configure = ata_scsi_slave_config,
328 .bios_param = ata_std_bios_param,
329};
330
331static struct ata_port_operations serverworks_osb4_port_ops = {
332 .port_disable = ata_port_disable,
333 .set_piomode = serverworks_set_piomode,
334 .set_dmamode = serverworks_set_dmamode,
335 .mode_filter = serverworks_osb4_filter,
336
337 .tf_load = ata_tf_load,
338 .tf_read = ata_tf_read,
339 .check_status = ata_check_status,
340 .exec_command = ata_exec_command,
341 .dev_select = ata_std_dev_select,
342
343 .freeze = ata_bmdma_freeze,
344 .thaw = ata_bmdma_thaw,
345 .error_handler = serverworks_error_handler,
346 .post_internal_cmd = ata_bmdma_post_internal_cmd,
347
348 .bmdma_setup = ata_bmdma_setup,
349 .bmdma_start = ata_bmdma_start,
350 .bmdma_stop = ata_bmdma_stop,
351 .bmdma_status = ata_bmdma_status,
352
353 .qc_prep = ata_qc_prep,
354 .qc_issue = ata_qc_issue_prot,
355 .eng_timeout = ata_eng_timeout,
356 .data_xfer = ata_pio_data_xfer,
357
358 .irq_handler = ata_interrupt,
359 .port_start = ata_port_start,
360 .port_stop = ata_port_stop,
361 .host_stop = ata_host_stop
362};
363
364static struct ata_port_operations serverworks_csb_port_ops = {
365 .port_disable = ata_port_disable,
366 .set_piomode = serverworks_set_piomode,
367 .set_dmamode = serverworks_set_dmamode,
368 .mode_filter = serverworks_csb_filter,
369
370 .tf_load = ata_tf_load,
371 .tf_read = ata_tf_read,
372 .check_status = ata_check_status,
373 .exec_command = ata_exec_command,
374 .dev_select = ata_std_dev_select,
375
376 .freeze = ata_bmdma_freeze,
377 .thaw = ata_bmdma_thaw,
378 .error_handler = serverworks_error_handler,
379 .post_internal_cmd = ata_bmdma_post_internal_cmd,
380
381 .bmdma_setup = ata_bmdma_setup,
382 .bmdma_start = ata_bmdma_start,
383 .bmdma_stop = ata_bmdma_stop,
384 .bmdma_status = ata_bmdma_status,
385
386 .qc_prep = ata_qc_prep,
387 .qc_issue = ata_qc_issue_prot,
388 .eng_timeout = ata_eng_timeout,
389 .data_xfer = ata_pio_data_xfer,
390
391 .irq_handler = ata_interrupt,
392 .port_start = ata_port_start,
393 .port_stop = ata_port_stop,
394 .host_stop = ata_host_stop
395};
396
397static int serverworks_fixup_osb4(struct pci_dev *pdev)
398{
399 u32 reg;
400 struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
401 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
402 if (isa_dev) {
403 pci_read_config_dword(isa_dev, 0x64, &reg);
404 reg &= ~0x00002000; /* disable 600ns interrupt mask */
405 if (!(reg & 0x00004000))
406 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
407 reg |= 0x00004000; /* enable UDMA/33 support */
408 pci_write_config_dword(isa_dev, 0x64, reg);
409 pci_dev_put(isa_dev);
410 return 0;
411 }
412 printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
413 return -ENODEV;
414}
415
416static int serverworks_fixup_csb(struct pci_dev *pdev)
417{
418 u8 rev;
419 u8 btr;
420
421 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
422
423 /* Third Channel Test */
424 if (!(PCI_FUNC(pdev->devfn) & 1)) {
425 struct pci_dev * findev = NULL;
426 u32 reg4c = 0;
427 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
428 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
429 if (findev) {
430 pci_read_config_dword(findev, 0x4C, &reg4c);
431 reg4c &= ~0x000007FF;
432 reg4c |= 0x00000040;
433 reg4c |= 0x00000020;
434 pci_write_config_dword(findev, 0x4C, reg4c);
435 pci_dev_put(findev);
436 }
437 } else {
438 struct pci_dev * findev = NULL;
439 u8 reg41 = 0;
440
441 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
442 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
443 if (findev) {
444 pci_read_config_byte(findev, 0x41, &reg41);
445 reg41 &= ~0x40;
446 pci_write_config_byte(findev, 0x41, reg41);
447 pci_dev_put(findev);
448 }
449 }
450 /* setup the UDMA Control register
451 *
452 * 1. clear bit 6 to enable DMA
453 * 2. enable DMA modes with bits 0-1
454 * 00 : legacy
455 * 01 : udma2
456 * 10 : udma2/udma4
457 * 11 : udma2/udma4/udma5
458 */
459 pci_read_config_byte(pdev, 0x5A, &btr);
460 btr &= ~0x40;
461 if (!(PCI_FUNC(pdev->devfn) & 1))
462 btr |= 0x2;
463 else
464 btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
465 pci_write_config_byte(pdev, 0x5A, btr);
466
467 return btr;
468}
469
470static void serverworks_fixup_ht1000(struct pci_dev *pdev)
471{
472 u8 btr;
473 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
474 pci_read_config_byte(pdev, 0x5A, &btr);
475 btr &= ~0x40;
476 btr |= 0x3;
477 pci_write_config_byte(pdev, 0x5A, btr);
478}
479
480
481static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
482{
483 int ports = 2;
484 static struct ata_port_info info[4] = {
485 { /* OSB4 */
486 .sht = &serverworks_sht,
487 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
488 .pio_mask = 0x1f,
489 .mwdma_mask = 0x07,
490 .udma_mask = 0x07,
491 .port_ops = &serverworks_osb4_port_ops
492 }, { /* OSB4 no UDMA */
493 .sht = &serverworks_sht,
494 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
495 .pio_mask = 0x1f,
496 .mwdma_mask = 0x07,
497 .udma_mask = 0x00,
498 .port_ops = &serverworks_osb4_port_ops
499 }, { /* CSB5 */
500 .sht = &serverworks_sht,
501 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
502 .pio_mask = 0x1f,
503 .mwdma_mask = 0x07,
504 .udma_mask = 0x1f,
505 .port_ops = &serverworks_csb_port_ops
506 }, { /* CSB5 - later revisions*/
507 .sht = &serverworks_sht,
508 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
509 .pio_mask = 0x1f,
510 .mwdma_mask = 0x07,
511 .udma_mask = 0x3f,
512 .port_ops = &serverworks_csb_port_ops
513 }
514 };
515 static struct ata_port_info *port_info[2];
516 struct ata_port_info *devinfo = &info[id->driver_data];
517
518 /* Force master latency timer to 64 PCI clocks */
519 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
520
521 /* OSB4 : South Bridge and IDE */
522 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
523 /* Select non UDMA capable OSB4 if we can't do fixups */
524 if ( serverworks_fixup_osb4(pdev) < 0)
525 devinfo = &info[1];
526 }
527 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
528 else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
529 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
530 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
531
532 /* If the returned btr is the newer revision then
533 select the right info block */
534 if (serverworks_fixup_csb(pdev) == 3)
535 devinfo = &info[3];
536
537 /* Is this the 3rd channel CSB6 IDE ? */
538 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
539 ports = 1;
540 }
541 /* setup HT1000E */
542 else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
543 serverworks_fixup_ht1000(pdev);
544
545 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
546 ata_pci_clear_simplex(pdev);
547
548 port_info[0] = port_info[1] = devinfo;
549 return ata_pci_init_one(pdev, port_info, ports);
550}
551
552static struct pci_device_id serverworks[] = {
553 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
554 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
555 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
556 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
557 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
558 { 0, },
559};
560
561static struct pci_driver serverworks_pci_driver = {
562 .name = DRV_NAME,
563 .id_table = serverworks,
564 .probe = serverworks_init_one,
565 .remove = ata_pci_remove_one
566};
567
568static int __init serverworks_init(void)
569{
570 return pci_register_driver(&serverworks_pci_driver);
571}
572
573
574static void __exit serverworks_exit(void)
575{
576 pci_unregister_driver(&serverworks_pci_driver);
577}
578
579
580MODULE_AUTHOR("Alan Cox");
581MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
582MODULE_LICENSE("GPL");
583MODULE_DEVICE_TABLE(pci, serverworks);
584MODULE_VERSION(DRV_VERSION);
585
586module_init(serverworks_init);
587module_exit(serverworks_exit);
diff --git a/drivers/ata/pata_sil680.c b/drivers/ata/pata_sil680.c
new file mode 100644
index 00000000000..8f7db9638d0
--- /dev/null
+++ b/drivers/ata/pata_sil680.c
@@ -0,0 +1,381 @@
1/*
2 * pata_sil680.c - SIL680 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
9 *
10 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat <alan@redhat.com>
12 *
13 * May be copied or modified under the terms of the GNU General Public License
14 *
15 * Documentation publically available.
16 *
17 * If you have strange problems with nVidia chipset systems please
18 * see the SI support documentation and update your system BIOS
19 * if neccessary
20 *
21 * TODO
22 * If we know all our devices are LBA28 (or LBA28 sized) we could use
23 * the command fifo mode.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34
35#define DRV_NAME "pata_sil680"
36#define DRV_VERSION "0.3.2"
37
38/**
39 * sil680_selreg - return register base
40 * @hwif: interface
41 * @r: config offset
42 *
43 * Turn a config register offset into the right address in either
44 * PCI space or MMIO space to access the control register in question
45 * Thankfully this is a configuration operation so isnt performance
46 * criticial.
47 */
48
49static unsigned long sil680_selreg(struct ata_port *ap, int r)
50{
51 unsigned long base = 0xA0 + r;
52 base += (ap->port_no << 4);
53 return base;
54}
55
56/**
57 * sil680_seldev - return register base
58 * @hwif: interface
59 * @r: config offset
60 *
61 * Turn a config register offset into the right address in either
62 * PCI space or MMIO space to access the control register in question
63 * including accounting for the unit shift.
64 */
65
66static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
67{
68 unsigned long base = 0xA0 + r;
69 base += (ap->port_no << 4);
70 base |= adev->devno ? 2 : 0;
71 return base;
72}
73
74
75/**
76 * sil680_cable_detect - cable detection
77 * @ap: ATA port
78 *
79 * Perform cable detection. The SIL680 stores this in PCI config
80 * space for us.
81 */
82
83static int sil680_cable_detect(struct ata_port *ap) {
84 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85 unsigned long addr = sil680_selreg(ap, 0);
86 u8 ata66;
87 pci_read_config_byte(pdev, addr, &ata66);
88 if (ata66 & 1)
89 return ATA_CBL_PATA80;
90 else
91 return ATA_CBL_PATA40;
92}
93
94static int sil680_pre_reset(struct ata_port *ap)
95{
96 ap->cbl = sil680_cable_detect(ap);
97 return ata_std_prereset(ap);
98}
99
100/**
101 * sil680_bus_reset - reset the SIL680 bus
102 * @ap: ATA port to reset
103 *
104 * Perform the SIL680 housekeeping when doing an ATA bus reset
105 */
106
107static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes)
108{
109 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
110 unsigned long addr = sil680_selreg(ap, 0);
111 u8 reset;
112
113 pci_read_config_byte(pdev, addr, &reset);
114 pci_write_config_byte(pdev, addr, reset | 0x03);
115 udelay(25);
116 pci_write_config_byte(pdev, addr, reset);
117 return ata_std_softreset(ap, classes);
118}
119
120static void sil680_error_handler(struct ata_port *ap)
121{
122 ata_bmdma_drive_eh(ap, sil680_pre_reset, sil680_bus_reset, NULL, ata_std_postreset);
123}
124
125/**
126 * sil680_set_piomode - set initial PIO mode data
127 * @ap: ATA interface
128 * @adev: ATA device
129 *
130 * Program the SIL680 registers for PIO mode. Note that the task speed
131 * registers are shared between the devices so we must pick the lowest
132 * mode for command work.
133 */
134
135static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
136{
137 static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
138 static u16 speed_t[5] = { 0x328A, 0x1281, 0x1281, 0x10C3, 0x10C1 };
139
140 unsigned long tfaddr = sil680_selreg(ap, 0x02);
141 unsigned long addr = sil680_seldev(ap, adev, 0x04);
142 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
143 int pio = adev->pio_mode - XFER_PIO_0;
144 int lowest_pio = pio;
145 u16 reg;
146
147 struct ata_device *pair = ata_dev_pair(adev);
148
149 if (pair != NULL && adev->pio_mode > pair->pio_mode)
150 lowest_pio = pair->pio_mode - XFER_PIO_0;
151
152 pci_write_config_word(pdev, addr, speed_p[pio]);
153 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
154
155 pci_read_config_word(pdev, tfaddr-2, &reg);
156 reg &= ~0x0200; /* Clear IORDY */
157 if (ata_pio_need_iordy(adev))
158 reg |= 0x0200; /* Enable IORDY */
159 pci_write_config_word(pdev, tfaddr-2, reg);
160}
161
162/**
163 * sil680_set_dmamode - set initial DMA mode data
164 * @ap: ATA interface
165 * @adev: ATA device
166 *
167 * Program the MWDMA/UDMA modes for the sil680 k
168 * chipset. The MWDMA mode values are pulled from a lookup table
169 * while the chipset uses mode number for UDMA.
170 */
171
172static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
173{
174 static u8 ultra_table[2][7] = {
175 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
176 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
177 };
178 static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
179
180 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
181 unsigned long ma = sil680_seldev(ap, adev, 0x08);
182 unsigned long ua = sil680_seldev(ap, adev, 0x0C);
183 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
184 int port_shift = adev->devno * 4;
185 u8 scsc, mode;
186 u16 multi, ultra;
187
188 pci_read_config_byte(pdev, 0x8A, &scsc);
189 pci_read_config_byte(pdev, addr_mask, &mode);
190 pci_read_config_word(pdev, ma, &multi);
191 pci_read_config_word(pdev, ua, &ultra);
192
193 /* Mask timing bits */
194 ultra &= ~0x3F;
195 mode &= ~(0x03 << port_shift);
196
197 /* Extract scsc */
198 scsc = (scsc & 0x30) ? 1: 0;
199
200 if (adev->dma_mode >= XFER_UDMA_0) {
201 multi = 0x10C1;
202 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
203 mode |= (0x03 << port_shift);
204 } else {
205 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
206 mode |= (0x02 << port_shift);
207 }
208 pci_write_config_byte(pdev, addr_mask, mode);
209 pci_write_config_word(pdev, ma, multi);
210 pci_write_config_word(pdev, ua, ultra);
211}
212
213static struct scsi_host_template sil680_sht = {
214 .module = THIS_MODULE,
215 .name = DRV_NAME,
216 .ioctl = ata_scsi_ioctl,
217 .queuecommand = ata_scsi_queuecmd,
218 .can_queue = ATA_DEF_QUEUE,
219 .this_id = ATA_SHT_THIS_ID,
220 .sg_tablesize = LIBATA_MAX_PRD,
221 .max_sectors = ATA_MAX_SECTORS,
222 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
223 .emulated = ATA_SHT_EMULATED,
224 .use_clustering = ATA_SHT_USE_CLUSTERING,
225 .proc_name = DRV_NAME,
226 .dma_boundary = ATA_DMA_BOUNDARY,
227 .slave_configure = ata_scsi_slave_config,
228 .bios_param = ata_std_bios_param,
229};
230
231static struct ata_port_operations sil680_port_ops = {
232 .port_disable = ata_port_disable,
233 .set_piomode = sil680_set_piomode,
234 .set_dmamode = sil680_set_dmamode,
235 .mode_filter = ata_pci_default_filter,
236 .tf_load = ata_tf_load,
237 .tf_read = ata_tf_read,
238 .check_status = ata_check_status,
239 .exec_command = ata_exec_command,
240 .dev_select = ata_std_dev_select,
241
242 .freeze = ata_bmdma_freeze,
243 .thaw = ata_bmdma_thaw,
244 .error_handler = sil680_error_handler,
245 .post_internal_cmd = ata_bmdma_post_internal_cmd,
246
247 .bmdma_setup = ata_bmdma_setup,
248 .bmdma_start = ata_bmdma_start,
249 .bmdma_stop = ata_bmdma_stop,
250 .bmdma_status = ata_bmdma_status,
251
252 .qc_prep = ata_qc_prep,
253 .qc_issue = ata_qc_issue_prot,
254 .eng_timeout = ata_eng_timeout,
255 .data_xfer = ata_pio_data_xfer,
256
257 .irq_handler = ata_interrupt,
258 .irq_clear = ata_bmdma_irq_clear,
259
260 .port_start = ata_port_start,
261 .port_stop = ata_port_stop,
262 .host_stop = ata_host_stop
263};
264
265static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
266{
267 static struct ata_port_info info = {
268 .sht = &sil680_sht,
269 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
270 .pio_mask = 0x1f,
271 .mwdma_mask = 0x07,
272 .udma_mask = 0x7f,
273 .port_ops = &sil680_port_ops
274 };
275 static struct ata_port_info info_slow = {
276 .sht = &sil680_sht,
277 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
278 .pio_mask = 0x1f,
279 .mwdma_mask = 0x07,
280 .udma_mask = 0x3f,
281 .port_ops = &sil680_port_ops
282 };
283 static struct ata_port_info *port_info[2] = {&info, &info};
284 static int printed_version;
285 u32 class_rev = 0;
286 u8 tmpbyte = 0;
287
288 if (!printed_version++)
289 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
290
291 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
292 class_rev &= 0xff;
293 /* FIXME: double check */
294 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
295
296 pci_write_config_byte(pdev, 0x80, 0x00);
297 pci_write_config_byte(pdev, 0x84, 0x00);
298
299 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
300
301 printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
302 tmpbyte & 1, tmpbyte & 0x30);
303
304 switch(tmpbyte & 0x30) {
305 case 0x00:
306 /* 133 clock attempt to force it on */
307 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
308 break;
309 case 0x30:
310 /* if clocking is disabled */
311 /* 133 clock attempt to force it on */
312 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
313 break;
314 case 0x10:
315 /* 133 already */
316 break;
317 case 0x20:
318 /* BIOS set PCI x2 clocking */
319 break;
320 }
321
322 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
323 printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
324 tmpbyte & 1, tmpbyte & 0x30);
325 if ((tmpbyte & 0x30) == 0)
326 port_info[0] = port_info[1] = &info_slow;
327
328 pci_write_config_byte(pdev, 0xA1, 0x72);
329 pci_write_config_word(pdev, 0xA2, 0x328A);
330 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
331 pci_write_config_dword(pdev, 0xA8, 0x43924392);
332 pci_write_config_dword(pdev, 0xAC, 0x40094009);
333 pci_write_config_byte(pdev, 0xB1, 0x72);
334 pci_write_config_word(pdev, 0xB2, 0x328A);
335 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
336 pci_write_config_dword(pdev, 0xB8, 0x43924392);
337 pci_write_config_dword(pdev, 0xBC, 0x40094009);
338
339 switch(tmpbyte & 0x30) {
340 case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
341 case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
342 case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
343 /* This last case is _NOT_ ok */
344 case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
345 return -EIO;
346 }
347 return ata_pci_init_one(pdev, port_info, 2);
348}
349
350static const struct pci_device_id sil680[] = {
351 { PCI_DEVICE(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680), },
352 { 0, },
353};
354
355static struct pci_driver sil680_pci_driver = {
356 .name = DRV_NAME,
357 .id_table = sil680,
358 .probe = sil680_init_one,
359 .remove = ata_pci_remove_one
360};
361
362static int __init sil680_init(void)
363{
364 return pci_register_driver(&sil680_pci_driver);
365}
366
367
368static void __exit sil680_exit(void)
369{
370 pci_unregister_driver(&sil680_pci_driver);
371}
372
373
374MODULE_AUTHOR("Alan Cox");
375MODULE_DESCRIPTION("low-level driver for SI680 PATA");
376MODULE_LICENSE("GPL");
377MODULE_DEVICE_TABLE(pci, sil680);
378MODULE_VERSION(DRV_VERSION);
379
380module_init(sil680_init);
381module_exit(sil680_exit);
diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c
new file mode 100644
index 00000000000..4ad7fb44bfa
--- /dev/null
+++ b/drivers/ata/pata_sis.c
@@ -0,0 +1,1030 @@
1/*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Based upon linux/drivers/ide/pci/sis5513.c
7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
10 * SiS Taiwan : for direct support and hardware.
11 * Daniela Engert : for initial ATA100 advices and numerous others.
12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
13 * for checking code correctness, providing patches.
14 * Original tests and design on the SiS620 chipset.
15 * ATA100 tests and design on the SiS735 chipset.
16 * ATA16/33 support from specs
17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
18 *
19 *
20 * TODO
21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
22 * More Testing
23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/ata.h>
35
36#define DRV_NAME "pata_sis"
37#define DRV_VERSION "0.4.2"
38
39struct sis_chipset {
40 u16 device; /* PCI host ID */
41 struct ata_port_info *info; /* Info block */
42 /* Probably add family, cable detect type etc here to clean
43 up code later */
44};
45
46/**
47 * sis_port_base - return PCI configuration base for dev
48 * @adev: device
49 *
50 * Returns the base of the PCI configuration registers for this port
51 * number.
52 */
53
54static int sis_port_base(struct ata_device *adev)
55{
56 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
57}
58
59/**
60 * sis_133_pre_reset - check for 40/80 pin
61 * @ap: Port
62 *
63 * Perform cable detection for the later UDMA133 capable
64 * SiS chipset.
65 */
66
67static int sis_133_pre_reset(struct ata_port *ap)
68{
69 static const struct pci_bits sis_enable_bits[] = {
70 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
71 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
72 };
73
74 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
75 u16 tmp;
76
77 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
78 ata_port_disable(ap);
79 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
80 return 0;
81 }
82 /* The top bit of this register is the cable detect bit */
83 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
84 if (tmp & 0x8000)
85 ap->cbl = ATA_CBL_PATA40;
86 else
87 ap->cbl = ATA_CBL_PATA80;
88
89 return ata_std_prereset(ap);
90}
91
92/**
93 * sis_error_handler - Probe specified port on PATA host controller
94 * @ap: Port to probe
95 *
96 * LOCKING:
97 * None (inherited from caller).
98 */
99
100static void sis_133_error_handler(struct ata_port *ap)
101{
102 ata_bmdma_drive_eh(ap, sis_133_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
103}
104
105
106/**
107 * sis_66_pre_reset - check for 40/80 pin
108 * @ap: Port
109 *
110 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
111 * SiS IDE controllers.
112 */
113
114static int sis_66_pre_reset(struct ata_port *ap)
115{
116 static const struct pci_bits sis_enable_bits[] = {
117 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
118 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
119 };
120
121 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
122 u8 tmp;
123
124 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
125 ata_port_disable(ap);
126 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
127 return 0;
128 }
129 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
130 pci_read_config_byte(pdev, 0x48, &tmp);
131 tmp >>= ap->port_no;
132 if (tmp & 0x10)
133 ap->cbl = ATA_CBL_PATA40;
134 else
135 ap->cbl = ATA_CBL_PATA80;
136
137 return ata_std_prereset(ap);
138}
139
140/**
141 * sis_66_error_handler - Probe specified port on PATA host controller
142 * @ap: Port to probe
143 * @classes:
144 *
145 * LOCKING:
146 * None (inherited from caller).
147 */
148
149static void sis_66_error_handler(struct ata_port *ap)
150{
151 ata_bmdma_drive_eh(ap, sis_66_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
152}
153
154/**
155 * sis_old_pre_reset - probe begin
156 * @ap: ATA port
157 *
158 * Set up cable type and use generic probe init
159 */
160
161static int sis_old_pre_reset(struct ata_port *ap)
162{
163 static const struct pci_bits sis_enable_bits[] = {
164 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
165 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
166 };
167
168 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
169
170 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
171 ata_port_disable(ap);
172 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
173 return 0;
174 }
175 ap->cbl = ATA_CBL_PATA40;
176 return ata_std_prereset(ap);
177}
178
179
180/**
181 * sis_old_error_handler - Probe specified port on PATA host controller
182 * @ap: Port to probe
183 *
184 * LOCKING:
185 * None (inherited from caller).
186 */
187
188static void sis_old_error_handler(struct ata_port *ap)
189{
190 ata_bmdma_drive_eh(ap, sis_old_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
191}
192
193/**
194 * sis_set_fifo - Set RWP fifo bits for this device
195 * @ap: Port
196 * @adev: Device
197 *
198 * SIS chipsets implement prefetch/postwrite bits for each device
199 * on both channels. This functionality is not ATAPI compatible and
200 * must be configured according to the class of device present
201 */
202
203static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
204{
205 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
206 u8 fifoctrl;
207 u8 mask = 0x11;
208
209 mask <<= (2 * ap->port_no);
210 mask <<= adev->devno;
211
212 /* This holds various bits including the FIFO control */
213 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
214 fifoctrl &= ~mask;
215
216 /* Enable for ATA (disk) only */
217 if (adev->class == ATA_DEV_ATA)
218 fifoctrl |= mask;
219 pci_write_config_byte(pdev, 0x4B, fifoctrl);
220}
221
222/**
223 * sis_old_set_piomode - Initialize host controller PATA PIO timings
224 * @ap: Port whose timings we are configuring
225 * @adev: Device we are configuring for.
226 *
227 * Set PIO mode for device, in host controller PCI config space. This
228 * function handles PIO set up for all chips that are pre ATA100 and
229 * also early ATA100 devices.
230 *
231 * LOCKING:
232 * None (inherited from caller).
233 */
234
235static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
236{
237 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
238 int port = sis_port_base(adev);
239 u8 t1, t2;
240 int speed = adev->pio_mode - XFER_PIO_0;
241
242 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
243 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
244
245 sis_set_fifo(ap, adev);
246
247 pci_read_config_byte(pdev, port, &t1);
248 pci_read_config_byte(pdev, port + 1, &t2);
249
250 t1 &= ~0x0F; /* Clear active/recovery timings */
251 t2 &= ~0x07;
252
253 t1 |= active[speed];
254 t2 |= recovery[speed];
255
256 pci_write_config_byte(pdev, port, t1);
257 pci_write_config_byte(pdev, port + 1, t2);
258}
259
260/**
261 * sis_100_set_pioode - Initialize host controller PATA PIO timings
262 * @ap: Port whose timings we are configuring
263 * @adev: Device we are configuring for.
264 *
265 * Set PIO mode for device, in host controller PCI config space. This
266 * function handles PIO set up for ATA100 devices and early ATA133.
267 *
268 * LOCKING:
269 * None (inherited from caller).
270 */
271
272static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
273{
274 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
275 int port = sis_port_base(adev);
276 int speed = adev->pio_mode - XFER_PIO_0;
277
278 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
279
280 sis_set_fifo(ap, adev);
281
282 pci_write_config_byte(pdev, port, actrec[speed]);
283}
284
285/**
286 * sis_133_set_pioode - Initialize host controller PATA PIO timings
287 * @ap: Port whose timings we are configuring
288 * @adev: Device we are configuring for.
289 *
290 * Set PIO mode for device, in host controller PCI config space. This
291 * function handles PIO set up for the later ATA133 devices.
292 *
293 * LOCKING:
294 * None (inherited from caller).
295 */
296
297static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
298{
299 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
300 int port = 0x40;
301 u32 t1;
302 u32 reg54;
303 int speed = adev->pio_mode - XFER_PIO_0;
304
305 const u32 timing133[] = {
306 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
307 0x0C266000,
308 0x04263000,
309 0x0C0A3000,
310 0x05093000
311 };
312 const u32 timing100[] = {
313 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
314 0x091C4000,
315 0x031C2000,
316 0x09072000,
317 0x04062000
318 };
319
320 sis_set_fifo(ap, adev);
321
322 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
323 pci_read_config_dword(pdev, 0x54, &reg54);
324 if (reg54 & 0x40000000)
325 port = 0x70;
326 port += 8 * ap->port_no + 4 * adev->devno;
327
328 pci_read_config_dword(pdev, port, &t1);
329 t1 &= 0xC0C00FFF; /* Mask out timing */
330
331 if (t1 & 0x08) /* 100 or 133 ? */
332 t1 |= timing133[speed];
333 else
334 t1 |= timing100[speed];
335 pci_write_config_byte(pdev, port, t1);
336}
337
338/**
339 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
340 * @ap: Port whose timings we are configuring
341 * @adev: Device to program
342 *
343 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
344 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
345 * the old ide/pci driver.
346 *
347 * LOCKING:
348 * None (inherited from caller).
349 */
350
351static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
352{
353 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
354 int speed = adev->dma_mode - XFER_MW_DMA_0;
355 int drive_pci = sis_port_base(adev);
356 u16 timing;
357
358 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
359 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
360
361 pci_read_config_word(pdev, drive_pci, &timing);
362
363 if (adev->dma_mode < XFER_UDMA_0) {
364 /* bits 3-0 hold recovery timing bits 8-10 active timing and
365 the higer bits are dependant on the device */
366 timing &= ~ 0x870F;
367 timing |= mwdma_bits[speed];
368 pci_write_config_word(pdev, drive_pci, timing);
369 } else {
370 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
371 speed = adev->dma_mode - XFER_UDMA_0;
372 timing &= ~0x6000;
373 timing |= udma_bits[speed];
374 }
375}
376
377/**
378 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
379 * @ap: Port whose timings we are configuring
380 * @adev: Device to program
381 *
382 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
383 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
384 * the old ide/pci driver.
385 *
386 * LOCKING:
387 * None (inherited from caller).
388 */
389
390static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
391{
392 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
393 int speed = adev->dma_mode - XFER_MW_DMA_0;
394 int drive_pci = sis_port_base(adev);
395 u16 timing;
396
397 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
398 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
399
400 pci_read_config_word(pdev, drive_pci, &timing);
401
402 if (adev->dma_mode < XFER_UDMA_0) {
403 /* bits 3-0 hold recovery timing bits 8-10 active timing and
404 the higer bits are dependant on the device, bit 15 udma */
405 timing &= ~ 0x870F;
406 timing |= mwdma_bits[speed];
407 } else {
408 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
409 speed = adev->dma_mode - XFER_UDMA_0;
410 timing &= ~0x6000;
411 timing |= udma_bits[speed];
412 }
413 pci_write_config_word(pdev, drive_pci, timing);
414}
415
416/**
417 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
418 * @ap: Port whose timings we are configuring
419 * @adev: Device to program
420 *
421 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
422 * Handles UDMA66 and early UDMA100 devices.
423 *
424 * LOCKING:
425 * None (inherited from caller).
426 */
427
428static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
429{
430 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
431 int speed = adev->dma_mode - XFER_MW_DMA_0;
432 int drive_pci = sis_port_base(adev);
433 u16 timing;
434
435 const u16 udma_bits[] = { 0x8B00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
436
437 pci_read_config_word(pdev, drive_pci, &timing);
438
439 if (adev->dma_mode < XFER_UDMA_0) {
440 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
441 } else {
442 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
443 speed = adev->dma_mode - XFER_UDMA_0;
444 timing &= ~0x0F00;
445 timing |= udma_bits[speed];
446 }
447 pci_write_config_word(pdev, drive_pci, timing);
448}
449
450/**
451 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
452 * @ap: Port whose timings we are configuring
453 * @adev: Device to program
454 *
455 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
456 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
457 * the old ide/pci driver.
458 *
459 * LOCKING:
460 * None (inherited from caller).
461 */
462
463static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
464{
465 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
466 int speed = adev->dma_mode - XFER_MW_DMA_0;
467 int drive_pci = sis_port_base(adev);
468 u16 timing;
469
470 const u16 udma_bits[] = { 0x8F00, 0x8A00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
471
472 pci_read_config_word(pdev, drive_pci, &timing);
473
474 if (adev->dma_mode < XFER_UDMA_0) {
475 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
476 } else {
477 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
478 speed = adev->dma_mode - XFER_UDMA_0;
479 timing &= ~0x0F00;
480 timing |= udma_bits[speed];
481 }
482 pci_write_config_word(pdev, drive_pci, timing);
483}
484
485/**
486 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
487 * @ap: Port whose timings we are configuring
488 * @adev: Device to program
489 *
490 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
491 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
492 * the old ide/pci driver.
493 *
494 * LOCKING:
495 * None (inherited from caller).
496 */
497
498static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
499{
500 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
501 int speed = adev->dma_mode - XFER_MW_DMA_0;
502 int port = 0x40;
503 u32 t1;
504 u32 reg54;
505
506 /* bits 4- cycle time 8 - cvs time */
507 const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
508 const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
509
510 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
511 pci_read_config_dword(pdev, 0x54, &reg54);
512 if (reg54 & 0x40000000)
513 port = 0x70;
514 port += (8 * ap->port_no) + (4 * adev->devno);
515
516 pci_read_config_dword(pdev, port, &t1);
517
518 if (adev->dma_mode < XFER_UDMA_0) {
519 t1 &= ~0x00000004;
520 /* FIXME: need data sheet to add MWDMA here. Also lacking on
521 ide/pci driver */
522 } else {
523 speed = adev->dma_mode - XFER_UDMA_0;
524 /* if & 8 no UDMA133 - need info for ... */
525 t1 &= ~0x00000FF0;
526 t1 |= 0x00000004;
527 if (t1 & 0x08)
528 t1 |= timing_u133[speed];
529 else
530 t1 |= timing_u100[speed];
531 }
532 pci_write_config_dword(pdev, port, t1);
533}
534
535static struct scsi_host_template sis_sht = {
536 .module = THIS_MODULE,
537 .name = DRV_NAME,
538 .ioctl = ata_scsi_ioctl,
539 .queuecommand = ata_scsi_queuecmd,
540 .can_queue = ATA_DEF_QUEUE,
541 .this_id = ATA_SHT_THIS_ID,
542 .sg_tablesize = LIBATA_MAX_PRD,
543 .max_sectors = ATA_MAX_SECTORS,
544 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
545 .emulated = ATA_SHT_EMULATED,
546 .use_clustering = ATA_SHT_USE_CLUSTERING,
547 .proc_name = DRV_NAME,
548 .dma_boundary = ATA_DMA_BOUNDARY,
549 .slave_configure = ata_scsi_slave_config,
550 .bios_param = ata_std_bios_param,
551};
552
553static const struct ata_port_operations sis_133_ops = {
554 .port_disable = ata_port_disable,
555 .set_piomode = sis_133_set_piomode,
556 .set_dmamode = sis_133_set_dmamode,
557 .mode_filter = ata_pci_default_filter,
558
559 .tf_load = ata_tf_load,
560 .tf_read = ata_tf_read,
561 .check_status = ata_check_status,
562 .exec_command = ata_exec_command,
563 .dev_select = ata_std_dev_select,
564
565 .freeze = ata_bmdma_freeze,
566 .thaw = ata_bmdma_thaw,
567 .error_handler = sis_133_error_handler,
568 .post_internal_cmd = ata_bmdma_post_internal_cmd,
569
570 .bmdma_setup = ata_bmdma_setup,
571 .bmdma_start = ata_bmdma_start,
572 .bmdma_stop = ata_bmdma_stop,
573 .bmdma_status = ata_bmdma_status,
574 .qc_prep = ata_qc_prep,
575 .qc_issue = ata_qc_issue_prot,
576 .data_xfer = ata_pio_data_xfer,
577
578 .eng_timeout = ata_eng_timeout,
579
580 .irq_handler = ata_interrupt,
581 .irq_clear = ata_bmdma_irq_clear,
582
583 .port_start = ata_port_start,
584 .port_stop = ata_port_stop,
585 .host_stop = ata_host_stop,
586};
587
588static const struct ata_port_operations sis_133_early_ops = {
589 .port_disable = ata_port_disable,
590 .set_piomode = sis_100_set_piomode,
591 .set_dmamode = sis_133_early_set_dmamode,
592 .mode_filter = ata_pci_default_filter,
593
594 .tf_load = ata_tf_load,
595 .tf_read = ata_tf_read,
596 .check_status = ata_check_status,
597 .exec_command = ata_exec_command,
598 .dev_select = ata_std_dev_select,
599
600 .freeze = ata_bmdma_freeze,
601 .thaw = ata_bmdma_thaw,
602 .error_handler = sis_66_error_handler,
603 .post_internal_cmd = ata_bmdma_post_internal_cmd,
604
605 .bmdma_setup = ata_bmdma_setup,
606 .bmdma_start = ata_bmdma_start,
607 .bmdma_stop = ata_bmdma_stop,
608 .bmdma_status = ata_bmdma_status,
609 .qc_prep = ata_qc_prep,
610 .qc_issue = ata_qc_issue_prot,
611 .data_xfer = ata_pio_data_xfer,
612
613 .eng_timeout = ata_eng_timeout,
614
615 .irq_handler = ata_interrupt,
616 .irq_clear = ata_bmdma_irq_clear,
617
618 .port_start = ata_port_start,
619 .port_stop = ata_port_stop,
620 .host_stop = ata_host_stop,
621};
622
623static const struct ata_port_operations sis_100_ops = {
624 .port_disable = ata_port_disable,
625 .set_piomode = sis_100_set_piomode,
626 .set_dmamode = sis_100_set_dmamode,
627 .mode_filter = ata_pci_default_filter,
628
629 .tf_load = ata_tf_load,
630 .tf_read = ata_tf_read,
631 .check_status = ata_check_status,
632 .exec_command = ata_exec_command,
633 .dev_select = ata_std_dev_select,
634
635 .freeze = ata_bmdma_freeze,
636 .thaw = ata_bmdma_thaw,
637 .error_handler = sis_66_error_handler,
638 .post_internal_cmd = ata_bmdma_post_internal_cmd,
639
640
641 .bmdma_setup = ata_bmdma_setup,
642 .bmdma_start = ata_bmdma_start,
643 .bmdma_stop = ata_bmdma_stop,
644 .bmdma_status = ata_bmdma_status,
645 .qc_prep = ata_qc_prep,
646 .qc_issue = ata_qc_issue_prot,
647 .data_xfer = ata_pio_data_xfer,
648
649 .eng_timeout = ata_eng_timeout,
650
651 .irq_handler = ata_interrupt,
652 .irq_clear = ata_bmdma_irq_clear,
653
654 .port_start = ata_port_start,
655 .port_stop = ata_port_stop,
656 .host_stop = ata_host_stop,
657};
658
659static const struct ata_port_operations sis_66_ops = {
660 .port_disable = ata_port_disable,
661 .set_piomode = sis_old_set_piomode,
662 .set_dmamode = sis_66_set_dmamode,
663 .mode_filter = ata_pci_default_filter,
664
665 .tf_load = ata_tf_load,
666 .tf_read = ata_tf_read,
667 .check_status = ata_check_status,
668 .exec_command = ata_exec_command,
669 .dev_select = ata_std_dev_select,
670
671 .freeze = ata_bmdma_freeze,
672 .thaw = ata_bmdma_thaw,
673 .error_handler = sis_66_error_handler,
674 .post_internal_cmd = ata_bmdma_post_internal_cmd,
675
676 .bmdma_setup = ata_bmdma_setup,
677 .bmdma_start = ata_bmdma_start,
678 .bmdma_stop = ata_bmdma_stop,
679 .bmdma_status = ata_bmdma_status,
680 .qc_prep = ata_qc_prep,
681 .qc_issue = ata_qc_issue_prot,
682 .data_xfer = ata_pio_data_xfer,
683
684 .eng_timeout = ata_eng_timeout,
685
686 .irq_handler = ata_interrupt,
687 .irq_clear = ata_bmdma_irq_clear,
688
689 .port_start = ata_port_start,
690 .port_stop = ata_port_stop,
691 .host_stop = ata_host_stop,
692};
693
694static const struct ata_port_operations sis_old_ops = {
695 .port_disable = ata_port_disable,
696 .set_piomode = sis_old_set_piomode,
697 .set_dmamode = sis_old_set_dmamode,
698 .mode_filter = ata_pci_default_filter,
699
700 .tf_load = ata_tf_load,
701 .tf_read = ata_tf_read,
702 .check_status = ata_check_status,
703 .exec_command = ata_exec_command,
704 .dev_select = ata_std_dev_select,
705
706 .freeze = ata_bmdma_freeze,
707 .thaw = ata_bmdma_thaw,
708 .error_handler = sis_old_error_handler,
709 .post_internal_cmd = ata_bmdma_post_internal_cmd,
710
711 .bmdma_setup = ata_bmdma_setup,
712 .bmdma_start = ata_bmdma_start,
713 .bmdma_stop = ata_bmdma_stop,
714 .bmdma_status = ata_bmdma_status,
715 .qc_prep = ata_qc_prep,
716 .qc_issue = ata_qc_issue_prot,
717 .data_xfer = ata_pio_data_xfer,
718
719 .eng_timeout = ata_eng_timeout,
720
721 .irq_handler = ata_interrupt,
722 .irq_clear = ata_bmdma_irq_clear,
723
724 .port_start = ata_port_start,
725 .port_stop = ata_port_stop,
726 .host_stop = ata_host_stop,
727};
728
729static struct ata_port_info sis_info = {
730 .sht = &sis_sht,
731 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
732 .pio_mask = 0x1f, /* pio0-4 */
733 .mwdma_mask = 0x07,
734 .udma_mask = 0,
735 .port_ops = &sis_old_ops,
736};
737static struct ata_port_info sis_info33 = {
738 .sht = &sis_sht,
739 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
740 .pio_mask = 0x1f, /* pio0-4 */
741 .mwdma_mask = 0x07,
742 .udma_mask = ATA_UDMA2, /* UDMA 33 */
743 .port_ops = &sis_old_ops,
744};
745static struct ata_port_info sis_info66 = {
746 .sht = &sis_sht,
747 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
748 .pio_mask = 0x1f, /* pio0-4 */
749 .udma_mask = ATA_UDMA4, /* UDMA 66 */
750 .port_ops = &sis_66_ops,
751};
752static struct ata_port_info sis_info100 = {
753 .sht = &sis_sht,
754 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
755 .pio_mask = 0x1f, /* pio0-4 */
756 .udma_mask = ATA_UDMA5,
757 .port_ops = &sis_100_ops,
758};
759static struct ata_port_info sis_info100_early = {
760 .sht = &sis_sht,
761 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
762 .udma_mask = ATA_UDMA5,
763 .pio_mask = 0x1f, /* pio0-4 */
764 .port_ops = &sis_66_ops,
765};
766static struct ata_port_info sis_info133 = {
767 .sht = &sis_sht,
768 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
769 .pio_mask = 0x1f, /* pio0-4 */
770 .udma_mask = ATA_UDMA6,
771 .port_ops = &sis_133_ops,
772};
773static struct ata_port_info sis_info133_early = {
774 .sht = &sis_sht,
775 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
776 .pio_mask = 0x1f, /* pio0-4 */
777 .udma_mask = ATA_UDMA6,
778 .port_ops = &sis_133_early_ops,
779};
780
781
782static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
783{
784 u16 regw;
785 u8 reg;
786
787 if (sis->info == &sis_info133) {
788 pci_read_config_word(pdev, 0x50, &regw);
789 if (regw & 0x08)
790 pci_write_config_word(pdev, 0x50, regw & ~0x08);
791 pci_read_config_word(pdev, 0x52, &regw);
792 if (regw & 0x08)
793 pci_write_config_word(pdev, 0x52, regw & ~0x08);
794 return;
795 }
796
797 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
798 /* Fix up latency */
799 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
800 /* Set compatibility bit */
801 pci_read_config_byte(pdev, 0x49, &reg);
802 if (!(reg & 0x01))
803 pci_write_config_byte(pdev, 0x49, reg | 0x01);
804 return;
805 }
806
807 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
808 /* Fix up latency */
809 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
810 /* Set compatibility bit */
811 pci_read_config_byte(pdev, 0x52, &reg);
812 if (!(reg & 0x04))
813 pci_write_config_byte(pdev, 0x52, reg | 0x04);
814 return;
815 }
816
817 if (sis->info == &sis_info33) {
818 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
819 if (( reg & 0x0F ) != 0x00)
820 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
821 /* Fall through to ATA16 fixup below */
822 }
823
824 if (sis->info == &sis_info || sis->info == &sis_info33) {
825 /* force per drive recovery and active timings
826 needed on ATA_33 and below chips */
827 pci_read_config_byte(pdev, 0x52, &reg);
828 if (!(reg & 0x08))
829 pci_write_config_byte(pdev, 0x52, reg|0x08);
830 return;
831 }
832
833 BUG();
834}
835
836/**
837 * sis_init_one - Register SiS ATA PCI device with kernel services
838 * @pdev: PCI device to register
839 * @ent: Entry in sis_pci_tbl matching with @pdev
840 *
841 * Called from kernel PCI layer. We probe for combined mode (sigh),
842 * and then hand over control to libata, for it to do the rest.
843 *
844 * LOCKING:
845 * Inherited from PCI layer (may sleep).
846 *
847 * RETURNS:
848 * Zero on success, or -ERRNO value.
849 */
850
851static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
852{
853 static int printed_version;
854 static struct ata_port_info *port_info[2];
855 struct ata_port_info *port;
856 struct pci_dev *host = NULL;
857 struct sis_chipset *chipset = NULL;
858
859 static struct sis_chipset sis_chipsets[] = {
860 { 0x0745, &sis_info100 },
861 { 0x0735, &sis_info100 },
862 { 0x0733, &sis_info100 },
863 { 0x0635, &sis_info100 },
864 { 0x0633, &sis_info100 },
865
866 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
867 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
868
869 { 0x0640, &sis_info66 },
870 { 0x0630, &sis_info66 },
871 { 0x0620, &sis_info66 },
872 { 0x0540, &sis_info66 },
873 { 0x0530, &sis_info66 },
874
875 { 0x5600, &sis_info33 },
876 { 0x5598, &sis_info33 },
877 { 0x5597, &sis_info33 },
878 { 0x5591, &sis_info33 },
879 { 0x5582, &sis_info33 },
880 { 0x5581, &sis_info33 },
881
882 { 0x5596, &sis_info },
883 { 0x5571, &sis_info },
884 { 0x5517, &sis_info },
885 { 0x5511, &sis_info },
886
887 {0}
888 };
889 static struct sis_chipset sis133_early = {
890 0x0, &sis_info133_early
891 };
892 static struct sis_chipset sis133 = {
893 0x0, &sis_info133
894 };
895 static struct sis_chipset sis100_early = {
896 0x0, &sis_info100_early
897 };
898 static struct sis_chipset sis100 = {
899 0x0, &sis_info100
900 };
901
902 if (!printed_version++)
903 dev_printk(KERN_DEBUG, &pdev->dev,
904 "version " DRV_VERSION "\n");
905
906 /* We have to find the bridge first */
907
908 for (chipset = &sis_chipsets[0]; chipset->device; chipset++) {
909 host = pci_get_device(PCI_VENDOR_ID_SI, chipset->device, NULL);
910 if (host != NULL) {
911 if (chipset->device == 0x630) { /* SIS630 */
912 u8 host_rev;
913 pci_read_config_byte(host, PCI_REVISION_ID, &host_rev);
914 if (host_rev >= 0x30) /* 630 ET */
915 chipset = &sis100_early;
916 }
917 break;
918 }
919 }
920
921 /* Look for concealed bridges */
922 if (host == NULL) {
923 /* Second check */
924 u32 idemisc;
925 u16 trueid;
926
927 /* Disable ID masking and register remapping then
928 see what the real ID is */
929
930 pci_read_config_dword(pdev, 0x54, &idemisc);
931 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
932 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
933 pci_write_config_dword(pdev, 0x54, idemisc);
934
935 switch(trueid) {
936 case 0x5518: /* SIS 962/963 */
937 chipset = &sis133;
938 if ((idemisc & 0x40000000) == 0) {
939 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
940 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
941 }
942 break;
943 case 0x0180: /* SIS 965/965L */
944 chipset = &sis133;
945 break;
946 case 0x1180: /* SIS 966/966L */
947 chipset = &sis133;
948 break;
949 }
950 }
951
952 /* Further check */
953 if (chipset == NULL) {
954 struct pci_dev *lpc_bridge;
955 u16 trueid;
956 u8 prefctl;
957 u8 idecfg;
958 u8 sbrev;
959
960 /* Try the second unmasking technique */
961 pci_read_config_byte(pdev, 0x4a, &idecfg);
962 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
963 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
964 pci_write_config_byte(pdev, 0x4a, idecfg);
965
966 switch(trueid) {
967 case 0x5517:
968 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
969 if (lpc_bridge == NULL)
970 break;
971 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
972 pci_read_config_byte(pdev, 0x49, &prefctl);
973 pci_dev_put(lpc_bridge);
974
975 if (sbrev == 0x10 && (prefctl & 0x80)) {
976 chipset = &sis133_early;
977 break;
978 }
979 chipset = &sis100;
980 break;
981 }
982 }
983 pci_dev_put(host);
984
985 /* No chipset info, no support */
986 if (chipset == NULL)
987 return -ENODEV;
988
989 port = chipset->info;
990 port->private_data = chipset;
991
992 sis_fixup(pdev, chipset);
993
994 port_info[0] = port_info[1] = port;
995 return ata_pci_init_one(pdev, port_info, 2);
996}
997
998static const struct pci_device_id sis_pci_tbl[] = {
999 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x5513), }, /* SiS 5513 */
1000 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x5518), }, /* SiS 5518 */
1001 { }
1002};
1003
1004static struct pci_driver sis_pci_driver = {
1005 .name = DRV_NAME,
1006 .id_table = sis_pci_tbl,
1007 .probe = sis_init_one,
1008 .remove = ata_pci_remove_one,
1009};
1010
1011static int __init sis_init(void)
1012{
1013 return pci_register_driver(&sis_pci_driver);
1014}
1015
1016static void __exit sis_exit(void)
1017{
1018 pci_unregister_driver(&sis_pci_driver);
1019}
1020
1021
1022module_init(sis_init);
1023module_exit(sis_exit);
1024
1025MODULE_AUTHOR("Alan Cox");
1026MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1027MODULE_LICENSE("GPL");
1028MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1029MODULE_VERSION(DRV_VERSION);
1030
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
new file mode 100644
index 00000000000..47b290b5604
--- /dev/null
+++ b/drivers/ata/pata_sl82c105.c
@@ -0,0 +1,388 @@
1/*
2 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based in part on linux/drivers/ide/pci/sl82c105.c
7 * SL82C105/Winbond 553 IDE driver
8 *
9 * and in part on the documentation and errata sheet
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/blkdev.h>
17#include <linux/delay.h>
18#include <scsi/scsi_host.h>
19#include <linux/libata.h>
20
21#define DRV_NAME "pata_sl82c105"
22#define DRV_VERSION "0.2.2"
23
24enum {
25 /*
26 * SL82C105 PCI config register 0x40 bits.
27 */
28 CTRL_IDE_IRQB = (1 << 30),
29 CTRL_IDE_IRQA = (1 << 28),
30 CTRL_LEGIRQ = (1 << 11),
31 CTRL_P1F16 = (1 << 5),
32 CTRL_P1EN = (1 << 4),
33 CTRL_P0F16 = (1 << 1),
34 CTRL_P0EN = (1 << 0)
35};
36
37/**
38 * sl82c105_pre_reset - probe begin
39 * @ap: ATA port
40 *
41 * Set up cable type and use generic probe init
42 */
43
44static int sl82c105_pre_reset(struct ata_port *ap)
45{
46 static const struct pci_bits sl82c105_enable_bits[] = {
47 { 0x40, 1, 0x01, 0x01 },
48 { 0x40, 1, 0x10, 0x10 }
49 };
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51
52 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) {
53 ata_port_disable(ap);
54 dev_printk(KERN_INFO, &pdev->dev, "port disabled. ignoring.\n");
55 return 0;
56 }
57 ap->cbl = ATA_CBL_PATA40;
58 return ata_std_prereset(ap);
59}
60
61
62static void sl82c105_error_handler(struct ata_port *ap)
63{
64 ata_bmdma_drive_eh(ap, sl82c105_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
65}
66
67
68/**
69 * sl82c105_configure_piomode - set chip PIO timing
70 * @ap: ATA interface
71 * @adev: ATA device
72 * @pio: PIO mode
73 *
74 * Called to do the PIO mode setup. Our timing registers are shared
75 * so a configure_dmamode call will undo any work we do here and vice
76 * versa
77 */
78
79static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
80{
81 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
82 static u16 pio_timing[5] = {
83 0x50D, 0x407, 0x304, 0x242, 0x240
84 };
85 u16 dummy;
86 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
87
88 pci_write_config_word(pdev, timing, pio_timing[pio]);
89 /* Can we lose this oddity of the old driver */
90 pci_read_config_word(pdev, timing, &dummy);
91}
92
93/**
94 * sl82c105_set_piomode - set initial PIO mode data
95 * @ap: ATA interface
96 * @adev: ATA device
97 *
98 * Called to do the PIO mode setup. Our timing registers are shared
99 * but we want to set the PIO timing by default.
100 */
101
102static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
103{
104 sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
105}
106
107/**
108 * sl82c105_configure_dmamode - set DMA mode in chip
109 * @ap: ATA interface
110 * @adev: ATA device
111 *
112 * Load DMA cycle times into the chip ready for a DMA transfer
113 * to occur.
114 */
115
116static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
117{
118 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
119 static u16 dma_timing[3] = {
120 0x707, 0x201, 0x200
121 };
122 u16 dummy;
123 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
124 int dma = adev->dma_mode - XFER_MW_DMA_0;
125
126 pci_write_config_word(pdev, timing, dma_timing[dma]);
127 /* Can we lose this oddity of the old driver */
128 pci_read_config_word(pdev, timing, &dummy);
129}
130
131/**
132 * sl82c105_set_dmamode - set initial DMA mode data
133 * @ap: ATA interface
134 * @adev: ATA device
135 *
136 * Called to do the DMA mode setup. This replaces the PIO timings
137 * for the device in question. Set appropriate PIO timings not DMA
138 * timings at this point.
139 */
140
141static void sl82c105_set_dmamode(struct ata_port *ap, struct ata_device *adev)
142{
143 switch(adev->dma_mode) {
144 case XFER_MW_DMA_0:
145 sl82c105_configure_piomode(ap, adev, 1);
146 break;
147 case XFER_MW_DMA_1:
148 sl82c105_configure_piomode(ap, adev, 3);
149 break;
150 case XFER_MW_DMA_2:
151 sl82c105_configure_piomode(ap, adev, 3);
152 break;
153 default:
154 BUG();
155 }
156}
157
158/**
159 * sl82c105_reset_engine - Reset the DMA engine
160 * @ap: ATA interface
161 *
162 * The sl82c105 has some serious problems with the DMA engine
163 * when transfers don't run as expected or ATAPI is used. The
164 * recommended fix is to reset the engine each use using a chip
165 * test register.
166 */
167
168static void sl82c105_reset_engine(struct ata_port *ap)
169{
170 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
171 u16 val;
172
173 pci_read_config_word(pdev, 0x7E, &val);
174 pci_write_config_word(pdev, 0x7E, val | 4);
175 pci_write_config_word(pdev, 0x7E, val & ~4);
176}
177
178/**
179 * sl82c105_bmdma_start - DMA engine begin
180 * @qc: ATA command
181 *
182 * Reset the DMA engine each use as recommended by the errata
183 * document.
184 *
185 * FIXME: if we switch clock at BMDMA start/end we might get better
186 * PIO performance on DMA capable devices.
187 */
188
189static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
190{
191 struct ata_port *ap = qc->ap;
192
193 sl82c105_reset_engine(ap);
194
195 /* Set the clocks for DMA */
196 sl82c105_configure_dmamode(ap, qc->dev);
197 /* Activate DMA */
198 ata_bmdma_start(qc);
199}
200
201/**
202 * sl82c105_bmdma_end - DMA engine stop
203 * @qc: ATA command
204 *
205 * Reset the DMA engine each use as recommended by the errata
206 * document.
207 *
208 * This function is also called to turn off DMA when a timeout occurs
209 * during DMA operation. In both cases we need to reset the engine,
210 * so no actual eng_timeout handler is required.
211 *
212 * We assume bmdma_stop is always called if bmdma_start as called. If
213 * not then we may need to wrap qc_issue.
214 */
215
216static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
217{
218 struct ata_port *ap = qc->ap;
219
220 ata_bmdma_stop(qc);
221 sl82c105_reset_engine(ap);
222
223 /* This will redo the initial setup of the DMA device to matching
224 PIO timings */
225 sl82c105_set_dmamode(ap, qc->dev);
226}
227
228static struct scsi_host_template sl82c105_sht = {
229 .module = THIS_MODULE,
230 .name = DRV_NAME,
231 .ioctl = ata_scsi_ioctl,
232 .queuecommand = ata_scsi_queuecmd,
233 .can_queue = ATA_DEF_QUEUE,
234 .this_id = ATA_SHT_THIS_ID,
235 .sg_tablesize = LIBATA_MAX_PRD,
236 .max_sectors = ATA_MAX_SECTORS,
237 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
238 .emulated = ATA_SHT_EMULATED,
239 .use_clustering = ATA_SHT_USE_CLUSTERING,
240 .proc_name = DRV_NAME,
241 .dma_boundary = ATA_DMA_BOUNDARY,
242 .slave_configure = ata_scsi_slave_config,
243 .bios_param = ata_std_bios_param,
244};
245
246static struct ata_port_operations sl82c105_port_ops = {
247 .port_disable = ata_port_disable,
248 .set_piomode = sl82c105_set_piomode,
249 .set_dmamode = sl82c105_set_dmamode,
250 .mode_filter = ata_pci_default_filter,
251
252 .tf_load = ata_tf_load,
253 .tf_read = ata_tf_read,
254 .check_status = ata_check_status,
255 .exec_command = ata_exec_command,
256 .dev_select = ata_std_dev_select,
257
258 .error_handler = sl82c105_error_handler,
259
260 .bmdma_setup = ata_bmdma_setup,
261 .bmdma_start = sl82c105_bmdma_start,
262 .bmdma_stop = sl82c105_bmdma_stop,
263 .bmdma_status = ata_bmdma_status,
264
265 .qc_prep = ata_qc_prep,
266 .qc_issue = ata_qc_issue_prot,
267 .eng_timeout = ata_eng_timeout,
268 .data_xfer = ata_pio_data_xfer,
269
270 .irq_handler = ata_interrupt,
271 .irq_clear = ata_bmdma_irq_clear,
272
273 .port_start = ata_port_start,
274 .port_stop = ata_port_stop,
275 .host_stop = ata_host_stop
276};
277
278/**
279 * sl82c105_bridge_revision - find bridge version
280 * @pdev: PCI device for the ATA function
281 *
282 * Locates the PCI bridge associated with the ATA function and
283 * providing it is a Winbond 553 reports the revision. If it cannot
284 * find a revision or the right device it returns -1
285 */
286
287static int sl82c105_bridge_revision(struct pci_dev *pdev)
288{
289 struct pci_dev *bridge;
290 u8 rev;
291
292 /*
293 * The bridge should be part of the same device, but function 0.
294 */
295 bridge = pci_get_slot(pdev->bus,
296 PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
297 if (!bridge)
298 return -1;
299
300 /*
301 * Make sure it is a Winbond 553 and is an ISA bridge.
302 */
303 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
304 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
305 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
306 pci_dev_put(bridge);
307 return -1;
308 }
309 /*
310 * We need to find function 0's revision, not function 1
311 */
312 pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
313
314 pci_dev_put(bridge);
315 return rev;
316}
317
318
319static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
320{
321 static struct ata_port_info info_dma = {
322 .sht = &sl82c105_sht,
323 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
324 .pio_mask = 0x1f,
325 .mwdma_mask = 0x07,
326 .port_ops = &sl82c105_port_ops
327 };
328 static struct ata_port_info info_early = {
329 .sht = &sl82c105_sht,
330 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
331 .pio_mask = 0x1f,
332 .port_ops = &sl82c105_port_ops
333 };
334 static struct ata_port_info *port_info[2] = { &info_early, &info_early };
335 u32 val;
336 int rev;
337
338 rev = sl82c105_bridge_revision(dev);
339
340 if (rev == -1)
341 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
342 else if (rev <= 5)
343 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
344 else {
345 port_info[0] = &info_dma;
346 port_info[1] = &info_dma;
347 }
348
349 pci_read_config_dword(dev, 0x40, &val);
350 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
351 pci_write_config_dword(dev, 0x40, val);
352
353
354 return ata_pci_init_one(dev, port_info, 1); /* For now */
355}
356
357static struct pci_device_id sl82c105[] = {
358 { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
359 { 0, },
360};
361
362static struct pci_driver sl82c105_pci_driver = {
363 .name = DRV_NAME,
364 .id_table = sl82c105,
365 .probe = sl82c105_init_one,
366 .remove = ata_pci_remove_one
367};
368
369static int __init sl82c105_init(void)
370{
371 return pci_register_driver(&sl82c105_pci_driver);
372}
373
374
375static void __exit sl82c105_exit(void)
376{
377 pci_unregister_driver(&sl82c105_pci_driver);
378}
379
380
381MODULE_AUTHOR("Alan Cox");
382MODULE_DESCRIPTION("low-level driver for Sl82c105");
383MODULE_LICENSE("GPL");
384MODULE_DEVICE_TABLE(pci, sl82c105);
385MODULE_VERSION(DRV_VERSION);
386
387module_init(sl82c105_init);
388module_exit(sl82c105_exit);
diff --git a/drivers/ata/pata_triflex.c b/drivers/ata/pata_triflex.c
new file mode 100644
index 00000000000..7dd6ea3a21e
--- /dev/null
+++ b/drivers/ata/pata_triflex.c
@@ -0,0 +1,285 @@
1/*
2 * pata_triflex.c - Compaq PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * triflex.c
9 *
10 * IDE Chipset driver for the Compaq TriFlex IDE controller.
11 *
12 * Known to work with the Compaq Workstation 5x00 series.
13 *
14 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
15 * Author: Torben Mathiasen <torben.mathiasen@hp.com>
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 *
30 * Loosely based on the piix & svwks drivers.
31 *
32 * Documentation:
33 * Not publically available.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/blkdev.h>
41#include <linux/delay.h>
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "pata_triflex"
46#define DRV_VERSION "0.2.5"
47
48/**
49 * triflex_probe_init - probe begin
50 * @ap: ATA port
51 *
52 * Set up cable type and use generic probe init
53 */
54
55static int triflex_probe_init(struct ata_port *ap)
56{
57 static const struct pci_bits triflex_enable_bits[] = {
58 { 0x80, 1, 0x01, 0x01 },
59 { 0x80, 1, 0x02, 0x02 }
60 };
61
62 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63
64 if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no])) {
65 ata_port_disable(ap);
66 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
67 return 0;
68 }
69 ap->cbl = ATA_CBL_PATA40;
70 return ata_std_prereset(ap);
71}
72
73
74
75static void triflex_error_handler(struct ata_port *ap)
76{
77 ata_bmdma_drive_eh(ap, triflex_probe_init, ata_std_softreset, NULL, ata_std_postreset);
78}
79
80/**
81 * triflex_load_timing - timing configuration
82 * @ap: ATA interface
83 * @adev: Device on the bus
84 * @speed: speed to configure
85 *
86 * The Triflex has one set of timings per device per channel. This
87 * means we must do some switching. As the PIO and DMA timings don't
88 * match we have to do some reloading unlike PIIX devices where tuning
89 * tricks can avoid it.
90 */
91
92static void triflex_load_timing(struct ata_port *ap, struct ata_device *adev, int speed)
93{
94 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
95 u32 timing = 0;
96 u32 triflex_timing, old_triflex_timing;
97 int channel_offset = ap->port_no ? 0x74: 0x70;
98 unsigned int is_slave = (adev->devno != 0);
99
100
101 pci_read_config_dword(pdev, channel_offset, &old_triflex_timing);
102 triflex_timing = old_triflex_timing;
103
104 switch(speed)
105 {
106 case XFER_MW_DMA_2:
107 timing = 0x0103;break;
108 case XFER_MW_DMA_1:
109 timing = 0x0203;break;
110 case XFER_MW_DMA_0:
111 timing = 0x0808;break;
112 case XFER_SW_DMA_2:
113 case XFER_SW_DMA_1:
114 case XFER_SW_DMA_0:
115 timing = 0x0F0F;break;
116 case XFER_PIO_4:
117 timing = 0x0202;break;
118 case XFER_PIO_3:
119 timing = 0x0204;break;
120 case XFER_PIO_2:
121 timing = 0x0404;break;
122 case XFER_PIO_1:
123 timing = 0x0508;break;
124 case XFER_PIO_0:
125 timing = 0x0808;break;
126 default:
127 BUG();
128 }
129 triflex_timing &= ~ (0xFFFF << (16 * is_slave));
130 triflex_timing |= (timing << (16 * is_slave));
131
132 if (triflex_timing != old_triflex_timing)
133 pci_write_config_dword(pdev, channel_offset, triflex_timing);
134}
135
136/**
137 * triflex_set_piomode - set initial PIO mode data
138 * @ap: ATA interface
139 * @adev: ATA device
140 *
141 * Use the timing loader to set up the PIO mode. We have to do this
142 * because DMA start/stop will only be called once DMA occurs. If there
143 * has been no DMA then the PIO timings are still needed.
144 */
145static void triflex_set_piomode(struct ata_port *ap, struct ata_device *adev)
146{
147 triflex_load_timing(ap, adev, adev->pio_mode);
148}
149
150/**
151 * triflex_dma_start - DMA start callback
152 * @qc: Command in progress
153 *
154 * Usually drivers set the DMA timing at the point the set_dmamode call
155 * is made. Triflex however requires we load new timings on the
156 * transition or keep matching PIO/DMA pairs (ie MWDMA2/PIO4 etc).
157 * We load the DMA timings just before starting DMA and then restore
158 * the PIO timing when the DMA is finished.
159 */
160
161static void triflex_bmdma_start(struct ata_queued_cmd *qc)
162{
163 triflex_load_timing(qc->ap, qc->dev, qc->dev->dma_mode);
164 ata_bmdma_start(qc);
165}
166
167/**
168 * triflex_dma_stop - DMA stop callback
169 * @ap: ATA interface
170 * @adev: ATA device
171 *
172 * We loaded new timings in dma_start, as a result we need to restore
173 * the PIO timings in dma_stop so that the next command issue gets the
174 * right clock values.
175 */
176
177static void triflex_bmdma_stop(struct ata_queued_cmd *qc)
178{
179 ata_bmdma_stop(qc);
180 triflex_load_timing(qc->ap, qc->dev, qc->dev->pio_mode);
181}
182
183static struct scsi_host_template triflex_sht = {
184 .module = THIS_MODULE,
185 .name = DRV_NAME,
186 .ioctl = ata_scsi_ioctl,
187 .queuecommand = ata_scsi_queuecmd,
188 .can_queue = ATA_DEF_QUEUE,
189 .this_id = ATA_SHT_THIS_ID,
190 .sg_tablesize = LIBATA_MAX_PRD,
191 .max_sectors = ATA_MAX_SECTORS,
192 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
193 .emulated = ATA_SHT_EMULATED,
194 .use_clustering = ATA_SHT_USE_CLUSTERING,
195 .proc_name = DRV_NAME,
196 .dma_boundary = ATA_DMA_BOUNDARY,
197 .slave_configure = ata_scsi_slave_config,
198 .bios_param = ata_std_bios_param,
199};
200
201static struct ata_port_operations triflex_port_ops = {
202 .port_disable = ata_port_disable,
203 .set_piomode = triflex_set_piomode,
204 .mode_filter = ata_pci_default_filter,
205
206 .tf_load = ata_tf_load,
207 .tf_read = ata_tf_read,
208 .check_status = ata_check_status,
209 .exec_command = ata_exec_command,
210 .dev_select = ata_std_dev_select,
211
212 .freeze = ata_bmdma_freeze,
213 .thaw = ata_bmdma_thaw,
214 .error_handler = triflex_error_handler,
215 .post_internal_cmd = ata_bmdma_post_internal_cmd,
216
217 .bmdma_setup = ata_bmdma_setup,
218 .bmdma_start = triflex_bmdma_start,
219 .bmdma_stop = triflex_bmdma_stop,
220 .bmdma_status = ata_bmdma_status,
221
222 .qc_prep = ata_qc_prep,
223 .qc_issue = ata_qc_issue_prot,
224 .eng_timeout = ata_eng_timeout,
225 .data_xfer = ata_pio_data_xfer,
226
227 .irq_handler = ata_interrupt,
228 .irq_clear = ata_bmdma_irq_clear,
229
230 .port_start = ata_port_start,
231 .port_stop = ata_port_stop,
232 .host_stop = ata_host_stop
233};
234
235static int triflex_init_one(struct pci_dev *dev, const struct pci_device_id *id)
236{
237 static struct ata_port_info info = {
238 .sht = &triflex_sht,
239 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
240 .pio_mask = 0x1f,
241 .mwdma_mask = 0x07,
242 .port_ops = &triflex_port_ops
243 };
244 static struct ata_port_info *port_info[2] = { &info, &info };
245 static int printed_version;
246
247 if (!printed_version++)
248 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
249
250 return ata_pci_init_one(dev, port_info, 2);
251}
252
253static const struct pci_device_id triflex[] = {
254 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
256 { 0, },
257};
258
259static struct pci_driver triflex_pci_driver = {
260 .name = DRV_NAME,
261 .id_table = triflex,
262 .probe = triflex_init_one,
263 .remove = ata_pci_remove_one
264};
265
266static int __init triflex_init(void)
267{
268 return pci_register_driver(&triflex_pci_driver);
269}
270
271
272static void __exit triflex_exit(void)
273{
274 pci_unregister_driver(&triflex_pci_driver);
275}
276
277
278MODULE_AUTHOR("Alan Cox");
279MODULE_DESCRIPTION("low-level driver for Compaq Triflex");
280MODULE_LICENSE("GPL");
281MODULE_DEVICE_TABLE(pci, triflex);
282MODULE_VERSION(DRV_VERSION);
283
284module_init(triflex_init);
285module_exit(triflex_exit);
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
new file mode 100644
index 00000000000..2580e1606d9
--- /dev/null
+++ b/drivers/ata/pata_via.c
@@ -0,0 +1,568 @@
1/*
2 * pata_via.c - VIA PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
26 *
27 * Most registers remain compatible across chips. Others start reserved
28 * and acquire sensible semantics if set to 1 (eg cable detect). A few
29 * exceptions exist, notably around the FIFO settings.
30 *
31 * One additional quirk of the VIA design is that like ALi they use few
32 * PCI IDs for a lot of chips.
33 *
34 * Based heavily on:
35 *
36 * Version 3.38
37 *
38 * VIA IDE driver for Linux. Supported southbridges:
39 *
40 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
41 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
42 * vt8235, vt8237
43 *
44 * Copyright (c) 2000-2002 Vojtech Pavlik
45 *
46 * Based on the work of:
47 * Michel Aubry
48 * Jeff Garzik
49 * Andre Hedrick
50
51 */
52
53#include <linux/kernel.h>
54#include <linux/module.h>
55#include <linux/pci.h>
56#include <linux/init.h>
57#include <linux/blkdev.h>
58#include <linux/delay.h>
59#include <scsi/scsi_host.h>
60#include <linux/libata.h>
61
62#define DRV_NAME "pata_via"
63#define DRV_VERSION "0.1.13"
64
65/*
66 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
67 * driver.
68 */
69
70enum {
71 VIA_UDMA = 0x007,
72 VIA_UDMA_NONE = 0x000,
73 VIA_UDMA_33 = 0x001,
74 VIA_UDMA_66 = 0x002,
75 VIA_UDMA_100 = 0x003,
76 VIA_UDMA_133 = 0x004,
77 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
78 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
79 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
80 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
81 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
82 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
83 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
84};
85
86/*
87 * VIA SouthBridge chips.
88 */
89
90static const struct via_isa_bridge {
91 const char *name;
92 u16 id;
93 u8 rev_min;
94 u8 rev_max;
95 u16 flags;
96} via_isa_bridges[] = {
97 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
98 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
99 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
100 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
101 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
102 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
103 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
104 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
105 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
106 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
107 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
108 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
109 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
110 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
111 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
112 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
113 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
114 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
115 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
116 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
117 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
118 { NULL }
119};
120
121/**
122 * via_cable_detect - cable detection
123 * @ap: ATA port
124 *
125 * Perform cable detection. Actually for the VIA case the BIOS
126 * already did this for us. We read the values provided by the
127 * BIOS. If you are using an 8235 in a non-PC configuration you
128 * may need to update this code.
129 *
130 * Hotplug also impacts on this.
131 */
132
133static int via_cable_detect(struct ata_port *ap) {
134 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
135 u32 ata66;
136
137 pci_read_config_dword(pdev, 0x50, &ata66);
138 /* Check both the drive cable reporting bits, we might not have
139 two drives */
140 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
141 return ATA_CBL_PATA80;
142 else
143 return ATA_CBL_PATA40;
144}
145
146static int via_pre_reset(struct ata_port *ap)
147{
148 const struct via_isa_bridge *config = ap->host->private_data;
149
150 if (!(config->flags & VIA_NO_ENABLES)) {
151 static const struct pci_bits via_enable_bits[] = {
152 { 0x40, 1, 0x02, 0x02 },
153 { 0x40, 1, 0x01, 0x01 }
154 };
155
156 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
157
158 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) {
159 ata_port_disable(ap);
160 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
161 return 0;
162 }
163 }
164
165 if ((config->flags & VIA_UDMA) >= VIA_UDMA_66)
166 ap->cbl = via_cable_detect(ap);
167 else
168 ap->cbl = ATA_CBL_PATA40;
169 return ata_std_prereset(ap);
170}
171
172
173/**
174 * via_error_handler - reset for VIA chips
175 * @ap: ATA port
176 *
177 * Handle the reset callback for the later chips with cable detect
178 */
179
180static void via_error_handler(struct ata_port *ap)
181{
182 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
183}
184
185/**
186 * via_do_set_mode - set initial PIO mode data
187 * @ap: ATA interface
188 * @adev: ATA device
189 * @mode: ATA mode being programmed
190 * @tdiv: Clocks per PCI clock
191 * @set_ast: Set to program address setup
192 * @udma_type: UDMA mode/format of registers
193 *
194 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
195 * support in order to compute modes.
196 *
197 * FIXME: Hotplug will require we serialize multiple mode changes
198 * on the two channels.
199 */
200
201static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
202{
203 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
204 struct ata_device *peer = ata_dev_pair(adev);
205 struct ata_timing t, p;
206 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
207 unsigned long T = 1000000000 / via_clock;
208 unsigned long UT = T/tdiv;
209 int ut;
210 int offset = 3 - (2*ap->port_no) - adev->devno;
211
212
213 /* Calculate the timing values we require */
214 ata_timing_compute(adev, mode, &t, T, UT);
215
216 /* We share 8bit timing so we must merge the constraints */
217 if (peer) {
218 if (peer->pio_mode) {
219 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
220 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
221 }
222 }
223
224 /* Address setup is programmable but breaks on UDMA133 setups */
225 if (set_ast) {
226 u8 setup; /* 2 bits per drive */
227 int shift = 2 * offset;
228
229 pci_read_config_byte(pdev, 0x4C, &setup);
230 setup &= ~(3 << shift);
231 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
232 pci_write_config_byte(pdev, 0x4C, setup);
233 }
234
235 /* Load the PIO mode bits */
236 pci_write_config_byte(pdev, 0x4F - ap->port_no,
237 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
238 pci_write_config_byte(pdev, 0x48 + offset,
239 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));
240
241 /* Load the UDMA bits according to type */
242 switch(udma_type) {
243 default:
244 /* BUG() ? */
245 /* fall through */
246 case 33:
247 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
248 break;
249 case 66:
250 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
251 break;
252 case 100:
253 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
254 break;
255 case 133:
256 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
257 break;
258 }
259 /* Set UDMA unless device is not UDMA capable */
260 if (udma_type)
261 pci_write_config_byte(pdev, 0x50 + offset, ut);
262}
263
264static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
265{
266 const struct via_isa_bridge *config = ap->host->private_data;
267 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
268 int mode = config->flags & VIA_UDMA;
269 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
270 static u8 udma[5] = { 0, 33, 66, 100, 133 };
271
272 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
273}
274
275static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
276{
277 const struct via_isa_bridge *config = ap->host->private_data;
278 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
279 int mode = config->flags & VIA_UDMA;
280 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
281 static u8 udma[5] = { 0, 33, 66, 100, 133 };
282
283 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
284}
285
286static struct scsi_host_template via_sht = {
287 .module = THIS_MODULE,
288 .name = DRV_NAME,
289 .ioctl = ata_scsi_ioctl,
290 .queuecommand = ata_scsi_queuecmd,
291 .can_queue = ATA_DEF_QUEUE,
292 .this_id = ATA_SHT_THIS_ID,
293 .sg_tablesize = LIBATA_MAX_PRD,
294 .max_sectors = ATA_MAX_SECTORS,
295 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
296 .emulated = ATA_SHT_EMULATED,
297 .use_clustering = ATA_SHT_USE_CLUSTERING,
298 .proc_name = DRV_NAME,
299 .dma_boundary = ATA_DMA_BOUNDARY,
300 .slave_configure = ata_scsi_slave_config,
301 .bios_param = ata_std_bios_param,
302};
303
304static struct ata_port_operations via_port_ops = {
305 .port_disable = ata_port_disable,
306 .set_piomode = via_set_piomode,
307 .set_dmamode = via_set_dmamode,
308 .mode_filter = ata_pci_default_filter,
309
310 .tf_load = ata_tf_load,
311 .tf_read = ata_tf_read,
312 .check_status = ata_check_status,
313 .exec_command = ata_exec_command,
314 .dev_select = ata_std_dev_select,
315
316 .freeze = ata_bmdma_freeze,
317 .thaw = ata_bmdma_thaw,
318 .error_handler = via_error_handler,
319 .post_internal_cmd = ata_bmdma_post_internal_cmd,
320
321 .bmdma_setup = ata_bmdma_setup,
322 .bmdma_start = ata_bmdma_start,
323 .bmdma_stop = ata_bmdma_stop,
324 .bmdma_status = ata_bmdma_status,
325
326 .qc_prep = ata_qc_prep,
327 .qc_issue = ata_qc_issue_prot,
328 .eng_timeout = ata_eng_timeout,
329 .data_xfer = ata_pio_data_xfer,
330
331 .irq_handler = ata_interrupt,
332 .irq_clear = ata_bmdma_irq_clear,
333
334 .port_start = ata_port_start,
335 .port_stop = ata_port_stop,
336 .host_stop = ata_host_stop
337};
338
339static struct ata_port_operations via_port_ops_noirq = {
340 .port_disable = ata_port_disable,
341 .set_piomode = via_set_piomode,
342 .set_dmamode = via_set_dmamode,
343 .mode_filter = ata_pci_default_filter,
344
345 .tf_load = ata_tf_load,
346 .tf_read = ata_tf_read,
347 .check_status = ata_check_status,
348 .exec_command = ata_exec_command,
349 .dev_select = ata_std_dev_select,
350
351 .freeze = ata_bmdma_freeze,
352 .thaw = ata_bmdma_thaw,
353 .error_handler = via_error_handler,
354 .post_internal_cmd = ata_bmdma_post_internal_cmd,
355
356 .bmdma_setup = ata_bmdma_setup,
357 .bmdma_start = ata_bmdma_start,
358 .bmdma_stop = ata_bmdma_stop,
359 .bmdma_status = ata_bmdma_status,
360
361 .qc_prep = ata_qc_prep,
362 .qc_issue = ata_qc_issue_prot,
363 .eng_timeout = ata_eng_timeout,
364 .data_xfer = ata_pio_data_xfer_noirq,
365
366 .irq_handler = ata_interrupt,
367 .irq_clear = ata_bmdma_irq_clear,
368
369 .port_start = ata_port_start,
370 .port_stop = ata_port_stop,
371 .host_stop = ata_host_stop
372};
373
374/**
375 * via_init_one - discovery callback
376 * @pdev: PCI device ID
377 * @id: PCI table info
378 *
379 * A VIA IDE interface has been discovered. Figure out what revision
380 * and perform configuration work before handing it to the ATA layer
381 */
382
383static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
384{
385 /* Early VIA without UDMA support */
386 static struct ata_port_info via_mwdma_info = {
387 .sht = &via_sht,
388 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
389 .pio_mask = 0x1f,
390 .mwdma_mask = 0x07,
391 .port_ops = &via_port_ops
392 };
393 /* Ditto with IRQ masking required */
394 static struct ata_port_info via_mwdma_info_borked = {
395 .sht = &via_sht,
396 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
397 .pio_mask = 0x1f,
398 .mwdma_mask = 0x07,
399 .port_ops = &via_port_ops_noirq,
400 };
401 /* VIA UDMA 33 devices (and borked 66) */
402 static struct ata_port_info via_udma33_info = {
403 .sht = &via_sht,
404 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
405 .pio_mask = 0x1f,
406 .mwdma_mask = 0x07,
407 .udma_mask = 0x7,
408 .port_ops = &via_port_ops
409 };
410 /* VIA UDMA 66 devices */
411 static struct ata_port_info via_udma66_info = {
412 .sht = &via_sht,
413 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
414 .pio_mask = 0x1f,
415 .mwdma_mask = 0x07,
416 .udma_mask = 0x1f,
417 .port_ops = &via_port_ops
418 };
419 /* VIA UDMA 100 devices */
420 static struct ata_port_info via_udma100_info = {
421 .sht = &via_sht,
422 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
423 .pio_mask = 0x1f,
424 .mwdma_mask = 0x07,
425 .udma_mask = 0x3f,
426 .port_ops = &via_port_ops
427 };
428 /* UDMA133 with bad AST (All current 133) */
429 static struct ata_port_info via_udma133_info = {
430 .sht = &via_sht,
431 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
432 .pio_mask = 0x1f,
433 .mwdma_mask = 0x07,
434 .udma_mask = 0x7f, /* FIXME: should check north bridge */
435 .port_ops = &via_port_ops
436 };
437 struct ata_port_info *port_info[2], *type;
438 struct pci_dev *isa = NULL;
439 const struct via_isa_bridge *config;
440 static int printed_version;
441 u8 t;
442 u8 enable;
443 u32 timing;
444
445 if (!printed_version++)
446 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
447
448 /* To find out how the IDE will behave and what features we
449 actually have to look at the bridge not the IDE controller */
450 for (config = via_isa_bridges; config->id; config++)
451 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
452 !!(config->flags & VIA_BAD_ID),
453 config->id, NULL))) {
454
455 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
456 if (t >= config->rev_min &&
457 t <= config->rev_max)
458 break;
459 pci_dev_put(isa);
460 }
461
462 if (!config->id) {
463 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
464 return -ENODEV;
465 }
466 pci_dev_put(isa);
467
468 /* 0x40 low bits indicate enabled channels */
469 pci_read_config_byte(pdev, 0x40 , &enable);
470 enable &= 3;
471 if (enable == 0) {
472 return -ENODEV;
473 }
474
475 /* Initialise the FIFO for the enabled channels. */
476 if (config->flags & VIA_SET_FIFO) {
477 u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
478 u8 fifo;
479
480 pci_read_config_byte(pdev, 0x43, &fifo);
481
482 /* Clear PREQ# until DDACK# for errata */
483 if (config->flags & VIA_BAD_PREQ)
484 fifo &= 0x7F;
485 else
486 fifo &= 0x9f;
487 /* Turn on FIFO for enabled channels */
488 fifo |= fifo_setting[enable];
489 pci_write_config_byte(pdev, 0x43, fifo);
490 }
491 /* Clock set up */
492 switch(config->flags & VIA_UDMA) {
493 case VIA_UDMA_NONE:
494 if (config->flags & VIA_NO_UNMASK)
495 type = &via_mwdma_info_borked;
496 else
497 type = &via_mwdma_info;
498 break;
499 case VIA_UDMA_33:
500 type = &via_udma33_info;
501 break;
502 case VIA_UDMA_66:
503 type = &via_udma66_info;
504 /* The 66 MHz devices require we enable the clock */
505 pci_read_config_dword(pdev, 0x50, &timing);
506 timing |= 0x80008;
507 pci_write_config_dword(pdev, 0x50, timing);
508 break;
509 case VIA_UDMA_100:
510 type = &via_udma100_info;
511 break;
512 case VIA_UDMA_133:
513 type = &via_udma133_info;
514 break;
515 default:
516 WARN_ON(1);
517 return -ENODEV;
518 }
519
520 if (config->flags & VIA_BAD_CLK66) {
521 /* Disable the 66MHz clock on problem devices */
522 pci_read_config_dword(pdev, 0x50, &timing);
523 timing &= ~0x80008;
524 pci_write_config_dword(pdev, 0x50, timing);
525 }
526
527 /* We have established the device type, now fire it up */
528 type->private_data = (void *)config;
529
530 port_info[0] = port_info[1] = type;
531 return ata_pci_init_one(pdev, port_info, 2);
532}
533
534static const struct pci_device_id via[] = {
535 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1), },
536 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1), },
537 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410), },
538 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
539 { 0, },
540};
541
542static struct pci_driver via_pci_driver = {
543 .name = DRV_NAME,
544 .id_table = via,
545 .probe = via_init_one,
546 .remove = ata_pci_remove_one
547};
548
549static int __init via_init(void)
550{
551 return pci_register_driver(&via_pci_driver);
552}
553
554
555static void __exit via_exit(void)
556{
557 pci_unregister_driver(&via_pci_driver);
558}
559
560
561MODULE_AUTHOR("Alan Cox");
562MODULE_DESCRIPTION("low-level driver for VIA PATA");
563MODULE_LICENSE("GPL");
564MODULE_DEVICE_TABLE(pci, via);
565MODULE_VERSION(DRV_VERSION);
566
567module_init(via_init);
568module_exit(via_exit);