diff options
Diffstat (limited to 'drivers/video')
81 files changed, 6109 insertions, 3419 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 344c3759530..1132ba5ff39 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig | |||
@@ -5,6 +5,11 @@ | |||
5 | menu "Graphics support" | 5 | menu "Graphics support" |
6 | 6 | ||
7 | source "drivers/video/backlight/Kconfig" | 7 | source "drivers/video/backlight/Kconfig" |
8 | source "drivers/video/display/Kconfig" | ||
9 | |||
10 | config VGASTATE | ||
11 | tristate | ||
12 | default n | ||
8 | 13 | ||
9 | config FB | 14 | config FB |
10 | tristate "Support for frame buffer devices" | 15 | tristate "Support for frame buffer devices" |
@@ -90,6 +95,43 @@ config FB_CFB_IMAGEBLIT | |||
90 | blitting. This is used by drivers that don't provide their own | 95 | blitting. This is used by drivers that don't provide their own |
91 | (accelerated) version. | 96 | (accelerated) version. |
92 | 97 | ||
98 | config FB_SYS_FILLRECT | ||
99 | tristate | ||
100 | depends on FB | ||
101 | default n | ||
102 | ---help--- | ||
103 | Include the sys_fillrect function for generic software rectangle | ||
104 | filling. This is used by drivers that don't provide their own | ||
105 | (accelerated) version and the framebuffer is in system RAM. | ||
106 | |||
107 | config FB_SYS_COPYAREA | ||
108 | tristate | ||
109 | depends on FB | ||
110 | default n | ||
111 | ---help--- | ||
112 | Include the sys_copyarea function for generic software area copying. | ||
113 | This is used by drivers that don't provide their own (accelerated) | ||
114 | version and the framebuffer is in system RAM. | ||
115 | |||
116 | config FB_SYS_IMAGEBLIT | ||
117 | tristate | ||
118 | depends on FB | ||
119 | default n | ||
120 | ---help--- | ||
121 | Include the sys_imageblit function for generic software image | ||
122 | blitting. This is used by drivers that don't provide their own | ||
123 | (accelerated) version and the framebuffer is in system RAM. | ||
124 | |||
125 | config FB_SYS_FOPS | ||
126 | tristate | ||
127 | depends on FB | ||
128 | default n | ||
129 | |||
130 | config FB_DEFERRED_IO | ||
131 | bool | ||
132 | depends on FB | ||
133 | default y | ||
134 | |||
93 | config FB_SVGALIB | 135 | config FB_SVGALIB |
94 | tristate | 136 | tristate |
95 | depends on FB | 137 | depends on FB |
@@ -375,9 +417,10 @@ config FB_FM2 | |||
375 | config FB_ARC | 417 | config FB_ARC |
376 | tristate "Arc Monochrome LCD board support" | 418 | tristate "Arc Monochrome LCD board support" |
377 | depends on FB && X86 | 419 | depends on FB && X86 |
378 | select FB_CFB_FILLRECT | 420 | select FB_SYS_FILLRECT |
379 | select FB_CFB_COPYAREA | 421 | select FB_SYS_COPYAREA |
380 | select FB_CFB_IMAGEBLIT | 422 | select FB_SYS_IMAGEBLIT |
423 | select FB_SYS_FOPS | ||
381 | help | 424 | help |
382 | This enables support for the Arc Monochrome LCD board. The board | 425 | This enables support for the Arc Monochrome LCD board. The board |
383 | is based on the KS-108 lcd controller and is typically a matrix | 426 | is based on the KS-108 lcd controller and is typically a matrix |
@@ -475,6 +518,8 @@ config FB_VGA16 | |||
475 | select FB_CFB_FILLRECT | 518 | select FB_CFB_FILLRECT |
476 | select FB_CFB_COPYAREA | 519 | select FB_CFB_COPYAREA |
477 | select FB_CFB_IMAGEBLIT | 520 | select FB_CFB_IMAGEBLIT |
521 | select VGASTATE | ||
522 | select FONT_8x16 if FRAMEBUFFER_CONSOLE | ||
478 | help | 523 | help |
479 | This is the frame buffer device driver for VGA 16 color graphic | 524 | This is the frame buffer device driver for VGA 16 color graphic |
480 | cards. Say Y if you have such a card. | 525 | cards. Say Y if you have such a card. |
@@ -519,15 +564,25 @@ config FB_HP300 | |||
519 | default y | 564 | default y |
520 | 565 | ||
521 | config FB_TGA | 566 | config FB_TGA |
522 | tristate "TGA framebuffer support" | 567 | tristate "TGA/SFB+ framebuffer support" |
523 | depends on FB && ALPHA | 568 | depends on FB && (ALPHA || TC) |
524 | select FB_CFB_FILLRECT | 569 | select FB_CFB_FILLRECT |
525 | select FB_CFB_COPYAREA | 570 | select FB_CFB_COPYAREA |
526 | select FB_CFB_IMAGEBLIT | 571 | select FB_CFB_IMAGEBLIT |
527 | select BITREVERSE | 572 | select BITREVERSE |
528 | help | 573 | ---help--- |
529 | This is the frame buffer device driver for generic TGA graphic | 574 | This is the frame buffer device driver for generic TGA and SFB+ |
530 | cards. Say Y if you have one of those. | 575 | graphic cards. These include DEC ZLXp-E1, -E2 and -E3 PCI cards, |
576 | also known as PBXGA-A, -B and -C, and DEC ZLX-E1, -E2 and -E3 | ||
577 | TURBOchannel cards, also known as PMAGD-A, -B and -C. | ||
578 | |||
579 | Due to hardware limitations ZLX-E2 and E3 cards are not supported | ||
580 | for DECstation 5000/200 systems. Additionally due to firmware | ||
581 | limitations these cards may cause troubles with booting DECstation | ||
582 | 5000/240 and /260 systems, but are fully supported under Linux if | ||
583 | you manage to get it going. ;-) | ||
584 | |||
585 | Say Y if you have one of those. | ||
531 | 586 | ||
532 | config FB_VESA | 587 | config FB_VESA |
533 | bool "VESA VGA graphics support" | 588 | bool "VESA VGA graphics support" |
@@ -551,6 +606,21 @@ config FB_IMAC | |||
551 | help | 606 | help |
552 | This is the frame buffer device driver for the Intel-based Macintosh | 607 | This is the frame buffer device driver for the Intel-based Macintosh |
553 | 608 | ||
609 | config FB_HECUBA | ||
610 | tristate "Hecuba board support" | ||
611 | depends on FB && X86 && MMU | ||
612 | select FB_SYS_FILLRECT | ||
613 | select FB_SYS_COPYAREA | ||
614 | select FB_SYS_IMAGEBLIT | ||
615 | select FB_SYS_FOPS | ||
616 | select FB_DEFERRED_IO | ||
617 | help | ||
618 | This enables support for the Hecuba board. This driver was tested | ||
619 | with an E-Ink 800x600 display and x86 SBCs through a 16 bit GPIO | ||
620 | interface (8 bit data, 4 bit control). If you anticpate using | ||
621 | this driver, say Y or M; otherwise say N. You must specify the | ||
622 | GPIO IO address to be used for setting control and data. | ||
623 | |||
554 | config FB_HGA | 624 | config FB_HGA |
555 | tristate "Hercules mono graphics support" | 625 | tristate "Hercules mono graphics support" |
556 | depends on FB && X86 | 626 | depends on FB && X86 |
@@ -686,6 +756,7 @@ config FB_NVIDIA | |||
686 | select FB_CFB_COPYAREA | 756 | select FB_CFB_COPYAREA |
687 | select FB_CFB_IMAGEBLIT | 757 | select FB_CFB_IMAGEBLIT |
688 | select BITREVERSE | 758 | select BITREVERSE |
759 | select VGASTATE | ||
689 | help | 760 | help |
690 | This driver supports graphics boards with the nVidia chips, TNT | 761 | This driver supports graphics boards with the nVidia chips, TNT |
691 | and newer. For very old chipsets, such as the RIVA128, then use | 762 | and newer. For very old chipsets, such as the RIVA128, then use |
@@ -724,6 +795,7 @@ config FB_RIVA | |||
724 | select FB_CFB_COPYAREA | 795 | select FB_CFB_COPYAREA |
725 | select FB_CFB_IMAGEBLIT | 796 | select FB_CFB_IMAGEBLIT |
726 | select BITREVERSE | 797 | select BITREVERSE |
798 | select VGASTATE | ||
727 | help | 799 | help |
728 | This driver supports graphics boards with the nVidia Riva/Geforce | 800 | This driver supports graphics boards with the nVidia Riva/Geforce |
729 | chips. | 801 | chips. |
@@ -770,6 +842,7 @@ config FB_I810 | |||
770 | select FB_CFB_FILLRECT | 842 | select FB_CFB_FILLRECT |
771 | select FB_CFB_COPYAREA | 843 | select FB_CFB_COPYAREA |
772 | select FB_CFB_IMAGEBLIT | 844 | select FB_CFB_IMAGEBLIT |
845 | select VGASTATE | ||
773 | help | 846 | help |
774 | This driver supports the on-board graphics built in to the Intel 810 | 847 | This driver supports the on-board graphics built in to the Intel 810 |
775 | and 815 chipsets. Say Y if you have and plan to use such a board. | 848 | and 815 chipsets. Say Y if you have and plan to use such a board. |
@@ -809,6 +882,22 @@ config FB_I810_I2C | |||
809 | select FB_DDC | 882 | select FB_DDC |
810 | help | 883 | help |
811 | 884 | ||
885 | config FB_LE80578 | ||
886 | tristate "Intel LE80578 (Vermilion) support" | ||
887 | depends on FB && PCI && X86 | ||
888 | select FB_MODE_HELPERS | ||
889 | select FB_CFB_FILLRECT | ||
890 | select FB_CFB_COPYAREA | ||
891 | select FB_CFB_IMAGEBLIT | ||
892 | help | ||
893 | This driver supports the LE80578 (Vermilion Range) chipset | ||
894 | |||
895 | config FB_CARILLO_RANCH | ||
896 | tristate "Intel Carillo Ranch support" | ||
897 | depends on FB_LE80578 && FB && PCI && X86 | ||
898 | help | ||
899 | This driver supports the LE80578 (Carillo Ranch) board | ||
900 | |||
812 | config FB_INTEL | 901 | config FB_INTEL |
813 | tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G support (EXPERIMENTAL)" | 902 | tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G support (EXPERIMENTAL)" |
814 | depends on FB && EXPERIMENTAL && PCI && X86 | 903 | depends on FB && EXPERIMENTAL && PCI && X86 |
@@ -1120,6 +1209,8 @@ config FB_S3 | |||
1120 | select FB_CFB_IMAGEBLIT | 1209 | select FB_CFB_IMAGEBLIT |
1121 | select FB_TILEBLITTING | 1210 | select FB_TILEBLITTING |
1122 | select FB_SVGALIB | 1211 | select FB_SVGALIB |
1212 | select VGASTATE | ||
1213 | select FONT_8x16 if FRAMEBUFFER_CONSOLE | ||
1123 | ---help--- | 1214 | ---help--- |
1124 | Driver for graphics boards with S3 Trio / S3 Virge chip. | 1215 | Driver for graphics boards with S3 Trio / S3 Virge chip. |
1125 | 1216 | ||
@@ -1130,6 +1221,7 @@ config FB_SAVAGE | |||
1130 | select FB_CFB_FILLRECT | 1221 | select FB_CFB_FILLRECT |
1131 | select FB_CFB_COPYAREA | 1222 | select FB_CFB_COPYAREA |
1132 | select FB_CFB_IMAGEBLIT | 1223 | select FB_CFB_IMAGEBLIT |
1224 | select VGASTATE | ||
1133 | help | 1225 | help |
1134 | This driver supports notebooks and computers with S3 Savage PCI/AGP | 1226 | This driver supports notebooks and computers with S3 Savage PCI/AGP |
1135 | chips. | 1227 | chips. |
@@ -1196,6 +1288,7 @@ config FB_NEOMAGIC | |||
1196 | select FB_CFB_FILLRECT | 1288 | select FB_CFB_FILLRECT |
1197 | select FB_CFB_COPYAREA | 1289 | select FB_CFB_COPYAREA |
1198 | select FB_CFB_IMAGEBLIT | 1290 | select FB_CFB_IMAGEBLIT |
1291 | select VGASTATE | ||
1199 | help | 1292 | help |
1200 | This driver supports notebooks with NeoMagic PCI chips. | 1293 | This driver supports notebooks with NeoMagic PCI chips. |
1201 | Say Y if you have such a graphics card. | 1294 | Say Y if you have such a graphics card. |
@@ -1662,13 +1755,25 @@ config FB_PS3_DEFAULT_SIZE_M | |||
1662 | The default value can be overridden on the kernel command line | 1755 | The default value can be overridden on the kernel command line |
1663 | using the "ps3fb" option (e.g. "ps3fb=9M"); | 1756 | using the "ps3fb" option (e.g. "ps3fb=9M"); |
1664 | 1757 | ||
1665 | config FB_VIRTUAL | 1758 | config FB_XILINX |
1666 | tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)" | 1759 | tristate "Xilinx frame buffer support" |
1667 | depends on FB | 1760 | depends on FB && XILINX_VIRTEX |
1668 | select FB_CFB_FILLRECT | 1761 | select FB_CFB_FILLRECT |
1669 | select FB_CFB_COPYAREA | 1762 | select FB_CFB_COPYAREA |
1670 | select FB_CFB_IMAGEBLIT | 1763 | select FB_CFB_IMAGEBLIT |
1671 | ---help--- | 1764 | ---help--- |
1765 | Include support for the Xilinx ML300/ML403 reference design | ||
1766 | framebuffer. ML300 carries a 640*480 LCD display on the board, | ||
1767 | ML403 uses a standard DB15 VGA connector. | ||
1768 | |||
1769 | config FB_VIRTUAL | ||
1770 | tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)" | ||
1771 | depends on FB | ||
1772 | select FB_SYS_FILLRECT | ||
1773 | select FB_SYS_COPYAREA | ||
1774 | select FB_SYS_IMAGEBLIT | ||
1775 | select FB_SYS_FOPS | ||
1776 | ---help--- | ||
1672 | This is a `virtual' frame buffer device. It operates on a chunk of | 1777 | This is a `virtual' frame buffer device. It operates on a chunk of |
1673 | unswappable kernel memory instead of on the memory of a graphics | 1778 | unswappable kernel memory instead of on the memory of a graphics |
1674 | board. This means you cannot see any output sent to this frame | 1779 | board. This means you cannot see any output sent to this frame |
diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 558473d040d..a916c204274 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile | |||
@@ -4,6 +4,7 @@ | |||
4 | 4 | ||
5 | # Each configuration option enables a list of files. | 5 | # Each configuration option enables a list of files. |
6 | 6 | ||
7 | obj-$(CONFIG_VGASTATE) += vgastate.o | ||
7 | obj-y += fb_notify.o | 8 | obj-y += fb_notify.o |
8 | obj-$(CONFIG_FB) += fb.o | 9 | obj-$(CONFIG_FB) += fb.o |
9 | fb-y := fbmem.o fbmon.o fbcmap.o fbsysfs.o \ | 10 | fb-y := fbmem.o fbmon.o fbcmap.o fbsysfs.o \ |
@@ -12,14 +13,19 @@ fb-objs := $(fb-y) | |||
12 | 13 | ||
13 | obj-$(CONFIG_VT) += console/ | 14 | obj-$(CONFIG_VT) += console/ |
14 | obj-$(CONFIG_LOGO) += logo/ | 15 | obj-$(CONFIG_LOGO) += logo/ |
15 | obj-y += backlight/ | 16 | obj-y += backlight/ display/ |
16 | 17 | ||
17 | obj-$(CONFIG_FB_CFB_FILLRECT) += cfbfillrect.o | 18 | obj-$(CONFIG_FB_CFB_FILLRECT) += cfbfillrect.o |
18 | obj-$(CONFIG_FB_CFB_COPYAREA) += cfbcopyarea.o | 19 | obj-$(CONFIG_FB_CFB_COPYAREA) += cfbcopyarea.o |
19 | obj-$(CONFIG_FB_CFB_IMAGEBLIT) += cfbimgblt.o | 20 | obj-$(CONFIG_FB_CFB_IMAGEBLIT) += cfbimgblt.o |
21 | obj-$(CONFIG_FB_SYS_FILLRECT) += sysfillrect.o | ||
22 | obj-$(CONFIG_FB_SYS_COPYAREA) += syscopyarea.o | ||
23 | obj-$(CONFIG_FB_SYS_IMAGEBLIT) += sysimgblt.o | ||
24 | obj-$(CONFIG_FB_SYS_FOPS) += fb_sys_fops.o | ||
20 | obj-$(CONFIG_FB_SVGALIB) += svgalib.o | 25 | obj-$(CONFIG_FB_SVGALIB) += svgalib.o |
21 | obj-$(CONFIG_FB_MACMODES) += macmodes.o | 26 | obj-$(CONFIG_FB_MACMODES) += macmodes.o |
22 | obj-$(CONFIG_FB_DDC) += fb_ddc.o | 27 | obj-$(CONFIG_FB_DDC) += fb_ddc.o |
28 | obj-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o | ||
23 | 29 | ||
24 | # Hardware specific drivers go first | 30 | # Hardware specific drivers go first |
25 | obj-$(CONFIG_FB_AMIGA) += amifb.o c2p.o | 31 | obj-$(CONFIG_FB_AMIGA) += amifb.o c2p.o |
@@ -30,7 +36,7 @@ obj-$(CONFIG_FB_PM2) += pm2fb.o | |||
30 | obj-$(CONFIG_FB_PM3) += pm3fb.o | 36 | obj-$(CONFIG_FB_PM3) += pm3fb.o |
31 | 37 | ||
32 | obj-$(CONFIG_FB_MATROX) += matrox/ | 38 | obj-$(CONFIG_FB_MATROX) += matrox/ |
33 | obj-$(CONFIG_FB_RIVA) += riva/ vgastate.o | 39 | obj-$(CONFIG_FB_RIVA) += riva/ |
34 | obj-$(CONFIG_FB_NVIDIA) += nvidia/ | 40 | obj-$(CONFIG_FB_NVIDIA) += nvidia/ |
35 | obj-$(CONFIG_FB_ATY) += aty/ macmodes.o | 41 | obj-$(CONFIG_FB_ATY) += aty/ macmodes.o |
36 | obj-$(CONFIG_FB_ATY128) += aty/ macmodes.o | 42 | obj-$(CONFIG_FB_ATY128) += aty/ macmodes.o |
@@ -40,8 +46,7 @@ obj-$(CONFIG_FB_KYRO) += kyro/ | |||
40 | obj-$(CONFIG_FB_SAVAGE) += savage/ | 46 | obj-$(CONFIG_FB_SAVAGE) += savage/ |
41 | obj-$(CONFIG_FB_GEODE) += geode/ | 47 | obj-$(CONFIG_FB_GEODE) += geode/ |
42 | obj-$(CONFIG_FB_MBX) += mbx/ | 48 | obj-$(CONFIG_FB_MBX) += mbx/ |
43 | obj-$(CONFIG_FB_I810) += vgastate.o | 49 | obj-$(CONFIG_FB_NEOMAGIC) += neofb.o |
44 | obj-$(CONFIG_FB_NEOMAGIC) += neofb.o vgastate.o | ||
45 | obj-$(CONFIG_FB_3DFX) += tdfxfb.o | 50 | obj-$(CONFIG_FB_3DFX) += tdfxfb.o |
46 | obj-$(CONFIG_FB_CONTROL) += controlfb.o | 51 | obj-$(CONFIG_FB_CONTROL) += controlfb.o |
47 | obj-$(CONFIG_FB_PLATINUM) += platinumfb.o | 52 | obj-$(CONFIG_FB_PLATINUM) += platinumfb.o |
@@ -51,7 +56,8 @@ obj-$(CONFIG_FB_IMSTT) += imsttfb.o | |||
51 | obj-$(CONFIG_FB_FM2) += fm2fb.o | 56 | obj-$(CONFIG_FB_FM2) += fm2fb.o |
52 | obj-$(CONFIG_FB_CYBLA) += cyblafb.o | 57 | obj-$(CONFIG_FB_CYBLA) += cyblafb.o |
53 | obj-$(CONFIG_FB_TRIDENT) += tridentfb.o | 58 | obj-$(CONFIG_FB_TRIDENT) += tridentfb.o |
54 | obj-$(CONFIG_FB_S3) += s3fb.o vgastate.o | 59 | obj-$(CONFIG_FB_LE80578) += vermilion/ |
60 | obj-$(CONFIG_FB_S3) += s3fb.o | ||
55 | obj-$(CONFIG_FB_STI) += stifb.o | 61 | obj-$(CONFIG_FB_STI) += stifb.o |
56 | obj-$(CONFIG_FB_FFB) += ffb.o sbuslib.o | 62 | obj-$(CONFIG_FB_FFB) += ffb.o sbuslib.o |
57 | obj-$(CONFIG_FB_CG6) += cg6.o sbuslib.o | 63 | obj-$(CONFIG_FB_CG6) += cg6.o sbuslib.o |
@@ -66,6 +72,7 @@ obj-$(CONFIG_FB_ACORN) += acornfb.o | |||
66 | obj-$(CONFIG_FB_ATARI) += atafb.o c2p.o atafb_mfb.o \ | 72 | obj-$(CONFIG_FB_ATARI) += atafb.o c2p.o atafb_mfb.o \ |
67 | atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o | 73 | atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o |
68 | obj-$(CONFIG_FB_MAC) += macfb.o | 74 | obj-$(CONFIG_FB_MAC) += macfb.o |
75 | obj-$(CONFIG_FB_HECUBA) += hecubafb.o | ||
69 | obj-$(CONFIG_FB_HGA) += hgafb.o | 76 | obj-$(CONFIG_FB_HGA) += hgafb.o |
70 | obj-$(CONFIG_FB_XVR500) += sunxvr500.o | 77 | obj-$(CONFIG_FB_XVR500) += sunxvr500.o |
71 | obj-$(CONFIG_FB_XVR2500) += sunxvr2500.o | 78 | obj-$(CONFIG_FB_XVR2500) += sunxvr2500.o |
@@ -102,11 +109,12 @@ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ | |||
102 | obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o | 109 | obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o |
103 | obj-$(CONFIG_FB_PS3) += ps3fb.o | 110 | obj-$(CONFIG_FB_PS3) += ps3fb.o |
104 | obj-$(CONFIG_FB_SM501) += sm501fb.o | 111 | obj-$(CONFIG_FB_SM501) += sm501fb.o |
112 | obj-$(CONFIG_FB_XILINX) += xilinxfb.o | ||
105 | 113 | ||
106 | # Platform or fallback drivers go here | 114 | # Platform or fallback drivers go here |
107 | obj-$(CONFIG_FB_VESA) += vesafb.o | 115 | obj-$(CONFIG_FB_VESA) += vesafb.o |
108 | obj-$(CONFIG_FB_IMAC) += imacfb.o | 116 | obj-$(CONFIG_FB_IMAC) += imacfb.o |
109 | obj-$(CONFIG_FB_VGA16) += vga16fb.o vgastate.o | 117 | obj-$(CONFIG_FB_VGA16) += vga16fb.o |
110 | obj-$(CONFIG_FB_OF) += offb.o | 118 | obj-$(CONFIG_FB_OF) += offb.o |
111 | 119 | ||
112 | # the test framebuffer is last | 120 | # the test framebuffer is last |
diff --git a/drivers/video/arcfb.c b/drivers/video/arcfb.c index 30a8369757e..db15baca3f7 100644 --- a/drivers/video/arcfb.c +++ b/drivers/video/arcfb.c | |||
@@ -262,7 +262,8 @@ static void arcfb_lcd_update_page(struct arcfb_par *par, unsigned int upper, | |||
262 | ks108_set_yaddr(par, chipindex, upper/8); | 262 | ks108_set_yaddr(par, chipindex, upper/8); |
263 | 263 | ||
264 | linesize = par->info->var.xres/8; | 264 | linesize = par->info->var.xres/8; |
265 | src = par->info->screen_base + (left/8) + (upper * linesize); | 265 | src = (unsigned char __force *) par->info->screen_base + (left/8) + |
266 | (upper * linesize); | ||
266 | ks108_set_xaddr(par, chipindex, left); | 267 | ks108_set_xaddr(par, chipindex, left); |
267 | 268 | ||
268 | bitmask=1; | 269 | bitmask=1; |
@@ -368,7 +369,7 @@ static void arcfb_fillrect(struct fb_info *info, | |||
368 | { | 369 | { |
369 | struct arcfb_par *par = info->par; | 370 | struct arcfb_par *par = info->par; |
370 | 371 | ||
371 | cfb_fillrect(info, rect); | 372 | sys_fillrect(info, rect); |
372 | 373 | ||
373 | /* update the physical lcd */ | 374 | /* update the physical lcd */ |
374 | arcfb_lcd_update(par, rect->dx, rect->dy, rect->width, rect->height); | 375 | arcfb_lcd_update(par, rect->dx, rect->dy, rect->width, rect->height); |
@@ -379,7 +380,7 @@ static void arcfb_copyarea(struct fb_info *info, | |||
379 | { | 380 | { |
380 | struct arcfb_par *par = info->par; | 381 | struct arcfb_par *par = info->par; |
381 | 382 | ||
382 | cfb_copyarea(info, area); | 383 | sys_copyarea(info, area); |
383 | 384 | ||
384 | /* update the physical lcd */ | 385 | /* update the physical lcd */ |
385 | arcfb_lcd_update(par, area->dx, area->dy, area->width, area->height); | 386 | arcfb_lcd_update(par, area->dx, area->dy, area->width, area->height); |
@@ -389,7 +390,7 @@ static void arcfb_imageblit(struct fb_info *info, const struct fb_image *image) | |||
389 | { | 390 | { |
390 | struct arcfb_par *par = info->par; | 391 | struct arcfb_par *par = info->par; |
391 | 392 | ||
392 | cfb_imageblit(info, image); | 393 | sys_imageblit(info, image); |
393 | 394 | ||
394 | /* update the physical lcd */ | 395 | /* update the physical lcd */ |
395 | arcfb_lcd_update(par, image->dx, image->dy, image->width, | 396 | arcfb_lcd_update(par, image->dx, image->dy, image->width, |
@@ -439,14 +440,11 @@ static int arcfb_ioctl(struct fb_info *info, | |||
439 | * the fb. it's inefficient for them to do anything less than 64*8 | 440 | * the fb. it's inefficient for them to do anything less than 64*8 |
440 | * writes since we update the lcd in each write() anyway. | 441 | * writes since we update the lcd in each write() anyway. |
441 | */ | 442 | */ |
442 | static ssize_t arcfb_write(struct file *file, const char __user *buf, size_t count, | 443 | static ssize_t arcfb_write(struct fb_info *info, const char __user *buf, |
443 | loff_t *ppos) | 444 | size_t count, loff_t *ppos) |
444 | { | 445 | { |
445 | /* modded from epson 1355 */ | 446 | /* modded from epson 1355 */ |
446 | 447 | ||
447 | struct inode *inode; | ||
448 | int fbidx; | ||
449 | struct fb_info *info; | ||
450 | unsigned long p; | 448 | unsigned long p; |
451 | int err=-EINVAL; | 449 | int err=-EINVAL; |
452 | unsigned int fbmemlength,x,y,w,h, bitppos, startpos, endpos, bitcount; | 450 | unsigned int fbmemlength,x,y,w,h, bitppos, startpos, endpos, bitcount; |
@@ -454,13 +452,6 @@ static ssize_t arcfb_write(struct file *file, const char __user *buf, size_t cou | |||
454 | unsigned int xres; | 452 | unsigned int xres; |
455 | 453 | ||
456 | p = *ppos; | 454 | p = *ppos; |
457 | inode = file->f_path.dentry->d_inode; | ||
458 | fbidx = iminor(inode); | ||
459 | info = registered_fb[fbidx]; | ||
460 | |||
461 | if (!info || !info->screen_base) | ||
462 | return -ENODEV; | ||
463 | |||
464 | par = info->par; | 455 | par = info->par; |
465 | xres = info->var.xres; | 456 | xres = info->var.xres; |
466 | fbmemlength = (xres * info->var.yres)/8; | 457 | fbmemlength = (xres * info->var.yres)/8; |
@@ -477,7 +468,7 @@ static ssize_t arcfb_write(struct file *file, const char __user *buf, size_t cou | |||
477 | if (count) { | 468 | if (count) { |
478 | char *base_addr; | 469 | char *base_addr; |
479 | 470 | ||
480 | base_addr = info->screen_base; | 471 | base_addr = (char __force *)info->screen_base; |
481 | count -= copy_from_user(base_addr + p, buf, count); | 472 | count -= copy_from_user(base_addr + p, buf, count); |
482 | *ppos += count; | 473 | *ppos += count; |
483 | err = -EFAULT; | 474 | err = -EFAULT; |
@@ -503,6 +494,7 @@ static ssize_t arcfb_write(struct file *file, const char __user *buf, size_t cou | |||
503 | static struct fb_ops arcfb_ops = { | 494 | static struct fb_ops arcfb_ops = { |
504 | .owner = THIS_MODULE, | 495 | .owner = THIS_MODULE, |
505 | .fb_open = arcfb_open, | 496 | .fb_open = arcfb_open, |
497 | .fb_read = fb_sys_read, | ||
506 | .fb_write = arcfb_write, | 498 | .fb_write = arcfb_write, |
507 | .fb_release = arcfb_release, | 499 | .fb_release = arcfb_release, |
508 | .fb_pan_display = arcfb_pan_display, | 500 | .fb_pan_display = arcfb_pan_display, |
@@ -603,7 +595,7 @@ static int arcfb_remove(struct platform_device *dev) | |||
603 | 595 | ||
604 | if (info) { | 596 | if (info) { |
605 | unregister_framebuffer(info); | 597 | unregister_framebuffer(info); |
606 | vfree(info->screen_base); | 598 | vfree((void __force *)info->screen_base); |
607 | framebuffer_release(info); | 599 | framebuffer_release(info); |
608 | } | 600 | } |
609 | return 0; | 601 | return 0; |
diff --git a/drivers/video/aty/ati_ids.h b/drivers/video/aty/ati_ids.h index 39ab483fc25..90e7df22f50 100644 --- a/drivers/video/aty/ati_ids.h +++ b/drivers/video/aty/ati_ids.h | |||
@@ -209,4 +209,4 @@ | |||
209 | #define PCI_CHIP_R423_5D57 0x5D57 | 209 | #define PCI_CHIP_R423_5D57 0x5D57 |
210 | #define PCI_CHIP_RS350_7834 0x7834 | 210 | #define PCI_CHIP_RS350_7834 0x7834 |
211 | #define PCI_CHIP_RS350_7835 0x7835 | 211 | #define PCI_CHIP_RS350_7835 0x7835 |
212 | 212 | #define PCI_CHIP_RS480_5955 0x5955 | |
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c index e86d7e0c982..7fea4d8ae8e 100644 --- a/drivers/video/aty/aty128fb.c +++ b/drivers/video/aty/aty128fb.c | |||
@@ -2165,18 +2165,29 @@ static void __devexit aty128_remove(struct pci_dev *pdev) | |||
2165 | static int aty128fb_blank(int blank, struct fb_info *fb) | 2165 | static int aty128fb_blank(int blank, struct fb_info *fb) |
2166 | { | 2166 | { |
2167 | struct aty128fb_par *par = fb->par; | 2167 | struct aty128fb_par *par = fb->par; |
2168 | u8 state = 0; | 2168 | u8 state; |
2169 | 2169 | ||
2170 | if (par->lock_blank || par->asleep) | 2170 | if (par->lock_blank || par->asleep) |
2171 | return 0; | 2171 | return 0; |
2172 | 2172 | ||
2173 | if (blank & FB_BLANK_VSYNC_SUSPEND) | 2173 | switch (blank) { |
2174 | state |= 2; | 2174 | case FB_BLANK_NORMAL: |
2175 | if (blank & FB_BLANK_HSYNC_SUSPEND) | 2175 | state = 4; |
2176 | state |= 1; | 2176 | break; |
2177 | if (blank & FB_BLANK_POWERDOWN) | 2177 | case FB_BLANK_VSYNC_SUSPEND: |
2178 | state |= 4; | 2178 | state = 6; |
2179 | 2179 | break; | |
2180 | case FB_BLANK_HSYNC_SUSPEND: | ||
2181 | state = 5; | ||
2182 | break; | ||
2183 | case FB_BLANK_POWERDOWN: | ||
2184 | state = 7; | ||
2185 | break; | ||
2186 | case FB_BLANK_UNBLANK: | ||
2187 | default: | ||
2188 | state = 0; | ||
2189 | break; | ||
2190 | } | ||
2180 | aty_st_8(CRTC_EXT_CNTL+1, state); | 2191 | aty_st_8(CRTC_EXT_CNTL+1, state); |
2181 | 2192 | ||
2182 | if (par->chip_gen == rage_M3) { | 2193 | if (par->chip_gen == rage_M3) { |
@@ -2430,7 +2441,7 @@ static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |||
2430 | wait_for_idle(par); | 2441 | wait_for_idle(par); |
2431 | 2442 | ||
2432 | /* Blank display and LCD */ | 2443 | /* Blank display and LCD */ |
2433 | aty128fb_blank(VESA_POWERDOWN, info); | 2444 | aty128fb_blank(FB_BLANK_POWERDOWN, info); |
2434 | 2445 | ||
2435 | /* Sleep */ | 2446 | /* Sleep */ |
2436 | par->asleep = 1; | 2447 | par->asleep = 1; |
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c index 8514f2a6f06..ea67dd902d4 100644 --- a/drivers/video/aty/atyfb_base.c +++ b/drivers/video/aty/atyfb_base.c | |||
@@ -2297,20 +2297,6 @@ static int __devinit aty_init(struct fb_info *info) | |||
2297 | par->pll_limits.xclk = 53; | 2297 | par->pll_limits.xclk = 53; |
2298 | } | 2298 | } |
2299 | #endif | 2299 | #endif |
2300 | if (pll) | ||
2301 | par->pll_limits.pll_max = pll; | ||
2302 | if (mclk) | ||
2303 | par->pll_limits.mclk = mclk; | ||
2304 | if (xclk) | ||
2305 | par->pll_limits.xclk = xclk; | ||
2306 | |||
2307 | aty_calc_mem_refresh(par, par->pll_limits.xclk); | ||
2308 | par->pll_per = 1000000/par->pll_limits.pll_max; | ||
2309 | par->mclk_per = 1000000/par->pll_limits.mclk; | ||
2310 | par->xclk_per = 1000000/par->pll_limits.xclk; | ||
2311 | |||
2312 | par->ref_clk_per = 1000000000000ULL / 14318180; | ||
2313 | xtal = "14.31818"; | ||
2314 | 2300 | ||
2315 | #ifdef CONFIG_FB_ATY_GX | 2301 | #ifdef CONFIG_FB_ATY_GX |
2316 | if (!M64_HAS(INTEGRATED)) { | 2302 | if (!M64_HAS(INTEGRATED)) { |
@@ -2338,6 +2324,7 @@ static int __devinit aty_init(struct fb_info *info) | |||
2338 | case DAC_IBMRGB514: | 2324 | case DAC_IBMRGB514: |
2339 | par->dac_ops = &aty_dac_ibm514; | 2325 | par->dac_ops = &aty_dac_ibm514; |
2340 | break; | 2326 | break; |
2327 | #ifdef CONFIG_ATARI | ||
2341 | case DAC_ATI68860_B: | 2328 | case DAC_ATI68860_B: |
2342 | case DAC_ATI68860_C: | 2329 | case DAC_ATI68860_C: |
2343 | par->dac_ops = &aty_dac_ati68860b; | 2330 | par->dac_ops = &aty_dac_ati68860b; |
@@ -2346,6 +2333,7 @@ static int __devinit aty_init(struct fb_info *info) | |||
2346 | case DAC_ATT21C498: | 2333 | case DAC_ATT21C498: |
2347 | par->dac_ops = &aty_dac_att21c498; | 2334 | par->dac_ops = &aty_dac_att21c498; |
2348 | break; | 2335 | break; |
2336 | #endif | ||
2349 | default: | 2337 | default: |
2350 | PRINTKI("aty_init: DAC type not implemented yet!\n"); | 2338 | PRINTKI("aty_init: DAC type not implemented yet!\n"); |
2351 | par->dac_ops = &aty_dac_unsupported; | 2339 | par->dac_ops = &aty_dac_unsupported; |
@@ -2389,8 +2377,29 @@ static int __devinit aty_init(struct fb_info *info) | |||
2389 | /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ | 2377 | /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ |
2390 | if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM) | 2378 | if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM) |
2391 | par->pll_limits.mclk = 63; | 2379 | par->pll_limits.mclk = 63; |
2380 | /* Mobility + 32bit memory interface need halved XCLK. */ | ||
2381 | if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32) | ||
2382 | par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1; | ||
2392 | } | 2383 | } |
2384 | #endif | ||
2393 | 2385 | ||
2386 | /* Allow command line to override clocks. */ | ||
2387 | if (pll) | ||
2388 | par->pll_limits.pll_max = pll; | ||
2389 | if (mclk) | ||
2390 | par->pll_limits.mclk = mclk; | ||
2391 | if (xclk) | ||
2392 | par->pll_limits.xclk = xclk; | ||
2393 | |||
2394 | aty_calc_mem_refresh(par, par->pll_limits.xclk); | ||
2395 | par->pll_per = 1000000/par->pll_limits.pll_max; | ||
2396 | par->mclk_per = 1000000/par->pll_limits.mclk; | ||
2397 | par->xclk_per = 1000000/par->pll_limits.xclk; | ||
2398 | |||
2399 | par->ref_clk_per = 1000000000000ULL / 14318180; | ||
2400 | xtal = "14.31818"; | ||
2401 | |||
2402 | #ifdef CONFIG_FB_ATY_CT | ||
2394 | if (M64_HAS(GTB_DSP)) { | 2403 | if (M64_HAS(GTB_DSP)) { |
2395 | u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); | 2404 | u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); |
2396 | 2405 | ||
diff --git a/drivers/video/aty/mach64_ct.c b/drivers/video/aty/mach64_ct.c index 1fdcfdbf669..cc9e9779b75 100644 --- a/drivers/video/aty/mach64_ct.c +++ b/drivers/video/aty/mach64_ct.c | |||
@@ -608,12 +608,10 @@ static void aty_resume_pll_ct(const struct fb_info *info, | |||
608 | aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par); | 608 | aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par); |
609 | aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par); | 609 | aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par); |
610 | /* | 610 | /* |
611 | * The sclk has been started. However, I believe the first clock | 611 | * SCLK has been started. Wait for the PLL to lock. 5 ms |
612 | * ticks it generates are not very stable. Hope this primitive loop | 612 | * should be enough according to mach64 programmer's guide. |
613 | * helps for Rage Mobilities that sometimes crash when | ||
614 | * we switch to sclk. (Daniel Mantione, 13-05-2003) | ||
615 | */ | 613 | */ |
616 | udelay(500); | 614 | mdelay(5); |
617 | } | 615 | } |
618 | 616 | ||
619 | aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); | 617 | aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); |
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c index a4b3fd185de..2ce05019301 100644 --- a/drivers/video/aty/radeon_base.c +++ b/drivers/video/aty/radeon_base.c | |||
@@ -100,6 +100,8 @@ | |||
100 | { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } | 100 | { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } |
101 | 101 | ||
102 | static struct pci_device_id radeonfb_pci_table[] = { | 102 | static struct pci_device_id radeonfb_pci_table[] = { |
103 | /* Radeon Xpress 200m */ | ||
104 | CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | ||
103 | /* Mobility M6 */ | 105 | /* Mobility M6 */ |
104 | CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | 106 | CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), |
105 | CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | 107 | CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), |
@@ -422,7 +424,7 @@ static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo) | |||
422 | 424 | ||
423 | if (dp == NULL) | 425 | if (dp == NULL) |
424 | return -ENODEV; | 426 | return -ENODEV; |
425 | val = get_property(dp, "ATY,RefCLK", NULL); | 427 | val = of_get_property(dp, "ATY,RefCLK", NULL); |
426 | if (!val || !*val) { | 428 | if (!val || !*val) { |
427 | printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); | 429 | printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); |
428 | return -EINVAL; | 430 | return -EINVAL; |
@@ -430,11 +432,11 @@ static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo) | |||
430 | 432 | ||
431 | rinfo->pll.ref_clk = (*val) / 10; | 433 | rinfo->pll.ref_clk = (*val) / 10; |
432 | 434 | ||
433 | val = get_property(dp, "ATY,SCLK", NULL); | 435 | val = of_get_property(dp, "ATY,SCLK", NULL); |
434 | if (val && *val) | 436 | if (val && *val) |
435 | rinfo->pll.sclk = (*val) / 10; | 437 | rinfo->pll.sclk = (*val) / 10; |
436 | 438 | ||
437 | val = get_property(dp, "ATY,MCLK", NULL); | 439 | val = of_get_property(dp, "ATY,MCLK", NULL); |
438 | if (val && *val) | 440 | if (val && *val) |
439 | rinfo->pll.mclk = (*val) / 10; | 441 | rinfo->pll.mclk = (*val) / 10; |
440 | 442 | ||
@@ -1994,7 +1996,8 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo) | |||
1994 | /* framebuffer size */ | 1996 | /* framebuffer size */ |
1995 | if ((rinfo->family == CHIP_FAMILY_RS100) || | 1997 | if ((rinfo->family == CHIP_FAMILY_RS100) || |
1996 | (rinfo->family == CHIP_FAMILY_RS200) || | 1998 | (rinfo->family == CHIP_FAMILY_RS200) || |
1997 | (rinfo->family == CHIP_FAMILY_RS300)) { | 1999 | (rinfo->family == CHIP_FAMILY_RS300) || |
2000 | (rinfo->family == CHIP_FAMILY_RS480) ) { | ||
1998 | u32 tom = INREG(NB_TOM); | 2001 | u32 tom = INREG(NB_TOM); |
1999 | tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); | 2002 | tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); |
2000 | 2003 | ||
diff --git a/drivers/video/aty/radeon_monitor.c b/drivers/video/aty/radeon_monitor.c index 737b5c09dbd..2030ed81342 100644 --- a/drivers/video/aty/radeon_monitor.c +++ b/drivers/video/aty/radeon_monitor.c | |||
@@ -70,7 +70,7 @@ static int __devinit radeon_parse_montype_prop(struct device_node *dp, u8 **out_ | |||
70 | int i, mt = MT_NONE; | 70 | int i, mt = MT_NONE; |
71 | 71 | ||
72 | RTRACE("analyzing OF properties...\n"); | 72 | RTRACE("analyzing OF properties...\n"); |
73 | pmt = get_property(dp, "display-type", NULL); | 73 | pmt = of_get_property(dp, "display-type", NULL); |
74 | if (!pmt) | 74 | if (!pmt) |
75 | return MT_NONE; | 75 | return MT_NONE; |
76 | RTRACE("display-type: %s\n", pmt); | 76 | RTRACE("display-type: %s\n", pmt); |
@@ -89,7 +89,7 @@ static int __devinit radeon_parse_montype_prop(struct device_node *dp, u8 **out_ | |||
89 | } | 89 | } |
90 | 90 | ||
91 | for (i = 0; propnames[i] != NULL; ++i) { | 91 | for (i = 0; propnames[i] != NULL; ++i) { |
92 | pedid = get_property(dp, propnames[i], NULL); | 92 | pedid = of_get_property(dp, propnames[i], NULL); |
93 | if (pedid != NULL) | 93 | if (pedid != NULL) |
94 | break; | 94 | break; |
95 | } | 95 | } |
@@ -98,9 +98,10 @@ static int __devinit radeon_parse_montype_prop(struct device_node *dp, u8 **out_ | |||
98 | * single-head cards have hdno == -1 and skip this step | 98 | * single-head cards have hdno == -1 and skip this step |
99 | */ | 99 | */ |
100 | if (pedid == NULL && dp->parent && (hdno != -1)) | 100 | if (pedid == NULL && dp->parent && (hdno != -1)) |
101 | pedid = get_property(dp->parent, (hdno == 0) ? "EDID1" : "EDID2", NULL); | 101 | pedid = of_get_property(dp->parent, |
102 | (hdno == 0) ? "EDID1" : "EDID2", NULL); | ||
102 | if (pedid == NULL && dp->parent && (hdno == 0)) | 103 | if (pedid == NULL && dp->parent && (hdno == 0)) |
103 | pedid = get_property(dp->parent, "EDID", NULL); | 104 | pedid = of_get_property(dp->parent, "EDID", NULL); |
104 | if (pedid == NULL) | 105 | if (pedid == NULL) |
105 | return mt; | 106 | return mt; |
106 | 107 | ||
@@ -130,7 +131,7 @@ static int __devinit radeon_probe_OF_head(struct radeonfb_info *rinfo, int head_ | |||
130 | do { | 131 | do { |
131 | if (!dp) | 132 | if (!dp) |
132 | return MT_NONE; | 133 | return MT_NONE; |
133 | pname = get_property(dp, "name", NULL); | 134 | pname = of_get_property(dp, "name", NULL); |
134 | if (!pname) | 135 | if (!pname) |
135 | return MT_NONE; | 136 | return MT_NONE; |
136 | len = strlen(pname); | 137 | len = strlen(pname); |
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c index c411293cefc..be1d57bf9dc 100644 --- a/drivers/video/aty/radeon_pm.c +++ b/drivers/video/aty/radeon_pm.c | |||
@@ -1290,7 +1290,7 @@ static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo) | |||
1290 | if (rinfo->of_node != NULL) { | 1290 | if (rinfo->of_node != NULL) { |
1291 | int size; | 1291 | int size; |
1292 | 1292 | ||
1293 | mrtable = get_property(rinfo->of_node, "ATY,MRT", &size); | 1293 | mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size); |
1294 | if (mrtable) | 1294 | if (mrtable) |
1295 | mrtable_size = size >> 2; | 1295 | mrtable_size = size >> 2; |
1296 | else | 1296 | else |
@@ -2826,11 +2826,15 @@ void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlis | |||
2826 | rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM); | 2826 | rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM); |
2827 | 2827 | ||
2828 | /* Enable/Disable dynamic clocks: TODO add sysfs access */ | 2828 | /* Enable/Disable dynamic clocks: TODO add sysfs access */ |
2829 | rinfo->dynclk = dynclk; | 2829 | if (rinfo->family == CHIP_FAMILY_RS480) |
2830 | if (dynclk == 1) { | 2830 | rinfo->dynclk = -1; |
2831 | else | ||
2832 | rinfo->dynclk = dynclk; | ||
2833 | |||
2834 | if (rinfo->dynclk == 1) { | ||
2831 | radeon_pm_enable_dynamic_mode(rinfo); | 2835 | radeon_pm_enable_dynamic_mode(rinfo); |
2832 | printk("radeonfb: Dynamic Clock Power Management enabled\n"); | 2836 | printk("radeonfb: Dynamic Clock Power Management enabled\n"); |
2833 | } else if (dynclk == 0) { | 2837 | } else if (rinfo->dynclk == 0) { |
2834 | radeon_pm_disable_dynamic_mode(rinfo); | 2838 | radeon_pm_disable_dynamic_mode(rinfo); |
2835 | printk("radeonfb: Dynamic Clock Power Management disabled\n"); | 2839 | printk("radeonfb: Dynamic Clock Power Management disabled\n"); |
2836 | } | 2840 | } |
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h index 31900036028..7ebffcdfd1e 100644 --- a/drivers/video/aty/radeonfb.h +++ b/drivers/video/aty/radeonfb.h | |||
@@ -48,6 +48,7 @@ enum radeon_family { | |||
48 | CHIP_FAMILY_RV350, | 48 | CHIP_FAMILY_RV350, |
49 | CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ | 49 | CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ |
50 | CHIP_FAMILY_R420, /* R420/R423/M18 */ | 50 | CHIP_FAMILY_R420, /* R420/R423/M18 */ |
51 | CHIP_FAMILY_RS480, | ||
51 | CHIP_FAMILY_LAST, | 52 | CHIP_FAMILY_LAST, |
52 | }; | 53 | }; |
53 | 54 | ||
@@ -64,7 +65,8 @@ enum radeon_family { | |||
64 | ((rinfo)->family == CHIP_FAMILY_RV350) || \ | 65 | ((rinfo)->family == CHIP_FAMILY_RV350) || \ |
65 | ((rinfo)->family == CHIP_FAMILY_R350) || \ | 66 | ((rinfo)->family == CHIP_FAMILY_R350) || \ |
66 | ((rinfo)->family == CHIP_FAMILY_RV380) || \ | 67 | ((rinfo)->family == CHIP_FAMILY_RV380) || \ |
67 | ((rinfo)->family == CHIP_FAMILY_R420)) | 68 | ((rinfo)->family == CHIP_FAMILY_R420) || \ |
69 | ((rinfo)->family == CHIP_FAMILY_RS480) ) | ||
68 | 70 | ||
69 | /* | 71 | /* |
70 | * Chip flags | 72 | * Chip flags |
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index 47d15b5d985..fbef663fc05 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig | |||
@@ -63,3 +63,11 @@ config BACKLIGHT_PROGEAR | |||
63 | help | 63 | help |
64 | If you have a Frontpath ProGear say Y to enable the | 64 | If you have a Frontpath ProGear say Y to enable the |
65 | backlight driver. | 65 | backlight driver. |
66 | |||
67 | config BACKLIGHT_CARILLO_RANCH | ||
68 | tristate "Intel Carillo Ranch Backlight Driver" | ||
69 | depends on BACKLIGHT_CLASS_DEVICE && LCD_CLASS_DEVICE && PCI && X86 && FB_LE80578 | ||
70 | default n | ||
71 | help | ||
72 | If you have a Intel LE80578 (Carillo Ranch) say Y to enable the | ||
73 | backlight driver. | ||
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index 0c3ce46f509..c6e2266f63e 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile | |||
@@ -6,3 +6,4 @@ obj-$(CONFIG_BACKLIGHT_CORGI) += corgi_bl.o | |||
6 | obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o | 6 | obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o |
7 | obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o | 7 | obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o |
8 | obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o | 8 | obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o |
9 | obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o | ||
diff --git a/drivers/video/backlight/cr_bllcd.c b/drivers/video/backlight/cr_bllcd.c new file mode 100644 index 00000000000..e9bbc3455c9 --- /dev/null +++ b/drivers/video/backlight/cr_bllcd.c | |||
@@ -0,0 +1,287 @@ | |||
1 | /* | ||
2 | * Copyright (c) Intel Corp. 2007. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
6 | * develop this driver. | ||
7 | * | ||
8 | * This file is part of the Carillo Ranch video subsystem driver. | ||
9 | * The Carillo Ranch video subsystem driver is free software; | ||
10 | * you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * The Carillo Ranch video subsystem driver is distributed | ||
16 | * in the hope that it will be useful, | ||
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
19 | * GNU General Public License for more details. | ||
20 | * | ||
21 | * You should have received a copy of the GNU General Public License | ||
22 | * along with this driver; if not, write to the Free Software | ||
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
24 | * | ||
25 | * Authors: | ||
26 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | ||
27 | * Alan Hourihane <alanh-at-tungstengraphics-dot-com> | ||
28 | */ | ||
29 | |||
30 | #include <linux/module.h> | ||
31 | #include <linux/kernel.h> | ||
32 | #include <linux/init.h> | ||
33 | #include <linux/platform_device.h> | ||
34 | #include <linux/mutex.h> | ||
35 | #include <linux/fb.h> | ||
36 | #include <linux/backlight.h> | ||
37 | #include <linux/lcd.h> | ||
38 | #include <linux/pci.h> | ||
39 | #include <asm/uaccess.h> | ||
40 | |||
41 | /* The LVDS- and panel power controls sits on the | ||
42 | * GPIO port of the ISA bridge. | ||
43 | */ | ||
44 | |||
45 | #define CRVML_DEVICE_LPC 0x27B8 | ||
46 | #define CRVML_REG_GPIOBAR 0x48 | ||
47 | #define CRVML_REG_GPIOEN 0x4C | ||
48 | #define CRVML_GPIOEN_BIT (1 << 4) | ||
49 | #define CRVML_PANEL_PORT 0x38 | ||
50 | #define CRVML_LVDS_ON 0x00000001 | ||
51 | #define CRVML_PANEL_ON 0x00000002 | ||
52 | #define CRVML_BACKLIGHT_OFF 0x00000004 | ||
53 | |||
54 | /* The PLL Clock register sits on Host bridge */ | ||
55 | #define CRVML_DEVICE_MCH 0x5001 | ||
56 | #define CRVML_REG_MCHBAR 0x44 | ||
57 | #define CRVML_REG_MCHEN 0x54 | ||
58 | #define CRVML_MCHEN_BIT (1 << 28) | ||
59 | #define CRVML_MCHMAP_SIZE 4096 | ||
60 | #define CRVML_REG_CLOCK 0xc3c | ||
61 | #define CRVML_CLOCK_SHIFT 8 | ||
62 | #define CRVML_CLOCK_MASK 0x00000f00 | ||
63 | |||
64 | static struct pci_dev *lpc_dev; | ||
65 | static u32 gpio_bar; | ||
66 | |||
67 | struct cr_panel { | ||
68 | struct backlight_device *cr_backlight_device; | ||
69 | struct lcd_device *cr_lcd_device; | ||
70 | }; | ||
71 | |||
72 | static int cr_backlight_set_intensity(struct backlight_device *bd) | ||
73 | { | ||
74 | int intensity = bd->props.brightness; | ||
75 | u32 addr = gpio_bar + CRVML_PANEL_PORT; | ||
76 | u32 cur = inl(addr); | ||
77 | |||
78 | if (bd->props.power == FB_BLANK_UNBLANK) | ||
79 | intensity = FB_BLANK_UNBLANK; | ||
80 | if (bd->props.fb_blank == FB_BLANK_UNBLANK) | ||
81 | intensity = FB_BLANK_UNBLANK; | ||
82 | if (bd->props.power == FB_BLANK_POWERDOWN) | ||
83 | intensity = FB_BLANK_POWERDOWN; | ||
84 | if (bd->props.fb_blank == FB_BLANK_POWERDOWN) | ||
85 | intensity = FB_BLANK_POWERDOWN; | ||
86 | |||
87 | if (intensity == FB_BLANK_UNBLANK) { /* FULL ON */ | ||
88 | cur &= ~CRVML_BACKLIGHT_OFF; | ||
89 | outl(cur, addr); | ||
90 | } else if (intensity == FB_BLANK_POWERDOWN) { /* OFF */ | ||
91 | cur |= CRVML_BACKLIGHT_OFF; | ||
92 | outl(cur, addr); | ||
93 | } /* anything else, don't bother */ | ||
94 | |||
95 | return 0; | ||
96 | } | ||
97 | |||
98 | static int cr_backlight_get_intensity(struct backlight_device *bd) | ||
99 | { | ||
100 | u32 addr = gpio_bar + CRVML_PANEL_PORT; | ||
101 | u32 cur = inl(addr); | ||
102 | u8 intensity; | ||
103 | |||
104 | if (cur & CRVML_BACKLIGHT_OFF) | ||
105 | intensity = FB_BLANK_POWERDOWN; | ||
106 | else | ||
107 | intensity = FB_BLANK_UNBLANK; | ||
108 | |||
109 | return intensity; | ||
110 | } | ||
111 | |||
112 | static struct backlight_ops cr_backlight_ops = { | ||
113 | .get_brightness = cr_backlight_get_intensity, | ||
114 | .update_status = cr_backlight_set_intensity, | ||
115 | }; | ||
116 | |||
117 | static void cr_panel_on(void) | ||
118 | { | ||
119 | u32 addr = gpio_bar + CRVML_PANEL_PORT; | ||
120 | u32 cur = inl(addr); | ||
121 | |||
122 | if (!(cur & CRVML_PANEL_ON)) { | ||
123 | /* Make sure LVDS controller is down. */ | ||
124 | if (cur & 0x00000001) { | ||
125 | cur &= ~CRVML_LVDS_ON; | ||
126 | outl(cur, addr); | ||
127 | } | ||
128 | /* Power up Panel */ | ||
129 | schedule_timeout(HZ / 10); | ||
130 | cur |= CRVML_PANEL_ON; | ||
131 | outl(cur, addr); | ||
132 | } | ||
133 | |||
134 | /* Power up LVDS controller */ | ||
135 | |||
136 | if (!(cur & CRVML_LVDS_ON)) { | ||
137 | schedule_timeout(HZ / 10); | ||
138 | outl(cur | CRVML_LVDS_ON, addr); | ||
139 | } | ||
140 | } | ||
141 | |||
142 | static void cr_panel_off(void) | ||
143 | { | ||
144 | u32 addr = gpio_bar + CRVML_PANEL_PORT; | ||
145 | u32 cur = inl(addr); | ||
146 | |||
147 | /* Power down LVDS controller first to avoid high currents */ | ||
148 | if (cur & CRVML_LVDS_ON) { | ||
149 | cur &= ~CRVML_LVDS_ON; | ||
150 | outl(cur, addr); | ||
151 | } | ||
152 | if (cur & CRVML_PANEL_ON) { | ||
153 | schedule_timeout(HZ / 10); | ||
154 | outl(cur & ~CRVML_PANEL_ON, addr); | ||
155 | } | ||
156 | } | ||
157 | |||
158 | static int cr_lcd_set_power(struct lcd_device *ld, int power) | ||
159 | { | ||
160 | if (power == FB_BLANK_UNBLANK) | ||
161 | cr_panel_on(); | ||
162 | if (power == FB_BLANK_POWERDOWN) | ||
163 | cr_panel_off(); | ||
164 | |||
165 | return 0; | ||
166 | } | ||
167 | |||
168 | static struct lcd_ops cr_lcd_ops = { | ||
169 | .set_power = cr_lcd_set_power, | ||
170 | }; | ||
171 | |||
172 | static int cr_backlight_probe(struct platform_device *pdev) | ||
173 | { | ||
174 | struct cr_panel *crp; | ||
175 | u8 dev_en; | ||
176 | |||
177 | crp = kzalloc(sizeof(crp), GFP_KERNEL); | ||
178 | if (crp == NULL) | ||
179 | return -ENOMEM; | ||
180 | |||
181 | lpc_dev = pci_get_device(PCI_VENDOR_ID_INTEL, | ||
182 | CRVML_DEVICE_LPC, NULL); | ||
183 | if (!lpc_dev) { | ||
184 | printk("INTEL CARILLO RANCH LPC not found.\n"); | ||
185 | return -ENODEV; | ||
186 | } | ||
187 | |||
188 | pci_read_config_byte(lpc_dev, CRVML_REG_GPIOEN, &dev_en); | ||
189 | if (!(dev_en & CRVML_GPIOEN_BIT)) { | ||
190 | printk(KERN_ERR | ||
191 | "Carillo Ranch GPIO device was not enabled.\n"); | ||
192 | pci_dev_put(lpc_dev); | ||
193 | return -ENODEV; | ||
194 | } | ||
195 | |||
196 | crp->cr_backlight_device = backlight_device_register("cr-backlight", | ||
197 | &pdev->dev, NULL, | ||
198 | &cr_backlight_ops); | ||
199 | if (IS_ERR(crp->cr_backlight_device)) { | ||
200 | pci_dev_put(lpc_dev); | ||
201 | return PTR_ERR(crp->cr_backlight_device); | ||
202 | } | ||
203 | |||
204 | crp->cr_lcd_device = lcd_device_register("cr-lcd", | ||
205 | &pdev->dev, | ||
206 | &cr_lcd_ops); | ||
207 | |||
208 | if (IS_ERR(crp->cr_lcd_device)) { | ||
209 | pci_dev_put(lpc_dev); | ||
210 | return PTR_ERR(crp->cr_backlight_device); | ||
211 | } | ||
212 | |||
213 | pci_read_config_dword(lpc_dev, CRVML_REG_GPIOBAR, | ||
214 | &gpio_bar); | ||
215 | gpio_bar &= ~0x3F; | ||
216 | |||
217 | crp->cr_backlight_device->props.power = FB_BLANK_UNBLANK; | ||
218 | crp->cr_backlight_device->props.brightness = 0; | ||
219 | crp->cr_backlight_device->props.max_brightness = 0; | ||
220 | cr_backlight_set_intensity(crp->cr_backlight_device); | ||
221 | |||
222 | cr_lcd_set_power(crp->cr_lcd_device, FB_BLANK_UNBLANK); | ||
223 | |||
224 | platform_set_drvdata(pdev, crp); | ||
225 | |||
226 | return 0; | ||
227 | } | ||
228 | |||
229 | static int cr_backlight_remove(struct platform_device *pdev) | ||
230 | { | ||
231 | struct cr_panel *crp = platform_get_drvdata(pdev); | ||
232 | crp->cr_backlight_device->props.power = FB_BLANK_POWERDOWN; | ||
233 | crp->cr_backlight_device->props.brightness = 0; | ||
234 | crp->cr_backlight_device->props.max_brightness = 0; | ||
235 | cr_backlight_set_intensity(crp->cr_backlight_device); | ||
236 | cr_lcd_set_power(crp->cr_lcd_device, FB_BLANK_POWERDOWN); | ||
237 | backlight_device_unregister(crp->cr_backlight_device); | ||
238 | lcd_device_unregister(crp->cr_lcd_device); | ||
239 | pci_dev_put(lpc_dev); | ||
240 | |||
241 | return 0; | ||
242 | } | ||
243 | |||
244 | static struct platform_driver cr_backlight_driver = { | ||
245 | .probe = cr_backlight_probe, | ||
246 | .remove = cr_backlight_remove, | ||
247 | .driver = { | ||
248 | .name = "cr_backlight", | ||
249 | }, | ||
250 | }; | ||
251 | |||
252 | static struct platform_device *crp; | ||
253 | |||
254 | static int __init cr_backlight_init(void) | ||
255 | { | ||
256 | int ret = platform_driver_register(&cr_backlight_driver); | ||
257 | |||
258 | if (!ret) { | ||
259 | crp = platform_device_alloc("cr_backlight", -1); | ||
260 | if (!crp) | ||
261 | return -ENOMEM; | ||
262 | |||
263 | ret = platform_device_add(crp); | ||
264 | |||
265 | if (ret) { | ||
266 | platform_device_put(crp); | ||
267 | platform_driver_unregister(&cr_backlight_driver); | ||
268 | } | ||
269 | } | ||
270 | |||
271 | printk("Carillo Ranch Backlight Driver Initialized.\n"); | ||
272 | |||
273 | return ret; | ||
274 | } | ||
275 | |||
276 | static void __exit cr_backlight_exit(void) | ||
277 | { | ||
278 | platform_device_unregister(crp); | ||
279 | platform_driver_unregister(&cr_backlight_driver); | ||
280 | } | ||
281 | |||
282 | module_init(cr_backlight_init); | ||
283 | module_exit(cr_backlight_exit); | ||
284 | |||
285 | MODULE_AUTHOR("Tungsten Graphics Inc."); | ||
286 | MODULE_DESCRIPTION("Carillo Ranch Backlight Driver"); | ||
287 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/cfbcopyarea.c b/drivers/video/cfbcopyarea.c index 6faea4034e3..032210f45be 100644 --- a/drivers/video/cfbcopyarea.c +++ b/drivers/video/cfbcopyarea.c | |||
@@ -22,8 +22,6 @@ | |||
22 | * help moving some redundant computations and branches out of the loop, too. | 22 | * help moving some redundant computations and branches out of the loop, too. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | |||
26 | |||
27 | #include <linux/module.h> | 25 | #include <linux/module.h> |
28 | #include <linux/kernel.h> | 26 | #include <linux/kernel.h> |
29 | #include <linux/string.h> | 27 | #include <linux/string.h> |
@@ -31,6 +29,7 @@ | |||
31 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
32 | #include <asm/types.h> | 30 | #include <asm/types.h> |
33 | #include <asm/io.h> | 31 | #include <asm/io.h> |
32 | #include "fb_draw.h" | ||
34 | 33 | ||
35 | #if BITS_PER_LONG == 32 | 34 | #if BITS_PER_LONG == 32 |
36 | # define FB_WRITEL fb_writel | 35 | # define FB_WRITEL fb_writel |
@@ -41,17 +40,6 @@ | |||
41 | #endif | 40 | #endif |
42 | 41 | ||
43 | /* | 42 | /* |
44 | * Compose two values, using a bitmask as decision value | ||
45 | * This is equivalent to (a & mask) | (b & ~mask) | ||
46 | */ | ||
47 | |||
48 | static inline unsigned long | ||
49 | comp(unsigned long a, unsigned long b, unsigned long mask) | ||
50 | { | ||
51 | return ((a ^ b) & mask) ^ b; | ||
52 | } | ||
53 | |||
54 | /* | ||
55 | * Generic bitwise copy algorithm | 43 | * Generic bitwise copy algorithm |
56 | */ | 44 | */ |
57 | 45 | ||
diff --git a/drivers/video/cfbfillrect.c b/drivers/video/cfbfillrect.c index f00b50aab60..71623b4f8ca 100644 --- a/drivers/video/cfbfillrect.c +++ b/drivers/video/cfbfillrect.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <linux/string.h> | 21 | #include <linux/string.h> |
22 | #include <linux/fb.h> | 22 | #include <linux/fb.h> |
23 | #include <asm/types.h> | 23 | #include <asm/types.h> |
24 | #include "fb_draw.h" | ||
24 | 25 | ||
25 | #if BITS_PER_LONG == 32 | 26 | #if BITS_PER_LONG == 32 |
26 | # define FB_WRITEL fb_writel | 27 | # define FB_WRITEL fb_writel |
@@ -31,73 +32,6 @@ | |||
31 | #endif | 32 | #endif |
32 | 33 | ||
33 | /* | 34 | /* |
34 | * Compose two values, using a bitmask as decision value | ||
35 | * This is equivalent to (a & mask) | (b & ~mask) | ||
36 | */ | ||
37 | |||
38 | static inline unsigned long | ||
39 | comp(unsigned long a, unsigned long b, unsigned long mask) | ||
40 | { | ||
41 | return ((a ^ b) & mask) ^ b; | ||
42 | } | ||
43 | |||
44 | /* | ||
45 | * Create a pattern with the given pixel's color | ||
46 | */ | ||
47 | |||
48 | #if BITS_PER_LONG == 64 | ||
49 | static inline unsigned long | ||
50 | pixel_to_pat( u32 bpp, u32 pixel) | ||
51 | { | ||
52 | switch (bpp) { | ||
53 | case 1: | ||
54 | return 0xfffffffffffffffful*pixel; | ||
55 | case 2: | ||
56 | return 0x5555555555555555ul*pixel; | ||
57 | case 4: | ||
58 | return 0x1111111111111111ul*pixel; | ||
59 | case 8: | ||
60 | return 0x0101010101010101ul*pixel; | ||
61 | case 12: | ||
62 | return 0x0001001001001001ul*pixel; | ||
63 | case 16: | ||
64 | return 0x0001000100010001ul*pixel; | ||
65 | case 24: | ||
66 | return 0x0000000001000001ul*pixel; | ||
67 | case 32: | ||
68 | return 0x0000000100000001ul*pixel; | ||
69 | default: | ||
70 | panic("pixel_to_pat(): unsupported pixelformat\n"); | ||
71 | } | ||
72 | } | ||
73 | #else | ||
74 | static inline unsigned long | ||
75 | pixel_to_pat( u32 bpp, u32 pixel) | ||
76 | { | ||
77 | switch (bpp) { | ||
78 | case 1: | ||
79 | return 0xfffffffful*pixel; | ||
80 | case 2: | ||
81 | return 0x55555555ul*pixel; | ||
82 | case 4: | ||
83 | return 0x11111111ul*pixel; | ||
84 | case 8: | ||
85 | return 0x01010101ul*pixel; | ||
86 | case 12: | ||
87 | return 0x00001001ul*pixel; | ||
88 | case 16: | ||
89 | return 0x00010001ul*pixel; | ||
90 | case 24: | ||
91 | return 0x00000001ul*pixel; | ||
92 | case 32: | ||
93 | return 0x00000001ul*pixel; | ||
94 | default: | ||
95 | panic("pixel_to_pat(): unsupported pixelformat\n"); | ||
96 | } | ||
97 | } | ||
98 | #endif | ||
99 | |||
100 | /* | ||
101 | * Aligned pattern fill using 32/64-bit memory accesses | 35 | * Aligned pattern fill using 32/64-bit memory accesses |
102 | */ | 36 | */ |
103 | 37 | ||
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c index 2c4bc620573..8269d704ab2 100644 --- a/drivers/video/cirrusfb.c +++ b/drivers/video/cirrusfb.c | |||
@@ -98,15 +98,6 @@ | |||
98 | #define assert(expr) | 98 | #define assert(expr) |
99 | #endif | 99 | #endif |
100 | 100 | ||
101 | #ifdef TRUE | ||
102 | #undef TRUE | ||
103 | #endif | ||
104 | #ifdef FALSE | ||
105 | #undef FALSE | ||
106 | #endif | ||
107 | #define TRUE 1 | ||
108 | #define FALSE 0 | ||
109 | |||
110 | #define MB_ (1024*1024) | 101 | #define MB_ (1024*1024) |
111 | #define KB_ (1024) | 102 | #define KB_ (1024) |
112 | 103 | ||
@@ -146,9 +137,9 @@ static const struct cirrusfb_board_info_rec { | |||
146 | char *name; /* ASCII name of chipset */ | 137 | char *name; /* ASCII name of chipset */ |
147 | long maxclock[5]; /* maximum video clock */ | 138 | long maxclock[5]; /* maximum video clock */ |
148 | /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */ | 139 | /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */ |
149 | unsigned init_sr07 : 1; /* init SR07 during init_vgachip() */ | 140 | bool init_sr07 : 1; /* init SR07 during init_vgachip() */ |
150 | unsigned init_sr1f : 1; /* write SR1F during init_vgachip() */ | 141 | bool init_sr1f : 1; /* write SR1F during init_vgachip() */ |
151 | unsigned scrn_start_bit19 : 1; /* construct bit 19 of screen start address */ | 142 | bool scrn_start_bit19 : 1; /* construct bit 19 of screen start address */ |
152 | 143 | ||
153 | /* initial SR07 value, then for each mode */ | 144 | /* initial SR07 value, then for each mode */ |
154 | unsigned char sr07; | 145 | unsigned char sr07; |
@@ -166,9 +157,9 @@ static const struct cirrusfb_board_info_rec { | |||
166 | /* the SD64/P4 have a higher max. videoclock */ | 157 | /* the SD64/P4 have a higher max. videoclock */ |
167 | 140000, 140000, 140000, 140000, 140000, | 158 | 140000, 140000, 140000, 140000, 140000, |
168 | }, | 159 | }, |
169 | .init_sr07 = TRUE, | 160 | .init_sr07 = true, |
170 | .init_sr1f = TRUE, | 161 | .init_sr1f = true, |
171 | .scrn_start_bit19 = TRUE, | 162 | .scrn_start_bit19 = true, |
172 | .sr07 = 0xF0, | 163 | .sr07 = 0xF0, |
173 | .sr07_1bpp = 0xF0, | 164 | .sr07_1bpp = 0xF0, |
174 | .sr07_8bpp = 0xF1, | 165 | .sr07_8bpp = 0xF1, |
@@ -180,9 +171,9 @@ static const struct cirrusfb_board_info_rec { | |||
180 | /* guess */ | 171 | /* guess */ |
181 | 90000, 90000, 90000, 90000, 90000 | 172 | 90000, 90000, 90000, 90000, 90000 |
182 | }, | 173 | }, |
183 | .init_sr07 = TRUE, | 174 | .init_sr07 = true, |
184 | .init_sr1f = TRUE, | 175 | .init_sr1f = true, |
185 | .scrn_start_bit19 = FALSE, | 176 | .scrn_start_bit19 = false, |
186 | .sr07 = 0x80, | 177 | .sr07 = 0x80, |
187 | .sr07_1bpp = 0x80, | 178 | .sr07_1bpp = 0x80, |
188 | .sr07_8bpp = 0x81, | 179 | .sr07_8bpp = 0x81, |
@@ -194,9 +185,9 @@ static const struct cirrusfb_board_info_rec { | |||
194 | /* guess */ | 185 | /* guess */ |
195 | 90000, 90000, 90000, 90000, 90000 | 186 | 90000, 90000, 90000, 90000, 90000 |
196 | }, | 187 | }, |
197 | .init_sr07 = TRUE, | 188 | .init_sr07 = true, |
198 | .init_sr1f = TRUE, | 189 | .init_sr1f = true, |
199 | .scrn_start_bit19 = FALSE, | 190 | .scrn_start_bit19 = false, |
200 | .sr07 = 0x20, | 191 | .sr07 = 0x20, |
201 | .sr07_1bpp = 0x20, | 192 | .sr07_1bpp = 0x20, |
202 | .sr07_8bpp = 0x21, | 193 | .sr07_8bpp = 0x21, |
@@ -208,9 +199,9 @@ static const struct cirrusfb_board_info_rec { | |||
208 | /* guess */ | 199 | /* guess */ |
209 | 90000, 90000, 90000, 90000, 90000 | 200 | 90000, 90000, 90000, 90000, 90000 |
210 | }, | 201 | }, |
211 | .init_sr07 = TRUE, | 202 | .init_sr07 = true, |
212 | .init_sr1f = TRUE, | 203 | .init_sr1f = true, |
213 | .scrn_start_bit19 = FALSE, | 204 | .scrn_start_bit19 = false, |
214 | .sr07 = 0x80, | 205 | .sr07 = 0x80, |
215 | .sr07_1bpp = 0x80, | 206 | .sr07_1bpp = 0x80, |
216 | .sr07_8bpp = 0x81, | 207 | .sr07_8bpp = 0x81, |
@@ -221,9 +212,9 @@ static const struct cirrusfb_board_info_rec { | |||
221 | .maxclock = { | 212 | .maxclock = { |
222 | 135100, 135100, 85500, 85500, 0 | 213 | 135100, 135100, 85500, 85500, 0 |
223 | }, | 214 | }, |
224 | .init_sr07 = TRUE, | 215 | .init_sr07 = true, |
225 | .init_sr1f = FALSE, | 216 | .init_sr1f = false, |
226 | .scrn_start_bit19 = TRUE, | 217 | .scrn_start_bit19 = true, |
227 | .sr07 = 0x20, | 218 | .sr07 = 0x20, |
228 | .sr07_1bpp = 0x20, | 219 | .sr07_1bpp = 0x20, |
229 | .sr07_8bpp = 0x21, | 220 | .sr07_8bpp = 0x21, |
@@ -235,9 +226,9 @@ static const struct cirrusfb_board_info_rec { | |||
235 | /* for the GD5430. GD5446 can do more... */ | 226 | /* for the GD5430. GD5446 can do more... */ |
236 | 85500, 85500, 50000, 28500, 0 | 227 | 85500, 85500, 50000, 28500, 0 |
237 | }, | 228 | }, |
238 | .init_sr07 = TRUE, | 229 | .init_sr07 = true, |
239 | .init_sr1f = TRUE, | 230 | .init_sr1f = true, |
240 | .scrn_start_bit19 = TRUE, | 231 | .scrn_start_bit19 = true, |
241 | .sr07 = 0xA0, | 232 | .sr07 = 0xA0, |
242 | .sr07_1bpp = 0xA1, | 233 | .sr07_1bpp = 0xA1, |
243 | .sr07_1bpp_mux = 0xA7, | 234 | .sr07_1bpp_mux = 0xA7, |
@@ -250,9 +241,9 @@ static const struct cirrusfb_board_info_rec { | |||
250 | .maxclock = { | 241 | .maxclock = { |
251 | 135100, 200000, 200000, 135100, 135100 | 242 | 135100, 200000, 200000, 135100, 135100 |
252 | }, | 243 | }, |
253 | .init_sr07 = TRUE, | 244 | .init_sr07 = true, |
254 | .init_sr1f = TRUE, | 245 | .init_sr1f = true, |
255 | .scrn_start_bit19 = TRUE, | 246 | .scrn_start_bit19 = true, |
256 | .sr07 = 0x10, | 247 | .sr07 = 0x10, |
257 | .sr07_1bpp = 0x11, | 248 | .sr07_1bpp = 0x11, |
258 | .sr07_8bpp = 0x11, | 249 | .sr07_8bpp = 0x11, |
@@ -264,9 +255,9 @@ static const struct cirrusfb_board_info_rec { | |||
264 | /* guess */ | 255 | /* guess */ |
265 | 135100, 135100, 135100, 135100, 135100, | 256 | 135100, 135100, 135100, 135100, 135100, |
266 | }, | 257 | }, |
267 | .init_sr07 = FALSE, | 258 | .init_sr07 = false, |
268 | .init_sr1f = FALSE, | 259 | .init_sr1f = false, |
269 | .scrn_start_bit19 = TRUE, | 260 | .scrn_start_bit19 = true, |
270 | } | 261 | } |
271 | }; | 262 | }; |
272 | 263 | ||
@@ -815,7 +806,7 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var, | |||
815 | 806 | ||
816 | default: | 807 | default: |
817 | DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel); | 808 | DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel); |
818 | assert (FALSE); | 809 | assert(false); |
819 | /* should never occur */ | 810 | /* should never occur */ |
820 | break; | 811 | break; |
821 | } | 812 | } |
@@ -886,7 +877,7 @@ static int cirrusfb_decode_var (const struct fb_var_screeninfo *var, | |||
886 | 877 | ||
887 | default: | 878 | default: |
888 | DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel); | 879 | DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel); |
889 | assert (FALSE); | 880 | assert(false); |
890 | /* should never occur */ | 881 | /* should never occur */ |
891 | break; | 882 | break; |
892 | } | 883 | } |
@@ -3203,7 +3194,7 @@ void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_clas | |||
3203 | break; | 3194 | break; |
3204 | default: | 3195 | default: |
3205 | /* should never occur */ | 3196 | /* should never occur */ |
3206 | assert (FALSE); | 3197 | assert(false); |
3207 | break; | 3198 | break; |
3208 | } | 3199 | } |
3209 | 3200 | ||
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c index 0429fd2cece..73813c60d03 100644 --- a/drivers/video/console/fbcon.c +++ b/drivers/video/console/fbcon.c | |||
@@ -107,7 +107,9 @@ static struct display fb_display[MAX_NR_CONSOLES]; | |||
107 | 107 | ||
108 | static signed char con2fb_map[MAX_NR_CONSOLES]; | 108 | static signed char con2fb_map[MAX_NR_CONSOLES]; |
109 | static signed char con2fb_map_boot[MAX_NR_CONSOLES]; | 109 | static signed char con2fb_map_boot[MAX_NR_CONSOLES]; |
110 | #ifndef MODULE | ||
110 | static int logo_height; | 111 | static int logo_height; |
112 | #endif | ||
111 | static int logo_lines; | 113 | static int logo_lines; |
112 | /* logo_shown is an index to vc_cons when >= 0; otherwise follows FBCON_LOGO | 114 | /* logo_shown is an index to vc_cons when >= 0; otherwise follows FBCON_LOGO |
113 | enums. */ | 115 | enums. */ |
@@ -576,6 +578,13 @@ static int fbcon_takeover(int show_logo) | |||
576 | return err; | 578 | return err; |
577 | } | 579 | } |
578 | 580 | ||
581 | #ifdef MODULE | ||
582 | static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info, | ||
583 | int cols, int rows, int new_cols, int new_rows) | ||
584 | { | ||
585 | logo_shown = FBCON_LOGO_DONTSHOW; | ||
586 | } | ||
587 | #else | ||
579 | static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info, | 588 | static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info, |
580 | int cols, int rows, int new_cols, int new_rows) | 589 | int cols, int rows, int new_cols, int new_rows) |
581 | { | 590 | { |
@@ -584,6 +593,11 @@ static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info, | |||
584 | int cnt, erase = vc->vc_video_erase_char, step; | 593 | int cnt, erase = vc->vc_video_erase_char, step; |
585 | unsigned short *save = NULL, *r, *q; | 594 | unsigned short *save = NULL, *r, *q; |
586 | 595 | ||
596 | if (info->flags & FBINFO_MODULE) { | ||
597 | logo_shown = FBCON_LOGO_DONTSHOW; | ||
598 | return; | ||
599 | } | ||
600 | |||
587 | /* | 601 | /* |
588 | * remove underline attribute from erase character | 602 | * remove underline attribute from erase character |
589 | * if black and white framebuffer. | 603 | * if black and white framebuffer. |
@@ -618,8 +632,13 @@ static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info, | |||
618 | r -= cols; | 632 | r -= cols; |
619 | } | 633 | } |
620 | if (!save) { | 634 | if (!save) { |
621 | vc->vc_y += logo_lines; | 635 | int lines; |
622 | vc->vc_pos += logo_lines * vc->vc_size_row; | 636 | if (vc->vc_y + logo_lines >= rows) |
637 | lines = rows - vc->vc_y - 1; | ||
638 | else | ||
639 | lines = logo_lines; | ||
640 | vc->vc_y += lines; | ||
641 | vc->vc_pos += lines * vc->vc_size_row; | ||
623 | } | 642 | } |
624 | } | 643 | } |
625 | scr_memsetw((unsigned short *) vc->vc_origin, | 644 | scr_memsetw((unsigned short *) vc->vc_origin, |
@@ -650,6 +669,7 @@ static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info, | |||
650 | vc->vc_top = logo_lines; | 669 | vc->vc_top = logo_lines; |
651 | } | 670 | } |
652 | } | 671 | } |
672 | #endif /* MODULE */ | ||
653 | 673 | ||
654 | #ifdef CONFIG_FB_TILEBLITTING | 674 | #ifdef CONFIG_FB_TILEBLITTING |
655 | static void set_blitting_type(struct vc_data *vc, struct fb_info *info) | 675 | static void set_blitting_type(struct vc_data *vc, struct fb_info *info) |
@@ -665,6 +685,17 @@ static void set_blitting_type(struct vc_data *vc, struct fb_info *info) | |||
665 | fbcon_set_bitops(ops); | 685 | fbcon_set_bitops(ops); |
666 | } | 686 | } |
667 | } | 687 | } |
688 | |||
689 | static int fbcon_invalid_charcount(struct fb_info *info, unsigned charcount) | ||
690 | { | ||
691 | int err = 0; | ||
692 | |||
693 | if (info->flags & FBINFO_MISC_TILEBLITTING && | ||
694 | info->tileops->fb_get_tilemax(info) < charcount) | ||
695 | err = 1; | ||
696 | |||
697 | return err; | ||
698 | } | ||
668 | #else | 699 | #else |
669 | static void set_blitting_type(struct vc_data *vc, struct fb_info *info) | 700 | static void set_blitting_type(struct vc_data *vc, struct fb_info *info) |
670 | { | 701 | { |
@@ -675,6 +706,12 @@ static void set_blitting_type(struct vc_data *vc, struct fb_info *info) | |||
675 | fbcon_set_rotation(info); | 706 | fbcon_set_rotation(info); |
676 | fbcon_set_bitops(ops); | 707 | fbcon_set_bitops(ops); |
677 | } | 708 | } |
709 | |||
710 | static int fbcon_invalid_charcount(struct fb_info *info, unsigned charcount) | ||
711 | { | ||
712 | return 0; | ||
713 | } | ||
714 | |||
678 | #endif /* CONFIG_MISC_TILEBLITTING */ | 715 | #endif /* CONFIG_MISC_TILEBLITTING */ |
679 | 716 | ||
680 | 717 | ||
@@ -968,7 +1005,9 @@ static const char *fbcon_startup(void) | |||
968 | if (!p->fontdata) { | 1005 | if (!p->fontdata) { |
969 | if (!fontname[0] || !(font = find_font(fontname))) | 1006 | if (!fontname[0] || !(font = find_font(fontname))) |
970 | font = get_default_font(info->var.xres, | 1007 | font = get_default_font(info->var.xres, |
971 | info->var.yres); | 1008 | info->var.yres, |
1009 | info->pixmap.blit_x, | ||
1010 | info->pixmap.blit_y); | ||
972 | vc->vc_font.width = font->width; | 1011 | vc->vc_font.width = font->width; |
973 | vc->vc_font.height = font->height; | 1012 | vc->vc_font.height = font->height; |
974 | vc->vc_font.data = (void *)(p->fontdata = font->data); | 1013 | vc->vc_font.data = (void *)(p->fontdata = font->data); |
@@ -1088,7 +1127,9 @@ static void fbcon_init(struct vc_data *vc, int init) | |||
1088 | 1127 | ||
1089 | if (!fontname[0] || !(font = find_font(fontname))) | 1128 | if (!fontname[0] || !(font = find_font(fontname))) |
1090 | font = get_default_font(info->var.xres, | 1129 | font = get_default_font(info->var.xres, |
1091 | info->var.yres); | 1130 | info->var.yres, |
1131 | info->pixmap.blit_x, | ||
1132 | info->pixmap.blit_y); | ||
1092 | vc->vc_font.width = font->width; | 1133 | vc->vc_font.width = font->width; |
1093 | vc->vc_font.height = font->height; | 1134 | vc->vc_font.height = font->height; |
1094 | vc->vc_font.data = (void *)(p->fontdata = font->data); | 1135 | vc->vc_font.data = (void *)(p->fontdata = font->data); |
@@ -1305,7 +1346,7 @@ static void fbcon_cursor(struct vc_data *vc, int mode) | |||
1305 | int y; | 1346 | int y; |
1306 | int c = scr_readw((u16 *) vc->vc_pos); | 1347 | int c = scr_readw((u16 *) vc->vc_pos); |
1307 | 1348 | ||
1308 | if (fbcon_is_inactive(vc, info)) | 1349 | if (fbcon_is_inactive(vc, info) || vc->vc_deccm != 1) |
1309 | return; | 1350 | return; |
1310 | 1351 | ||
1311 | ops->cursor_flash = (mode == CM_ERASE) ? 0 : 1; | 1352 | ops->cursor_flash = (mode == CM_ERASE) ? 0 : 1; |
@@ -2475,6 +2516,7 @@ static int fbcon_copy_font(struct vc_data *vc, int con) | |||
2475 | 2516 | ||
2476 | static int fbcon_set_font(struct vc_data *vc, struct console_font *font, unsigned flags) | 2517 | static int fbcon_set_font(struct vc_data *vc, struct console_font *font, unsigned flags) |
2477 | { | 2518 | { |
2519 | struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]]; | ||
2478 | unsigned charcount = font->charcount; | 2520 | unsigned charcount = font->charcount; |
2479 | int w = font->width; | 2521 | int w = font->width; |
2480 | int h = font->height; | 2522 | int h = font->height; |
@@ -2488,6 +2530,15 @@ static int fbcon_set_font(struct vc_data *vc, struct console_font *font, unsigne | |||
2488 | if (charcount != 256 && charcount != 512) | 2530 | if (charcount != 256 && charcount != 512) |
2489 | return -EINVAL; | 2531 | return -EINVAL; |
2490 | 2532 | ||
2533 | /* Make sure drawing engine can handle the font */ | ||
2534 | if (!(info->pixmap.blit_x & (1 << (font->width - 1))) || | ||
2535 | !(info->pixmap.blit_y & (1 << (font->height - 1)))) | ||
2536 | return -EINVAL; | ||
2537 | |||
2538 | /* Make sure driver can handle the font length */ | ||
2539 | if (fbcon_invalid_charcount(info, charcount)) | ||
2540 | return -EINVAL; | ||
2541 | |||
2491 | size = h * pitch * charcount; | 2542 | size = h * pitch * charcount; |
2492 | 2543 | ||
2493 | new_data = kmalloc(FONT_EXTRA_WORDS * sizeof(int) + size, GFP_USER); | 2544 | new_data = kmalloc(FONT_EXTRA_WORDS * sizeof(int) + size, GFP_USER); |
@@ -2532,7 +2583,8 @@ static int fbcon_set_def_font(struct vc_data *vc, struct console_font *font, cha | |||
2532 | const struct font_desc *f; | 2583 | const struct font_desc *f; |
2533 | 2584 | ||
2534 | if (!name) | 2585 | if (!name) |
2535 | f = get_default_font(info->var.xres, info->var.yres); | 2586 | f = get_default_font(info->var.xres, info->var.yres, |
2587 | info->pixmap.blit_x, info->pixmap.blit_y); | ||
2536 | else if (!(f = find_font(name))) | 2588 | else if (!(f = find_font(name))) |
2537 | return -ENOENT; | 2589 | return -ENOENT; |
2538 | 2590 | ||
@@ -2829,7 +2881,7 @@ static void fbcon_set_all_vcs(struct fb_info *info) | |||
2829 | struct fbcon_ops *ops = info->fbcon_par; | 2881 | struct fbcon_ops *ops = info->fbcon_par; |
2830 | struct vc_data *vc; | 2882 | struct vc_data *vc; |
2831 | struct display *p; | 2883 | struct display *p; |
2832 | int i, rows, cols; | 2884 | int i, rows, cols, fg = -1; |
2833 | 2885 | ||
2834 | if (!ops || ops->currcon < 0) | 2886 | if (!ops || ops->currcon < 0) |
2835 | return; | 2887 | return; |
@@ -2840,34 +2892,23 @@ static void fbcon_set_all_vcs(struct fb_info *info) | |||
2840 | registered_fb[con2fb_map[i]] != info) | 2892 | registered_fb[con2fb_map[i]] != info) |
2841 | continue; | 2893 | continue; |
2842 | 2894 | ||
2895 | if (CON_IS_VISIBLE(vc)) { | ||
2896 | fg = i; | ||
2897 | continue; | ||
2898 | } | ||
2899 | |||
2843 | p = &fb_display[vc->vc_num]; | 2900 | p = &fb_display[vc->vc_num]; |
2844 | set_blitting_type(vc, info); | 2901 | set_blitting_type(vc, info); |
2845 | var_to_display(p, &info->var, info); | 2902 | var_to_display(p, &info->var, info); |
2846 | cols = FBCON_SWAP(ops->rotate, info->var.xres, info->var.yres); | 2903 | cols = FBCON_SWAP(p->rotate, info->var.xres, info->var.yres); |
2847 | rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres); | 2904 | rows = FBCON_SWAP(p->rotate, info->var.yres, info->var.xres); |
2848 | cols /= vc->vc_font.width; | 2905 | cols /= vc->vc_font.width; |
2849 | rows /= vc->vc_font.height; | 2906 | rows /= vc->vc_font.height; |
2850 | vc_resize(vc, cols, rows); | 2907 | vc_resize(vc, cols, rows); |
2851 | |||
2852 | if (CON_IS_VISIBLE(vc)) { | ||
2853 | updatescrollmode(p, info, vc); | ||
2854 | scrollback_max = 0; | ||
2855 | scrollback_current = 0; | ||
2856 | |||
2857 | if (!fbcon_is_inactive(vc, info)) { | ||
2858 | ops->var.xoffset = ops->var.yoffset = | ||
2859 | p->yscroll = 0; | ||
2860 | ops->update_start(info); | ||
2861 | } | ||
2862 | |||
2863 | fbcon_set_palette(vc, color_table); | ||
2864 | update_screen(vc); | ||
2865 | if (softback_buf) | ||
2866 | fbcon_update_softback(vc); | ||
2867 | } | ||
2868 | } | 2908 | } |
2869 | 2909 | ||
2870 | ops->p = &fb_display[ops->currcon]; | 2910 | if (fg != -1) |
2911 | fbcon_modechanged(info); | ||
2871 | } | 2912 | } |
2872 | 2913 | ||
2873 | static int fbcon_mode_deleted(struct fb_info *info, | 2914 | static int fbcon_mode_deleted(struct fb_info *info, |
@@ -3002,6 +3043,42 @@ static void fbcon_new_modelist(struct fb_info *info) | |||
3002 | } | 3043 | } |
3003 | } | 3044 | } |
3004 | 3045 | ||
3046 | static void fbcon_get_requirement(struct fb_info *info, | ||
3047 | struct fb_blit_caps *caps) | ||
3048 | { | ||
3049 | struct vc_data *vc; | ||
3050 | struct display *p; | ||
3051 | |||
3052 | if (caps->flags) { | ||
3053 | int i, charcnt; | ||
3054 | |||
3055 | for (i = first_fb_vc; i <= last_fb_vc; i++) { | ||
3056 | vc = vc_cons[i].d; | ||
3057 | if (vc && vc->vc_mode == KD_TEXT && | ||
3058 | info->node == con2fb_map[i]) { | ||
3059 | p = &fb_display[i]; | ||
3060 | caps->x |= 1 << (vc->vc_font.width - 1); | ||
3061 | caps->y |= 1 << (vc->vc_font.height - 1); | ||
3062 | charcnt = (p->userfont) ? | ||
3063 | FNTCHARCNT(p->fontdata) : 256; | ||
3064 | if (caps->len < charcnt) | ||
3065 | caps->len = charcnt; | ||
3066 | } | ||
3067 | } | ||
3068 | } else { | ||
3069 | vc = vc_cons[fg_console].d; | ||
3070 | |||
3071 | if (vc && vc->vc_mode == KD_TEXT && | ||
3072 | info->node == con2fb_map[fg_console]) { | ||
3073 | p = &fb_display[fg_console]; | ||
3074 | caps->x = 1 << (vc->vc_font.width - 1); | ||
3075 | caps->y = 1 << (vc->vc_font.height - 1); | ||
3076 | caps->len = (p->userfont) ? | ||
3077 | FNTCHARCNT(p->fontdata) : 256; | ||
3078 | } | ||
3079 | } | ||
3080 | } | ||
3081 | |||
3005 | static int fbcon_event_notify(struct notifier_block *self, | 3082 | static int fbcon_event_notify(struct notifier_block *self, |
3006 | unsigned long action, void *data) | 3083 | unsigned long action, void *data) |
3007 | { | 3084 | { |
@@ -3009,6 +3086,7 @@ static int fbcon_event_notify(struct notifier_block *self, | |||
3009 | struct fb_info *info = event->info; | 3086 | struct fb_info *info = event->info; |
3010 | struct fb_videomode *mode; | 3087 | struct fb_videomode *mode; |
3011 | struct fb_con2fbmap *con2fb; | 3088 | struct fb_con2fbmap *con2fb; |
3089 | struct fb_blit_caps *caps; | ||
3012 | int ret = 0; | 3090 | int ret = 0; |
3013 | 3091 | ||
3014 | /* | 3092 | /* |
@@ -3057,6 +3135,10 @@ static int fbcon_event_notify(struct notifier_block *self, | |||
3057 | case FB_EVENT_NEW_MODELIST: | 3135 | case FB_EVENT_NEW_MODELIST: |
3058 | fbcon_new_modelist(info); | 3136 | fbcon_new_modelist(info); |
3059 | break; | 3137 | break; |
3138 | case FB_EVENT_GET_REQ: | ||
3139 | caps = event->data; | ||
3140 | fbcon_get_requirement(info, caps); | ||
3141 | break; | ||
3060 | } | 3142 | } |
3061 | 3143 | ||
3062 | done: | 3144 | done: |
diff --git a/drivers/video/console/fonts.c b/drivers/video/console/fonts.c index c960728b7e8..a6828d0a4c5 100644 --- a/drivers/video/console/fonts.c +++ b/drivers/video/console/fonts.c | |||
@@ -98,6 +98,8 @@ const struct font_desc *find_font(const char *name) | |||
98 | * get_default_font - get default font | 98 | * get_default_font - get default font |
99 | * @xres: screen size of X | 99 | * @xres: screen size of X |
100 | * @yres: screen size of Y | 100 | * @yres: screen size of Y |
101 | * @font_w: bit array of supported widths (1 - 32) | ||
102 | * @font_h: bit array of supported heights (1 - 32) | ||
101 | * | 103 | * |
102 | * Get the default font for a specified screen size. | 104 | * Get the default font for a specified screen size. |
103 | * Dimensions are in pixels. | 105 | * Dimensions are in pixels. |
@@ -107,7 +109,8 @@ const struct font_desc *find_font(const char *name) | |||
107 | * | 109 | * |
108 | */ | 110 | */ |
109 | 111 | ||
110 | const struct font_desc *get_default_font(int xres, int yres) | 112 | const struct font_desc *get_default_font(int xres, int yres, u32 font_w, |
113 | u32 font_h) | ||
111 | { | 114 | { |
112 | int i, c, cc; | 115 | int i, c, cc; |
113 | const struct font_desc *f, *g; | 116 | const struct font_desc *f, *g; |
@@ -129,6 +132,11 @@ const struct font_desc *get_default_font(int xres, int yres) | |||
129 | #endif | 132 | #endif |
130 | if ((yres < 400) == (f->height <= 8)) | 133 | if ((yres < 400) == (f->height <= 8)) |
131 | c += 1000; | 134 | c += 1000; |
135 | |||
136 | if (!(font_w & (1 << (f->width - 1))) || | ||
137 | !(font_w & (1 << (f->height - 1)))) | ||
138 | c += 1000; | ||
139 | |||
132 | if (c > cc) { | 140 | if (c > cc) { |
133 | cc = c; | 141 | cc = c; |
134 | g = f; | 142 | g = f; |
diff --git a/drivers/video/console/mdacon.c b/drivers/video/console/mdacon.c index 124ecbe6f88..bd8d995fe25 100644 --- a/drivers/video/console/mdacon.c +++ b/drivers/video/console/mdacon.c | |||
@@ -384,7 +384,7 @@ static inline u16 mda_convert_attr(u16 ch) | |||
384 | } | 384 | } |
385 | 385 | ||
386 | static u8 mdacon_build_attr(struct vc_data *c, u8 color, u8 intensity, | 386 | static u8 mdacon_build_attr(struct vc_data *c, u8 color, u8 intensity, |
387 | u8 blink, u8 underline, u8 reverse) | 387 | u8 blink, u8 underline, u8 reverse, u8 italic) |
388 | { | 388 | { |
389 | /* The attribute is just a bit vector: | 389 | /* The attribute is just a bit vector: |
390 | * | 390 | * |
@@ -397,6 +397,7 @@ static u8 mdacon_build_attr(struct vc_data *c, u8 color, u8 intensity, | |||
397 | return (intensity & 3) | | 397 | return (intensity & 3) | |
398 | ((underline & 1) << 2) | | 398 | ((underline & 1) << 2) | |
399 | ((reverse & 1) << 3) | | 399 | ((reverse & 1) << 3) | |
400 | (!!italic << 4) | | ||
400 | ((blink & 1) << 7); | 401 | ((blink & 1) << 7); |
401 | } | 402 | } |
402 | 403 | ||
diff --git a/drivers/video/console/promcon.c b/drivers/video/console/promcon.c index b78eac63459..ae02e4eb18e 100644 --- a/drivers/video/console/promcon.c +++ b/drivers/video/console/promcon.c | |||
@@ -548,7 +548,8 @@ promcon_scroll(struct vc_data *conp, int t, int b, int dir, int count) | |||
548 | } | 548 | } |
549 | 549 | ||
550 | #if !(PROMCON_COLOR) | 550 | #if !(PROMCON_COLOR) |
551 | static u8 promcon_build_attr(struct vc_data *conp, u8 _color, u8 _intensity, u8 _blink, u8 _underline, u8 _reverse) | 551 | static u8 promcon_build_attr(struct vc_data *conp, u8 _color, u8 _intensity, |
552 | u8 _blink, u8 _underline, u8 _reverse, u8 _italic) | ||
552 | { | 553 | { |
553 | return (_reverse) ? 0xf : 0x7; | 554 | return (_reverse) ? 0xf : 0x7; |
554 | } | 555 | } |
diff --git a/drivers/video/console/sticon.c b/drivers/video/console/sticon.c index 57b21e53303..67a682d6cc7 100644 --- a/drivers/video/console/sticon.c +++ b/drivers/video/console/sticon.c | |||
@@ -314,7 +314,7 @@ static unsigned long sticon_getxy(struct vc_data *conp, unsigned long pos, | |||
314 | } | 314 | } |
315 | 315 | ||
316 | static u8 sticon_build_attr(struct vc_data *conp, u8 color, u8 intens, | 316 | static u8 sticon_build_attr(struct vc_data *conp, u8 color, u8 intens, |
317 | u8 blink, u8 underline, u8 reverse) | 317 | u8 blink, u8 underline, u8 reverse, u8 italic) |
318 | { | 318 | { |
319 | u8 attr = ((color & 0x70) >> 1) | ((color & 7)); | 319 | u8 attr = ((color & 0x70) >> 1) | ((color & 7)); |
320 | 320 | ||
diff --git a/drivers/video/console/sticore.c b/drivers/video/console/sticore.c index 88e7038eab8..717b360d041 100644 --- a/drivers/video/console/sticore.c +++ b/drivers/video/console/sticore.c | |||
@@ -495,7 +495,7 @@ sti_select_fbfont(struct sti_cooked_rom *cooked_rom, const char *fbfont_name) | |||
495 | return NULL; | 495 | return NULL; |
496 | fbfont = find_font(fbfont_name); | 496 | fbfont = find_font(fbfont_name); |
497 | if (!fbfont) | 497 | if (!fbfont) |
498 | fbfont = get_default_font(1024,768); | 498 | fbfont = get_default_font(1024,768, ~(u32)0, ~(u32)0); |
499 | if (!fbfont) | 499 | if (!fbfont) |
500 | return NULL; | 500 | return NULL; |
501 | 501 | ||
diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c index 3e67c34df9a..2460b82a1d9 100644 --- a/drivers/video/console/vgacon.c +++ b/drivers/video/console/vgacon.c | |||
@@ -86,8 +86,6 @@ static int vgacon_set_origin(struct vc_data *c); | |||
86 | static void vgacon_save_screen(struct vc_data *c); | 86 | static void vgacon_save_screen(struct vc_data *c); |
87 | static int vgacon_scroll(struct vc_data *c, int t, int b, int dir, | 87 | static int vgacon_scroll(struct vc_data *c, int t, int b, int dir, |
88 | int lines); | 88 | int lines); |
89 | static u8 vgacon_build_attr(struct vc_data *c, u8 color, u8 intensity, | ||
90 | u8 blink, u8 underline, u8 reverse); | ||
91 | static void vgacon_invert_region(struct vc_data *c, u16 * p, int count); | 89 | static void vgacon_invert_region(struct vc_data *c, u16 * p, int count); |
92 | static unsigned long vgacon_uni_pagedir[2]; | 90 | static unsigned long vgacon_uni_pagedir[2]; |
93 | 91 | ||
@@ -578,12 +576,14 @@ static void vgacon_deinit(struct vc_data *c) | |||
578 | } | 576 | } |
579 | 577 | ||
580 | static u8 vgacon_build_attr(struct vc_data *c, u8 color, u8 intensity, | 578 | static u8 vgacon_build_attr(struct vc_data *c, u8 color, u8 intensity, |
581 | u8 blink, u8 underline, u8 reverse) | 579 | u8 blink, u8 underline, u8 reverse, u8 italic) |
582 | { | 580 | { |
583 | u8 attr = color; | 581 | u8 attr = color; |
584 | 582 | ||
585 | if (vga_can_do_color) { | 583 | if (vga_can_do_color) { |
586 | if (underline) | 584 | if (italic) |
585 | attr = (attr & 0xF0) | c->vc_itcolor; | ||
586 | else if (underline) | ||
587 | attr = (attr & 0xf0) | c->vc_ulcolor; | 587 | attr = (attr & 0xf0) | c->vc_ulcolor; |
588 | else if (intensity == 0) | 588 | else if (intensity == 0) |
589 | attr = (attr & 0xf0) | c->vc_halfcolor; | 589 | attr = (attr & 0xf0) | c->vc_halfcolor; |
@@ -597,7 +597,9 @@ static u8 vgacon_build_attr(struct vc_data *c, u8 color, u8 intensity, | |||
597 | if (intensity == 2) | 597 | if (intensity == 2) |
598 | attr ^= 0x08; | 598 | attr ^= 0x08; |
599 | if (!vga_can_do_color) { | 599 | if (!vga_can_do_color) { |
600 | if (underline) | 600 | if (italic) |
601 | attr = (attr & 0xF8) | 0x02; | ||
602 | else if (underline) | ||
601 | attr = (attr & 0xf8) | 0x01; | 603 | attr = (attr & 0xf8) | 0x01; |
602 | else if (intensity == 0) | 604 | else if (intensity == 0) |
603 | attr = (attr & 0xf0) | 0x08; | 605 | attr = (attr & 0xf0) | 0x08; |
@@ -658,6 +660,9 @@ static void vgacon_set_cursor_size(int xpos, int from, int to) | |||
658 | 660 | ||
659 | static void vgacon_cursor(struct vc_data *c, int mode) | 661 | static void vgacon_cursor(struct vc_data *c, int mode) |
660 | { | 662 | { |
663 | if (c->vc_mode != KD_TEXT) | ||
664 | return; | ||
665 | |||
661 | vgacon_restore_screen(c); | 666 | vgacon_restore_screen(c); |
662 | 667 | ||
663 | switch (mode) { | 668 | switch (mode) { |
@@ -1316,7 +1321,7 @@ static int vgacon_scroll(struct vc_data *c, int t, int b, int dir, | |||
1316 | unsigned long oldo; | 1321 | unsigned long oldo; |
1317 | unsigned int delta; | 1322 | unsigned int delta; |
1318 | 1323 | ||
1319 | if (t || b != c->vc_rows || vga_is_gfx) | 1324 | if (t || b != c->vc_rows || vga_is_gfx || c->vc_mode != KD_TEXT) |
1320 | return 0; | 1325 | return 0; |
1321 | 1326 | ||
1322 | if (!vga_hardscroll_enabled || lines >= c->vc_rows / 2) | 1327 | if (!vga_hardscroll_enabled || lines >= c->vc_rows / 2) |
diff --git a/drivers/video/display/Kconfig b/drivers/video/display/Kconfig new file mode 100644 index 00000000000..f99af931d4f --- /dev/null +++ b/drivers/video/display/Kconfig | |||
@@ -0,0 +1,24 @@ | |||
1 | # | ||
2 | # Display drivers configuration | ||
3 | # | ||
4 | |||
5 | menu "Display device support" | ||
6 | |||
7 | config DISPLAY_SUPPORT | ||
8 | tristate "Display panel/monitor support" | ||
9 | ---help--- | ||
10 | This framework adds support for low-level control of a display. | ||
11 | This includes support for power. | ||
12 | |||
13 | Enable this to be able to choose the drivers for controlling the | ||
14 | physical display panel/monitor on some platforms. This not only | ||
15 | covers LCD displays for PDAs but also other types of displays | ||
16 | such as CRT, TVout etc. | ||
17 | |||
18 | To have support for your specific display panel you will have to | ||
19 | select the proper drivers which depend on this option. | ||
20 | |||
21 | comment "Display hardware drivers" | ||
22 | depends on DISPLAY_SUPPORT | ||
23 | |||
24 | endmenu | ||
diff --git a/drivers/video/display/Makefile b/drivers/video/display/Makefile new file mode 100644 index 00000000000..c0ea832bf17 --- /dev/null +++ b/drivers/video/display/Makefile | |||
@@ -0,0 +1,6 @@ | |||
1 | # Display drivers | ||
2 | |||
3 | display-objs := display-sysfs.o | ||
4 | |||
5 | obj-$(CONFIG_DISPLAY_SUPPORT) += display.o | ||
6 | |||
diff --git a/drivers/video/display/display-sysfs.c b/drivers/video/display/display-sysfs.c new file mode 100644 index 00000000000..35477177bef --- /dev/null +++ b/drivers/video/display/display-sysfs.c | |||
@@ -0,0 +1,217 @@ | |||
1 | /* | ||
2 | * display-sysfs.c - Display output driver sysfs interface | ||
3 | * | ||
4 | * Copyright (C) 2007 James Simmons <jsimmons@infradead.org> | ||
5 | * | ||
6 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or (at | ||
11 | * your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but | ||
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
16 | * General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | ||
21 | * | ||
22 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
23 | */ | ||
24 | #include <linux/module.h> | ||
25 | #include <linux/display.h> | ||
26 | #include <linux/ctype.h> | ||
27 | #include <linux/idr.h> | ||
28 | #include <linux/err.h> | ||
29 | |||
30 | static ssize_t display_show_name(struct device *dev, | ||
31 | struct device_attribute *attr, char *buf) | ||
32 | { | ||
33 | struct display_device *dsp = dev_get_drvdata(dev); | ||
34 | return snprintf(buf, PAGE_SIZE, "%s\n", dsp->name); | ||
35 | } | ||
36 | |||
37 | static ssize_t display_show_type(struct device *dev, | ||
38 | struct device_attribute *attr, char *buf) | ||
39 | { | ||
40 | struct display_device *dsp = dev_get_drvdata(dev); | ||
41 | return snprintf(buf, PAGE_SIZE, "%s\n", dsp->type); | ||
42 | } | ||
43 | |||
44 | static ssize_t display_show_contrast(struct device *dev, | ||
45 | struct device_attribute *attr, char *buf) | ||
46 | { | ||
47 | struct display_device *dsp = dev_get_drvdata(dev); | ||
48 | ssize_t rc = -ENXIO; | ||
49 | |||
50 | mutex_lock(&dsp->lock); | ||
51 | if (likely(dsp->driver) && dsp->driver->get_contrast) | ||
52 | rc = sprintf(buf, "%d\n", dsp->driver->get_contrast(dsp)); | ||
53 | mutex_unlock(&dsp->lock); | ||
54 | return rc; | ||
55 | } | ||
56 | |||
57 | static ssize_t display_store_contrast(struct device *dev, | ||
58 | struct device_attribute *attr, | ||
59 | const char *buf, size_t count) | ||
60 | { | ||
61 | struct display_device *dsp = dev_get_drvdata(dev); | ||
62 | ssize_t ret = -EINVAL, size; | ||
63 | int contrast; | ||
64 | char *endp; | ||
65 | |||
66 | contrast = simple_strtoul(buf, &endp, 0); | ||
67 | size = endp - buf; | ||
68 | |||
69 | if (*endp && isspace(*endp)) | ||
70 | size++; | ||
71 | |||
72 | if (size != count) | ||
73 | return ret; | ||
74 | |||
75 | mutex_lock(&dsp->lock); | ||
76 | if (likely(dsp->driver && dsp->driver->set_contrast)) { | ||
77 | pr_debug("display: set contrast to %d\n", contrast); | ||
78 | dsp->driver->set_contrast(dsp, contrast); | ||
79 | ret = count; | ||
80 | } | ||
81 | mutex_unlock(&dsp->lock); | ||
82 | return ret; | ||
83 | } | ||
84 | |||
85 | static ssize_t display_show_max_contrast(struct device *dev, | ||
86 | struct device_attribute *attr, | ||
87 | char *buf) | ||
88 | { | ||
89 | struct display_device *dsp = dev_get_drvdata(dev); | ||
90 | ssize_t rc = -ENXIO; | ||
91 | |||
92 | mutex_lock(&dsp->lock); | ||
93 | if (likely(dsp->driver)) | ||
94 | rc = sprintf(buf, "%d\n", dsp->driver->max_contrast); | ||
95 | mutex_unlock(&dsp->lock); | ||
96 | return rc; | ||
97 | } | ||
98 | |||
99 | static struct device_attribute display_attrs[] = { | ||
100 | __ATTR(name, S_IRUGO, display_show_name, NULL), | ||
101 | __ATTR(type, S_IRUGO, display_show_type, NULL), | ||
102 | __ATTR(contrast, S_IRUGO | S_IWUSR, display_show_contrast, display_store_contrast), | ||
103 | __ATTR(max_contrast, S_IRUGO, display_show_max_contrast, NULL), | ||
104 | }; | ||
105 | |||
106 | static int display_suspend(struct device *dev, pm_message_t state) | ||
107 | { | ||
108 | struct display_device *dsp = dev_get_drvdata(dev); | ||
109 | |||
110 | mutex_lock(&dsp->lock); | ||
111 | if (likely(dsp->driver->suspend)) | ||
112 | dsp->driver->suspend(dsp, state); | ||
113 | mutex_unlock(&dsp->lock); | ||
114 | return 0; | ||
115 | }; | ||
116 | |||
117 | static int display_resume(struct device *dev) | ||
118 | { | ||
119 | struct display_device *dsp = dev_get_drvdata(dev); | ||
120 | |||
121 | mutex_lock(&dsp->lock); | ||
122 | if (likely(dsp->driver->resume)) | ||
123 | dsp->driver->resume(dsp); | ||
124 | mutex_unlock(&dsp->lock); | ||
125 | return 0; | ||
126 | }; | ||
127 | |||
128 | static struct mutex allocated_dsp_lock; | ||
129 | static DEFINE_IDR(allocated_dsp); | ||
130 | static struct class *display_class; | ||
131 | |||
132 | struct display_device *display_device_register(struct display_driver *driver, | ||
133 | struct device *parent, void *devdata) | ||
134 | { | ||
135 | struct display_device *new_dev = NULL; | ||
136 | int ret = -EINVAL; | ||
137 | |||
138 | if (unlikely(!driver)) | ||
139 | return ERR_PTR(ret); | ||
140 | |||
141 | mutex_lock(&allocated_dsp_lock); | ||
142 | ret = idr_pre_get(&allocated_dsp, GFP_KERNEL); | ||
143 | mutex_unlock(&allocated_dsp_lock); | ||
144 | if (!ret) | ||
145 | return ERR_PTR(ret); | ||
146 | |||
147 | new_dev = kzalloc(sizeof(struct display_device), GFP_KERNEL); | ||
148 | if (likely(new_dev) && unlikely(driver->probe(new_dev, devdata))) { | ||
149 | // Reserve the index for this display | ||
150 | mutex_lock(&allocated_dsp_lock); | ||
151 | ret = idr_get_new(&allocated_dsp, new_dev, &new_dev->idx); | ||
152 | mutex_unlock(&allocated_dsp_lock); | ||
153 | |||
154 | if (!ret) { | ||
155 | new_dev->dev = device_create(display_class, parent, 0, | ||
156 | "display%d", new_dev->idx); | ||
157 | if (!IS_ERR(new_dev->dev)) { | ||
158 | dev_set_drvdata(new_dev->dev, new_dev); | ||
159 | new_dev->parent = parent; | ||
160 | new_dev->driver = driver; | ||
161 | mutex_init(&new_dev->lock); | ||
162 | return new_dev; | ||
163 | } | ||
164 | mutex_lock(&allocated_dsp_lock); | ||
165 | idr_remove(&allocated_dsp, new_dev->idx); | ||
166 | mutex_unlock(&allocated_dsp_lock); | ||
167 | ret = -EINVAL; | ||
168 | } | ||
169 | } | ||
170 | kfree(new_dev); | ||
171 | return ERR_PTR(ret); | ||
172 | } | ||
173 | EXPORT_SYMBOL(display_device_register); | ||
174 | |||
175 | void display_device_unregister(struct display_device *ddev) | ||
176 | { | ||
177 | if (!ddev) | ||
178 | return; | ||
179 | // Free device | ||
180 | mutex_lock(&ddev->lock); | ||
181 | device_unregister(ddev->dev); | ||
182 | mutex_unlock(&ddev->lock); | ||
183 | // Mark device index as avaliable | ||
184 | mutex_lock(&allocated_dsp_lock); | ||
185 | idr_remove(&allocated_dsp, ddev->idx); | ||
186 | mutex_unlock(&allocated_dsp_lock); | ||
187 | kfree(ddev); | ||
188 | } | ||
189 | EXPORT_SYMBOL(display_device_unregister); | ||
190 | |||
191 | static int __init display_class_init(void) | ||
192 | { | ||
193 | display_class = class_create(THIS_MODULE, "display"); | ||
194 | if (IS_ERR(display_class)) { | ||
195 | printk(KERN_ERR "Failed to create display class\n"); | ||
196 | display_class = NULL; | ||
197 | return -EINVAL; | ||
198 | } | ||
199 | display_class->dev_attrs = display_attrs; | ||
200 | display_class->suspend = display_suspend; | ||
201 | display_class->resume = display_resume; | ||
202 | mutex_init(&allocated_dsp_lock); | ||
203 | return 0; | ||
204 | } | ||
205 | |||
206 | static void __exit display_class_exit(void) | ||
207 | { | ||
208 | class_destroy(display_class); | ||
209 | } | ||
210 | |||
211 | module_init(display_class_init); | ||
212 | module_exit(display_class_exit); | ||
213 | |||
214 | MODULE_DESCRIPTION("Display Hardware handling"); | ||
215 | MODULE_AUTHOR("James Simmons <jsimmons@infradead.org>"); | ||
216 | MODULE_LICENSE("GPL"); | ||
217 | |||
diff --git a/drivers/video/epson1355fb.c b/drivers/video/epson1355fb.c index 29e07c10988..ca2c54ce508 100644 --- a/drivers/video/epson1355fb.c +++ b/drivers/video/epson1355fb.c | |||
@@ -403,17 +403,10 @@ static inline unsigned long copy_to_user16(void *to, const void *from, | |||
403 | 403 | ||
404 | 404 | ||
405 | static ssize_t | 405 | static ssize_t |
406 | epson1355fb_read(struct file *file, char *buf, size_t count, loff_t * ppos) | 406 | epson1355fb_read(struct fb_info *info, char *buf, size_t count, loff_t * ppos) |
407 | { | 407 | { |
408 | struct inode *inode = file->f_path.dentry->d_inode; | ||
409 | int fbidx = iminor(inode); | ||
410 | struct fb_info *info = registered_fb[fbidx]; | ||
411 | unsigned long p = *ppos; | 408 | unsigned long p = *ppos; |
412 | 409 | ||
413 | /* from fbmem.c except for our own copy_*_user */ | ||
414 | if (!info || !info->screen_base) | ||
415 | return -ENODEV; | ||
416 | |||
417 | if (p >= info->fix.smem_len) | 410 | if (p >= info->fix.smem_len) |
418 | return 0; | 411 | return 0; |
419 | if (count >= info->fix.smem_len) | 412 | if (count >= info->fix.smem_len) |
@@ -434,20 +427,13 @@ epson1355fb_read(struct file *file, char *buf, size_t count, loff_t * ppos) | |||
434 | } | 427 | } |
435 | 428 | ||
436 | static ssize_t | 429 | static ssize_t |
437 | epson1355fb_write(struct file *file, const char *buf, | 430 | epson1355fb_write(struct fb_info *info, const char *buf, |
438 | size_t count, loff_t * ppos) | 431 | size_t count, loff_t * ppos) |
439 | { | 432 | { |
440 | struct inode *inode = file->f_path.dentry->d_inode; | ||
441 | int fbidx = iminor(inode); | ||
442 | struct fb_info *info = registered_fb[fbidx]; | ||
443 | unsigned long p = *ppos; | 433 | unsigned long p = *ppos; |
444 | int err; | 434 | int err; |
445 | 435 | ||
446 | /* from fbmem.c except for our own copy_*_user */ | 436 | /* from fbmem.c except for our own copy_*_user */ |
447 | if (!info || !info->screen_base) | ||
448 | return -ENODEV; | ||
449 | |||
450 | /* from fbmem.c except for our own copy_*_user */ | ||
451 | if (p > info->fix.smem_len) | 437 | if (p > info->fix.smem_len) |
452 | return -ENOSPC; | 438 | return -ENOSPC; |
453 | if (count >= info->fix.smem_len) | 439 | if (count >= info->fix.smem_len) |
@@ -650,9 +636,10 @@ int __init epson1355fb_probe(struct platform_device *dev) | |||
650 | } | 636 | } |
651 | 637 | ||
652 | info = framebuffer_alloc(sizeof(struct epson1355_par) + sizeof(u32) * 256, &dev->dev); | 638 | info = framebuffer_alloc(sizeof(struct epson1355_par) + sizeof(u32) * 256, &dev->dev); |
653 | if (!info) | 639 | if (!info) { |
654 | rc = -ENOMEM; | 640 | rc = -ENOMEM; |
655 | goto bail; | 641 | goto bail; |
642 | } | ||
656 | 643 | ||
657 | default_par = info->par; | 644 | default_par = info->par; |
658 | default_par->reg_addr = (unsigned long) ioremap(EPSON1355FB_REGS_PHYS, EPSON1355FB_REGS_LEN); | 645 | default_par->reg_addr = (unsigned long) ioremap(EPSON1355FB_REGS_PHYS, EPSON1355FB_REGS_LEN); |
diff --git a/drivers/video/fb_defio.c b/drivers/video/fb_defio.c new file mode 100644 index 00000000000..1a8643f053d --- /dev/null +++ b/drivers/video/fb_defio.c | |||
@@ -0,0 +1,151 @@ | |||
1 | /* | ||
2 | * linux/drivers/video/fb_defio.c | ||
3 | * | ||
4 | * Copyright (C) 2006 Jaya Kumar | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file COPYING in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | |||
11 | #include <linux/module.h> | ||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/errno.h> | ||
14 | #include <linux/string.h> | ||
15 | #include <linux/mm.h> | ||
16 | #include <linux/slab.h> | ||
17 | #include <linux/vmalloc.h> | ||
18 | #include <linux/delay.h> | ||
19 | #include <linux/interrupt.h> | ||
20 | #include <linux/fb.h> | ||
21 | #include <linux/list.h> | ||
22 | #include <asm/uaccess.h> | ||
23 | |||
24 | /* to support deferred IO */ | ||
25 | #include <linux/rmap.h> | ||
26 | #include <linux/pagemap.h> | ||
27 | |||
28 | /* this is to find and return the vmalloc-ed fb pages */ | ||
29 | static struct page* fb_deferred_io_nopage(struct vm_area_struct *vma, | ||
30 | unsigned long vaddr, int *type) | ||
31 | { | ||
32 | unsigned long offset; | ||
33 | struct page *page; | ||
34 | struct fb_info *info = vma->vm_private_data; | ||
35 | /* info->screen_base is in System RAM */ | ||
36 | void *screen_base = (void __force *) info->screen_base; | ||
37 | |||
38 | offset = (vaddr - vma->vm_start) + (vma->vm_pgoff << PAGE_SHIFT); | ||
39 | if (offset >= info->fix.smem_len) | ||
40 | return NOPAGE_SIGBUS; | ||
41 | |||
42 | page = vmalloc_to_page(screen_base + offset); | ||
43 | if (!page) | ||
44 | return NOPAGE_OOM; | ||
45 | |||
46 | get_page(page); | ||
47 | if (type) | ||
48 | *type = VM_FAULT_MINOR; | ||
49 | return page; | ||
50 | } | ||
51 | |||
52 | int fb_deferred_io_fsync(struct file *file, struct dentry *dentry, int datasync) | ||
53 | { | ||
54 | struct fb_info *info = file->private_data; | ||
55 | |||
56 | /* Kill off the delayed work */ | ||
57 | cancel_rearming_delayed_work(&info->deferred_work); | ||
58 | |||
59 | /* Run it immediately */ | ||
60 | return schedule_delayed_work(&info->deferred_work, 0); | ||
61 | } | ||
62 | EXPORT_SYMBOL_GPL(fb_deferred_io_fsync); | ||
63 | |||
64 | /* vm_ops->page_mkwrite handler */ | ||
65 | static int fb_deferred_io_mkwrite(struct vm_area_struct *vma, | ||
66 | struct page *page) | ||
67 | { | ||
68 | struct fb_info *info = vma->vm_private_data; | ||
69 | struct fb_deferred_io *fbdefio = info->fbdefio; | ||
70 | |||
71 | /* this is a callback we get when userspace first tries to | ||
72 | write to the page. we schedule a workqueue. that workqueue | ||
73 | will eventually mkclean the touched pages and execute the | ||
74 | deferred framebuffer IO. then if userspace touches a page | ||
75 | again, we repeat the same scheme */ | ||
76 | |||
77 | /* protect against the workqueue changing the page list */ | ||
78 | mutex_lock(&fbdefio->lock); | ||
79 | list_add(&page->lru, &fbdefio->pagelist); | ||
80 | mutex_unlock(&fbdefio->lock); | ||
81 | |||
82 | /* come back after delay to process the deferred IO */ | ||
83 | schedule_delayed_work(&info->deferred_work, fbdefio->delay); | ||
84 | return 0; | ||
85 | } | ||
86 | |||
87 | static struct vm_operations_struct fb_deferred_io_vm_ops = { | ||
88 | .nopage = fb_deferred_io_nopage, | ||
89 | .page_mkwrite = fb_deferred_io_mkwrite, | ||
90 | }; | ||
91 | |||
92 | static int fb_deferred_io_mmap(struct fb_info *info, struct vm_area_struct *vma) | ||
93 | { | ||
94 | vma->vm_ops = &fb_deferred_io_vm_ops; | ||
95 | vma->vm_flags |= ( VM_IO | VM_RESERVED | VM_DONTEXPAND ); | ||
96 | vma->vm_private_data = info; | ||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | /* workqueue callback */ | ||
101 | static void fb_deferred_io_work(struct work_struct *work) | ||
102 | { | ||
103 | struct fb_info *info = container_of(work, struct fb_info, | ||
104 | deferred_work.work); | ||
105 | struct list_head *node, *next; | ||
106 | struct page *cur; | ||
107 | struct fb_deferred_io *fbdefio = info->fbdefio; | ||
108 | |||
109 | /* here we mkclean the pages, then do all deferred IO */ | ||
110 | mutex_lock(&fbdefio->lock); | ||
111 | list_for_each_entry(cur, &fbdefio->pagelist, lru) { | ||
112 | lock_page(cur); | ||
113 | page_mkclean(cur); | ||
114 | unlock_page(cur); | ||
115 | } | ||
116 | |||
117 | /* driver's callback with pagelist */ | ||
118 | fbdefio->deferred_io(info, &fbdefio->pagelist); | ||
119 | |||
120 | /* clear the list */ | ||
121 | list_for_each_safe(node, next, &fbdefio->pagelist) { | ||
122 | list_del(node); | ||
123 | } | ||
124 | mutex_unlock(&fbdefio->lock); | ||
125 | } | ||
126 | |||
127 | void fb_deferred_io_init(struct fb_info *info) | ||
128 | { | ||
129 | struct fb_deferred_io *fbdefio = info->fbdefio; | ||
130 | |||
131 | BUG_ON(!fbdefio); | ||
132 | mutex_init(&fbdefio->lock); | ||
133 | info->fbops->fb_mmap = fb_deferred_io_mmap; | ||
134 | INIT_DELAYED_WORK(&info->deferred_work, fb_deferred_io_work); | ||
135 | INIT_LIST_HEAD(&fbdefio->pagelist); | ||
136 | if (fbdefio->delay == 0) /* set a default of 1 s */ | ||
137 | fbdefio->delay = HZ; | ||
138 | } | ||
139 | EXPORT_SYMBOL_GPL(fb_deferred_io_init); | ||
140 | |||
141 | void fb_deferred_io_cleanup(struct fb_info *info) | ||
142 | { | ||
143 | struct fb_deferred_io *fbdefio = info->fbdefio; | ||
144 | |||
145 | BUG_ON(!fbdefio); | ||
146 | cancel_delayed_work(&info->deferred_work); | ||
147 | flush_scheduled_work(); | ||
148 | } | ||
149 | EXPORT_SYMBOL_GPL(fb_deferred_io_cleanup); | ||
150 | |||
151 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/fb_draw.h b/drivers/video/fb_draw.h new file mode 100644 index 00000000000..c5c45203833 --- /dev/null +++ b/drivers/video/fb_draw.h | |||
@@ -0,0 +1,72 @@ | |||
1 | #ifndef _FB_DRAW_H | ||
2 | #define _FB_DRAW_H | ||
3 | |||
4 | #include <asm/types.h> | ||
5 | |||
6 | /* | ||
7 | * Compose two values, using a bitmask as decision value | ||
8 | * This is equivalent to (a & mask) | (b & ~mask) | ||
9 | */ | ||
10 | |||
11 | static inline unsigned long | ||
12 | comp(unsigned long a, unsigned long b, unsigned long mask) | ||
13 | { | ||
14 | return ((a ^ b) & mask) ^ b; | ||
15 | } | ||
16 | |||
17 | /* | ||
18 | * Create a pattern with the given pixel's color | ||
19 | */ | ||
20 | |||
21 | #if BITS_PER_LONG == 64 | ||
22 | static inline unsigned long | ||
23 | pixel_to_pat( u32 bpp, u32 pixel) | ||
24 | { | ||
25 | switch (bpp) { | ||
26 | case 1: | ||
27 | return 0xfffffffffffffffful*pixel; | ||
28 | case 2: | ||
29 | return 0x5555555555555555ul*pixel; | ||
30 | case 4: | ||
31 | return 0x1111111111111111ul*pixel; | ||
32 | case 8: | ||
33 | return 0x0101010101010101ul*pixel; | ||
34 | case 12: | ||
35 | return 0x0001001001001001ul*pixel; | ||
36 | case 16: | ||
37 | return 0x0001000100010001ul*pixel; | ||
38 | case 24: | ||
39 | return 0x0000000001000001ul*pixel; | ||
40 | case 32: | ||
41 | return 0x0000000100000001ul*pixel; | ||
42 | default: | ||
43 | panic("pixel_to_pat(): unsupported pixelformat\n"); | ||
44 | } | ||
45 | } | ||
46 | #else | ||
47 | static inline unsigned long | ||
48 | pixel_to_pat( u32 bpp, u32 pixel) | ||
49 | { | ||
50 | switch (bpp) { | ||
51 | case 1: | ||
52 | return 0xfffffffful*pixel; | ||
53 | case 2: | ||
54 | return 0x55555555ul*pixel; | ||
55 | case 4: | ||
56 | return 0x11111111ul*pixel; | ||
57 | case 8: | ||
58 | return 0x01010101ul*pixel; | ||
59 | case 12: | ||
60 | return 0x00001001ul*pixel; | ||
61 | case 16: | ||
62 | return 0x00010001ul*pixel; | ||
63 | case 24: | ||
64 | return 0x00000001ul*pixel; | ||
65 | case 32: | ||
66 | return 0x00000001ul*pixel; | ||
67 | default: | ||
68 | panic("pixel_to_pat(): unsupported pixelformat\n"); | ||
69 | } | ||
70 | } | ||
71 | #endif | ||
72 | #endif /* FB_DRAW_H */ | ||
diff --git a/drivers/video/fb_sys_fops.c b/drivers/video/fb_sys_fops.c new file mode 100644 index 00000000000..cf2538d669c --- /dev/null +++ b/drivers/video/fb_sys_fops.c | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * linux/drivers/video/fb_sys_read.c - Generic file operations where | ||
3 | * framebuffer is in system RAM | ||
4 | * | ||
5 | * Copyright (C) 2007 Antonino Daplas <adaplas@pol.net> | ||
6 | * | ||
7 | * This file is subject to the terms and conditions of the GNU General Public | ||
8 | * License. See the file COPYING in the main directory of this archive | ||
9 | * for more details. | ||
10 | * | ||
11 | */ | ||
12 | #include <linux/fb.h> | ||
13 | #include <linux/module.h> | ||
14 | #include <asm/uaccess.h> | ||
15 | |||
16 | ssize_t fb_sys_read(struct fb_info *info, char __user *buf, size_t count, | ||
17 | loff_t *ppos) | ||
18 | { | ||
19 | unsigned long p = *ppos; | ||
20 | void *src; | ||
21 | int err = 0; | ||
22 | unsigned long total_size; | ||
23 | |||
24 | if (info->state != FBINFO_STATE_RUNNING) | ||
25 | return -EPERM; | ||
26 | |||
27 | total_size = info->screen_size; | ||
28 | |||
29 | if (total_size == 0) | ||
30 | total_size = info->fix.smem_len; | ||
31 | |||
32 | if (p >= total_size) | ||
33 | return 0; | ||
34 | |||
35 | if (count >= total_size) | ||
36 | count = total_size; | ||
37 | |||
38 | if (count + p > total_size) | ||
39 | count = total_size - p; | ||
40 | |||
41 | src = (void __force *)(info->screen_base + p); | ||
42 | |||
43 | if (info->fbops->fb_sync) | ||
44 | info->fbops->fb_sync(info); | ||
45 | |||
46 | if (copy_to_user(buf, src, count)) | ||
47 | err = -EFAULT; | ||
48 | |||
49 | if (!err) | ||
50 | *ppos += count; | ||
51 | |||
52 | return (err) ? err : count; | ||
53 | } | ||
54 | EXPORT_SYMBOL_GPL(fb_sys_read); | ||
55 | |||
56 | ssize_t fb_sys_write(struct fb_info *info, const char __user *buf, | ||
57 | size_t count, loff_t *ppos) | ||
58 | { | ||
59 | unsigned long p = *ppos; | ||
60 | void *dst; | ||
61 | int err = 0; | ||
62 | unsigned long total_size; | ||
63 | |||
64 | if (info->state != FBINFO_STATE_RUNNING) | ||
65 | return -EPERM; | ||
66 | |||
67 | total_size = info->screen_size; | ||
68 | |||
69 | if (total_size == 0) | ||
70 | total_size = info->fix.smem_len; | ||
71 | |||
72 | if (p > total_size) | ||
73 | return -EFBIG; | ||
74 | |||
75 | if (count > total_size) { | ||
76 | err = -EFBIG; | ||
77 | count = total_size; | ||
78 | } | ||
79 | |||
80 | if (count + p > total_size) { | ||
81 | if (!err) | ||
82 | err = -ENOSPC; | ||
83 | |||
84 | count = total_size - p; | ||
85 | } | ||
86 | |||
87 | dst = (void __force *) (info->screen_base + p); | ||
88 | |||
89 | if (info->fbops->fb_sync) | ||
90 | info->fbops->fb_sync(info); | ||
91 | |||
92 | if (copy_from_user(dst, buf, count)) | ||
93 | err = -EFAULT; | ||
94 | |||
95 | if (!err) | ||
96 | *ppos += count; | ||
97 | |||
98 | return (err) ? err : count; | ||
99 | } | ||
100 | EXPORT_SYMBOL_GPL(fb_sys_write); | ||
101 | |||
102 | MODULE_AUTHOR("Antonino Daplas <adaplas@pol.net>"); | ||
103 | MODULE_DESCRIPTION("Generic file read (fb in system RAM)"); | ||
104 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index 28225265159..08d4e11d912 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c | |||
@@ -354,59 +354,59 @@ static void fb_rotate_logo(struct fb_info *info, u8 *dst, | |||
354 | if (rotate == FB_ROTATE_UD) { | 354 | if (rotate == FB_ROTATE_UD) { |
355 | fb_rotate_logo_ud(image->data, dst, image->width, | 355 | fb_rotate_logo_ud(image->data, dst, image->width, |
356 | image->height); | 356 | image->height); |
357 | image->dx = info->var.xres - image->width; | 357 | image->dx = info->var.xres - image->width - image->dx; |
358 | image->dy = info->var.yres - image->height; | 358 | image->dy = info->var.yres - image->height - image->dy; |
359 | } else if (rotate == FB_ROTATE_CW) { | 359 | } else if (rotate == FB_ROTATE_CW) { |
360 | fb_rotate_logo_cw(image->data, dst, image->width, | 360 | fb_rotate_logo_cw(image->data, dst, image->width, |
361 | image->height); | 361 | image->height); |
362 | tmp = image->width; | 362 | tmp = image->width; |
363 | image->width = image->height; | 363 | image->width = image->height; |
364 | image->height = tmp; | 364 | image->height = tmp; |
365 | image->dx = info->var.xres - image->width; | 365 | tmp = image->dy; |
366 | image->dy = image->dx; | ||
367 | image->dx = info->var.xres - image->width - tmp; | ||
366 | } else if (rotate == FB_ROTATE_CCW) { | 368 | } else if (rotate == FB_ROTATE_CCW) { |
367 | fb_rotate_logo_ccw(image->data, dst, image->width, | 369 | fb_rotate_logo_ccw(image->data, dst, image->width, |
368 | image->height); | 370 | image->height); |
369 | tmp = image->width; | 371 | tmp = image->width; |
370 | image->width = image->height; | 372 | image->width = image->height; |
371 | image->height = tmp; | 373 | image->height = tmp; |
372 | image->dy = info->var.yres - image->height; | 374 | tmp = image->dx; |
375 | image->dx = image->dy; | ||
376 | image->dy = info->var.yres - image->height - tmp; | ||
373 | } | 377 | } |
374 | 378 | ||
375 | image->data = dst; | 379 | image->data = dst; |
376 | } | 380 | } |
377 | 381 | ||
378 | static void fb_do_show_logo(struct fb_info *info, struct fb_image *image, | 382 | static void fb_do_show_logo(struct fb_info *info, struct fb_image *image, |
379 | int rotate) | 383 | int rotate, unsigned int num) |
380 | { | 384 | { |
381 | int x; | 385 | unsigned int x; |
382 | 386 | ||
383 | if (rotate == FB_ROTATE_UR) { | 387 | if (rotate == FB_ROTATE_UR) { |
384 | for (x = 0; x < num_online_cpus() && | 388 | for (x = 0; |
385 | x * (fb_logo.logo->width + 8) <= | 389 | x < num && image->dx + image->width <= info->var.xres; |
386 | info->var.xres - fb_logo.logo->width; x++) { | 390 | x++) { |
387 | info->fbops->fb_imageblit(info, image); | 391 | info->fbops->fb_imageblit(info, image); |
388 | image->dx += fb_logo.logo->width + 8; | 392 | image->dx += image->width + 8; |
389 | } | 393 | } |
390 | } else if (rotate == FB_ROTATE_UD) { | 394 | } else if (rotate == FB_ROTATE_UD) { |
391 | for (x = 0; x < num_online_cpus() && | 395 | for (x = 0; x < num && image->dx >= 0; x++) { |
392 | x * (fb_logo.logo->width + 8) <= | ||
393 | info->var.xres - fb_logo.logo->width; x++) { | ||
394 | info->fbops->fb_imageblit(info, image); | 396 | info->fbops->fb_imageblit(info, image); |
395 | image->dx -= fb_logo.logo->width + 8; | 397 | image->dx -= image->width + 8; |
396 | } | 398 | } |
397 | } else if (rotate == FB_ROTATE_CW) { | 399 | } else if (rotate == FB_ROTATE_CW) { |
398 | for (x = 0; x < num_online_cpus() && | 400 | for (x = 0; |
399 | x * (fb_logo.logo->width + 8) <= | 401 | x < num && image->dy + image->height <= info->var.yres; |
400 | info->var.yres - fb_logo.logo->width; x++) { | 402 | x++) { |
401 | info->fbops->fb_imageblit(info, image); | 403 | info->fbops->fb_imageblit(info, image); |
402 | image->dy += fb_logo.logo->width + 8; | 404 | image->dy += image->height + 8; |
403 | } | 405 | } |
404 | } else if (rotate == FB_ROTATE_CCW) { | 406 | } else if (rotate == FB_ROTATE_CCW) { |
405 | for (x = 0; x < num_online_cpus() && | 407 | for (x = 0; x < num && image->dy >= 0; x++) { |
406 | x * (fb_logo.logo->width + 8) <= | ||
407 | info->var.yres - fb_logo.logo->width; x++) { | ||
408 | info->fbops->fb_imageblit(info, image); | 408 | info->fbops->fb_imageblit(info, image); |
409 | image->dy -= fb_logo.logo->width + 8; | 409 | image->dy -= image->height + 8; |
410 | } | 410 | } |
411 | } | 411 | } |
412 | } | 412 | } |
@@ -418,7 +418,8 @@ int fb_prepare_logo(struct fb_info *info, int rotate) | |||
418 | 418 | ||
419 | memset(&fb_logo, 0, sizeof(struct logo_data)); | 419 | memset(&fb_logo, 0, sizeof(struct logo_data)); |
420 | 420 | ||
421 | if (info->flags & FBINFO_MISC_TILEBLITTING) | 421 | if (info->flags & FBINFO_MISC_TILEBLITTING || |
422 | info->flags & FBINFO_MODULE) | ||
422 | return 0; | 423 | return 0; |
423 | 424 | ||
424 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { | 425 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { |
@@ -483,7 +484,8 @@ int fb_show_logo(struct fb_info *info, int rotate) | |||
483 | struct fb_image image; | 484 | struct fb_image image; |
484 | 485 | ||
485 | /* Return if the frame buffer is not mapped or suspended */ | 486 | /* Return if the frame buffer is not mapped or suspended */ |
486 | if (fb_logo.logo == NULL || info->state != FBINFO_STATE_RUNNING) | 487 | if (fb_logo.logo == NULL || info->state != FBINFO_STATE_RUNNING || |
488 | info->flags & FBINFO_MODULE) | ||
487 | return 0; | 489 | return 0; |
488 | 490 | ||
489 | image.depth = 8; | 491 | image.depth = 8; |
@@ -532,7 +534,7 @@ int fb_show_logo(struct fb_info *info, int rotate) | |||
532 | fb_rotate_logo(info, logo_rotate, &image, rotate); | 534 | fb_rotate_logo(info, logo_rotate, &image, rotate); |
533 | } | 535 | } |
534 | 536 | ||
535 | fb_do_show_logo(info, &image, rotate); | 537 | fb_do_show_logo(info, &image, rotate, num_online_cpus()); |
536 | 538 | ||
537 | kfree(palette); | 539 | kfree(palette); |
538 | if (saved_pseudo_palette != NULL) | 540 | if (saved_pseudo_palette != NULL) |
@@ -586,7 +588,7 @@ fb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) | |||
586 | return -EPERM; | 588 | return -EPERM; |
587 | 589 | ||
588 | if (info->fbops->fb_read) | 590 | if (info->fbops->fb_read) |
589 | return info->fbops->fb_read(file, buf, count, ppos); | 591 | return info->fbops->fb_read(info, buf, count, ppos); |
590 | 592 | ||
591 | total_size = info->screen_size; | 593 | total_size = info->screen_size; |
592 | 594 | ||
@@ -661,7 +663,7 @@ fb_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | |||
661 | return -EPERM; | 663 | return -EPERM; |
662 | 664 | ||
663 | if (info->fbops->fb_write) | 665 | if (info->fbops->fb_write) |
664 | return info->fbops->fb_write(file, buf, count, ppos); | 666 | return info->fbops->fb_write(info, buf, count, ppos); |
665 | 667 | ||
666 | total_size = info->screen_size; | 668 | total_size = info->screen_size; |
667 | 669 | ||
@@ -771,14 +773,37 @@ fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var) | |||
771 | return 0; | 773 | return 0; |
772 | } | 774 | } |
773 | 775 | ||
776 | static int fb_check_caps(struct fb_info *info, struct fb_var_screeninfo *var, | ||
777 | u32 activate) | ||
778 | { | ||
779 | struct fb_event event; | ||
780 | struct fb_blit_caps caps, fbcaps; | ||
781 | int err = 0; | ||
782 | |||
783 | memset(&caps, 0, sizeof(caps)); | ||
784 | memset(&fbcaps, 0, sizeof(fbcaps)); | ||
785 | caps.flags = (activate & FB_ACTIVATE_ALL) ? 1 : 0; | ||
786 | event.info = info; | ||
787 | event.data = ∩︀ | ||
788 | fb_notifier_call_chain(FB_EVENT_GET_REQ, &event); | ||
789 | info->fbops->fb_get_caps(info, &fbcaps, var); | ||
790 | |||
791 | if (((fbcaps.x ^ caps.x) & caps.x) || | ||
792 | ((fbcaps.y ^ caps.y) & caps.y) || | ||
793 | (fbcaps.len < caps.len)) | ||
794 | err = -EINVAL; | ||
795 | |||
796 | return err; | ||
797 | } | ||
798 | |||
774 | int | 799 | int |
775 | fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var) | 800 | fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var) |
776 | { | 801 | { |
777 | int err, flags = info->flags; | 802 | int flags = info->flags; |
803 | int ret = 0; | ||
778 | 804 | ||
779 | if (var->activate & FB_ACTIVATE_INV_MODE) { | 805 | if (var->activate & FB_ACTIVATE_INV_MODE) { |
780 | struct fb_videomode mode1, mode2; | 806 | struct fb_videomode mode1, mode2; |
781 | int ret = 0; | ||
782 | 807 | ||
783 | fb_var_to_videomode(&mode1, var); | 808 | fb_var_to_videomode(&mode1, var); |
784 | fb_var_to_videomode(&mode2, &info->var); | 809 | fb_var_to_videomode(&mode2, &info->var); |
@@ -796,40 +821,51 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var) | |||
796 | if (!ret) | 821 | if (!ret) |
797 | fb_delete_videomode(&mode1, &info->modelist); | 822 | fb_delete_videomode(&mode1, &info->modelist); |
798 | 823 | ||
799 | return ret; | 824 | |
825 | ret = (ret) ? -EINVAL : 0; | ||
826 | goto done; | ||
800 | } | 827 | } |
801 | 828 | ||
802 | if ((var->activate & FB_ACTIVATE_FORCE) || | 829 | if ((var->activate & FB_ACTIVATE_FORCE) || |
803 | memcmp(&info->var, var, sizeof(struct fb_var_screeninfo))) { | 830 | memcmp(&info->var, var, sizeof(struct fb_var_screeninfo))) { |
831 | u32 activate = var->activate; | ||
832 | |||
804 | if (!info->fbops->fb_check_var) { | 833 | if (!info->fbops->fb_check_var) { |
805 | *var = info->var; | 834 | *var = info->var; |
806 | return 0; | 835 | goto done; |
807 | } | 836 | } |
808 | 837 | ||
809 | if ((err = info->fbops->fb_check_var(var, info))) | 838 | ret = info->fbops->fb_check_var(var, info); |
810 | return err; | 839 | |
840 | if (ret) | ||
841 | goto done; | ||
811 | 842 | ||
812 | if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) { | 843 | if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) { |
813 | struct fb_videomode mode; | 844 | struct fb_videomode mode; |
814 | int err = 0; | 845 | |
846 | if (info->fbops->fb_get_caps) { | ||
847 | ret = fb_check_caps(info, var, activate); | ||
848 | |||
849 | if (ret) | ||
850 | goto done; | ||
851 | } | ||
815 | 852 | ||
816 | info->var = *var; | 853 | info->var = *var; |
854 | |||
817 | if (info->fbops->fb_set_par) | 855 | if (info->fbops->fb_set_par) |
818 | info->fbops->fb_set_par(info); | 856 | info->fbops->fb_set_par(info); |
819 | 857 | ||
820 | fb_pan_display(info, &info->var); | 858 | fb_pan_display(info, &info->var); |
821 | |||
822 | fb_set_cmap(&info->cmap, info); | 859 | fb_set_cmap(&info->cmap, info); |
823 | |||
824 | fb_var_to_videomode(&mode, &info->var); | 860 | fb_var_to_videomode(&mode, &info->var); |
825 | 861 | ||
826 | if (info->modelist.prev && info->modelist.next && | 862 | if (info->modelist.prev && info->modelist.next && |
827 | !list_empty(&info->modelist)) | 863 | !list_empty(&info->modelist)) |
828 | err = fb_add_videomode(&mode, &info->modelist); | 864 | ret = fb_add_videomode(&mode, &info->modelist); |
829 | 865 | ||
830 | if (!err && (flags & FBINFO_MISC_USEREVENT)) { | 866 | if (!ret && (flags & FBINFO_MISC_USEREVENT)) { |
831 | struct fb_event event; | 867 | struct fb_event event; |
832 | int evnt = (var->activate & FB_ACTIVATE_ALL) ? | 868 | int evnt = (activate & FB_ACTIVATE_ALL) ? |
833 | FB_EVENT_MODE_CHANGE_ALL : | 869 | FB_EVENT_MODE_CHANGE_ALL : |
834 | FB_EVENT_MODE_CHANGE; | 870 | FB_EVENT_MODE_CHANGE; |
835 | 871 | ||
@@ -839,7 +875,9 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var) | |||
839 | } | 875 | } |
840 | } | 876 | } |
841 | } | 877 | } |
842 | return 0; | 878 | |
879 | done: | ||
880 | return ret; | ||
843 | } | 881 | } |
844 | 882 | ||
845 | int | 883 | int |
@@ -1266,6 +1304,9 @@ static const struct file_operations fb_fops = { | |||
1266 | #ifdef HAVE_ARCH_FB_UNMAPPED_AREA | 1304 | #ifdef HAVE_ARCH_FB_UNMAPPED_AREA |
1267 | .get_unmapped_area = get_fb_unmapped_area, | 1305 | .get_unmapped_area = get_fb_unmapped_area, |
1268 | #endif | 1306 | #endif |
1307 | #ifdef CONFIG_FB_DEFERRED_IO | ||
1308 | .fsync = fb_deferred_io_fsync, | ||
1309 | #endif | ||
1269 | }; | 1310 | }; |
1270 | 1311 | ||
1271 | struct class *fb_class; | 1312 | struct class *fb_class; |
@@ -1316,6 +1357,12 @@ register_framebuffer(struct fb_info *fb_info) | |||
1316 | } | 1357 | } |
1317 | fb_info->pixmap.offset = 0; | 1358 | fb_info->pixmap.offset = 0; |
1318 | 1359 | ||
1360 | if (!fb_info->pixmap.blit_x) | ||
1361 | fb_info->pixmap.blit_x = ~(u32)0; | ||
1362 | |||
1363 | if (!fb_info->pixmap.blit_y) | ||
1364 | fb_info->pixmap.blit_y = ~(u32)0; | ||
1365 | |||
1319 | if (!fb_info->modelist.prev || !fb_info->modelist.next) | 1366 | if (!fb_info->modelist.prev || !fb_info->modelist.next) |
1320 | INIT_LIST_HEAD(&fb_info->modelist); | 1367 | INIT_LIST_HEAD(&fb_info->modelist); |
1321 | 1368 | ||
diff --git a/drivers/video/fbmon.c b/drivers/video/fbmon.c index 6b385c39b8b..438b9411905 100644 --- a/drivers/video/fbmon.c +++ b/drivers/video/fbmon.c | |||
@@ -48,8 +48,9 @@ | |||
48 | #define DPRINTK(fmt, args...) | 48 | #define DPRINTK(fmt, args...) |
49 | #endif | 49 | #endif |
50 | 50 | ||
51 | #define FBMON_FIX_HEADER 1 | 51 | #define FBMON_FIX_HEADER 1 |
52 | #define FBMON_FIX_INPUT 2 | 52 | #define FBMON_FIX_INPUT 2 |
53 | #define FBMON_FIX_TIMINGS 3 | ||
53 | 54 | ||
54 | #ifdef CONFIG_FB_MODE_HELPERS | 55 | #ifdef CONFIG_FB_MODE_HELPERS |
55 | struct broken_edid { | 56 | struct broken_edid { |
@@ -71,6 +72,12 @@ static const struct broken_edid brokendb[] = { | |||
71 | .model = 0x5a44, | 72 | .model = 0x5a44, |
72 | .fix = FBMON_FIX_INPUT, | 73 | .fix = FBMON_FIX_INPUT, |
73 | }, | 74 | }, |
75 | /* Sharp UXGA? */ | ||
76 | { | ||
77 | .manufacturer = "SHP", | ||
78 | .model = 0x138e, | ||
79 | .fix = FBMON_FIX_TIMINGS, | ||
80 | }, | ||
74 | }; | 81 | }; |
75 | 82 | ||
76 | static const unsigned char edid_v1_header[] = { 0x00, 0xff, 0xff, 0xff, | 83 | static const unsigned char edid_v1_header[] = { 0x00, 0xff, 0xff, 0xff, |
@@ -87,6 +94,55 @@ static void copy_string(unsigned char *c, unsigned char *s) | |||
87 | while (i-- && (*--s == 0x20)) *s = 0; | 94 | while (i-- && (*--s == 0x20)) *s = 0; |
88 | } | 95 | } |
89 | 96 | ||
97 | static int edid_is_serial_block(unsigned char *block) | ||
98 | { | ||
99 | if ((block[0] == 0x00) && (block[1] == 0x00) && | ||
100 | (block[2] == 0x00) && (block[3] == 0xff) && | ||
101 | (block[4] == 0x00)) | ||
102 | return 1; | ||
103 | else | ||
104 | return 0; | ||
105 | } | ||
106 | |||
107 | static int edid_is_ascii_block(unsigned char *block) | ||
108 | { | ||
109 | if ((block[0] == 0x00) && (block[1] == 0x00) && | ||
110 | (block[2] == 0x00) && (block[3] == 0xfe) && | ||
111 | (block[4] == 0x00)) | ||
112 | return 1; | ||
113 | else | ||
114 | return 0; | ||
115 | } | ||
116 | |||
117 | static int edid_is_limits_block(unsigned char *block) | ||
118 | { | ||
119 | if ((block[0] == 0x00) && (block[1] == 0x00) && | ||
120 | (block[2] == 0x00) && (block[3] == 0xfd) && | ||
121 | (block[4] == 0x00)) | ||
122 | return 1; | ||
123 | else | ||
124 | return 0; | ||
125 | } | ||
126 | |||
127 | static int edid_is_monitor_block(unsigned char *block) | ||
128 | { | ||
129 | if ((block[0] == 0x00) && (block[1] == 0x00) && | ||
130 | (block[2] == 0x00) && (block[3] == 0xfc) && | ||
131 | (block[4] == 0x00)) | ||
132 | return 1; | ||
133 | else | ||
134 | return 0; | ||
135 | } | ||
136 | |||
137 | static int edid_is_timing_block(unsigned char *block) | ||
138 | { | ||
139 | if ((block[0] != 0x00) || (block[1] != 0x00) || | ||
140 | (block[2] != 0x00) || (block[4] != 0x00)) | ||
141 | return 1; | ||
142 | else | ||
143 | return 0; | ||
144 | } | ||
145 | |||
90 | static int check_edid(unsigned char *edid) | 146 | static int check_edid(unsigned char *edid) |
91 | { | 147 | { |
92 | unsigned char *block = edid + ID_MANUFACTURER_NAME, manufacturer[4]; | 148 | unsigned char *block = edid + ID_MANUFACTURER_NAME, manufacturer[4]; |
@@ -104,9 +160,6 @@ static int check_edid(unsigned char *edid) | |||
104 | for (i = 0; i < ARRAY_SIZE(brokendb); i++) { | 160 | for (i = 0; i < ARRAY_SIZE(brokendb); i++) { |
105 | if (!strncmp(manufacturer, brokendb[i].manufacturer, 4) && | 161 | if (!strncmp(manufacturer, brokendb[i].manufacturer, 4) && |
106 | brokendb[i].model == model) { | 162 | brokendb[i].model == model) { |
107 | printk("fbmon: The EDID Block of " | ||
108 | "Manufacturer: %s Model: 0x%x is known to " | ||
109 | "be broken,\n", manufacturer, model); | ||
110 | fix = brokendb[i].fix; | 163 | fix = brokendb[i].fix; |
111 | break; | 164 | break; |
112 | } | 165 | } |
@@ -115,8 +168,10 @@ static int check_edid(unsigned char *edid) | |||
115 | switch (fix) { | 168 | switch (fix) { |
116 | case FBMON_FIX_HEADER: | 169 | case FBMON_FIX_HEADER: |
117 | for (i = 0; i < 8; i++) { | 170 | for (i = 0; i < 8; i++) { |
118 | if (edid[i] != edid_v1_header[i]) | 171 | if (edid[i] != edid_v1_header[i]) { |
119 | ret = fix; | 172 | ret = fix; |
173 | break; | ||
174 | } | ||
120 | } | 175 | } |
121 | break; | 176 | break; |
122 | case FBMON_FIX_INPUT: | 177 | case FBMON_FIX_INPUT: |
@@ -126,14 +181,34 @@ static int check_edid(unsigned char *edid) | |||
126 | if (b[4] & 0x01 && b[0] & 0x80) | 181 | if (b[4] & 0x01 && b[0] & 0x80) |
127 | ret = fix; | 182 | ret = fix; |
128 | break; | 183 | break; |
184 | case FBMON_FIX_TIMINGS: | ||
185 | b = edid + DETAILED_TIMING_DESCRIPTIONS_START; | ||
186 | ret = fix; | ||
187 | |||
188 | for (i = 0; i < 4; i++) { | ||
189 | if (edid_is_limits_block(b)) { | ||
190 | ret = 0; | ||
191 | break; | ||
192 | } | ||
193 | |||
194 | b += DETAILED_TIMING_DESCRIPTION_SIZE; | ||
195 | } | ||
196 | |||
197 | break; | ||
129 | } | 198 | } |
130 | 199 | ||
200 | if (ret) | ||
201 | printk("fbmon: The EDID Block of " | ||
202 | "Manufacturer: %s Model: 0x%x is known to " | ||
203 | "be broken,\n", manufacturer, model); | ||
204 | |||
131 | return ret; | 205 | return ret; |
132 | } | 206 | } |
133 | 207 | ||
134 | static void fix_edid(unsigned char *edid, int fix) | 208 | static void fix_edid(unsigned char *edid, int fix) |
135 | { | 209 | { |
136 | unsigned char *b; | 210 | int i; |
211 | unsigned char *b, csum = 0; | ||
137 | 212 | ||
138 | switch (fix) { | 213 | switch (fix) { |
139 | case FBMON_FIX_HEADER: | 214 | case FBMON_FIX_HEADER: |
@@ -145,6 +220,37 @@ static void fix_edid(unsigned char *edid, int fix) | |||
145 | b = edid + EDID_STRUCT_DISPLAY; | 220 | b = edid + EDID_STRUCT_DISPLAY; |
146 | b[0] &= ~0x80; | 221 | b[0] &= ~0x80; |
147 | edid[127] += 0x80; | 222 | edid[127] += 0x80; |
223 | break; | ||
224 | case FBMON_FIX_TIMINGS: | ||
225 | printk("fbmon: trying to fix monitor timings\n"); | ||
226 | b = edid + DETAILED_TIMING_DESCRIPTIONS_START; | ||
227 | for (i = 0; i < 4; i++) { | ||
228 | if (!(edid_is_serial_block(b) || | ||
229 | edid_is_ascii_block(b) || | ||
230 | edid_is_monitor_block(b) || | ||
231 | edid_is_timing_block(b))) { | ||
232 | b[0] = 0x00; | ||
233 | b[1] = 0x00; | ||
234 | b[2] = 0x00; | ||
235 | b[3] = 0xfd; | ||
236 | b[4] = 0x00; | ||
237 | b[5] = 60; /* vfmin */ | ||
238 | b[6] = 60; /* vfmax */ | ||
239 | b[7] = 30; /* hfmin */ | ||
240 | b[8] = 75; /* hfmax */ | ||
241 | b[9] = 17; /* pixclock - 170 MHz*/ | ||
242 | b[10] = 0; /* GTF */ | ||
243 | break; | ||
244 | } | ||
245 | |||
246 | b += DETAILED_TIMING_DESCRIPTION_SIZE; | ||
247 | } | ||
248 | |||
249 | for (i = 0; i < EDID_LENGTH - 1; i++) | ||
250 | csum += edid[i]; | ||
251 | |||
252 | edid[127] = 256 - csum; | ||
253 | break; | ||
148 | } | 254 | } |
149 | } | 255 | } |
150 | 256 | ||
@@ -273,46 +379,6 @@ static void get_chroma(unsigned char *block, struct fb_monspecs *specs) | |||
273 | DPRINTK("WhiteY: 0.%03d\n", specs->chroma.whitey); | 379 | DPRINTK("WhiteY: 0.%03d\n", specs->chroma.whitey); |
274 | } | 380 | } |
275 | 381 | ||
276 | static int edid_is_serial_block(unsigned char *block) | ||
277 | { | ||
278 | if ((block[0] == 0x00) && (block[1] == 0x00) && | ||
279 | (block[2] == 0x00) && (block[3] == 0xff) && | ||
280 | (block[4] == 0x00)) | ||
281 | return 1; | ||
282 | else | ||
283 | return 0; | ||
284 | } | ||
285 | |||
286 | static int edid_is_ascii_block(unsigned char *block) | ||
287 | { | ||
288 | if ((block[0] == 0x00) && (block[1] == 0x00) && | ||
289 | (block[2] == 0x00) && (block[3] == 0xfe) && | ||
290 | (block[4] == 0x00)) | ||
291 | return 1; | ||
292 | else | ||
293 | return 0; | ||
294 | } | ||
295 | |||
296 | static int edid_is_limits_block(unsigned char *block) | ||
297 | { | ||
298 | if ((block[0] == 0x00) && (block[1] == 0x00) && | ||
299 | (block[2] == 0x00) && (block[3] == 0xfd) && | ||
300 | (block[4] == 0x00)) | ||
301 | return 1; | ||
302 | else | ||
303 | return 0; | ||
304 | } | ||
305 | |||
306 | static int edid_is_monitor_block(unsigned char *block) | ||
307 | { | ||
308 | if ((block[0] == 0x00) && (block[1] == 0x00) && | ||
309 | (block[2] == 0x00) && (block[3] == 0xfc) && | ||
310 | (block[4] == 0x00)) | ||
311 | return 1; | ||
312 | else | ||
313 | return 0; | ||
314 | } | ||
315 | |||
316 | static void calc_mode_timings(int xres, int yres, int refresh, | 382 | static void calc_mode_timings(int xres, int yres, int refresh, |
317 | struct fb_videomode *mode) | 383 | struct fb_videomode *mode) |
318 | { | 384 | { |
@@ -795,15 +861,6 @@ static void get_monspecs(unsigned char *edid, struct fb_monspecs *specs) | |||
795 | } | 861 | } |
796 | } | 862 | } |
797 | 863 | ||
798 | static int edid_is_timing_block(unsigned char *block) | ||
799 | { | ||
800 | if ((block[0] != 0x00) || (block[1] != 0x00) || | ||
801 | (block[2] != 0x00) || (block[4] != 0x00)) | ||
802 | return 1; | ||
803 | else | ||
804 | return 0; | ||
805 | } | ||
806 | |||
807 | int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var) | 864 | int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var) |
808 | { | 865 | { |
809 | int i; | 866 | int i; |
diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c index 40c80c8190e..d4a2c11d980 100644 --- a/drivers/video/fbsysfs.c +++ b/drivers/video/fbsysfs.c | |||
@@ -376,7 +376,7 @@ static ssize_t show_pan(struct device *device, | |||
376 | { | 376 | { |
377 | struct fb_info *fb_info = dev_get_drvdata(device); | 377 | struct fb_info *fb_info = dev_get_drvdata(device); |
378 | return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xoffset, | 378 | return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xoffset, |
379 | fb_info->var.xoffset); | 379 | fb_info->var.yoffset); |
380 | } | 380 | } |
381 | 381 | ||
382 | static ssize_t show_name(struct device *device, | 382 | static ssize_t show_name(struct device *device, |
diff --git a/drivers/video/hecubafb.c b/drivers/video/hecubafb.c new file mode 100644 index 00000000000..abfcb50364c --- /dev/null +++ b/drivers/video/hecubafb.c | |||
@@ -0,0 +1,471 @@ | |||
1 | /* | ||
2 | * linux/drivers/video/hecubafb.c -- FB driver for Hecuba controller | ||
3 | * | ||
4 | * Copyright (C) 2006, Jaya Kumar | ||
5 | * This work was sponsored by CIS(M) Sdn Bhd | ||
6 | * | ||
7 | * This file is subject to the terms and conditions of the GNU General Public | ||
8 | * License. See the file COPYING in the main directory of this archive for | ||
9 | * more details. | ||
10 | * | ||
11 | * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven. | ||
12 | * This work was possible because of apollo display code from E-Ink's website | ||
13 | * http://support.eink.com/community | ||
14 | * All information used to write this code is from public material made | ||
15 | * available by E-Ink on its support site. Some commands such as 0xA4 | ||
16 | * were found by looping through cmd=0x00 thru 0xFF and supplying random | ||
17 | * values. There are other commands that the display is capable of, | ||
18 | * beyond the 5 used here but they are more complex. | ||
19 | * | ||
20 | * This driver is written to be used with the Hecuba display controller | ||
21 | * board, and tested with the EInk 800x600 display in 1 bit mode. | ||
22 | * The interface between Hecuba and the host is TTL based GPIO. The | ||
23 | * GPIO requirements are 8 writable data lines and 6 lines for control. | ||
24 | * Only 4 of the controls are actually used here but 6 for future use. | ||
25 | * The driver requires the IO addresses for data and control GPIO at | ||
26 | * load time. It is also possible to use this display with a standard | ||
27 | * PC parallel port. | ||
28 | * | ||
29 | * General notes: | ||
30 | * - User must set hecubafb_enable=1 to enable it | ||
31 | * - User must set dio_addr=0xIOADDR cio_addr=0xIOADDR c2io_addr=0xIOADDR | ||
32 | * | ||
33 | */ | ||
34 | |||
35 | #include <linux/module.h> | ||
36 | #include <linux/kernel.h> | ||
37 | #include <linux/errno.h> | ||
38 | #include <linux/string.h> | ||
39 | #include <linux/mm.h> | ||
40 | #include <linux/slab.h> | ||
41 | #include <linux/vmalloc.h> | ||
42 | #include <linux/delay.h> | ||
43 | #include <linux/interrupt.h> | ||
44 | #include <linux/fb.h> | ||
45 | #include <linux/init.h> | ||
46 | #include <linux/platform_device.h> | ||
47 | #include <linux/list.h> | ||
48 | #include <asm/uaccess.h> | ||
49 | |||
50 | /* Apollo controller specific defines */ | ||
51 | #define APOLLO_START_NEW_IMG 0xA0 | ||
52 | #define APOLLO_STOP_IMG_DATA 0xA1 | ||
53 | #define APOLLO_DISPLAY_IMG 0xA2 | ||
54 | #define APOLLO_ERASE_DISPLAY 0xA3 | ||
55 | #define APOLLO_INIT_DISPLAY 0xA4 | ||
56 | |||
57 | /* Hecuba interface specific defines */ | ||
58 | /* WUP is inverted, CD is inverted, DS is inverted */ | ||
59 | #define HCB_NWUP_BIT 0x01 | ||
60 | #define HCB_NDS_BIT 0x02 | ||
61 | #define HCB_RW_BIT 0x04 | ||
62 | #define HCB_NCD_BIT 0x08 | ||
63 | #define HCB_ACK_BIT 0x80 | ||
64 | |||
65 | /* Display specific information */ | ||
66 | #define DPY_W 600 | ||
67 | #define DPY_H 800 | ||
68 | |||
69 | struct hecubafb_par { | ||
70 | unsigned long dio_addr; | ||
71 | unsigned long cio_addr; | ||
72 | unsigned long c2io_addr; | ||
73 | unsigned char ctl; | ||
74 | struct fb_info *info; | ||
75 | unsigned int irq; | ||
76 | }; | ||
77 | |||
78 | static struct fb_fix_screeninfo hecubafb_fix __devinitdata = { | ||
79 | .id = "hecubafb", | ||
80 | .type = FB_TYPE_PACKED_PIXELS, | ||
81 | .visual = FB_VISUAL_MONO01, | ||
82 | .xpanstep = 0, | ||
83 | .ypanstep = 0, | ||
84 | .ywrapstep = 0, | ||
85 | .accel = FB_ACCEL_NONE, | ||
86 | }; | ||
87 | |||
88 | static struct fb_var_screeninfo hecubafb_var __devinitdata = { | ||
89 | .xres = DPY_W, | ||
90 | .yres = DPY_H, | ||
91 | .xres_virtual = DPY_W, | ||
92 | .yres_virtual = DPY_H, | ||
93 | .bits_per_pixel = 1, | ||
94 | .nonstd = 1, | ||
95 | }; | ||
96 | |||
97 | static unsigned long dio_addr; | ||
98 | static unsigned long cio_addr; | ||
99 | static unsigned long c2io_addr; | ||
100 | static unsigned long splashval; | ||
101 | static unsigned int nosplash; | ||
102 | static unsigned int hecubafb_enable; | ||
103 | static unsigned int irq; | ||
104 | |||
105 | static DECLARE_WAIT_QUEUE_HEAD(hecubafb_waitq); | ||
106 | |||
107 | static void hcb_set_ctl(struct hecubafb_par *par) | ||
108 | { | ||
109 | outb(par->ctl, par->cio_addr); | ||
110 | } | ||
111 | |||
112 | static unsigned char hcb_get_ctl(struct hecubafb_par *par) | ||
113 | { | ||
114 | return inb(par->c2io_addr); | ||
115 | } | ||
116 | |||
117 | static void hcb_set_data(struct hecubafb_par *par, unsigned char value) | ||
118 | { | ||
119 | outb(value, par->dio_addr); | ||
120 | } | ||
121 | |||
122 | static int __devinit apollo_init_control(struct hecubafb_par *par) | ||
123 | { | ||
124 | unsigned char ctl; | ||
125 | /* for init, we want the following setup to be set: | ||
126 | WUP = lo | ||
127 | ACK = hi | ||
128 | DS = hi | ||
129 | RW = hi | ||
130 | CD = lo | ||
131 | */ | ||
132 | |||
133 | /* write WUP to lo, DS to hi, RW to hi, CD to lo */ | ||
134 | par->ctl = HCB_NWUP_BIT | HCB_RW_BIT | HCB_NCD_BIT ; | ||
135 | par->ctl &= ~HCB_NDS_BIT; | ||
136 | hcb_set_ctl(par); | ||
137 | |||
138 | /* check ACK is not lo */ | ||
139 | ctl = hcb_get_ctl(par); | ||
140 | if ((ctl & HCB_ACK_BIT)) { | ||
141 | printk(KERN_ERR "Fail because ACK is already low\n"); | ||
142 | return -ENXIO; | ||
143 | } | ||
144 | |||
145 | return 0; | ||
146 | } | ||
147 | |||
148 | static void hcb_wait_for_ack(struct hecubafb_par *par) | ||
149 | { | ||
150 | |||
151 | int timeout; | ||
152 | unsigned char ctl; | ||
153 | |||
154 | timeout=500; | ||
155 | do { | ||
156 | ctl = hcb_get_ctl(par); | ||
157 | if ((ctl & HCB_ACK_BIT)) | ||
158 | return; | ||
159 | udelay(1); | ||
160 | } while (timeout--); | ||
161 | printk(KERN_ERR "timed out waiting for ack\n"); | ||
162 | } | ||
163 | |||
164 | static void hcb_wait_for_ack_clear(struct hecubafb_par *par) | ||
165 | { | ||
166 | |||
167 | int timeout; | ||
168 | unsigned char ctl; | ||
169 | |||
170 | timeout=500; | ||
171 | do { | ||
172 | ctl = hcb_get_ctl(par); | ||
173 | if (!(ctl & HCB_ACK_BIT)) | ||
174 | return; | ||
175 | udelay(1); | ||
176 | } while (timeout--); | ||
177 | printk(KERN_ERR "timed out waiting for clear\n"); | ||
178 | } | ||
179 | |||
180 | static void apollo_send_data(struct hecubafb_par *par, unsigned char data) | ||
181 | { | ||
182 | /* set data */ | ||
183 | hcb_set_data(par, data); | ||
184 | |||
185 | /* set DS low */ | ||
186 | par->ctl |= HCB_NDS_BIT; | ||
187 | hcb_set_ctl(par); | ||
188 | |||
189 | hcb_wait_for_ack(par); | ||
190 | |||
191 | /* set DS hi */ | ||
192 | par->ctl &= ~(HCB_NDS_BIT); | ||
193 | hcb_set_ctl(par); | ||
194 | |||
195 | hcb_wait_for_ack_clear(par); | ||
196 | } | ||
197 | |||
198 | static void apollo_send_command(struct hecubafb_par *par, unsigned char data) | ||
199 | { | ||
200 | /* command so set CD to high */ | ||
201 | par->ctl &= ~(HCB_NCD_BIT); | ||
202 | hcb_set_ctl(par); | ||
203 | |||
204 | /* actually strobe with command */ | ||
205 | apollo_send_data(par, data); | ||
206 | |||
207 | /* clear CD back to low */ | ||
208 | par->ctl |= (HCB_NCD_BIT); | ||
209 | hcb_set_ctl(par); | ||
210 | } | ||
211 | |||
212 | /* main hecubafb functions */ | ||
213 | |||
214 | static void hecubafb_dpy_update(struct hecubafb_par *par) | ||
215 | { | ||
216 | int i; | ||
217 | unsigned char *buf = (unsigned char __force *)par->info->screen_base; | ||
218 | |||
219 | apollo_send_command(par, 0xA0); | ||
220 | |||
221 | for (i=0; i < (DPY_W*DPY_H/8); i++) { | ||
222 | apollo_send_data(par, *(buf++)); | ||
223 | } | ||
224 | |||
225 | apollo_send_command(par, 0xA1); | ||
226 | apollo_send_command(par, 0xA2); | ||
227 | } | ||
228 | |||
229 | /* this is called back from the deferred io workqueue */ | ||
230 | static void hecubafb_dpy_deferred_io(struct fb_info *info, | ||
231 | struct list_head *pagelist) | ||
232 | { | ||
233 | hecubafb_dpy_update(info->par); | ||
234 | } | ||
235 | |||
236 | static void hecubafb_fillrect(struct fb_info *info, | ||
237 | const struct fb_fillrect *rect) | ||
238 | { | ||
239 | struct hecubafb_par *par = info->par; | ||
240 | |||
241 | sys_fillrect(info, rect); | ||
242 | |||
243 | hecubafb_dpy_update(par); | ||
244 | } | ||
245 | |||
246 | static void hecubafb_copyarea(struct fb_info *info, | ||
247 | const struct fb_copyarea *area) | ||
248 | { | ||
249 | struct hecubafb_par *par = info->par; | ||
250 | |||
251 | sys_copyarea(info, area); | ||
252 | |||
253 | hecubafb_dpy_update(par); | ||
254 | } | ||
255 | |||
256 | static void hecubafb_imageblit(struct fb_info *info, | ||
257 | const struct fb_image *image) | ||
258 | { | ||
259 | struct hecubafb_par *par = info->par; | ||
260 | |||
261 | sys_imageblit(info, image); | ||
262 | |||
263 | hecubafb_dpy_update(par); | ||
264 | } | ||
265 | |||
266 | /* | ||
267 | * this is the slow path from userspace. they can seek and write to | ||
268 | * the fb. it's inefficient to do anything less than a full screen draw | ||
269 | */ | ||
270 | static ssize_t hecubafb_write(struct fb_info *info, const char __user *buf, | ||
271 | size_t count, loff_t *ppos) | ||
272 | { | ||
273 | unsigned long p; | ||
274 | int err=-EINVAL; | ||
275 | struct hecubafb_par *par; | ||
276 | unsigned int xres; | ||
277 | unsigned int fbmemlength; | ||
278 | |||
279 | p = *ppos; | ||
280 | par = info->par; | ||
281 | xres = info->var.xres; | ||
282 | fbmemlength = (xres * info->var.yres)/8; | ||
283 | |||
284 | if (p > fbmemlength) | ||
285 | return -ENOSPC; | ||
286 | |||
287 | err = 0; | ||
288 | if ((count + p) > fbmemlength) { | ||
289 | count = fbmemlength - p; | ||
290 | err = -ENOSPC; | ||
291 | } | ||
292 | |||
293 | if (count) { | ||
294 | char *base_addr; | ||
295 | |||
296 | base_addr = (char __force *)info->screen_base; | ||
297 | count -= copy_from_user(base_addr + p, buf, count); | ||
298 | *ppos += count; | ||
299 | err = -EFAULT; | ||
300 | } | ||
301 | |||
302 | hecubafb_dpy_update(par); | ||
303 | |||
304 | if (count) | ||
305 | return count; | ||
306 | |||
307 | return err; | ||
308 | } | ||
309 | |||
310 | static struct fb_ops hecubafb_ops = { | ||
311 | .owner = THIS_MODULE, | ||
312 | .fb_read = fb_sys_read, | ||
313 | .fb_write = hecubafb_write, | ||
314 | .fb_fillrect = hecubafb_fillrect, | ||
315 | .fb_copyarea = hecubafb_copyarea, | ||
316 | .fb_imageblit = hecubafb_imageblit, | ||
317 | }; | ||
318 | |||
319 | static struct fb_deferred_io hecubafb_defio = { | ||
320 | .delay = HZ, | ||
321 | .deferred_io = hecubafb_dpy_deferred_io, | ||
322 | }; | ||
323 | |||
324 | static int __devinit hecubafb_probe(struct platform_device *dev) | ||
325 | { | ||
326 | struct fb_info *info; | ||
327 | int retval = -ENOMEM; | ||
328 | int videomemorysize; | ||
329 | unsigned char *videomemory; | ||
330 | struct hecubafb_par *par; | ||
331 | |||
332 | videomemorysize = (DPY_W*DPY_H)/8; | ||
333 | |||
334 | if (!(videomemory = vmalloc(videomemorysize))) | ||
335 | return retval; | ||
336 | |||
337 | memset(videomemory, 0, videomemorysize); | ||
338 | |||
339 | info = framebuffer_alloc(sizeof(struct hecubafb_par), &dev->dev); | ||
340 | if (!info) | ||
341 | goto err; | ||
342 | |||
343 | info->screen_base = (char __iomem *) videomemory; | ||
344 | info->fbops = &hecubafb_ops; | ||
345 | |||
346 | info->var = hecubafb_var; | ||
347 | info->fix = hecubafb_fix; | ||
348 | info->fix.smem_len = videomemorysize; | ||
349 | par = info->par; | ||
350 | par->info = info; | ||
351 | |||
352 | if (!dio_addr || !cio_addr || !c2io_addr) { | ||
353 | printk(KERN_WARNING "no IO addresses supplied\n"); | ||
354 | goto err1; | ||
355 | } | ||
356 | par->dio_addr = dio_addr; | ||
357 | par->cio_addr = cio_addr; | ||
358 | par->c2io_addr = c2io_addr; | ||
359 | info->flags = FBINFO_FLAG_DEFAULT; | ||
360 | |||
361 | info->fbdefio = &hecubafb_defio; | ||
362 | fb_deferred_io_init(info); | ||
363 | |||
364 | retval = register_framebuffer(info); | ||
365 | if (retval < 0) | ||
366 | goto err1; | ||
367 | platform_set_drvdata(dev, info); | ||
368 | |||
369 | printk(KERN_INFO | ||
370 | "fb%d: Hecuba frame buffer device, using %dK of video memory\n", | ||
371 | info->node, videomemorysize >> 10); | ||
372 | |||
373 | /* this inits the dpy */ | ||
374 | apollo_init_control(par); | ||
375 | |||
376 | apollo_send_command(par, APOLLO_INIT_DISPLAY); | ||
377 | apollo_send_data(par, 0x81); | ||
378 | |||
379 | /* have to wait while display resets */ | ||
380 | udelay(1000); | ||
381 | |||
382 | /* if we were told to splash the screen, we just clear it */ | ||
383 | if (!nosplash) { | ||
384 | apollo_send_command(par, APOLLO_ERASE_DISPLAY); | ||
385 | apollo_send_data(par, splashval); | ||
386 | } | ||
387 | |||
388 | return 0; | ||
389 | err1: | ||
390 | framebuffer_release(info); | ||
391 | err: | ||
392 | vfree(videomemory); | ||
393 | return retval; | ||
394 | } | ||
395 | |||
396 | static int __devexit hecubafb_remove(struct platform_device *dev) | ||
397 | { | ||
398 | struct fb_info *info = platform_get_drvdata(dev); | ||
399 | |||
400 | if (info) { | ||
401 | fb_deferred_io_cleanup(info); | ||
402 | unregister_framebuffer(info); | ||
403 | vfree((void __force *)info->screen_base); | ||
404 | framebuffer_release(info); | ||
405 | } | ||
406 | return 0; | ||
407 | } | ||
408 | |||
409 | static struct platform_driver hecubafb_driver = { | ||
410 | .probe = hecubafb_probe, | ||
411 | .remove = hecubafb_remove, | ||
412 | .driver = { | ||
413 | .name = "hecubafb", | ||
414 | }, | ||
415 | }; | ||
416 | |||
417 | static struct platform_device *hecubafb_device; | ||
418 | |||
419 | static int __init hecubafb_init(void) | ||
420 | { | ||
421 | int ret; | ||
422 | |||
423 | if (!hecubafb_enable) { | ||
424 | printk(KERN_ERR "Use hecubafb_enable to enable the device\n"); | ||
425 | return -ENXIO; | ||
426 | } | ||
427 | |||
428 | ret = platform_driver_register(&hecubafb_driver); | ||
429 | if (!ret) { | ||
430 | hecubafb_device = platform_device_alloc("hecubafb", 0); | ||
431 | if (hecubafb_device) | ||
432 | ret = platform_device_add(hecubafb_device); | ||
433 | else | ||
434 | ret = -ENOMEM; | ||
435 | |||
436 | if (ret) { | ||
437 | platform_device_put(hecubafb_device); | ||
438 | platform_driver_unregister(&hecubafb_driver); | ||
439 | } | ||
440 | } | ||
441 | return ret; | ||
442 | |||
443 | } | ||
444 | |||
445 | static void __exit hecubafb_exit(void) | ||
446 | { | ||
447 | platform_device_unregister(hecubafb_device); | ||
448 | platform_driver_unregister(&hecubafb_driver); | ||
449 | } | ||
450 | |||
451 | module_param(nosplash, uint, 0); | ||
452 | MODULE_PARM_DESC(nosplash, "Disable doing the splash screen"); | ||
453 | module_param(hecubafb_enable, uint, 0); | ||
454 | MODULE_PARM_DESC(hecubafb_enable, "Enable communication with Hecuba board"); | ||
455 | module_param(dio_addr, ulong, 0); | ||
456 | MODULE_PARM_DESC(dio_addr, "IO address for data, eg: 0x480"); | ||
457 | module_param(cio_addr, ulong, 0); | ||
458 | MODULE_PARM_DESC(cio_addr, "IO address for control, eg: 0x400"); | ||
459 | module_param(c2io_addr, ulong, 0); | ||
460 | MODULE_PARM_DESC(c2io_addr, "IO address for secondary control, eg: 0x408"); | ||
461 | module_param(splashval, ulong, 0); | ||
462 | MODULE_PARM_DESC(splashval, "Splash pattern: 0x00 is black, 0x01 is white"); | ||
463 | module_param(irq, uint, 0); | ||
464 | MODULE_PARM_DESC(irq, "IRQ for the Hecuba board"); | ||
465 | |||
466 | module_init(hecubafb_init); | ||
467 | module_exit(hecubafb_exit); | ||
468 | |||
469 | MODULE_DESCRIPTION("fbdev driver for Hecuba board"); | ||
470 | MODULE_AUTHOR("Jaya Kumar"); | ||
471 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/i810/i810.h b/drivers/video/i810/i810.h index aa65ffce915..889e4ea5edc 100644 --- a/drivers/video/i810/i810.h +++ b/drivers/video/i810/i810.h | |||
@@ -133,7 +133,7 @@ | |||
133 | /* Masks (AND ops) and OR's */ | 133 | /* Masks (AND ops) and OR's */ |
134 | #define FB_START_MASK (0x3f << (32 - 6)) | 134 | #define FB_START_MASK (0x3f << (32 - 6)) |
135 | #define MMIO_ADDR_MASK (0x1FFF << (32 - 13)) | 135 | #define MMIO_ADDR_MASK (0x1FFF << (32 - 13)) |
136 | #define FREQ_MASK 0x1EF | 136 | #define FREQ_MASK (1 << 4) |
137 | #define SCR_OFF 0x20 | 137 | #define SCR_OFF 0x20 |
138 | #define DRAM_ON 0x08 | 138 | #define DRAM_ON 0x08 |
139 | #define DRAM_OFF 0xE7 | 139 | #define DRAM_OFF 0xE7 |
diff --git a/drivers/video/intelfb/intelfbhw.c b/drivers/video/intelfb/intelfbhw.c index c1eb18bf088..16bc8d75e36 100644 --- a/drivers/video/intelfb/intelfbhw.c +++ b/drivers/video/intelfb/intelfbhw.c | |||
@@ -1428,6 +1428,24 @@ static void refresh_ring(struct intelfb_info *dinfo); | |||
1428 | static void reset_state(struct intelfb_info *dinfo); | 1428 | static void reset_state(struct intelfb_info *dinfo); |
1429 | static void do_flush(struct intelfb_info *dinfo); | 1429 | static void do_flush(struct intelfb_info *dinfo); |
1430 | 1430 | ||
1431 | static u32 get_ring_space(struct intelfb_info *dinfo) | ||
1432 | { | ||
1433 | u32 ring_space; | ||
1434 | |||
1435 | if (dinfo->ring_tail >= dinfo->ring_head) | ||
1436 | ring_space = dinfo->ring.size - | ||
1437 | (dinfo->ring_tail - dinfo->ring_head); | ||
1438 | else | ||
1439 | ring_space = dinfo->ring_head - dinfo->ring_tail; | ||
1440 | |||
1441 | if (ring_space > RING_MIN_FREE) | ||
1442 | ring_space -= RING_MIN_FREE; | ||
1443 | else | ||
1444 | ring_space = 0; | ||
1445 | |||
1446 | return ring_space; | ||
1447 | } | ||
1448 | |||
1431 | static int | 1449 | static int |
1432 | wait_ring(struct intelfb_info *dinfo, int n) | 1450 | wait_ring(struct intelfb_info *dinfo, int n) |
1433 | { | 1451 | { |
@@ -1442,13 +1460,8 @@ wait_ring(struct intelfb_info *dinfo, int n) | |||
1442 | end = jiffies + (HZ * 3); | 1460 | end = jiffies + (HZ * 3); |
1443 | while (dinfo->ring_space < n) { | 1461 | while (dinfo->ring_space < n) { |
1444 | dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; | 1462 | dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; |
1445 | if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head) | 1463 | dinfo->ring_space = get_ring_space(dinfo); |
1446 | dinfo->ring_space = dinfo->ring_head | 1464 | |
1447 | - (dinfo->ring_tail + RING_MIN_FREE); | ||
1448 | else | ||
1449 | dinfo->ring_space = (dinfo->ring.size + | ||
1450 | dinfo->ring_head) | ||
1451 | - (dinfo->ring_tail + RING_MIN_FREE); | ||
1452 | if (dinfo->ring_head != last_head) { | 1465 | if (dinfo->ring_head != last_head) { |
1453 | end = jiffies + (HZ * 3); | 1466 | end = jiffies + (HZ * 3); |
1454 | last_head = dinfo->ring_head; | 1467 | last_head = dinfo->ring_head; |
@@ -1513,12 +1526,7 @@ refresh_ring(struct intelfb_info *dinfo) | |||
1513 | 1526 | ||
1514 | dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; | 1527 | dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; |
1515 | dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; | 1528 | dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; |
1516 | if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head) | 1529 | dinfo->ring_space = get_ring_space(dinfo); |
1517 | dinfo->ring_space = dinfo->ring_head | ||
1518 | - (dinfo->ring_tail + RING_MIN_FREE); | ||
1519 | else | ||
1520 | dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head) | ||
1521 | - (dinfo->ring_tail + RING_MIN_FREE); | ||
1522 | } | 1530 | } |
1523 | 1531 | ||
1524 | static void | 1532 | static void |
diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig index f0e6512c87f..9397bcef301 100644 --- a/drivers/video/logo/Kconfig +++ b/drivers/video/logo/Kconfig | |||
@@ -2,73 +2,69 @@ | |||
2 | # Logo configuration | 2 | # Logo configuration |
3 | # | 3 | # |
4 | 4 | ||
5 | menu "Logo configuration" | 5 | menuconfig LOGO |
6 | |||
7 | config LOGO | ||
8 | bool "Bootup logo" | 6 | bool "Bootup logo" |
9 | depends on FB || SGI_NEWPORT_CONSOLE | 7 | depends on FB || SGI_NEWPORT_CONSOLE |
10 | help | 8 | help |
11 | Enable and select frame buffer bootup logos. | 9 | Enable and select frame buffer bootup logos. |
12 | 10 | ||
11 | if LOGO | ||
12 | |||
13 | config LOGO_LINUX_MONO | 13 | config LOGO_LINUX_MONO |
14 | bool "Standard black and white Linux logo" | 14 | bool "Standard black and white Linux logo" |
15 | depends on LOGO | ||
16 | default y | 15 | default y |
17 | 16 | ||
18 | config LOGO_LINUX_VGA16 | 17 | config LOGO_LINUX_VGA16 |
19 | bool "Standard 16-color Linux logo" | 18 | bool "Standard 16-color Linux logo" |
20 | depends on LOGO | ||
21 | default y | 19 | default y |
22 | 20 | ||
23 | config LOGO_LINUX_CLUT224 | 21 | config LOGO_LINUX_CLUT224 |
24 | bool "Standard 224-color Linux logo" | 22 | bool "Standard 224-color Linux logo" |
25 | depends on LOGO | ||
26 | default y | 23 | default y |
27 | 24 | ||
28 | config LOGO_DEC_CLUT224 | 25 | config LOGO_DEC_CLUT224 |
29 | bool "224-color Digital Equipment Corporation Linux logo" | 26 | bool "224-color Digital Equipment Corporation Linux logo" |
30 | depends on LOGO && (MACH_DECSTATION || ALPHA) | 27 | depends on MACH_DECSTATION || ALPHA |
31 | default y | 28 | default y |
32 | 29 | ||
33 | config LOGO_MAC_CLUT224 | 30 | config LOGO_MAC_CLUT224 |
34 | bool "224-color Macintosh Linux logo" | 31 | bool "224-color Macintosh Linux logo" |
35 | depends on LOGO && MAC | 32 | depends on MAC |
36 | default y | 33 | default y |
37 | 34 | ||
38 | config LOGO_PARISC_CLUT224 | 35 | config LOGO_PARISC_CLUT224 |
39 | bool "224-color PA-RISC Linux logo" | 36 | bool "224-color PA-RISC Linux logo" |
40 | depends on LOGO && PARISC | 37 | depends on PARISC |
41 | default y | 38 | default y |
42 | 39 | ||
43 | config LOGO_SGI_CLUT224 | 40 | config LOGO_SGI_CLUT224 |
44 | bool "224-color SGI Linux logo" | 41 | bool "224-color SGI Linux logo" |
45 | depends on LOGO && (SGI_IP22 || SGI_IP27 || SGI_IP32 || X86_VISWS) | 42 | depends on SGI_IP22 || SGI_IP27 || SGI_IP32 || X86_VISWS |
46 | default y | 43 | default y |
47 | 44 | ||
48 | config LOGO_SUN_CLUT224 | 45 | config LOGO_SUN_CLUT224 |
49 | bool "224-color Sun Linux logo" | 46 | bool "224-color Sun Linux logo" |
50 | depends on LOGO && SPARC | 47 | depends on SPARC |
51 | default y | 48 | default y |
52 | 49 | ||
53 | config LOGO_SUPERH_MONO | 50 | config LOGO_SUPERH_MONO |
54 | bool "Black and white SuperH Linux logo" | 51 | bool "Black and white SuperH Linux logo" |
55 | depends on LOGO && SUPERH | 52 | depends on SUPERH |
56 | default y | 53 | default y |
57 | 54 | ||
58 | config LOGO_SUPERH_VGA16 | 55 | config LOGO_SUPERH_VGA16 |
59 | bool "16-color SuperH Linux logo" | 56 | bool "16-color SuperH Linux logo" |
60 | depends on LOGO && SUPERH | 57 | depends on SUPERH |
61 | default y | 58 | default y |
62 | 59 | ||
63 | config LOGO_SUPERH_CLUT224 | 60 | config LOGO_SUPERH_CLUT224 |
64 | bool "224-color SuperH Linux logo" | 61 | bool "224-color SuperH Linux logo" |
65 | depends on LOGO && SUPERH | 62 | depends on SUPERH |
66 | default y | 63 | default y |
67 | 64 | ||
68 | config LOGO_M32R_CLUT224 | 65 | config LOGO_M32R_CLUT224 |
69 | bool "224-color M32R Linux logo" | 66 | bool "224-color M32R Linux logo" |
70 | depends on LOGO && M32R | 67 | depends on M32R |
71 | default y | 68 | default y |
72 | 69 | ||
73 | endmenu | 70 | endif # LOGO |
74 | |||
diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c index 3e517940c5a..3741ad72940 100644 --- a/drivers/video/modedb.c +++ b/drivers/video/modedb.c | |||
@@ -395,7 +395,7 @@ static int my_atoi(const char *name) | |||
395 | 395 | ||
396 | for (;; name++) { | 396 | for (;; name++) { |
397 | switch (*name) { | 397 | switch (*name) { |
398 | case '0'...'9': | 398 | case '0' ... '9': |
399 | val = 10*val+(*name-'0'); | 399 | val = 10*val+(*name-'0'); |
400 | break; | 400 | break; |
401 | default: | 401 | default: |
@@ -548,7 +548,7 @@ int fb_find_mode(struct fb_var_screeninfo *var, | |||
548 | } else | 548 | } else |
549 | goto done; | 549 | goto done; |
550 | break; | 550 | break; |
551 | case '0'...'9': | 551 | case '0' ... '9': |
552 | break; | 552 | break; |
553 | case 'M': | 553 | case 'M': |
554 | if (!yres_specified) | 554 | if (!yres_specified) |
diff --git a/drivers/video/neofb.c b/drivers/video/neofb.c index 395ccedde9a..bd30aba242d 100644 --- a/drivers/video/neofb.c +++ b/drivers/video/neofb.c | |||
@@ -665,6 +665,7 @@ neofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
665 | var->red.msb_right = 0; | 665 | var->red.msb_right = 0; |
666 | var->green.msb_right = 0; | 666 | var->green.msb_right = 0; |
667 | var->blue.msb_right = 0; | 667 | var->blue.msb_right = 0; |
668 | var->transp.msb_right = 0; | ||
668 | 669 | ||
669 | switch (var->bits_per_pixel) { | 670 | switch (var->bits_per_pixel) { |
670 | case 8: /* PSEUDOCOLOUR, 256 */ | 671 | case 8: /* PSEUDOCOLOUR, 256 */ |
diff --git a/drivers/video/nvidia/nv_accel.c b/drivers/video/nvidia/nv_accel.c index 9efb8a3854e..fa4821c5572 100644 --- a/drivers/video/nvidia/nv_accel.c +++ b/drivers/video/nvidia/nv_accel.c | |||
@@ -69,27 +69,38 @@ static const int NVCopyROP_PM[16] = { | |||
69 | 0x5A, /* invert */ | 69 | 0x5A, /* invert */ |
70 | }; | 70 | }; |
71 | 71 | ||
72 | static inline void NVFlush(struct nvidia_par *par) | 72 | static inline void nvidiafb_safe_mode(struct fb_info *info) |
73 | { | 73 | { |
74 | struct nvidia_par *par = info->par; | ||
75 | |||
76 | touch_softlockup_watchdog(); | ||
77 | info->pixmap.scan_align = 1; | ||
78 | par->lockup = 1; | ||
79 | } | ||
80 | |||
81 | static inline void NVFlush(struct fb_info *info) | ||
82 | { | ||
83 | struct nvidia_par *par = info->par; | ||
74 | int count = 1000000000; | 84 | int count = 1000000000; |
75 | 85 | ||
76 | while (--count && READ_GET(par) != par->dmaPut) ; | 86 | while (--count && READ_GET(par) != par->dmaPut) ; |
77 | 87 | ||
78 | if (!count) { | 88 | if (!count) { |
79 | printk("nvidiafb: DMA Flush lockup\n"); | 89 | printk("nvidiafb: DMA Flush lockup\n"); |
80 | par->lockup = 1; | 90 | nvidiafb_safe_mode(info); |
81 | } | 91 | } |
82 | } | 92 | } |
83 | 93 | ||
84 | static inline void NVSync(struct nvidia_par *par) | 94 | static inline void NVSync(struct fb_info *info) |
85 | { | 95 | { |
96 | struct nvidia_par *par = info->par; | ||
86 | int count = 1000000000; | 97 | int count = 1000000000; |
87 | 98 | ||
88 | while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; | 99 | while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; |
89 | 100 | ||
90 | if (!count) { | 101 | if (!count) { |
91 | printk("nvidiafb: DMA Sync lockup\n"); | 102 | printk("nvidiafb: DMA Sync lockup\n"); |
92 | par->lockup = 1; | 103 | nvidiafb_safe_mode(info); |
93 | } | 104 | } |
94 | } | 105 | } |
95 | 106 | ||
@@ -101,8 +112,9 @@ static void NVDmaKickoff(struct nvidia_par *par) | |||
101 | } | 112 | } |
102 | } | 113 | } |
103 | 114 | ||
104 | static void NVDmaWait(struct nvidia_par *par, int size) | 115 | static void NVDmaWait(struct fb_info *info, int size) |
105 | { | 116 | { |
117 | struct nvidia_par *par = info->par; | ||
106 | int dmaGet; | 118 | int dmaGet; |
107 | int count = 1000000000, cnt; | 119 | int count = 1000000000, cnt; |
108 | size++; | 120 | size++; |
@@ -135,34 +147,38 @@ static void NVDmaWait(struct nvidia_par *par, int size) | |||
135 | } | 147 | } |
136 | 148 | ||
137 | if (!count) { | 149 | if (!count) { |
138 | printk("DMA Wait Lockup\n"); | 150 | printk("nvidiafb: DMA Wait Lockup\n"); |
139 | par->lockup = 1; | 151 | nvidiafb_safe_mode(info); |
140 | } | 152 | } |
141 | } | 153 | } |
142 | 154 | ||
143 | static void NVSetPattern(struct nvidia_par *par, u32 clr0, u32 clr1, | 155 | static void NVSetPattern(struct fb_info *info, u32 clr0, u32 clr1, |
144 | u32 pat0, u32 pat1) | 156 | u32 pat0, u32 pat1) |
145 | { | 157 | { |
146 | NVDmaStart(par, PATTERN_COLOR_0, 4); | 158 | struct nvidia_par *par = info->par; |
159 | |||
160 | NVDmaStart(info, par, PATTERN_COLOR_0, 4); | ||
147 | NVDmaNext(par, clr0); | 161 | NVDmaNext(par, clr0); |
148 | NVDmaNext(par, clr1); | 162 | NVDmaNext(par, clr1); |
149 | NVDmaNext(par, pat0); | 163 | NVDmaNext(par, pat0); |
150 | NVDmaNext(par, pat1); | 164 | NVDmaNext(par, pat1); |
151 | } | 165 | } |
152 | 166 | ||
153 | static void NVSetRopSolid(struct nvidia_par *par, u32 rop, u32 planemask) | 167 | static void NVSetRopSolid(struct fb_info *info, u32 rop, u32 planemask) |
154 | { | 168 | { |
169 | struct nvidia_par *par = info->par; | ||
170 | |||
155 | if (planemask != ~0) { | 171 | if (planemask != ~0) { |
156 | NVSetPattern(par, 0, planemask, ~0, ~0); | 172 | NVSetPattern(info, 0, planemask, ~0, ~0); |
157 | if (par->currentRop != (rop + 32)) { | 173 | if (par->currentRop != (rop + 32)) { |
158 | NVDmaStart(par, ROP_SET, 1); | 174 | NVDmaStart(info, par, ROP_SET, 1); |
159 | NVDmaNext(par, NVCopyROP_PM[rop]); | 175 | NVDmaNext(par, NVCopyROP_PM[rop]); |
160 | par->currentRop = rop + 32; | 176 | par->currentRop = rop + 32; |
161 | } | 177 | } |
162 | } else if (par->currentRop != rop) { | 178 | } else if (par->currentRop != rop) { |
163 | if (par->currentRop >= 16) | 179 | if (par->currentRop >= 16) |
164 | NVSetPattern(par, ~0, ~0, ~0, ~0); | 180 | NVSetPattern(info, ~0, ~0, ~0, ~0); |
165 | NVDmaStart(par, ROP_SET, 1); | 181 | NVDmaStart(info, par, ROP_SET, 1); |
166 | NVDmaNext(par, NVCopyROP[rop]); | 182 | NVDmaNext(par, NVCopyROP[rop]); |
167 | par->currentRop = rop; | 183 | par->currentRop = rop; |
168 | } | 184 | } |
@@ -175,7 +191,7 @@ static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1, | |||
175 | int h = y2 - y1 + 1; | 191 | int h = y2 - y1 + 1; |
176 | int w = x2 - x1 + 1; | 192 | int w = x2 - x1 + 1; |
177 | 193 | ||
178 | NVDmaStart(par, CLIP_POINT, 2); | 194 | NVDmaStart(info, par, CLIP_POINT, 2); |
179 | NVDmaNext(par, (y1 << 16) | x1); | 195 | NVDmaNext(par, (y1 << 16) | x1); |
180 | NVDmaNext(par, (h << 16) | w); | 196 | NVDmaNext(par, (h << 16) | w); |
181 | } | 197 | } |
@@ -237,23 +253,23 @@ void NVResetGraphics(struct fb_info *info) | |||
237 | break; | 253 | break; |
238 | } | 254 | } |
239 | 255 | ||
240 | NVDmaStart(par, SURFACE_FORMAT, 4); | 256 | NVDmaStart(info, par, SURFACE_FORMAT, 4); |
241 | NVDmaNext(par, surfaceFormat); | 257 | NVDmaNext(par, surfaceFormat); |
242 | NVDmaNext(par, pitch | (pitch << 16)); | 258 | NVDmaNext(par, pitch | (pitch << 16)); |
243 | NVDmaNext(par, 0); | 259 | NVDmaNext(par, 0); |
244 | NVDmaNext(par, 0); | 260 | NVDmaNext(par, 0); |
245 | 261 | ||
246 | NVDmaStart(par, PATTERN_FORMAT, 1); | 262 | NVDmaStart(info, par, PATTERN_FORMAT, 1); |
247 | NVDmaNext(par, patternFormat); | 263 | NVDmaNext(par, patternFormat); |
248 | 264 | ||
249 | NVDmaStart(par, RECT_FORMAT, 1); | 265 | NVDmaStart(info, par, RECT_FORMAT, 1); |
250 | NVDmaNext(par, rectFormat); | 266 | NVDmaNext(par, rectFormat); |
251 | 267 | ||
252 | NVDmaStart(par, LINE_FORMAT, 1); | 268 | NVDmaStart(info, par, LINE_FORMAT, 1); |
253 | NVDmaNext(par, lineFormat); | 269 | NVDmaNext(par, lineFormat); |
254 | 270 | ||
255 | par->currentRop = ~0; /* set to something invalid */ | 271 | par->currentRop = ~0; /* set to something invalid */ |
256 | NVSetRopSolid(par, ROP_COPY, ~0); | 272 | NVSetRopSolid(info, ROP_COPY, ~0); |
257 | 273 | ||
258 | NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual, | 274 | NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual, |
259 | info->var.yres_virtual); | 275 | info->var.yres_virtual); |
@@ -269,10 +285,10 @@ int nvidiafb_sync(struct fb_info *info) | |||
269 | return 0; | 285 | return 0; |
270 | 286 | ||
271 | if (!par->lockup) | 287 | if (!par->lockup) |
272 | NVFlush(par); | 288 | NVFlush(info); |
273 | 289 | ||
274 | if (!par->lockup) | 290 | if (!par->lockup) |
275 | NVSync(par); | 291 | NVSync(info); |
276 | 292 | ||
277 | return 0; | 293 | return 0; |
278 | } | 294 | } |
@@ -287,7 +303,7 @@ void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) | |||
287 | if (par->lockup) | 303 | if (par->lockup) |
288 | return cfb_copyarea(info, region); | 304 | return cfb_copyarea(info, region); |
289 | 305 | ||
290 | NVDmaStart(par, BLIT_POINT_SRC, 3); | 306 | NVDmaStart(info, par, BLIT_POINT_SRC, 3); |
291 | NVDmaNext(par, (region->sy << 16) | region->sx); | 307 | NVDmaNext(par, (region->sy << 16) | region->sx); |
292 | NVDmaNext(par, (region->dy << 16) | region->dx); | 308 | NVDmaNext(par, (region->dy << 16) | region->dx); |
293 | NVDmaNext(par, (region->height << 16) | region->width); | 309 | NVDmaNext(par, (region->height << 16) | region->width); |
@@ -312,19 +328,19 @@ void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |||
312 | color = ((u32 *) info->pseudo_palette)[rect->color]; | 328 | color = ((u32 *) info->pseudo_palette)[rect->color]; |
313 | 329 | ||
314 | if (rect->rop != ROP_COPY) | 330 | if (rect->rop != ROP_COPY) |
315 | NVSetRopSolid(par, rect->rop, ~0); | 331 | NVSetRopSolid(info, rect->rop, ~0); |
316 | 332 | ||
317 | NVDmaStart(par, RECT_SOLID_COLOR, 1); | 333 | NVDmaStart(info, par, RECT_SOLID_COLOR, 1); |
318 | NVDmaNext(par, color); | 334 | NVDmaNext(par, color); |
319 | 335 | ||
320 | NVDmaStart(par, RECT_SOLID_RECTS(0), 2); | 336 | NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2); |
321 | NVDmaNext(par, (rect->dx << 16) | rect->dy); | 337 | NVDmaNext(par, (rect->dx << 16) | rect->dy); |
322 | NVDmaNext(par, (rect->width << 16) | rect->height); | 338 | NVDmaNext(par, (rect->width << 16) | rect->height); |
323 | 339 | ||
324 | NVDmaKickoff(par); | 340 | NVDmaKickoff(par); |
325 | 341 | ||
326 | if (rect->rop != ROP_COPY) | 342 | if (rect->rop != ROP_COPY) |
327 | NVSetRopSolid(par, ROP_COPY, ~0); | 343 | NVSetRopSolid(info, ROP_COPY, ~0); |
328 | } | 344 | } |
329 | 345 | ||
330 | static void nvidiafb_mono_color_expand(struct fb_info *info, | 346 | static void nvidiafb_mono_color_expand(struct fb_info *info, |
@@ -346,7 +362,7 @@ static void nvidiafb_mono_color_expand(struct fb_info *info, | |||
346 | bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask; | 362 | bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask; |
347 | } | 363 | } |
348 | 364 | ||
349 | NVDmaStart(par, RECT_EXPAND_TWO_COLOR_CLIP, 7); | 365 | NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7); |
350 | NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff)); | 366 | NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff)); |
351 | NVDmaNext(par, ((image->dy + image->height) << 16) | | 367 | NVDmaNext(par, ((image->dy + image->height) << 16) | |
352 | ((image->dx + image->width) & 0xffff)); | 368 | ((image->dx + image->width) & 0xffff)); |
@@ -357,7 +373,7 @@ static void nvidiafb_mono_color_expand(struct fb_info *info, | |||
357 | NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff)); | 373 | NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff)); |
358 | 374 | ||
359 | while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) { | 375 | while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) { |
360 | NVDmaStart(par, RECT_EXPAND_TWO_COLOR_DATA(0), | 376 | NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), |
361 | RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS); | 377 | RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS); |
362 | 378 | ||
363 | for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) { | 379 | for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) { |
@@ -370,7 +386,7 @@ static void nvidiafb_mono_color_expand(struct fb_info *info, | |||
370 | } | 386 | } |
371 | 387 | ||
372 | if (dsize) { | 388 | if (dsize) { |
373 | NVDmaStart(par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize); | 389 | NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize); |
374 | 390 | ||
375 | for (j = dsize; j--;) { | 391 | for (j = dsize; j--;) { |
376 | tmp = data[k++]; | 392 | tmp = data[k++]; |
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c index ea426115c6f..f297c7b14a4 100644 --- a/drivers/video/nvidia/nv_hw.c +++ b/drivers/video/nvidia/nv_hw.c | |||
@@ -686,7 +686,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, | |||
686 | 686 | ||
687 | if ((par->Chipset & 0x0FF0) == 0x01A0) { | 687 | if ((par->Chipset & 0x0FF0) == 0x01A0) { |
688 | unsigned int uMClkPostDiv; | 688 | unsigned int uMClkPostDiv; |
689 | dev = pci_find_slot(0, 3); | 689 | dev = pci_get_bus_and_slot(0, 3); |
690 | pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); | 690 | pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); |
691 | uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; | 691 | uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; |
692 | 692 | ||
@@ -694,11 +694,11 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, | |||
694 | uMClkPostDiv = 4; | 694 | uMClkPostDiv = 4; |
695 | MClk = 400000 / uMClkPostDiv; | 695 | MClk = 400000 / uMClkPostDiv; |
696 | } else { | 696 | } else { |
697 | dev = pci_find_slot(0, 5); | 697 | dev = pci_get_bus_and_slot(0, 5); |
698 | pci_read_config_dword(dev, 0x4c, &MClk); | 698 | pci_read_config_dword(dev, 0x4c, &MClk); |
699 | MClk /= 1000; | 699 | MClk /= 1000; |
700 | } | 700 | } |
701 | 701 | pci_dev_put(dev); | |
702 | pll = NV_RD32(par->PRAMDAC0, 0x0500); | 702 | pll = NV_RD32(par->PRAMDAC0, 0x0500); |
703 | M = (pll >> 0) & 0xFF; | 703 | M = (pll >> 0) & 0xFF; |
704 | N = (pll >> 8) & 0xFF; | 704 | N = (pll >> 8) & 0xFF; |
@@ -707,19 +707,21 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, | |||
707 | sim_data.pix_bpp = (char)pixelDepth; | 707 | sim_data.pix_bpp = (char)pixelDepth; |
708 | sim_data.enable_video = 0; | 708 | sim_data.enable_video = 0; |
709 | sim_data.enable_mp = 0; | 709 | sim_data.enable_mp = 0; |
710 | pci_find_slot(0, 1); | 710 | dev = pci_get_bus_and_slot(0, 1); |
711 | pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); | 711 | pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); |
712 | pci_dev_put(dev); | ||
712 | sim_data.memory_type = (sim_data.memory_type >> 12) & 1; | 713 | sim_data.memory_type = (sim_data.memory_type >> 12) & 1; |
713 | sim_data.memory_width = 64; | 714 | sim_data.memory_width = 64; |
714 | 715 | ||
715 | dev = pci_find_slot(0, 3); | 716 | dev = pci_get_bus_and_slot(0, 3); |
716 | pci_read_config_dword(dev, 0, &memctrl); | 717 | pci_read_config_dword(dev, 0, &memctrl); |
718 | pci_dev_put(dev); | ||
717 | memctrl >>= 16; | 719 | memctrl >>= 16; |
718 | 720 | ||
719 | if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) { | 721 | if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) { |
720 | int dimm[3]; | 722 | int dimm[3]; |
721 | 723 | ||
722 | pci_find_slot(0, 2); | 724 | dev = pci_get_bus_and_slot(0, 2); |
723 | pci_read_config_dword(dev, 0x40, &dimm[0]); | 725 | pci_read_config_dword(dev, 0x40, &dimm[0]); |
724 | dimm[0] = (dimm[0] >> 8) & 0x4f; | 726 | dimm[0] = (dimm[0] >> 8) & 0x4f; |
725 | pci_read_config_dword(dev, 0x44, &dimm[1]); | 727 | pci_read_config_dword(dev, 0x44, &dimm[1]); |
@@ -731,6 +733,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, | |||
731 | printk("nvidiafb: your nForce DIMMs are not arranged " | 733 | printk("nvidiafb: your nForce DIMMs are not arranged " |
732 | "in optimal banks!\n"); | 734 | "in optimal banks!\n"); |
733 | } | 735 | } |
736 | pci_dev_put(dev); | ||
734 | } | 737 | } |
735 | 738 | ||
736 | sim_data.mem_latency = 3; | 739 | sim_data.mem_latency = 3; |
diff --git a/drivers/video/nvidia/nv_i2c.c b/drivers/video/nvidia/nv_i2c.c index b8588973e40..afe4567e1ff 100644 --- a/drivers/video/nvidia/nv_i2c.c +++ b/drivers/video/nvidia/nv_i2c.c | |||
@@ -30,16 +30,14 @@ static void nvidia_gpio_setscl(void *data, int state) | |||
30 | struct nvidia_par *par = chan->par; | 30 | struct nvidia_par *par = chan->par; |
31 | u32 val; | 31 | u32 val; |
32 | 32 | ||
33 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1); | 33 | val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; |
34 | val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0; | ||
35 | 34 | ||
36 | if (state) | 35 | if (state) |
37 | val |= 0x20; | 36 | val |= 0x20; |
38 | else | 37 | else |
39 | val &= ~0x20; | 38 | val &= ~0x20; |
40 | 39 | ||
41 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1); | 40 | NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); |
42 | VGA_WR08(par->PCIO, 0x3d5, val | 0x1); | ||
43 | } | 41 | } |
44 | 42 | ||
45 | static void nvidia_gpio_setsda(void *data, int state) | 43 | static void nvidia_gpio_setsda(void *data, int state) |
@@ -48,16 +46,14 @@ static void nvidia_gpio_setsda(void *data, int state) | |||
48 | struct nvidia_par *par = chan->par; | 46 | struct nvidia_par *par = chan->par; |
49 | u32 val; | 47 | u32 val; |
50 | 48 | ||
51 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1); | 49 | val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; |
52 | val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0; | ||
53 | 50 | ||
54 | if (state) | 51 | if (state) |
55 | val |= 0x10; | 52 | val |= 0x10; |
56 | else | 53 | else |
57 | val &= ~0x10; | 54 | val &= ~0x10; |
58 | 55 | ||
59 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1); | 56 | NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); |
60 | VGA_WR08(par->PCIO, 0x3d5, val | 0x1); | ||
61 | } | 57 | } |
62 | 58 | ||
63 | static int nvidia_gpio_getscl(void *data) | 59 | static int nvidia_gpio_getscl(void *data) |
@@ -66,12 +62,9 @@ static int nvidia_gpio_getscl(void *data) | |||
66 | struct nvidia_par *par = chan->par; | 62 | struct nvidia_par *par = chan->par; |
67 | u32 val = 0; | 63 | u32 val = 0; |
68 | 64 | ||
69 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base); | 65 | if (NVReadCrtc(par, chan->ddc_base) & 0x04) |
70 | if (VGA_RD08(par->PCIO, 0x3d5) & 0x04) | ||
71 | val = 1; | 66 | val = 1; |
72 | 67 | ||
73 | val = VGA_RD08(par->PCIO, 0x3d5); | ||
74 | |||
75 | return val; | 68 | return val; |
76 | } | 69 | } |
77 | 70 | ||
@@ -81,20 +74,21 @@ static int nvidia_gpio_getsda(void *data) | |||
81 | struct nvidia_par *par = chan->par; | 74 | struct nvidia_par *par = chan->par; |
82 | u32 val = 0; | 75 | u32 val = 0; |
83 | 76 | ||
84 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base); | 77 | if (NVReadCrtc(par, chan->ddc_base) & 0x08) |
85 | if (VGA_RD08(par->PCIO, 0x3d5) & 0x08) | ||
86 | val = 1; | 78 | val = 1; |
87 | 79 | ||
88 | return val; | 80 | return val; |
89 | } | 81 | } |
90 | 82 | ||
91 | static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name) | 83 | static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name, |
84 | unsigned int i2c_class) | ||
92 | { | 85 | { |
93 | int rc; | 86 | int rc; |
94 | 87 | ||
95 | strcpy(chan->adapter.name, name); | 88 | strcpy(chan->adapter.name, name); |
96 | chan->adapter.owner = THIS_MODULE; | 89 | chan->adapter.owner = THIS_MODULE; |
97 | chan->adapter.id = I2C_HW_B_NVIDIA; | 90 | chan->adapter.id = I2C_HW_B_NVIDIA; |
91 | chan->adapter.class = i2c_class; | ||
98 | chan->adapter.algo_data = &chan->algo; | 92 | chan->adapter.algo_data = &chan->algo; |
99 | chan->adapter.dev.parent = &chan->par->pci_dev->dev; | 93 | chan->adapter.dev.parent = &chan->par->pci_dev->dev; |
100 | chan->algo.setsda = nvidia_gpio_setsda; | 94 | chan->algo.setsda = nvidia_gpio_setsda; |
@@ -127,83 +121,39 @@ static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name) | |||
127 | 121 | ||
128 | void nvidia_create_i2c_busses(struct nvidia_par *par) | 122 | void nvidia_create_i2c_busses(struct nvidia_par *par) |
129 | { | 123 | { |
130 | par->bus = 3; | ||
131 | |||
132 | par->chan[0].par = par; | 124 | par->chan[0].par = par; |
133 | par->chan[1].par = par; | 125 | par->chan[1].par = par; |
134 | par->chan[2].par = par; | 126 | par->chan[2].par = par; |
135 | 127 | ||
136 | par->chan[0].ddc_base = 0x3e; | 128 | par->chan[0].ddc_base = 0x36; |
137 | nvidia_setup_i2c_bus(&par->chan[0], "nvidia #0"); | 129 | nvidia_setup_i2c_bus(&par->chan[0], "nvidia #0", I2C_CLASS_HWMON); |
138 | 130 | ||
139 | par->chan[1].ddc_base = 0x36; | 131 | par->chan[1].ddc_base = 0x3e; |
140 | nvidia_setup_i2c_bus(&par->chan[1], "nvidia #1"); | 132 | nvidia_setup_i2c_bus(&par->chan[1], "nvidia #1", 0); |
141 | 133 | ||
142 | par->chan[2].ddc_base = 0x50; | 134 | par->chan[2].ddc_base = 0x50; |
143 | nvidia_setup_i2c_bus(&par->chan[2], "nvidia #2"); | 135 | nvidia_setup_i2c_bus(&par->chan[2], "nvidia #2", 0); |
144 | } | 136 | } |
145 | 137 | ||
146 | void nvidia_delete_i2c_busses(struct nvidia_par *par) | 138 | void nvidia_delete_i2c_busses(struct nvidia_par *par) |
147 | { | 139 | { |
148 | if (par->chan[0].par) | 140 | int i; |
149 | i2c_del_adapter(&par->chan[0].adapter); | ||
150 | par->chan[0].par = NULL; | ||
151 | |||
152 | if (par->chan[1].par) | ||
153 | i2c_del_adapter(&par->chan[1].adapter); | ||
154 | par->chan[1].par = NULL; | ||
155 | |||
156 | if (par->chan[2].par) | ||
157 | i2c_del_adapter(&par->chan[2].adapter); | ||
158 | par->chan[2].par = NULL; | ||
159 | |||
160 | } | ||
161 | 141 | ||
162 | static u8 *nvidia_do_probe_i2c_edid(struct nvidia_i2c_chan *chan) | 142 | for (i = 0; i < 3; i++) { |
163 | { | 143 | if (!par->chan[i].par) |
164 | u8 start = 0x0; | 144 | continue; |
165 | struct i2c_msg msgs[] = { | 145 | i2c_del_adapter(&par->chan[i].adapter); |
166 | { | 146 | par->chan[i].par = NULL; |
167 | .addr = 0x50, | ||
168 | .len = 1, | ||
169 | .buf = &start, | ||
170 | }, { | ||
171 | .addr = 0x50, | ||
172 | .flags = I2C_M_RD, | ||
173 | .len = EDID_LENGTH, | ||
174 | }, | ||
175 | }; | ||
176 | u8 *buf; | ||
177 | |||
178 | if (!chan->par) | ||
179 | return NULL; | ||
180 | |||
181 | buf = kmalloc(EDID_LENGTH, GFP_KERNEL); | ||
182 | if (!buf) { | ||
183 | dev_warn(&chan->par->pci_dev->dev, "Out of memory!\n"); | ||
184 | return NULL; | ||
185 | } | 147 | } |
186 | msgs[1].buf = buf; | ||
187 | |||
188 | if (i2c_transfer(&chan->adapter, msgs, 2) == 2) | ||
189 | return buf; | ||
190 | dev_dbg(&chan->par->pci_dev->dev, "Unable to read EDID block.\n"); | ||
191 | kfree(buf); | ||
192 | return NULL; | ||
193 | } | 148 | } |
194 | 149 | ||
195 | int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid) | 150 | int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid) |
196 | { | 151 | { |
197 | struct nvidia_par *par = info->par; | 152 | struct nvidia_par *par = info->par; |
198 | u8 *edid = NULL; | 153 | u8 *edid = NULL; |
199 | int i; | ||
200 | 154 | ||
201 | for (i = 0; i < 3; i++) { | 155 | if (par->chan[conn - 1].par) |
202 | /* Do the real work */ | 156 | edid = fb_ddc_read(&par->chan[conn - 1].adapter); |
203 | edid = nvidia_do_probe_i2c_edid(&par->chan[conn - 1]); | ||
204 | if (edid) | ||
205 | break; | ||
206 | } | ||
207 | 157 | ||
208 | if (!edid && conn == 1) { | 158 | if (!edid && conn == 1) { |
209 | /* try to get from firmware */ | 159 | /* try to get from firmware */ |
diff --git a/drivers/video/nvidia/nv_local.h b/drivers/video/nvidia/nv_local.h index e009d242ea1..68e508daa41 100644 --- a/drivers/video/nvidia/nv_local.h +++ b/drivers/video/nvidia/nv_local.h | |||
@@ -73,9 +73,9 @@ | |||
73 | #define NVDmaNext(par, data) \ | 73 | #define NVDmaNext(par, data) \ |
74 | NV_WR32(&(par)->dmaBase[(par)->dmaCurrent++], 0, (data)) | 74 | NV_WR32(&(par)->dmaBase[(par)->dmaCurrent++], 0, (data)) |
75 | 75 | ||
76 | #define NVDmaStart(par, tag, size) { \ | 76 | #define NVDmaStart(info, par, tag, size) { \ |
77 | if((par)->dmaFree <= (size)) \ | 77 | if((par)->dmaFree <= (size)) \ |
78 | NVDmaWait(par, size); \ | 78 | NVDmaWait(info, size); \ |
79 | NVDmaNext(par, ((size) << 18) | (tag)); \ | 79 | NVDmaNext(par, ((size) << 18) | (tag)); \ |
80 | (par)->dmaFree -= ((size) + 1); \ | 80 | (par)->dmaFree -= ((size) + 1); \ |
81 | } | 81 | } |
diff --git a/drivers/video/nvidia/nv_of.c b/drivers/video/nvidia/nv_of.c index 163a774a1b3..73afd7eb997 100644 --- a/drivers/video/nvidia/nv_of.c +++ b/drivers/video/nvidia/nv_of.c | |||
@@ -46,15 +46,15 @@ int nvidia_probe_of_connector(struct fb_info *info, int conn, u8 **out_edid) | |||
46 | 46 | ||
47 | for (dp = NULL; | 47 | for (dp = NULL; |
48 | (dp = of_get_next_child(parent, dp)) != NULL;) { | 48 | (dp = of_get_next_child(parent, dp)) != NULL;) { |
49 | pname = get_property(dp, "name", NULL); | 49 | pname = of_get_property(dp, "name", NULL); |
50 | if (!pname) | 50 | if (!pname) |
51 | continue; | 51 | continue; |
52 | len = strlen(pname); | 52 | len = strlen(pname); |
53 | if ((pname[len-1] == 'A' && conn == 1) || | 53 | if ((pname[len-1] == 'A' && conn == 1) || |
54 | (pname[len-1] == 'B' && conn == 2)) { | 54 | (pname[len-1] == 'B' && conn == 2)) { |
55 | for (i = 0; propnames[i] != NULL; ++i) { | 55 | for (i = 0; propnames[i] != NULL; ++i) { |
56 | pedid = get_property(dp, propnames[i], | 56 | pedid = of_get_property(dp, |
57 | NULL); | 57 | propnames[i], NULL); |
58 | if (pedid != NULL) | 58 | if (pedid != NULL) |
59 | break; | 59 | break; |
60 | } | 60 | } |
@@ -65,7 +65,7 @@ int nvidia_probe_of_connector(struct fb_info *info, int conn, u8 **out_edid) | |||
65 | } | 65 | } |
66 | if (pedid == NULL) { | 66 | if (pedid == NULL) { |
67 | for (i = 0; propnames[i] != NULL; ++i) { | 67 | for (i = 0; propnames[i] != NULL; ++i) { |
68 | pedid = get_property(parent, propnames[i], NULL); | 68 | pedid = of_get_property(parent, propnames[i], NULL); |
69 | if (pedid != NULL) | 69 | if (pedid != NULL) |
70 | break; | 70 | break; |
71 | } | 71 | } |
diff --git a/drivers/video/nvidia/nv_setup.c b/drivers/video/nvidia/nv_setup.c index eab3e282a4d..707e2c8a13e 100644 --- a/drivers/video/nvidia/nv_setup.c +++ b/drivers/video/nvidia/nv_setup.c | |||
@@ -261,7 +261,7 @@ static void nv10GetConfig(struct nvidia_par *par) | |||
261 | } | 261 | } |
262 | #endif | 262 | #endif |
263 | 263 | ||
264 | dev = pci_find_slot(0, 1); | 264 | dev = pci_get_bus_and_slot(0, 1); |
265 | if ((par->Chipset & 0xffff) == 0x01a0) { | 265 | if ((par->Chipset & 0xffff) == 0x01a0) { |
266 | int amt = 0; | 266 | int amt = 0; |
267 | 267 | ||
@@ -276,6 +276,7 @@ static void nv10GetConfig(struct nvidia_par *par) | |||
276 | par->RamAmountKBytes = | 276 | par->RamAmountKBytes = |
277 | (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; | 277 | (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; |
278 | } | 278 | } |
279 | pci_dev_put(dev); | ||
279 | 280 | ||
280 | par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? | 281 | par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? |
281 | 14318 : 13500; | 282 | 14318 : 13500; |
@@ -656,7 +657,7 @@ int NVCommonSetup(struct fb_info *info) | |||
656 | par->LVDS = 0; | 657 | par->LVDS = 0; |
657 | if (par->FlatPanel && par->twoHeads) { | 658 | if (par->FlatPanel && par->twoHeads) { |
658 | NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004); | 659 | NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004); |
659 | if (par->PRAMDAC0[0x08b4] & 1) | 660 | if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1) |
660 | par->LVDS = 1; | 661 | par->LVDS = 1; |
661 | printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS"); | 662 | printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS"); |
662 | } | 663 | } |
diff --git a/drivers/video/nvidia/nv_type.h b/drivers/video/nvidia/nv_type.h index 86e65dea60d..38f7cc0a233 100644 --- a/drivers/video/nvidia/nv_type.h +++ b/drivers/video/nvidia/nv_type.h | |||
@@ -4,8 +4,9 @@ | |||
4 | #include <linux/fb.h> | 4 | #include <linux/fb.h> |
5 | #include <linux/types.h> | 5 | #include <linux/types.h> |
6 | #include <linux/i2c.h> | 6 | #include <linux/i2c.h> |
7 | #include <linux/i2c-id.h> | ||
8 | #include <linux/i2c-algo-bit.h> | 7 | #include <linux/i2c-algo-bit.h> |
8 | #include <linux/mutex.h> | ||
9 | #include <video/vga.h> | ||
9 | 10 | ||
10 | #define NV_ARCH_04 0x04 | 11 | #define NV_ARCH_04 0x04 |
11 | #define NV_ARCH_10 0x10 | 12 | #define NV_ARCH_10 0x10 |
@@ -94,13 +95,15 @@ struct riva_regs { | |||
94 | struct nvidia_par { | 95 | struct nvidia_par { |
95 | RIVA_HW_STATE SavedReg; | 96 | RIVA_HW_STATE SavedReg; |
96 | RIVA_HW_STATE ModeReg; | 97 | RIVA_HW_STATE ModeReg; |
98 | RIVA_HW_STATE initial_state; | ||
97 | RIVA_HW_STATE *CurrentState; | 99 | RIVA_HW_STATE *CurrentState; |
100 | struct vgastate vgastate; | ||
101 | struct mutex open_lock; | ||
98 | u32 pseudo_palette[16]; | 102 | u32 pseudo_palette[16]; |
99 | struct pci_dev *pci_dev; | 103 | struct pci_dev *pci_dev; |
100 | u32 Architecture; | 104 | u32 Architecture; |
101 | u32 CursorStart; | 105 | u32 CursorStart; |
102 | int Chipset; | 106 | int Chipset; |
103 | int bus; | ||
104 | unsigned long FbAddress; | 107 | unsigned long FbAddress; |
105 | u8 __iomem *FbStart; | 108 | u8 __iomem *FbStart; |
106 | u32 FbMapSize; | 109 | u32 FbMapSize; |
@@ -143,6 +146,7 @@ struct nvidia_par { | |||
143 | int BlendingPossible; | 146 | int BlendingPossible; |
144 | u32 paletteEnabled; | 147 | u32 paletteEnabled; |
145 | u32 forceCRTC; | 148 | u32 forceCRTC; |
149 | u32 open_count; | ||
146 | u8 DDCBase; | 150 | u8 DDCBase; |
147 | #ifdef CONFIG_MTRR | 151 | #ifdef CONFIG_MTRR |
148 | struct { | 152 | struct { |
diff --git a/drivers/video/nvidia/nvidia.c b/drivers/video/nvidia/nvidia.c index b97ec690126..7c36b5fe582 100644 --- a/drivers/video/nvidia/nvidia.c +++ b/drivers/video/nvidia/nvidia.c | |||
@@ -200,7 +200,7 @@ static int nvidia_panel_tweak(struct nvidia_par *par, | |||
200 | return tweak; | 200 | return tweak; |
201 | } | 201 | } |
202 | 202 | ||
203 | static void nvidia_vga_protect(struct nvidia_par *par, int on) | 203 | static void nvidia_screen_off(struct nvidia_par *par, int on) |
204 | { | 204 | { |
205 | unsigned char tmp; | 205 | unsigned char tmp; |
206 | 206 | ||
@@ -649,7 +649,7 @@ static int nvidiafb_set_par(struct fb_info *info) | |||
649 | NVLockUnlock(par, 0); | 649 | NVLockUnlock(par, 0); |
650 | } | 650 | } |
651 | 651 | ||
652 | nvidia_vga_protect(par, 1); | 652 | nvidia_screen_off(par, 1); |
653 | 653 | ||
654 | nvidia_write_regs(par, &par->ModeReg); | 654 | nvidia_write_regs(par, &par->ModeReg); |
655 | NVSetStartAddress(par, 0); | 655 | NVSetStartAddress(par, 0); |
@@ -687,7 +687,7 @@ static int nvidiafb_set_par(struct fb_info *info) | |||
687 | 687 | ||
688 | par->cursor_reset = 1; | 688 | par->cursor_reset = 1; |
689 | 689 | ||
690 | nvidia_vga_protect(par, 0); | 690 | nvidia_screen_off(par, 0); |
691 | 691 | ||
692 | #ifdef CONFIG_BOOTX_TEXT | 692 | #ifdef CONFIG_BOOTX_TEXT |
693 | /* Update debug text engine */ | 693 | /* Update debug text engine */ |
@@ -696,6 +696,7 @@ static int nvidiafb_set_par(struct fb_info *info) | |||
696 | info->var.bits_per_pixel, info->fix.line_length); | 696 | info->var.bits_per_pixel, info->fix.line_length); |
697 | #endif | 697 | #endif |
698 | 698 | ||
699 | NVLockUnlock(par, 0); | ||
699 | NVTRACE_LEAVE(); | 700 | NVTRACE_LEAVE(); |
700 | return 0; | 701 | return 0; |
701 | } | 702 | } |
@@ -948,8 +949,80 @@ static int nvidiafb_blank(int blank, struct fb_info *info) | |||
948 | return 0; | 949 | return 0; |
949 | } | 950 | } |
950 | 951 | ||
952 | /* | ||
953 | * Because the VGA registers are not mapped linearly in its MMIO space, | ||
954 | * restrict VGA register saving and restore to x86 only, where legacy VGA IO | ||
955 | * access is legal. Consequently, we must also check if the device is the | ||
956 | * primary display. | ||
957 | */ | ||
958 | #ifdef CONFIG_X86 | ||
959 | static void save_vga_x86(struct nvidia_par *par) | ||
960 | { | ||
961 | struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; | ||
962 | |||
963 | if (res && res->flags & IORESOURCE_ROM_SHADOW) { | ||
964 | memset(&par->vgastate, 0, sizeof(par->vgastate)); | ||
965 | par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | | ||
966 | VGA_SAVE_CMAP; | ||
967 | save_vga(&par->vgastate); | ||
968 | } | ||
969 | } | ||
970 | |||
971 | static void restore_vga_x86(struct nvidia_par *par) | ||
972 | { | ||
973 | struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; | ||
974 | |||
975 | if (res && res->flags & IORESOURCE_ROM_SHADOW) | ||
976 | restore_vga(&par->vgastate); | ||
977 | } | ||
978 | #else | ||
979 | #define save_vga_x86(x) do {} while (0) | ||
980 | #define restore_vga_x86(x) do {} while (0) | ||
981 | #endif /* X86 */ | ||
982 | |||
983 | static int nvidiafb_open(struct fb_info *info, int user) | ||
984 | { | ||
985 | struct nvidia_par *par = info->par; | ||
986 | |||
987 | mutex_lock(&par->open_lock); | ||
988 | |||
989 | if (!par->open_count) { | ||
990 | save_vga_x86(par); | ||
991 | nvidia_save_vga(par, &par->initial_state); | ||
992 | } | ||
993 | |||
994 | par->open_count++; | ||
995 | mutex_unlock(&par->open_lock); | ||
996 | return 0; | ||
997 | } | ||
998 | |||
999 | static int nvidiafb_release(struct fb_info *info, int user) | ||
1000 | { | ||
1001 | struct nvidia_par *par = info->par; | ||
1002 | int err = 0; | ||
1003 | |||
1004 | mutex_lock(&par->open_lock); | ||
1005 | |||
1006 | if (!par->open_count) { | ||
1007 | err = -EINVAL; | ||
1008 | goto done; | ||
1009 | } | ||
1010 | |||
1011 | if (par->open_count == 1) { | ||
1012 | nvidia_write_regs(par, &par->initial_state); | ||
1013 | restore_vga_x86(par); | ||
1014 | } | ||
1015 | |||
1016 | par->open_count--; | ||
1017 | done: | ||
1018 | mutex_unlock(&par->open_lock); | ||
1019 | return err; | ||
1020 | } | ||
1021 | |||
951 | static struct fb_ops nvidia_fb_ops = { | 1022 | static struct fb_ops nvidia_fb_ops = { |
952 | .owner = THIS_MODULE, | 1023 | .owner = THIS_MODULE, |
1024 | .fb_open = nvidiafb_open, | ||
1025 | .fb_release = nvidiafb_release, | ||
953 | .fb_check_var = nvidiafb_check_var, | 1026 | .fb_check_var = nvidiafb_check_var, |
954 | .fb_set_par = nvidiafb_set_par, | 1027 | .fb_set_par = nvidiafb_set_par, |
955 | .fb_setcolreg = nvidiafb_setcolreg, | 1028 | .fb_setcolreg = nvidiafb_setcolreg, |
@@ -1207,7 +1280,7 @@ static int __devinit nvidiafb_probe(struct pci_dev *pd, | |||
1207 | 1280 | ||
1208 | par = info->par; | 1281 | par = info->par; |
1209 | par->pci_dev = pd; | 1282 | par->pci_dev = pd; |
1210 | 1283 | mutex_init(&par->open_lock); | |
1211 | info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); | 1284 | info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); |
1212 | 1285 | ||
1213 | if (info->pixmap.addr == NULL) | 1286 | if (info->pixmap.addr == NULL) |
diff --git a/drivers/video/offb.c b/drivers/video/offb.c index 9576a55eaf1..885b42836cb 100644 --- a/drivers/video/offb.c +++ b/drivers/video/offb.c | |||
@@ -322,8 +322,8 @@ static void __init offb_init_fb(const char *name, const char *full_name, | |||
322 | ioremap(base + 0x7ff000, 0x1000) + 0xcc0; | 322 | ioremap(base + 0x7ff000, 0x1000) + 0xcc0; |
323 | par->cmap_data = par->cmap_adr + 1; | 323 | par->cmap_data = par->cmap_adr + 1; |
324 | par->cmap_type = cmap_m64; | 324 | par->cmap_type = cmap_m64; |
325 | } else if (dp && (device_is_compatible(dp, "pci1014,b7") || | 325 | } else if (dp && (of_device_is_compatible(dp, "pci1014,b7") || |
326 | device_is_compatible(dp, "pci1014,21c"))) { | 326 | of_device_is_compatible(dp, "pci1014,21c"))) { |
327 | par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000); | 327 | par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000); |
328 | if (par->cmap_adr) | 328 | if (par->cmap_adr) |
329 | par->cmap_type = cmap_gxt2000; | 329 | par->cmap_type = cmap_gxt2000; |
@@ -425,27 +425,27 @@ static void __init offb_init_nodriver(struct device_node *dp, int no_real_node) | |||
425 | const u32 *pp, *addrp, *up; | 425 | const u32 *pp, *addrp, *up; |
426 | u64 asize; | 426 | u64 asize; |
427 | 427 | ||
428 | pp = get_property(dp, "linux,bootx-depth", &len); | 428 | pp = of_get_property(dp, "linux,bootx-depth", &len); |
429 | if (pp == NULL) | 429 | if (pp == NULL) |
430 | pp = get_property(dp, "depth", &len); | 430 | pp = of_get_property(dp, "depth", &len); |
431 | if (pp && len == sizeof(u32)) | 431 | if (pp && len == sizeof(u32)) |
432 | depth = *pp; | 432 | depth = *pp; |
433 | 433 | ||
434 | pp = get_property(dp, "linux,bootx-width", &len); | 434 | pp = of_get_property(dp, "linux,bootx-width", &len); |
435 | if (pp == NULL) | 435 | if (pp == NULL) |
436 | pp = get_property(dp, "width", &len); | 436 | pp = of_get_property(dp, "width", &len); |
437 | if (pp && len == sizeof(u32)) | 437 | if (pp && len == sizeof(u32)) |
438 | width = *pp; | 438 | width = *pp; |
439 | 439 | ||
440 | pp = get_property(dp, "linux,bootx-height", &len); | 440 | pp = of_get_property(dp, "linux,bootx-height", &len); |
441 | if (pp == NULL) | 441 | if (pp == NULL) |
442 | pp = get_property(dp, "height", &len); | 442 | pp = of_get_property(dp, "height", &len); |
443 | if (pp && len == sizeof(u32)) | 443 | if (pp && len == sizeof(u32)) |
444 | height = *pp; | 444 | height = *pp; |
445 | 445 | ||
446 | pp = get_property(dp, "linux,bootx-linebytes", &len); | 446 | pp = of_get_property(dp, "linux,bootx-linebytes", &len); |
447 | if (pp == NULL) | 447 | if (pp == NULL) |
448 | pp = get_property(dp, "linebytes", &len); | 448 | pp = of_get_property(dp, "linebytes", &len); |
449 | if (pp && len == sizeof(u32) && (*pp != 0xffffffffu)) | 449 | if (pp && len == sizeof(u32) && (*pp != 0xffffffffu)) |
450 | pitch = *pp; | 450 | pitch = *pp; |
451 | else | 451 | else |
@@ -463,9 +463,9 @@ static void __init offb_init_nodriver(struct device_node *dp, int no_real_node) | |||
463 | * ranges and pick one that is both big enough and if possible encloses | 463 | * ranges and pick one that is both big enough and if possible encloses |
464 | * the "address" property. If none match, we pick the biggest | 464 | * the "address" property. If none match, we pick the biggest |
465 | */ | 465 | */ |
466 | up = get_property(dp, "linux,bootx-addr", &len); | 466 | up = of_get_property(dp, "linux,bootx-addr", &len); |
467 | if (up == NULL) | 467 | if (up == NULL) |
468 | up = get_property(dp, "address", &len); | 468 | up = of_get_property(dp, "address", &len); |
469 | if (up && len == sizeof(u32)) | 469 | if (up && len == sizeof(u32)) |
470 | addr_prop = *up; | 470 | addr_prop = *up; |
471 | 471 | ||
@@ -521,7 +521,7 @@ static int __init offb_init(void) | |||
521 | return -ENODEV; | 521 | return -ENODEV; |
522 | 522 | ||
523 | /* Check if we have a MacOS display without a node spec */ | 523 | /* Check if we have a MacOS display without a node spec */ |
524 | if (get_property(of_chosen, "linux,bootx-noscreen", NULL) != NULL) { | 524 | if (of_get_property(of_chosen, "linux,bootx-noscreen", NULL) != NULL) { |
525 | /* The old code tried to work out which node was the MacOS | 525 | /* The old code tried to work out which node was the MacOS |
526 | * display based on the address. I'm dropping that since the | 526 | * display based on the address. I'm dropping that since the |
527 | * lack of a node spec only happens with old BootX versions | 527 | * lack of a node spec only happens with old BootX versions |
@@ -532,14 +532,14 @@ static int __init offb_init(void) | |||
532 | } | 532 | } |
533 | 533 | ||
534 | for (dp = NULL; (dp = of_find_node_by_type(dp, "display"));) { | 534 | for (dp = NULL; (dp = of_find_node_by_type(dp, "display"));) { |
535 | if (get_property(dp, "linux,opened", NULL) && | 535 | if (of_get_property(dp, "linux,opened", NULL) && |
536 | get_property(dp, "linux,boot-display", NULL)) { | 536 | of_get_property(dp, "linux,boot-display", NULL)) { |
537 | boot_disp = dp; | 537 | boot_disp = dp; |
538 | offb_init_nodriver(dp, 0); | 538 | offb_init_nodriver(dp, 0); |
539 | } | 539 | } |
540 | } | 540 | } |
541 | for (dp = NULL; (dp = of_find_node_by_type(dp, "display"));) { | 541 | for (dp = NULL; (dp = of_find_node_by_type(dp, "display"));) { |
542 | if (get_property(dp, "linux,opened", NULL) && | 542 | if (of_get_property(dp, "linux,opened", NULL) && |
543 | dp != boot_disp) | 543 | dp != boot_disp) |
544 | offb_init_nodriver(dp, 0); | 544 | offb_init_nodriver(dp, 0); |
545 | } | 545 | } |
diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c index a560a222382..1ac5264bb2c 100644 --- a/drivers/video/pm2fb.c +++ b/drivers/video/pm2fb.c | |||
@@ -81,8 +81,6 @@ static int lowvsync; | |||
81 | struct pm2fb_par | 81 | struct pm2fb_par |
82 | { | 82 | { |
83 | pm2type_t type; /* Board type */ | 83 | pm2type_t type; /* Board type */ |
84 | u32 fb_size; /* framebuffer memory size */ | ||
85 | unsigned char __iomem *v_fb; /* virtual address of frame buffer */ | ||
86 | unsigned char __iomem *v_regs;/* virtual address of p_regs */ | 84 | unsigned char __iomem *v_regs;/* virtual address of p_regs */ |
87 | u32 memclock; /* memclock */ | 85 | u32 memclock; /* memclock */ |
88 | u32 video; /* video flags before blanking */ | 86 | u32 video; /* video flags before blanking */ |
@@ -103,7 +101,7 @@ static struct fb_fix_screeninfo pm2fb_fix __devinitdata = { | |||
103 | .xpanstep = 1, | 101 | .xpanstep = 1, |
104 | .ypanstep = 1, | 102 | .ypanstep = 1, |
105 | .ywrapstep = 0, | 103 | .ywrapstep = 0, |
106 | .accel = FB_ACCEL_NONE, | 104 | .accel = FB_ACCEL_3DLABS_PERMEDIA2, |
107 | }; | 105 | }; |
108 | 106 | ||
109 | /* | 107 | /* |
@@ -206,6 +204,17 @@ static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a) | |||
206 | } | 204 | } |
207 | #endif | 205 | #endif |
208 | 206 | ||
207 | static void wait_pm2(struct pm2fb_par* par) { | ||
208 | |||
209 | WAIT_FIFO(par, 1); | ||
210 | pm2_WR(par, PM2R_SYNC, 0); | ||
211 | mb(); | ||
212 | do { | ||
213 | while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0); | ||
214 | rmb(); | ||
215 | } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC)); | ||
216 | } | ||
217 | |||
209 | /* | 218 | /* |
210 | * partial products for the supported horizontal resolutions. | 219 | * partial products for the supported horizontal resolutions. |
211 | */ | 220 | */ |
@@ -302,10 +311,10 @@ static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn, | |||
302 | s32 delta = 1000; | 311 | s32 delta = 1000; |
303 | 312 | ||
304 | *mm = *nn = *pp = 0; | 313 | *mm = *nn = *pp = 0; |
305 | for (n = 1; n; n++) { | 314 | for ( m = 1; m < 128; m++) { |
306 | for ( m = 1; m; m++) { | 315 | for (n = 2 * m + 1; n; n++) { |
307 | for ( p = 0; p < 2; p++) { | 316 | for ( p = 0; p < 2; p++) { |
308 | f = PM2_REFERENCE_CLOCK * n / (m * (1 << (p + 1))); | 317 | f = ( PM2_REFERENCE_CLOCK >> ( p + 1 )) * n / m; |
309 | if ( clk > f - delta && clk < f + delta ) { | 318 | if ( clk > f - delta && clk < f + delta ) { |
310 | delta = ( clk > f ) ? clk - f : f - clk; | 319 | delta = ( clk > f ) ? clk - f : f - clk; |
311 | *mm=m; | 320 | *mm=m; |
@@ -462,21 +471,43 @@ static void set_memclock(struct pm2fb_par* par, u32 clk) | |||
462 | int i; | 471 | int i; |
463 | unsigned char m, n, p; | 472 | unsigned char m, n, p; |
464 | 473 | ||
465 | pm2_mnp(clk, &m, &n, &p); | 474 | switch (par->type) { |
466 | WAIT_FIFO(par, 10); | 475 | case PM2_TYPE_PERMEDIA2V: |
467 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6); | 476 | pm2v_mnp(clk/2, &m, &n, &p); |
468 | wmb(); | 477 | WAIT_FIFO(par, 8); |
469 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m); | 478 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8); |
470 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n); | 479 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0); |
471 | wmb(); | 480 | wmb(); |
472 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p); | 481 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m); |
473 | wmb(); | 482 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n); |
474 | pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS); | 483 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p); |
475 | rmb(); | 484 | wmb(); |
476 | for (i = 256; | 485 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1); |
477 | i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED); | 486 | rmb(); |
478 | i--) | 487 | for (i = 256; |
479 | ; | 488 | i && !(pm2_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2); |
489 | i--) | ||
490 | ; | ||
491 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); | ||
492 | break; | ||
493 | case PM2_TYPE_PERMEDIA2: | ||
494 | pm2_mnp(clk, &m, &n, &p); | ||
495 | WAIT_FIFO(par, 10); | ||
496 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6); | ||
497 | wmb(); | ||
498 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m); | ||
499 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n); | ||
500 | wmb(); | ||
501 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p); | ||
502 | wmb(); | ||
503 | pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS); | ||
504 | rmb(); | ||
505 | for (i = 256; | ||
506 | i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED); | ||
507 | i--) | ||
508 | ; | ||
509 | break; | ||
510 | } | ||
480 | } | 511 | } |
481 | 512 | ||
482 | static void set_pixclock(struct pm2fb_par* par, u32 clk) | 513 | static void set_pixclock(struct pm2fb_par* par, u32 clk) |
@@ -623,6 +654,8 @@ static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
623 | return -EINVAL; | 654 | return -EINVAL; |
624 | } | 655 | } |
625 | 656 | ||
657 | var->transp.offset = 0; | ||
658 | var->transp.length = 0; | ||
626 | switch(var->bits_per_pixel) { | 659 | switch(var->bits_per_pixel) { |
627 | case 8: | 660 | case 8: |
628 | var->red.length = var->green.length = var->blue.length = 8; | 661 | var->red.length = var->green.length = var->blue.length = 8; |
@@ -1017,6 +1050,117 @@ static int pm2fb_blank(int blank_mode, struct fb_info *info) | |||
1017 | return 0; | 1050 | return 0; |
1018 | } | 1051 | } |
1019 | 1052 | ||
1053 | /* | ||
1054 | * block operation. copy=0: rectangle fill, copy=1: rectangle copy. | ||
1055 | */ | ||
1056 | static void pm2fb_block_op(struct pm2fb_par* par, int copy, | ||
1057 | s32 xsrc, s32 ysrc, | ||
1058 | s32 x, s32 y, s32 w, s32 h, | ||
1059 | u32 color) { | ||
1060 | |||
1061 | if (!w || !h) | ||
1062 | return; | ||
1063 | WAIT_FIFO(par, 6); | ||
1064 | pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE | | ||
1065 | PM2F_CONFIG_FB_READ_SOURCE_ENABLE); | ||
1066 | pm2_WR(par, PM2R_FB_PIXEL_OFFSET, 0); | ||
1067 | if (copy) | ||
1068 | pm2_WR(par, PM2R_FB_SOURCE_DELTA, | ||
1069 | ((ysrc-y) & 0xfff) << 16 | ((xsrc-x) & 0xfff)); | ||
1070 | else | ||
1071 | pm2_WR(par, PM2R_FB_BLOCK_COLOR, color); | ||
1072 | pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (y << 16) | x); | ||
1073 | pm2_WR(par, PM2R_RECTANGLE_SIZE, (h << 16) | w); | ||
1074 | wmb(); | ||
1075 | pm2_WR(par, PM2R_RENDER,PM2F_RENDER_RECTANGLE | | ||
1076 | (x<xsrc ? PM2F_INCREASE_X : 0) | | ||
1077 | (y<ysrc ? PM2F_INCREASE_Y : 0) | | ||
1078 | (copy ? 0 : PM2F_RENDER_FASTFILL)); | ||
1079 | wait_pm2(par); | ||
1080 | } | ||
1081 | |||
1082 | static void pm2fb_fillrect (struct fb_info *info, | ||
1083 | const struct fb_fillrect *region) | ||
1084 | { | ||
1085 | struct pm2fb_par *par = info->par; | ||
1086 | struct fb_fillrect modded; | ||
1087 | int vxres, vyres; | ||
1088 | u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? | ||
1089 | ((u32*)info->pseudo_palette)[region->color] : region->color; | ||
1090 | |||
1091 | if (info->state != FBINFO_STATE_RUNNING) | ||
1092 | return; | ||
1093 | if ((info->flags & FBINFO_HWACCEL_DISABLED) || | ||
1094 | region->rop != ROP_COPY ) { | ||
1095 | cfb_fillrect(info, region); | ||
1096 | return; | ||
1097 | } | ||
1098 | |||
1099 | vxres = info->var.xres_virtual; | ||
1100 | vyres = info->var.yres_virtual; | ||
1101 | |||
1102 | memcpy(&modded, region, sizeof(struct fb_fillrect)); | ||
1103 | |||
1104 | if(!modded.width || !modded.height || | ||
1105 | modded.dx >= vxres || modded.dy >= vyres) | ||
1106 | return; | ||
1107 | |||
1108 | if(modded.dx + modded.width > vxres) | ||
1109 | modded.width = vxres - modded.dx; | ||
1110 | if(modded.dy + modded.height > vyres) | ||
1111 | modded.height = vyres - modded.dy; | ||
1112 | |||
1113 | if(info->var.bits_per_pixel == 8) | ||
1114 | color |= color << 8; | ||
1115 | if(info->var.bits_per_pixel <= 16) | ||
1116 | color |= color << 16; | ||
1117 | |||
1118 | if(info->var.bits_per_pixel != 24) | ||
1119 | pm2fb_block_op(par, 0, 0, 0, | ||
1120 | modded.dx, modded.dy, | ||
1121 | modded.width, modded.height, color); | ||
1122 | else | ||
1123 | cfb_fillrect(info, region); | ||
1124 | } | ||
1125 | |||
1126 | static void pm2fb_copyarea(struct fb_info *info, | ||
1127 | const struct fb_copyarea *area) | ||
1128 | { | ||
1129 | struct pm2fb_par *par = info->par; | ||
1130 | struct fb_copyarea modded; | ||
1131 | u32 vxres, vyres; | ||
1132 | |||
1133 | if (info->state != FBINFO_STATE_RUNNING) | ||
1134 | return; | ||
1135 | if (info->flags & FBINFO_HWACCEL_DISABLED) { | ||
1136 | cfb_copyarea(info, area); | ||
1137 | return; | ||
1138 | } | ||
1139 | |||
1140 | memcpy(&modded, area, sizeof(struct fb_copyarea)); | ||
1141 | |||
1142 | vxres = info->var.xres_virtual; | ||
1143 | vyres = info->var.yres_virtual; | ||
1144 | |||
1145 | if(!modded.width || !modded.height || | ||
1146 | modded.sx >= vxres || modded.sy >= vyres || | ||
1147 | modded.dx >= vxres || modded.dy >= vyres) | ||
1148 | return; | ||
1149 | |||
1150 | if(modded.sx + modded.width > vxres) | ||
1151 | modded.width = vxres - modded.sx; | ||
1152 | if(modded.dx + modded.width > vxres) | ||
1153 | modded.width = vxres - modded.dx; | ||
1154 | if(modded.sy + modded.height > vyres) | ||
1155 | modded.height = vyres - modded.sy; | ||
1156 | if(modded.dy + modded.height > vyres) | ||
1157 | modded.height = vyres - modded.dy; | ||
1158 | |||
1159 | pm2fb_block_op(par, 1, modded.sx, modded.sy, | ||
1160 | modded.dx, modded.dy, | ||
1161 | modded.width, modded.height, 0); | ||
1162 | } | ||
1163 | |||
1020 | /* ------------ Hardware Independent Functions ------------ */ | 1164 | /* ------------ Hardware Independent Functions ------------ */ |
1021 | 1165 | ||
1022 | /* | 1166 | /* |
@@ -1030,8 +1174,8 @@ static struct fb_ops pm2fb_ops = { | |||
1030 | .fb_setcolreg = pm2fb_setcolreg, | 1174 | .fb_setcolreg = pm2fb_setcolreg, |
1031 | .fb_blank = pm2fb_blank, | 1175 | .fb_blank = pm2fb_blank, |
1032 | .fb_pan_display = pm2fb_pan_display, | 1176 | .fb_pan_display = pm2fb_pan_display, |
1033 | .fb_fillrect = cfb_fillrect, | 1177 | .fb_fillrect = pm2fb_fillrect, |
1034 | .fb_copyarea = cfb_copyarea, | 1178 | .fb_copyarea = pm2fb_copyarea, |
1035 | .fb_imageblit = cfb_imageblit, | 1179 | .fb_imageblit = cfb_imageblit, |
1036 | }; | 1180 | }; |
1037 | 1181 | ||
@@ -1119,38 +1263,47 @@ static int __devinit pm2fb_probe(struct pci_dev *pdev, | |||
1119 | 1263 | ||
1120 | if(default_par->mem_control == 0 && | 1264 | if(default_par->mem_control == 0 && |
1121 | default_par->boot_address == 0x31 && | 1265 | default_par->boot_address == 0x31 && |
1122 | default_par->mem_config == 0x259fffff && | 1266 | default_par->mem_config == 0x259fffff) { |
1123 | pdev->subsystem_vendor == 0x1048 && | 1267 | default_par->memclock = CVPPC_MEMCLOCK; |
1124 | pdev->subsystem_device == 0x0a31) { | ||
1125 | DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n", | ||
1126 | pdev->subsystem_vendor, pdev->subsystem_device); | ||
1127 | DPRINTK("We have not been initialized by VGA BIOS " | ||
1128 | "and are running on an Elsa Winner 2000 Office\n"); | ||
1129 | DPRINTK("Initializing card timings manually...\n"); | ||
1130 | default_par->mem_control=0; | 1268 | default_par->mem_control=0; |
1131 | default_par->boot_address=0x20; | 1269 | default_par->boot_address=0x20; |
1132 | default_par->mem_config=0xe6002021; | 1270 | default_par->mem_config=0xe6002021; |
1133 | default_par->memclock=100000; | 1271 | if (pdev->subsystem_vendor == 0x1048 && |
1272 | pdev->subsystem_device == 0x0a31) { | ||
1273 | DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n", | ||
1274 | pdev->subsystem_vendor, pdev->subsystem_device); | ||
1275 | DPRINTK("We have not been initialized by VGA BIOS " | ||
1276 | "and are running on an Elsa Winner 2000 Office\n"); | ||
1277 | DPRINTK("Initializing card timings manually...\n"); | ||
1278 | default_par->memclock=70000; | ||
1279 | } | ||
1280 | if (pdev->subsystem_vendor == 0x3d3d && | ||
1281 | pdev->subsystem_device == 0x0100) { | ||
1282 | DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n", | ||
1283 | pdev->subsystem_vendor, pdev->subsystem_device); | ||
1284 | DPRINTK("We have not been initialized by VGA BIOS " | ||
1285 | "and are running on an 3dlabs reference board\n"); | ||
1286 | DPRINTK("Initializing card timings manually...\n"); | ||
1287 | default_par->memclock=74894; | ||
1288 | } | ||
1134 | } | 1289 | } |
1135 | 1290 | ||
1136 | /* Now work out how big lfb is going to be. */ | 1291 | /* Now work out how big lfb is going to be. */ |
1137 | switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) { | 1292 | switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) { |
1138 | case PM2F_MEM_BANKS_1: | 1293 | case PM2F_MEM_BANKS_1: |
1139 | default_par->fb_size=0x200000; | 1294 | pm2fb_fix.smem_len=0x200000; |
1140 | break; | 1295 | break; |
1141 | case PM2F_MEM_BANKS_2: | 1296 | case PM2F_MEM_BANKS_2: |
1142 | default_par->fb_size=0x400000; | 1297 | pm2fb_fix.smem_len=0x400000; |
1143 | break; | 1298 | break; |
1144 | case PM2F_MEM_BANKS_3: | 1299 | case PM2F_MEM_BANKS_3: |
1145 | default_par->fb_size=0x600000; | 1300 | pm2fb_fix.smem_len=0x600000; |
1146 | break; | 1301 | break; |
1147 | case PM2F_MEM_BANKS_4: | 1302 | case PM2F_MEM_BANKS_4: |
1148 | default_par->fb_size=0x800000; | 1303 | pm2fb_fix.smem_len=0x800000; |
1149 | break; | 1304 | break; |
1150 | } | 1305 | } |
1151 | default_par->memclock = CVPPC_MEMCLOCK; | ||
1152 | pm2fb_fix.smem_start = pci_resource_start(pdev, 1); | 1306 | pm2fb_fix.smem_start = pci_resource_start(pdev, 1); |
1153 | pm2fb_fix.smem_len = default_par->fb_size; | ||
1154 | 1307 | ||
1155 | /* Linear frame buffer - request region and map it. */ | 1308 | /* Linear frame buffer - request region and map it. */ |
1156 | if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len, | 1309 | if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len, |
@@ -1158,9 +1311,9 @@ static int __devinit pm2fb_probe(struct pci_dev *pdev, | |||
1158 | printk(KERN_WARNING "pm2fb: Can't reserve smem.\n"); | 1311 | printk(KERN_WARNING "pm2fb: Can't reserve smem.\n"); |
1159 | goto err_exit_mmio; | 1312 | goto err_exit_mmio; |
1160 | } | 1313 | } |
1161 | info->screen_base = default_par->v_fb = | 1314 | info->screen_base = |
1162 | ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len); | 1315 | ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len); |
1163 | if ( !default_par->v_fb ) { | 1316 | if ( !info->screen_base ) { |
1164 | printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n"); | 1317 | printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n"); |
1165 | release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); | 1318 | release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); |
1166 | goto err_exit_mmio; | 1319 | goto err_exit_mmio; |
@@ -1170,7 +1323,9 @@ static int __devinit pm2fb_probe(struct pci_dev *pdev, | |||
1170 | info->fix = pm2fb_fix; | 1323 | info->fix = pm2fb_fix; |
1171 | info->pseudo_palette = default_par->palette; | 1324 | info->pseudo_palette = default_par->palette; |
1172 | info->flags = FBINFO_DEFAULT | | 1325 | info->flags = FBINFO_DEFAULT | |
1173 | FBINFO_HWACCEL_YPAN; | 1326 | FBINFO_HWACCEL_YPAN | |
1327 | FBINFO_HWACCEL_COPYAREA | | ||
1328 | FBINFO_HWACCEL_FILLRECT; | ||
1174 | 1329 | ||
1175 | if (!mode) | 1330 | if (!mode) |
1176 | mode = "640x480@60"; | 1331 | mode = "640x480@60"; |
@@ -1180,13 +1335,13 @@ static int __devinit pm2fb_probe(struct pci_dev *pdev, | |||
1180 | info->var = pm2fb_var; | 1335 | info->var = pm2fb_var; |
1181 | 1336 | ||
1182 | if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) | 1337 | if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) |
1183 | goto err_exit_all; | 1338 | goto err_exit_both; |
1184 | 1339 | ||
1185 | if (register_framebuffer(info) < 0) | 1340 | if (register_framebuffer(info) < 0) |
1186 | goto err_exit_both; | 1341 | goto err_exit_all; |
1187 | 1342 | ||
1188 | printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n", | 1343 | printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n", |
1189 | info->node, info->fix.id, default_par->fb_size / 1024); | 1344 | info->node, info->fix.id, pm2fb_fix.smem_len / 1024); |
1190 | 1345 | ||
1191 | /* | 1346 | /* |
1192 | * Our driver data | 1347 | * Our driver data |
@@ -1242,6 +1397,9 @@ static struct pci_device_id pm2fb_id_table[] = { | |||
1242 | { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V, | 1397 | { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V, |
1243 | PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, | 1398 | PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, |
1244 | 0xff0000, 0 }, | 1399 | 0xff0000, 0 }, |
1400 | { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V, | ||
1401 | PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8, | ||
1402 | 0xff00, 0 }, | ||
1245 | { 0, } | 1403 | { 0, } |
1246 | }; | 1404 | }; |
1247 | 1405 | ||
diff --git a/drivers/video/ps3fb.c b/drivers/video/ps3fb.c index 07d1979bc23..9756a728b74 100644 --- a/drivers/video/ps3fb.c +++ b/drivers/video/ps3fb.c | |||
@@ -898,8 +898,8 @@ static int ps3fb_vsync_settings(struct gpu_driver_info *dinfo, void *dev) | |||
898 | } | 898 | } |
899 | 899 | ||
900 | ps3fb.dev = dev; | 900 | ps3fb.dev = dev; |
901 | error = ps3_alloc_irq(PS3_BINDING_CPU_ANY, dinfo->irq.irq_outlet, | 901 | error = ps3_irq_plug_setup(PS3_BINDING_CPU_ANY, dinfo->irq.irq_outlet, |
902 | &ps3fb.irq_no); | 902 | &ps3fb.irq_no); |
903 | if (error) { | 903 | if (error) { |
904 | printk(KERN_ERR "%s: ps3_alloc_irq failed %d\n", __func__, | 904 | printk(KERN_ERR "%s: ps3_alloc_irq failed %d\n", __func__, |
905 | error); | 905 | error); |
@@ -911,7 +911,7 @@ static int ps3fb_vsync_settings(struct gpu_driver_info *dinfo, void *dev) | |||
911 | if (error) { | 911 | if (error) { |
912 | printk(KERN_ERR "%s: request_irq failed %d\n", __func__, | 912 | printk(KERN_ERR "%s: request_irq failed %d\n", __func__, |
913 | error); | 913 | error); |
914 | ps3_free_irq(ps3fb.irq_no); | 914 | ps3_irq_plug_destroy(ps3fb.irq_no); |
915 | return error; | 915 | return error; |
916 | } | 916 | } |
917 | 917 | ||
@@ -1083,7 +1083,7 @@ err_framebuffer_release: | |||
1083 | framebuffer_release(info); | 1083 | framebuffer_release(info); |
1084 | err_free_irq: | 1084 | err_free_irq: |
1085 | free_irq(ps3fb.irq_no, ps3fb.dev); | 1085 | free_irq(ps3fb.irq_no, ps3fb.dev); |
1086 | ps3_free_irq(ps3fb.irq_no); | 1086 | ps3_irq_plug_destroy(ps3fb.irq_no); |
1087 | err_iounmap_dinfo: | 1087 | err_iounmap_dinfo: |
1088 | iounmap((u8 __iomem *)ps3fb.dinfo); | 1088 | iounmap((u8 __iomem *)ps3fb.dinfo); |
1089 | err_gpu_context_free: | 1089 | err_gpu_context_free: |
@@ -1099,7 +1099,7 @@ static void ps3fb_shutdown(struct platform_device *dev) | |||
1099 | ps3fb_flip_ctl(0); /* flip off */ | 1099 | ps3fb_flip_ctl(0); /* flip off */ |
1100 | ps3fb.dinfo->irq.mask = 0; | 1100 | ps3fb.dinfo->irq.mask = 0; |
1101 | free_irq(ps3fb.irq_no, ps3fb.dev); | 1101 | free_irq(ps3fb.irq_no, ps3fb.dev); |
1102 | ps3_free_irq(ps3fb.irq_no); | 1102 | ps3_irq_plug_destroy(ps3fb.irq_no); |
1103 | iounmap((u8 __iomem *)ps3fb.dinfo); | 1103 | iounmap((u8 __iomem *)ps3fb.dinfo); |
1104 | } | 1104 | } |
1105 | 1105 | ||
@@ -1114,7 +1114,7 @@ void ps3fb_cleanup(void) | |||
1114 | } | 1114 | } |
1115 | if (ps3fb.irq_no) { | 1115 | if (ps3fb.irq_no) { |
1116 | free_irq(ps3fb.irq_no, ps3fb.dev); | 1116 | free_irq(ps3fb.irq_no, ps3fb.dev); |
1117 | ps3_free_irq(ps3fb.irq_no); | 1117 | ps3_irq_plug_destroy(ps3fb.irq_no); |
1118 | } | 1118 | } |
1119 | iounmap((u8 __iomem *)ps3fb.dinfo); | 1119 | iounmap((u8 __iomem *)ps3fb.dinfo); |
1120 | 1120 | ||
diff --git a/drivers/video/pvr2fb.c b/drivers/video/pvr2fb.c index a93618bc9d2..df2909ae704 100644 --- a/drivers/video/pvr2fb.c +++ b/drivers/video/pvr2fb.c | |||
@@ -214,7 +214,7 @@ static int pvr2_init_cable(void); | |||
214 | static int pvr2_get_param(const struct pvr2_params *p, const char *s, | 214 | static int pvr2_get_param(const struct pvr2_params *p, const char *s, |
215 | int val, int size); | 215 | int val, int size); |
216 | #ifdef CONFIG_SH_DMA | 216 | #ifdef CONFIG_SH_DMA |
217 | static ssize_t pvr2fb_write(struct file *file, const char *buf, | 217 | static ssize_t pvr2fb_write(struct fb_info *info, const char *buf, |
218 | size_t count, loff_t *ppos); | 218 | size_t count, loff_t *ppos); |
219 | #endif | 219 | #endif |
220 | 220 | ||
@@ -674,7 +674,7 @@ static int pvr2_init_cable(void) | |||
674 | } | 674 | } |
675 | 675 | ||
676 | #ifdef CONFIG_SH_DMA | 676 | #ifdef CONFIG_SH_DMA |
677 | static ssize_t pvr2fb_write(struct file *file, const char *buf, | 677 | static ssize_t pvr2fb_write(struct fb_info *info, const char *buf, |
678 | size_t count, loff_t *ppos) | 678 | size_t count, loff_t *ppos) |
679 | { | 679 | { |
680 | unsigned long dst, start, end, len; | 680 | unsigned long dst, start, end, len; |
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 0b195f33f84..81e571d59b5 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c | |||
@@ -1203,7 +1203,7 @@ static int __init pxafb_parse_options(struct device *dev, char *options) | |||
1203 | } else | 1203 | } else |
1204 | goto done; | 1204 | goto done; |
1205 | break; | 1205 | break; |
1206 | case '0'...'9': | 1206 | case '0' ... '9': |
1207 | break; | 1207 | break; |
1208 | default: | 1208 | default: |
1209 | goto done; | 1209 | goto done; |
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c index d7ece8d17a2..0fe547842c6 100644 --- a/drivers/video/riva/fbdev.c +++ b/drivers/video/riva/fbdev.c | |||
@@ -317,15 +317,15 @@ static int riva_bl_update_status(struct backlight_device *bd) | |||
317 | else | 317 | else |
318 | level = bd->props.brightness; | 318 | level = bd->props.brightness; |
319 | 319 | ||
320 | tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF; | 320 | tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; |
321 | tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC; | 321 | tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC; |
322 | if(level > 0) { | 322 | if(level > 0) { |
323 | tmp_pcrt |= 0x1; | 323 | tmp_pcrt |= 0x1; |
324 | tmp_pmc |= (1 << 31); /* backlight bit */ | 324 | tmp_pmc |= (1 << 31); /* backlight bit */ |
325 | tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ | 325 | tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ |
326 | } | 326 | } |
327 | par->riva.PCRTC0[0x081C/4] = tmp_pcrt; | 327 | NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt); |
328 | par->riva.PMC[0x10F0/4] = tmp_pmc; | 328 | NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); |
329 | 329 | ||
330 | return 0; | 330 | return 0; |
331 | } | 331 | } |
@@ -1760,13 +1760,13 @@ static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) | |||
1760 | NVTRACE_ENTER(); | 1760 | NVTRACE_ENTER(); |
1761 | dp = pci_device_to_OF_node(pd); | 1761 | dp = pci_device_to_OF_node(pd); |
1762 | for (; dp != NULL; dp = dp->child) { | 1762 | for (; dp != NULL; dp = dp->child) { |
1763 | disptype = get_property(dp, "display-type", NULL); | 1763 | disptype = of_get_property(dp, "display-type", NULL); |
1764 | if (disptype == NULL) | 1764 | if (disptype == NULL) |
1765 | continue; | 1765 | continue; |
1766 | if (strncmp(disptype, "LCD", 3) != 0) | 1766 | if (strncmp(disptype, "LCD", 3) != 0) |
1767 | continue; | 1767 | continue; |
1768 | for (i = 0; propnames[i] != NULL; ++i) { | 1768 | for (i = 0; propnames[i] != NULL; ++i) { |
1769 | pedid = get_property(dp, propnames[i], NULL); | 1769 | pedid = of_get_property(dp, propnames[i], NULL); |
1770 | if (pedid != NULL) { | 1770 | if (pedid != NULL) { |
1771 | par->EDID = (unsigned char *)pedid; | 1771 | par->EDID = (unsigned char *)pedid; |
1772 | NVTRACE("LCD found.\n"); | 1772 | NVTRACE("LCD found.\n"); |
@@ -1788,8 +1788,10 @@ static int __devinit riva_get_EDID_i2c(struct fb_info *info) | |||
1788 | 1788 | ||
1789 | NVTRACE_ENTER(); | 1789 | NVTRACE_ENTER(); |
1790 | riva_create_i2c_busses(par); | 1790 | riva_create_i2c_busses(par); |
1791 | for (i = 0; i < par->bus; i++) { | 1791 | for (i = 0; i < 3; i++) { |
1792 | riva_probe_i2c_connector(par, i+1, &par->EDID); | 1792 | if (!par->chan[i].par) |
1793 | continue; | ||
1794 | riva_probe_i2c_connector(par, i, &par->EDID); | ||
1793 | if (par->EDID && !fb_parse_edid(par->EDID, &var)) { | 1795 | if (par->EDID && !fb_parse_edid(par->EDID, &var)) { |
1794 | printk(PFX "Found EDID Block from BUS %i\n", i); | 1796 | printk(PFX "Found EDID Block from BUS %i\n", i); |
1795 | break; | 1797 | break; |
@@ -2104,7 +2106,7 @@ err_ret: | |||
2104 | return ret; | 2106 | return ret; |
2105 | } | 2107 | } |
2106 | 2108 | ||
2107 | static void __exit rivafb_remove(struct pci_dev *pd) | 2109 | static void __devexit rivafb_remove(struct pci_dev *pd) |
2108 | { | 2110 | { |
2109 | struct fb_info *info = pci_get_drvdata(pd); | 2111 | struct fb_info *info = pci_get_drvdata(pd); |
2110 | struct riva_par *par = info->par; | 2112 | struct riva_par *par = info->par; |
@@ -2185,7 +2187,7 @@ static struct pci_driver rivafb_driver = { | |||
2185 | .name = "rivafb", | 2187 | .name = "rivafb", |
2186 | .id_table = rivafb_pci_tbl, | 2188 | .id_table = rivafb_pci_tbl, |
2187 | .probe = rivafb_probe, | 2189 | .probe = rivafb_probe, |
2188 | .remove = __exit_p(rivafb_remove), | 2190 | .remove = __devexit_p(rivafb_remove), |
2189 | }; | 2191 | }; |
2190 | 2192 | ||
2191 | 2193 | ||
diff --git a/drivers/video/riva/nv4ref.h b/drivers/video/riva/nv4ref.h deleted file mode 100644 index 3b5f9117c37..00000000000 --- a/drivers/video/riva/nv4ref.h +++ /dev/null | |||
@@ -1,2445 +0,0 @@ | |||
1 | /***************************************************************************\ | ||
2 | |* *| | ||
3 | |* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| | ||
4 | |* *| | ||
5 | |* NOTICE TO USER: The source code is copyrighted under U.S. and *| | ||
6 | |* international laws. Users and possessors of this source code are *| | ||
7 | |* hereby granted a nonexclusive, royalty-free copyright license to *| | ||
8 | |* use this code in individual and commercial software. *| | ||
9 | |* *| | ||
10 | |* Any use of this source code must include, in the user documenta- *| | ||
11 | |* tion and internal comments to the code, notices to the end user *| | ||
12 | |* as follows: *| | ||
13 | |* *| | ||
14 | |* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| | ||
15 | |* *| | ||
16 | |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| | ||
17 | |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| | ||
18 | |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| | ||
19 | |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| | ||
20 | |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| | ||
21 | |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| | ||
22 | |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| | ||
23 | |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| | ||
24 | |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| | ||
25 | |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| | ||
26 | |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| | ||
27 | |* *| | ||
28 | |* U.S. Government End Users. This source code is a "commercial *| | ||
29 | |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| | ||
30 | |* consisting of "commercial computer software" and "commercial *| | ||
31 | |* computer software documentation," as such terms are used in *| | ||
32 | |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| | ||
33 | |* ment only as a commercial end item. Consistent with 48 C.F.R. *| | ||
34 | |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| | ||
35 | |* all U.S. Government End Users acquire the source code with only *| | ||
36 | |* those rights set forth herein. *| | ||
37 | |* *| | ||
38 | \***************************************************************************/ | ||
39 | |||
40 | /* | ||
41 | * GPL licensing note -- nVidia is allowing a liberal interpretation of | ||
42 | * the documentation restriction above, to merely say that this nVidia's | ||
43 | * copyright and disclaimer should be included with all code derived | ||
44 | * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 | ||
45 | */ | ||
46 | |||
47 | /***************************************************************************\ | ||
48 | |* Modified 1999 by Fredrik Reite (fredrik@reite.com) *| | ||
49 | \***************************************************************************/ | ||
50 | |||
51 | |||
52 | #ifndef __NV4REF_H__ | ||
53 | #define __NV4REF_H__ | ||
54 | |||
55 | /* Magic values to lock/unlock extended regs */ | ||
56 | #define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */ | ||
57 | #define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */ | ||
58 | #define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */ | ||
59 | #define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */ | ||
60 | |||
61 | #define UNLOCK_EXT_MAGIC 0x57 | ||
62 | #define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */ | ||
63 | |||
64 | #define LOCK_EXT_INDEX 0x6 | ||
65 | |||
66 | #define NV_PCRTC_HORIZ_TOTAL 0x00 | ||
67 | #define NV_PCRTC_HORIZ_DISPLAY_END 0x01 | ||
68 | #define NV_PCRTC_HORIZ_BLANK_START 0x02 | ||
69 | |||
70 | #define NV_PCRTC_HORIZ_BLANK_END 0x03 | ||
71 | #define NV_PCRTC_HORIZ_BLANK_END_EVRA 7:7 | ||
72 | #define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW 6:5 | ||
73 | #define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END 4:0 | ||
74 | |||
75 | #define NV_PCRTC_HORIZ_RETRACE_START 0x04 | ||
76 | |||
77 | #define NV_PCRTC_HORIZ_RETRACE_END 0x05 | ||
78 | #define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5 7:7 | ||
79 | #define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW 6:5 | ||
80 | #define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END 4:0 | ||
81 | |||
82 | #define NV_PCRTC_VERT_TOTAL 0x06 | ||
83 | |||
84 | #define NV_PCRTC_OVERFLOW 0x07 | ||
85 | #define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9 7:7 | ||
86 | #define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9 6:6 | ||
87 | #define NV_PCRTC_OVERFLOW_VERT_TOTAL_9 5:5 | ||
88 | #define NV_PCRTC_OVERFLOW_LINE_COMPARE_8 4:4 | ||
89 | #define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8 3:3 | ||
90 | #define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8 2:2 | ||
91 | #define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8 1:1 | ||
92 | #define NV_PCRTC_OVERFLOW_VERT_TOTAL_8 0:0 | ||
93 | |||
94 | #define NV_PCRTC_PRESET_ROW_SCAN 0x08 | ||
95 | |||
96 | #define NV_PCRTC_MAX_SCAN_LINE 0x09 | ||
97 | #define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN 7:7 | ||
98 | #define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9 6:6 | ||
99 | #define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9 5:5 | ||
100 | #define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE 4:0 | ||
101 | |||
102 | #define NV_PCRTC_CURSOR_START 0x0A | ||
103 | #define NV_PCRTC_CURSOR_END 0x0B | ||
104 | #define NV_PCRTC_START_ADDR_HIGH 0x0C | ||
105 | #define NV_PCRTC_START_ADDR_LOW 0x0D | ||
106 | #define NV_PCRTC_CURSOR_LOCATION_HIGH 0x0E | ||
107 | #define NV_PCRTC_CURSOR_LOCATION_LOW 0x0F | ||
108 | |||
109 | #define NV_PCRTC_VERT_RETRACE_START 0x10 | ||
110 | #define NV_PCRTC_VERT_RETRACE_END 0x11 | ||
111 | #define NV_PCRTC_VERT_DISPLAY_END 0x12 | ||
112 | #define NV_PCRTC_OFFSET 0x13 | ||
113 | #define NV_PCRTC_UNDERLINE_LOCATION 0x14 | ||
114 | #define NV_PCRTC_VERT_BLANK_START 0x15 | ||
115 | #define NV_PCRTC_VERT_BLANK_END 0x16 | ||
116 | #define NV_PCRTC_MODE_CONTROL 0x17 | ||
117 | #define NV_PCRTC_LINE_COMPARE 0x18 | ||
118 | |||
119 | /* Extended offset and start address */ | ||
120 | #define NV_PCRTC_REPAINT0 0x19 | ||
121 | #define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5 | ||
122 | #define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0 | ||
123 | |||
124 | /* Horizonal extended bits */ | ||
125 | #define NV_PCRTC_HORIZ_EXTRA 0x2d | ||
126 | #define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4 | ||
127 | #define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3 | ||
128 | #define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2 | ||
129 | #define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1 | ||
130 | #define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0 | ||
131 | |||
132 | /* Assorted extra bits */ | ||
133 | #define NV_PCRTC_EXTRA 0x25 | ||
134 | #define NV_PCRTC_EXTRA_OFFSET_11 5:5 | ||
135 | #define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4 | ||
136 | #define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3 | ||
137 | #define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2 | ||
138 | #define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1 | ||
139 | #define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0 | ||
140 | |||
141 | /* Controls how much data the refresh fifo requests */ | ||
142 | #define NV_PCRTC_FIFO_CONTROL 0x1b | ||
143 | #define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7 | ||
144 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0 | ||
145 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0 | ||
146 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1 | ||
147 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2 | ||
148 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3 | ||
149 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4 | ||
150 | |||
151 | /* When the fifo occupancy falls below *twice* the watermark, | ||
152 | * the refresh fifo will start to be refilled. If this value is | ||
153 | * too low, you will get junk on the screen. Too high, and performance | ||
154 | * will suffer. Watermark in units of 8 bytes | ||
155 | */ | ||
156 | #define NV_PCRTC_FIFO 0x20 | ||
157 | #define NV_PCRTC_FIFO_RESET 7:7 | ||
158 | #define NV_PCRTC_FIFO_WATERMARK 5:0 | ||
159 | |||
160 | /* Various flags */ | ||
161 | #define NV_PCRTC_REPAINT1 0x1a | ||
162 | #define NV_PCRTC_REPAINT1_HSYNC 7:7 | ||
163 | #define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01 | ||
164 | #define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00 | ||
165 | #define NV_PCRTC_REPAINT1_VSYNC 6:6 | ||
166 | #define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01 | ||
167 | #define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00 | ||
168 | #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4 | ||
169 | #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01 | ||
170 | #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00 | ||
171 | #define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2 | ||
172 | #define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01 | ||
173 | #define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */ | ||
174 | #define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1 | ||
175 | #define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00 | ||
176 | #define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01 | ||
177 | |||
178 | #define NV_PCRTC_GRCURSOR0 0x30 | ||
179 | #define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0 | ||
180 | |||
181 | #define NV_PCRTC_GRCURSOR1 0x31 | ||
182 | #define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3 | ||
183 | #define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1 | ||
184 | #define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0 | ||
185 | #define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1 | ||
186 | #define NV_PCRTC_GRCURSOR1_CURSOR 0:0 | ||
187 | #define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0 | ||
188 | #define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1 | ||
189 | |||
190 | /* Controls what the format of the framebuffer is */ | ||
191 | #define NV_PCRTC_PIXEL 0x28 | ||
192 | #define NV_PCRTC_PIXEL_MODE 7:7 | ||
193 | #define NV_PCRTC_PIXEL_MODE_TV 0x01 | ||
194 | #define NV_PCRTC_PIXEL_MODE_VGA 0x00 | ||
195 | #define NV_PCRTC_PIXEL_TV_MODE 6:6 | ||
196 | #define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00 | ||
197 | #define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01 | ||
198 | #define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3 | ||
199 | #define NV_PCRTC_PIXEL_FORMAT 1:0 | ||
200 | #define NV_PCRTC_PIXEL_FORMAT_VGA 0x00 | ||
201 | #define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01 | ||
202 | #define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02 | ||
203 | #define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03 | ||
204 | |||
205 | /* RAMDAC registers and fields */ | ||
206 | #define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */ | ||
207 | #define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */ | ||
208 | #define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */ | ||
209 | #define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */ | ||
210 | #define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */ | ||
211 | #define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */ | ||
212 | #define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */ | ||
213 | #define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */ | ||
214 | #define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */ | ||
215 | #define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */ | ||
216 | #define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */ | ||
217 | #define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */ | ||
218 | #define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */ | ||
219 | #define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */ | ||
220 | #define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */ | ||
221 | #define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */ | ||
222 | #define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */ | ||
223 | #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */ | ||
224 | #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */ | ||
225 | #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */ | ||
226 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */ | ||
227 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ | ||
228 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */ | ||
229 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */ | ||
230 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ | ||
231 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */ | ||
232 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */ | ||
233 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ | ||
234 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */ | ||
235 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */ | ||
236 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ | ||
237 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */ | ||
238 | #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */ | ||
239 | #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */ | ||
240 | #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */ | ||
241 | #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */ | ||
242 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */ | ||
243 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */ | ||
244 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */ | ||
245 | #define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */ | ||
246 | #define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */ | ||
247 | #define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */ | ||
248 | #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */ | ||
249 | #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */ | ||
250 | #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */ | ||
251 | #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */ | ||
252 | #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */ | ||
253 | #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */ | ||
254 | #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */ | ||
255 | #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */ | ||
256 | #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */ | ||
257 | #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */ | ||
258 | #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */ | ||
259 | #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */ | ||
260 | #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */ | ||
261 | #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */ | ||
262 | #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */ | ||
263 | #define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */ | ||
264 | #define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */ | ||
265 | #define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */ | ||
266 | #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */ | ||
267 | #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */ | ||
268 | #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */ | ||
269 | #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */ | ||
270 | #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */ | ||
271 | #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */ | ||
272 | |||
273 | /* Master Control */ | ||
274 | #define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ | ||
275 | #define NV_PMC_BOOT_0 0x00000000 /* R--4R */ | ||
276 | #define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */ | ||
277 | #define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */ | ||
278 | #define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */ | ||
279 | #define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */ | ||
280 | #define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */ | ||
281 | #define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */ | ||
282 | #define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */ | ||
283 | #define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */ | ||
284 | #define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */ | ||
285 | #define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */ | ||
286 | #define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */ | ||
287 | #define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */ | ||
288 | #define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* C---V */ | ||
289 | #define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */ | ||
290 | #define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */ | ||
291 | #define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */ | ||
292 | #define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */ | ||
293 | #define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */ | ||
294 | #define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */ | ||
295 | #define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */ | ||
296 | #define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */ | ||
297 | #define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */ | ||
298 | #define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */ | ||
299 | #define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */ | ||
300 | #define NV_PMC_INTR_0 0x00000100 /* RW-4R */ | ||
301 | #define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */ | ||
302 | #define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */ | ||
303 | #define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */ | ||
304 | #define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ | ||
305 | #define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ | ||
306 | #define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ | ||
307 | #define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */ | ||
308 | #define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */ | ||
309 | #define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */ | ||
310 | #define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */ | ||
311 | #define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */ | ||
312 | #define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */ | ||
313 | #define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ | ||
314 | #define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ | ||
315 | #define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ | ||
316 | #define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */ | ||
317 | #define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */ | ||
318 | #define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */ | ||
319 | #define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */ | ||
320 | #define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */ | ||
321 | #define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */ | ||
322 | #define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */ | ||
323 | #define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ | ||
324 | #define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ | ||
325 | #define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */ | ||
326 | #define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */ | ||
327 | #define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */ | ||
328 | #define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */ | ||
329 | #define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */ | ||
330 | #define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */ | ||
331 | #define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */ | ||
332 | #define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */ | ||
333 | #define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */ | ||
334 | #define NV_PMC_ENABLE 0x00000200 /* RW-4R */ | ||
335 | #define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */ | ||
336 | #define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */ | ||
337 | #define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */ | ||
338 | #define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ | ||
339 | #define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ | ||
340 | #define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ | ||
341 | #define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */ | ||
342 | #define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */ | ||
343 | #define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */ | ||
344 | #define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */ | ||
345 | #define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */ | ||
346 | #define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */ | ||
347 | #define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */ | ||
348 | #define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */ | ||
349 | #define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */ | ||
350 | #define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */ | ||
351 | #define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */ | ||
352 | #define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */ | ||
353 | #define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */ | ||
354 | #define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */ | ||
355 | #define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */ | ||
356 | |||
357 | /* dev_timer.ref */ | ||
358 | #define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */ | ||
359 | #define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */ | ||
360 | #define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */ | ||
361 | #define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */ | ||
362 | #define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */ | ||
363 | #define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */ | ||
364 | #define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */ | ||
365 | #define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */ | ||
366 | #define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */ | ||
367 | #define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */ | ||
368 | #define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */ | ||
369 | #define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */ | ||
370 | #define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */ | ||
371 | #define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */ | ||
372 | #define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */ | ||
373 | #define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */ | ||
374 | #define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */ | ||
375 | #define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */ | ||
376 | #define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */ | ||
377 | #define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */ | ||
378 | #define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */ | ||
379 | #define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */ | ||
380 | |||
381 | /* dev_fifo.ref */ | ||
382 | #define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ | ||
383 | #define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */ | ||
384 | #define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */ | ||
385 | #define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */ | ||
386 | #define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */ | ||
387 | #define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */ | ||
388 | #define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ | ||
389 | #define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ | ||
390 | #define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ | ||
391 | #define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ | ||
392 | #define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ | ||
393 | #define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ | ||
394 | #define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ | ||
395 | #define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ | ||
396 | #define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */ | ||
397 | #define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */ | ||
398 | #define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ | ||
399 | #define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ | ||
400 | #define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ | ||
401 | #define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ | ||
402 | #define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ | ||
403 | #define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ | ||
404 | #define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ | ||
405 | #define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ | ||
406 | #define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */ | ||
407 | #define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */ | ||
408 | #define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */ | ||
409 | #define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */ | ||
410 | #define NV_PFIFO_NEXT_CHANNEL_CHID 3:0 /* RWXUF */ | ||
411 | #define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */ | ||
412 | #define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */ | ||
413 | #define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */ | ||
414 | #define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */ | ||
415 | #define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */ | ||
416 | #define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */ | ||
417 | #define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */ | ||
418 | #define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */ | ||
419 | #define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */ | ||
420 | #define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */ | ||
421 | #define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */ | ||
422 | #define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */ | ||
423 | #define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */ | ||
424 | #define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ | ||
425 | #define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ | ||
426 | #define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ | ||
427 | #define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ | ||
428 | #define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ | ||
429 | #define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ | ||
430 | #define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ | ||
431 | #define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ | ||
432 | #define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ | ||
433 | #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ | ||
434 | #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ | ||
435 | #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ | ||
436 | #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ | ||
437 | #define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */ | ||
438 | #define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */ | ||
439 | #define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */ | ||
440 | #define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */ | ||
441 | #define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */ | ||
442 | #define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */ | ||
443 | #define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */ | ||
444 | #define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */ | ||
445 | #define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ | ||
446 | #define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ | ||
447 | #define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ | ||
448 | #define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ | ||
449 | #define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ | ||
450 | #define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ | ||
451 | #define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ | ||
452 | #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ | ||
453 | #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ | ||
454 | #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ | ||
455 | #define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */ | ||
456 | #define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */ | ||
457 | #define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */ | ||
458 | #define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */ | ||
459 | #define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */ | ||
460 | #define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */ | ||
461 | #define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */ | ||
462 | #define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */ | ||
463 | #define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */ | ||
464 | #define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */ | ||
465 | #define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */ | ||
466 | #define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */ | ||
467 | #define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */ | ||
468 | #define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */ | ||
469 | #define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */ | ||
470 | #define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */ | ||
471 | #define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */ | ||
472 | #define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */ | ||
473 | #define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */ | ||
474 | #define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */ | ||
475 | #define NV_PFIFO_RAMFC_BASE_ADDRESS 8:1 /* RWIUF */ | ||
476 | #define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000088 /* RWI-V */ | ||
477 | #define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */ | ||
478 | #define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */ | ||
479 | #define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RWI-V */ | ||
480 | #define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */ | ||
481 | #define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */ | ||
482 | #define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */ | ||
483 | #define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */ | ||
484 | #define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ | ||
485 | #define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ | ||
486 | #define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ | ||
487 | #define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ | ||
488 | #define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */ | ||
489 | #define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */ | ||
490 | #define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */ | ||
491 | #define NV_PFIFO_MODE 0x00002504 /* RW-4R */ | ||
492 | #define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */ | ||
493 | #define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */ | ||
494 | #define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */ | ||
495 | #define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */ | ||
496 | #define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */ | ||
497 | #define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */ | ||
498 | #define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */ | ||
499 | #define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */ | ||
500 | #define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */ | ||
501 | #define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */ | ||
502 | #define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */ | ||
503 | #define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */ | ||
504 | #define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */ | ||
505 | #define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */ | ||
506 | #define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */ | ||
507 | #define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */ | ||
508 | #define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */ | ||
509 | #define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */ | ||
510 | #define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */ | ||
511 | #define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */ | ||
512 | #define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */ | ||
513 | #define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */ | ||
514 | #define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */ | ||
515 | #define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */ | ||
516 | #define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */ | ||
517 | #define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */ | ||
518 | #define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */ | ||
519 | #define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */ | ||
520 | #define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */ | ||
521 | #define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */ | ||
522 | #define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */ | ||
523 | #define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */ | ||
524 | #define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */ | ||
525 | #define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */ | ||
526 | #define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */ | ||
527 | #define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */ | ||
528 | #define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */ | ||
529 | #define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */ | ||
530 | #define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */ | ||
531 | #define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */ | ||
532 | #define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */ | ||
533 | #define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */ | ||
534 | #define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */ | ||
535 | #define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */ | ||
536 | #define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */ | ||
537 | #define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */ | ||
538 | #define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */ | ||
539 | #define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */ | ||
540 | #define NV_PFIFO_DMA 0x00002508 /* RW-4R */ | ||
541 | #define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */ | ||
542 | #define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */ | ||
543 | #define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */ | ||
544 | #define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */ | ||
545 | #define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */ | ||
546 | #define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */ | ||
547 | #define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */ | ||
548 | #define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */ | ||
549 | #define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */ | ||
550 | #define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */ | ||
551 | #define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */ | ||
552 | #define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */ | ||
553 | #define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */ | ||
554 | #define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */ | ||
555 | #define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */ | ||
556 | #define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */ | ||
557 | #define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */ | ||
558 | #define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */ | ||
559 | #define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */ | ||
560 | #define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */ | ||
561 | #define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */ | ||
562 | #define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */ | ||
563 | #define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */ | ||
564 | #define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */ | ||
565 | #define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */ | ||
566 | #define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */ | ||
567 | #define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */ | ||
568 | #define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */ | ||
569 | #define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */ | ||
570 | #define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */ | ||
571 | #define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */ | ||
572 | #define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */ | ||
573 | #define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */ | ||
574 | #define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */ | ||
575 | #define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */ | ||
576 | #define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */ | ||
577 | #define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */ | ||
578 | #define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */ | ||
579 | #define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */ | ||
580 | #define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */ | ||
581 | #define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */ | ||
582 | #define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */ | ||
583 | #define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */ | ||
584 | #define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */ | ||
585 | #define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */ | ||
586 | #define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */ | ||
587 | #define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */ | ||
588 | #define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */ | ||
589 | #define NV_PFIFO_SIZE 0x0000250C /* RW-4R */ | ||
590 | #define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */ | ||
591 | #define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */ | ||
592 | #define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */ | ||
593 | #define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */ | ||
594 | #define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */ | ||
595 | #define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */ | ||
596 | #define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */ | ||
597 | #define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */ | ||
598 | #define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */ | ||
599 | #define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */ | ||
600 | #define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */ | ||
601 | #define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */ | ||
602 | #define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */ | ||
603 | #define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */ | ||
604 | #define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */ | ||
605 | #define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */ | ||
606 | #define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */ | ||
607 | #define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */ | ||
608 | #define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */ | ||
609 | #define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */ | ||
610 | #define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */ | ||
611 | #define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */ | ||
612 | #define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */ | ||
613 | #define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */ | ||
614 | #define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */ | ||
615 | #define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */ | ||
616 | #define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */ | ||
617 | #define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */ | ||
618 | #define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */ | ||
619 | #define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */ | ||
620 | #define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */ | ||
621 | #define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */ | ||
622 | #define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */ | ||
623 | #define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */ | ||
624 | #define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */ | ||
625 | #define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */ | ||
626 | #define NV_PFIFO_SIZE_CHANNEL_12 12:12 /* RWIVF */ | ||
627 | #define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES 0x00000000 /* RWI-V */ | ||
628 | #define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES 0x00000001 /* RW--V */ | ||
629 | #define NV_PFIFO_SIZE_CHANNEL_13 13:13 /* RWIVF */ | ||
630 | #define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES 0x00000000 /* RWI-V */ | ||
631 | #define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES 0x00000001 /* RW--V */ | ||
632 | #define NV_PFIFO_SIZE_CHANNEL_14 14:14 /* RWIVF */ | ||
633 | #define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES 0x00000000 /* RWI-V */ | ||
634 | #define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES 0x00000001 /* RW--V */ | ||
635 | #define NV_PFIFO_SIZE_CHANNEL_15 15:15 /* RWIVF */ | ||
636 | #define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES 0x00000000 /* RWI-V */ | ||
637 | #define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES 0x00000001 /* RW--V */ | ||
638 | #define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */ | ||
639 | #define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */ | ||
640 | #define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ | ||
641 | #define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ | ||
642 | #define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */ | ||
643 | #define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */ | ||
644 | #define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ | ||
645 | #define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ | ||
646 | #define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */ | ||
647 | #define NV_PFIFO_CACHE0_PUSH1_CHID 3:0 /* RWXUF */ | ||
648 | #define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */ | ||
649 | #define NV_PFIFO_CACHE1_PUSH1_CHID 3:0 /* RWXUF */ | ||
650 | #define NV_PFIFO_CACHE1_PUSH1_MODE 8:8 /* RWIVF */ | ||
651 | #define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 /* RWI-V */ | ||
652 | #define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000001 /* RW--V */ | ||
653 | #define NV_PFIFO_CACHE1_DMA_PUSH 0x00003220 /* RW-4R */ | ||
654 | #define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS 0:0 /* RWIVF */ | ||
655 | #define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 /* RWI-V */ | ||
656 | #define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 /* RW--V */ | ||
657 | #define NV_PFIFO_CACHE1_DMA_PUSH_STATE 4:4 /* R--VF */ | ||
658 | #define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 /* R---V */ | ||
659 | #define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000001 /* R---V */ | ||
660 | #define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER 8:8 /* R--VF */ | ||
661 | #define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 /* R---V */ | ||
662 | #define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000001 /* R---V */ | ||
663 | #define NV_PFIFO_CACHE1_DMA_PUSH_STATUS 12:12 /* RWIVF */ | ||
664 | #define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 /* RWI-V */ | ||
665 | #define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00000001 /* RW--V */ | ||
666 | #define NV_PFIFO_CACHE1_DMA_FETCH 0x00003224 /* RW-4R */ | ||
667 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 /* RWIUF */ | ||
668 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 /* RW--V */ | ||
669 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000001 /* RW--V */ | ||
670 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000002 /* RW--V */ | ||
671 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000003 /* RW--V */ | ||
672 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000004 /* RW--V */ | ||
673 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000005 /* RW--V */ | ||
674 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000006 /* RW--V */ | ||
675 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000007 /* RW--V */ | ||
676 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000008 /* RW--V */ | ||
677 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000009 /* RW--V */ | ||
678 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000000A /* RW--V */ | ||
679 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000000B /* RW--V */ | ||
680 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000000C /* RW--V */ | ||
681 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000000D /* RW--V */ | ||
682 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000000E /* RW--V */ | ||
683 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000000F /* RWI-V */ | ||
684 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000010 /* RW--V */ | ||
685 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000011 /* RW--V */ | ||
686 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000012 /* RW--V */ | ||
687 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000013 /* RW--V */ | ||
688 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x00000014 /* RW--V */ | ||
689 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x00000015 /* RW--V */ | ||
690 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x00000016 /* RW--V */ | ||
691 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x00000017 /* RW--V */ | ||
692 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x00000018 /* RW--V */ | ||
693 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x00000019 /* RW--V */ | ||
694 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x0000001A /* RW--V */ | ||
695 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x0000001B /* RW--V */ | ||
696 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x0000001C /* RW--V */ | ||
697 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x0000001D /* RW--V */ | ||
698 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x0000001E /* RW--V */ | ||
699 | #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x0000001F /* RW--V */ | ||
700 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 15:13 /* RWIUF */ | ||
701 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 /* RW--V */ | ||
702 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00000001 /* RW--V */ | ||
703 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00000002 /* RW--V */ | ||
704 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00000003 /* RWI-V */ | ||
705 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00000004 /* RW--V */ | ||
706 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x00000005 /* RW--V */ | ||
707 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x00000006 /* RW--V */ | ||
708 | #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x00000007 /* RW--V */ | ||
709 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 19:16 /* RWIUF */ | ||
710 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 /* RWI-V */ | ||
711 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00000001 /* RW--V */ | ||
712 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00000002 /* RW--V */ | ||
713 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00000003 /* RW--V */ | ||
714 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00000004 /* RW--V */ | ||
715 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00000005 /* RW--V */ | ||
716 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00000006 /* RW--V */ | ||
717 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00000007 /* RW--V */ | ||
718 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00000008 /* RW--V */ | ||
719 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00000009 /* RW--V */ | ||
720 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x0000000A /* RW--V */ | ||
721 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x0000000B /* RW--V */ | ||
722 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x0000000C /* RW--V */ | ||
723 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x0000000D /* RW--V */ | ||
724 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x0000000E /* RW--V */ | ||
725 | #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x0000000F /* RW--V */ | ||
726 | #define NV_PFIFO_CACHE1_DMA_PUT 0x00003240 /* RW-4R */ | ||
727 | #define NV_PFIFO_CACHE1_DMA_PUT_OFFSET 28:2 /* RWXUF */ | ||
728 | #define NV_PFIFO_CACHE1_DMA_GET 0x00003244 /* RW-4R */ | ||
729 | #define NV_PFIFO_CACHE1_DMA_GET_OFFSET 28:2 /* RWXUF */ | ||
730 | #define NV_PFIFO_CACHE1_DMA_STATE 0x00003228 /* RW-4R */ | ||
731 | #define NV_PFIFO_CACHE1_DMA_STATE_METHOD 12:2 /* RWXUF */ | ||
732 | #define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 15:13 /* RWXUF */ | ||
733 | #define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 28:18 /* RWIUF */ | ||
734 | #define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x00000000 /* RWI-V */ | ||
735 | #define NV_PFIFO_CACHE1_DMA_STATE_ERROR 31:30 /* RWXUF */ | ||
736 | #define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 /* RW--V */ | ||
737 | #define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x00000001 /* RW--V */ | ||
738 | #define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x00000002 /* RW--V */ | ||
739 | #define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x00000003 /* RW--V */ | ||
740 | #define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000322C /* RW-4R */ | ||
741 | #define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 15:0 /* RWXUF */ | ||
742 | #define NV_PFIFO_CACHE1_DMA_CTL 0x00003230 /* RW-4R */ | ||
743 | #define NV_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 /* RWXUF */ | ||
744 | #define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12:12 /* RWXUF */ | ||
745 | #define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */ | ||
746 | #define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ | ||
747 | #define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13:13 /* RWXUF */ | ||
748 | #define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ | ||
749 | #define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ | ||
750 | #define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 17:16 /* RWXUF */ | ||
751 | #define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00000002 /* RW--V */ | ||
752 | #define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00000003 /* RW--V */ | ||
753 | #define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO 31:31 /* RWIUF */ | ||
754 | #define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 /* RW--V */ | ||
755 | #define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x00000001 /* RWI-V */ | ||
756 | #define NV_PFIFO_CACHE1_DMA_LIMIT 0x00003234 /* RW-4R */ | ||
757 | #define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET 28:2 /* RWXUF */ | ||
758 | #define NV_PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 /* RW-4R */ | ||
759 | #define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 /* RWXUF */ | ||
760 | #define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0:0 /* RWIUF */ | ||
761 | #define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 /* RWI-V */ | ||
762 | #define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 /* RW--V */ | ||
763 | #define NV_PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C /* RW-4R */ | ||
764 | #define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ | ||
765 | #define NV_PFIFO_CACHE0_PULL0 0x00003050 /* RW-4R */ | ||
766 | #define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */ | ||
767 | #define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ | ||
768 | #define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ | ||
769 | #define NV_PFIFO_CACHE0_PULL0_HASH 4:4 /* R-XVF */ | ||
770 | #define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ | ||
771 | #define NV_PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000001 /* R---V */ | ||
772 | #define NV_PFIFO_CACHE0_PULL0_DEVICE 8:8 /* R-XVF */ | ||
773 | #define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ | ||
774 | #define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ | ||
775 | #define NV_PFIFO_CACHE0_PULL0_HASH_STATE 12:12 /* R-XVF */ | ||
776 | #define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ | ||
777 | #define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ | ||
778 | #define NV_PFIFO_CACHE1_PULL0 0x00003250 /* RW-4R */ | ||
779 | #define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */ | ||
780 | #define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ | ||
781 | #define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ | ||
782 | #define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */ | ||
783 | #define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ | ||
784 | #define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */ | ||
785 | #define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */ | ||
786 | #define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ | ||
787 | #define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ | ||
788 | #define NV_PFIFO_CACHE1_PULL0_HASH_STATE 12:12 /* R-XVF */ | ||
789 | #define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ | ||
790 | #define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ | ||
791 | #define NV_PFIFO_CACHE0_PULL1 0x00003054 /* RW-4R */ | ||
792 | #define NV_PFIFO_CACHE0_PULL1_ENGINE 1:0 /* RWXUF */ | ||
793 | #define NV_PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 /* RW--V */ | ||
794 | #define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ | ||
795 | #define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ | ||
796 | #define NV_PFIFO_CACHE1_PULL1 0x00003254 /* RW-4R */ | ||
797 | #define NV_PFIFO_CACHE1_PULL1_ENGINE 1:0 /* RWXUF */ | ||
798 | #define NV_PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 /* RW--V */ | ||
799 | #define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ | ||
800 | #define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ | ||
801 | #define NV_PFIFO_CACHE0_HASH 0x00003058 /* RW-4R */ | ||
802 | #define NV_PFIFO_CACHE0_HASH_INSTANCE 15:0 /* RWXUF */ | ||
803 | #define NV_PFIFO_CACHE0_HASH_VALID 16:16 /* RWXVF */ | ||
804 | #define NV_PFIFO_CACHE1_HASH 0x00003258 /* RW-4R */ | ||
805 | #define NV_PFIFO_CACHE1_HASH_INSTANCE 15:0 /* RWXUF */ | ||
806 | #define NV_PFIFO_CACHE1_HASH_VALID 16:16 /* RWXVF */ | ||
807 | #define NV_PFIFO_CACHE0_STATUS 0x00003014 /* R--4R */ | ||
808 | #define NV_PFIFO_CACHE0_STATUS_LOW_MARK 4:4 /* R--VF */ | ||
809 | #define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ | ||
810 | #define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ | ||
811 | #define NV_PFIFO_CACHE0_STATUS_HIGH_MARK 8:8 /* R--VF */ | ||
812 | #define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ | ||
813 | #define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ | ||
814 | #define NV_PFIFO_CACHE1_STATUS 0x00003214 /* R--4R */ | ||
815 | #define NV_PFIFO_CACHE1_STATUS_LOW_MARK 4:4 /* R--VF */ | ||
816 | #define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ | ||
817 | #define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ | ||
818 | #define NV_PFIFO_CACHE1_STATUS_HIGH_MARK 8:8 /* R--VF */ | ||
819 | #define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ | ||
820 | #define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ | ||
821 | #define NV_PFIFO_CACHE1_STATUS1 0x00003218 /* R--4R */ | ||
822 | #define NV_PFIFO_CACHE1_STATUS1_RANOUT 0:0 /* R-XVF */ | ||
823 | #define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 /* R---V */ | ||
824 | #define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 /* R---V */ | ||
825 | #define NV_PFIFO_CACHE0_PUT 0x00003010 /* RW-4R */ | ||
826 | #define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */ | ||
827 | #define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */ | ||
828 | #define NV_PFIFO_CACHE1_PUT_ADDRESS 9:2 /* RWXUF */ | ||
829 | #define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */ | ||
830 | #define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */ | ||
831 | #define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */ | ||
832 | #define NV_PFIFO_CACHE1_GET_ADDRESS 9:2 /* RWXUF */ | ||
833 | #define NV_PFIFO_CACHE0_ENGINE 0x00003080 /* RW-4R */ | ||
834 | #define NV_PFIFO_CACHE0_ENGINE_0 1:0 /* RWXUF */ | ||
835 | #define NV_PFIFO_CACHE0_ENGINE_0_SW 0x00000000 /* RW--V */ | ||
836 | #define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ | ||
837 | #define NV_PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 /* RW--V */ | ||
838 | #define NV_PFIFO_CACHE0_ENGINE_1 5:4 /* RWXUF */ | ||
839 | #define NV_PFIFO_CACHE0_ENGINE_1_SW 0x00000000 /* RW--V */ | ||
840 | #define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ | ||
841 | #define NV_PFIFO_CACHE0_ENGINE_1_DVD 0x00000002 /* RW--V */ | ||
842 | #define NV_PFIFO_CACHE0_ENGINE_2 9:8 /* RWXUF */ | ||
843 | #define NV_PFIFO_CACHE0_ENGINE_2_SW 0x00000000 /* RW--V */ | ||
844 | #define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ | ||
845 | #define NV_PFIFO_CACHE0_ENGINE_2_DVD 0x00000002 /* RW--V */ | ||
846 | #define NV_PFIFO_CACHE0_ENGINE_3 13:12 /* RWXUF */ | ||
847 | #define NV_PFIFO_CACHE0_ENGINE_3_SW 0x00000000 /* RW--V */ | ||
848 | #define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ | ||
849 | #define NV_PFIFO_CACHE0_ENGINE_3_DVD 0x00000002 /* RW--V */ | ||
850 | #define NV_PFIFO_CACHE0_ENGINE_4 17:16 /* RWXUF */ | ||
851 | #define NV_PFIFO_CACHE0_ENGINE_4_SW 0x00000000 /* RW--V */ | ||
852 | #define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ | ||
853 | #define NV_PFIFO_CACHE0_ENGINE_4_DVD 0x00000002 /* RW--V */ | ||
854 | #define NV_PFIFO_CACHE0_ENGINE_5 21:20 /* RWXUF */ | ||
855 | #define NV_PFIFO_CACHE0_ENGINE_5_SW 0x00000000 /* RW--V */ | ||
856 | #define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ | ||
857 | #define NV_PFIFO_CACHE0_ENGINE_5_DVD 0x00000002 /* RW--V */ | ||
858 | #define NV_PFIFO_CACHE0_ENGINE_6 25:24 /* RWXUF */ | ||
859 | #define NV_PFIFO_CACHE0_ENGINE_6_SW 0x00000000 /* RW--V */ | ||
860 | #define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ | ||
861 | #define NV_PFIFO_CACHE0_ENGINE_6_DVD 0x00000002 /* RW--V */ | ||
862 | #define NV_PFIFO_CACHE0_ENGINE_7 29:28 /* RWXUF */ | ||
863 | #define NV_PFIFO_CACHE0_ENGINE_7_SW 0x00000000 /* RW--V */ | ||
864 | #define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ | ||
865 | #define NV_PFIFO_CACHE0_ENGINE_7_DVD 0x00000002 /* RW--V */ | ||
866 | #define NV_PFIFO_CACHE1_ENGINE 0x00003280 /* RW-4R */ | ||
867 | #define NV_PFIFO_CACHE1_ENGINE_0 1:0 /* RWXUF */ | ||
868 | #define NV_PFIFO_CACHE1_ENGINE_0_SW 0x00000000 /* RW--V */ | ||
869 | #define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ | ||
870 | #define NV_PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 /* RW--V */ | ||
871 | #define NV_PFIFO_CACHE1_ENGINE_1 5:4 /* RWXUF */ | ||
872 | #define NV_PFIFO_CACHE1_ENGINE_1_SW 0x00000000 /* RW--V */ | ||
873 | #define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ | ||
874 | #define NV_PFIFO_CACHE1_ENGINE_1_DVD 0x00000002 /* RW--V */ | ||
875 | #define NV_PFIFO_CACHE1_ENGINE_2 9:8 /* RWXUF */ | ||
876 | #define NV_PFIFO_CACHE1_ENGINE_2_SW 0x00000000 /* RW--V */ | ||
877 | #define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ | ||
878 | #define NV_PFIFO_CACHE1_ENGINE_2_DVD 0x00000002 /* RW--V */ | ||
879 | #define NV_PFIFO_CACHE1_ENGINE_3 13:12 /* RWXUF */ | ||
880 | #define NV_PFIFO_CACHE1_ENGINE_3_SW 0x00000000 /* RW--V */ | ||
881 | #define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ | ||
882 | #define NV_PFIFO_CACHE1_ENGINE_3_DVD 0x00000002 /* RW--V */ | ||
883 | #define NV_PFIFO_CACHE1_ENGINE_4 17:16 /* RWXUF */ | ||
884 | #define NV_PFIFO_CACHE1_ENGINE_4_SW 0x00000000 /* RW--V */ | ||
885 | #define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ | ||
886 | #define NV_PFIFO_CACHE1_ENGINE_4_DVD 0x00000002 /* RW--V */ | ||
887 | #define NV_PFIFO_CACHE1_ENGINE_5 21:20 /* RWXUF */ | ||
888 | #define NV_PFIFO_CACHE1_ENGINE_5_SW 0x00000000 /* RW--V */ | ||
889 | #define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ | ||
890 | #define NV_PFIFO_CACHE1_ENGINE_5_DVD 0x00000002 /* RW--V */ | ||
891 | #define NV_PFIFO_CACHE1_ENGINE_6 25:24 /* RWXUF */ | ||
892 | #define NV_PFIFO_CACHE1_ENGINE_6_SW 0x00000000 /* RW--V */ | ||
893 | #define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ | ||
894 | #define NV_PFIFO_CACHE1_ENGINE_6_DVD 0x00000002 /* RW--V */ | ||
895 | #define NV_PFIFO_CACHE1_ENGINE_7 29:28 /* RWXUF */ | ||
896 | #define NV_PFIFO_CACHE1_ENGINE_7_SW 0x00000000 /* RW--V */ | ||
897 | #define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ | ||
898 | #define NV_PFIFO_CACHE1_ENGINE_7_DVD 0x00000002 /* RW--V */ | ||
899 | #define NV_PFIFO_CACHE0_METHOD(i) (0x00003100+(i)*8) /* RW-4A */ | ||
900 | #define NV_PFIFO_CACHE0_METHOD__SIZE_1 1 /* */ | ||
901 | #define NV_PFIFO_CACHE0_METHOD_ADDRESS 12:2 /* RWXUF */ | ||
902 | #define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL 15:13 /* RWXUF */ | ||
903 | #define NV_PFIFO_CACHE1_METHOD(i) (0x00003800+(i)*8) /* RW-4A */ | ||
904 | #define NV_PFIFO_CACHE1_METHOD__SIZE_1 128 /* */ | ||
905 | #define NV_PFIFO_CACHE1_METHOD_ADDRESS 12:2 /* RWXUF */ | ||
906 | #define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 15:13 /* RWXUF */ | ||
907 | #define NV_PFIFO_CACHE1_METHOD_ALIAS(i) (0x00003C00+(i)*8) /* RW-4A */ | ||
908 | #define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1 128 /* */ | ||
909 | #define NV_PFIFO_CACHE0_DATA(i) (0x00003104+(i)*8) /* RW-4A */ | ||
910 | #define NV_PFIFO_CACHE0_DATA__SIZE_1 1 /* */ | ||
911 | #define NV_PFIFO_CACHE0_DATA_VALUE 31:0 /* RWXVF */ | ||
912 | #define NV_PFIFO_CACHE1_DATA(i) (0x00003804+(i)*8) /* RW-4A */ | ||
913 | #define NV_PFIFO_CACHE1_DATA__SIZE_1 128 /* */ | ||
914 | #define NV_PFIFO_CACHE1_DATA_VALUE 31:0 /* RWXVF */ | ||
915 | #define NV_PFIFO_CACHE1_DATA_ALIAS(i) (0x00003C04+(i)*8) /* RW-4A */ | ||
916 | #define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1 128 /* */ | ||
917 | #define NV_PFIFO_DEVICE(i) (0x00002800+(i)*4) /* R--4A */ | ||
918 | #define NV_PFIFO_DEVICE__SIZE_1 128 /* */ | ||
919 | #define NV_PFIFO_DEVICE_CHID 3:0 /* R--UF */ | ||
920 | #define NV_PFIFO_DEVICE_SWITCH 24:24 /* R--VF */ | ||
921 | #define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 /* R---V */ | ||
922 | #define NV_PFIFO_DEVICE_SWITCH_AVAILABLE 0x00000001 /* R---V */ | ||
923 | #define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */ | ||
924 | #define NV_PFIFO_RUNOUT_STATUS_RANOUT 0:0 /* R--VF */ | ||
925 | #define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 /* R---V */ | ||
926 | #define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 /* R---V */ | ||
927 | #define NV_PFIFO_RUNOUT_STATUS_LOW_MARK 4:4 /* R--VF */ | ||
928 | #define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ | ||
929 | #define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ | ||
930 | #define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK 8:8 /* R--VF */ | ||
931 | #define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ | ||
932 | #define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ | ||
933 | #define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */ | ||
934 | #define NV_PFIFO_RUNOUT_PUT_ADDRESS 12:3 /* RWXUF */ | ||
935 | #define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0 8:3 /* RWXUF */ | ||
936 | #define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1 12:3 /* RWXUF */ | ||
937 | #define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */ | ||
938 | #define NV_PFIFO_RUNOUT_GET_ADDRESS 13:3 /* RWXUF */ | ||
939 | /* dev_graphics.ref */ | ||
940 | #define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */ | ||
941 | #define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */ | ||
942 | #define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */ | ||
943 | #define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */ | ||
944 | #define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */ | ||
945 | #define NV_PGRAPH_INTR 0x00400100 /* RW-4R */ | ||
946 | #define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWIVF */ | ||
947 | #define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ | ||
948 | #define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */ | ||
949 | #define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--C */ | ||
950 | #define NV_PGRAPH_INTR_MISSING_HW 4:4 /* RWIVF */ | ||
951 | #define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x00000000 /* R-I-V */ | ||
952 | #define NV_PGRAPH_INTR_MISSING_HW_PENDING 0x00000001 /* R---V */ | ||
953 | #define NV_PGRAPH_INTR_MISSING_HW_RESET 0x00000001 /* -W--C */ | ||
954 | #define NV_PGRAPH_INTR_TLB_PRESENT_A 8:8 /* RWIVF */ | ||
955 | #define NV_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x00000000 /* R-I-V */ | ||
956 | #define NV_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x00000001 /* R---V */ | ||
957 | #define NV_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x00000001 /* -W--C */ | ||
958 | #define NV_PGRAPH_INTR_TLB_PRESENT_B 9:9 /* RWIVF */ | ||
959 | #define NV_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x00000000 /* R-I-V */ | ||
960 | #define NV_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x00000001 /* R---V */ | ||
961 | #define NV_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x00000001 /* -W--C */ | ||
962 | #define NV_PGRAPH_INTR_CONTEXT_SWITCH 12:12 /* RWIVF */ | ||
963 | #define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ | ||
964 | #define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */ | ||
965 | #define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x00000001 /* -W--C */ | ||
966 | #define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWIVF */ | ||
967 | #define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ | ||
968 | #define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */ | ||
969 | #define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--C */ | ||
970 | #define NV_PGRAPH_NSTATUS 0x00400104 /* RW-4R */ | ||
971 | #define NV_PGRAPH_NSTATUS_STATE_IN_USE 11:11 /* RWIVF */ | ||
972 | #define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x00000000 /* RWI-V */ | ||
973 | #define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x00000001 /* RW--V */ | ||
974 | #define NV_PGRAPH_NSTATUS_INVALID_STATE 12:12 /* RWIVF */ | ||
975 | #define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x00000000 /* RWI-V */ | ||
976 | #define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x00000001 /* RW--V */ | ||
977 | #define NV_PGRAPH_NSTATUS_BAD_ARGUMENT 13:13 /* RWIVF */ | ||
978 | #define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x00000000 /* RWI-V */ | ||
979 | #define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x00000001 /* RW--V */ | ||
980 | #define NV_PGRAPH_NSTATUS_PROTECTION_FAULT 14:14 /* RWIVF */ | ||
981 | #define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x00000000 /* RWI-V */ | ||
982 | #define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x00000001 /* RW--V */ | ||
983 | #define NV_PGRAPH_NSOURCE 0x00400108 /* R--4R */ | ||
984 | #define NV_PGRAPH_NSOURCE_NOTIFICATION 0:0 /* R-IVF */ | ||
985 | #define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ | ||
986 | #define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x00000001 /* R---V */ | ||
987 | #define NV_PGRAPH_NSOURCE_DATA_ERROR 1:1 /* R-IVF */ | ||
988 | #define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ | ||
989 | #define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x00000001 /* R---V */ | ||
990 | #define NV_PGRAPH_NSOURCE_PROTECTION_ERROR 2:2 /* R-IVF */ | ||
991 | #define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ | ||
992 | #define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x00000001 /* R---V */ | ||
993 | #define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION 3:3 /* R-IVF */ | ||
994 | #define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ | ||
995 | #define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x00000001 /* R---V */ | ||
996 | #define NV_PGRAPH_NSOURCE_LIMIT_COLOR 4:4 /* R-IVF */ | ||
997 | #define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x00000000 /* R-I-V */ | ||
998 | #define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x00000001 /* R---V */ | ||
999 | #define NV_PGRAPH_NSOURCE_LIMIT_ZETA_ 5:5 /* R-IVF */ | ||
1000 | #define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1001 | #define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x00000001 /* R---V */ | ||
1002 | #define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD 6:6 /* R-IVF */ | ||
1003 | #define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1004 | #define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */ | ||
1005 | #define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION 7:7 /* R-IVF */ | ||
1006 | #define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1007 | #define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x00000001 /* R---V */ | ||
1008 | #define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION 8:8 /* R-IVF */ | ||
1009 | #define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1010 | #define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x00000001 /* R---V */ | ||
1011 | #define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9:9 /* R-IVF */ | ||
1012 | #define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1013 | #define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x00000001 /* R---V */ | ||
1014 | #define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION 10:10 /* R-IVF */ | ||
1015 | #define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1016 | #define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x00000001 /* R---V */ | ||
1017 | #define NV_PGRAPH_NSOURCE_STATE_INVALID 11:11 /* R-IVF */ | ||
1018 | #define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1019 | #define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x00000001 /* R---V */ | ||
1020 | #define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12:12 /* R-IVF */ | ||
1021 | #define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1022 | #define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */ | ||
1023 | #define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE 13:13 /* R-IVF */ | ||
1024 | #define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1025 | #define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x00000001 /* R---V */ | ||
1026 | #define NV_PGRAPH_NSOURCE_METHOD_CNT 14:14 /* R-IVF */ | ||
1027 | #define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1028 | #define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x00000001 /* R---V */ | ||
1029 | #define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION 15:15 /* R-IVF */ | ||
1030 | #define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ | ||
1031 | #define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x00000001 /* R---V */ | ||
1032 | #define NV_PGRAPH_INTR_EN 0x00400140 /* RW-4R */ | ||
1033 | #define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWIVF */ | ||
1034 | #define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWI-V */ | ||
1035 | #define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */ | ||
1036 | #define NV_PGRAPH_INTR_EN_MISSING_HW 4:4 /* RWIVF */ | ||
1037 | #define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED 0x00000000 /* RWI-V */ | ||
1038 | #define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x00000001 /* RW--V */ | ||
1039 | #define NV_PGRAPH_INTR_EN_TLB_PRESENT_A 8:8 /* RWIVF */ | ||
1040 | #define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_DISABLED 0x00000000 /* RWI-V */ | ||
1041 | #define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x00000001 /* RW--V */ | ||
1042 | #define NV_PGRAPH_INTR_EN_TLB_PRESENT_B 9:9 /* RWIVF */ | ||
1043 | #define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_DISABLED 0x00000000 /* RWI-V */ | ||
1044 | #define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x00000001 /* RW--V */ | ||
1045 | #define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH 12:12 /* RWIVF */ | ||
1046 | #define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */ | ||
1047 | #define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */ | ||
1048 | #define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWIVF */ | ||
1049 | #define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWI-V */ | ||
1050 | #define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */ | ||
1051 | #define NV_PGRAPH_CTX_SWITCH1 0x00400160 /* RW-4R */ | ||
1052 | #define NV_PGRAPH_CTX_SWITCH1_GRCLASS 7:0 /* RWXVF */ | ||
1053 | #define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12:12 /* RWXUF */ | ||
1054 | #define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x00000000 /* RW--V */ | ||
1055 | #define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */ | ||
1056 | #define NV_PGRAPH_CTX_SWITCH1_USER_CLIP 13:13 /* RWXUF */ | ||
1057 | #define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x00000000 /* RW--V */ | ||
1058 | #define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x00000001 /* RW--V */ | ||
1059 | #define NV_PGRAPH_CTX_SWITCH1_SWIZZLE 14:14 /* RWXUF */ | ||
1060 | #define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x00000000 /* RW--V */ | ||
1061 | #define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x00000001 /* RW--V */ | ||
1062 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 /* RWXUF */ | ||
1063 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RW--V */ | ||
1064 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */ | ||
1065 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */ | ||
1066 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */ | ||
1067 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */ | ||
1068 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */ | ||
1069 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24:24 /* RWXUF */ | ||
1070 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x00000000 /* RW--V */ | ||
1071 | #define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x00000001 /* RW--V */ | ||
1072 | #define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25:25 /* RWXUF */ | ||
1073 | #define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x00000000 /* RW--V */ | ||
1074 | #define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x00000001 /* RW--V */ | ||
1075 | #define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31:31 /* CWIVF */ | ||
1076 | #define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x00000000 /* CWI-V */ | ||
1077 | #define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x00000001 /* -W--T */ | ||
1078 | #define NV_PGRAPH_CTX_SWITCH2 0x00400164 /* RW-4R */ | ||
1079 | #define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT 1:0 /* RWXUF */ | ||
1080 | #define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 /* RW--V */ | ||
1081 | #define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */ | ||
1082 | #define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 /* RW--V */ | ||
1083 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 /* RWXUF */ | ||
1084 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 /* RW--V */ | ||
1085 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */ | ||
1086 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */ | ||
1087 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */ | ||
1088 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */ | ||
1089 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */ | ||
1090 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */ | ||
1091 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */ | ||
1092 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */ | ||
1093 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */ | ||
1094 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */ | ||
1095 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */ | ||
1096 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */ | ||
1097 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */ | ||
1098 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */ | ||
1099 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */ | ||
1100 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ | ||
1101 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ | ||
1102 | #define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */ | ||
1103 | #define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 31:16 /* RWXUF */ | ||
1104 | #define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x0000 /* RW--V */ | ||
1105 | #define NV_PGRAPH_CTX_SWITCH3 0x00400168 /* RW-4R */ | ||
1106 | #define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 15:0 /* RWXUF */ | ||
1107 | #define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x0000 /* RW--V */ | ||
1108 | #define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 31:16 /* RWXUF */ | ||
1109 | #define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x0000 /* RW--V */ | ||
1110 | #define NV_PGRAPH_CTX_SWITCH4 0x0040016C /* RW-4R */ | ||
1111 | #define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 15:0 /* RWXUF */ | ||
1112 | #define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x0000 /* RW--V */ | ||
1113 | #define NV_PGRAPH_CTX_CACHE1(i) (0x00400180+(i)*4) /* RW-4A */ | ||
1114 | #define NV_PGRAPH_CTX_CACHE1__SIZE_1 8 /* */ | ||
1115 | #define NV_PGRAPH_CTX_CACHE1_GRCLASS 7:0 /* RWXVF */ | ||
1116 | #define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY 12:12 /* RWXVF */ | ||
1117 | #define NV_PGRAPH_CTX_CACHE1_USER_CLIP 13:13 /* RWXVF */ | ||
1118 | #define NV_PGRAPH_CTX_CACHE1_SWIZZLE 14:14 /* RWXVF */ | ||
1119 | #define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 /* RWXVF */ | ||
1120 | #define NV_PGRAPH_CTX_CACHE1_SPARE1 20:20 /* RWXVF */ | ||
1121 | #define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS 24:24 /* RWXVF */ | ||
1122 | #define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25:25 /* RWXVF */ | ||
1123 | #define NV_PGRAPH_CTX_CACHE2(i) (0x004001a0+(i)*4) /* RW-4A */ | ||
1124 | #define NV_PGRAPH_CTX_CACHE2__SIZE_1 8 /* */ | ||
1125 | #define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT 1:0 /* RWXVF */ | ||
1126 | #define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 /* RWXVF */ | ||
1127 | #define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 31:16 /* RWXVF */ | ||
1128 | #define NV_PGRAPH_CTX_CACHE3(i) (0x004001c0+(i)*4) /* RW-4A */ | ||
1129 | #define NV_PGRAPH_CTX_CACHE3__SIZE_1 8 /* */ | ||
1130 | #define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 15:0 /* RWXVF */ | ||
1131 | #define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 31:16 /* RWXVF */ | ||
1132 | #define NV_PGRAPH_CTX_CACHE4(i) (0x004001e0+(i)*4) /* RW-4A */ | ||
1133 | #define NV_PGRAPH_CTX_CACHE4__SIZE_1 8 /* */ | ||
1134 | #define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE 15:0 /* RWXVF */ | ||
1135 | #define NV_PGRAPH_CTX_CONTROL 0x00400170 /* RW-4R */ | ||
1136 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */ | ||
1137 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */ | ||
1138 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */ | ||
1139 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */ | ||
1140 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */ | ||
1141 | #define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */ | ||
1142 | #define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */ | ||
1143 | #define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */ | ||
1144 | #define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */ | ||
1145 | #define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */ | ||
1146 | #define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */ | ||
1147 | #define NV_PGRAPH_CTX_CONTROL_CHANGE 20:20 /* R--VF */ | ||
1148 | #define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x00000000 /* R---V */ | ||
1149 | #define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x00000001 /* R---V */ | ||
1150 | #define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */ | ||
1151 | #define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */ | ||
1152 | #define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */ | ||
1153 | #define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */ | ||
1154 | #define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */ | ||
1155 | #define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */ | ||
1156 | #define NV_PGRAPH_CTX_USER 0x00400174 /* RW-4R */ | ||
1157 | #define NV_PGRAPH_CTX_USER_SUBCH 15:13 /* RWIVF */ | ||
1158 | #define NV_PGRAPH_CTX_USER_SUBCH_0 0x00000000 /* RWI-V */ | ||
1159 | #define NV_PGRAPH_CTX_USER_CHID 27:24 /* RWIVF */ | ||
1160 | #define NV_PGRAPH_CTX_USER_CHID_0 0x00000000 /* RWI-V */ | ||
1161 | #define NV_PGRAPH_FIFO 0x00400720 /* RW-4R */ | ||
1162 | #define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */ | ||
1163 | #define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */ | ||
1164 | #define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */ | ||
1165 | #define NV_PGRAPH_FFINTFC_FIFO_0(i) (0x00400730+(i)*4) /* RW-4A */ | ||
1166 | #define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1 4 /* */ | ||
1167 | #define NV_PGRAPH_FFINTFC_FIFO_0_TAG 0:0 /* RWXVF */ | ||
1168 | #define NV_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x00000000 /* RW--V */ | ||
1169 | #define NV_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x00000001 /* RW--V */ | ||
1170 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH 3:1 /* RWXVF */ | ||
1171 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0 0x00000000 /* RW--V */ | ||
1172 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1 0x00000001 /* RW--V */ | ||
1173 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2 0x00000002 /* RW--V */ | ||
1174 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3 0x00000003 /* RW--V */ | ||
1175 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4 0x00000004 /* RW--V */ | ||
1176 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5 0x00000005 /* RW--V */ | ||
1177 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6 0x00000006 /* RW--V */ | ||
1178 | #define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7 0x00000007 /* RW--V */ | ||
1179 | #define NV_PGRAPH_FFINTFC_FIFO_0_MTHD 14:4 /* RWXVF */ | ||
1180 | #define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x00000000 /* RW--V */ | ||
1181 | #define NV_PGRAPH_FFINTFC_FIFO_1(i) (0x00400740+(i)*4) /* RW-4A */ | ||
1182 | #define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1 4 /* */ | ||
1183 | #define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 31:0 /* RWXVF */ | ||
1184 | #define NV_PGRAPH_FFINTFC_FIFO_PTR 0x00400750 /* RW-4R */ | ||
1185 | #define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE 2:0 /* RWIVF */ | ||
1186 | #define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x00000000 /* RWI-V */ | ||
1187 | #define NV_PGRAPH_FFINTFC_FIFO_PTR_READ 6:4 /* RWIVF */ | ||
1188 | #define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x00000000 /* RWI-V */ | ||
1189 | #define NV_PGRAPH_FFINTFC_ST2 0x00400754 /* RW-4R */ | ||
1190 | #define NV_PGRAPH_FFINTFC_ST2_STATUS 0:0 /* RWIVF */ | ||
1191 | #define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x00000000 /* RWI-V */ | ||
1192 | #define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x00000001 /* RW--V */ | ||
1193 | #define NV_PGRAPH_FFINTFC_ST2_MTHD 11:1 /* RWIVF */ | ||
1194 | #define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x00000000 /* RWI-V */ | ||
1195 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH 14:12 /* RWIVF */ | ||
1196 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH_0 0x00000000 /* RWI-V */ | ||
1197 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH_1 0x00000001 /* RW--V */ | ||
1198 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH_2 0x00000002 /* RW--V */ | ||
1199 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH_3 0x00000003 /* RW--V */ | ||
1200 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH_4 0x00000004 /* RW--V */ | ||
1201 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH_5 0x00000005 /* RW--V */ | ||
1202 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH_6 0x00000006 /* RW--V */ | ||
1203 | #define NV_PGRAPH_FFINTFC_ST2_SUBCH_7 0x00000007 /* RW--V */ | ||
1204 | #define NV_PGRAPH_FFINTFC_ST2_CHID 18:15 /* RWIVF */ | ||
1205 | #define NV_PGRAPH_FFINTFC_ST2_CHID_0 0x00000000 /* RWI-V */ | ||
1206 | #define NV_PGRAPH_FFINTFC_ST2_CHID_1 0x00000001 /* RW--V */ | ||
1207 | #define NV_PGRAPH_FFINTFC_ST2_CHID_2 0x00000002 /* RW--V */ | ||
1208 | #define NV_PGRAPH_FFINTFC_ST2_CHID_3 0x00000003 /* RW--V */ | ||
1209 | #define NV_PGRAPH_FFINTFC_ST2_CHID_4 0x00000004 /* RW--V */ | ||
1210 | #define NV_PGRAPH_FFINTFC_ST2_CHID_5 0x00000005 /* RW--V */ | ||
1211 | #define NV_PGRAPH_FFINTFC_ST2_CHID_6 0x00000006 /* RW--V */ | ||
1212 | #define NV_PGRAPH_FFINTFC_ST2_CHID_7 0x00000007 /* RW--V */ | ||
1213 | #define NV_PGRAPH_FFINTFC_ST2_CHID_8 0x00000008 /* RW--V */ | ||
1214 | #define NV_PGRAPH_FFINTFC_ST2_CHID_9 0x00000009 /* RW--V */ | ||
1215 | #define NV_PGRAPH_FFINTFC_ST2_CHID_10 0x0000000A /* RW--V */ | ||
1216 | #define NV_PGRAPH_FFINTFC_ST2_CHID_11 0x0000000B /* RW--V */ | ||
1217 | #define NV_PGRAPH_FFINTFC_ST2_CHID_12 0x0000000C /* RW--V */ | ||
1218 | #define NV_PGRAPH_FFINTFC_ST2_CHID_13 0x0000000D /* RW--V */ | ||
1219 | #define NV_PGRAPH_FFINTFC_ST2_CHID_14 0x0000000E /* RW--V */ | ||
1220 | #define NV_PGRAPH_FFINTFC_ST2_CHID_15 0x0000000F /* RW--V */ | ||
1221 | #define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS 19:19 /* RWIVF */ | ||
1222 | #define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x00000000 /* RWI-V */ | ||
1223 | #define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x00000001 /* RW--V */ | ||
1224 | #define NV_PGRAPH_FFINTFC_ST2_D 0x00400758 /* RW-4R */ | ||
1225 | #define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT 31:0 /* RWIVF */ | ||
1226 | #define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x00000000 /* RWI-V */ | ||
1227 | #define NV_PGRAPH_STATUS 0x00400700 /* R--4R */ | ||
1228 | #define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */ | ||
1229 | #define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */ | ||
1230 | #define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */ | ||
1231 | #define NV_PGRAPH_STATUS_XY_LOGIC 4:4 /* R-IVF */ | ||
1232 | #define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */ | ||
1233 | #define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */ | ||
1234 | #define NV_PGRAPH_STATUS_FE 5:5 /* R-IVF */ | ||
1235 | #define NV_PGRAPH_STATUS_FE_IDLE 0x00000000 /* R-I-V */ | ||
1236 | #define NV_PGRAPH_STATUS_FE_BUSY 0x00000001 /* R---V */ | ||
1237 | #define NV_PGRAPH_STATUS_RASTERIZER 6:6 /* R-IVF */ | ||
1238 | #define NV_PGRAPH_STATUS_RASTERIZER_IDLE 0x00000000 /* R-I-V */ | ||
1239 | #define NV_PGRAPH_STATUS_RASTERIZER_BUSY 0x00000001 /* R---V */ | ||
1240 | #define NV_PGRAPH_STATUS_PORT_NOTIFY 8:8 /* R-IVF */ | ||
1241 | #define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */ | ||
1242 | #define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */ | ||
1243 | #define NV_PGRAPH_STATUS_PORT_REGISTER 12:12 /* R-IVF */ | ||
1244 | #define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x00000000 /* R-I-V */ | ||
1245 | #define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x00000001 /* R---V */ | ||
1246 | #define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */ | ||
1247 | #define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */ | ||
1248 | #define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */ | ||
1249 | #define NV_PGRAPH_STATUS_DMA_ENGINE 17:17 /* R-IVF */ | ||
1250 | #define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 /* R-I-V */ | ||
1251 | #define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00000001 /* R---V */ | ||
1252 | #define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */ | ||
1253 | #define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */ | ||
1254 | #define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */ | ||
1255 | #define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21:21 /* R-IVF */ | ||
1256 | #define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 /* R-I-V */ | ||
1257 | #define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00000001 /* R---V */ | ||
1258 | #define NV_PGRAPH_STATUS_D3D 24:24 /* R-IVF */ | ||
1259 | #define NV_PGRAPH_STATUS_D3D_IDLE 0x00000000 /* R-I-V */ | ||
1260 | #define NV_PGRAPH_STATUS_D3D_BUSY 0x00000001 /* R---V */ | ||
1261 | #define NV_PGRAPH_STATUS_CACHE 25:25 /* R-IVF */ | ||
1262 | #define NV_PGRAPH_STATUS_CACHE_IDLE 0x00000000 /* R-I-V */ | ||
1263 | #define NV_PGRAPH_STATUS_CACHE_BUSY 0x00000001 /* R---V */ | ||
1264 | #define NV_PGRAPH_STATUS_LIGHTING 26:26 /* R-IVF */ | ||
1265 | #define NV_PGRAPH_STATUS_LIGHTING_IDLE 0x00000000 /* R-I-V */ | ||
1266 | #define NV_PGRAPH_STATUS_LIGHTING_BUSY 0x00000001 /* R---V */ | ||
1267 | #define NV_PGRAPH_STATUS_PREROP 27:27 /* R-IVF */ | ||
1268 | #define NV_PGRAPH_STATUS_PREROP_IDLE 0x00000000 /* R-I-V */ | ||
1269 | #define NV_PGRAPH_STATUS_PREROP_BUSY 0x00000001 /* R---V */ | ||
1270 | #define NV_PGRAPH_STATUS_ROP 28:28 /* R-IVF */ | ||
1271 | #define NV_PGRAPH_STATUS_ROP_IDLE 0x00000000 /* R-I-V */ | ||
1272 | #define NV_PGRAPH_STATUS_ROP_BUSY 0x00000001 /* R---V */ | ||
1273 | #define NV_PGRAPH_STATUS_PORT_USER 29:29 /* R-IVF */ | ||
1274 | #define NV_PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 /* R-I-V */ | ||
1275 | #define NV_PGRAPH_STATUS_PORT_USER_BUSY 0x00000001 /* R---V */ | ||
1276 | #define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */ | ||
1277 | #define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 /* R-XUF */ | ||
1278 | #define NV_PGRAPH_TRAPPED_ADDR_SUBCH 15:13 /* R-XUF */ | ||
1279 | #define NV_PGRAPH_TRAPPED_ADDR_CHID 27:24 /* R-XUF */ | ||
1280 | #define NV_PGRAPH_TRAPPED_DATA 0x00400708 /* R--4R */ | ||
1281 | #define NV_PGRAPH_TRAPPED_DATA_VALUE 31:0 /* R-XVF */ | ||
1282 | #define NV_PGRAPH_SURFACE 0x0040070C /* RW-4R */ | ||
1283 | #define NV_PGRAPH_SURFACE_TYPE 1:0 /* RWIVF */ | ||
1284 | #define NV_PGRAPH_SURFACE_TYPE_INVALID 0x00000000 /* RWI-V */ | ||
1285 | #define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x00000001 /* RW--V */ | ||
1286 | #define NV_PGRAPH_SURFACE_TYPE_SWIZZLE 0x00000002 /* RW--V */ | ||
1287 | #define NV_PGRAPH_NOTIFY 0x00400714 /* RW-4R */ | ||
1288 | #define NV_PGRAPH_NOTIFY_BUFFER_REQ 0:0 /* RWIVF */ | ||
1289 | #define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x00000000 /* RWI-V */ | ||
1290 | #define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x00000001 /* RW--V */ | ||
1291 | #define NV_PGRAPH_NOTIFY_BUFFER_STYLE 8:8 /* RWIVF */ | ||
1292 | #define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ | ||
1293 | #define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ | ||
1294 | #define NV_PGRAPH_NOTIFY_REQ 16:16 /* RWIVF */ | ||
1295 | #define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x00000000 /* RWI-V */ | ||
1296 | #define NV_PGRAPH_NOTIFY_REQ_PENDING 0x00000001 /* RW--V */ | ||
1297 | #define NV_PGRAPH_NOTIFY_STYLE 20:20 /* RWIVF */ | ||
1298 | #define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ | ||
1299 | #define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ | ||
1300 | #define NV_PGRAPH_BOFFSET(i) (0x00400640+(i)*4) /* RW-4A */ | ||
1301 | #define NV_PGRAPH_BOFFSET__SIZE_1 6 /* */ | ||
1302 | #define NV_PGRAPH_BOFFSET_LINADRS 23:0 /* RWIUF */ | ||
1303 | #define NV_PGRAPH_BOFFSET_LINADRS_0 0x00000000 /* RWI-V */ | ||
1304 | #define NV_PGRAPH_BOFFSET0 0x00400640 /* RW-4R */ | ||
1305 | #define NV_PGRAPH_BOFFSET0__ALIAS_1 NV_PGRAPH_BOFFSET(0) /* */ | ||
1306 | #define NV_PGRAPH_BOFFSET0_LINADRS 23:0 /* RWIUF */ | ||
1307 | #define NV_PGRAPH_BOFFSET0_LINADRS_0 0x00000000 /* RWI-V */ | ||
1308 | #define NV_PGRAPH_BOFFSET1 0x00400644 /* RW-4R */ | ||
1309 | #define NV_PGRAPH_BOFFSET1__ALIAS_1 NV_PGRAPH_BOFFSET(1) /* */ | ||
1310 | #define NV_PGRAPH_BOFFSET1_LINADRS 23:0 /* RWIUF */ | ||
1311 | #define NV_PGRAPH_BOFFSET1_LINADRS_0 0x00000000 /* RWI-V */ | ||
1312 | #define NV_PGRAPH_BOFFSET2 0x00400648 /* RW-4R */ | ||
1313 | #define NV_PGRAPH_BOFFSET2__ALIAS_1 NV_PGRAPH_BOFFSET(2) /* */ | ||
1314 | #define NV_PGRAPH_BOFFSET2_LINADRS 23:0 /* RWIUF */ | ||
1315 | #define NV_PGRAPH_BOFFSET2_LINADRS_0 0x00000000 /* RWI-V */ | ||
1316 | #define NV_PGRAPH_BOFFSET3 0x0040064C /* RW-4R */ | ||
1317 | #define NV_PGRAPH_BOFFSET3__ALIAS_1 NV_PGRAPH_BOFFSET(3) /* */ | ||
1318 | #define NV_PGRAPH_BOFFSET3_LINADRS 23:0 /* RWIUF */ | ||
1319 | #define NV_PGRAPH_BOFFSET3_LINADRS_0 0x00000000 /* RWI-V */ | ||
1320 | #define NV_PGRAPH_BOFFSET4 0x00400650 /* RW-4R */ | ||
1321 | #define NV_PGRAPH_BOFFSET4__ALIAS_1 NV_PGRAPH_BOFFSET(4) /* */ | ||
1322 | #define NV_PGRAPH_BOFFSET4_LINADRS 23:0 /* RWIUF */ | ||
1323 | #define NV_PGRAPH_BOFFSET4_LINADRS_0 0x00000000 /* RWI-V */ | ||
1324 | #define NV_PGRAPH_BOFFSET5 0x00400654 /* RW-4R */ | ||
1325 | #define NV_PGRAPH_BOFFSET5__ALIAS_1 NV_PGRAPH_BOFFSET(5) /* */ | ||
1326 | #define NV_PGRAPH_BOFFSET5_LINADRS 23:0 /* RWIUF */ | ||
1327 | #define NV_PGRAPH_BOFFSET5_LINADRS_0 0x00000000 /* RWI-V */ | ||
1328 | #define NV_PGRAPH_BBASE(i) (0x00400658+(i)*4) /* RW-4A */ | ||
1329 | #define NV_PGRAPH_BBASE__SIZE_1 6 /* */ | ||
1330 | #define NV_PGRAPH_BBASE_LINADRS 23:0 /* RWIUF */ | ||
1331 | #define NV_PGRAPH_BBASE_LINADRS_0 0x00000000 /* RWI-V */ | ||
1332 | #define NV_PGRAPH_BBASE0 0x00400658 /* RW-4R */ | ||
1333 | #define NV_PGRAPH_BBASE0__ALIAS_1 NV_PGRAPH_BBASE(0) /* */ | ||
1334 | #define NV_PGRAPH_BBASE0_LINADRS 23:0 /* RWIUF */ | ||
1335 | #define NV_PGRAPH_BBASE0_LINADRS_0 0x00000000 /* RWI-V */ | ||
1336 | #define NV_PGRAPH_BBASE1 0x0040065c /* RW-4R */ | ||
1337 | #define NV_PGRAPH_BBASE1__ALIAS_1 NV_PGRAPH_BBASE(1) /* */ | ||
1338 | #define NV_PGRAPH_BBASE1_LINADRS 23:0 /* RWIUF */ | ||
1339 | #define NV_PGRAPH_BBASE1_LINADRS_0 0x00000000 /* RWI-V */ | ||
1340 | #define NV_PGRAPH_BBASE2 0x00400660 /* RW-4R */ | ||
1341 | #define NV_PGRAPH_BBASE2__ALIAS_1 NV_PGRAPH_BBASE(2) /* */ | ||
1342 | #define NV_PGRAPH_BBASE2_LINADRS 23:0 /* RWIUF */ | ||
1343 | #define NV_PGRAPH_BBASE2_LINADRS_0 0x00000000 /* RWI-V */ | ||
1344 | #define NV_PGRAPH_BBASE3 0x00400664 /* RW-4R */ | ||
1345 | #define NV_PGRAPH_BBASE3__ALIAS_1 NV_PGRAPH_BBASE(3) /* */ | ||
1346 | #define NV_PGRAPH_BBASE3_LINADRS 23:0 /* RWIUF */ | ||
1347 | #define NV_PGRAPH_BBASE3_LINADRS_0 0x00000000 /* RWI-V */ | ||
1348 | #define NV_PGRAPH_BBASE4 0x00400668 /* RW-4R */ | ||
1349 | #define NV_PGRAPH_BBASE4__ALIAS_1 NV_PGRAPH_BBASE(4) /* */ | ||
1350 | #define NV_PGRAPH_BBASE4_LINADRS 23:0 /* RWIUF */ | ||
1351 | #define NV_PGRAPH_BBASE4_LINADRS_0 0x00000000 /* RWI-V */ | ||
1352 | #define NV_PGRAPH_BBASE5 0x0040066C /* RW-4R */ | ||
1353 | #define NV_PGRAPH_BBASE5__ALIAS_1 NV_PGRAPH_BBASE(5) /* */ | ||
1354 | #define NV_PGRAPH_BBASE5_LINADRS 23:0 /* RWIUF */ | ||
1355 | #define NV_PGRAPH_BBASE5_LINADRS_0 0x00000000 /* RWI-V */ | ||
1356 | #define NV_PGRAPH_BPITCH(i) (0x00400670+(i)*4) /* RW-4A */ | ||
1357 | #define NV_PGRAPH_BPITCH__SIZE_1 5 /* */ | ||
1358 | #define NV_PGRAPH_BPITCH_VALUE 12:0 /* RWIUF */ | ||
1359 | #define NV_PGRAPH_BPITCH_VALUE_0 0x00000000 /* RWI-V */ | ||
1360 | #define NV_PGRAPH_BPITCH0 0x00400670 /* RW-4R */ | ||
1361 | #define NV_PGRAPH_BPITCH0__ALIAS_1 NV_PGRAPH_BPITCH(0) /* */ | ||
1362 | #define NV_PGRAPH_BPITCH0_VALUE 12:0 /* RWIUF */ | ||
1363 | #define NV_PGRAPH_BPITCH0_VALUE_0 0x00000000 /* RWI-V */ | ||
1364 | #define NV_PGRAPH_BPITCH1 0x00400674 /* RW-4R */ | ||
1365 | #define NV_PGRAPH_BPITCH1__ALIAS_1 NV_PGRAPH_BPITCH(1) /* */ | ||
1366 | #define NV_PGRAPH_BPITCH1_VALUE 12:0 /* RWIUF */ | ||
1367 | #define NV_PGRAPH_BPITCH1_VALUE_0 0x00000000 /* RWI-V */ | ||
1368 | #define NV_PGRAPH_BPITCH2 0x00400678 /* RW-4R */ | ||
1369 | #define NV_PGRAPH_BPITCH2__ALIAS_1 NV_PGRAPH_BPITCH(2) /* */ | ||
1370 | #define NV_PGRAPH_BPITCH2_VALUE 12:0 /* RWIUF */ | ||
1371 | #define NV_PGRAPH_BPITCH2_VALUE_0 0x00000000 /* RWI-V */ | ||
1372 | #define NV_PGRAPH_BPITCH3 0x0040067C /* RW-4R */ | ||
1373 | #define NV_PGRAPH_BPITCH3__ALIAS_1 NV_PGRAPH_BPITCH(3) /* */ | ||
1374 | #define NV_PGRAPH_BPITCH3_VALUE 12:0 /* RWIUF */ | ||
1375 | #define NV_PGRAPH_BPITCH3_VALUE_0 0x00000000 /* RWI-V */ | ||
1376 | #define NV_PGRAPH_BPITCH4 0x00400680 /* RW-4R */ | ||
1377 | #define NV_PGRAPH_BPITCH4__ALIAS_1 NV_PGRAPH_BPITCH(4) /* */ | ||
1378 | #define NV_PGRAPH_BPITCH4_VALUE 12:0 /* RWIUF */ | ||
1379 | #define NV_PGRAPH_BPITCH4_VALUE_0 0x00000000 /* RWI-V */ | ||
1380 | #define NV_PGRAPH_BLIMIT(i) (0x00400684+(i)*4) /* RW-4A */ | ||
1381 | #define NV_PGRAPH_BLIMIT__SIZE_1 6 /* */ | ||
1382 | #define NV_PGRAPH_BLIMIT_VALUE 23:0 /* RWXUF */ | ||
1383 | #define NV_PGRAPH_BLIMIT_TYPE 31:31 /* RWIVF */ | ||
1384 | #define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x00000000 /* RW--V */ | ||
1385 | #define NV_PGRAPH_BLIMIT_TYPE_NULL 0x00000001 /* RWI-V */ | ||
1386 | #define NV_PGRAPH_BLIMIT0 0x00400684 /* RW-4R */ | ||
1387 | #define NV_PGRAPH_BLIMIT0__ALIAS_1 NV_PGRAPH_BLIMIT(0) /* */ | ||
1388 | #define NV_PGRAPH_BLIMIT0_VALUE 23:0 /* RWXUF */ | ||
1389 | #define NV_PGRAPH_BLIMIT0_TYPE 31:31 /* RWIVF */ | ||
1390 | #define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY 0x00000000 /* RW--V */ | ||
1391 | #define NV_PGRAPH_BLIMIT0_TYPE_NULL 0x00000001 /* RWI-V */ | ||
1392 | #define NV_PGRAPH_BLIMIT1 0x00400688 /* RW-4R */ | ||
1393 | #define NV_PGRAPH_BLIMIT1__ALIAS_1 NV_PGRAPH_BLIMIT(1) /* */ | ||
1394 | #define NV_PGRAPH_BLIMIT1_VALUE 23:0 /* RWXUF */ | ||
1395 | #define NV_PGRAPH_BLIMIT1_TYPE 31:31 /* RWIVF */ | ||
1396 | #define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY 0x00000000 /* RW--V */ | ||
1397 | #define NV_PGRAPH_BLIMIT1_TYPE_NULL 0x00000001 /* RWI-V */ | ||
1398 | #define NV_PGRAPH_BLIMIT2 0x0040068c /* RW-4R */ | ||
1399 | #define NV_PGRAPH_BLIMIT2__ALIAS_1 NV_PGRAPH_BLIMIT(2) /* */ | ||
1400 | #define NV_PGRAPH_BLIMIT2_VALUE 23:0 /* RWXUF */ | ||
1401 | #define NV_PGRAPH_BLIMIT2_TYPE 31:31 /* RWIVF */ | ||
1402 | #define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY 0x00000000 /* RW--V */ | ||
1403 | #define NV_PGRAPH_BLIMIT2_TYPE_NULL 0x00000001 /* RWI-V */ | ||
1404 | #define NV_PGRAPH_BLIMIT3 0x00400690 /* RW-4R */ | ||
1405 | #define NV_PGRAPH_BLIMIT3__ALIAS_1 NV_PGRAPH_BLIMIT(3) /* */ | ||
1406 | #define NV_PGRAPH_BLIMIT3_VALUE 23:0 /* RWXUF */ | ||
1407 | #define NV_PGRAPH_BLIMIT3_TYPE 31:31 /* RWIVF */ | ||
1408 | #define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY 0x00000000 /* RW--V */ | ||
1409 | #define NV_PGRAPH_BLIMIT3_TYPE_NULL 0x00000001 /* RWI-V */ | ||
1410 | #define NV_PGRAPH_BLIMIT4 0x00400694 /* RW-4R */ | ||
1411 | #define NV_PGRAPH_BLIMIT4__ALIAS_1 NV_PGRAPH_BLIMIT(4) /* */ | ||
1412 | #define NV_PGRAPH_BLIMIT4_VALUE 23:0 /* RWXUF */ | ||
1413 | #define NV_PGRAPH_BLIMIT4_TYPE 31:31 /* RWIVF */ | ||
1414 | #define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY 0x00000000 /* RW--V */ | ||
1415 | #define NV_PGRAPH_BLIMIT4_TYPE_NULL 0x00000001 /* RWI-V */ | ||
1416 | #define NV_PGRAPH_BLIMIT5 0x00400698 /* RW-4R */ | ||
1417 | #define NV_PGRAPH_BLIMIT5__ALIAS_1 NV_PGRAPH_BLIMIT(5) /* */ | ||
1418 | #define NV_PGRAPH_BLIMIT5_VALUE 23:0 /* RWXUF */ | ||
1419 | #define NV_PGRAPH_BLIMIT5_TYPE 31:31 /* RWIVF */ | ||
1420 | #define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY 0x00000000 /* RW--V */ | ||
1421 | #define NV_PGRAPH_BLIMIT5_TYPE_NULL 0x00000001 /* RWI-V */ | ||
1422 | #define NV_PGRAPH_BSWIZZLE2 0x0040069c /* RW-4R */ | ||
1423 | #define NV_PGRAPH_BSWIZZLE2_WIDTH 19:16 /* RWIUF */ | ||
1424 | #define NV_PGRAPH_BSWIZZLE2_WIDTH_0 0x00000000 /* RWI-V */ | ||
1425 | #define NV_PGRAPH_BSWIZZLE2_HEIGHT 27:24 /* RWIUF */ | ||
1426 | #define NV_PGRAPH_BSWIZZLE2_HEIGHT_0 0x00000000 /* RWI-V */ | ||
1427 | #define NV_PGRAPH_BSWIZZLE5 0x004006a0 /* RW-4R */ | ||
1428 | #define NV_PGRAPH_BSWIZZLE5_WIDTH 19:16 /* RWIUF */ | ||
1429 | #define NV_PGRAPH_BSWIZZLE5_WIDTH_0 0x00000000 /* RWI-V */ | ||
1430 | #define NV_PGRAPH_BSWIZZLE5_HEIGHT 27:24 /* RWIUF */ | ||
1431 | #define NV_PGRAPH_BSWIZZLE5_HEIGHT_0 0x00000000 /* RWI-V */ | ||
1432 | #define NV_PGRAPH_BPIXEL 0x00400724 /* RW-4R */ | ||
1433 | #define NV_PGRAPH_BPIXEL_DEPTH0 3:0 /* RWIVF */ | ||
1434 | #define NV_PGRAPH_BPIXEL_DEPTH0_INVALID 0x00000000 /* RWI-V */ | ||
1435 | #define NV_PGRAPH_BPIXEL_DEPTH0_Y8 0x00000001 /* RW--V */ | ||
1436 | #define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ | ||
1437 | #define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ | ||
1438 | #define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5 0x00000004 /* RW--V */ | ||
1439 | #define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5 0x00000005 /* RW--V */ | ||
1440 | #define NV_PGRAPH_BPIXEL_DEPTH0_Y16 0x00000006 /* RW--V */ | ||
1441 | #define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ | ||
1442 | #define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ | ||
1443 | #define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ | ||
1444 | #define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ | ||
1445 | #define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ | ||
1446 | #define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8 0x0000000c /* RW--V */ | ||
1447 | #define NV_PGRAPH_BPIXEL_DEPTH0_Y32 0x0000000d /* RW--V */ | ||
1448 | #define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8 0x0000000e /* RW--V */ | ||
1449 | #define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8 0x0000000f /* RW--V */ | ||
1450 | #define NV_PGRAPH_BPIXEL_DEPTH1 7:4 /* RWIVF */ | ||
1451 | #define NV_PGRAPH_BPIXEL_DEPTH1_INVALID 0x00000000 /* RWI-V */ | ||
1452 | #define NV_PGRAPH_BPIXEL_DEPTH1_Y8 0x00000001 /* RW--V */ | ||
1453 | #define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ | ||
1454 | #define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ | ||
1455 | #define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5 0x00000004 /* RW--V */ | ||
1456 | #define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5 0x00000005 /* RW--V */ | ||
1457 | #define NV_PGRAPH_BPIXEL_DEPTH1_Y16 0x00000006 /* RW--V */ | ||
1458 | #define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ | ||
1459 | #define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ | ||
1460 | #define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ | ||
1461 | #define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ | ||
1462 | #define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ | ||
1463 | #define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8 0x0000000c /* RW--V */ | ||
1464 | #define NV_PGRAPH_BPIXEL_DEPTH1_Y32 0x0000000d /* RW--V */ | ||
1465 | #define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8 0x0000000e /* RW--V */ | ||
1466 | #define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8 0x0000000f /* RW--V */ | ||
1467 | #define NV_PGRAPH_BPIXEL_DEPTH2 11:8 /* RWIVF */ | ||
1468 | #define NV_PGRAPH_BPIXEL_DEPTH2_INVALID 0x00000000 /* RWI-V */ | ||
1469 | #define NV_PGRAPH_BPIXEL_DEPTH2_Y8 0x00000001 /* RW--V */ | ||
1470 | #define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ | ||
1471 | #define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ | ||
1472 | #define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5 0x00000004 /* RW--V */ | ||
1473 | #define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5 0x00000005 /* RW--V */ | ||
1474 | #define NV_PGRAPH_BPIXEL_DEPTH2_Y16 0x00000006 /* RW--V */ | ||
1475 | #define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ | ||
1476 | #define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ | ||
1477 | #define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ | ||
1478 | #define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ | ||
1479 | #define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ | ||
1480 | #define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8 0x0000000c /* RW--V */ | ||
1481 | #define NV_PGRAPH_BPIXEL_DEPTH2_Y32 0x0000000d /* RW--V */ | ||
1482 | #define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8 0x0000000e /* RW--V */ | ||
1483 | #define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8 0x0000000f /* RW--V */ | ||
1484 | #define NV_PGRAPH_BPIXEL_DEPTH3 15:12 /* RWIVF */ | ||
1485 | #define NV_PGRAPH_BPIXEL_DEPTH3_INVALID 0x00000000 /* RWI-V */ | ||
1486 | #define NV_PGRAPH_BPIXEL_DEPTH3_Y8 0x00000001 /* RW--V */ | ||
1487 | #define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ | ||
1488 | #define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ | ||
1489 | #define NV_PGRAPH_BPIXEL_DEPTH3_A1R5G5B5 0x00000004 /* RW--V */ | ||
1490 | #define NV_PGRAPH_BPIXEL_DEPTH3_R5G6B5 0x00000005 /* RW--V */ | ||
1491 | #define NV_PGRAPH_BPIXEL_DEPTH3_Y16 0x00000006 /* RW--V */ | ||
1492 | #define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ | ||
1493 | #define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ | ||
1494 | #define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ | ||
1495 | #define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ | ||
1496 | #define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ | ||
1497 | #define NV_PGRAPH_BPIXEL_DEPTH3_A8R8G8B8 0x0000000c /* RW--V */ | ||
1498 | #define NV_PGRAPH_BPIXEL_DEPTH3_Y32 0x0000000d /* RW--V */ | ||
1499 | #define NV_PGRAPH_BPIXEL_DEPTH3_V8YB8U8YA8 0x0000000e /* RW--V */ | ||
1500 | #define NV_PGRAPH_BPIXEL_DEPTH3_YB8V8YA8U8 0x0000000f /* RW--V */ | ||
1501 | #define NV_PGRAPH_BPIXEL_DEPTH4 19:16 /* RWIVF */ | ||
1502 | #define NV_PGRAPH_BPIXEL_DEPTH4_INVALID 0x00000000 /* RWI-V */ | ||
1503 | #define NV_PGRAPH_BPIXEL_DEPTH4_Y8 0x00000001 /* RW--V */ | ||
1504 | #define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ | ||
1505 | #define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ | ||
1506 | #define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5 0x00000004 /* RW--V */ | ||
1507 | #define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5 0x00000005 /* RW--V */ | ||
1508 | #define NV_PGRAPH_BPIXEL_DEPTH4_Y16 0x00000006 /* RW--V */ | ||
1509 | #define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ | ||
1510 | #define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ | ||
1511 | #define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ | ||
1512 | #define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ | ||
1513 | #define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ | ||
1514 | #define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8 0x0000000c /* RW--V */ | ||
1515 | #define NV_PGRAPH_BPIXEL_DEPTH4_Y32 0x0000000d /* RW--V */ | ||
1516 | #define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8 0x0000000e /* RW--V */ | ||
1517 | #define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8 0x0000000f /* RW--V */ | ||
1518 | #define NV_PGRAPH_BPIXEL_DEPTH5 23:20 /* RWIVF */ | ||
1519 | #define NV_PGRAPH_BPIXEL_DEPTH5_INVALID 0x00000000 /* RWI-V */ | ||
1520 | #define NV_PGRAPH_BPIXEL_DEPTH5_Y8 0x00000001 /* RW--V */ | ||
1521 | #define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ | ||
1522 | #define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ | ||
1523 | #define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5 0x00000004 /* RW--V */ | ||
1524 | #define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5 0x00000005 /* RW--V */ | ||
1525 | #define NV_PGRAPH_BPIXEL_DEPTH5_Y16 0x00000006 /* RW--V */ | ||
1526 | #define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ | ||
1527 | #define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ | ||
1528 | #define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ | ||
1529 | #define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ | ||
1530 | #define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ | ||
1531 | #define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8 0x0000000c /* RW--V */ | ||
1532 | #define NV_PGRAPH_BPIXEL_DEPTH5_Y32 0x0000000d /* RW--V */ | ||
1533 | #define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8 0x0000000e /* RW--V */ | ||
1534 | #define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8 0x0000000f /* RW--V */ | ||
1535 | #define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 /* RW-4R */ | ||
1536 | #define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS 23:0 /* RWIVF */ | ||
1537 | #define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x00000000 /* RWI-V */ | ||
1538 | #define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT 29:29 /* RWIVF */ | ||
1539 | #define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x00000000 /* RWI-V */ | ||
1540 | #define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x00000001 /* RW--V */ | ||
1541 | #define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30:30 /* RWIVF */ | ||
1542 | #define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ | ||
1543 | #define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x00000001 /* RW--V */ | ||
1544 | #define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31:31 /* RWIVF */ | ||
1545 | #define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ | ||
1546 | #define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x00000001 /* RW--V */ | ||
1547 | #define NV_PGRAPH_LIMIT_VIOL_Z 0x00400614 /* RW-4R */ | ||
1548 | #define NV_PGRAPH_LIMIT_VIOL_Z_ADRS 23:0 /* RWIVF */ | ||
1549 | #define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x00000000 /* RWI-V */ | ||
1550 | #define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT 30:30 /* RWIVF */ | ||
1551 | #define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ | ||
1552 | #define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x00000001 /* RW--V */ | ||
1553 | #define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31:31 /* RWIVF */ | ||
1554 | #define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ | ||
1555 | #define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x00000001 /* RW--V */ | ||
1556 | #define NV_PGRAPH_STATE 0x00400710 /* RW-4R */ | ||
1557 | #define NV_PGRAPH_STATE_BUFFER_0 0:0 /* RWIVF */ | ||
1558 | #define NV_PGRAPH_STATE_BUFFER_0_INVALID 0x00000000 /* RWI-V */ | ||
1559 | #define NV_PGRAPH_STATE_BUFFER_0_VALID 0x00000001 /* RW--V */ | ||
1560 | #define NV_PGRAPH_STATE_BUFFER_1 1:1 /* RWIVF */ | ||
1561 | #define NV_PGRAPH_STATE_BUFFER_1_INVALID 0x00000000 /* RWI-V */ | ||
1562 | #define NV_PGRAPH_STATE_BUFFER_1_VALID 0x00000001 /* RW--V */ | ||
1563 | #define NV_PGRAPH_STATE_BUFFER_2 2:2 /* RWIVF */ | ||
1564 | #define NV_PGRAPH_STATE_BUFFER_2_INVALID 0x00000000 /* RWI-V */ | ||
1565 | #define NV_PGRAPH_STATE_BUFFER_2_VALID 0x00000001 /* RW--V */ | ||
1566 | #define NV_PGRAPH_STATE_BUFFER_3 3:3 /* RWIVF */ | ||
1567 | #define NV_PGRAPH_STATE_BUFFER_3_INVALID 0x00000000 /* RWI-V */ | ||
1568 | #define NV_PGRAPH_STATE_BUFFER_3_VALID 0x00000001 /* RW--V */ | ||
1569 | #define NV_PGRAPH_STATE_BUFFER_4 4:4 /* RWIVF */ | ||
1570 | #define NV_PGRAPH_STATE_BUFFER_4_INVALID 0x00000000 /* RWI-V */ | ||
1571 | #define NV_PGRAPH_STATE_BUFFER_4_VALID 0x00000001 /* RW--V */ | ||
1572 | #define NV_PGRAPH_STATE_BUFFER_5 5:5 /* RWIVF */ | ||
1573 | #define NV_PGRAPH_STATE_BUFFER_5_INVALID 0x00000000 /* RWI-V */ | ||
1574 | #define NV_PGRAPH_STATE_BUFFER_5_VALID 0x00000001 /* RW--V */ | ||
1575 | #define NV_PGRAPH_STATE_PITCH_0 8:8 /* RWIVF */ | ||
1576 | #define NV_PGRAPH_STATE_PITCH_0_INVALID 0x00000000 /* RWI-V */ | ||
1577 | #define NV_PGRAPH_STATE_PITCH_0_VALID 0x00000001 /* RW--V */ | ||
1578 | #define NV_PGRAPH_STATE_PITCH_1 9:9 /* RWIVF */ | ||
1579 | #define NV_PGRAPH_STATE_PITCH_1_INVALID 0x00000000 /* RWI-V */ | ||
1580 | #define NV_PGRAPH_STATE_PITCH_1_VALID 0x00000001 /* RW--V */ | ||
1581 | #define NV_PGRAPH_STATE_PITCH_2 10:10 /* RWIVF */ | ||
1582 | #define NV_PGRAPH_STATE_PITCH_2_INVALID 0x00000000 /* RWI-V */ | ||
1583 | #define NV_PGRAPH_STATE_PITCH_2_VALID 0x00000001 /* RW--V */ | ||
1584 | #define NV_PGRAPH_STATE_PITCH_3 11:11 /* RWIVF */ | ||
1585 | #define NV_PGRAPH_STATE_PITCH_3_INVALID 0x00000000 /* RWI-V */ | ||
1586 | #define NV_PGRAPH_STATE_PITCH_3_VALID 0x00000001 /* RW--V */ | ||
1587 | #define NV_PGRAPH_STATE_PITCH_4 12:12 /* RWIVF */ | ||
1588 | #define NV_PGRAPH_STATE_PITCH_4_INVALID 0x00000000 /* RWI-V */ | ||
1589 | #define NV_PGRAPH_STATE_PITCH_4_VALID 0x00000001 /* RW--V */ | ||
1590 | #define NV_PGRAPH_STATE_CHROMA_COLOR 16:16 /* RWIVF */ | ||
1591 | #define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x00000000 /* RWI-V */ | ||
1592 | #define NV_PGRAPH_STATE_CHROMA_COLOR_VALID 0x00000001 /* RW--V */ | ||
1593 | #define NV_PGRAPH_STATE_CHROMA_COLORFMT 17:17 /* RWIVF */ | ||
1594 | #define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x00000000 /* RWI-V */ | ||
1595 | #define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x00000001 /* RW--V */ | ||
1596 | #define NV_PGRAPH_STATE_CPATTERN_COLORFMT 20:20 /* RWIVF */ | ||
1597 | #define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x00000000 /* RWI-V */ | ||
1598 | #define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x00000001 /* RW--V */ | ||
1599 | #define NV_PGRAPH_STATE_CPATTERN_MONOFMT 21:21 /* RWIVF */ | ||
1600 | #define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x00000000 /* RWI-V */ | ||
1601 | #define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x00000001 /* RW--V */ | ||
1602 | #define NV_PGRAPH_STATE_CPATTERN_SELECT 22:22 /* RWIVF */ | ||
1603 | #define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x00000000 /* RWI-V */ | ||
1604 | #define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x00000001 /* RW--V */ | ||
1605 | #define NV_PGRAPH_STATE_PATTERN_COLOR0 24:24 /* RWIVF */ | ||
1606 | #define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x00000000 /* RWI-V */ | ||
1607 | #define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x00000001 /* RW--V */ | ||
1608 | #define NV_PGRAPH_STATE_PATTERN_COLOR1 25:25 /* RWIVF */ | ||
1609 | #define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x00000000 /* RWI-V */ | ||
1610 | #define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x00000001 /* RW--V */ | ||
1611 | #define NV_PGRAPH_STATE_PATTERN_PATT0 26:26 /* RWIVF */ | ||
1612 | #define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x00000000 /* RWI-V */ | ||
1613 | #define NV_PGRAPH_STATE_PATTERN_PATT0_VALID 0x00000001 /* RW--V */ | ||
1614 | #define NV_PGRAPH_STATE_PATTERN_PATT1 27:27 /* RWIVF */ | ||
1615 | #define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x00000000 /* RWI-V */ | ||
1616 | #define NV_PGRAPH_STATE_PATTERN_PATT1_VALID 0x00000001 /* RW--V */ | ||
1617 | #define NV_PGRAPH_CACHE_INDEX 0x00400728 /* RW-4R */ | ||
1618 | #define NV_PGRAPH_CACHE_INDEX_BANK 2:2 /* RWXVF */ | ||
1619 | #define NV_PGRAPH_CACHE_INDEX_BANK_10 0x00000000 /* RW--V */ | ||
1620 | #define NV_PGRAPH_CACHE_INDEX_BANK_32 0x00000001 /* RW--V */ | ||
1621 | #define NV_PGRAPH_CACHE_INDEX_ADRS 12:3 /* RWXVF */ | ||
1622 | #define NV_PGRAPH_CACHE_INDEX_ADRS_0 0x00000000 /* RW--V */ | ||
1623 | #define NV_PGRAPH_CACHE_INDEX_ADRS_1024 0x00000400 /* RW--V */ | ||
1624 | #define NV_PGRAPH_CACHE_INDEX_OP 14:13 /* RWXVF */ | ||
1625 | #define NV_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x00000000 /* RW--V */ | ||
1626 | #define NV_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x00000001 /* RW--V */ | ||
1627 | #define NV_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x00000002 /* RW--V */ | ||
1628 | #define NV_PGRAPH_CACHE_RAM 0x0040072c /* RW-4R */ | ||
1629 | #define NV_PGRAPH_CACHE_RAM_VALUE 31:0 /* RWXVF */ | ||
1630 | #define NV_PGRAPH_DMA_PITCH 0x00400760 /* RW-4R */ | ||
1631 | #define NV_PGRAPH_DMA_PITCH_S0 15:0 /* RWXSF */ | ||
1632 | #define NV_PGRAPH_DMA_PITCH_S1 31:16 /* RWXSF */ | ||
1633 | #define NV_PGRAPH_DVD_COLORFMT 0x00400764 /* RW-4R */ | ||
1634 | #define NV_PGRAPH_DVD_COLORFMT_IMAGE 5:0 /* RWNVF */ | ||
1635 | #define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 /* RWN-V */ | ||
1636 | #define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ | ||
1637 | #define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ | ||
1638 | #define NV_PGRAPH_DVD_COLORFMT_OVLY 9:8 /* RWNVF */ | ||
1639 | #define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 /* RWN-V */ | ||
1640 | #define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 /* RW--V */ | ||
1641 | #define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 /* RW--V */ | ||
1642 | #define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 /* RW--V */ | ||
1643 | #define NV_PGRAPH_SCALED_FORMAT 0x00400768 /* RW-4R */ | ||
1644 | #define NV_PGRAPH_SCALED_FORMAT_ORIGIN 17:16 /* RWIVF */ | ||
1645 | #define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x00000000 /* RWI-V */ | ||
1646 | #define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* RW--V */ | ||
1647 | #define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* RW--V */ | ||
1648 | #define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24:24 /* RWIVF */ | ||
1649 | #define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* RWI-V */ | ||
1650 | #define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* RW--V */ | ||
1651 | #define NV_PGRAPH_PATT_COLOR0 0x00400800 /* RW-4R */ | ||
1652 | #define NV_PGRAPH_PATT_COLOR0_VALUE 31:0 /* RWXUF */ | ||
1653 | #define NV_PGRAPH_PATT_COLOR1 0x00400804 /* RW-4R */ | ||
1654 | #define NV_PGRAPH_PATT_COLOR1_VALUE 31:0 /* RWXUF */ | ||
1655 | #define NV_PGRAPH_PATT_COLORRAM(i) (0x00400900+(i)*4) /* R--4A */ | ||
1656 | #define NV_PGRAPH_PATT_COLORRAM__SIZE_1 64 /* */ | ||
1657 | #define NV_PGRAPH_PATT_COLORRAM_VALUE 23:0 /* R--UF */ | ||
1658 | #define NV_PGRAPH_PATTERN(i) (0x00400808+(i)*4) /* RW-4A */ | ||
1659 | #define NV_PGRAPH_PATTERN__SIZE_1 2 /* */ | ||
1660 | #define NV_PGRAPH_PATTERN_BITMAP 31:0 /* RWXVF */ | ||
1661 | #define NV_PGRAPH_PATTERN_SHAPE 0x00400810 /* RW-4R */ | ||
1662 | #define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */ | ||
1663 | #define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x00000000 /* RW--V */ | ||
1664 | #define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x00000001 /* RW--V */ | ||
1665 | #define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x00000002 /* RW--V */ | ||
1666 | #define NV_PGRAPH_PATTERN_SHAPE_SELECT 4:4 /* RWXVF */ | ||
1667 | #define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x00000000 /* RW--V */ | ||
1668 | #define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x00000001 /* RW--V */ | ||
1669 | #define NV_PGRAPH_MONO_COLOR0 0x00400600 /* RW-4R */ | ||
1670 | #define NV_PGRAPH_MONO_COLOR0_VALUE 31:0 /* RWXUF */ | ||
1671 | #define NV_PGRAPH_ROP3 0x00400604 /* RW-4R */ | ||
1672 | #define NV_PGRAPH_ROP3_VALUE 7:0 /* RWXVF */ | ||
1673 | #define NV_PGRAPH_CHROMA 0x00400814 /* RW-4R */ | ||
1674 | #define NV_PGRAPH_CHROMA_VALUE 31:0 /* RWXUF */ | ||
1675 | #define NV_PGRAPH_BETA_AND 0x00400608 /* RW-4R */ | ||
1676 | #define NV_PGRAPH_BETA_AND_VALUE_FRACTION 30:23 /* RWXUF */ | ||
1677 | #define NV_PGRAPH_BETA_PREMULT 0x0040060c /* RW-4R */ | ||
1678 | #define NV_PGRAPH_BETA_PREMULT_VALUE 31:0 /* RWXUF */ | ||
1679 | #define NV_PGRAPH_CONTROL0 0x00400818 /* RW-4R */ | ||
1680 | #define NV_PGRAPH_CONTROL1 0x0040081c /* RW-4R */ | ||
1681 | #define NV_PGRAPH_CONTROL2 0x00400820 /* RW-4R */ | ||
1682 | #define NV_PGRAPH_BLEND 0x00400824 /* RW-4R */ | ||
1683 | #define NV_PGRAPH_DPRAM_INDEX 0x00400828 /* RW-4R */ | ||
1684 | #define NV_PGRAPH_DPRAM_INDEX_ADRS 6:0 /* RWIVF */ | ||
1685 | #define NV_PGRAPH_DPRAM_INDEX_ADRS_0 0x00000000 /* RWI-V */ | ||
1686 | #define NV_PGRAPH_DPRAM_INDEX_SELECT 10:8 /* RWIVF */ | ||
1687 | #define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x00000000 /* RWI-V */ | ||
1688 | #define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x00000001 /* RW--V */ | ||
1689 | #define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x00000002 /* RW--V */ | ||
1690 | #define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x00000003 /* RW--V */ | ||
1691 | #define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x00000004 /* RW--V */ | ||
1692 | #define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x00000005 /* RW--V */ | ||
1693 | #define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x00000006 /* RW--V */ | ||
1694 | #define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x00000007 /* RW--V */ | ||
1695 | #define NV_PGRAPH_DPRAM_DATA 0x0040082c /* RW-4R */ | ||
1696 | #define NV_PGRAPH_DPRAM_DATA_VALUE 31:0 /* RWXVF */ | ||
1697 | #define NV_PGRAPH_DPRAM_ADRS_0 0x0040082c /* RW-4R */ | ||
1698 | #define NV_PGRAPH_DPRAM_ADRS_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ | ||
1699 | #define NV_PGRAPH_DPRAM_ADRS_0_VALUE 19:0 /* RWXVF */ | ||
1700 | #define NV_PGRAPH_DPRAM_ADRS_1 0x0040082c /* RW-4R */ | ||
1701 | #define NV_PGRAPH_DPRAM_ADRS_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ | ||
1702 | #define NV_PGRAPH_DPRAM_ADRS_1_VALUE 19:0 /* RWXVF */ | ||
1703 | #define NV_PGRAPH_DPRAM_DATA_0 0x0040082c /* RW-4R */ | ||
1704 | #define NV_PGRAPH_DPRAM_DATA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ | ||
1705 | #define NV_PGRAPH_DPRAM_DATA_0_VALUE 31:0 /* RWXVF */ | ||
1706 | #define NV_PGRAPH_DPRAM_DATA_1 0x0040082c /* RW-4R */ | ||
1707 | #define NV_PGRAPH_DPRAM_DATA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ | ||
1708 | #define NV_PGRAPH_DPRAM_DATA_1_VALUE 31:0 /* RWXVF */ | ||
1709 | #define NV_PGRAPH_DPRAM_WE_0 0x0040082c /* RW-4R */ | ||
1710 | #define NV_PGRAPH_DPRAM_WE_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ | ||
1711 | #define NV_PGRAPH_DPRAM_WE_0_VALUE 23:0 /* RWXVF */ | ||
1712 | #define NV_PGRAPH_DPRAM_WE_1 0x0040082c /* RW-4R */ | ||
1713 | #define NV_PGRAPH_DPRAM_WE_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ | ||
1714 | #define NV_PGRAPH_DPRAM_WE_1_VALUE 23:0 /* RWXVF */ | ||
1715 | #define NV_PGRAPH_DPRAM_ALPHA_0 0x0040082c /* RW-4R */ | ||
1716 | #define NV_PGRAPH_DPRAM_ALPHA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ | ||
1717 | #define NV_PGRAPH_DPRAM_ALPHA_0_VALUE 31:0 /* RWXVF */ | ||
1718 | #define NV_PGRAPH_DPRAM_ALPHA_1 0x0040082c /* RW-4R */ | ||
1719 | #define NV_PGRAPH_DPRAM_ALPHA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ | ||
1720 | #define NV_PGRAPH_DPRAM_ALPHA_1_VALUE 31:0 /* RWXVF */ | ||
1721 | #define NV_PGRAPH_STORED_FMT 0x00400830 /* RW-4R */ | ||
1722 | #define NV_PGRAPH_STORED_FMT_MONO0 5:0 /* RWXVF */ | ||
1723 | #define NV_PGRAPH_STORED_FMT_PATT0 13:8 /* RWXVF */ | ||
1724 | #define NV_PGRAPH_STORED_FMT_PATT1 21:16 /* RWXVF */ | ||
1725 | #define NV_PGRAPH_STORED_FMT_CHROMA 29:24 /* RWXVF */ | ||
1726 | #define NV_PGRAPH_FORMATS 0x00400618 /* RW-4R */ | ||
1727 | #define NV_PGRAPH_FORMATS_ROP 2:0 /* R-XVF */ | ||
1728 | #define NV_PGRAPH_FORMATS_ROP_Y8 0x00000000 /* -W--V */ | ||
1729 | #define NV_PGRAPH_FORMATS_ROP_RGB15 0x00000001 /* -W--V */ | ||
1730 | #define NV_PGRAPH_FORMATS_ROP_RGB16 0x00000002 /* -W--V */ | ||
1731 | #define NV_PGRAPH_FORMATS_ROP_Y16 0x00000003 /* -W--V */ | ||
1732 | #define NV_PGRAPH_FORMATS_ROP_INVALID 0x00000004 /* -W--V */ | ||
1733 | #define NV_PGRAPH_FORMATS_ROP_RGB24 0x00000005 /* -W--V */ | ||
1734 | #define NV_PGRAPH_FORMATS_ROP_RGB30 0x00000006 /* -W--V */ | ||
1735 | #define NV_PGRAPH_FORMATS_ROP_Y32 0x00000007 /* -W--V */ | ||
1736 | #define NV_PGRAPH_FORMATS_SRC 9:4 /* R-XVF */ | ||
1737 | #define NV_PGRAPH_FORMATS_SRC_INVALID 0x00000000 /* RW--V */ | ||
1738 | #define NV_PGRAPH_FORMATS_SRC_LE_Y8 0x00000001 /* RW--V */ | ||
1739 | #define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x00000002 /* RW--V */ | ||
1740 | #define NV_PGRAPH_FORMATS_SRC_LE_X24Y8 0x00000003 /* RW--V */ | ||
1741 | #define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x00000006 /* RW--V */ | ||
1742 | #define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x00000007 /* RW--V */ | ||
1743 | #define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x00000008 /* RW--V */ | ||
1744 | #define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x00000009 /* RW--V */ | ||
1745 | #define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5 0x0000000A /* RW--V */ | ||
1746 | #define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0x0000000B /* RW--V */ | ||
1747 | #define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0x0000000C /* RW--V */ | ||
1748 | #define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0x0000000D /* RW--V */ | ||
1749 | #define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0x0000000E /* RW--V */ | ||
1750 | #define NV_PGRAPH_FORMATS_SRC_LE_Y16 0x0000000F /* RW--V */ | ||
1751 | #define NV_PGRAPH_FORMATS_SRC_LE_A16Y16 0x00000010 /* RW--V */ | ||
1752 | #define NV_PGRAPH_FORMATS_SRC_LE_X16Y16 0x00000011 /* RW--V */ | ||
1753 | #define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x00000012 /* RW--V */ | ||
1754 | #define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x00000013 /* RW--V */ | ||
1755 | #define NV_PGRAPH_FORMATS_SRC_LE_Y32 0x00000014 /* RW--V */ | ||
1756 | #define NV_PGRAPH_FORMATS_FB 15:12 /* R-XVF */ | ||
1757 | #define NV_PGRAPH_FORMATS_FB_INVALID 0x00000000 /* RWI-V */ | ||
1758 | #define NV_PGRAPH_FORMATS_FB_Y8 0x00000001 /* RW--V */ | ||
1759 | #define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ | ||
1760 | #define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ | ||
1761 | #define NV_PGRAPH_FORMATS_FB_A1R5G5B5 0x00000004 /* RW--V */ | ||
1762 | #define NV_PGRAPH_FORMATS_FB_R5G6B5 0x00000005 /* RW--V */ | ||
1763 | #define NV_PGRAPH_FORMATS_FB_Y16 0x00000006 /* RW--V */ | ||
1764 | #define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ | ||
1765 | #define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ | ||
1766 | #define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ | ||
1767 | #define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ | ||
1768 | #define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ | ||
1769 | #define NV_PGRAPH_FORMATS_FB_A8R8G8B8 0x0000000c /* RW--V */ | ||
1770 | #define NV_PGRAPH_FORMATS_FB_Y32 0x0000000d /* RW--V */ | ||
1771 | #define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8 0x0000000e /* RW--V */ | ||
1772 | #define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8 0x0000000f /* RW--V */ | ||
1773 | #define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */ | ||
1774 | #define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */ | ||
1775 | #define NV_PGRAPH_ABS_X_RAM_VALUE 31:0 /* RWXUF */ | ||
1776 | #define NV_PGRAPH_X_RAM_BPORT(i) (0x00400c00+(i)*4) /* R--4A */ | ||
1777 | #define NV_PGRAPH_X_RAM_BPORT__SIZE_1 32 /* */ | ||
1778 | #define NV_PGRAPH_X_RAM_BPORT_VALUE 31:0 /* R--UF */ | ||
1779 | #define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */ | ||
1780 | #define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */ | ||
1781 | #define NV_PGRAPH_ABS_Y_RAM_VALUE 31:0 /* RWXUF */ | ||
1782 | #define NV_PGRAPH_Y_RAM_BPORT(i) (0x00400c80+(i)*4) /* R--4A */ | ||
1783 | #define NV_PGRAPH_Y_RAM_BPORT__SIZE_1 32 /* */ | ||
1784 | #define NV_PGRAPH_Y_RAM_BPORT_VALUE 31:0 /* R--UF */ | ||
1785 | #define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */ | ||
1786 | #define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER 17:0 /* RWBUF */ | ||
1787 | #define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x00000000 /* RWB-V */ | ||
1788 | #define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20:20 /* RWVVF */ | ||
1789 | #define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x00000000 /* RWV-V */ | ||
1790 | #define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x00000001 /* RW--V */ | ||
1791 | #define NV_PGRAPH_XY_LOGIC_MISC0_INDEX 31:28 /* RWBUF */ | ||
1792 | #define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x00000000 /* RWB-V */ | ||
1793 | #define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */ | ||
1794 | #define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL 0:0 /* RWNVF */ | ||
1795 | #define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x00000000 /* RWN-V */ | ||
1796 | #define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x00000001 /* RW--V */ | ||
1797 | #define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4:4 /* RWIVF */ | ||
1798 | #define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ | ||
1799 | #define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x00000001 /* RW--V */ | ||
1800 | #define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5:5 /* RWIVF */ | ||
1801 | #define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ | ||
1802 | #define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x00000001 /* RW--V */ | ||
1803 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12:12 /* RWIVF */ | ||
1804 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x00000000 /* RWI-V */ | ||
1805 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ | ||
1806 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16:16 /* RWIVF */ | ||
1807 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x00000000 /* RWI-V */ | ||
1808 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ | ||
1809 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20:20 /* RWIVF */ | ||
1810 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ | ||
1811 | #define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ | ||
1812 | #define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */ | ||
1813 | #define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0:0 /* RWIVF */ | ||
1814 | #define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x00000000 /* RWI-V */ | ||
1815 | #define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x00000001 /* RW--V */ | ||
1816 | #define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4:4 /* RWIVF */ | ||
1817 | #define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ | ||
1818 | #define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x00000001 /* RW--V */ | ||
1819 | #define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5:5 /* RWIVF */ | ||
1820 | #define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ | ||
1821 | #define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x00000001 /* RW--V */ | ||
1822 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12:12 /* RWIVF */ | ||
1823 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x00000000 /* RWI-V */ | ||
1824 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ | ||
1825 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16:16 /* RWIVF */ | ||
1826 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x00000000 /* RWI-V */ | ||
1827 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ | ||
1828 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20:20 /* RWIVF */ | ||
1829 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ | ||
1830 | #define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ | ||
1831 | #define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */ | ||
1832 | #define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0:0 /* RWXVF */ | ||
1833 | #define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x00000000 /* RW--V */ | ||
1834 | #define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x00000001 /* RW--V */ | ||
1835 | #define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4:4 /* RWXVF */ | ||
1836 | #define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x00000000 /* RW--V */ | ||
1837 | #define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x00000001 /* RW--V */ | ||
1838 | #define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8:8 /* RWIVF */ | ||
1839 | #define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x00000000 /* RWI-V */ | ||
1840 | #define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x00000001 /* RW--V */ | ||
1841 | #define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12:12 /* RWIVF */ | ||
1842 | #define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x00000000 /* RWI-V */ | ||
1843 | #define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x00000001 /* RW--V */ | ||
1844 | #define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 22:16 /* RWXUF */ | ||
1845 | #define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x00000000 /* RW--V */ | ||
1846 | #define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 30:24 /* RWXUF */ | ||
1847 | #define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x00000000 /* RW--V */ | ||
1848 | #define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */ | ||
1849 | #define NV_PGRAPH_X_MISC_BIT33_0 0:0 /* RWNVF */ | ||
1850 | #define NV_PGRAPH_X_MISC_BIT33_0_0 0x00000000 /* RWN-V */ | ||
1851 | #define NV_PGRAPH_X_MISC_BIT33_1 1:1 /* RWNVF */ | ||
1852 | #define NV_PGRAPH_X_MISC_BIT33_1_0 0x00000000 /* RWN-V */ | ||
1853 | #define NV_PGRAPH_X_MISC_BIT33_2 2:2 /* RWNVF */ | ||
1854 | #define NV_PGRAPH_X_MISC_BIT33_2_0 0x00000000 /* RWN-V */ | ||
1855 | #define NV_PGRAPH_X_MISC_BIT33_3 3:3 /* RWNVF */ | ||
1856 | #define NV_PGRAPH_X_MISC_BIT33_3_0 0x00000000 /* RWN-V */ | ||
1857 | #define NV_PGRAPH_X_MISC_RANGE_0 4:4 /* RWNVF */ | ||
1858 | #define NV_PGRAPH_X_MISC_RANGE_0_0 0x00000000 /* RWN-V */ | ||
1859 | #define NV_PGRAPH_X_MISC_RANGE_1 5:5 /* RWNVF */ | ||
1860 | #define NV_PGRAPH_X_MISC_RANGE_1_0 0x00000000 /* RWN-V */ | ||
1861 | #define NV_PGRAPH_X_MISC_RANGE_2 6:6 /* RWNVF */ | ||
1862 | #define NV_PGRAPH_X_MISC_RANGE_2_0 0x00000000 /* RWN-V */ | ||
1863 | #define NV_PGRAPH_X_MISC_RANGE_3 7:7 /* RWNVF */ | ||
1864 | #define NV_PGRAPH_X_MISC_RANGE_3_0 0x00000000 /* RWN-V */ | ||
1865 | #define NV_PGRAPH_X_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ | ||
1866 | #define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ | ||
1867 | #define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ | ||
1868 | #define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ | ||
1869 | #define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */ | ||
1870 | #define NV_PGRAPH_Y_MISC_BIT33_0 0:0 /* RWNVF */ | ||
1871 | #define NV_PGRAPH_Y_MISC_BIT33_0_0 0x00000000 /* RWN-V */ | ||
1872 | #define NV_PGRAPH_Y_MISC_BIT33_1 1:1 /* RWNVF */ | ||
1873 | #define NV_PGRAPH_Y_MISC_BIT33_1_0 0x00000000 /* RWN-V */ | ||
1874 | #define NV_PGRAPH_Y_MISC_BIT33_2 2:2 /* RWNVF */ | ||
1875 | #define NV_PGRAPH_Y_MISC_BIT33_2_0 0x00000000 /* RWN-V */ | ||
1876 | #define NV_PGRAPH_Y_MISC_BIT33_3 3:3 /* RWNVF */ | ||
1877 | #define NV_PGRAPH_Y_MISC_BIT33_3_0 0x00000000 /* RWN-V */ | ||
1878 | #define NV_PGRAPH_Y_MISC_RANGE_0 4:4 /* RWNVF */ | ||
1879 | #define NV_PGRAPH_Y_MISC_RANGE_0_0 0x00000000 /* RWN-V */ | ||
1880 | #define NV_PGRAPH_Y_MISC_RANGE_1 5:5 /* RWNVF */ | ||
1881 | #define NV_PGRAPH_Y_MISC_RANGE_1_0 0x00000000 /* RWN-V */ | ||
1882 | #define NV_PGRAPH_Y_MISC_RANGE_2 6:6 /* RWNVF */ | ||
1883 | #define NV_PGRAPH_Y_MISC_RANGE_2_0 0x00000000 /* RWN-V */ | ||
1884 | #define NV_PGRAPH_Y_MISC_RANGE_3 7:7 /* RWNVF */ | ||
1885 | #define NV_PGRAPH_Y_MISC_RANGE_3_0 0x00000000 /* RWN-V */ | ||
1886 | #define NV_PGRAPH_Y_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ | ||
1887 | #define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ | ||
1888 | #define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ | ||
1889 | #define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ | ||
1890 | #define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */ | ||
1891 | #define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE 15:0 /* RWXSF */ | ||
1892 | #define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */ | ||
1893 | #define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE 17:0 /* RWXSF */ | ||
1894 | #define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */ | ||
1895 | #define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE 15:0 /* RWXSF */ | ||
1896 | #define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */ | ||
1897 | #define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE 17:0 /* RWXSF */ | ||
1898 | #define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */ | ||
1899 | #define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE 15:0 /* RWXSF */ | ||
1900 | #define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */ | ||
1901 | #define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE 17:0 /* RWXSF */ | ||
1902 | #define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */ | ||
1903 | #define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE 15:0 /* RWXSF */ | ||
1904 | #define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */ | ||
1905 | #define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE 17:0 /* RWXSF */ | ||
1906 | #define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */ | ||
1907 | #define NV_PGRAPH_SOURCE_COLOR_VALUE 31:0 /* RWNVF */ | ||
1908 | #define NV_PGRAPH_SOURCE_COLOR_VALUE_0 0x00000000 /* RWN-V */ | ||
1909 | #define NV_PGRAPH_VALID1 0x00400508 /* RW-4R */ | ||
1910 | #define NV_PGRAPH_VALID1_VLD 22:0 /* RWNVF */ | ||
1911 | #define NV_PGRAPH_VALID1_VLD_0 0x00000000 /* RWN-V */ | ||
1912 | #define NV_PGRAPH_VALID1_CLIP_MIN 28:28 /* RWIVF */ | ||
1913 | #define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x00000000 /* RWI-V */ | ||
1914 | #define NV_PGRAPH_VALID1_CLIP_MIN_ONLY 0x00000001 /* RW--V */ | ||
1915 | #define NV_PGRAPH_VALID1_CLIPA_MIN 29:29 /* RWIVF */ | ||
1916 | #define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x00000000 /* RWI-V */ | ||
1917 | #define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x00000001 /* RW--V */ | ||
1918 | #define NV_PGRAPH_VALID1_CLIP_MAX 30:30 /* RWIVF */ | ||
1919 | #define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x00000000 /* RWI-V */ | ||
1920 | #define NV_PGRAPH_VALID1_CLIP_MAX_ONLY 0x00000001 /* RW--V */ | ||
1921 | #define NV_PGRAPH_VALID1_CLIPA_MAX 31:31 /* RWIVF */ | ||
1922 | #define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x00000000 /* RWI-V */ | ||
1923 | #define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x00000001 /* RW--V */ | ||
1924 | #define NV_PGRAPH_VALID2 0x00400578 /* RW-4R */ | ||
1925 | #define NV_PGRAPH_VALID2_VLD2 28:0 /* RWNVF */ | ||
1926 | #define NV_PGRAPH_VALID2_VLD2_0 0x00000000 /* RWN-V */ | ||
1927 | #define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */ | ||
1928 | #define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE 17:0 /* RWXSF */ | ||
1929 | #define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */ | ||
1930 | #define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE 17:0 /* RWXSF */ | ||
1931 | #define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */ | ||
1932 | #define NV_PGRAPH_CLIPX_0_CLIP0_MIN 1:0 /* RWNVF */ | ||
1933 | #define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ | ||
1934 | #define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ | ||
1935 | #define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ | ||
1936 | #define NV_PGRAPH_CLIPX_0_CLIP0_MAX 3:2 /* RWNVF */ | ||
1937 | #define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ | ||
1938 | #define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ | ||
1939 | #define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ | ||
1940 | #define NV_PGRAPH_CLIPX_0_CLIP1_MIN 5:4 /* RWNVF */ | ||
1941 | #define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ | ||
1942 | #define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ | ||
1943 | #define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ | ||
1944 | #define NV_PGRAPH_CLIPX_0_CLIP1_MAX 7:6 /* RWNVF */ | ||
1945 | #define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ | ||
1946 | #define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ | ||
1947 | #define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ | ||
1948 | #define NV_PGRAPH_CLIPX_0_CLIP2_MIN 9:8 /* RWNVF */ | ||
1949 | #define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ | ||
1950 | #define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ | ||
1951 | #define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ | ||
1952 | #define NV_PGRAPH_CLIPX_0_CLIP2_MAX 11:10 /* RWNVF */ | ||
1953 | #define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ | ||
1954 | #define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ | ||
1955 | #define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ | ||
1956 | #define NV_PGRAPH_CLIPX_0_CLIP3_MIN 13:12 /* RWNVF */ | ||
1957 | #define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ | ||
1958 | #define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ | ||
1959 | #define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ | ||
1960 | #define NV_PGRAPH_CLIPX_0_CLIP3_MAX 15:14 /* RWNVF */ | ||
1961 | #define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ | ||
1962 | #define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ | ||
1963 | #define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ | ||
1964 | #define NV_PGRAPH_CLIPX_0_CLIP4_MIN 17:16 /* RWNVF */ | ||
1965 | #define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ | ||
1966 | #define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ | ||
1967 | #define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ | ||
1968 | #define NV_PGRAPH_CLIPX_0_CLIP4_MAX 19:18 /* RWNVF */ | ||
1969 | #define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ | ||
1970 | #define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ | ||
1971 | #define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ | ||
1972 | #define NV_PGRAPH_CLIPX_0_CLIP5_MIN 21:20 /* RWNVF */ | ||
1973 | #define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ | ||
1974 | #define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ | ||
1975 | #define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ | ||
1976 | #define NV_PGRAPH_CLIPX_0_CLIP5_MAX 23:22 /* RWNVF */ | ||
1977 | #define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ | ||
1978 | #define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ | ||
1979 | #define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ | ||
1980 | #define NV_PGRAPH_CLIPX_0_CLIP6_MIN 25:24 /* RWNVF */ | ||
1981 | #define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ | ||
1982 | #define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ | ||
1983 | #define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ | ||
1984 | #define NV_PGRAPH_CLIPX_0_CLIP6_MAX 27:26 /* RWNVF */ | ||
1985 | #define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ | ||
1986 | #define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ | ||
1987 | #define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ | ||
1988 | #define NV_PGRAPH_CLIPX_0_CLIP7_MIN 29:28 /* RWNVF */ | ||
1989 | #define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ | ||
1990 | #define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ | ||
1991 | #define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ | ||
1992 | #define NV_PGRAPH_CLIPX_0_CLIP7_MAX 31:30 /* RWNVF */ | ||
1993 | #define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ | ||
1994 | #define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ | ||
1995 | #define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ | ||
1996 | #define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */ | ||
1997 | #define NV_PGRAPH_CLIPX_1_CLIP8_MIN 1:0 /* RWNVF */ | ||
1998 | #define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ | ||
1999 | #define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ | ||
2000 | #define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ | ||
2001 | #define NV_PGRAPH_CLIPX_1_CLIP8_MAX 3:2 /* RWNVF */ | ||
2002 | #define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ | ||
2003 | #define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ | ||
2004 | #define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ | ||
2005 | #define NV_PGRAPH_CLIPX_1_CLIP9_MIN 5:4 /* RWNVF */ | ||
2006 | #define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ | ||
2007 | #define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ | ||
2008 | #define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ | ||
2009 | #define NV_PGRAPH_CLIPX_1_CLIP9_MAX 7:6 /* RWNVF */ | ||
2010 | #define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ | ||
2011 | #define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ | ||
2012 | #define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ | ||
2013 | #define NV_PGRAPH_CLIPX_1_CLIP10_MIN 9:8 /* RWNVF */ | ||
2014 | #define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ | ||
2015 | #define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ | ||
2016 | #define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ | ||
2017 | #define NV_PGRAPH_CLIPX_1_CLIP10_MAX 11:10 /* RWNVF */ | ||
2018 | #define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ | ||
2019 | #define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ | ||
2020 | #define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ | ||
2021 | #define NV_PGRAPH_CLIPX_1_CLIP11_MIN 13:12 /* RWNVF */ | ||
2022 | #define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ | ||
2023 | #define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ | ||
2024 | #define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ | ||
2025 | #define NV_PGRAPH_CLIPX_1_CLIP11_MAX 15:14 /* RWNVF */ | ||
2026 | #define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ | ||
2027 | #define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ | ||
2028 | #define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ | ||
2029 | #define NV_PGRAPH_CLIPX_1_CLIP12_MIN 17:16 /* RWNVF */ | ||
2030 | #define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ | ||
2031 | #define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ | ||
2032 | #define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ | ||
2033 | #define NV_PGRAPH_CLIPX_1_CLIP12_MAX 19:18 /* RWNVF */ | ||
2034 | #define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ | ||
2035 | #define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ | ||
2036 | #define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ | ||
2037 | #define NV_PGRAPH_CLIPX_1_CLIP13_MIN 21:20 /* RWNVF */ | ||
2038 | #define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ | ||
2039 | #define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ | ||
2040 | #define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ | ||
2041 | #define NV_PGRAPH_CLIPX_1_CLIP13_MAX 23:22 /* RWNVF */ | ||
2042 | #define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ | ||
2043 | #define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ | ||
2044 | #define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ | ||
2045 | #define NV_PGRAPH_CLIPX_1_CLIP14_MIN 25:24 /* RWNVF */ | ||
2046 | #define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ | ||
2047 | #define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ | ||
2048 | #define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ | ||
2049 | #define NV_PGRAPH_CLIPX_1_CLIP14_MAX 27:26 /* RWNVF */ | ||
2050 | #define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ | ||
2051 | #define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ | ||
2052 | #define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ | ||
2053 | #define NV_PGRAPH_CLIPX_1_CLIP15_MIN 29:28 /* RWNVF */ | ||
2054 | #define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ | ||
2055 | #define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ | ||
2056 | #define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ | ||
2057 | #define NV_PGRAPH_CLIPX_1_CLIP15_MAX 31:30 /* RWNVF */ | ||
2058 | #define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ | ||
2059 | #define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ | ||
2060 | #define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ | ||
2061 | #define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */ | ||
2062 | #define NV_PGRAPH_CLIPY_0_CLIP0_MIN 1:0 /* RWNVF */ | ||
2063 | #define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ | ||
2064 | #define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ | ||
2065 | #define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ | ||
2066 | #define NV_PGRAPH_CLIPY_0_CLIP0_MAX 3:2 /* RWNVF */ | ||
2067 | #define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ | ||
2068 | #define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ | ||
2069 | #define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ | ||
2070 | #define NV_PGRAPH_CLIPY_0_CLIP1_MIN 5:4 /* RWNVF */ | ||
2071 | #define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ | ||
2072 | #define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ | ||
2073 | #define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ | ||
2074 | #define NV_PGRAPH_CLIPY_0_CLIP1_MAX 7:6 /* RWNVF */ | ||
2075 | #define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ | ||
2076 | #define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ | ||
2077 | #define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ | ||
2078 | #define NV_PGRAPH_CLIPY_0_CLIP2_MIN 9:8 /* RWNVF */ | ||
2079 | #define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ | ||
2080 | #define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ | ||
2081 | #define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ | ||
2082 | #define NV_PGRAPH_CLIPY_0_CLIP2_MAX 11:10 /* RWNVF */ | ||
2083 | #define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ | ||
2084 | #define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ | ||
2085 | #define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ | ||
2086 | #define NV_PGRAPH_CLIPY_0_CLIP3_MIN 13:12 /* RWNVF */ | ||
2087 | #define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ | ||
2088 | #define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ | ||
2089 | #define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ | ||
2090 | #define NV_PGRAPH_CLIPY_0_CLIP3_MAX 15:14 /* RWNVF */ | ||
2091 | #define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ | ||
2092 | #define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ | ||
2093 | #define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ | ||
2094 | #define NV_PGRAPH_CLIPY_0_CLIP4_MIN 17:16 /* RWNVF */ | ||
2095 | #define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ | ||
2096 | #define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ | ||
2097 | #define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ | ||
2098 | #define NV_PGRAPH_CLIPY_0_CLIP4_MAX 19:18 /* RWNVF */ | ||
2099 | #define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ | ||
2100 | #define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ | ||
2101 | #define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ | ||
2102 | #define NV_PGRAPH_CLIPY_0_CLIP5_MIN 21:20 /* RWNVF */ | ||
2103 | #define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ | ||
2104 | #define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ | ||
2105 | #define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ | ||
2106 | #define NV_PGRAPH_CLIPY_0_CLIP5_MAX 23:22 /* RWNVF */ | ||
2107 | #define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ | ||
2108 | #define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ | ||
2109 | #define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ | ||
2110 | #define NV_PGRAPH_CLIPY_0_CLIP6_MIN 25:24 /* RWNVF */ | ||
2111 | #define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ | ||
2112 | #define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ | ||
2113 | #define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ | ||
2114 | #define NV_PGRAPH_CLIPY_0_CLIP6_MAX 27:26 /* RWNVF */ | ||
2115 | #define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ | ||
2116 | #define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ | ||
2117 | #define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ | ||
2118 | #define NV_PGRAPH_CLIPY_0_CLIP7_MIN 29:28 /* RWNVF */ | ||
2119 | #define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ | ||
2120 | #define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ | ||
2121 | #define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ | ||
2122 | #define NV_PGRAPH_CLIPY_0_CLIP7_MAX 31:30 /* RWNVF */ | ||
2123 | #define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ | ||
2124 | #define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ | ||
2125 | #define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ | ||
2126 | #define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */ | ||
2127 | #define NV_PGRAPH_CLIPY_1_CLIP8_MIN 1:0 /* RWNVF */ | ||
2128 | #define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ | ||
2129 | #define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ | ||
2130 | #define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ | ||
2131 | #define NV_PGRAPH_CLIPY_1_CLIP8_MAX 3:2 /* RWNVF */ | ||
2132 | #define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ | ||
2133 | #define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ | ||
2134 | #define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ | ||
2135 | #define NV_PGRAPH_CLIPY_1_CLIP9_MIN 5:4 /* RWNVF */ | ||
2136 | #define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ | ||
2137 | #define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ | ||
2138 | #define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ | ||
2139 | #define NV_PGRAPH_CLIPY_1_CLIP9_MAX 7:6 /* RWNVF */ | ||
2140 | #define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ | ||
2141 | #define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ | ||
2142 | #define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ | ||
2143 | #define NV_PGRAPH_CLIPY_1_CLIP10_MIN 9:8 /* RWNVF */ | ||
2144 | #define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ | ||
2145 | #define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ | ||
2146 | #define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ | ||
2147 | #define NV_PGRAPH_CLIPY_1_CLIP10_MAX 11:10 /* RWNVF */ | ||
2148 | #define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ | ||
2149 | #define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ | ||
2150 | #define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ | ||
2151 | #define NV_PGRAPH_CLIPY_1_CLIP11_MIN 13:12 /* RWNVF */ | ||
2152 | #define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ | ||
2153 | #define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ | ||
2154 | #define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ | ||
2155 | #define NV_PGRAPH_CLIPY_1_CLIP11_MAX 15:14 /* RWNVF */ | ||
2156 | #define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ | ||
2157 | #define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ | ||
2158 | #define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ | ||
2159 | #define NV_PGRAPH_CLIPY_1_CLIP12_MIN 17:16 /* RWNVF */ | ||
2160 | #define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ | ||
2161 | #define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ | ||
2162 | #define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ | ||
2163 | #define NV_PGRAPH_CLIPY_1_CLIP12_MAX 19:18 /* RWNVF */ | ||
2164 | #define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ | ||
2165 | #define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ | ||
2166 | #define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ | ||
2167 | #define NV_PGRAPH_CLIPY_1_CLIP13_MIN 21:20 /* RWNVF */ | ||
2168 | #define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ | ||
2169 | #define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ | ||
2170 | #define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ | ||
2171 | #define NV_PGRAPH_CLIPY_1_CLIP13_MAX 23:22 /* RWNVF */ | ||
2172 | #define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ | ||
2173 | #define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ | ||
2174 | #define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ | ||
2175 | #define NV_PGRAPH_CLIPY_1_CLIP14_MIN 25:24 /* RWNVF */ | ||
2176 | #define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ | ||
2177 | #define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ | ||
2178 | #define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ | ||
2179 | #define NV_PGRAPH_CLIPY_1_CLIP14_MAX 27:26 /* RWNVF */ | ||
2180 | #define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ | ||
2181 | #define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ | ||
2182 | #define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ | ||
2183 | #define NV_PGRAPH_CLIPY_1_CLIP15_MIN 29:28 /* RWNVF */ | ||
2184 | #define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ | ||
2185 | #define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ | ||
2186 | #define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ | ||
2187 | #define NV_PGRAPH_CLIPY_1_CLIP15_MAX 31:30 /* RWNVF */ | ||
2188 | #define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ | ||
2189 | #define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ | ||
2190 | #define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ | ||
2191 | #define NV_PGRAPH_MISC24_0 0x00400510 /* RW-4R */ | ||
2192 | #define NV_PGRAPH_MISC24_0_VALUE 23:0 /* RWXUF */ | ||
2193 | #define NV_PGRAPH_MISC24_1 0x00400570 /* RW-4R */ | ||
2194 | #define NV_PGRAPH_MISC24_1_VALUE 23:0 /* RWXUF */ | ||
2195 | #define NV_PGRAPH_MISC24_2 0x00400574 /* RW-4R */ | ||
2196 | #define NV_PGRAPH_MISC24_2_VALUE 23:0 /* RWXUF */ | ||
2197 | #define NV_PGRAPH_PASSTHRU_0 0x0040057C /* RW-4R */ | ||
2198 | #define NV_PGRAPH_PASSTHRU_0_VALUE 31:0 /* RWXUF */ | ||
2199 | #define NV_PGRAPH_PASSTHRU_1 0x00400580 /* RW-4R */ | ||
2200 | #define NV_PGRAPH_PASSTHRU_1_VALUE 31:0 /* RWXUF */ | ||
2201 | #define NV_PGRAPH_PASSTHRU_2 0x00400584 /* RW-4R */ | ||
2202 | #define NV_PGRAPH_PASSTHRU_2_VALUE 31:0 /* RWXUF */ | ||
2203 | #define NV_PGRAPH_U_RAM(i) (0x00400d00+(i)*4) /* RW-4A */ | ||
2204 | #define NV_PGRAPH_U_RAM__SIZE_1 16 /* */ | ||
2205 | #define NV_PGRAPH_U_RAM_VALUE 31:6 /* RWXFF */ | ||
2206 | #define NV_PGRAPH_V_RAM(i) (0x00400d40+(i)*4) /* RW-4A */ | ||
2207 | #define NV_PGRAPH_V_RAM__SIZE_1 16 /* */ | ||
2208 | #define NV_PGRAPH_V_RAM_VALUE 31:6 /* RWXFF */ | ||
2209 | #define NV_PGRAPH_M_RAM(i) (0x00400d80+(i)*4) /* RW-4A */ | ||
2210 | #define NV_PGRAPH_M_RAM__SIZE_1 16 /* */ | ||
2211 | #define NV_PGRAPH_M_RAM_VALUE 31:6 /* RWXFF */ | ||
2212 | #define NV_PGRAPH_DMA_START_0 0x00401000 /* RW-4R */ | ||
2213 | #define NV_PGRAPH_DMA_START_0_VALUE 31:0 /* RWXUF */ | ||
2214 | #define NV_PGRAPH_DMA_START_1 0x00401004 /* RW-4R */ | ||
2215 | #define NV_PGRAPH_DMA_START_1_VALUE 31:0 /* RWXUF */ | ||
2216 | #define NV_PGRAPH_DMA_LENGTH 0x00401008 /* RW-4R */ | ||
2217 | #define NV_PGRAPH_DMA_LENGTH_VALUE 21:0 /* RWXUF */ | ||
2218 | #define NV_PGRAPH_DMA_MISC 0x0040100C /* RW-4R */ | ||
2219 | #define NV_PGRAPH_DMA_MISC_COUNT 15:0 /* RWXUF */ | ||
2220 | #define NV_PGRAPH_DMA_MISC_FMT_SRC 18:16 /* RWXVF */ | ||
2221 | #define NV_PGRAPH_DMA_MISC_FMT_DST 22:20 /* RWXVF */ | ||
2222 | #define NV_PGRAPH_DMA_DATA_0 0x00401020 /* RW-4R */ | ||
2223 | #define NV_PGRAPH_DMA_DATA_0_VALUE 31:0 /* RWXUF */ | ||
2224 | #define NV_PGRAPH_DMA_DATA_1 0x00401024 /* RW-4R */ | ||
2225 | #define NV_PGRAPH_DMA_DATA_1_VALUE 31:0 /* RWXUF */ | ||
2226 | #define NV_PGRAPH_DMA_RM 0x00401030 /* RW-4R */ | ||
2227 | #define NV_PGRAPH_DMA_RM_ASSIST_A 0:0 /* RWIVF */ | ||
2228 | #define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x00000000 /* R-I-V */ | ||
2229 | #define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x00000001 /* R---V */ | ||
2230 | #define NV_PGRAPH_DMA_RM_ASSIST_A_RESET 0x00000001 /* -W--C */ | ||
2231 | #define NV_PGRAPH_DMA_RM_ASSIST_B 1:1 /* RWIVF */ | ||
2232 | #define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x00000000 /* R-I-V */ | ||
2233 | #define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x00000001 /* R---V */ | ||
2234 | #define NV_PGRAPH_DMA_RM_ASSIST_B_RESET 0x00000001 /* -W--C */ | ||
2235 | #define NV_PGRAPH_DMA_RM_WRITE_REQ 4:4 /* CWIVF */ | ||
2236 | #define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x00000000 /* CWI-V */ | ||
2237 | #define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x00000001 /* -W--T */ | ||
2238 | #define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040 /* RW-4R */ | ||
2239 | #define NV_PGRAPH_DMA_A_XLATE_INST_VALUE 15:0 /* RWXUF */ | ||
2240 | #define NV_PGRAPH_DMA_A_CONTROL 0x00401044 /* RW-4R */ | ||
2241 | #define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ | ||
2242 | #define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ | ||
2243 | #define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ | ||
2244 | #define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ | ||
2245 | #define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ | ||
2246 | #define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ | ||
2247 | #define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE 17:16 /* RWXUF */ | ||
2248 | #define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ | ||
2249 | #define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ | ||
2250 | #define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ | ||
2251 | #define NV_PGRAPH_DMA_A_CONTROL_ADJUST 31:20 /* RWXUF */ | ||
2252 | #define NV_PGRAPH_DMA_A_LIMIT 0x00401048 /* RW-4R */ | ||
2253 | #define NV_PGRAPH_DMA_A_LIMIT_OFFSET 31:0 /* RWXUF */ | ||
2254 | #define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C /* RW-4R */ | ||
2255 | #define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS 1:1 /* RWXVF */ | ||
2256 | #define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ | ||
2257 | #define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ | ||
2258 | #define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ | ||
2259 | #define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050 /* RW-4R */ | ||
2260 | #define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS 31:12 /* RWXUF */ | ||
2261 | #define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 /* RW-4R */ | ||
2262 | #define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ | ||
2263 | #define NV_PGRAPH_DMA_A_OFFSET 0x00401058 /* RW-4R */ | ||
2264 | #define NV_PGRAPH_DMA_A_OFFSET_VALUE 31:0 /* RWXUF */ | ||
2265 | #define NV_PGRAPH_DMA_A_SIZE 0x0040105C /* RW-4R */ | ||
2266 | #define NV_PGRAPH_DMA_A_SIZE_VALUE 24:0 /* RWXUF */ | ||
2267 | #define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060 /* RW-4R */ | ||
2268 | #define NV_PGRAPH_DMA_A_Y_SIZE_VALUE 10:0 /* RWXUF */ | ||
2269 | #define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080 /* RW-4R */ | ||
2270 | #define NV_PGRAPH_DMA_B_XLATE_INST_VALUE 15:0 /* RWXUF */ | ||
2271 | #define NV_PGRAPH_DMA_B_CONTROL 0x00401084 /* RW-4R */ | ||
2272 | #define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ | ||
2273 | #define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ | ||
2274 | #define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ | ||
2275 | #define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ | ||
2276 | #define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ | ||
2277 | #define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ | ||
2278 | #define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE 17:16 /* RWXUF */ | ||
2279 | #define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ | ||
2280 | #define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ | ||
2281 | #define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ | ||
2282 | #define NV_PGRAPH_DMA_B_CONTROL_ADJUST 31:20 /* RWXUF */ | ||
2283 | #define NV_PGRAPH_DMA_B_LIMIT 0x00401088 /* RW-4R */ | ||
2284 | #define NV_PGRAPH_DMA_B_LIMIT_OFFSET 31:0 /* RWXUF */ | ||
2285 | #define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C /* RW-4R */ | ||
2286 | #define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS 1:1 /* RWXVF */ | ||
2287 | #define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ | ||
2288 | #define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ | ||
2289 | #define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ | ||
2290 | #define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090 /* RW-4R */ | ||
2291 | #define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS 31:12 /* RWXUF */ | ||
2292 | #define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 /* RW-4R */ | ||
2293 | #define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ | ||
2294 | #define NV_PGRAPH_DMA_B_OFFSET 0x00401098 /* RW-4R */ | ||
2295 | #define NV_PGRAPH_DMA_B_OFFSET_VALUE 31:0 /* RWXUF */ | ||
2296 | #define NV_PGRAPH_DMA_B_SIZE 0x0040109C /* RW-4R */ | ||
2297 | #define NV_PGRAPH_DMA_B_SIZE_VALUE 24:0 /* RWXUF */ | ||
2298 | #define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0 /* RW-4R */ | ||
2299 | #define NV_PGRAPH_DMA_B_Y_SIZE_VALUE 10:0 /* RWXUF */ | ||
2300 | |||
2301 | /* Framebuffer registers */ | ||
2302 | #define NV_PFB 0x00100FFF:0x00100000 /* RW--D */ | ||
2303 | #define NV_PFB_BOOT_0 0x00100000 /* RW-4R */ | ||
2304 | #define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RW-VF */ | ||
2305 | #define NV_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 /* RW--V */ | ||
2306 | #define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 /* RW--V */ | ||
2307 | #define NV_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 /* RW--V */ | ||
2308 | #define NV_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 /* RW--V */ | ||
2309 | #define NV_PFB_BOOT_0_RAM_WIDTH_128 2:2 /* RW-VF */ | ||
2310 | #define NV_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x00000000 /* RW--V */ | ||
2311 | #define NV_PFB_BOOT_0_RAM_WIDTH_128_ON 0x00000001 /* RW--V */ | ||
2312 | #define NV_PFB_BOOT_0_RAM_TYPE 4:3 /* RW-VF */ | ||
2313 | #define NV_PFB_BOOT_0_RAM_TYPE_256K 0x00000000 /* RW--V */ | ||
2314 | #define NV_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x00000001 /* RW--V */ | ||
2315 | #define NV_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x00000002 /* RW--V */ | ||
2316 | #define NV_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x00000003 /* RW--V */ | ||
2317 | #define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */ | ||
2318 | #define NV_PFB_CONFIG_0_TYPE 14:0 /* RWIVF */ | ||
2319 | #define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x00000120 /* RW--V */ | ||
2320 | #define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x00000220 /* RW--V */ | ||
2321 | #define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x00000320 /* RW--V */ | ||
2322 | #define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x00004120 /* RW--V */ | ||
2323 | #define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x00004220 /* RW--V */ | ||
2324 | #define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x00004320 /* RW--V */ | ||
2325 | #define NV_PFB_CONFIG_0_TYPE_TETRIS 0x00002000 /* RW--V */ | ||
2326 | #define NV_PFB_CONFIG_0_TYPE_NOTILING 0x00001114 /* RWI-V */ | ||
2327 | #define NV_PFB_CONFIG_0_TETRIS_MODE 17:15 /* RWI-F */ | ||
2328 | #define NV_PFB_CONFIG_0_TETRIS_MODE_PASS 0x00000000 /* RWI-V */ | ||
2329 | #define NV_PFB_CONFIG_0_TETRIS_MODE_1 0x00000001 /* RW--V */ | ||
2330 | #define NV_PFB_CONFIG_0_TETRIS_MODE_2 0x00000002 /* RW--V */ | ||
2331 | #define NV_PFB_CONFIG_0_TETRIS_MODE_3 0x00000003 /* RW--V */ | ||
2332 | #define NV_PFB_CONFIG_0_TETRIS_MODE_4 0x00000004 /* RW--V */ | ||
2333 | #define NV_PFB_CONFIG_0_TETRIS_MODE_5 0x00000005 /* RW--V */ | ||
2334 | #define NV_PFB_CONFIG_0_TETRIS_MODE_6 0x00000006 /* RW--V */ | ||
2335 | #define NV_PFB_CONFIG_0_TETRIS_MODE_7 0x00000007 /* RW--V */ | ||
2336 | #define NV_PFB_CONFIG_0_TETRIS_SHIFT 19:18 /* RWI-F */ | ||
2337 | #define NV_PFB_CONFIG_0_TETRIS_SHIFT_0 0x00000000 /* RWI-V */ | ||
2338 | #define NV_PFB_CONFIG_0_TETRIS_SHIFT_1 0x00000001 /* RW--V */ | ||
2339 | #define NV_PFB_CONFIG_0_TETRIS_SHIFT_2 0x00000002 /* RW--V */ | ||
2340 | #define NV_PFB_CONFIG_0_BANK_SWAP 22:20 /* RWI-F */ | ||
2341 | #define NV_PFB_CONFIG_0_BANK_SWAP_OFF 0x00000000 /* RWI-V */ | ||
2342 | #define NV_PFB_CONFIG_0_BANK_SWAP_1M 0x00000001 /* RW--V */ | ||
2343 | #define NV_PFB_CONFIG_0_BANK_SWAP_2M 0x00000005 /* RW--V */ | ||
2344 | #define NV_PFB_CONFIG_0_BANK_SWAP_4M 0x00000007 /* RW--V */ | ||
2345 | #define NV_PFB_CONFIG_0_UNUSED 23:23 /* RW-VF */ | ||
2346 | #define NV_PFB_CONFIG_0_SCRAMBLE_EN 29:29 /* RWIVF */ | ||
2347 | #define NV_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x00000000 /* RW--V */ | ||
2348 | #define NV_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x00000001 /* RW--V */ | ||
2349 | #define NV_PFB_CONFIG_0_PRAMIN_WR 28:28 /* RWIVF */ | ||
2350 | #define NV_PFB_CONFIG_0_PRAMIN_WR_INIT 0x00000000 /* RW--V */ | ||
2351 | #define NV_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x00000001 /* RW--V */ | ||
2352 | #define NV_PFB_CONFIG_0_PRAMIN_WR_MASK 27:24 /* RWIVF */ | ||
2353 | #define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x00000000 /* RWI-V */ | ||
2354 | #define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0x0000000f /* RWI-V */ | ||
2355 | #define NV_PFB_CONFIG_1 0x00100204 /* RW-4R */ | ||
2356 | #define NV_PFB_RTL 0x00100300 /* RW-4R */ | ||
2357 | #define NV_PFB_RTL_H 0:0 /* RWIUF */ | ||
2358 | #define NV_PFB_RTL_H_DEFAULT 0x00000000 /* RWI-V */ | ||
2359 | #define NV_PFB_RTL_MC 1:1 /* RWIUF */ | ||
2360 | #define NV_PFB_RTL_MC_DEFAULT 0x00000000 /* RWI-V */ | ||
2361 | #define NV_PFB_RTL_V 2:2 /* RWIUF */ | ||
2362 | #define NV_PFB_RTL_V_DEFAULT 0x00000000 /* RWI-V */ | ||
2363 | #define NV_PFB_RTL_G 3:3 /* RWIUF */ | ||
2364 | #define NV_PFB_RTL_G_DEFAULT 0x00000000 /* RWI-V */ | ||
2365 | #define NV_PFB_RTL_GB 4:4 /* RWIUF */ | ||
2366 | #define NV_PFB_RTL_GB_DEFAULT 0x00000000 /* RWI-V */ | ||
2367 | #define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */ | ||
2368 | #define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */ | ||
2369 | #define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */ | ||
2370 | #define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */ | ||
2371 | #define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */ | ||
2372 | #define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */ | ||
2373 | #define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */ | ||
2374 | #define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */ | ||
2375 | #define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */ | ||
2376 | #define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */ | ||
2377 | #define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */ | ||
2378 | #define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */ | ||
2379 | #define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */ | ||
2380 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */ | ||
2381 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */ | ||
2382 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */ | ||
2383 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */ | ||
2384 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */ | ||
2385 | #define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */ | ||
2386 | #define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */ | ||
2387 | #define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */ | ||
2388 | #define NV_PFB_CONFIG_1_SGRAM100 3:3 /* RWIVF */ | ||
2389 | #define NV_PFB_CONFIG_1_SGRAM100_ENABLED 0x00000000 /* RWI-V */ | ||
2390 | #define NV_PFB_CONFIG_1_SGRAM100_DISABLED 0x00000001 /* RW--V */ | ||
2391 | #define NV_PFB_DEBUG_0_CKE_ALWAYSON 29:29 /* RWIVF */ | ||
2392 | #define NV_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x00000000 /* RW--V */ | ||
2393 | #define NV_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x00000001 /* RWI-V */ | ||
2394 | |||
2395 | #define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */ | ||
2396 | #define NV_PEXTDEV_BOOT_0 0x00101000 /* R--4R */ | ||
2397 | #define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0:0 /* R-XVF */ | ||
2398 | #define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x00000000 /* R---V */ | ||
2399 | #define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x00000001 /* R---V */ | ||
2400 | #define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1:1 /* R-XVF */ | ||
2401 | #define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x00000000 /* R---V */ | ||
2402 | #define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x00000001 /* R---V */ | ||
2403 | #define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 3:2 /* R-XVF */ | ||
2404 | #define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x00000000 /* R---V */ | ||
2405 | #define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x00000001 /* R---V */ | ||
2406 | #define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x00000002 /* R---V */ | ||
2407 | #define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x00000003 /* R---V */ | ||
2408 | #define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4:4 /* R-XVF */ | ||
2409 | #define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x00000000 /* R---V */ | ||
2410 | #define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x00000001 /* R---V */ | ||
2411 | #define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5:5 /* R-XVF */ | ||
2412 | #define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x00000000 /* R---V */ | ||
2413 | #define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x00000001 /* R---V */ | ||
2414 | #define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* R-XVF */ | ||
2415 | #define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x00000000 /* R---V */ | ||
2416 | #define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x00000001 /* R---V */ | ||
2417 | #define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 8:7 /* R-XVF */ | ||
2418 | #define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x00000000 /* R---V */ | ||
2419 | #define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x00000001 /* R---V */ | ||
2420 | #define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x00000002 /* R---V */ | ||
2421 | #define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x00000003 /* R---V */ | ||
2422 | #define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11:11 /* RWIVF */ | ||
2423 | #define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */ | ||
2424 | #define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */ | ||
2425 | |||
2426 | /* Extras */ | ||
2427 | #define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */ | ||
2428 | /*#define NV_PRAMIN 0x00FFFFFF:0x00C00000*/ | ||
2429 | #define NV_PNVM 0x01FFFFFF:0x01000000 /* RW--M */ | ||
2430 | /*#define NV_PNVM 0x00BFFFFF:0x00800000*/ | ||
2431 | #define NV_CHAN0 0x0080ffff:0x00800000 | ||
2432 | |||
2433 | /* FIFO subchannels */ | ||
2434 | #define NV_UROP 0x43 | ||
2435 | #define NV_UCHROMA 0x57 | ||
2436 | #define NV_UCLIP 0x19 | ||
2437 | #define NV_UPATT 0x18 | ||
2438 | #define NV_ULIN 0x5C | ||
2439 | #define NV_UTRI 0x5D | ||
2440 | #define NV_URECT 0x5E | ||
2441 | #define NV_UBLIT 0x5F | ||
2442 | #define NV_UGLYPH 0x4B | ||
2443 | |||
2444 | #endif /*__NV4REF_H__*/ | ||
2445 | |||
diff --git a/drivers/video/riva/nv_driver.c b/drivers/video/riva/nv_driver.c index be630a0ccfd..a11026812d1 100644 --- a/drivers/video/riva/nv_driver.c +++ b/drivers/video/riva/nv_driver.c | |||
@@ -231,12 +231,14 @@ unsigned long riva_get_memlen(struct riva_par *par) | |||
231 | case NV_ARCH_30: | 231 | case NV_ARCH_30: |
232 | if(chipset == NV_CHIP_IGEFORCE2) { | 232 | if(chipset == NV_CHIP_IGEFORCE2) { |
233 | 233 | ||
234 | dev = pci_find_slot(0, 1); | 234 | dev = pci_get_bus_and_slot(0, 1); |
235 | pci_read_config_dword(dev, 0x7C, &amt); | 235 | pci_read_config_dword(dev, 0x7C, &amt); |
236 | pci_dev_put(dev); | ||
236 | memlen = (((amt >> 6) & 31) + 1) * 1024; | 237 | memlen = (((amt >> 6) & 31) + 1) * 1024; |
237 | } else if (chipset == NV_CHIP_0x01F0) { | 238 | } else if (chipset == NV_CHIP_0x01F0) { |
238 | dev = pci_find_slot(0, 1); | 239 | dev = pci_get_bus_and_slot(0, 1); |
239 | pci_read_config_dword(dev, 0x84, &amt); | 240 | pci_read_config_dword(dev, 0x84, &amt); |
241 | pci_dev_put(dev); | ||
240 | memlen = (((amt >> 4) & 127) + 1) * 1024; | 242 | memlen = (((amt >> 4) & 127) + 1) * 1024; |
241 | } else { | 243 | } else { |
242 | switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & | 244 | switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & |
diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c index e0b8c521cc9..70bfd78eca8 100644 --- a/drivers/video/riva/riva_hw.c +++ b/drivers/video/riva/riva_hw.c | |||
@@ -1118,8 +1118,9 @@ static void nForceUpdateArbitrationSettings | |||
1118 | unsigned int uMClkPostDiv; | 1118 | unsigned int uMClkPostDiv; |
1119 | struct pci_dev *dev; | 1119 | struct pci_dev *dev; |
1120 | 1120 | ||
1121 | dev = pci_find_slot(0, 3); | 1121 | dev = pci_get_bus_and_slot(0, 3); |
1122 | pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); | 1122 | pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); |
1123 | pci_dev_put(dev); | ||
1123 | uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; | 1124 | uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; |
1124 | 1125 | ||
1125 | if(!uMClkPostDiv) uMClkPostDiv = 4; | 1126 | if(!uMClkPostDiv) uMClkPostDiv = 4; |
@@ -1132,8 +1133,9 @@ static void nForceUpdateArbitrationSettings | |||
1132 | sim_data.enable_video = 0; | 1133 | sim_data.enable_video = 0; |
1133 | sim_data.enable_mp = 0; | 1134 | sim_data.enable_mp = 0; |
1134 | 1135 | ||
1135 | dev = pci_find_slot(0, 1); | 1136 | dev = pci_get_bus_and_slot(0, 1); |
1136 | pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); | 1137 | pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); |
1138 | pci_dev_put(dev); | ||
1137 | sim_data.memory_type = (sim_data.memory_type >> 12) & 1; | 1139 | sim_data.memory_type = (sim_data.memory_type >> 12) & 1; |
1138 | 1140 | ||
1139 | sim_data.memory_width = 64; | 1141 | sim_data.memory_width = 64; |
@@ -2112,12 +2114,14 @@ static void nv10GetConfig | |||
2112 | * Fill in chip configuration. | 2114 | * Fill in chip configuration. |
2113 | */ | 2115 | */ |
2114 | if(chipset == NV_CHIP_IGEFORCE2) { | 2116 | if(chipset == NV_CHIP_IGEFORCE2) { |
2115 | dev = pci_find_slot(0, 1); | 2117 | dev = pci_get_bus_and_slot(0, 1); |
2116 | pci_read_config_dword(dev, 0x7C, &amt); | 2118 | pci_read_config_dword(dev, 0x7C, &amt); |
2119 | pci_dev_put(dev); | ||
2117 | chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; | 2120 | chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; |
2118 | } else if(chipset == NV_CHIP_0x01F0) { | 2121 | } else if(chipset == NV_CHIP_0x01F0) { |
2119 | dev = pci_find_slot(0, 1); | 2122 | dev = pci_get_bus_and_slot(0, 1); |
2120 | pci_read_config_dword(dev, 0x84, &amt); | 2123 | pci_read_config_dword(dev, 0x84, &amt); |
2124 | pci_dev_put(dev); | ||
2121 | chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; | 2125 | chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; |
2122 | } else { | 2126 | } else { |
2123 | switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) | 2127 | switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) |
diff --git a/drivers/video/riva/rivafb-i2c.c b/drivers/video/riva/rivafb-i2c.c index 0405e839ff9..76e6ce353c8 100644 --- a/drivers/video/riva/rivafb-i2c.c +++ b/drivers/video/riva/rivafb-i2c.c | |||
@@ -88,13 +88,16 @@ static int riva_gpio_getsda(void* data) | |||
88 | return val; | 88 | return val; |
89 | } | 89 | } |
90 | 90 | ||
91 | static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name) | 91 | static int __devinit riva_setup_i2c_bus(struct riva_i2c_chan *chan, |
92 | const char *name, | ||
93 | unsigned int i2c_class) | ||
92 | { | 94 | { |
93 | int rc; | 95 | int rc; |
94 | 96 | ||
95 | strcpy(chan->adapter.name, name); | 97 | strcpy(chan->adapter.name, name); |
96 | chan->adapter.owner = THIS_MODULE; | 98 | chan->adapter.owner = THIS_MODULE; |
97 | chan->adapter.id = I2C_HW_B_RIVA; | 99 | chan->adapter.id = I2C_HW_B_RIVA; |
100 | chan->adapter.class = i2c_class; | ||
98 | chan->adapter.algo_data = &chan->algo; | 101 | chan->adapter.algo_data = &chan->algo; |
99 | chan->adapter.dev.parent = &chan->par->pdev->dev; | 102 | chan->adapter.dev.parent = &chan->par->pdev->dev; |
100 | chan->algo.setsda = riva_gpio_setsda; | 103 | chan->algo.setsda = riva_gpio_setsda; |
@@ -124,42 +127,38 @@ static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name) | |||
124 | return rc; | 127 | return rc; |
125 | } | 128 | } |
126 | 129 | ||
127 | void riva_create_i2c_busses(struct riva_par *par) | 130 | void __devinit riva_create_i2c_busses(struct riva_par *par) |
128 | { | 131 | { |
129 | par->bus = 3; | ||
130 | |||
131 | par->chan[0].par = par; | 132 | par->chan[0].par = par; |
132 | par->chan[1].par = par; | 133 | par->chan[1].par = par; |
133 | par->chan[2].par = par; | 134 | par->chan[2].par = par; |
134 | 135 | ||
135 | par->chan[0].ddc_base = 0x3e; | 136 | par->chan[0].ddc_base = 0x36; |
136 | par->chan[1].ddc_base = 0x36; | 137 | par->chan[1].ddc_base = 0x3e; |
137 | par->chan[2].ddc_base = 0x50; | 138 | par->chan[2].ddc_base = 0x50; |
138 | riva_setup_i2c_bus(&par->chan[0], "BUS1"); | 139 | riva_setup_i2c_bus(&par->chan[0], "BUS1", I2C_CLASS_HWMON); |
139 | riva_setup_i2c_bus(&par->chan[1], "BUS2"); | 140 | riva_setup_i2c_bus(&par->chan[1], "BUS2", 0); |
140 | riva_setup_i2c_bus(&par->chan[2], "BUS3"); | 141 | riva_setup_i2c_bus(&par->chan[2], "BUS3", 0); |
141 | } | 142 | } |
142 | 143 | ||
143 | void riva_delete_i2c_busses(struct riva_par *par) | 144 | void riva_delete_i2c_busses(struct riva_par *par) |
144 | { | 145 | { |
145 | if (par->chan[0].par) | 146 | int i; |
146 | i2c_del_adapter(&par->chan[0].adapter); | ||
147 | par->chan[0].par = NULL; | ||
148 | |||
149 | if (par->chan[1].par) | ||
150 | i2c_del_adapter(&par->chan[1].adapter); | ||
151 | par->chan[1].par = NULL; | ||
152 | 147 | ||
153 | if (par->chan[2].par) | 148 | for (i = 0; i < 3; i++) { |
154 | i2c_del_adapter(&par->chan[2].adapter); | 149 | if (!par->chan[i].par) |
155 | par->chan[2].par = NULL; | 150 | continue; |
151 | i2c_del_adapter(&par->chan[i].adapter); | ||
152 | par->chan[i].par = NULL; | ||
153 | } | ||
156 | } | 154 | } |
157 | 155 | ||
158 | int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid) | 156 | int __devinit riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid) |
159 | { | 157 | { |
160 | u8 *edid = NULL; | 158 | u8 *edid = NULL; |
161 | 159 | ||
162 | edid = fb_ddc_read(&par->chan[conn-1].adapter); | 160 | if (par->chan[conn].par) |
161 | edid = fb_ddc_read(&par->chan[conn].adapter); | ||
163 | 162 | ||
164 | if (out_edid) | 163 | if (out_edid) |
165 | *out_edid = edid; | 164 | *out_edid = edid; |
diff --git a/drivers/video/riva/rivafb.h b/drivers/video/riva/rivafb.h index 48ead6d72f2..d9f107b704c 100644 --- a/drivers/video/riva/rivafb.h +++ b/drivers/video/riva/rivafb.h | |||
@@ -4,7 +4,6 @@ | |||
4 | #include <linux/fb.h> | 4 | #include <linux/fb.h> |
5 | #include <video/vga.h> | 5 | #include <video/vga.h> |
6 | #include <linux/i2c.h> | 6 | #include <linux/i2c.h> |
7 | #include <linux/i2c-id.h> | ||
8 | #include <linux/i2c-algo-bit.h> | 7 | #include <linux/i2c-algo-bit.h> |
9 | 8 | ||
10 | #include "riva_hw.h" | 9 | #include "riva_hw.h" |
@@ -61,7 +60,6 @@ struct riva_par { | |||
61 | Bool SecondCRTC; | 60 | Bool SecondCRTC; |
62 | int FlatPanel; | 61 | int FlatPanel; |
63 | struct pci_dev *pdev; | 62 | struct pci_dev *pdev; |
64 | int bus; | ||
65 | int cursor_reset; | 63 | int cursor_reset; |
66 | #ifdef CONFIG_MTRR | 64 | #ifdef CONFIG_MTRR |
67 | struct { int vram; int vram_valid; } mtrr; | 65 | struct { int vram; int vram_valid; } mtrr; |
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 3091b20124b..756fafb41d7 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c | |||
@@ -65,7 +65,7 @@ static const struct svga_fb_format s3fb_formats[] = { | |||
65 | 65 | ||
66 | 66 | ||
67 | static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, | 67 | static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, |
68 | 60000, 240000, 14318}; | 68 | 35000, 240000, 14318}; |
69 | 69 | ||
70 | static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; | 70 | static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; |
71 | 71 | ||
@@ -164,7 +164,7 @@ MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, defau | |||
164 | static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) | 164 | static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) |
165 | { | 165 | { |
166 | const u8 *font = map->data; | 166 | const u8 *font = map->data; |
167 | u8* fb = (u8 *) info->screen_base; | 167 | u8 __iomem *fb = (u8 __iomem *) info->screen_base; |
168 | int i, c; | 168 | int i, c; |
169 | 169 | ||
170 | if ((map->width != 8) || (map->height != 16) || | 170 | if ((map->width != 8) || (map->height != 16) || |
@@ -177,20 +177,19 @@ static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) | |||
177 | fb += 2; | 177 | fb += 2; |
178 | for (i = 0; i < map->height; i++) { | 178 | for (i = 0; i < map->height; i++) { |
179 | for (c = 0; c < map->length; c++) { | 179 | for (c = 0; c < map->length; c++) { |
180 | fb[c * 4] = font[c * map->height + i]; | 180 | fb_writeb(font[c * map->height + i], fb + c * 4); |
181 | } | 181 | } |
182 | fb += 1024; | 182 | fb += 1024; |
183 | } | 183 | } |
184 | } | 184 | } |
185 | 185 | ||
186 | |||
187 | |||
188 | static struct fb_tile_ops s3fb_tile_ops = { | 186 | static struct fb_tile_ops s3fb_tile_ops = { |
189 | .fb_settile = svga_settile, | 187 | .fb_settile = svga_settile, |
190 | .fb_tilecopy = svga_tilecopy, | 188 | .fb_tilecopy = svga_tilecopy, |
191 | .fb_tilefill = svga_tilefill, | 189 | .fb_tilefill = svga_tilefill, |
192 | .fb_tileblit = svga_tileblit, | 190 | .fb_tileblit = svga_tileblit, |
193 | .fb_tilecursor = svga_tilecursor, | 191 | .fb_tilecursor = svga_tilecursor, |
192 | .fb_get_tilemax = svga_get_tilemax, | ||
194 | }; | 193 | }; |
195 | 194 | ||
196 | static struct fb_tile_ops s3fb_fast_tile_ops = { | 195 | static struct fb_tile_ops s3fb_fast_tile_ops = { |
@@ -199,6 +198,7 @@ static struct fb_tile_ops s3fb_fast_tile_ops = { | |||
199 | .fb_tilefill = svga_tilefill, | 198 | .fb_tilefill = svga_tilefill, |
200 | .fb_tileblit = svga_tileblit, | 199 | .fb_tileblit = svga_tileblit, |
201 | .fb_tilecursor = svga_tilecursor, | 200 | .fb_tilecursor = svga_tilecursor, |
201 | .fb_get_tilemax = svga_get_tilemax, | ||
202 | }; | 202 | }; |
203 | 203 | ||
204 | 204 | ||
@@ -326,8 +326,13 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock) | |||
326 | { | 326 | { |
327 | u16 m, n, r; | 327 | u16 m, n, r; |
328 | u8 regval; | 328 | u8 regval; |
329 | int rv; | ||
329 | 330 | ||
330 | svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); | 331 | rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); |
332 | if (rv < 0) { | ||
333 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); | ||
334 | return; | ||
335 | } | ||
331 | 336 | ||
332 | /* Set VGA misc register */ | 337 | /* Set VGA misc register */ |
333 | regval = vga_r(NULL, VGA_MIS_R); | 338 | regval = vga_r(NULL, VGA_MIS_R); |
@@ -449,6 +454,10 @@ static int s3fb_set_par(struct fb_info *info) | |||
449 | info->flags &= ~FBINFO_MISC_TILEBLITTING; | 454 | info->flags &= ~FBINFO_MISC_TILEBLITTING; |
450 | info->tileops = NULL; | 455 | info->tileops = NULL; |
451 | 456 | ||
457 | /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ | ||
458 | info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); | ||
459 | info->pixmap.blit_y = ~(u32)0; | ||
460 | |||
452 | offset_value = (info->var.xres_virtual * bpp) / 64; | 461 | offset_value = (info->var.xres_virtual * bpp) / 64; |
453 | screen_size = info->var.yres_virtual * info->fix.line_length; | 462 | screen_size = info->var.yres_virtual * info->fix.line_length; |
454 | } else { | 463 | } else { |
@@ -458,6 +467,10 @@ static int s3fb_set_par(struct fb_info *info) | |||
458 | info->flags |= FBINFO_MISC_TILEBLITTING; | 467 | info->flags |= FBINFO_MISC_TILEBLITTING; |
459 | info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; | 468 | info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; |
460 | 469 | ||
470 | /* supports 8x16 tiles only */ | ||
471 | info->pixmap.blit_x = 1 << (8 - 1); | ||
472 | info->pixmap.blit_y = 1 << (16 - 1); | ||
473 | |||
461 | offset_value = info->var.xres_virtual / 16; | 474 | offset_value = info->var.xres_virtual / 16; |
462 | screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; | 475 | screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; |
463 | } | 476 | } |
@@ -656,7 +669,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
656 | value = ((value * hmul) / 8) - 5; | 669 | value = ((value * hmul) / 8) - 5; |
657 | vga_wcrt(NULL, 0x3C, (value + 1) / 2); | 670 | vga_wcrt(NULL, 0x3C, (value + 1) / 2); |
658 | 671 | ||
659 | memset((u8*)info->screen_base, 0x00, screen_size); | 672 | memset_io(info->screen_base, 0x00, screen_size); |
660 | /* Device and screen back on */ | 673 | /* Device and screen back on */ |
661 | svga_wcrt_mask(0x17, 0x80, 0x80); | 674 | svga_wcrt_mask(0x17, 0x80, 0x80); |
662 | svga_wseq_mask(0x01, 0x00, 0x20); | 675 | svga_wseq_mask(0x01, 0x00, 0x20); |
@@ -699,7 +712,7 @@ static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |||
699 | break; | 712 | break; |
700 | case 16: | 713 | case 16: |
701 | if (regno >= 16) | 714 | if (regno >= 16) |
702 | return -EINVAL; | 715 | return 0; |
703 | 716 | ||
704 | if (fb->var.green.length == 5) | 717 | if (fb->var.green.length == 5) |
705 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | | 718 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | |
@@ -712,9 +725,9 @@ static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |||
712 | case 24: | 725 | case 24: |
713 | case 32: | 726 | case 32: |
714 | if (regno >= 16) | 727 | if (regno >= 16) |
715 | return -EINVAL; | 728 | return 0; |
716 | 729 | ||
717 | ((u32*)fb->pseudo_palette)[regno] = ((transp & 0xFF00) << 16) | ((red & 0xFF00) << 8) | | 730 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | |
718 | (green & 0xFF00) | ((blue & 0xFF00) >> 8); | 731 | (green & 0xFF00) | ((blue & 0xFF00) >> 8); |
719 | break; | 732 | break; |
720 | default: | 733 | default: |
@@ -767,12 +780,6 @@ static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |||
767 | 780 | ||
768 | unsigned int offset; | 781 | unsigned int offset; |
769 | 782 | ||
770 | /* Validate the offsets */ | ||
771 | if ((var->xoffset + var->xres) > var->xres_virtual) | ||
772 | return -EINVAL; | ||
773 | if ((var->yoffset + var->yres) > var->yres_virtual) | ||
774 | return -EINVAL; | ||
775 | |||
776 | /* Calculate the offset */ | 783 | /* Calculate the offset */ |
777 | if (var->bits_per_pixel == 0) { | 784 | if (var->bits_per_pixel == 0) { |
778 | offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2); | 785 | offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2); |
@@ -789,6 +796,23 @@ static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |||
789 | return 0; | 796 | return 0; |
790 | } | 797 | } |
791 | 798 | ||
799 | /* Get capabilities of accelerator based on the mode */ | ||
800 | |||
801 | static void s3fb_get_caps(struct fb_info *info, struct fb_blit_caps *caps, | ||
802 | struct fb_var_screeninfo *var) | ||
803 | { | ||
804 | if (var->bits_per_pixel == 0) { | ||
805 | /* can only support 256 8x16 bitmap */ | ||
806 | caps->x = 1 << (8 - 1); | ||
807 | caps->y = 1 << (16 - 1); | ||
808 | caps->len = 256; | ||
809 | } else { | ||
810 | caps->x = ~(u32)0; | ||
811 | caps->y = ~(u32)0; | ||
812 | caps->len = ~(u32)0; | ||
813 | } | ||
814 | } | ||
815 | |||
792 | /* ------------------------------------------------------------------------- */ | 816 | /* ------------------------------------------------------------------------- */ |
793 | 817 | ||
794 | /* Frame buffer operations */ | 818 | /* Frame buffer operations */ |
@@ -805,6 +829,7 @@ static struct fb_ops s3fb_ops = { | |||
805 | .fb_fillrect = s3fb_fillrect, | 829 | .fb_fillrect = s3fb_fillrect, |
806 | .fb_copyarea = cfb_copyarea, | 830 | .fb_copyarea = cfb_copyarea, |
807 | .fb_imageblit = s3fb_imageblit, | 831 | .fb_imageblit = s3fb_imageblit, |
832 | .fb_get_caps = s3fb_get_caps, | ||
808 | }; | 833 | }; |
809 | 834 | ||
810 | /* ------------------------------------------------------------------------- */ | 835 | /* ------------------------------------------------------------------------- */ |
@@ -1061,6 +1086,7 @@ static int s3_pci_resume(struct pci_dev* dev) | |||
1061 | { | 1086 | { |
1062 | struct fb_info *info = pci_get_drvdata(dev); | 1087 | struct fb_info *info = pci_get_drvdata(dev); |
1063 | struct s3fb_info *par = info->par; | 1088 | struct s3fb_info *par = info->par; |
1089 | int err; | ||
1064 | 1090 | ||
1065 | dev_info(&(dev->dev), "resume\n"); | 1091 | dev_info(&(dev->dev), "resume\n"); |
1066 | 1092 | ||
@@ -1075,7 +1101,13 @@ static int s3_pci_resume(struct pci_dev* dev) | |||
1075 | 1101 | ||
1076 | pci_set_power_state(dev, PCI_D0); | 1102 | pci_set_power_state(dev, PCI_D0); |
1077 | pci_restore_state(dev); | 1103 | pci_restore_state(dev); |
1078 | pci_enable_device(dev); | 1104 | err = pci_enable_device(dev); |
1105 | if (err) { | ||
1106 | mutex_unlock(&(par->open_lock)); | ||
1107 | release_console_sem(); | ||
1108 | dev_err(&(dev->dev), "error %d enabling device for resume\n", err); | ||
1109 | return err; | ||
1110 | } | ||
1079 | pci_set_master(dev); | 1111 | pci_set_master(dev); |
1080 | 1112 | ||
1081 | s3fb_set_par(info); | 1113 | s3fb_set_par(info); |
diff --git a/drivers/video/savage/savagefb-i2c.c b/drivers/video/savage/savagefb-i2c.c index 8db066ccca6..35c1ce62b21 100644 --- a/drivers/video/savage/savagefb-i2c.c +++ b/drivers/video/savage/savagefb-i2c.c | |||
@@ -41,10 +41,6 @@ | |||
41 | #define SAVAGE4_I2C_SCL_IN 0x00000008 | 41 | #define SAVAGE4_I2C_SCL_IN 0x00000008 |
42 | #define SAVAGE4_I2C_SDA_IN 0x00000010 | 42 | #define SAVAGE4_I2C_SDA_IN 0x00000010 |
43 | 43 | ||
44 | #define SET_CR_IX(base, val) writeb((val), base + 0x8000 + VGA_CR_IX) | ||
45 | #define SET_CR_DATA(base, val) writeb((val), base + 0x8000 + VGA_CR_DATA) | ||
46 | #define GET_CR_DATA(base) readb(base + 0x8000 + VGA_CR_DATA) | ||
47 | |||
48 | static void savage4_gpio_setscl(void *data, int val) | 44 | static void savage4_gpio_setscl(void *data, int val) |
49 | { | 45 | { |
50 | struct savagefb_i2c_chan *chan = data; | 46 | struct savagefb_i2c_chan *chan = data; |
@@ -92,15 +88,15 @@ static void prosavage_gpio_setscl(void* data, int val) | |||
92 | struct savagefb_i2c_chan *chan = data; | 88 | struct savagefb_i2c_chan *chan = data; |
93 | u32 r; | 89 | u32 r; |
94 | 90 | ||
95 | SET_CR_IX(chan->ioaddr, chan->reg); | 91 | r = VGArCR(chan->reg, chan->par); |
96 | r = GET_CR_DATA(chan->ioaddr); | ||
97 | r |= PROSAVAGE_I2C_ENAB; | 92 | r |= PROSAVAGE_I2C_ENAB; |
98 | if (val) { | 93 | if (val) { |
99 | r |= PROSAVAGE_I2C_SCL_OUT; | 94 | r |= PROSAVAGE_I2C_SCL_OUT; |
100 | } else { | 95 | } else { |
101 | r &= ~PROSAVAGE_I2C_SCL_OUT; | 96 | r &= ~PROSAVAGE_I2C_SCL_OUT; |
102 | } | 97 | } |
103 | SET_CR_DATA(chan->ioaddr, r); | 98 | |
99 | VGAwCR(chan->reg, r, chan->par); | ||
104 | } | 100 | } |
105 | 101 | ||
106 | static void prosavage_gpio_setsda(void* data, int val) | 102 | static void prosavage_gpio_setsda(void* data, int val) |
@@ -108,31 +104,29 @@ static void prosavage_gpio_setsda(void* data, int val) | |||
108 | struct savagefb_i2c_chan *chan = data; | 104 | struct savagefb_i2c_chan *chan = data; |
109 | unsigned int r; | 105 | unsigned int r; |
110 | 106 | ||
111 | SET_CR_IX(chan->ioaddr, chan->reg); | 107 | r = VGArCR(chan->reg, chan->par); |
112 | r = GET_CR_DATA(chan->ioaddr); | ||
113 | r |= PROSAVAGE_I2C_ENAB; | 108 | r |= PROSAVAGE_I2C_ENAB; |
114 | if (val) { | 109 | if (val) { |
115 | r |= PROSAVAGE_I2C_SDA_OUT; | 110 | r |= PROSAVAGE_I2C_SDA_OUT; |
116 | } else { | 111 | } else { |
117 | r &= ~PROSAVAGE_I2C_SDA_OUT; | 112 | r &= ~PROSAVAGE_I2C_SDA_OUT; |
118 | } | 113 | } |
119 | SET_CR_DATA(chan->ioaddr, r); | 114 | |
115 | VGAwCR(chan->reg, r, chan->par); | ||
120 | } | 116 | } |
121 | 117 | ||
122 | static int prosavage_gpio_getscl(void* data) | 118 | static int prosavage_gpio_getscl(void* data) |
123 | { | 119 | { |
124 | struct savagefb_i2c_chan *chan = data; | 120 | struct savagefb_i2c_chan *chan = data; |
125 | 121 | ||
126 | SET_CR_IX(chan->ioaddr, chan->reg); | 122 | return (VGArCR(chan->reg, chan->par) & PROSAVAGE_I2C_SCL_IN) ? 1 : 0; |
127 | return (0 != (GET_CR_DATA(chan->ioaddr) & PROSAVAGE_I2C_SCL_IN)); | ||
128 | } | 123 | } |
129 | 124 | ||
130 | static int prosavage_gpio_getsda(void* data) | 125 | static int prosavage_gpio_getsda(void* data) |
131 | { | 126 | { |
132 | struct savagefb_i2c_chan *chan = data; | 127 | struct savagefb_i2c_chan *chan = data; |
133 | 128 | ||
134 | SET_CR_IX(chan->ioaddr, chan->reg); | 129 | return (VGArCR(chan->reg, chan->par) & PROSAVAGE_I2C_SDA_IN) ? 1 : 0; |
135 | return (0 != (GET_CR_DATA(chan->ioaddr) & PROSAVAGE_I2C_SDA_IN)); | ||
136 | } | 130 | } |
137 | 131 | ||
138 | static int savage_setup_i2c_bus(struct savagefb_i2c_chan *chan, | 132 | static int savage_setup_i2c_bus(struct savagefb_i2c_chan *chan, |
diff --git a/drivers/video/savage/savagefb.h b/drivers/video/savage/savagefb.h index e648a6c0f6d..8bfdfc3c523 100644 --- a/drivers/video/savage/savagefb.h +++ b/drivers/video/savage/savagefb.h | |||
@@ -15,6 +15,8 @@ | |||
15 | #include <linux/i2c.h> | 15 | #include <linux/i2c.h> |
16 | #include <linux/i2c-id.h> | 16 | #include <linux/i2c-id.h> |
17 | #include <linux/i2c-algo-bit.h> | 17 | #include <linux/i2c-algo-bit.h> |
18 | #include <linux/mutex.h> | ||
19 | #include <video/vga.h> | ||
18 | #include "../edid.h" | 20 | #include "../edid.h" |
19 | 21 | ||
20 | #ifdef SAVAGEFB_DEBUG | 22 | #ifdef SAVAGEFB_DEBUG |
@@ -189,8 +191,12 @@ struct savagefb_par { | |||
189 | struct savagefb_i2c_chan chan; | 191 | struct savagefb_i2c_chan chan; |
190 | struct savage_reg state; | 192 | struct savage_reg state; |
191 | struct savage_reg save; | 193 | struct savage_reg save; |
194 | struct savage_reg initial; | ||
195 | struct vgastate vgastate; | ||
196 | struct mutex open_lock; | ||
192 | unsigned char *edid; | 197 | unsigned char *edid; |
193 | u32 pseudo_palette[16]; | 198 | u32 pseudo_palette[16]; |
199 | u32 open_count; | ||
194 | int paletteEnabled; | 200 | int paletteEnabled; |
195 | int pm_state; | 201 | int pm_state; |
196 | int display_type; | 202 | int display_type; |
@@ -203,7 +209,7 @@ struct savagefb_par { | |||
203 | int clock[4]; | 209 | int clock[4]; |
204 | int MCLK, REFCLK, LCDclk; | 210 | int MCLK, REFCLK, LCDclk; |
205 | struct { | 211 | struct { |
206 | u8 __iomem *vbase; | 212 | void __iomem *vbase; |
207 | u32 pbase; | 213 | u32 pbase; |
208 | u32 len; | 214 | u32 len; |
209 | #ifdef CONFIG_MTRR | 215 | #ifdef CONFIG_MTRR |
@@ -212,7 +218,7 @@ struct savagefb_par { | |||
212 | } video; | 218 | } video; |
213 | 219 | ||
214 | struct { | 220 | struct { |
215 | volatile u8 __iomem *vbase; | 221 | void __iomem *vbase; |
216 | u32 pbase; | 222 | u32 pbase; |
217 | u32 len; | 223 | u32 len; |
218 | } mmio; | 224 | } mmio; |
diff --git a/drivers/video/savage/savagefb_driver.c b/drivers/video/savage/savagefb_driver.c index 0166ec2ccf3..3d7507ad55f 100644 --- a/drivers/video/savage/savagefb_driver.c +++ b/drivers/video/savage/savagefb_driver.c | |||
@@ -1623,8 +1623,46 @@ static void savagefb_restore_state(struct fb_info *info) | |||
1623 | savagefb_blank(FB_BLANK_UNBLANK, info); | 1623 | savagefb_blank(FB_BLANK_UNBLANK, info); |
1624 | } | 1624 | } |
1625 | 1625 | ||
1626 | static int savagefb_open(struct fb_info *info, int user) | ||
1627 | { | ||
1628 | struct savagefb_par *par = info->par; | ||
1629 | |||
1630 | mutex_lock(&par->open_lock); | ||
1631 | |||
1632 | if (!par->open_count) { | ||
1633 | memset(&par->vgastate, 0, sizeof(par->vgastate)); | ||
1634 | par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS | | ||
1635 | VGA_SAVE_MODE; | ||
1636 | par->vgastate.vgabase = par->mmio.vbase + 0x8000; | ||
1637 | save_vga(&par->vgastate); | ||
1638 | savage_get_default_par(par, &par->initial); | ||
1639 | } | ||
1640 | |||
1641 | par->open_count++; | ||
1642 | mutex_unlock(&par->open_lock); | ||
1643 | return 0; | ||
1644 | } | ||
1645 | |||
1646 | static int savagefb_release(struct fb_info *info, int user) | ||
1647 | { | ||
1648 | struct savagefb_par *par = info->par; | ||
1649 | |||
1650 | mutex_lock(&par->open_lock); | ||
1651 | |||
1652 | if (par->open_count == 1) { | ||
1653 | savage_set_default_par(par, &par->initial); | ||
1654 | restore_vga(&par->vgastate); | ||
1655 | } | ||
1656 | |||
1657 | par->open_count--; | ||
1658 | mutex_unlock(&par->open_lock); | ||
1659 | return 0; | ||
1660 | } | ||
1661 | |||
1626 | static struct fb_ops savagefb_ops = { | 1662 | static struct fb_ops savagefb_ops = { |
1627 | .owner = THIS_MODULE, | 1663 | .owner = THIS_MODULE, |
1664 | .fb_open = savagefb_open, | ||
1665 | .fb_release = savagefb_release, | ||
1628 | .fb_check_var = savagefb_check_var, | 1666 | .fb_check_var = savagefb_check_var, |
1629 | .fb_set_par = savagefb_set_par, | 1667 | .fb_set_par = savagefb_set_par, |
1630 | .fb_setcolreg = savagefb_setcolreg, | 1668 | .fb_setcolreg = savagefb_setcolreg, |
@@ -2173,6 +2211,7 @@ static int __devinit savagefb_probe(struct pci_dev* dev, | |||
2173 | if (!info) | 2211 | if (!info) |
2174 | return -ENOMEM; | 2212 | return -ENOMEM; |
2175 | par = info->par; | 2213 | par = info->par; |
2214 | mutex_init(&par->open_lock); | ||
2176 | err = pci_enable_device(dev); | 2215 | err = pci_enable_device(dev); |
2177 | if (err) | 2216 | if (err) |
2178 | goto failed_enable; | 2217 | goto failed_enable; |
diff --git a/drivers/video/sis/osdef.h b/drivers/video/sis/osdef.h index d048bd39961..c1492782cb1 100644 --- a/drivers/video/sis/osdef.h +++ b/drivers/video/sis/osdef.h | |||
@@ -58,9 +58,6 @@ | |||
58 | #define SIS_LINUX_KERNEL /* Linux kernel framebuffer */ | 58 | #define SIS_LINUX_KERNEL /* Linux kernel framebuffer */ |
59 | #undef SIS_XORG_XF86 /* XFree86/X.org */ | 59 | #undef SIS_XORG_XF86 /* XFree86/X.org */ |
60 | 60 | ||
61 | #undef SIS_LINUX_KERNEL_24 | ||
62 | #undef SIS_LINUX_KERNEL_26 | ||
63 | |||
64 | #ifdef OutPortByte | 61 | #ifdef OutPortByte |
65 | #undef OutPortByte | 62 | #undef OutPortByte |
66 | #endif | 63 | #endif |
@@ -100,8 +97,6 @@ | |||
100 | #define SIS315H | 97 | #define SIS315H |
101 | #endif | 98 | #endif |
102 | 99 | ||
103 | #define SIS_LINUX_KERNEL_26 | ||
104 | |||
105 | #if !defined(SIS300) && !defined(SIS315H) | 100 | #if !defined(SIS300) && !defined(SIS315H) |
106 | #warning Neither CONFIG_FB_SIS_300 nor CONFIG_FB_SIS_315 is set | 101 | #warning Neither CONFIG_FB_SIS_300 nor CONFIG_FB_SIS_315 is set |
107 | #warning sisfb will not work! | 102 | #warning sisfb will not work! |
diff --git a/drivers/video/sis/sis.h b/drivers/video/sis/sis.h index 7d5ee2145e2..d5e2d9c2784 100644 --- a/drivers/video/sis/sis.h +++ b/drivers/video/sis/sis.h | |||
@@ -27,11 +27,7 @@ | |||
27 | #include <linux/version.h> | 27 | #include <linux/version.h> |
28 | 28 | ||
29 | #include "osdef.h" | 29 | #include "osdef.h" |
30 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) | ||
31 | #include <video/sisfb.h> | 30 | #include <video/sisfb.h> |
32 | #else | ||
33 | #include <linux/sisfb.h> | ||
34 | #endif | ||
35 | 31 | ||
36 | #include "vgatypes.h" | 32 | #include "vgatypes.h" |
37 | #include "vstruct.h" | 33 | #include "vstruct.h" |
@@ -40,33 +36,17 @@ | |||
40 | #define VER_MINOR 8 | 36 | #define VER_MINOR 8 |
41 | #define VER_LEVEL 9 | 37 | #define VER_LEVEL 9 |
42 | 38 | ||
43 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) | ||
44 | #include <linux/spinlock.h> | 39 | #include <linux/spinlock.h> |
45 | #define SIS_PCI_GET_CLASS(a, b) pci_get_class(a, b) | 40 | |
46 | #define SIS_PCI_GET_DEVICE(a,b,c) pci_get_device(a,b,c) | ||
47 | #define SIS_PCI_GET_SLOT(a,b) pci_get_slot(a,b) | ||
48 | #define SIS_PCI_PUT_DEVICE(a) pci_dev_put(a) | ||
49 | #ifdef CONFIG_COMPAT | 41 | #ifdef CONFIG_COMPAT |
50 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10) | 42 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10) |
51 | #include <linux/ioctl32.h> | 43 | #include <linux/ioctl32.h> |
52 | #define SIS_OLD_CONFIG_COMPAT | 44 | #define SIS_OLD_CONFIG_COMPAT |
53 | #else | 45 | #else |
54 | #include <linux/smp_lock.h> | ||
55 | #define SIS_NEW_CONFIG_COMPAT | 46 | #define SIS_NEW_CONFIG_COMPAT |
56 | #endif | 47 | #endif |
57 | #endif /* CONFIG_COMPAT */ | 48 | #endif /* CONFIG_COMPAT */ |
58 | #else /* 2.4 */ | 49 | |
59 | #define SIS_PCI_GET_CLASS(a, b) pci_find_class(a, b) | ||
60 | #define SIS_PCI_GET_DEVICE(a,b,c) pci_find_device(a,b,c) | ||
61 | #define SIS_PCI_GET_SLOT(a,b) pci_find_slot(a,b) | ||
62 | #define SIS_PCI_PUT_DEVICE(a) | ||
63 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,19) | ||
64 | #ifdef __x86_64__ /* Shouldn't we check for CONFIG_IA32_EMULATION here? */ | ||
65 | #include <asm/ioctl32.h> | ||
66 | #define SIS_OLD_CONFIG_COMPAT | ||
67 | #endif | ||
68 | #endif | ||
69 | #endif /* 2.4 */ | ||
70 | #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,8) | 50 | #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,8) |
71 | #define SIS_IOTYPE1 void __iomem | 51 | #define SIS_IOTYPE1 void __iomem |
72 | #define SIS_IOTYPE2 __iomem | 52 | #define SIS_IOTYPE2 __iomem |
@@ -498,26 +478,8 @@ struct sis_video_info { | |||
498 | 478 | ||
499 | struct fb_var_screeninfo default_var; | 479 | struct fb_var_screeninfo default_var; |
500 | 480 | ||
501 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) | ||
502 | struct fb_fix_screeninfo sisfb_fix; | 481 | struct fb_fix_screeninfo sisfb_fix; |
503 | u32 pseudo_palette[17]; | 482 | u32 pseudo_palette[17]; |
504 | #endif | ||
505 | |||
506 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) | ||
507 | struct display sis_disp; | ||
508 | struct display_switch sisfb_sw; | ||
509 | struct { | ||
510 | u16 red, green, blue, pad; | ||
511 | } sis_palette[256]; | ||
512 | union { | ||
513 | #ifdef FBCON_HAS_CFB16 | ||
514 | u16 cfb16[16]; | ||
515 | #endif | ||
516 | #ifdef FBCON_HAS_CFB32 | ||
517 | u32 cfb32[16]; | ||
518 | #endif | ||
519 | } sis_fbcon_cmap; | ||
520 | #endif | ||
521 | 483 | ||
522 | struct sisfb_monitor { | 484 | struct sisfb_monitor { |
523 | u16 hmin; | 485 | u16 hmin; |
@@ -538,10 +500,6 @@ struct sis_video_info { | |||
538 | 500 | ||
539 | int mni; /* Mode number index */ | 501 | int mni; /* Mode number index */ |
540 | 502 | ||
541 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) | ||
542 | int currcon; | ||
543 | #endif | ||
544 | |||
545 | unsigned long video_size; | 503 | unsigned long video_size; |
546 | unsigned long video_base; | 504 | unsigned long video_base; |
547 | unsigned long mmio_size; | 505 | unsigned long mmio_size; |
@@ -578,9 +536,6 @@ struct sis_video_info { | |||
578 | int sisfb_tvplug; | 536 | int sisfb_tvplug; |
579 | int sisfb_tvstd; | 537 | int sisfb_tvstd; |
580 | int sisfb_nocrt2rate; | 538 | int sisfb_nocrt2rate; |
581 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) | ||
582 | int sisfb_inverse; | ||
583 | #endif | ||
584 | 539 | ||
585 | u32 heapstart; /* offset */ | 540 | u32 heapstart; /* offset */ |
586 | SIS_IOTYPE1 *sisfb_heap_start; /* address */ | 541 | SIS_IOTYPE1 *sisfb_heap_start; /* address */ |
@@ -646,9 +601,7 @@ struct sis_video_info { | |||
646 | int modechanged; | 601 | int modechanged; |
647 | unsigned char modeprechange; | 602 | unsigned char modeprechange; |
648 | 603 | ||
649 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) | ||
650 | u8 sisfb_lastrates[128]; | 604 | u8 sisfb_lastrates[128]; |
651 | #endif | ||
652 | 605 | ||
653 | int newrom; | 606 | int newrom; |
654 | int haveXGIROM; | 607 | int haveXGIROM; |
diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 01197d74021..a30e1e13d8b 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c | |||
@@ -37,7 +37,6 @@ | |||
37 | #include <linux/module.h> | 37 | #include <linux/module.h> |
38 | #include <linux/moduleparam.h> | 38 | #include <linux/moduleparam.h> |
39 | #include <linux/kernel.h> | 39 | #include <linux/kernel.h> |
40 | #include <linux/smp_lock.h> | ||
41 | #include <linux/spinlock.h> | 40 | #include <linux/spinlock.h> |
42 | #include <linux/errno.h> | 41 | #include <linux/errno.h> |
43 | #include <linux/string.h> | 42 | #include <linux/string.h> |
@@ -1948,7 +1947,7 @@ sisfb_get_northbridge(int basechipid) | |||
1948 | default: return NULL; | 1947 | default: return NULL; |
1949 | } | 1948 | } |
1950 | for(i = 0; i < nbridgenum; i++) { | 1949 | for(i = 0; i < nbridgenum; i++) { |
1951 | if((pdev = SIS_PCI_GET_DEVICE(PCI_VENDOR_ID_SI, | 1950 | if((pdev = pci_get_device(PCI_VENDOR_ID_SI, |
1952 | nbridgeids[nbridgeidx+i], NULL))) | 1951 | nbridgeids[nbridgeidx+i], NULL))) |
1953 | break; | 1952 | break; |
1954 | } | 1953 | } |
@@ -4613,9 +4612,9 @@ sisfb_find_host_bridge(struct sis_video_info *ivideo, struct pci_dev *mypdev, | |||
4613 | unsigned short temp; | 4612 | unsigned short temp; |
4614 | int ret = 0; | 4613 | int ret = 0; |
4615 | 4614 | ||
4616 | while((pdev = SIS_PCI_GET_CLASS(PCI_CLASS_BRIDGE_HOST, pdev))) { | 4615 | while((pdev = pci_get_class(PCI_CLASS_BRIDGE_HOST, pdev))) { |
4617 | temp = pdev->vendor; | 4616 | temp = pdev->vendor; |
4618 | SIS_PCI_PUT_DEVICE(pdev); | 4617 | pci_dev_put(pdev); |
4619 | if(temp == pcivendor) { | 4618 | if(temp == pcivendor) { |
4620 | ret = 1; | 4619 | ret = 1; |
4621 | break; | 4620 | break; |
@@ -5154,24 +5153,24 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5154 | if(reg & 0x80) v2 |= 0x80; | 5153 | if(reg & 0x80) v2 |= 0x80; |
5155 | v2 |= 0x01; | 5154 | v2 |= 0x01; |
5156 | 5155 | ||
5157 | if((mypdev = SIS_PCI_GET_DEVICE(PCI_VENDOR_ID_SI, 0x0730, NULL))) { | 5156 | if((mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0730, NULL))) { |
5158 | SIS_PCI_PUT_DEVICE(mypdev); | 5157 | pci_dev_put(mypdev); |
5159 | if(((v2 & 0x06) == 2) || ((v2 & 0x06) == 4)) | 5158 | if(((v2 & 0x06) == 2) || ((v2 & 0x06) == 4)) |
5160 | v2 &= 0xf9; | 5159 | v2 &= 0xf9; |
5161 | v2 |= 0x08; | 5160 | v2 |= 0x08; |
5162 | v1 &= 0xfe; | 5161 | v1 &= 0xfe; |
5163 | } else { | 5162 | } else { |
5164 | mypdev = SIS_PCI_GET_DEVICE(PCI_VENDOR_ID_SI, 0x0735, NULL); | 5163 | mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0735, NULL); |
5165 | if(!mypdev) | 5164 | if(!mypdev) |
5166 | mypdev = SIS_PCI_GET_DEVICE(PCI_VENDOR_ID_SI, 0x0645, NULL); | 5165 | mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0645, NULL); |
5167 | if(!mypdev) | 5166 | if(!mypdev) |
5168 | mypdev = SIS_PCI_GET_DEVICE(PCI_VENDOR_ID_SI, 0x0650, NULL); | 5167 | mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0650, NULL); |
5169 | if(mypdev) { | 5168 | if(mypdev) { |
5170 | pci_read_config_dword(mypdev, 0x94, ®d); | 5169 | pci_read_config_dword(mypdev, 0x94, ®d); |
5171 | regd &= 0xfffffeff; | 5170 | regd &= 0xfffffeff; |
5172 | pci_write_config_dword(mypdev, 0x94, regd); | 5171 | pci_write_config_dword(mypdev, 0x94, regd); |
5173 | v1 &= 0xfe; | 5172 | v1 &= 0xfe; |
5174 | SIS_PCI_PUT_DEVICE(mypdev); | 5173 | pci_dev_put(mypdev); |
5175 | } else if(sisfb_find_host_bridge(ivideo, pdev, PCI_VENDOR_ID_SI)) { | 5174 | } else if(sisfb_find_host_bridge(ivideo, pdev, PCI_VENDOR_ID_SI)) { |
5176 | v1 &= 0xfe; | 5175 | v1 &= 0xfe; |
5177 | } else if(sisfb_find_host_bridge(ivideo, pdev, 0x1106) || | 5176 | } else if(sisfb_find_host_bridge(ivideo, pdev, 0x1106) || |
@@ -5194,13 +5193,13 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5194 | if( (!(v1 & 0x02)) && (v2 & 0x30) && (regd < 0xcf) ) | 5193 | if( (!(v1 & 0x02)) && (v2 & 0x30) && (regd < 0xcf) ) |
5195 | setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01); | 5194 | setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01); |
5196 | 5195 | ||
5197 | if((mypdev = SIS_PCI_GET_DEVICE(0x10de, 0x01e0, NULL))) { | 5196 | if((mypdev = pci_get_device(0x10de, 0x01e0, NULL))) { |
5198 | /* TODO: set CR5f &0xf1 | 0x01 for version 6570 | 5197 | /* TODO: set CR5f &0xf1 | 0x01 for version 6570 |
5199 | * of nforce 2 ROM | 5198 | * of nforce 2 ROM |
5200 | */ | 5199 | */ |
5201 | if(0) | 5200 | if(0) |
5202 | setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01); | 5201 | setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01); |
5203 | SIS_PCI_PUT_DEVICE(mypdev); | 5202 | pci_dev_put(mypdev); |
5204 | } | 5203 | } |
5205 | } | 5204 | } |
5206 | 5205 | ||
@@ -5236,9 +5235,9 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5236 | setSISIDXREG(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f); | 5235 | setSISIDXREG(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f); |
5237 | setSISIDXREG(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f); | 5236 | setSISIDXREG(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f); |
5238 | v1 = bios[0x501]; | 5237 | v1 = bios[0x501]; |
5239 | if((mypdev = SIS_PCI_GET_DEVICE(0x8086, 0x2530, NULL))) { | 5238 | if((mypdev = pci_get_device(0x8086, 0x2530, NULL))) { |
5240 | v1 = 0xf0; | 5239 | v1 = 0xf0; |
5241 | SIS_PCI_PUT_DEVICE(mypdev); | 5240 | pci_dev_put(mypdev); |
5242 | } | 5241 | } |
5243 | outSISIDXREG(SISCR, 0x77, v1); | 5242 | outSISIDXREG(SISCR, 0x77, v1); |
5244 | } | 5243 | } |
@@ -5947,7 +5946,7 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
5947 | 5946 | ||
5948 | if(!ivideo->sisvga_enabled) { | 5947 | if(!ivideo->sisvga_enabled) { |
5949 | if(pci_enable_device(pdev)) { | 5948 | if(pci_enable_device(pdev)) { |
5950 | if(ivideo->nbridge) SIS_PCI_PUT_DEVICE(ivideo->nbridge); | 5949 | if(ivideo->nbridge) pci_dev_put(ivideo->nbridge); |
5951 | pci_set_drvdata(pdev, NULL); | 5950 | pci_set_drvdata(pdev, NULL); |
5952 | kfree(sis_fb_info); | 5951 | kfree(sis_fb_info); |
5953 | return -EIO; | 5952 | return -EIO; |
@@ -5974,7 +5973,7 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
5974 | "requiring Chrontel/GPIO setup\n", | 5973 | "requiring Chrontel/GPIO setup\n", |
5975 | mychswtable[i].vendorName, | 5974 | mychswtable[i].vendorName, |
5976 | mychswtable[i].cardName); | 5975 | mychswtable[i].cardName); |
5977 | ivideo->lpcdev = SIS_PCI_GET_DEVICE(PCI_VENDOR_ID_SI, 0x0008, NULL); | 5976 | ivideo->lpcdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, NULL); |
5978 | break; | 5977 | break; |
5979 | } | 5978 | } |
5980 | i++; | 5979 | i++; |
@@ -5984,7 +5983,7 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
5984 | 5983 | ||
5985 | #ifdef CONFIG_FB_SIS_315 | 5984 | #ifdef CONFIG_FB_SIS_315 |
5986 | if((ivideo->chip == SIS_760) && (ivideo->nbridge)) { | 5985 | if((ivideo->chip == SIS_760) && (ivideo->nbridge)) { |
5987 | ivideo->lpcdev = SIS_PCI_GET_SLOT(ivideo->nbridge->bus, (2 << 3)); | 5986 | ivideo->lpcdev = pci_get_slot(ivideo->nbridge->bus, (2 << 3)); |
5988 | } | 5987 | } |
5989 | #endif | 5988 | #endif |
5990 | 5989 | ||
@@ -6149,9 +6148,9 @@ error_1: release_mem_region(ivideo->video_base, ivideo->video_size); | |||
6149 | error_2: release_mem_region(ivideo->mmio_base, ivideo->mmio_size); | 6148 | error_2: release_mem_region(ivideo->mmio_base, ivideo->mmio_size); |
6150 | error_3: vfree(ivideo->bios_abase); | 6149 | error_3: vfree(ivideo->bios_abase); |
6151 | if(ivideo->lpcdev) | 6150 | if(ivideo->lpcdev) |
6152 | SIS_PCI_PUT_DEVICE(ivideo->lpcdev); | 6151 | pci_dev_put(ivideo->lpcdev); |
6153 | if(ivideo->nbridge) | 6152 | if(ivideo->nbridge) |
6154 | SIS_PCI_PUT_DEVICE(ivideo->nbridge); | 6153 | pci_dev_put(ivideo->nbridge); |
6155 | pci_set_drvdata(pdev, NULL); | 6154 | pci_set_drvdata(pdev, NULL); |
6156 | if(!ivideo->sisvga_enabled) | 6155 | if(!ivideo->sisvga_enabled) |
6157 | pci_disable_device(pdev); | 6156 | pci_disable_device(pdev); |
@@ -6331,70 +6330,6 @@ error_3: vfree(ivideo->bios_abase); | |||
6331 | 6330 | ||
6332 | sisfb_set_vparms(ivideo); | 6331 | sisfb_set_vparms(ivideo); |
6333 | 6332 | ||
6334 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) | ||
6335 | |||
6336 | /* ---------------- For 2.4: Now switch the mode ------------------ */ | ||
6337 | |||
6338 | printk(KERN_INFO "sisfb: Setting mode %dx%dx%d (%dHz)\n", | ||
6339 | ivideo->video_width, ivideo->video_height, ivideo->video_bpp, | ||
6340 | ivideo->refresh_rate); | ||
6341 | |||
6342 | /* Determine whether or not acceleration is to be | ||
6343 | * used. Need to know before pre/post_set_mode() | ||
6344 | */ | ||
6345 | ivideo->accel = 0; | ||
6346 | ivideo->default_var.accel_flags &= ~FB_ACCELF_TEXT; | ||
6347 | if(ivideo->sisfb_accel) { | ||
6348 | ivideo->accel = -1; | ||
6349 | ivideo->default_var.accel_flags |= FB_ACCELF_TEXT; | ||
6350 | } | ||
6351 | |||
6352 | /* Now switch the mode */ | ||
6353 | sisfb_pre_setmode(ivideo); | ||
6354 | |||
6355 | if(SiSSetMode(&ivideo->SiS_Pr, ivideo->mode_no) == 0) { | ||
6356 | printk(KERN_ERR "sisfb: Fatal error: Setting mode[0x%x] failed\n", | ||
6357 | ivideo->mode_no); | ||
6358 | ret = -EINVAL; | ||
6359 | iounmap(ivideo->mmio_vbase); | ||
6360 | goto error_0; | ||
6361 | } | ||
6362 | |||
6363 | outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD); | ||
6364 | |||
6365 | sisfb_post_setmode(ivideo); | ||
6366 | |||
6367 | /* Maximize regardless of sisfb_max at startup */ | ||
6368 | ivideo->default_var.yres_virtual = 32767; | ||
6369 | |||
6370 | /* Force reset of x virtual in crtc_to_var */ | ||
6371 | ivideo->default_var.xres_virtual = 0; | ||
6372 | |||
6373 | /* Copy mode timing to var */ | ||
6374 | sisfb_crtc_to_var(ivideo, &ivideo->default_var); | ||
6375 | |||
6376 | /* Find out about screen pitch */ | ||
6377 | sisfb_calc_pitch(ivideo, &ivideo->default_var); | ||
6378 | sisfb_set_pitch(ivideo); | ||
6379 | |||
6380 | /* Init the accelerator (does nothing currently) */ | ||
6381 | sisfb_initaccel(ivideo); | ||
6382 | |||
6383 | /* Init some fbinfo entries */ | ||
6384 | sis_fb_info->node = -1; | ||
6385 | sis_fb_info->flags = FBINFO_FLAG_DEFAULT; | ||
6386 | sis_fb_info->fbops = &sisfb_ops; | ||
6387 | sis_fb_info->disp = &ivideo->sis_disp; | ||
6388 | sis_fb_info->blank = &sisfb_blank; | ||
6389 | sis_fb_info->switch_con = &sisfb_switch; | ||
6390 | sis_fb_info->updatevar = &sisfb_update_var; | ||
6391 | sis_fb_info->changevar = NULL; | ||
6392 | strcpy(sis_fb_info->fontname, sisfb_fontname); | ||
6393 | |||
6394 | sisfb_set_disp(-1, &ivideo->default_var, sis_fb_info); | ||
6395 | |||
6396 | #else /* --------- For 2.6: Setup a somewhat sane default var ------------ */ | ||
6397 | |||
6398 | printk(KERN_INFO "sisfb: Default mode is %dx%dx%d (%dHz)\n", | 6333 | printk(KERN_INFO "sisfb: Default mode is %dx%dx%d (%dHz)\n", |
6399 | ivideo->video_width, ivideo->video_height, ivideo->video_bpp, | 6334 | ivideo->video_width, ivideo->video_height, ivideo->video_bpp, |
6400 | ivideo->refresh_rate); | 6335 | ivideo->refresh_rate); |
@@ -6454,7 +6389,6 @@ error_3: vfree(ivideo->bios_abase); | |||
6454 | sis_fb_info->pseudo_palette = ivideo->pseudo_palette; | 6389 | sis_fb_info->pseudo_palette = ivideo->pseudo_palette; |
6455 | 6390 | ||
6456 | fb_alloc_cmap(&sis_fb_info->cmap, 256 , 0); | 6391 | fb_alloc_cmap(&sis_fb_info->cmap, 256 , 0); |
6457 | #endif /* 2.6 */ | ||
6458 | 6392 | ||
6459 | printk(KERN_DEBUG "sisfb: Initial vbflags 0x%x\n", (int)ivideo->vbflags); | 6393 | printk(KERN_DEBUG "sisfb: Initial vbflags 0x%x\n", (int)ivideo->vbflags); |
6460 | 6394 | ||
@@ -6564,10 +6498,10 @@ static void __devexit sisfb_remove(struct pci_dev *pdev) | |||
6564 | vfree(ivideo->bios_abase); | 6498 | vfree(ivideo->bios_abase); |
6565 | 6499 | ||
6566 | if(ivideo->lpcdev) | 6500 | if(ivideo->lpcdev) |
6567 | SIS_PCI_PUT_DEVICE(ivideo->lpcdev); | 6501 | pci_dev_put(ivideo->lpcdev); |
6568 | 6502 | ||
6569 | if(ivideo->nbridge) | 6503 | if(ivideo->nbridge) |
6570 | SIS_PCI_PUT_DEVICE(ivideo->nbridge); | 6504 | pci_dev_put(ivideo->nbridge); |
6571 | 6505 | ||
6572 | #ifdef CONFIG_MTRR | 6506 | #ifdef CONFIG_MTRR |
6573 | /* Release MTRR region */ | 6507 | /* Release MTRR region */ |
diff --git a/drivers/video/skeletonfb.c b/drivers/video/skeletonfb.c index bb96cb65fda..842b5cd054c 100644 --- a/drivers/video/skeletonfb.c +++ b/drivers/video/skeletonfb.c | |||
@@ -51,6 +51,7 @@ | |||
51 | #include <linux/delay.h> | 51 | #include <linux/delay.h> |
52 | #include <linux/fb.h> | 52 | #include <linux/fb.h> |
53 | #include <linux/init.h> | 53 | #include <linux/init.h> |
54 | #include <linux/pci.h> | ||
54 | 55 | ||
55 | /* | 56 | /* |
56 | * This is just simple sample code. | 57 | * This is just simple sample code. |
@@ -60,6 +61,11 @@ | |||
60 | */ | 61 | */ |
61 | 62 | ||
62 | /* | 63 | /* |
64 | * Driver data | ||
65 | */ | ||
66 | static char *mode_option __devinitdata; | ||
67 | |||
68 | /* | ||
63 | * If your driver supports multiple boards, you should make the | 69 | * If your driver supports multiple boards, you should make the |
64 | * below data types arrays, or allocate them dynamically (using kmalloc()). | 70 | * below data types arrays, or allocate them dynamically (using kmalloc()). |
65 | */ | 71 | */ |
@@ -78,7 +84,7 @@ struct xxx_par; | |||
78 | * if we don't use modedb. If we do use modedb see xxxfb_init how to use it | 84 | * if we don't use modedb. If we do use modedb see xxxfb_init how to use it |
79 | * to get a fb_var_screeninfo. Otherwise define a default var as well. | 85 | * to get a fb_var_screeninfo. Otherwise define a default var as well. |
80 | */ | 86 | */ |
81 | static struct fb_fix_screeninfo xxxfb_fix __initdata = { | 87 | static struct fb_fix_screeninfo xxxfb_fix __devinitdata = { |
82 | .id = "FB's name", | 88 | .id = "FB's name", |
83 | .type = FB_TYPE_PACKED_PIXELS, | 89 | .type = FB_TYPE_PACKED_PIXELS, |
84 | .visual = FB_VISUAL_PSEUDOCOLOR, | 90 | .visual = FB_VISUAL_PSEUDOCOLOR, |
@@ -142,7 +148,7 @@ int xxxfb_setup(char*); | |||
142 | * | 148 | * |
143 | * Returns negative errno on error, or zero on success. | 149 | * Returns negative errno on error, or zero on success. |
144 | */ | 150 | */ |
145 | static int xxxfb_open(const struct fb_info *info, int user) | 151 | static int xxxfb_open(struct fb_info *info, int user) |
146 | { | 152 | { |
147 | return 0; | 153 | return 0; |
148 | } | 154 | } |
@@ -161,7 +167,7 @@ static int xxxfb_open(const struct fb_info *info, int user) | |||
161 | * | 167 | * |
162 | * Returns negative errno on error, or zero on success. | 168 | * Returns negative errno on error, or zero on success. |
163 | */ | 169 | */ |
164 | static int xxxfb_release(const struct fb_info *info, int user) | 170 | static int xxxfb_release(struct fb_info *info, int user) |
165 | { | 171 | { |
166 | return 0; | 172 | return 0; |
167 | } | 173 | } |
@@ -278,7 +284,7 @@ static int xxxfb_set_par(struct fb_info *info) | |||
278 | */ | 284 | */ |
279 | static int xxxfb_setcolreg(unsigned regno, unsigned red, unsigned green, | 285 | static int xxxfb_setcolreg(unsigned regno, unsigned red, unsigned green, |
280 | unsigned blue, unsigned transp, | 286 | unsigned blue, unsigned transp, |
281 | const struct fb_info *info) | 287 | struct fb_info *info) |
282 | { | 288 | { |
283 | if (regno >= 256) /* no. of hw registers */ | 289 | if (regno >= 256) /* no. of hw registers */ |
284 | return -EINVAL; | 290 | return -EINVAL; |
@@ -416,7 +422,7 @@ static int xxxfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |||
416 | * Returns negative errno on error, or zero on success. | 422 | * Returns negative errno on error, or zero on success. |
417 | */ | 423 | */ |
418 | static int xxxfb_pan_display(struct fb_var_screeninfo *var, | 424 | static int xxxfb_pan_display(struct fb_var_screeninfo *var, |
419 | const struct fb_info *info) | 425 | struct fb_info *info) |
420 | { | 426 | { |
421 | /* | 427 | /* |
422 | * If your hardware does not support panning, _do_ _not_ implement this | 428 | * If your hardware does not support panning, _do_ _not_ implement this |
@@ -454,7 +460,7 @@ static int xxxfb_pan_display(struct fb_var_screeninfo *var, | |||
454 | * Return !0 for any modes that are unimplemented. | 460 | * Return !0 for any modes that are unimplemented. |
455 | * | 461 | * |
456 | */ | 462 | */ |
457 | static int xxxfb_blank(int blank_mode, const struct fb_info *info) | 463 | static int xxxfb_blank(int blank_mode, struct fb_info *info) |
458 | { | 464 | { |
459 | /* ... */ | 465 | /* ... */ |
460 | return 0; | 466 | return 0; |
@@ -483,7 +489,7 @@ static int xxxfb_blank(int blank_mode, const struct fb_info *info) | |||
483 | * depending on the rastering operation with the value of color which | 489 | * depending on the rastering operation with the value of color which |
484 | * is in the current color depth format. | 490 | * is in the current color depth format. |
485 | */ | 491 | */ |
486 | void xxfb_fillrect(struct fb_info *p, const struct fb_fillrect *region) | 492 | void xxxfb_fillrect(struct fb_info *p, const struct fb_fillrect *region) |
487 | { | 493 | { |
488 | /* Meaning of struct fb_fillrect | 494 | /* Meaning of struct fb_fillrect |
489 | * | 495 | * |
@@ -623,19 +629,6 @@ void xxxfb_rotate(struct fb_info *info, int angle) | |||
623 | } | 629 | } |
624 | 630 | ||
625 | /** | 631 | /** |
626 | * xxxfb_poll - NOT a required function. The purpose of this | ||
627 | * function is to provide a way for some process | ||
628 | * to wait until a specific hardware event occurs | ||
629 | * for the framebuffer device. | ||
630 | * | ||
631 | * @info: frame buffer structure that represents a single frame buffer | ||
632 | * @wait: poll table where we store process that await a event. | ||
633 | */ | ||
634 | void xxxfb_poll(struct fb_info *info, poll_table *wait) | ||
635 | { | ||
636 | } | ||
637 | |||
638 | /** | ||
639 | * xxxfb_sync - NOT a required function. Normally the accel engine | 632 | * xxxfb_sync - NOT a required function. Normally the accel engine |
640 | * for a graphics card take a specific amount of time. | 633 | * for a graphics card take a specific amount of time. |
641 | * Often we have to wait for the accelerator to finish | 634 | * Often we have to wait for the accelerator to finish |
@@ -647,21 +640,49 @@ void xxxfb_poll(struct fb_info *info, poll_table *wait) | |||
647 | * If the driver has implemented its own hardware-based drawing function, | 640 | * If the driver has implemented its own hardware-based drawing function, |
648 | * implementing this function is highly recommended. | 641 | * implementing this function is highly recommended. |
649 | */ | 642 | */ |
650 | void xxxfb_sync(struct fb_info *info) | 643 | int xxxfb_sync(struct fb_info *info) |
651 | { | 644 | { |
645 | return 0; | ||
652 | } | 646 | } |
653 | 647 | ||
654 | /* | 648 | /* |
649 | * Frame buffer operations | ||
650 | */ | ||
651 | |||
652 | static struct fb_ops xxxfb_ops = { | ||
653 | .owner = THIS_MODULE, | ||
654 | .fb_open = xxxfb_open, | ||
655 | .fb_read = xxxfb_read, | ||
656 | .fb_write = xxxfb_write, | ||
657 | .fb_release = xxxfb_release, | ||
658 | .fb_check_var = xxxfb_check_var, | ||
659 | .fb_set_par = xxxfb_set_par, | ||
660 | .fb_setcolreg = xxxfb_setcolreg, | ||
661 | .fb_blank = xxxfb_blank, | ||
662 | .fb_pan_display = xxxfb_pan_display, | ||
663 | .fb_fillrect = xxxfb_fillrect, /* Needed !!! */ | ||
664 | .fb_copyarea = xxxfb_copyarea, /* Needed !!! */ | ||
665 | .fb_imageblit = xxxfb_imageblit, /* Needed !!! */ | ||
666 | .fb_cursor = xxxfb_cursor, /* Optional !!! */ | ||
667 | .fb_rotate = xxxfb_rotate, | ||
668 | .fb_sync = xxxfb_sync, | ||
669 | .fb_ioctl = xxxfb_ioctl, | ||
670 | .fb_mmap = xxxfb_mmap, | ||
671 | }; | ||
672 | |||
673 | /* ------------------------------------------------------------------------- */ | ||
674 | |||
675 | /* | ||
655 | * Initialization | 676 | * Initialization |
656 | */ | 677 | */ |
657 | 678 | ||
658 | /* static int __init xxfb_probe (struct device *device) -- for platform devs */ | 679 | /* static int __init xxfb_probe (struct device *device) -- for platform devs */ |
659 | static int __init xxxfb_probe(struct pci_dev *dev, | 680 | static int __devinit xxxfb_probe(struct pci_dev *dev, |
660 | const_struct pci_device_id *ent) | 681 | const struct pci_device_id *ent) |
661 | { | 682 | { |
662 | struct fb_info *info; | 683 | struct fb_info *info; |
663 | struct xxx_par *par; | 684 | struct xxx_par *par; |
664 | struct device = &dev->dev; /* for pci drivers */ | 685 | struct device* device = &dev->dev; /* for pci drivers */ |
665 | int cmap_len, retval; | 686 | int cmap_len, retval; |
666 | 687 | ||
667 | /* | 688 | /* |
@@ -684,7 +705,7 @@ static int __init xxxfb_probe(struct pci_dev *dev, | |||
684 | info->screen_base = framebuffer_virtual_memory; | 705 | info->screen_base = framebuffer_virtual_memory; |
685 | info->fbops = &xxxfb_ops; | 706 | info->fbops = &xxxfb_ops; |
686 | info->fix = xxxfb_fix; /* this will be the only time xxxfb_fix will be | 707 | info->fix = xxxfb_fix; /* this will be the only time xxxfb_fix will be |
687 | * used, so mark it as __initdata | 708 | * used, so mark it as __devinitdata |
688 | */ | 709 | */ |
689 | info->pseudo_palette = pseudo_palette; /* The pseudopalette is an | 710 | info->pseudo_palette = pseudo_palette; /* The pseudopalette is an |
690 | * 16-member array | 711 | * 16-member array |
@@ -760,7 +781,7 @@ static int __init xxxfb_probe(struct pci_dev *dev, | |||
760 | * | 781 | * |
761 | * NOTE: This field is currently unused. | 782 | * NOTE: This field is currently unused. |
762 | */ | 783 | */ |
763 | info->pixmap.scan_align = 32 | 784 | info->pixmap.scan_align = 32; |
764 | /***************************** End optional stage ***************************/ | 785 | /***************************** End optional stage ***************************/ |
765 | 786 | ||
766 | /* | 787 | /* |
@@ -770,13 +791,13 @@ static int __init xxxfb_probe(struct pci_dev *dev, | |||
770 | if (!mode_option) | 791 | if (!mode_option) |
771 | mode_option = "640x480@60"; | 792 | mode_option = "640x480@60"; |
772 | 793 | ||
773 | retval = fb_find_mode(info->var, info, mode_option, NULL, 0, NULL, 8); | 794 | retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); |
774 | 795 | ||
775 | if (!retval || retval == 4) | 796 | if (!retval || retval == 4) |
776 | return -EINVAL; | 797 | return -EINVAL; |
777 | 798 | ||
778 | /* This has to been done !!! */ | 799 | /* This has to been done !!! */ |
779 | fb_alloc_cmap(info->cmap, cmap_len, 0); | 800 | fb_alloc_cmap(&info->cmap, cmap_len, 0); |
780 | 801 | ||
781 | /* | 802 | /* |
782 | * The following is done in the case of having hardware with a static | 803 | * The following is done in the case of having hardware with a static |
@@ -811,34 +832,77 @@ static int __init xxxfb_probe(struct pci_dev *dev, | |||
811 | /* | 832 | /* |
812 | * Cleanup | 833 | * Cleanup |
813 | */ | 834 | */ |
814 | /* static void __exit xxxfb_remove(struct device *device) */ | 835 | /* static void __devexit xxxfb_remove(struct device *device) */ |
815 | static void __exit xxxfb_remove(struct pci_dev *dev) | 836 | static void __devexit xxxfb_remove(struct pci_dev *dev) |
816 | { | 837 | { |
817 | struct fb_info *info = pci_get_drv_data(dev); | 838 | struct fb_info *info = pci_get_drvdata(dev); |
818 | /* or dev_get_drv_data(device); */ | 839 | /* or dev_get_drvdata(device); */ |
819 | 840 | ||
820 | if (info) { | 841 | if (info) { |
821 | unregister_framebuffer(info); | 842 | unregister_framebuffer(info); |
822 | fb_dealloc_cmap(&info.cmap); | 843 | fb_dealloc_cmap(&info->cmap); |
823 | /* ... */ | 844 | /* ... */ |
824 | framebuffer_release(info); | 845 | framebuffer_release(info); |
825 | } | 846 | } |
847 | } | ||
848 | |||
849 | #ifdef CONFIG_PCI | ||
850 | #ifdef CONFIG_PM | ||
851 | /** | ||
852 | * xxxfb_suspend - Optional but recommended function. Suspend the device. | ||
853 | * @dev: PCI device | ||
854 | * @msg: the suspend event code. | ||
855 | * | ||
856 | * See Documentation/power/devices.txt for more information | ||
857 | */ | ||
858 | static int xxxfb_suspend(struct pci_dev *dev, pm_message_t msg) | ||
859 | { | ||
860 | struct fb_info *info = pci_get_drvdata(dev); | ||
861 | struct xxxfb_par *par = info->par; | ||
862 | |||
863 | /* suspend here */ | ||
864 | return 0; | ||
865 | } | ||
866 | |||
867 | /** | ||
868 | * xxxfb_resume - Optional but recommended function. Resume the device. | ||
869 | * @dev: PCI device | ||
870 | * | ||
871 | * See Documentation/power/devices.txt for more information | ||
872 | */ | ||
873 | static int xxxfb_resume(struct pci_dev *dev) | ||
874 | { | ||
875 | struct fb_info *info = pci_get_drvdata(dev); | ||
876 | struct xxxfb_par *par = info->par; | ||
826 | 877 | ||
878 | /* resume here */ | ||
827 | return 0; | 879 | return 0; |
828 | } | 880 | } |
881 | #else | ||
882 | #define xxxfb_suspend NULL | ||
883 | #define xxxfb_resume NULL | ||
884 | #endif /* CONFIG_PM */ | ||
885 | |||
886 | static struct pci_device_id xxxfb_id_table[] = { | ||
887 | { PCI_VENDOR_ID_XXX, PCI_DEVICE_ID_XXX, | ||
888 | PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, | ||
889 | PCI_CLASS_MASK, 0 }, | ||
890 | { 0, } | ||
891 | }; | ||
829 | 892 | ||
830 | #if CONFIG_PCI | ||
831 | /* For PCI drivers */ | 893 | /* For PCI drivers */ |
832 | static struct pci_driver xxxfb_driver = { | 894 | static struct pci_driver xxxfb_driver = { |
833 | .name = "xxxfb", | 895 | .name = "xxxfb", |
834 | .id_table = xxxfb_devices, | 896 | .id_table = xxxfb_id_table, |
835 | .probe = xxxfb_probe, | 897 | .probe = xxxfb_probe, |
836 | .remove = __devexit_p(xxxfb_remove), | 898 | .remove = __devexit_p(xxxfb_remove), |
837 | .suspend = xxxfb_suspend, /* optional */ | 899 | .suspend = xxxfb_suspend, /* optional but recommended */ |
838 | .resume = xxxfb_resume, /* optional */ | 900 | .resume = xxxfb_resume, /* optional but recommended */ |
839 | }; | 901 | }; |
840 | 902 | ||
841 | static int __init xxxfb_init(void) | 903 | MODULE_DEVICE_TABLE(pci, xxxfb_id_table); |
904 | |||
905 | int __init xxxfb_init(void) | ||
842 | { | 906 | { |
843 | /* | 907 | /* |
844 | * For kernel boot options (in 'video=xxxfb:<options>' format) | 908 | * For kernel boot options (in 'video=xxxfb:<options>' format) |
@@ -858,16 +922,53 @@ static void __exit xxxfb_exit(void) | |||
858 | { | 922 | { |
859 | pci_unregister_driver(&xxxfb_driver); | 923 | pci_unregister_driver(&xxxfb_driver); |
860 | } | 924 | } |
861 | #else | 925 | #else /* non PCI, platform drivers */ |
862 | #include <linux/platform_device.h> | 926 | #include <linux/platform_device.h> |
863 | /* for platform devices */ | 927 | /* for platform devices */ |
928 | |||
929 | #ifdef CONFIG_PM | ||
930 | /** | ||
931 | * xxxfb_suspend - Optional but recommended function. Suspend the device. | ||
932 | * @dev: platform device | ||
933 | * @msg: the suspend event code. | ||
934 | * | ||
935 | * See Documentation/power/devices.txt for more information | ||
936 | */ | ||
937 | static int xxxfb_suspend(struct platform_device *dev, pm_message_t msg) | ||
938 | { | ||
939 | struct fb_info *info = platform_get_drvdata(dev); | ||
940 | struct xxxfb_par *par = info->par; | ||
941 | |||
942 | /* suspend here */ | ||
943 | return 0; | ||
944 | } | ||
945 | |||
946 | /** | ||
947 | * xxxfb_resume - Optional but recommended function. Resume the device. | ||
948 | * @dev: platform device | ||
949 | * | ||
950 | * See Documentation/power/devices.txt for more information | ||
951 | */ | ||
952 | static int xxxfb_resume(struct platform_dev *dev) | ||
953 | { | ||
954 | struct fb_info *info = platform_get_drvdata(dev); | ||
955 | struct xxxfb_par *par = info->par; | ||
956 | |||
957 | /* resume here */ | ||
958 | return 0; | ||
959 | } | ||
960 | #else | ||
961 | #define xxxfb_suspend NULL | ||
962 | #define xxxfb_resume NULL | ||
963 | #endif /* CONFIG_PM */ | ||
964 | |||
864 | static struct device_driver xxxfb_driver = { | 965 | static struct device_driver xxxfb_driver = { |
865 | .name = "xxxfb", | 966 | .name = "xxxfb", |
866 | .bus = &platform_bus_type, | 967 | .bus = &platform_bus_type, |
867 | .probe = xxxfb_probe, | 968 | .probe = xxxfb_probe, |
868 | .remove = xxxfb_remove, | 969 | .remove = xxxfb_remove, |
869 | .suspend = xxxfb_suspend, /* optional */ | 970 | .suspend = xxxfb_suspend, /* optional but recommended */ |
870 | .resume = xxxfb_resume, /* optional */ | 971 | .resume = xxxfb_resume, /* optional but recommended */ |
871 | }; | 972 | }; |
872 | 973 | ||
873 | static struct platform_device xxxfb_device = { | 974 | static struct platform_device xxxfb_device = { |
@@ -903,8 +1004,9 @@ static void __exit xxxfb_exit(void) | |||
903 | platform_device_unregister(&xxxfb_device); | 1004 | platform_device_unregister(&xxxfb_device); |
904 | driver_unregister(&xxxfb_driver); | 1005 | driver_unregister(&xxxfb_driver); |
905 | } | 1006 | } |
906 | #endif | 1007 | #endif /* CONFIG_PCI */ |
907 | 1008 | ||
1009 | #ifdef MODULE | ||
908 | /* | 1010 | /* |
909 | * Setup | 1011 | * Setup |
910 | */ | 1012 | */ |
@@ -917,34 +1019,7 @@ int __init xxxfb_setup(char *options) | |||
917 | { | 1019 | { |
918 | /* Parse user speficied options (`video=xxxfb:') */ | 1020 | /* Parse user speficied options (`video=xxxfb:') */ |
919 | } | 1021 | } |
920 | 1022 | #endif /* MODULE */ | |
921 | /* ------------------------------------------------------------------------- */ | ||
922 | |||
923 | /* | ||
924 | * Frame buffer operations | ||
925 | */ | ||
926 | |||
927 | static struct fb_ops xxxfb_ops = { | ||
928 | .owner = THIS_MODULE, | ||
929 | .fb_open = xxxfb_open, | ||
930 | .fb_read = xxxfb_read, | ||
931 | .fb_write = xxxfb_write, | ||
932 | .fb_release = xxxfb_release, | ||
933 | .fb_check_var = xxxfb_check_var, | ||
934 | .fb_set_par = xxxfb_set_par, | ||
935 | .fb_setcolreg = xxxfb_setcolreg, | ||
936 | .fb_blank = xxxfb_blank, | ||
937 | .fb_pan_display = xxxfb_pan_display, | ||
938 | .fb_fillrect = xxxfb_fillrect, /* Needed !!! */ | ||
939 | .fb_copyarea = xxxfb_copyarea, /* Needed !!! */ | ||
940 | .fb_imageblit = xxxfb_imageblit, /* Needed !!! */ | ||
941 | .fb_cursor = xxxfb_cursor, /* Optional !!! */ | ||
942 | .fb_rotate = xxxfb_rotate, | ||
943 | .fb_poll = xxxfb_poll, | ||
944 | .fb_sync = xxxfb_sync, | ||
945 | .fb_ioctl = xxxfb_ioctl, | ||
946 | .fb_mmap = xxxfb_mmap, | ||
947 | }; | ||
948 | 1023 | ||
949 | /* ------------------------------------------------------------------------- */ | 1024 | /* ------------------------------------------------------------------------- */ |
950 | 1025 | ||
@@ -954,6 +1029,6 @@ static struct fb_ops xxxfb_ops = { | |||
954 | */ | 1029 | */ |
955 | 1030 | ||
956 | module_init(xxxfb_init); | 1031 | module_init(xxxfb_init); |
957 | module_exit(xxxfb_cleanup); | 1032 | module_exit(xxxfb_remove); |
958 | 1033 | ||
959 | MODULE_LICENSE("GPL"); | 1034 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/video/sm501fb.c b/drivers/video/sm501fb.c index 0a44c44672c..c86df126f93 100644 --- a/drivers/video/sm501fb.c +++ b/drivers/video/sm501fb.c | |||
@@ -989,7 +989,7 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |||
989 | ((info->cmap.green[fg_col] & 0xFC) << 3) | | 989 | ((info->cmap.green[fg_col] & 0xFC) << 3) | |
990 | ((info->cmap.blue[fg_col] & 0xF8) >> 3); | 990 | ((info->cmap.blue[fg_col] & 0xF8) >> 3); |
991 | 991 | ||
992 | dev_dbg(fbi->dev, "fgcol %08x, bgcol %08x\n", fg, bg); | 992 | dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg); |
993 | 993 | ||
994 | writel(bg, base + SM501_OFF_HWC_COLOR_1_2); | 994 | writel(bg, base + SM501_OFF_HWC_COLOR_1_2); |
995 | writel(fg, base + SM501_OFF_HWC_COLOR_3); | 995 | writel(fg, base + SM501_OFF_HWC_COLOR_3); |
diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index 68b30d9eac5..079cdc911e4 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c | |||
@@ -194,7 +194,7 @@ void svga_dump_var(struct fb_var_screeninfo *var, int node) | |||
194 | void svga_settile(struct fb_info *info, struct fb_tilemap *map) | 194 | void svga_settile(struct fb_info *info, struct fb_tilemap *map) |
195 | { | 195 | { |
196 | const u8 *font = map->data; | 196 | const u8 *font = map->data; |
197 | u8* fb = (u8 *) info->screen_base; | 197 | u8 __iomem *fb = (u8 __iomem *)info->screen_base; |
198 | int i, c; | 198 | int i, c; |
199 | 199 | ||
200 | if ((map->width != 8) || (map->height != 16) || | 200 | if ((map->width != 8) || (map->height != 16) || |
@@ -207,7 +207,8 @@ void svga_settile(struct fb_info *info, struct fb_tilemap *map) | |||
207 | fb += 2; | 207 | fb += 2; |
208 | for (c = 0; c < map->length; c++) { | 208 | for (c = 0; c < map->length; c++) { |
209 | for (i = 0; i < map->height; i++) { | 209 | for (i = 0; i < map->height; i++) { |
210 | fb[i * 4] = font[i]; | 210 | fb_writeb(font[i], fb + i * 4); |
211 | // fb[i * 4] = font[i]; | ||
211 | } | 212 | } |
212 | fb += 128; | 213 | fb += 128; |
213 | font += map->height; | 214 | font += map->height; |
@@ -221,8 +222,8 @@ void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area) | |||
221 | /* colstride is halved in this function because u16 are used */ | 222 | /* colstride is halved in this function because u16 are used */ |
222 | int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); | 223 | int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); |
223 | int rowstride = colstride * (info->var.xres_virtual / 8); | 224 | int rowstride = colstride * (info->var.xres_virtual / 8); |
224 | u16 *fb = (u16 *) info->screen_base; | 225 | u16 __iomem *fb = (u16 __iomem *) info->screen_base; |
225 | u16 *src, *dst; | 226 | u16 __iomem *src, *dst; |
226 | 227 | ||
227 | if ((area->sy > area->dy) || | 228 | if ((area->sy > area->dy) || |
228 | ((area->sy == area->dy) && (area->sx > area->dx))) { | 229 | ((area->sy == area->dy) && (area->sx > area->dx))) { |
@@ -239,10 +240,11 @@ void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area) | |||
239 | } | 240 | } |
240 | 241 | ||
241 | for (dy = 0; dy < area->height; dy++) { | 242 | for (dy = 0; dy < area->height; dy++) { |
242 | u16* src2 = src; | 243 | u16 __iomem *src2 = src; |
243 | u16* dst2 = dst; | 244 | u16 __iomem *dst2 = dst; |
244 | for (dx = 0; dx < area->width; dx++) { | 245 | for (dx = 0; dx < area->width; dx++) { |
245 | *dst2 = *src2; | 246 | fb_writew(fb_readw(src2), dst2); |
247 | // *dst2 = *src2; | ||
246 | src2 += colstride; | 248 | src2 += colstride; |
247 | dst2 += colstride; | 249 | dst2 += colstride; |
248 | } | 250 | } |
@@ -258,14 +260,14 @@ void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect) | |||
258 | int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); | 260 | int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); |
259 | int rowstride = colstride * (info->var.xres_virtual / 8); | 261 | int rowstride = colstride * (info->var.xres_virtual / 8); |
260 | int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg); | 262 | int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg); |
261 | u8 *fb = (u8 *) info->screen_base; | 263 | u8 __iomem *fb = (u8 __iomem *)info->screen_base; |
262 | fb += rect->sx * colstride + rect->sy * rowstride; | 264 | fb += rect->sx * colstride + rect->sy * rowstride; |
263 | 265 | ||
264 | for (dy = 0; dy < rect->height; dy++) { | 266 | for (dy = 0; dy < rect->height; dy++) { |
265 | u8* fb2 = fb; | 267 | u8 __iomem *fb2 = fb; |
266 | for (dx = 0; dx < rect->width; dx++) { | 268 | for (dx = 0; dx < rect->width; dx++) { |
267 | fb2[0] = rect->index; | 269 | fb_writeb(rect->index, fb2); |
268 | fb2[1] = attr; | 270 | fb_writeb(attr, fb2 + 1); |
269 | fb2 += colstride; | 271 | fb2 += colstride; |
270 | } | 272 | } |
271 | fb += rowstride; | 273 | fb += rowstride; |
@@ -279,15 +281,15 @@ void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit) | |||
279 | int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); | 281 | int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); |
280 | int rowstride = colstride * (info->var.xres_virtual / 8); | 282 | int rowstride = colstride * (info->var.xres_virtual / 8); |
281 | int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg); | 283 | int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg); |
282 | u8* fb = (u8 *) info->screen_base; | 284 | u8 __iomem *fb = (u8 __iomem *)info->screen_base; |
283 | fb += blit->sx * colstride + blit->sy * rowstride; | 285 | fb += blit->sx * colstride + blit->sy * rowstride; |
284 | 286 | ||
285 | i=0; | 287 | i=0; |
286 | for (dy=0; dy < blit->height; dy ++) { | 288 | for (dy=0; dy < blit->height; dy ++) { |
287 | u8* fb2 = fb; | 289 | u8 __iomem *fb2 = fb; |
288 | for (dx = 0; dx < blit->width; dx ++) { | 290 | for (dx = 0; dx < blit->width; dx ++) { |
289 | fb2[0] = blit->indices[i]; | 291 | fb_writeb(blit->indices[i], fb2); |
290 | fb2[1] = attr; | 292 | fb_writeb(attr, fb2 + 1); |
291 | fb2 += colstride; | 293 | fb2 += colstride; |
292 | i ++; | 294 | i ++; |
293 | if (i == blit->length) return; | 295 | if (i == blit->length) return; |
@@ -340,6 +342,11 @@ void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) | |||
340 | vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */ | 342 | vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */ |
341 | } | 343 | } |
342 | 344 | ||
345 | int svga_get_tilemax(struct fb_info *info) | ||
346 | { | ||
347 | return 256; | ||
348 | } | ||
349 | |||
343 | 350 | ||
344 | /* ------------------------------------------------------------------------- */ | 351 | /* ------------------------------------------------------------------------- */ |
345 | 352 | ||
@@ -621,6 +628,7 @@ EXPORT_SYMBOL(svga_tilecopy); | |||
621 | EXPORT_SYMBOL(svga_tilefill); | 628 | EXPORT_SYMBOL(svga_tilefill); |
622 | EXPORT_SYMBOL(svga_tileblit); | 629 | EXPORT_SYMBOL(svga_tileblit); |
623 | EXPORT_SYMBOL(svga_tilecursor); | 630 | EXPORT_SYMBOL(svga_tilecursor); |
631 | EXPORT_SYMBOL(svga_get_tilemax); | ||
624 | 632 | ||
625 | EXPORT_SYMBOL(svga_compute_pll); | 633 | EXPORT_SYMBOL(svga_compute_pll); |
626 | EXPORT_SYMBOL(svga_check_timings); | 634 | EXPORT_SYMBOL(svga_check_timings); |
diff --git a/drivers/video/syscopyarea.c b/drivers/video/syscopyarea.c new file mode 100644 index 00000000000..37af10ab8f5 --- /dev/null +++ b/drivers/video/syscopyarea.c | |||
@@ -0,0 +1,378 @@ | |||
1 | /* | ||
2 | * Generic Bit Block Transfer for frame buffers located in system RAM with | ||
3 | * packed pixels of any depth. | ||
4 | * | ||
5 | * Based almost entirely from cfbcopyarea.c (which is based almost entirely | ||
6 | * on Geert Uytterhoeven's copyarea routine) | ||
7 | * | ||
8 | * Copyright (C) 2007 Antonino Daplas <adaplas@pol.net> | ||
9 | * | ||
10 | * This file is subject to the terms and conditions of the GNU General Public | ||
11 | * License. See the file COPYING in the main directory of this archive for | ||
12 | * more details. | ||
13 | * | ||
14 | */ | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/string.h> | ||
18 | #include <linux/fb.h> | ||
19 | #include <linux/slab.h> | ||
20 | #include <asm/types.h> | ||
21 | #include <asm/io.h> | ||
22 | #include "fb_draw.h" | ||
23 | |||
24 | /* | ||
25 | * Generic bitwise copy algorithm | ||
26 | */ | ||
27 | |||
28 | static void | ||
29 | bitcpy(unsigned long *dst, int dst_idx, const unsigned long *src, | ||
30 | int src_idx, int bits, unsigned n) | ||
31 | { | ||
32 | unsigned long first, last; | ||
33 | int const shift = dst_idx-src_idx; | ||
34 | int left, right; | ||
35 | |||
36 | first = FB_SHIFT_HIGH(~0UL, dst_idx); | ||
37 | last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits)); | ||
38 | |||
39 | if (!shift) { | ||
40 | /* Same alignment for source and dest */ | ||
41 | if (dst_idx+n <= bits) { | ||
42 | /* Single word */ | ||
43 | if (last) | ||
44 | first &= last; | ||
45 | *dst = comp(*src, *dst, first); | ||
46 | } else { | ||
47 | /* Multiple destination words */ | ||
48 | /* Leading bits */ | ||
49 | if (first != ~0UL) { | ||
50 | *dst = comp(*src, *dst, first); | ||
51 | dst++; | ||
52 | src++; | ||
53 | n -= bits - dst_idx; | ||
54 | } | ||
55 | |||
56 | /* Main chunk */ | ||
57 | n /= bits; | ||
58 | while (n >= 8) { | ||
59 | *dst++ = *src++; | ||
60 | *dst++ = *src++; | ||
61 | *dst++ = *src++; | ||
62 | *dst++ = *src++; | ||
63 | *dst++ = *src++; | ||
64 | *dst++ = *src++; | ||
65 | *dst++ = *src++; | ||
66 | *dst++ = *src++; | ||
67 | n -= 8; | ||
68 | } | ||
69 | while (n--) | ||
70 | *dst++ = *src++; | ||
71 | |||
72 | /* Trailing bits */ | ||
73 | if (last) | ||
74 | *dst = comp(*src, *dst, last); | ||
75 | } | ||
76 | } else { | ||
77 | unsigned long d0, d1; | ||
78 | int m; | ||
79 | |||
80 | /* Different alignment for source and dest */ | ||
81 | right = shift & (bits - 1); | ||
82 | left = -shift & (bits - 1); | ||
83 | |||
84 | if (dst_idx+n <= bits) { | ||
85 | /* Single destination word */ | ||
86 | if (last) | ||
87 | first &= last; | ||
88 | if (shift > 0) { | ||
89 | /* Single source word */ | ||
90 | *dst = comp(*src >> right, *dst, first); | ||
91 | } else if (src_idx+n <= bits) { | ||
92 | /* Single source word */ | ||
93 | *dst = comp(*src << left, *dst, first); | ||
94 | } else { | ||
95 | /* 2 source words */ | ||
96 | d0 = *src++; | ||
97 | d1 = *src; | ||
98 | *dst = comp(d0 << left | d1 >> right, *dst, | ||
99 | first); | ||
100 | } | ||
101 | } else { | ||
102 | /* Multiple destination words */ | ||
103 | /** We must always remember the last value read, | ||
104 | because in case SRC and DST overlap bitwise (e.g. | ||
105 | when moving just one pixel in 1bpp), we always | ||
106 | collect one full long for DST and that might | ||
107 | overlap with the current long from SRC. We store | ||
108 | this value in 'd0'. */ | ||
109 | d0 = *src++; | ||
110 | /* Leading bits */ | ||
111 | if (shift > 0) { | ||
112 | /* Single source word */ | ||
113 | *dst = comp(d0 >> right, *dst, first); | ||
114 | dst++; | ||
115 | n -= bits - dst_idx; | ||
116 | } else { | ||
117 | /* 2 source words */ | ||
118 | d1 = *src++; | ||
119 | *dst = comp(d0 << left | *dst >> right, *dst, first); | ||
120 | d0 = d1; | ||
121 | dst++; | ||
122 | n -= bits - dst_idx; | ||
123 | } | ||
124 | |||
125 | /* Main chunk */ | ||
126 | m = n % bits; | ||
127 | n /= bits; | ||
128 | while (n >= 4) { | ||
129 | d1 = *src++; | ||
130 | *dst++ = d0 << left | d1 >> right; | ||
131 | d0 = d1; | ||
132 | d1 = *src++; | ||
133 | *dst++ = d0 << left | d1 >> right; | ||
134 | d0 = d1; | ||
135 | d1 = *src++; | ||
136 | *dst++ = d0 << left | d1 >> right; | ||
137 | d0 = d1; | ||
138 | d1 = *src++; | ||
139 | *dst++ = d0 << left | d1 >> right; | ||
140 | d0 = d1; | ||
141 | n -= 4; | ||
142 | } | ||
143 | while (n--) { | ||
144 | d1 = *src++; | ||
145 | *dst++ = d0 << left | d1 >> right; | ||
146 | d0 = d1; | ||
147 | } | ||
148 | |||
149 | /* Trailing bits */ | ||
150 | if (last) { | ||
151 | if (m <= right) { | ||
152 | /* Single source word */ | ||
153 | *dst = comp(d0 << left, *dst, last); | ||
154 | } else { | ||
155 | /* 2 source words */ | ||
156 | d1 = *src; | ||
157 | *dst = comp(d0 << left | d1 >> right, | ||
158 | *dst, last); | ||
159 | } | ||
160 | } | ||
161 | } | ||
162 | } | ||
163 | } | ||
164 | |||
165 | /* | ||
166 | * Generic bitwise copy algorithm, operating backward | ||
167 | */ | ||
168 | |||
169 | static void | ||
170 | bitcpy_rev(unsigned long *dst, int dst_idx, const unsigned long *src, | ||
171 | int src_idx, int bits, unsigned n) | ||
172 | { | ||
173 | unsigned long first, last; | ||
174 | int shift; | ||
175 | |||
176 | dst += (n-1)/bits; | ||
177 | src += (n-1)/bits; | ||
178 | if ((n-1) % bits) { | ||
179 | dst_idx += (n-1) % bits; | ||
180 | dst += dst_idx >> (ffs(bits) - 1); | ||
181 | dst_idx &= bits - 1; | ||
182 | src_idx += (n-1) % bits; | ||
183 | src += src_idx >> (ffs(bits) - 1); | ||
184 | src_idx &= bits - 1; | ||
185 | } | ||
186 | |||
187 | shift = dst_idx-src_idx; | ||
188 | |||
189 | first = FB_SHIFT_LOW(~0UL, bits - 1 - dst_idx); | ||
190 | last = ~(FB_SHIFT_LOW(~0UL, bits - 1 - ((dst_idx-n) % bits))); | ||
191 | |||
192 | if (!shift) { | ||
193 | /* Same alignment for source and dest */ | ||
194 | if ((unsigned long)dst_idx+1 >= n) { | ||
195 | /* Single word */ | ||
196 | if (last) | ||
197 | first &= last; | ||
198 | *dst = comp(*src, *dst, first); | ||
199 | } else { | ||
200 | /* Multiple destination words */ | ||
201 | |||
202 | /* Leading bits */ | ||
203 | if (first != ~0UL) { | ||
204 | *dst = comp(*src, *dst, first); | ||
205 | dst--; | ||
206 | src--; | ||
207 | n -= dst_idx+1; | ||
208 | } | ||
209 | |||
210 | /* Main chunk */ | ||
211 | n /= bits; | ||
212 | while (n >= 8) { | ||
213 | *dst-- = *src--; | ||
214 | *dst-- = *src--; | ||
215 | *dst-- = *src--; | ||
216 | *dst-- = *src--; | ||
217 | *dst-- = *src--; | ||
218 | *dst-- = *src--; | ||
219 | *dst-- = *src--; | ||
220 | *dst-- = *src--; | ||
221 | n -= 8; | ||
222 | } | ||
223 | while (n--) | ||
224 | *dst-- = *src--; | ||
225 | /* Trailing bits */ | ||
226 | if (last) | ||
227 | *dst = comp(*src, *dst, last); | ||
228 | } | ||
229 | } else { | ||
230 | /* Different alignment for source and dest */ | ||
231 | |||
232 | int const left = -shift & (bits-1); | ||
233 | int const right = shift & (bits-1); | ||
234 | |||
235 | if ((unsigned long)dst_idx+1 >= n) { | ||
236 | /* Single destination word */ | ||
237 | if (last) | ||
238 | first &= last; | ||
239 | if (shift < 0) { | ||
240 | /* Single source word */ | ||
241 | *dst = comp(*src << left, *dst, first); | ||
242 | } else if (1+(unsigned long)src_idx >= n) { | ||
243 | /* Single source word */ | ||
244 | *dst = comp(*src >> right, *dst, first); | ||
245 | } else { | ||
246 | /* 2 source words */ | ||
247 | *dst = comp(*src >> right | *(src-1) << left, | ||
248 | *dst, first); | ||
249 | } | ||
250 | } else { | ||
251 | /* Multiple destination words */ | ||
252 | /** We must always remember the last value read, | ||
253 | because in case SRC and DST overlap bitwise (e.g. | ||
254 | when moving just one pixel in 1bpp), we always | ||
255 | collect one full long for DST and that might | ||
256 | overlap with the current long from SRC. We store | ||
257 | this value in 'd0'. */ | ||
258 | unsigned long d0, d1; | ||
259 | int m; | ||
260 | |||
261 | d0 = *src--; | ||
262 | /* Leading bits */ | ||
263 | if (shift < 0) { | ||
264 | /* Single source word */ | ||
265 | *dst = comp(d0 << left, *dst, first); | ||
266 | } else { | ||
267 | /* 2 source words */ | ||
268 | d1 = *src--; | ||
269 | *dst = comp(d0 >> right | d1 << left, *dst, | ||
270 | first); | ||
271 | d0 = d1; | ||
272 | } | ||
273 | dst--; | ||
274 | n -= dst_idx+1; | ||
275 | |||
276 | /* Main chunk */ | ||
277 | m = n % bits; | ||
278 | n /= bits; | ||
279 | while (n >= 4) { | ||
280 | d1 = *src--; | ||
281 | *dst-- = d0 >> right | d1 << left; | ||
282 | d0 = d1; | ||
283 | d1 = *src--; | ||
284 | *dst-- = d0 >> right | d1 << left; | ||
285 | d0 = d1; | ||
286 | d1 = *src--; | ||
287 | *dst-- = d0 >> right | d1 << left; | ||
288 | d0 = d1; | ||
289 | d1 = *src--; | ||
290 | *dst-- = d0 >> right | d1 << left; | ||
291 | d0 = d1; | ||
292 | n -= 4; | ||
293 | } | ||
294 | while (n--) { | ||
295 | d1 = *src--; | ||
296 | *dst-- = d0 >> right | d1 << left; | ||
297 | d0 = d1; | ||
298 | } | ||
299 | |||
300 | /* Trailing bits */ | ||
301 | if (last) { | ||
302 | if (m <= left) { | ||
303 | /* Single source word */ | ||
304 | *dst = comp(d0 >> right, *dst, last); | ||
305 | } else { | ||
306 | /* 2 source words */ | ||
307 | d1 = *src; | ||
308 | *dst = comp(d0 >> right | d1 << left, | ||
309 | *dst, last); | ||
310 | } | ||
311 | } | ||
312 | } | ||
313 | } | ||
314 | } | ||
315 | |||
316 | void sys_copyarea(struct fb_info *p, const struct fb_copyarea *area) | ||
317 | { | ||
318 | u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy; | ||
319 | u32 height = area->height, width = area->width; | ||
320 | unsigned long const bits_per_line = p->fix.line_length*8u; | ||
321 | unsigned long *dst = NULL, *src = NULL; | ||
322 | int bits = BITS_PER_LONG, bytes = bits >> 3; | ||
323 | int dst_idx = 0, src_idx = 0, rev_copy = 0; | ||
324 | |||
325 | if (p->state != FBINFO_STATE_RUNNING) | ||
326 | return; | ||
327 | |||
328 | /* if the beginning of the target area might overlap with the end of | ||
329 | the source area, be have to copy the area reverse. */ | ||
330 | if ((dy == sy && dx > sx) || (dy > sy)) { | ||
331 | dy += height; | ||
332 | sy += height; | ||
333 | rev_copy = 1; | ||
334 | } | ||
335 | |||
336 | /* split the base of the framebuffer into a long-aligned address and | ||
337 | the index of the first bit */ | ||
338 | dst = src = (unsigned long *)((unsigned long)p->screen_base & | ||
339 | ~(bytes-1)); | ||
340 | dst_idx = src_idx = 8*((unsigned long)p->screen_base & (bytes-1)); | ||
341 | /* add offset of source and target area */ | ||
342 | dst_idx += dy*bits_per_line + dx*p->var.bits_per_pixel; | ||
343 | src_idx += sy*bits_per_line + sx*p->var.bits_per_pixel; | ||
344 | |||
345 | if (p->fbops->fb_sync) | ||
346 | p->fbops->fb_sync(p); | ||
347 | |||
348 | if (rev_copy) { | ||
349 | while (height--) { | ||
350 | dst_idx -= bits_per_line; | ||
351 | src_idx -= bits_per_line; | ||
352 | dst += dst_idx >> (ffs(bits) - 1); | ||
353 | dst_idx &= (bytes - 1); | ||
354 | src += src_idx >> (ffs(bits) - 1); | ||
355 | src_idx &= (bytes - 1); | ||
356 | bitcpy_rev(dst, dst_idx, src, src_idx, bits, | ||
357 | width*p->var.bits_per_pixel); | ||
358 | } | ||
359 | } else { | ||
360 | while (height--) { | ||
361 | dst += dst_idx >> (ffs(bits) - 1); | ||
362 | dst_idx &= (bytes - 1); | ||
363 | src += src_idx >> (ffs(bits) - 1); | ||
364 | src_idx &= (bytes - 1); | ||
365 | bitcpy(dst, dst_idx, src, src_idx, bits, | ||
366 | width*p->var.bits_per_pixel); | ||
367 | dst_idx += bits_per_line; | ||
368 | src_idx += bits_per_line; | ||
369 | } | ||
370 | } | ||
371 | } | ||
372 | |||
373 | EXPORT_SYMBOL(sys_copyarea); | ||
374 | |||
375 | MODULE_AUTHOR("Antonino Daplas <adaplas@pol.net>"); | ||
376 | MODULE_DESCRIPTION("Generic copyarea (sys-to-sys)"); | ||
377 | MODULE_LICENSE("GPL"); | ||
378 | |||
diff --git a/drivers/video/sysfillrect.c b/drivers/video/sysfillrect.c new file mode 100644 index 00000000000..a261e9e6a67 --- /dev/null +++ b/drivers/video/sysfillrect.c | |||
@@ -0,0 +1,334 @@ | |||
1 | /* | ||
2 | * Generic fillrect for frame buffers in system RAM with packed pixels of | ||
3 | * any depth. | ||
4 | * | ||
5 | * Based almost entirely from cfbfillrect.c (which is based almost entirely | ||
6 | * on Geert Uytterhoeven's fillrect routine) | ||
7 | * | ||
8 | * Copyright (C) 2007 Antonino Daplas <adaplas@pol.net> | ||
9 | * | ||
10 | * This file is subject to the terms and conditions of the GNU General Public | ||
11 | * License. See the file COPYING in the main directory of this archive for | ||
12 | * more details. | ||
13 | */ | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/string.h> | ||
16 | #include <linux/fb.h> | ||
17 | #include <asm/types.h> | ||
18 | #include "fb_draw.h" | ||
19 | |||
20 | /* | ||
21 | * Aligned pattern fill using 32/64-bit memory accesses | ||
22 | */ | ||
23 | |||
24 | static void | ||
25 | bitfill_aligned(unsigned long *dst, int dst_idx, unsigned long pat, | ||
26 | unsigned n, int bits) | ||
27 | { | ||
28 | unsigned long first, last; | ||
29 | |||
30 | if (!n) | ||
31 | return; | ||
32 | |||
33 | first = FB_SHIFT_HIGH(~0UL, dst_idx); | ||
34 | last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits)); | ||
35 | |||
36 | if (dst_idx+n <= bits) { | ||
37 | /* Single word */ | ||
38 | if (last) | ||
39 | first &= last; | ||
40 | *dst = comp(pat, *dst, first); | ||
41 | } else { | ||
42 | /* Multiple destination words */ | ||
43 | |||
44 | /* Leading bits */ | ||
45 | if (first!= ~0UL) { | ||
46 | *dst = comp(pat, *dst, first); | ||
47 | dst++; | ||
48 | n -= bits - dst_idx; | ||
49 | } | ||
50 | |||
51 | /* Main chunk */ | ||
52 | n /= bits; | ||
53 | while (n >= 8) { | ||
54 | *dst++ = pat; | ||
55 | *dst++ = pat; | ||
56 | *dst++ = pat; | ||
57 | *dst++ = pat; | ||
58 | *dst++ = pat; | ||
59 | *dst++ = pat; | ||
60 | *dst++ = pat; | ||
61 | *dst++ = pat; | ||
62 | n -= 8; | ||
63 | } | ||
64 | while (n--) | ||
65 | *dst++ = pat; | ||
66 | /* Trailing bits */ | ||
67 | if (last) | ||
68 | *dst = comp(pat, *dst, last); | ||
69 | } | ||
70 | } | ||
71 | |||
72 | |||
73 | /* | ||
74 | * Unaligned generic pattern fill using 32/64-bit memory accesses | ||
75 | * The pattern must have been expanded to a full 32/64-bit value | ||
76 | * Left/right are the appropriate shifts to convert to the pattern to be | ||
77 | * used for the next 32/64-bit word | ||
78 | */ | ||
79 | |||
80 | static void | ||
81 | bitfill_unaligned(unsigned long *dst, int dst_idx, unsigned long pat, | ||
82 | int left, int right, unsigned n, int bits) | ||
83 | { | ||
84 | unsigned long first, last; | ||
85 | |||
86 | if (!n) | ||
87 | return; | ||
88 | |||
89 | first = FB_SHIFT_HIGH(~0UL, dst_idx); | ||
90 | last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits)); | ||
91 | |||
92 | if (dst_idx+n <= bits) { | ||
93 | /* Single word */ | ||
94 | if (last) | ||
95 | first &= last; | ||
96 | *dst = comp(pat, *dst, first); | ||
97 | } else { | ||
98 | /* Multiple destination words */ | ||
99 | /* Leading bits */ | ||
100 | if (first) { | ||
101 | *dst = comp(pat, *dst, first); | ||
102 | dst++; | ||
103 | pat = pat << left | pat >> right; | ||
104 | n -= bits - dst_idx; | ||
105 | } | ||
106 | |||
107 | /* Main chunk */ | ||
108 | n /= bits; | ||
109 | while (n >= 4) { | ||
110 | *dst++ = pat; | ||
111 | pat = pat << left | pat >> right; | ||
112 | *dst++ = pat; | ||
113 | pat = pat << left | pat >> right; | ||
114 | *dst++ = pat; | ||
115 | pat = pat << left | pat >> right; | ||
116 | *dst++ = pat; | ||
117 | pat = pat << left | pat >> right; | ||
118 | n -= 4; | ||
119 | } | ||
120 | while (n--) { | ||
121 | *dst++ = pat; | ||
122 | pat = pat << left | pat >> right; | ||
123 | } | ||
124 | |||
125 | /* Trailing bits */ | ||
126 | if (last) | ||
127 | *dst = comp(pat, *dst, first); | ||
128 | } | ||
129 | } | ||
130 | |||
131 | /* | ||
132 | * Aligned pattern invert using 32/64-bit memory accesses | ||
133 | */ | ||
134 | static void | ||
135 | bitfill_aligned_rev(unsigned long *dst, int dst_idx, unsigned long pat, | ||
136 | unsigned n, int bits) | ||
137 | { | ||
138 | unsigned long val = pat; | ||
139 | unsigned long first, last; | ||
140 | |||
141 | if (!n) | ||
142 | return; | ||
143 | |||
144 | first = FB_SHIFT_HIGH(~0UL, dst_idx); | ||
145 | last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits)); | ||
146 | |||
147 | if (dst_idx+n <= bits) { | ||
148 | /* Single word */ | ||
149 | if (last) | ||
150 | first &= last; | ||
151 | *dst = comp(*dst ^ val, *dst, first); | ||
152 | } else { | ||
153 | /* Multiple destination words */ | ||
154 | /* Leading bits */ | ||
155 | if (first!=0UL) { | ||
156 | *dst = comp(*dst ^ val, *dst, first); | ||
157 | dst++; | ||
158 | n -= bits - dst_idx; | ||
159 | } | ||
160 | |||
161 | /* Main chunk */ | ||
162 | n /= bits; | ||
163 | while (n >= 8) { | ||
164 | *dst++ ^= val; | ||
165 | *dst++ ^= val; | ||
166 | *dst++ ^= val; | ||
167 | *dst++ ^= val; | ||
168 | *dst++ ^= val; | ||
169 | *dst++ ^= val; | ||
170 | *dst++ ^= val; | ||
171 | *dst++ ^= val; | ||
172 | n -= 8; | ||
173 | } | ||
174 | while (n--) | ||
175 | *dst++ ^= val; | ||
176 | /* Trailing bits */ | ||
177 | if (last) | ||
178 | *dst = comp(*dst ^ val, *dst, last); | ||
179 | } | ||
180 | } | ||
181 | |||
182 | |||
183 | /* | ||
184 | * Unaligned generic pattern invert using 32/64-bit memory accesses | ||
185 | * The pattern must have been expanded to a full 32/64-bit value | ||
186 | * Left/right are the appropriate shifts to convert to the pattern to be | ||
187 | * used for the next 32/64-bit word | ||
188 | */ | ||
189 | |||
190 | static void | ||
191 | bitfill_unaligned_rev(unsigned long *dst, int dst_idx, unsigned long pat, | ||
192 | int left, int right, unsigned n, int bits) | ||
193 | { | ||
194 | unsigned long first, last; | ||
195 | |||
196 | if (!n) | ||
197 | return; | ||
198 | |||
199 | first = FB_SHIFT_HIGH(~0UL, dst_idx); | ||
200 | last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits)); | ||
201 | |||
202 | if (dst_idx+n <= bits) { | ||
203 | /* Single word */ | ||
204 | if (last) | ||
205 | first &= last; | ||
206 | *dst = comp(*dst ^ pat, *dst, first); | ||
207 | } else { | ||
208 | /* Multiple destination words */ | ||
209 | |||
210 | /* Leading bits */ | ||
211 | if (first != 0UL) { | ||
212 | *dst = comp(*dst ^ pat, *dst, first); | ||
213 | dst++; | ||
214 | pat = pat << left | pat >> right; | ||
215 | n -= bits - dst_idx; | ||
216 | } | ||
217 | |||
218 | /* Main chunk */ | ||
219 | n /= bits; | ||
220 | while (n >= 4) { | ||
221 | *dst++ ^= pat; | ||
222 | pat = pat << left | pat >> right; | ||
223 | *dst++ ^= pat; | ||
224 | pat = pat << left | pat >> right; | ||
225 | *dst++ ^= pat; | ||
226 | pat = pat << left | pat >> right; | ||
227 | *dst++ ^= pat; | ||
228 | pat = pat << left | pat >> right; | ||
229 | n -= 4; | ||
230 | } | ||
231 | while (n--) { | ||
232 | *dst ^= pat; | ||
233 | pat = pat << left | pat >> right; | ||
234 | } | ||
235 | |||
236 | /* Trailing bits */ | ||
237 | if (last) | ||
238 | *dst = comp(*dst ^ pat, *dst, last); | ||
239 | } | ||
240 | } | ||
241 | |||
242 | void sys_fillrect(struct fb_info *p, const struct fb_fillrect *rect) | ||
243 | { | ||
244 | unsigned long pat, fg; | ||
245 | unsigned long width = rect->width, height = rect->height; | ||
246 | int bits = BITS_PER_LONG, bytes = bits >> 3; | ||
247 | u32 bpp = p->var.bits_per_pixel; | ||
248 | unsigned long *dst; | ||
249 | int dst_idx, left; | ||
250 | |||
251 | if (p->state != FBINFO_STATE_RUNNING) | ||
252 | return; | ||
253 | |||
254 | if (p->fix.visual == FB_VISUAL_TRUECOLOR || | ||
255 | p->fix.visual == FB_VISUAL_DIRECTCOLOR ) | ||
256 | fg = ((u32 *) (p->pseudo_palette))[rect->color]; | ||
257 | else | ||
258 | fg = rect->color; | ||
259 | |||
260 | pat = pixel_to_pat( bpp, fg); | ||
261 | |||
262 | dst = (unsigned long *)((unsigned long)p->screen_base & ~(bytes-1)); | ||
263 | dst_idx = ((unsigned long)p->screen_base & (bytes - 1))*8; | ||
264 | dst_idx += rect->dy*p->fix.line_length*8+rect->dx*bpp; | ||
265 | /* FIXME For now we support 1-32 bpp only */ | ||
266 | left = bits % bpp; | ||
267 | if (p->fbops->fb_sync) | ||
268 | p->fbops->fb_sync(p); | ||
269 | if (!left) { | ||
270 | void (*fill_op32)(unsigned long *dst, int dst_idx, | ||
271 | unsigned long pat, unsigned n, int bits) = | ||
272 | NULL; | ||
273 | |||
274 | switch (rect->rop) { | ||
275 | case ROP_XOR: | ||
276 | fill_op32 = bitfill_aligned_rev; | ||
277 | break; | ||
278 | case ROP_COPY: | ||
279 | fill_op32 = bitfill_aligned; | ||
280 | break; | ||
281 | default: | ||
282 | printk( KERN_ERR "cfb_fillrect(): unknown rop, " | ||
283 | "defaulting to ROP_COPY\n"); | ||
284 | fill_op32 = bitfill_aligned; | ||
285 | break; | ||
286 | } | ||
287 | while (height--) { | ||
288 | dst += dst_idx >> (ffs(bits) - 1); | ||
289 | dst_idx &= (bits - 1); | ||
290 | fill_op32(dst, dst_idx, pat, width*bpp, bits); | ||
291 | dst_idx += p->fix.line_length*8; | ||
292 | } | ||
293 | } else { | ||
294 | int right; | ||
295 | int r; | ||
296 | int rot = (left-dst_idx) % bpp; | ||
297 | void (*fill_op)(unsigned long *dst, int dst_idx, | ||
298 | unsigned long pat, int left, int right, | ||
299 | unsigned n, int bits) = NULL; | ||
300 | |||
301 | /* rotate pattern to correct start position */ | ||
302 | pat = pat << rot | pat >> (bpp-rot); | ||
303 | |||
304 | right = bpp-left; | ||
305 | switch (rect->rop) { | ||
306 | case ROP_XOR: | ||
307 | fill_op = bitfill_unaligned_rev; | ||
308 | break; | ||
309 | case ROP_COPY: | ||
310 | fill_op = bitfill_unaligned; | ||
311 | break; | ||
312 | default: | ||
313 | printk(KERN_ERR "cfb_fillrect(): unknown rop, " | ||
314 | "defaulting to ROP_COPY\n"); | ||
315 | fill_op = bitfill_unaligned; | ||
316 | break; | ||
317 | } | ||
318 | while (height--) { | ||
319 | dst += dst_idx >> (ffs(bits) - 1); | ||
320 | dst_idx &= (bits - 1); | ||
321 | fill_op(dst, dst_idx, pat, left, right, | ||
322 | width*bpp, bits); | ||
323 | r = (p->fix.line_length*8) % bpp; | ||
324 | pat = pat << (bpp-r) | pat >> r; | ||
325 | dst_idx += p->fix.line_length*8; | ||
326 | } | ||
327 | } | ||
328 | } | ||
329 | |||
330 | EXPORT_SYMBOL(sys_fillrect); | ||
331 | |||
332 | MODULE_AUTHOR("Antonino Daplas <adaplas@pol.net>"); | ||
333 | MODULE_DESCRIPTION("Generic fill rectangle (sys-to-sys)"); | ||
334 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/sysimgblt.c b/drivers/video/sysimgblt.c new file mode 100644 index 00000000000..bd7e7e9d155 --- /dev/null +++ b/drivers/video/sysimgblt.c | |||
@@ -0,0 +1,291 @@ | |||
1 | /* | ||
2 | * Generic 1-bit or 8-bit source to 1-32 bit destination expansion | ||
3 | * for frame buffer located in system RAM with packed pixels of any depth. | ||
4 | * | ||
5 | * Based almost entirely on cfbimgblt.c | ||
6 | * | ||
7 | * Copyright (C) April 2007 Antonino Daplas <adaplas@pol.net> | ||
8 | * | ||
9 | * This file is subject to the terms and conditions of the GNU General Public | ||
10 | * License. See the file COPYING in the main directory of this archive for | ||
11 | * more details. | ||
12 | */ | ||
13 | #include <linux/module.h> | ||
14 | #include <linux/string.h> | ||
15 | #include <linux/fb.h> | ||
16 | #include <asm/types.h> | ||
17 | |||
18 | #define DEBUG | ||
19 | |||
20 | #ifdef DEBUG | ||
21 | #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt,__FUNCTION__,## args) | ||
22 | #else | ||
23 | #define DPRINTK(fmt, args...) | ||
24 | #endif | ||
25 | |||
26 | static const u32 cfb_tab8[] = { | ||
27 | #if defined(__BIG_ENDIAN) | ||
28 | 0x00000000,0x000000ff,0x0000ff00,0x0000ffff, | ||
29 | 0x00ff0000,0x00ff00ff,0x00ffff00,0x00ffffff, | ||
30 | 0xff000000,0xff0000ff,0xff00ff00,0xff00ffff, | ||
31 | 0xffff0000,0xffff00ff,0xffffff00,0xffffffff | ||
32 | #elif defined(__LITTLE_ENDIAN) | ||
33 | 0x00000000,0xff000000,0x00ff0000,0xffff0000, | ||
34 | 0x0000ff00,0xff00ff00,0x00ffff00,0xffffff00, | ||
35 | 0x000000ff,0xff0000ff,0x00ff00ff,0xffff00ff, | ||
36 | 0x0000ffff,0xff00ffff,0x00ffffff,0xffffffff | ||
37 | #else | ||
38 | #error FIXME: No endianness?? | ||
39 | #endif | ||
40 | }; | ||
41 | |||
42 | static const u32 cfb_tab16[] = { | ||
43 | #if defined(__BIG_ENDIAN) | ||
44 | 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff | ||
45 | #elif defined(__LITTLE_ENDIAN) | ||
46 | 0x00000000, 0xffff0000, 0x0000ffff, 0xffffffff | ||
47 | #else | ||
48 | #error FIXME: No endianness?? | ||
49 | #endif | ||
50 | }; | ||
51 | |||
52 | static const u32 cfb_tab32[] = { | ||
53 | 0x00000000, 0xffffffff | ||
54 | }; | ||
55 | |||
56 | static void color_imageblit(const struct fb_image *image, struct fb_info *p, | ||
57 | void *dst1, u32 start_index, u32 pitch_index) | ||
58 | { | ||
59 | /* Draw the penguin */ | ||
60 | u32 *dst, *dst2; | ||
61 | u32 color = 0, val, shift; | ||
62 | int i, n, bpp = p->var.bits_per_pixel; | ||
63 | u32 null_bits = 32 - bpp; | ||
64 | u32 *palette = (u32 *) p->pseudo_palette; | ||
65 | const u8 *src = image->data; | ||
66 | |||
67 | dst2 = dst1; | ||
68 | for (i = image->height; i--; ) { | ||
69 | n = image->width; | ||
70 | dst = dst1; | ||
71 | shift = 0; | ||
72 | val = 0; | ||
73 | |||
74 | if (start_index) { | ||
75 | u32 start_mask = ~(FB_SHIFT_HIGH(~(u32)0, | ||
76 | start_index)); | ||
77 | val = *dst & start_mask; | ||
78 | shift = start_index; | ||
79 | } | ||
80 | while (n--) { | ||
81 | if (p->fix.visual == FB_VISUAL_TRUECOLOR || | ||
82 | p->fix.visual == FB_VISUAL_DIRECTCOLOR ) | ||
83 | color = palette[*src]; | ||
84 | else | ||
85 | color = *src; | ||
86 | color <<= FB_LEFT_POS(bpp); | ||
87 | val |= FB_SHIFT_HIGH(color, shift); | ||
88 | if (shift >= null_bits) { | ||
89 | *dst++ = val; | ||
90 | |||
91 | val = (shift == null_bits) ? 0 : | ||
92 | FB_SHIFT_LOW(color, 32 - shift); | ||
93 | } | ||
94 | shift += bpp; | ||
95 | shift &= (32 - 1); | ||
96 | src++; | ||
97 | } | ||
98 | if (shift) { | ||
99 | u32 end_mask = FB_SHIFT_HIGH(~(u32)0, shift); | ||
100 | |||
101 | *dst &= end_mask; | ||
102 | *dst |= val; | ||
103 | } | ||
104 | dst1 += p->fix.line_length; | ||
105 | if (pitch_index) { | ||
106 | dst2 += p->fix.line_length; | ||
107 | dst1 = (u8 *)((long)dst2 & ~(sizeof(u32) - 1)); | ||
108 | |||
109 | start_index += pitch_index; | ||
110 | start_index &= 32 - 1; | ||
111 | } | ||
112 | } | ||
113 | } | ||
114 | |||
115 | static void slow_imageblit(const struct fb_image *image, struct fb_info *p, | ||
116 | void *dst1, u32 fgcolor, u32 bgcolor, | ||
117 | u32 start_index, u32 pitch_index) | ||
118 | { | ||
119 | u32 shift, color = 0, bpp = p->var.bits_per_pixel; | ||
120 | u32 *dst, *dst2; | ||
121 | u32 val, pitch = p->fix.line_length; | ||
122 | u32 null_bits = 32 - bpp; | ||
123 | u32 spitch = (image->width+7)/8; | ||
124 | const u8 *src = image->data, *s; | ||
125 | u32 i, j, l; | ||
126 | |||
127 | dst2 = dst1; | ||
128 | fgcolor <<= FB_LEFT_POS(bpp); | ||
129 | bgcolor <<= FB_LEFT_POS(bpp); | ||
130 | |||
131 | for (i = image->height; i--; ) { | ||
132 | shift = val = 0; | ||
133 | l = 8; | ||
134 | j = image->width; | ||
135 | dst = dst1; | ||
136 | s = src; | ||
137 | |||
138 | /* write leading bits */ | ||
139 | if (start_index) { | ||
140 | u32 start_mask = ~(FB_SHIFT_HIGH(~(u32)0,start_index)); | ||
141 | val = *dst & start_mask; | ||
142 | shift = start_index; | ||
143 | } | ||
144 | |||
145 | while (j--) { | ||
146 | l--; | ||
147 | color = (*s & (1 << l)) ? fgcolor : bgcolor; | ||
148 | val |= FB_SHIFT_HIGH(color, shift); | ||
149 | |||
150 | /* Did the bitshift spill bits to the next long? */ | ||
151 | if (shift >= null_bits) { | ||
152 | *dst++ = val; | ||
153 | val = (shift == null_bits) ? 0 : | ||
154 | FB_SHIFT_LOW(color,32 - shift); | ||
155 | } | ||
156 | shift += bpp; | ||
157 | shift &= (32 - 1); | ||
158 | if (!l) { l = 8; s++; }; | ||
159 | } | ||
160 | |||
161 | /* write trailing bits */ | ||
162 | if (shift) { | ||
163 | u32 end_mask = FB_SHIFT_HIGH(~(u32)0, shift); | ||
164 | |||
165 | *dst &= end_mask; | ||
166 | *dst |= val; | ||
167 | } | ||
168 | |||
169 | dst1 += pitch; | ||
170 | src += spitch; | ||
171 | if (pitch_index) { | ||
172 | dst2 += pitch; | ||
173 | dst1 = (u8 *)((long)dst2 & ~(sizeof(u32) - 1)); | ||
174 | start_index += pitch_index; | ||
175 | start_index &= 32 - 1; | ||
176 | } | ||
177 | |||
178 | } | ||
179 | } | ||
180 | |||
181 | /* | ||
182 | * fast_imageblit - optimized monochrome color expansion | ||
183 | * | ||
184 | * Only if: bits_per_pixel == 8, 16, or 32 | ||
185 | * image->width is divisible by pixel/dword (ppw); | ||
186 | * fix->line_legth is divisible by 4; | ||
187 | * beginning and end of a scanline is dword aligned | ||
188 | */ | ||
189 | static void fast_imageblit(const struct fb_image *image, struct fb_info *p, | ||
190 | void *dst1, u32 fgcolor, u32 bgcolor) | ||
191 | { | ||
192 | u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel; | ||
193 | u32 ppw = 32/bpp, spitch = (image->width + 7)/8; | ||
194 | u32 bit_mask, end_mask, eorx, shift; | ||
195 | const char *s = image->data, *src; | ||
196 | u32 *dst; | ||
197 | const u32 *tab = NULL; | ||
198 | int i, j, k; | ||
199 | |||
200 | switch (bpp) { | ||
201 | case 8: | ||
202 | tab = cfb_tab8; | ||
203 | break; | ||
204 | case 16: | ||
205 | tab = cfb_tab16; | ||
206 | break; | ||
207 | case 32: | ||
208 | default: | ||
209 | tab = cfb_tab32; | ||
210 | break; | ||
211 | } | ||
212 | |||
213 | for (i = ppw-1; i--; ) { | ||
214 | fgx <<= bpp; | ||
215 | bgx <<= bpp; | ||
216 | fgx |= fgcolor; | ||
217 | bgx |= bgcolor; | ||
218 | } | ||
219 | |||
220 | bit_mask = (1 << ppw) - 1; | ||
221 | eorx = fgx ^ bgx; | ||
222 | k = image->width/ppw; | ||
223 | |||
224 | for (i = image->height; i--; ) { | ||
225 | dst = dst1; | ||
226 | shift = 8; | ||
227 | src = s; | ||
228 | |||
229 | for (j = k; j--; ) { | ||
230 | shift -= ppw; | ||
231 | end_mask = tab[(*src >> shift) & bit_mask]; | ||
232 | *dst++ = (end_mask & eorx) ^ bgx; | ||
233 | if (!shift) { | ||
234 | shift = 8; | ||
235 | src++; | ||
236 | } | ||
237 | } | ||
238 | dst1 += p->fix.line_length; | ||
239 | s += spitch; | ||
240 | } | ||
241 | } | ||
242 | |||
243 | void sys_imageblit(struct fb_info *p, const struct fb_image *image) | ||
244 | { | ||
245 | u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0; | ||
246 | u32 bpl = sizeof(u32), bpp = p->var.bits_per_pixel; | ||
247 | u32 width = image->width; | ||
248 | u32 dx = image->dx, dy = image->dy; | ||
249 | void *dst1; | ||
250 | |||
251 | if (p->state != FBINFO_STATE_RUNNING) | ||
252 | return; | ||
253 | |||
254 | bitstart = (dy * p->fix.line_length * 8) + (dx * bpp); | ||
255 | start_index = bitstart & (32 - 1); | ||
256 | pitch_index = (p->fix.line_length & (bpl - 1)) * 8; | ||
257 | |||
258 | bitstart /= 8; | ||
259 | bitstart &= ~(bpl - 1); | ||
260 | dst1 = (void __force *)p->screen_base + bitstart; | ||
261 | |||
262 | if (p->fbops->fb_sync) | ||
263 | p->fbops->fb_sync(p); | ||
264 | |||
265 | if (image->depth == 1) { | ||
266 | if (p->fix.visual == FB_VISUAL_TRUECOLOR || | ||
267 | p->fix.visual == FB_VISUAL_DIRECTCOLOR) { | ||
268 | fgcolor = ((u32*)(p->pseudo_palette))[image->fg_color]; | ||
269 | bgcolor = ((u32*)(p->pseudo_palette))[image->bg_color]; | ||
270 | } else { | ||
271 | fgcolor = image->fg_color; | ||
272 | bgcolor = image->bg_color; | ||
273 | } | ||
274 | |||
275 | if (32 % bpp == 0 && !start_index && !pitch_index && | ||
276 | ((width & (32/bpp-1)) == 0) && | ||
277 | bpp >= 8 && bpp <= 32) | ||
278 | fast_imageblit(image, p, dst1, fgcolor, bgcolor); | ||
279 | else | ||
280 | slow_imageblit(image, p, dst1, fgcolor, bgcolor, | ||
281 | start_index, pitch_index); | ||
282 | } else | ||
283 | color_imageblit(image, p, dst1, start_index, pitch_index); | ||
284 | } | ||
285 | |||
286 | EXPORT_SYMBOL(sys_imageblit); | ||
287 | |||
288 | MODULE_AUTHOR("Antonino Daplas <adaplas@pol.net>"); | ||
289 | MODULE_DESCRIPTION("1-bit/8-bit to 1-32 bit color expansion (sys-to-sys)"); | ||
290 | MODULE_LICENSE("GPL"); | ||
291 | |||
diff --git a/drivers/video/tgafb.c b/drivers/video/tgafb.c index 7478d0e3e21..f0fde6ea7c3 100644 --- a/drivers/video/tgafb.c +++ b/drivers/video/tgafb.c | |||
@@ -5,27 +5,45 @@ | |||
5 | * Copyright (C) 1997 Geert Uytterhoeven | 5 | * Copyright (C) 1997 Geert Uytterhoeven |
6 | * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha | 6 | * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha |
7 | * Copyright (C) 2002 Richard Henderson | 7 | * Copyright (C) 2002 Richard Henderson |
8 | * Copyright (C) 2006 Maciej W. Rozycki | ||
8 | * | 9 | * |
9 | * This file is subject to the terms and conditions of the GNU General Public | 10 | * This file is subject to the terms and conditions of the GNU General Public |
10 | * License. See the file COPYING in the main directory of this archive for | 11 | * License. See the file COPYING in the main directory of this archive for |
11 | * more details. | 12 | * more details. |
12 | */ | 13 | */ |
13 | 14 | ||
14 | #include <linux/module.h> | 15 | #include <linux/bitrev.h> |
15 | #include <linux/kernel.h> | ||
16 | #include <linux/errno.h> | ||
17 | #include <linux/string.h> | ||
18 | #include <linux/mm.h> | ||
19 | #include <linux/slab.h> | ||
20 | #include <linux/delay.h> | 16 | #include <linux/delay.h> |
21 | #include <linux/init.h> | 17 | #include <linux/device.h> |
18 | #include <linux/errno.h> | ||
22 | #include <linux/fb.h> | 19 | #include <linux/fb.h> |
20 | #include <linux/init.h> | ||
21 | #include <linux/ioport.h> | ||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/mm.h> | ||
24 | #include <linux/module.h> | ||
23 | #include <linux/pci.h> | 25 | #include <linux/pci.h> |
24 | #include <linux/selection.h> | 26 | #include <linux/selection.h> |
25 | #include <linux/bitrev.h> | 27 | #include <linux/slab.h> |
28 | #include <linux/string.h> | ||
29 | #include <linux/tc.h> | ||
30 | |||
26 | #include <asm/io.h> | 31 | #include <asm/io.h> |
32 | |||
27 | #include <video/tgafb.h> | 33 | #include <video/tgafb.h> |
28 | 34 | ||
35 | #ifdef CONFIG_PCI | ||
36 | #define TGA_BUS_PCI(dev) (dev->bus == &pci_bus_type) | ||
37 | #else | ||
38 | #define TGA_BUS_PCI(dev) 0 | ||
39 | #endif | ||
40 | |||
41 | #ifdef CONFIG_TC | ||
42 | #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type) | ||
43 | #else | ||
44 | #define TGA_BUS_TC(dev) 0 | ||
45 | #endif | ||
46 | |||
29 | /* | 47 | /* |
30 | * Local functions. | 48 | * Local functions. |
31 | */ | 49 | */ |
@@ -41,14 +59,19 @@ static void tgafb_init_fix(struct fb_info *); | |||
41 | static void tgafb_imageblit(struct fb_info *, const struct fb_image *); | 59 | static void tgafb_imageblit(struct fb_info *, const struct fb_image *); |
42 | static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *); | 60 | static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *); |
43 | static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *); | 61 | static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *); |
62 | static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); | ||
44 | 63 | ||
45 | static int __devinit tgafb_pci_register(struct pci_dev *, | 64 | static int __devinit tgafb_register(struct device *dev); |
46 | const struct pci_device_id *); | 65 | static void __devexit tgafb_unregister(struct device *dev); |
47 | static void __devexit tgafb_pci_unregister(struct pci_dev *); | ||
48 | 66 | ||
49 | static const char *mode_option = "640x480@60"; | 67 | static const char *mode_option; |
68 | static const char *mode_option_pci = "640x480@60"; | ||
69 | static const char *mode_option_tc = "1280x1024@72"; | ||
50 | 70 | ||
51 | 71 | ||
72 | static struct pci_driver tgafb_pci_driver; | ||
73 | static struct tc_driver tgafb_tc_driver; | ||
74 | |||
52 | /* | 75 | /* |
53 | * Frame buffer operations | 76 | * Frame buffer operations |
54 | */ | 77 | */ |
@@ -59,15 +82,20 @@ static struct fb_ops tgafb_ops = { | |||
59 | .fb_set_par = tgafb_set_par, | 82 | .fb_set_par = tgafb_set_par, |
60 | .fb_setcolreg = tgafb_setcolreg, | 83 | .fb_setcolreg = tgafb_setcolreg, |
61 | .fb_blank = tgafb_blank, | 84 | .fb_blank = tgafb_blank, |
85 | .fb_pan_display = tgafb_pan_display, | ||
62 | .fb_fillrect = tgafb_fillrect, | 86 | .fb_fillrect = tgafb_fillrect, |
63 | .fb_copyarea = tgafb_copyarea, | 87 | .fb_copyarea = tgafb_copyarea, |
64 | .fb_imageblit = tgafb_imageblit, | 88 | .fb_imageblit = tgafb_imageblit, |
65 | }; | 89 | }; |
66 | 90 | ||
67 | 91 | ||
92 | #ifdef CONFIG_PCI | ||
68 | /* | 93 | /* |
69 | * PCI registration operations | 94 | * PCI registration operations |
70 | */ | 95 | */ |
96 | static int __devinit tgafb_pci_register(struct pci_dev *, | ||
97 | const struct pci_device_id *); | ||
98 | static void __devexit tgafb_pci_unregister(struct pci_dev *); | ||
71 | 99 | ||
72 | static struct pci_device_id const tgafb_pci_table[] = { | 100 | static struct pci_device_id const tgafb_pci_table[] = { |
73 | { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) }, | 101 | { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) }, |
@@ -75,13 +103,68 @@ static struct pci_device_id const tgafb_pci_table[] = { | |||
75 | }; | 103 | }; |
76 | MODULE_DEVICE_TABLE(pci, tgafb_pci_table); | 104 | MODULE_DEVICE_TABLE(pci, tgafb_pci_table); |
77 | 105 | ||
78 | static struct pci_driver tgafb_driver = { | 106 | static struct pci_driver tgafb_pci_driver = { |
79 | .name = "tgafb", | 107 | .name = "tgafb", |
80 | .id_table = tgafb_pci_table, | 108 | .id_table = tgafb_pci_table, |
81 | .probe = tgafb_pci_register, | 109 | .probe = tgafb_pci_register, |
82 | .remove = __devexit_p(tgafb_pci_unregister), | 110 | .remove = __devexit_p(tgafb_pci_unregister), |
83 | }; | 111 | }; |
84 | 112 | ||
113 | static int __devinit | ||
114 | tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) | ||
115 | { | ||
116 | return tgafb_register(&pdev->dev); | ||
117 | } | ||
118 | |||
119 | static void __devexit | ||
120 | tgafb_pci_unregister(struct pci_dev *pdev) | ||
121 | { | ||
122 | tgafb_unregister(&pdev->dev); | ||
123 | } | ||
124 | #endif /* CONFIG_PCI */ | ||
125 | |||
126 | #ifdef CONFIG_TC | ||
127 | /* | ||
128 | * TC registration operations | ||
129 | */ | ||
130 | static int __devinit tgafb_tc_register(struct device *); | ||
131 | static int __devexit tgafb_tc_unregister(struct device *); | ||
132 | |||
133 | static struct tc_device_id const tgafb_tc_table[] = { | ||
134 | { "DEC ", "PMAGD-AA" }, | ||
135 | { "DEC ", "PMAGD " }, | ||
136 | { } | ||
137 | }; | ||
138 | MODULE_DEVICE_TABLE(tc, tgafb_tc_table); | ||
139 | |||
140 | static struct tc_driver tgafb_tc_driver = { | ||
141 | .id_table = tgafb_tc_table, | ||
142 | .driver = { | ||
143 | .name = "tgafb", | ||
144 | .bus = &tc_bus_type, | ||
145 | .probe = tgafb_tc_register, | ||
146 | .remove = __devexit_p(tgafb_tc_unregister), | ||
147 | }, | ||
148 | }; | ||
149 | |||
150 | static int __devinit | ||
151 | tgafb_tc_register(struct device *dev) | ||
152 | { | ||
153 | int status = tgafb_register(dev); | ||
154 | if (!status) | ||
155 | get_device(dev); | ||
156 | return status; | ||
157 | } | ||
158 | |||
159 | static int __devexit | ||
160 | tgafb_tc_unregister(struct device *dev) | ||
161 | { | ||
162 | put_device(dev); | ||
163 | tgafb_unregister(dev); | ||
164 | return 0; | ||
165 | } | ||
166 | #endif /* CONFIG_TC */ | ||
167 | |||
85 | 168 | ||
86 | /** | 169 | /** |
87 | * tgafb_check_var - Optional function. Validates a var passed in. | 170 | * tgafb_check_var - Optional function. Validates a var passed in. |
@@ -132,10 +215,10 @@ static int | |||
132 | tgafb_set_par(struct fb_info *info) | 215 | tgafb_set_par(struct fb_info *info) |
133 | { | 216 | { |
134 | static unsigned int const deep_presets[4] = { | 217 | static unsigned int const deep_presets[4] = { |
135 | 0x00014000, | 218 | 0x00004000, |
136 | 0x0001440d, | 219 | 0x0000440d, |
137 | 0xffffffff, | 220 | 0xffffffff, |
138 | 0x0001441d | 221 | 0x0000441d |
139 | }; | 222 | }; |
140 | static unsigned int const rasterop_presets[4] = { | 223 | static unsigned int const rasterop_presets[4] = { |
141 | 0x00000003, | 224 | 0x00000003, |
@@ -157,6 +240,8 @@ tgafb_set_par(struct fb_info *info) | |||
157 | }; | 240 | }; |
158 | 241 | ||
159 | struct tga_par *par = (struct tga_par *) info->par; | 242 | struct tga_par *par = (struct tga_par *) info->par; |
243 | int tga_bus_pci = TGA_BUS_PCI(par->dev); | ||
244 | int tga_bus_tc = TGA_BUS_TC(par->dev); | ||
160 | u32 htimings, vtimings, pll_freq; | 245 | u32 htimings, vtimings, pll_freq; |
161 | u8 tga_type; | 246 | u8 tga_type; |
162 | int i; | 247 | int i; |
@@ -221,7 +306,7 @@ tgafb_set_par(struct fb_info *info) | |||
221 | TGA_WRITE_REG(par, vtimings, TGA_VERT_REG); | 306 | TGA_WRITE_REG(par, vtimings, TGA_VERT_REG); |
222 | 307 | ||
223 | /* Initalise RAMDAC. */ | 308 | /* Initalise RAMDAC. */ |
224 | if (tga_type == TGA_TYPE_8PLANE) { | 309 | if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) { |
225 | 310 | ||
226 | /* Init BT485 RAMDAC registers. */ | 311 | /* Init BT485 RAMDAC registers. */ |
227 | BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0), | 312 | BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0), |
@@ -236,21 +321,7 @@ tgafb_set_par(struct fb_info *info) | |||
236 | BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE); | 321 | BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE); |
237 | TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); | 322 | TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); |
238 | 323 | ||
239 | #ifdef CONFIG_HW_CONSOLE | ||
240 | for (i = 0; i < 16; i++) { | ||
241 | int j = color_table[i]; | ||
242 | |||
243 | TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8), | ||
244 | TGA_RAMDAC_REG); | ||
245 | TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8), | ||
246 | TGA_RAMDAC_REG); | ||
247 | TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8), | ||
248 | TGA_RAMDAC_REG); | ||
249 | } | ||
250 | for (i = 0; i < 240 * 3; i += 4) { | ||
251 | #else | ||
252 | for (i = 0; i < 256 * 3; i += 4) { | 324 | for (i = 0; i < 256 * 3; i += 4) { |
253 | #endif | ||
254 | TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8), | 325 | TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8), |
255 | TGA_RAMDAC_REG); | 326 | TGA_RAMDAC_REG); |
256 | TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8), | 327 | TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8), |
@@ -261,6 +332,27 @@ tgafb_set_par(struct fb_info *info) | |||
261 | TGA_RAMDAC_REG); | 332 | TGA_RAMDAC_REG); |
262 | } | 333 | } |
263 | 334 | ||
335 | } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) { | ||
336 | |||
337 | /* Init BT459 RAMDAC registers. */ | ||
338 | BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40); | ||
339 | BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00); | ||
340 | BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2, | ||
341 | (par->sync_on_green ? 0xc0 : 0x40)); | ||
342 | |||
343 | BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00); | ||
344 | |||
345 | /* Fill the palette. */ | ||
346 | BT459_LOAD_ADDR(par, 0x0000); | ||
347 | TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG); | ||
348 | |||
349 | for (i = 0; i < 256 * 3; i += 4) { | ||
350 | TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG); | ||
351 | TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); | ||
352 | TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); | ||
353 | TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); | ||
354 | } | ||
355 | |||
264 | } else { /* 24-plane or 24plusZ */ | 356 | } else { /* 24-plane or 24plusZ */ |
265 | 357 | ||
266 | /* Init BT463 RAMDAC registers. */ | 358 | /* Init BT463 RAMDAC registers. */ |
@@ -431,6 +523,8 @@ tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, | |||
431 | unsigned transp, struct fb_info *info) | 523 | unsigned transp, struct fb_info *info) |
432 | { | 524 | { |
433 | struct tga_par *par = (struct tga_par *) info->par; | 525 | struct tga_par *par = (struct tga_par *) info->par; |
526 | int tga_bus_pci = TGA_BUS_PCI(par->dev); | ||
527 | int tga_bus_tc = TGA_BUS_TC(par->dev); | ||
434 | 528 | ||
435 | if (regno > 255) | 529 | if (regno > 255) |
436 | return 1; | 530 | return 1; |
@@ -438,12 +532,18 @@ tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, | |||
438 | green >>= 8; | 532 | green >>= 8; |
439 | blue >>= 8; | 533 | blue >>= 8; |
440 | 534 | ||
441 | if (par->tga_type == TGA_TYPE_8PLANE) { | 535 | if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) { |
442 | BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE); | 536 | BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE); |
443 | TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); | 537 | TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); |
444 | TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); | 538 | TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); |
445 | TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); | 539 | TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); |
446 | TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); | 540 | TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); |
541 | } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) { | ||
542 | BT459_LOAD_ADDR(par, regno); | ||
543 | TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG); | ||
544 | TGA_WRITE_REG(par, red, TGA_RAMDAC_REG); | ||
545 | TGA_WRITE_REG(par, green, TGA_RAMDAC_REG); | ||
546 | TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG); | ||
447 | } else { | 547 | } else { |
448 | if (regno < 16) { | 548 | if (regno < 16) { |
449 | u32 value = (regno << 16) | (regno << 8) | regno; | 549 | u32 value = (regno << 16) | (regno << 8) | regno; |
@@ -523,16 +623,8 @@ tgafb_blank(int blank, struct fb_info *info) | |||
523 | * Acceleration. | 623 | * Acceleration. |
524 | */ | 624 | */ |
525 | 625 | ||
526 | /** | ||
527 | * tgafb_imageblit - REQUIRED function. Can use generic routines if | ||
528 | * non acclerated hardware and packed pixel based. | ||
529 | * Copies a image from system memory to the screen. | ||
530 | * | ||
531 | * @info: frame buffer structure that represents a single frame buffer | ||
532 | * @image: structure defining the image. | ||
533 | */ | ||
534 | static void | 626 | static void |
535 | tgafb_imageblit(struct fb_info *info, const struct fb_image *image) | 627 | tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image) |
536 | { | 628 | { |
537 | struct tga_par *par = (struct tga_par *) info->par; | 629 | struct tga_par *par = (struct tga_par *) info->par; |
538 | u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask; | 630 | u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask; |
@@ -542,6 +634,17 @@ tgafb_imageblit(struct fb_info *info, const struct fb_image *image) | |||
542 | void __iomem *regs_base; | 634 | void __iomem *regs_base; |
543 | void __iomem *fb_base; | 635 | void __iomem *fb_base; |
544 | 636 | ||
637 | is8bpp = info->var.bits_per_pixel == 8; | ||
638 | |||
639 | /* For copies that aren't pixel expansion, there's little we | ||
640 | can do better than the generic code. */ | ||
641 | /* ??? There is a DMA write mode; I wonder if that could be | ||
642 | made to pull the data from the image buffer... */ | ||
643 | if (image->depth > 1) { | ||
644 | cfb_imageblit(info, image); | ||
645 | return; | ||
646 | } | ||
647 | |||
545 | dx = image->dx; | 648 | dx = image->dx; |
546 | dy = image->dy; | 649 | dy = image->dy; |
547 | width = image->width; | 650 | width = image->width; |
@@ -559,18 +662,8 @@ tgafb_imageblit(struct fb_info *info, const struct fb_image *image) | |||
559 | if (dy + height > vyres) | 662 | if (dy + height > vyres) |
560 | height = vyres - dy; | 663 | height = vyres - dy; |
561 | 664 | ||
562 | /* For copies that aren't pixel expansion, there's little we | ||
563 | can do better than the generic code. */ | ||
564 | /* ??? There is a DMA write mode; I wonder if that could be | ||
565 | made to pull the data from the image buffer... */ | ||
566 | if (image->depth > 1) { | ||
567 | cfb_imageblit(info, image); | ||
568 | return; | ||
569 | } | ||
570 | |||
571 | regs_base = par->tga_regs_base; | 665 | regs_base = par->tga_regs_base; |
572 | fb_base = par->tga_fb_base; | 666 | fb_base = par->tga_fb_base; |
573 | is8bpp = info->var.bits_per_pixel == 8; | ||
574 | 667 | ||
575 | /* Expand the color values to fill 32-bits. */ | 668 | /* Expand the color values to fill 32-bits. */ |
576 | /* ??? Would be nice to notice colour changes elsewhere, so | 669 | /* ??? Would be nice to notice colour changes elsewhere, so |
@@ -748,6 +841,85 @@ tgafb_imageblit(struct fb_info *info, const struct fb_image *image) | |||
748 | regs_base + TGA_MODE_REG); | 841 | regs_base + TGA_MODE_REG); |
749 | } | 842 | } |
750 | 843 | ||
844 | static void | ||
845 | tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image) | ||
846 | { | ||
847 | struct tga_par *par = (struct tga_par *) info->par; | ||
848 | u32 color, dx, dy, width, height, vxres, vyres; | ||
849 | u32 *palette = ((u32 *)info->pseudo_palette); | ||
850 | unsigned long pos, line_length, i, j; | ||
851 | const unsigned char *data; | ||
852 | void *regs_base, *fb_base; | ||
853 | |||
854 | dx = image->dx; | ||
855 | dy = image->dy; | ||
856 | width = image->width; | ||
857 | height = image->height; | ||
858 | vxres = info->var.xres_virtual; | ||
859 | vyres = info->var.yres_virtual; | ||
860 | line_length = info->fix.line_length; | ||
861 | |||
862 | /* Crop the image to the screen. */ | ||
863 | if (dx > vxres || dy > vyres) | ||
864 | return; | ||
865 | if (dx + width > vxres) | ||
866 | width = vxres - dx; | ||
867 | if (dy + height > vyres) | ||
868 | height = vyres - dy; | ||
869 | |||
870 | regs_base = par->tga_regs_base; | ||
871 | fb_base = par->tga_fb_base; | ||
872 | |||
873 | pos = dy * line_length + (dx * 4); | ||
874 | data = image->data; | ||
875 | |||
876 | /* Now copy the image, color_expanding via the palette. */ | ||
877 | for (i = 0; i < height; i++) { | ||
878 | for (j = 0; j < width; j++) { | ||
879 | color = palette[*data++]; | ||
880 | __raw_writel(color, fb_base + pos + j*4); | ||
881 | } | ||
882 | pos += line_length; | ||
883 | } | ||
884 | } | ||
885 | |||
886 | /** | ||
887 | * tgafb_imageblit - REQUIRED function. Can use generic routines if | ||
888 | * non acclerated hardware and packed pixel based. | ||
889 | * Copies a image from system memory to the screen. | ||
890 | * | ||
891 | * @info: frame buffer structure that represents a single frame buffer | ||
892 | * @image: structure defining the image. | ||
893 | */ | ||
894 | static void | ||
895 | tgafb_imageblit(struct fb_info *info, const struct fb_image *image) | ||
896 | { | ||
897 | unsigned int is8bpp = info->var.bits_per_pixel == 8; | ||
898 | |||
899 | /* If a mono image, regardless of FB depth, go do it. */ | ||
900 | if (image->depth == 1) { | ||
901 | tgafb_mono_imageblit(info, image); | ||
902 | return; | ||
903 | } | ||
904 | |||
905 | /* For copies that aren't pixel expansion, there's little we | ||
906 | can do better than the generic code. */ | ||
907 | /* ??? There is a DMA write mode; I wonder if that could be | ||
908 | made to pull the data from the image buffer... */ | ||
909 | if (image->depth == info->var.bits_per_pixel) { | ||
910 | cfb_imageblit(info, image); | ||
911 | return; | ||
912 | } | ||
913 | |||
914 | /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */ | ||
915 | if (!is8bpp && image->depth == 8) { | ||
916 | tgafb_clut_imageblit(info, image); | ||
917 | return; | ||
918 | } | ||
919 | |||
920 | /* Silently return... */ | ||
921 | } | ||
922 | |||
751 | /** | 923 | /** |
752 | * tgafb_fillrect - REQUIRED function. Can use generic routines if | 924 | * tgafb_fillrect - REQUIRED function. Can use generic routines if |
753 | * non acclerated hardware and packed pixel based. | 925 | * non acclerated hardware and packed pixel based. |
@@ -1309,18 +1481,29 @@ static void | |||
1309 | tgafb_init_fix(struct fb_info *info) | 1481 | tgafb_init_fix(struct fb_info *info) |
1310 | { | 1482 | { |
1311 | struct tga_par *par = (struct tga_par *)info->par; | 1483 | struct tga_par *par = (struct tga_par *)info->par; |
1484 | int tga_bus_pci = TGA_BUS_PCI(par->dev); | ||
1485 | int tga_bus_tc = TGA_BUS_TC(par->dev); | ||
1312 | u8 tga_type = par->tga_type; | 1486 | u8 tga_type = par->tga_type; |
1313 | const char *tga_type_name; | 1487 | const char *tga_type_name = NULL; |
1314 | 1488 | ||
1315 | switch (tga_type) { | 1489 | switch (tga_type) { |
1316 | case TGA_TYPE_8PLANE: | 1490 | case TGA_TYPE_8PLANE: |
1317 | tga_type_name = "Digital ZLXp-E1"; | 1491 | if (tga_bus_pci) |
1492 | tga_type_name = "Digital ZLXp-E1"; | ||
1493 | if (tga_bus_tc) | ||
1494 | tga_type_name = "Digital ZLX-E1"; | ||
1318 | break; | 1495 | break; |
1319 | case TGA_TYPE_24PLANE: | 1496 | case TGA_TYPE_24PLANE: |
1320 | tga_type_name = "Digital ZLXp-E2"; | 1497 | if (tga_bus_pci) |
1498 | tga_type_name = "Digital ZLXp-E2"; | ||
1499 | if (tga_bus_tc) | ||
1500 | tga_type_name = "Digital ZLX-E2"; | ||
1321 | break; | 1501 | break; |
1322 | case TGA_TYPE_24PLUSZ: | 1502 | case TGA_TYPE_24PLUSZ: |
1323 | tga_type_name = "Digital ZLXp-E3"; | 1503 | if (tga_bus_pci) |
1504 | tga_type_name = "Digital ZLXp-E3"; | ||
1505 | if (tga_bus_tc) | ||
1506 | tga_type_name = "Digital ZLX-E3"; | ||
1324 | break; | 1507 | break; |
1325 | default: | 1508 | default: |
1326 | tga_type_name = "Unknown"; | 1509 | tga_type_name = "Unknown"; |
@@ -1346,11 +1529,37 @@ tgafb_init_fix(struct fb_info *info) | |||
1346 | info->fix.ywrapstep = 0; | 1529 | info->fix.ywrapstep = 0; |
1347 | 1530 | ||
1348 | info->fix.accel = FB_ACCEL_DEC_TGA; | 1531 | info->fix.accel = FB_ACCEL_DEC_TGA; |
1532 | |||
1533 | /* | ||
1534 | * These are needed by fb_set_logo_truepalette(), so we | ||
1535 | * set them here for 24-plane cards. | ||
1536 | */ | ||
1537 | if (tga_type != TGA_TYPE_8PLANE) { | ||
1538 | info->var.red.length = 8; | ||
1539 | info->var.green.length = 8; | ||
1540 | info->var.blue.length = 8; | ||
1541 | info->var.red.offset = 16; | ||
1542 | info->var.green.offset = 8; | ||
1543 | info->var.blue.offset = 0; | ||
1544 | } | ||
1349 | } | 1545 | } |
1350 | 1546 | ||
1351 | static __devinit int | 1547 | static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
1352 | tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) | 1548 | { |
1549 | /* We just use this to catch switches out of graphics mode. */ | ||
1550 | tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */ | ||
1551 | return 0; | ||
1552 | } | ||
1553 | |||
1554 | static int __devinit | ||
1555 | tgafb_register(struct device *dev) | ||
1353 | { | 1556 | { |
1557 | static const struct fb_videomode modedb_tc = { | ||
1558 | /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */ | ||
1559 | "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3, | ||
1560 | FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED | ||
1561 | }; | ||
1562 | |||
1354 | static unsigned int const fb_offset_presets[4] = { | 1563 | static unsigned int const fb_offset_presets[4] = { |
1355 | TGA_8PLANE_FB_OFFSET, | 1564 | TGA_8PLANE_FB_OFFSET, |
1356 | TGA_24PLANE_FB_OFFSET, | 1565 | TGA_24PLANE_FB_OFFSET, |
@@ -1358,40 +1567,51 @@ tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1358 | TGA_24PLUSZ_FB_OFFSET | 1567 | TGA_24PLUSZ_FB_OFFSET |
1359 | }; | 1568 | }; |
1360 | 1569 | ||
1570 | const struct fb_videomode *modedb_tga = NULL; | ||
1571 | resource_size_t bar0_start = 0, bar0_len = 0; | ||
1572 | const char *mode_option_tga = NULL; | ||
1573 | int tga_bus_pci = TGA_BUS_PCI(dev); | ||
1574 | int tga_bus_tc = TGA_BUS_TC(dev); | ||
1575 | unsigned int modedbsize_tga = 0; | ||
1361 | void __iomem *mem_base; | 1576 | void __iomem *mem_base; |
1362 | unsigned long bar0_start, bar0_len; | ||
1363 | struct fb_info *info; | 1577 | struct fb_info *info; |
1364 | struct tga_par *par; | 1578 | struct tga_par *par; |
1365 | u8 tga_type; | 1579 | u8 tga_type; |
1366 | int ret; | 1580 | int ret = 0; |
1367 | 1581 | ||
1368 | /* Enable device in PCI config. */ | 1582 | /* Enable device in PCI config. */ |
1369 | if (pci_enable_device(pdev)) { | 1583 | if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) { |
1370 | printk(KERN_ERR "tgafb: Cannot enable PCI device\n"); | 1584 | printk(KERN_ERR "tgafb: Cannot enable PCI device\n"); |
1371 | return -ENODEV; | 1585 | return -ENODEV; |
1372 | } | 1586 | } |
1373 | 1587 | ||
1374 | /* Allocate the fb and par structures. */ | 1588 | /* Allocate the fb and par structures. */ |
1375 | info = framebuffer_alloc(sizeof(struct tga_par), &pdev->dev); | 1589 | info = framebuffer_alloc(sizeof(struct tga_par), dev); |
1376 | if (!info) { | 1590 | if (!info) { |
1377 | printk(KERN_ERR "tgafb: Cannot allocate memory\n"); | 1591 | printk(KERN_ERR "tgafb: Cannot allocate memory\n"); |
1378 | return -ENOMEM; | 1592 | return -ENOMEM; |
1379 | } | 1593 | } |
1380 | 1594 | ||
1381 | par = info->par; | 1595 | par = info->par; |
1382 | pci_set_drvdata(pdev, info); | 1596 | dev_set_drvdata(dev, info); |
1383 | 1597 | ||
1384 | /* Request the mem regions. */ | 1598 | /* Request the mem regions. */ |
1385 | bar0_start = pci_resource_start(pdev, 0); | ||
1386 | bar0_len = pci_resource_len(pdev, 0); | ||
1387 | ret = -ENODEV; | 1599 | ret = -ENODEV; |
1600 | if (tga_bus_pci) { | ||
1601 | bar0_start = pci_resource_start(to_pci_dev(dev), 0); | ||
1602 | bar0_len = pci_resource_len(to_pci_dev(dev), 0); | ||
1603 | } | ||
1604 | if (tga_bus_tc) { | ||
1605 | bar0_start = to_tc_dev(dev)->resource.start; | ||
1606 | bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1; | ||
1607 | } | ||
1388 | if (!request_mem_region (bar0_start, bar0_len, "tgafb")) { | 1608 | if (!request_mem_region (bar0_start, bar0_len, "tgafb")) { |
1389 | printk(KERN_ERR "tgafb: cannot reserve FB region\n"); | 1609 | printk(KERN_ERR "tgafb: cannot reserve FB region\n"); |
1390 | goto err0; | 1610 | goto err0; |
1391 | } | 1611 | } |
1392 | 1612 | ||
1393 | /* Map the framebuffer. */ | 1613 | /* Map the framebuffer. */ |
1394 | mem_base = ioremap(bar0_start, bar0_len); | 1614 | mem_base = ioremap_nocache(bar0_start, bar0_len); |
1395 | if (!mem_base) { | 1615 | if (!mem_base) { |
1396 | printk(KERN_ERR "tgafb: Cannot map MMIO\n"); | 1616 | printk(KERN_ERR "tgafb: Cannot map MMIO\n"); |
1397 | goto err1; | 1617 | goto err1; |
@@ -1399,12 +1619,16 @@ tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1399 | 1619 | ||
1400 | /* Grab info about the card. */ | 1620 | /* Grab info about the card. */ |
1401 | tga_type = (readl(mem_base) >> 12) & 0x0f; | 1621 | tga_type = (readl(mem_base) >> 12) & 0x0f; |
1402 | par->pdev = pdev; | 1622 | par->dev = dev; |
1403 | par->tga_mem_base = mem_base; | 1623 | par->tga_mem_base = mem_base; |
1404 | par->tga_fb_base = mem_base + fb_offset_presets[tga_type]; | 1624 | par->tga_fb_base = mem_base + fb_offset_presets[tga_type]; |
1405 | par->tga_regs_base = mem_base + TGA_REGS_OFFSET; | 1625 | par->tga_regs_base = mem_base + TGA_REGS_OFFSET; |
1406 | par->tga_type = tga_type; | 1626 | par->tga_type = tga_type; |
1407 | pci_read_config_byte(pdev, PCI_REVISION_ID, &par->tga_chip_rev); | 1627 | if (tga_bus_pci) |
1628 | pci_read_config_byte(to_pci_dev(dev), PCI_REVISION_ID, | ||
1629 | &par->tga_chip_rev); | ||
1630 | if (tga_bus_tc) | ||
1631 | par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff; | ||
1408 | 1632 | ||
1409 | /* Setup framebuffer. */ | 1633 | /* Setup framebuffer. */ |
1410 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | | 1634 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | |
@@ -1414,8 +1638,17 @@ tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1414 | info->pseudo_palette = (void *)(par + 1); | 1638 | info->pseudo_palette = (void *)(par + 1); |
1415 | 1639 | ||
1416 | /* This should give a reasonable default video mode. */ | 1640 | /* This should give a reasonable default video mode. */ |
1417 | 1641 | if (tga_bus_pci) { | |
1418 | ret = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, | 1642 | mode_option_tga = mode_option_pci; |
1643 | } | ||
1644 | if (tga_bus_tc) { | ||
1645 | mode_option_tga = mode_option_tc; | ||
1646 | modedb_tga = &modedb_tc; | ||
1647 | modedbsize_tga = 1; | ||
1648 | } | ||
1649 | ret = fb_find_mode(&info->var, info, | ||
1650 | mode_option ? mode_option : mode_option_tga, | ||
1651 | modedb_tga, modedbsize_tga, NULL, | ||
1419 | tga_type == TGA_TYPE_8PLANE ? 8 : 32); | 1652 | tga_type == TGA_TYPE_8PLANE ? 8 : 32); |
1420 | if (ret == 0 || ret == 4) { | 1653 | if (ret == 0 || ret == 4) { |
1421 | printk(KERN_ERR "tgafb: Could not find valid video mode\n"); | 1654 | printk(KERN_ERR "tgafb: Could not find valid video mode\n"); |
@@ -1438,13 +1671,19 @@ tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1438 | goto err1; | 1671 | goto err1; |
1439 | } | 1672 | } |
1440 | 1673 | ||
1441 | printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n", | 1674 | if (tga_bus_pci) { |
1442 | par->tga_chip_rev); | 1675 | pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n", |
1443 | printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n", | 1676 | par->tga_chip_rev); |
1444 | pdev->bus->number, PCI_SLOT(pdev->devfn), | 1677 | pr_info("tgafb: at PCI bus %d, device %d, function %d\n", |
1445 | PCI_FUNC(pdev->devfn)); | 1678 | to_pci_dev(dev)->bus->number, |
1446 | printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n", | 1679 | PCI_SLOT(to_pci_dev(dev)->devfn), |
1447 | info->node, info->fix.id, bar0_start); | 1680 | PCI_FUNC(to_pci_dev(dev)->devfn)); |
1681 | } | ||
1682 | if (tga_bus_tc) | ||
1683 | pr_info("tgafb: SFB+ detected, rev=0x%02x\n", | ||
1684 | par->tga_chip_rev); | ||
1685 | pr_info("fb%d: %s frame buffer device at 0x%lx\n", | ||
1686 | info->node, info->fix.id, (long)bar0_start); | ||
1448 | 1687 | ||
1449 | return 0; | 1688 | return 0; |
1450 | 1689 | ||
@@ -1458,25 +1697,39 @@ tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1458 | } | 1697 | } |
1459 | 1698 | ||
1460 | static void __devexit | 1699 | static void __devexit |
1461 | tgafb_pci_unregister(struct pci_dev *pdev) | 1700 | tgafb_unregister(struct device *dev) |
1462 | { | 1701 | { |
1463 | struct fb_info *info = pci_get_drvdata(pdev); | 1702 | resource_size_t bar0_start = 0, bar0_len = 0; |
1464 | struct tga_par *par = info->par; | 1703 | int tga_bus_pci = TGA_BUS_PCI(dev); |
1704 | int tga_bus_tc = TGA_BUS_TC(dev); | ||
1705 | struct fb_info *info = NULL; | ||
1706 | struct tga_par *par; | ||
1465 | 1707 | ||
1708 | info = dev_get_drvdata(dev); | ||
1466 | if (!info) | 1709 | if (!info) |
1467 | return; | 1710 | return; |
1711 | |||
1712 | par = info->par; | ||
1468 | unregister_framebuffer(info); | 1713 | unregister_framebuffer(info); |
1469 | fb_dealloc_cmap(&info->cmap); | 1714 | fb_dealloc_cmap(&info->cmap); |
1470 | iounmap(par->tga_mem_base); | 1715 | iounmap(par->tga_mem_base); |
1471 | release_mem_region(pci_resource_start(pdev, 0), | 1716 | if (tga_bus_pci) { |
1472 | pci_resource_len(pdev, 0)); | 1717 | bar0_start = pci_resource_start(to_pci_dev(dev), 0); |
1718 | bar0_len = pci_resource_len(to_pci_dev(dev), 0); | ||
1719 | } | ||
1720 | if (tga_bus_tc) { | ||
1721 | bar0_start = to_tc_dev(dev)->resource.start; | ||
1722 | bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1; | ||
1723 | } | ||
1724 | release_mem_region(bar0_start, bar0_len); | ||
1473 | framebuffer_release(info); | 1725 | framebuffer_release(info); |
1474 | } | 1726 | } |
1475 | 1727 | ||
1476 | static void __devexit | 1728 | static void __devexit |
1477 | tgafb_exit(void) | 1729 | tgafb_exit(void) |
1478 | { | 1730 | { |
1479 | pci_unregister_driver(&tgafb_driver); | 1731 | tc_unregister_driver(&tgafb_tc_driver); |
1732 | pci_unregister_driver(&tgafb_pci_driver); | ||
1480 | } | 1733 | } |
1481 | 1734 | ||
1482 | #ifndef MODULE | 1735 | #ifndef MODULE |
@@ -1505,6 +1758,7 @@ tgafb_setup(char *arg) | |||
1505 | static int __devinit | 1758 | static int __devinit |
1506 | tgafb_init(void) | 1759 | tgafb_init(void) |
1507 | { | 1760 | { |
1761 | int status; | ||
1508 | #ifndef MODULE | 1762 | #ifndef MODULE |
1509 | char *option = NULL; | 1763 | char *option = NULL; |
1510 | 1764 | ||
@@ -1512,7 +1766,10 @@ tgafb_init(void) | |||
1512 | return -ENODEV; | 1766 | return -ENODEV; |
1513 | tgafb_setup(option); | 1767 | tgafb_setup(option); |
1514 | #endif | 1768 | #endif |
1515 | return pci_register_driver(&tgafb_driver); | 1769 | status = pci_register_driver(&tgafb_pci_driver); |
1770 | if (!status) | ||
1771 | status = tc_register_driver(&tgafb_tc_driver); | ||
1772 | return status; | ||
1516 | } | 1773 | } |
1517 | 1774 | ||
1518 | /* | 1775 | /* |
@@ -1522,5 +1779,5 @@ tgafb_init(void) | |||
1522 | module_init(tgafb_init); | 1779 | module_init(tgafb_init); |
1523 | module_exit(tgafb_exit); | 1780 | module_exit(tgafb_exit); |
1524 | 1781 | ||
1525 | MODULE_DESCRIPTION("framebuffer driver for TGA chipset"); | 1782 | MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset"); |
1526 | MODULE_LICENSE("GPL"); | 1783 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/video/vermilion/Makefile b/drivers/video/vermilion/Makefile new file mode 100644 index 00000000000..cc21a656153 --- /dev/null +++ b/drivers/video/vermilion/Makefile | |||
@@ -0,0 +1,5 @@ | |||
1 | obj-$(CONFIG_FB_LE80578) += vmlfb.o | ||
2 | obj-$(CONFIG_FB_CARILLO_RANCH) += crvml.o | ||
3 | |||
4 | vmlfb-objs := vermilion.o | ||
5 | crvml-objs := cr_pll.o | ||
diff --git a/drivers/video/vermilion/cr_pll.c b/drivers/video/vermilion/cr_pll.c new file mode 100644 index 00000000000..ebc6e6e0dd0 --- /dev/null +++ b/drivers/video/vermilion/cr_pll.c | |||
@@ -0,0 +1,208 @@ | |||
1 | /* | ||
2 | * Copyright (c) Intel Corp. 2007. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
6 | * develop this driver. | ||
7 | * | ||
8 | * This file is part of the Carillo Ranch video subsystem driver. | ||
9 | * The Carillo Ranch video subsystem driver is free software; | ||
10 | * you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * The Carillo Ranch video subsystem driver is distributed | ||
16 | * in the hope that it will be useful, | ||
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
19 | * GNU General Public License for more details. | ||
20 | * | ||
21 | * You should have received a copy of the GNU General Public License | ||
22 | * along with this driver; if not, write to the Free Software | ||
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
24 | * | ||
25 | * Authors: | ||
26 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | ||
27 | * Alan Hourihane <alanh-at-tungstengraphics-dot-com> | ||
28 | */ | ||
29 | |||
30 | #include <linux/module.h> | ||
31 | #include <linux/kernel.h> | ||
32 | #include <linux/pci.h> | ||
33 | #include <linux/errno.h> | ||
34 | #include <linux/fb.h> | ||
35 | #include "vermilion.h" | ||
36 | |||
37 | /* The PLL Clock register sits on Host bridge */ | ||
38 | #define CRVML_DEVICE_MCH 0x5001 | ||
39 | #define CRVML_REG_MCHBAR 0x44 | ||
40 | #define CRVML_REG_MCHEN 0x54 | ||
41 | #define CRVML_MCHEN_BIT (1 << 28) | ||
42 | #define CRVML_MCHMAP_SIZE 4096 | ||
43 | #define CRVML_REG_CLOCK 0xc3c | ||
44 | #define CRVML_CLOCK_SHIFT 8 | ||
45 | #define CRVML_CLOCK_MASK 0x00000f00 | ||
46 | |||
47 | static struct pci_dev *mch_dev; | ||
48 | static u32 mch_bar; | ||
49 | static void __iomem *mch_regs_base; | ||
50 | static u32 saved_clock; | ||
51 | |||
52 | static const unsigned crvml_clocks[] = { | ||
53 | 6750, | ||
54 | 13500, | ||
55 | 27000, | ||
56 | 29700, | ||
57 | 37125, | ||
58 | 54000, | ||
59 | 59400, | ||
60 | 74250, | ||
61 | 120000 | ||
62 | /* | ||
63 | * There are more clocks, but they are disabled on the CR board. | ||
64 | */ | ||
65 | }; | ||
66 | |||
67 | static const u32 crvml_clock_bits[] = { | ||
68 | 0x0a, | ||
69 | 0x09, | ||
70 | 0x08, | ||
71 | 0x07, | ||
72 | 0x06, | ||
73 | 0x05, | ||
74 | 0x04, | ||
75 | 0x03, | ||
76 | 0x0b | ||
77 | }; | ||
78 | |||
79 | static const unsigned crvml_num_clocks = ARRAY_SIZE(crvml_clocks); | ||
80 | |||
81 | static int crvml_sys_restore(struct vml_sys *sys) | ||
82 | { | ||
83 | void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK; | ||
84 | |||
85 | iowrite32(saved_clock, clock_reg); | ||
86 | ioread32(clock_reg); | ||
87 | |||
88 | return 0; | ||
89 | } | ||
90 | |||
91 | static int crvml_sys_save(struct vml_sys *sys) | ||
92 | { | ||
93 | void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK; | ||
94 | |||
95 | saved_clock = ioread32(clock_reg); | ||
96 | |||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | static int crvml_nearest_index(const struct vml_sys *sys, int clock) | ||
101 | { | ||
102 | int i; | ||
103 | int cur_index = 0; | ||
104 | int cur_diff; | ||
105 | int diff; | ||
106 | |||
107 | cur_diff = clock - crvml_clocks[0]; | ||
108 | cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff; | ||
109 | for (i = 1; i < crvml_num_clocks; ++i) { | ||
110 | diff = clock - crvml_clocks[i]; | ||
111 | diff = (diff < 0) ? -diff : diff; | ||
112 | if (diff < cur_diff) { | ||
113 | cur_index = i; | ||
114 | cur_diff = diff; | ||
115 | } | ||
116 | } | ||
117 | return cur_index; | ||
118 | } | ||
119 | |||
120 | static int crvml_nearest_clock(const struct vml_sys *sys, int clock) | ||
121 | { | ||
122 | return crvml_clocks[crvml_nearest_index(sys, clock)]; | ||
123 | } | ||
124 | |||
125 | static int crvml_set_clock(struct vml_sys *sys, int clock) | ||
126 | { | ||
127 | void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK; | ||
128 | int index; | ||
129 | u32 clock_val; | ||
130 | |||
131 | index = crvml_nearest_index(sys, clock); | ||
132 | |||
133 | if (crvml_clocks[index] != clock) | ||
134 | return -EINVAL; | ||
135 | |||
136 | clock_val = ioread32(clock_reg) & ~CRVML_CLOCK_MASK; | ||
137 | clock_val = crvml_clock_bits[index] << CRVML_CLOCK_SHIFT; | ||
138 | iowrite32(clock_val, clock_reg); | ||
139 | ioread32(clock_reg); | ||
140 | |||
141 | return 0; | ||
142 | } | ||
143 | |||
144 | static struct vml_sys cr_pll_ops = { | ||
145 | .name = "Carillo Ranch", | ||
146 | .save = crvml_sys_save, | ||
147 | .restore = crvml_sys_restore, | ||
148 | .set_clock = crvml_set_clock, | ||
149 | .nearest_clock = crvml_nearest_clock, | ||
150 | }; | ||
151 | |||
152 | static int __init cr_pll_init(void) | ||
153 | { | ||
154 | int err; | ||
155 | u32 dev_en; | ||
156 | |||
157 | mch_dev = pci_get_device(PCI_VENDOR_ID_INTEL, | ||
158 | CRVML_DEVICE_MCH, NULL); | ||
159 | if (!mch_dev) { | ||
160 | printk(KERN_ERR | ||
161 | "Could not find Carillo Ranch MCH device.\n"); | ||
162 | return -ENODEV; | ||
163 | } | ||
164 | |||
165 | pci_read_config_dword(mch_dev, CRVML_REG_MCHEN, &dev_en); | ||
166 | if (!(dev_en & CRVML_MCHEN_BIT)) { | ||
167 | printk(KERN_ERR | ||
168 | "Carillo Ranch MCH device was not enabled.\n"); | ||
169 | pci_dev_put(mch_dev); | ||
170 | return -ENODEV; | ||
171 | } | ||
172 | |||
173 | pci_read_config_dword(mch_dev, CRVML_REG_MCHBAR, | ||
174 | &mch_bar); | ||
175 | mch_regs_base = | ||
176 | ioremap_nocache(mch_bar, CRVML_MCHMAP_SIZE); | ||
177 | if (!mch_regs_base) { | ||
178 | printk(KERN_ERR | ||
179 | "Carillo Ranch MCH device was not enabled.\n"); | ||
180 | pci_dev_put(mch_dev); | ||
181 | return -ENODEV; | ||
182 | } | ||
183 | |||
184 | err = vmlfb_register_subsys(&cr_pll_ops); | ||
185 | if (err) { | ||
186 | printk(KERN_ERR | ||
187 | "Carillo Ranch failed to initialize vml_sys.\n"); | ||
188 | pci_dev_put(mch_dev); | ||
189 | return err; | ||
190 | } | ||
191 | |||
192 | return 0; | ||
193 | } | ||
194 | |||
195 | static void __exit cr_pll_exit(void) | ||
196 | { | ||
197 | vmlfb_unregister_subsys(&cr_pll_ops); | ||
198 | |||
199 | iounmap(mch_regs_base); | ||
200 | pci_dev_put(mch_dev); | ||
201 | } | ||
202 | |||
203 | module_init(cr_pll_init); | ||
204 | module_exit(cr_pll_exit); | ||
205 | |||
206 | MODULE_AUTHOR("Tungsten Graphics Inc."); | ||
207 | MODULE_DESCRIPTION("Carillo Ranch PLL Driver"); | ||
208 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/vermilion/vermilion.c b/drivers/video/vermilion/vermilion.c new file mode 100644 index 00000000000..de531c90771 --- /dev/null +++ b/drivers/video/vermilion/vermilion.c | |||
@@ -0,0 +1,1195 @@ | |||
1 | /* | ||
2 | * Copyright (c) Intel Corp. 2007. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
6 | * develop this driver. | ||
7 | * | ||
8 | * This file is part of the Vermilion Range fb driver. | ||
9 | * The Vermilion Range fb driver is free software; | ||
10 | * you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * The Vermilion Range fb driver is distributed | ||
16 | * in the hope that it will be useful, | ||
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
19 | * GNU General Public License for more details. | ||
20 | * | ||
21 | * You should have received a copy of the GNU General Public License | ||
22 | * along with this driver; if not, write to the Free Software | ||
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
24 | * | ||
25 | * Authors: | ||
26 | * Thomas Hellstr�m <thomas-at-tungstengraphics-dot-com> | ||
27 | * Michel D�nzer <michel-at-tungstengraphics-dot-com> | ||
28 | * Alan Hourihane <alanh-at-tungstengraphics-dot-com> | ||
29 | */ | ||
30 | |||
31 | #include <linux/module.h> | ||
32 | #include <linux/kernel.h> | ||
33 | #include <linux/errno.h> | ||
34 | #include <linux/string.h> | ||
35 | #include <linux/delay.h> | ||
36 | #include <linux/mm.h> | ||
37 | #include <linux/fb.h> | ||
38 | #include <linux/pci.h> | ||
39 | #include <asm/cacheflush.h> | ||
40 | #include <asm/tlbflush.h> | ||
41 | #include <linux/mmzone.h> | ||
42 | #include <asm/uaccess.h> | ||
43 | |||
44 | /* #define VERMILION_DEBUG */ | ||
45 | |||
46 | #include "vermilion.h" | ||
47 | |||
48 | #define MODULE_NAME "vmlfb" | ||
49 | |||
50 | #define VML_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16) | ||
51 | |||
52 | static struct mutex vml_mutex; | ||
53 | static struct list_head global_no_mode; | ||
54 | static struct list_head global_has_mode; | ||
55 | static struct fb_ops vmlfb_ops; | ||
56 | static struct vml_sys *subsys = NULL; | ||
57 | static char *vml_default_mode = "1024x768@60"; | ||
58 | static struct fb_videomode defaultmode = { | ||
59 | NULL, 60, 1024, 768, 12896, 144, 24, 29, 3, 136, 6, | ||
60 | 0, FB_VMODE_NONINTERLACED | ||
61 | }; | ||
62 | |||
63 | static u32 vml_mem_requested = (10 * 1024 * 1024); | ||
64 | static u32 vml_mem_contig = (4 * 1024 * 1024); | ||
65 | static u32 vml_mem_min = (4 * 1024 * 1024); | ||
66 | |||
67 | static u32 vml_clocks[] = { | ||
68 | 6750, | ||
69 | 13500, | ||
70 | 27000, | ||
71 | 29700, | ||
72 | 37125, | ||
73 | 54000, | ||
74 | 59400, | ||
75 | 74250, | ||
76 | 120000, | ||
77 | 148500 | ||
78 | }; | ||
79 | |||
80 | static u32 vml_num_clocks = ARRAY_SIZE(vml_clocks); | ||
81 | |||
82 | /* | ||
83 | * Allocate a contiguous vram area and make its linear kernel map | ||
84 | * uncached. | ||
85 | */ | ||
86 | |||
87 | static int vmlfb_alloc_vram_area(struct vram_area *va, unsigned max_order, | ||
88 | unsigned min_order) | ||
89 | { | ||
90 | gfp_t flags; | ||
91 | unsigned long i; | ||
92 | pgprot_t wc_pageprot; | ||
93 | |||
94 | wc_pageprot = PAGE_KERNEL_NOCACHE; | ||
95 | max_order++; | ||
96 | do { | ||
97 | /* | ||
98 | * Really try hard to get the needed memory. | ||
99 | * We need memory below the first 32MB, so we | ||
100 | * add the __GFP_DMA flag that guarantees that we are | ||
101 | * below the first 16MB. | ||
102 | */ | ||
103 | |||
104 | flags = __GFP_DMA | __GFP_HIGH; | ||
105 | va->logical = | ||
106 | __get_free_pages(flags, --max_order); | ||
107 | } while (va->logical == 0 && max_order > min_order); | ||
108 | |||
109 | if (!va->logical) | ||
110 | return -ENOMEM; | ||
111 | |||
112 | va->phys = virt_to_phys((void *)va->logical); | ||
113 | va->size = PAGE_SIZE << max_order; | ||
114 | va->order = max_order; | ||
115 | |||
116 | /* | ||
117 | * It seems like __get_free_pages only ups the usage count | ||
118 | * of the first page. This doesn't work with nopage mapping, so | ||
119 | * up the usage count once more. | ||
120 | */ | ||
121 | |||
122 | memset((void *)va->logical, 0x00, va->size); | ||
123 | for (i = va->logical; i < va->logical + va->size; i += PAGE_SIZE) { | ||
124 | get_page(virt_to_page(i)); | ||
125 | } | ||
126 | |||
127 | /* | ||
128 | * Change caching policy of the linear kernel map to avoid | ||
129 | * mapping type conflicts with user-space mappings. | ||
130 | * The first global_flush_tlb() is really only there to do a global | ||
131 | * wbinvd(). | ||
132 | */ | ||
133 | |||
134 | global_flush_tlb(); | ||
135 | change_page_attr(virt_to_page(va->logical), va->size >> PAGE_SHIFT, | ||
136 | wc_pageprot); | ||
137 | global_flush_tlb(); | ||
138 | |||
139 | printk(KERN_DEBUG MODULE_NAME | ||
140 | ": Allocated %ld bytes vram area at 0x%08lx\n", | ||
141 | va->size, va->phys); | ||
142 | |||
143 | return 0; | ||
144 | } | ||
145 | |||
146 | /* | ||
147 | * Free a contiguous vram area and reset its linear kernel map | ||
148 | * mapping type. | ||
149 | */ | ||
150 | |||
151 | static void vmlfb_free_vram_area(struct vram_area *va) | ||
152 | { | ||
153 | unsigned long j; | ||
154 | |||
155 | if (va->logical) { | ||
156 | |||
157 | /* | ||
158 | * Reset the linear kernel map caching policy. | ||
159 | */ | ||
160 | |||
161 | change_page_attr(virt_to_page(va->logical), | ||
162 | va->size >> PAGE_SHIFT, PAGE_KERNEL); | ||
163 | global_flush_tlb(); | ||
164 | |||
165 | /* | ||
166 | * Decrease the usage count on the pages we've used | ||
167 | * to compensate for upping when allocating. | ||
168 | */ | ||
169 | |||
170 | for (j = va->logical; j < va->logical + va->size; | ||
171 | j += PAGE_SIZE) { | ||
172 | (void)put_page_testzero(virt_to_page(j)); | ||
173 | } | ||
174 | |||
175 | printk(KERN_DEBUG MODULE_NAME | ||
176 | ": Freeing %ld bytes vram area at 0x%08lx\n", | ||
177 | va->size, va->phys); | ||
178 | free_pages(va->logical, va->order); | ||
179 | |||
180 | va->logical = 0; | ||
181 | } | ||
182 | } | ||
183 | |||
184 | /* | ||
185 | * Free allocated vram. | ||
186 | */ | ||
187 | |||
188 | static void vmlfb_free_vram(struct vml_info *vinfo) | ||
189 | { | ||
190 | int i; | ||
191 | |||
192 | for (i = 0; i < vinfo->num_areas; ++i) { | ||
193 | vmlfb_free_vram_area(&vinfo->vram[i]); | ||
194 | } | ||
195 | vinfo->num_areas = 0; | ||
196 | } | ||
197 | |||
198 | /* | ||
199 | * Allocate vram. Currently we try to allocate contiguous areas from the | ||
200 | * __GFP_DMA zone and puzzle them together. A better approach would be to | ||
201 | * allocate one contiguous area for scanout and use one-page allocations for | ||
202 | * offscreen areas. This requires user-space and GPU virtual mappings. | ||
203 | */ | ||
204 | |||
205 | static int vmlfb_alloc_vram(struct vml_info *vinfo, | ||
206 | size_t requested, | ||
207 | size_t min_total, size_t min_contig) | ||
208 | { | ||
209 | int i, j; | ||
210 | int order; | ||
211 | int contiguous; | ||
212 | int err; | ||
213 | struct vram_area *va; | ||
214 | struct vram_area *va2; | ||
215 | |||
216 | vinfo->num_areas = 0; | ||
217 | for (i = 0; i < VML_VRAM_AREAS; ++i) { | ||
218 | va = &vinfo->vram[i]; | ||
219 | order = 0; | ||
220 | |||
221 | while (requested > (PAGE_SIZE << order) && order < MAX_ORDER) | ||
222 | order++; | ||
223 | |||
224 | err = vmlfb_alloc_vram_area(va, order, 0); | ||
225 | |||
226 | if (err) | ||
227 | break; | ||
228 | |||
229 | if (i == 0) { | ||
230 | vinfo->vram_start = va->phys; | ||
231 | vinfo->vram_logical = (void __iomem *) va->logical; | ||
232 | vinfo->vram_contig_size = va->size; | ||
233 | vinfo->num_areas = 1; | ||
234 | } else { | ||
235 | contiguous = 0; | ||
236 | |||
237 | for (j = 0; j < i; ++j) { | ||
238 | va2 = &vinfo->vram[j]; | ||
239 | if (va->phys + va->size == va2->phys || | ||
240 | va2->phys + va2->size == va->phys) { | ||
241 | contiguous = 1; | ||
242 | break; | ||
243 | } | ||
244 | } | ||
245 | |||
246 | if (contiguous) { | ||
247 | vinfo->num_areas++; | ||
248 | if (va->phys < vinfo->vram_start) { | ||
249 | vinfo->vram_start = va->phys; | ||
250 | vinfo->vram_logical = | ||
251 | (void __iomem *)va->logical; | ||
252 | } | ||
253 | vinfo->vram_contig_size += va->size; | ||
254 | } else { | ||
255 | vmlfb_free_vram_area(va); | ||
256 | break; | ||
257 | } | ||
258 | } | ||
259 | |||
260 | if (requested < va->size) | ||
261 | break; | ||
262 | else | ||
263 | requested -= va->size; | ||
264 | } | ||
265 | |||
266 | if (vinfo->vram_contig_size > min_total && | ||
267 | vinfo->vram_contig_size > min_contig) { | ||
268 | |||
269 | printk(KERN_DEBUG MODULE_NAME | ||
270 | ": Contiguous vram: %ld bytes at physical 0x%08lx.\n", | ||
271 | (unsigned long)vinfo->vram_contig_size, | ||
272 | (unsigned long)vinfo->vram_start); | ||
273 | |||
274 | return 0; | ||
275 | } | ||
276 | |||
277 | printk(KERN_ERR MODULE_NAME | ||
278 | ": Could not allocate requested minimal amount of vram.\n"); | ||
279 | |||
280 | vmlfb_free_vram(vinfo); | ||
281 | |||
282 | return -ENOMEM; | ||
283 | } | ||
284 | |||
285 | /* | ||
286 | * Find the GPU to use with our display controller. | ||
287 | */ | ||
288 | |||
289 | static int vmlfb_get_gpu(struct vml_par *par) | ||
290 | { | ||
291 | mutex_lock(&vml_mutex); | ||
292 | |||
293 | par->gpu = pci_get_device(PCI_VENDOR_ID_INTEL, VML_DEVICE_GPU, NULL); | ||
294 | |||
295 | if (!par->gpu) { | ||
296 | mutex_unlock(&vml_mutex); | ||
297 | return -ENODEV; | ||
298 | } | ||
299 | |||
300 | mutex_unlock(&vml_mutex); | ||
301 | |||
302 | if (pci_enable_device(par->gpu) < 0) | ||
303 | return -ENODEV; | ||
304 | |||
305 | return 0; | ||
306 | } | ||
307 | |||
308 | /* | ||
309 | * Find a contiguous vram area that contains a given offset from vram start. | ||
310 | */ | ||
311 | static int vmlfb_vram_offset(struct vml_info *vinfo, unsigned long offset) | ||
312 | { | ||
313 | unsigned long aoffset; | ||
314 | unsigned i; | ||
315 | |||
316 | for (i = 0; i < vinfo->num_areas; ++i) { | ||
317 | aoffset = offset - (vinfo->vram[i].phys - vinfo->vram_start); | ||
318 | |||
319 | if (aoffset < vinfo->vram[i].size) { | ||
320 | return 0; | ||
321 | } | ||
322 | } | ||
323 | |||
324 | return -EINVAL; | ||
325 | } | ||
326 | |||
327 | /* | ||
328 | * Remap the MMIO register spaces of the VDC and the GPU. | ||
329 | */ | ||
330 | |||
331 | static int vmlfb_enable_mmio(struct vml_par *par) | ||
332 | { | ||
333 | int err; | ||
334 | |||
335 | par->vdc_mem_base = pci_resource_start(par->vdc, 0); | ||
336 | par->vdc_mem_size = pci_resource_len(par->vdc, 0); | ||
337 | if (!request_mem_region(par->vdc_mem_base, par->vdc_mem_size, "vmlfb")) { | ||
338 | printk(KERN_ERR MODULE_NAME | ||
339 | ": Could not claim display controller MMIO.\n"); | ||
340 | return -EBUSY; | ||
341 | } | ||
342 | par->vdc_mem = ioremap_nocache(par->vdc_mem_base, par->vdc_mem_size); | ||
343 | if (par->vdc_mem == NULL) { | ||
344 | printk(KERN_ERR MODULE_NAME | ||
345 | ": Could not map display controller MMIO.\n"); | ||
346 | err = -ENOMEM; | ||
347 | goto out_err_0; | ||
348 | } | ||
349 | |||
350 | par->gpu_mem_base = pci_resource_start(par->gpu, 0); | ||
351 | par->gpu_mem_size = pci_resource_len(par->gpu, 0); | ||
352 | if (!request_mem_region(par->gpu_mem_base, par->gpu_mem_size, "vmlfb")) { | ||
353 | printk(KERN_ERR MODULE_NAME ": Could not claim GPU MMIO.\n"); | ||
354 | err = -EBUSY; | ||
355 | goto out_err_1; | ||
356 | } | ||
357 | par->gpu_mem = ioremap_nocache(par->gpu_mem_base, par->gpu_mem_size); | ||
358 | if (par->gpu_mem == NULL) { | ||
359 | printk(KERN_ERR MODULE_NAME ": Could not map GPU MMIO.\n"); | ||
360 | err = -ENOMEM; | ||
361 | goto out_err_2; | ||
362 | } | ||
363 | |||
364 | return 0; | ||
365 | |||
366 | out_err_2: | ||
367 | release_mem_region(par->gpu_mem_base, par->gpu_mem_size); | ||
368 | out_err_1: | ||
369 | iounmap(par->vdc_mem); | ||
370 | out_err_0: | ||
371 | release_mem_region(par->vdc_mem_base, par->vdc_mem_size); | ||
372 | return err; | ||
373 | } | ||
374 | |||
375 | /* | ||
376 | * Unmap the VDC and GPU register spaces. | ||
377 | */ | ||
378 | |||
379 | static void vmlfb_disable_mmio(struct vml_par *par) | ||
380 | { | ||
381 | iounmap(par->gpu_mem); | ||
382 | release_mem_region(par->gpu_mem_base, par->gpu_mem_size); | ||
383 | iounmap(par->vdc_mem); | ||
384 | release_mem_region(par->vdc_mem_base, par->vdc_mem_size); | ||
385 | } | ||
386 | |||
387 | /* | ||
388 | * Release and uninit the VDC and GPU. | ||
389 | */ | ||
390 | |||
391 | static void vmlfb_release_devices(struct vml_par *par) | ||
392 | { | ||
393 | if (atomic_dec_and_test(&par->refcount)) { | ||
394 | pci_set_drvdata(par->vdc, NULL); | ||
395 | pci_disable_device(par->gpu); | ||
396 | pci_disable_device(par->vdc); | ||
397 | } | ||
398 | } | ||
399 | |||
400 | /* | ||
401 | * Free up allocated resources for a device. | ||
402 | */ | ||
403 | |||
404 | static void __devexit vml_pci_remove(struct pci_dev *dev) | ||
405 | { | ||
406 | struct fb_info *info; | ||
407 | struct vml_info *vinfo; | ||
408 | struct vml_par *par; | ||
409 | |||
410 | info = pci_get_drvdata(dev); | ||
411 | if (info) { | ||
412 | vinfo = container_of(info, struct vml_info, info); | ||
413 | par = vinfo->par; | ||
414 | mutex_lock(&vml_mutex); | ||
415 | unregister_framebuffer(info); | ||
416 | fb_dealloc_cmap(&info->cmap); | ||
417 | vmlfb_free_vram(vinfo); | ||
418 | vmlfb_disable_mmio(par); | ||
419 | vmlfb_release_devices(par); | ||
420 | kfree(vinfo); | ||
421 | kfree(par); | ||
422 | mutex_unlock(&vml_mutex); | ||
423 | } | ||
424 | } | ||
425 | |||
426 | static void vmlfb_set_pref_pixel_format(struct fb_var_screeninfo *var) | ||
427 | { | ||
428 | switch (var->bits_per_pixel) { | ||
429 | case 16: | ||
430 | var->blue.offset = 0; | ||
431 | var->blue.length = 5; | ||
432 | var->green.offset = 5; | ||
433 | var->green.length = 5; | ||
434 | var->red.offset = 10; | ||
435 | var->red.length = 5; | ||
436 | var->transp.offset = 15; | ||
437 | var->transp.length = 1; | ||
438 | break; | ||
439 | case 32: | ||
440 | var->blue.offset = 0; | ||
441 | var->blue.length = 8; | ||
442 | var->green.offset = 8; | ||
443 | var->green.length = 8; | ||
444 | var->red.offset = 16; | ||
445 | var->red.length = 8; | ||
446 | var->transp.offset = 24; | ||
447 | var->transp.length = 0; | ||
448 | break; | ||
449 | default: | ||
450 | break; | ||
451 | } | ||
452 | |||
453 | var->blue.msb_right = var->green.msb_right = | ||
454 | var->red.msb_right = var->transp.msb_right = 0; | ||
455 | } | ||
456 | |||
457 | /* | ||
458 | * Device initialization. | ||
459 | * We initialize one vml_par struct per device and one vml_info | ||
460 | * struct per pipe. Currently we have only one pipe. | ||
461 | */ | ||
462 | |||
463 | static int __devinit vml_pci_probe(struct pci_dev *dev, | ||
464 | const struct pci_device_id *id) | ||
465 | { | ||
466 | struct vml_info *vinfo; | ||
467 | struct fb_info *info; | ||
468 | struct vml_par *par; | ||
469 | int err = 0; | ||
470 | |||
471 | par = kzalloc(sizeof(*par), GFP_KERNEL); | ||
472 | if (par == NULL) | ||
473 | return -ENOMEM; | ||
474 | |||
475 | vinfo = kzalloc(sizeof(*vinfo), GFP_KERNEL); | ||
476 | if (vinfo == NULL) { | ||
477 | err = -ENOMEM; | ||
478 | goto out_err_0; | ||
479 | } | ||
480 | |||
481 | vinfo->par = par; | ||
482 | par->vdc = dev; | ||
483 | atomic_set(&par->refcount, 1); | ||
484 | |||
485 | switch (id->device) { | ||
486 | case VML_DEVICE_VDC: | ||
487 | if ((err = vmlfb_get_gpu(par))) | ||
488 | goto out_err_1; | ||
489 | pci_set_drvdata(dev, &vinfo->info); | ||
490 | break; | ||
491 | default: | ||
492 | err = -ENODEV; | ||
493 | goto out_err_1; | ||
494 | break; | ||
495 | } | ||
496 | |||
497 | info = &vinfo->info; | ||
498 | info->flags = FBINFO_DEFAULT | FBINFO_PARTIAL_PAN_OK; | ||
499 | |||
500 | err = vmlfb_enable_mmio(par); | ||
501 | if (err) | ||
502 | goto out_err_2; | ||
503 | |||
504 | err = vmlfb_alloc_vram(vinfo, vml_mem_requested, | ||
505 | vml_mem_contig, vml_mem_min); | ||
506 | if (err) | ||
507 | goto out_err_3; | ||
508 | |||
509 | strcpy(info->fix.id, "Vermilion Range"); | ||
510 | info->fix.mmio_start = 0; | ||
511 | info->fix.mmio_len = 0; | ||
512 | info->fix.smem_start = vinfo->vram_start; | ||
513 | info->fix.smem_len = vinfo->vram_contig_size; | ||
514 | info->fix.type = FB_TYPE_PACKED_PIXELS; | ||
515 | info->fix.visual = FB_VISUAL_TRUECOLOR; | ||
516 | info->fix.ypanstep = 1; | ||
517 | info->fix.xpanstep = 1; | ||
518 | info->fix.ywrapstep = 0; | ||
519 | info->fix.accel = FB_ACCEL_NONE; | ||
520 | info->screen_base = vinfo->vram_logical; | ||
521 | info->pseudo_palette = vinfo->pseudo_palette; | ||
522 | info->par = par; | ||
523 | info->fbops = &vmlfb_ops; | ||
524 | info->device = &dev->dev; | ||
525 | |||
526 | INIT_LIST_HEAD(&vinfo->head); | ||
527 | vinfo->pipe_disabled = 1; | ||
528 | vinfo->cur_blank_mode = FB_BLANK_UNBLANK; | ||
529 | |||
530 | info->var.grayscale = 0; | ||
531 | info->var.bits_per_pixel = 16; | ||
532 | vmlfb_set_pref_pixel_format(&info->var); | ||
533 | |||
534 | if (!fb_find_mode | ||
535 | (&info->var, info, vml_default_mode, NULL, 0, &defaultmode, 16)) { | ||
536 | printk(KERN_ERR MODULE_NAME ": Could not find initial mode\n"); | ||
537 | } | ||
538 | |||
539 | if (fb_alloc_cmap(&info->cmap, 256, 1) < 0) { | ||
540 | err = -ENOMEM; | ||
541 | goto out_err_4; | ||
542 | } | ||
543 | |||
544 | err = register_framebuffer(info); | ||
545 | if (err) { | ||
546 | printk(KERN_ERR MODULE_NAME ": Register framebuffer error.\n"); | ||
547 | goto out_err_5; | ||
548 | } | ||
549 | |||
550 | printk("Initialized vmlfb\n"); | ||
551 | |||
552 | return 0; | ||
553 | |||
554 | out_err_5: | ||
555 | fb_dealloc_cmap(&info->cmap); | ||
556 | out_err_4: | ||
557 | vmlfb_free_vram(vinfo); | ||
558 | out_err_3: | ||
559 | vmlfb_disable_mmio(par); | ||
560 | out_err_2: | ||
561 | vmlfb_release_devices(par); | ||
562 | out_err_1: | ||
563 | kfree(vinfo); | ||
564 | out_err_0: | ||
565 | kfree(par); | ||
566 | return err; | ||
567 | } | ||
568 | |||
569 | static int vmlfb_open(struct fb_info *info, int user) | ||
570 | { | ||
571 | /* | ||
572 | * Save registers here? | ||
573 | */ | ||
574 | return 0; | ||
575 | } | ||
576 | |||
577 | static int vmlfb_release(struct fb_info *info, int user) | ||
578 | { | ||
579 | /* | ||
580 | * Restore registers here. | ||
581 | */ | ||
582 | |||
583 | return 0; | ||
584 | } | ||
585 | |||
586 | static int vml_nearest_clock(int clock) | ||
587 | { | ||
588 | |||
589 | int i; | ||
590 | int cur_index; | ||
591 | int cur_diff; | ||
592 | int diff; | ||
593 | |||
594 | cur_index = 0; | ||
595 | cur_diff = clock - vml_clocks[0]; | ||
596 | cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff; | ||
597 | for (i = 1; i < vml_num_clocks; ++i) { | ||
598 | diff = clock - vml_clocks[i]; | ||
599 | diff = (diff < 0) ? -diff : diff; | ||
600 | if (diff < cur_diff) { | ||
601 | cur_index = i; | ||
602 | cur_diff = diff; | ||
603 | } | ||
604 | } | ||
605 | return vml_clocks[cur_index]; | ||
606 | } | ||
607 | |||
608 | static int vmlfb_check_var_locked(struct fb_var_screeninfo *var, | ||
609 | struct vml_info *vinfo) | ||
610 | { | ||
611 | u32 pitch; | ||
612 | u64 mem; | ||
613 | int nearest_clock; | ||
614 | int clock; | ||
615 | int clock_diff; | ||
616 | struct fb_var_screeninfo v; | ||
617 | |||
618 | v = *var; | ||
619 | clock = PICOS2KHZ(var->pixclock); | ||
620 | |||
621 | if (subsys && subsys->nearest_clock) { | ||
622 | nearest_clock = subsys->nearest_clock(subsys, clock); | ||
623 | } else { | ||
624 | nearest_clock = vml_nearest_clock(clock); | ||
625 | } | ||
626 | |||
627 | /* | ||
628 | * Accept a 20% diff. | ||
629 | */ | ||
630 | |||
631 | clock_diff = nearest_clock - clock; | ||
632 | clock_diff = (clock_diff < 0) ? -clock_diff : clock_diff; | ||
633 | if (clock_diff > clock / 5) { | ||
634 | #if 0 | ||
635 | printk(KERN_DEBUG MODULE_NAME ": Diff failure. %d %d\n",clock_diff,clock); | ||
636 | #endif | ||
637 | return -EINVAL; | ||
638 | } | ||
639 | |||
640 | v.pixclock = KHZ2PICOS(nearest_clock); | ||
641 | |||
642 | if (var->xres > VML_MAX_XRES || var->yres > VML_MAX_YRES) { | ||
643 | printk(KERN_DEBUG MODULE_NAME ": Resolution failure.\n"); | ||
644 | return -EINVAL; | ||
645 | } | ||
646 | if (var->xres_virtual > VML_MAX_XRES_VIRTUAL) { | ||
647 | printk(KERN_DEBUG MODULE_NAME | ||
648 | ": Virtual resolution failure.\n"); | ||
649 | return -EINVAL; | ||
650 | } | ||
651 | switch (v.bits_per_pixel) { | ||
652 | case 0 ... 16: | ||
653 | v.bits_per_pixel = 16; | ||
654 | break; | ||
655 | case 17 ... 32: | ||
656 | v.bits_per_pixel = 32; | ||
657 | break; | ||
658 | default: | ||
659 | printk(KERN_DEBUG MODULE_NAME ": Invalid bpp: %d.\n", | ||
660 | var->bits_per_pixel); | ||
661 | return -EINVAL; | ||
662 | } | ||
663 | |||
664 | pitch = __ALIGN_MASK((var->xres * var->bits_per_pixel) >> 3, 0x3F); | ||
665 | mem = pitch * var->yres_virtual; | ||
666 | if (mem > vinfo->vram_contig_size) { | ||
667 | return -ENOMEM; | ||
668 | } | ||
669 | |||
670 | switch (v.bits_per_pixel) { | ||
671 | case 16: | ||
672 | if (var->blue.offset != 0 || | ||
673 | var->blue.length != 5 || | ||
674 | var->green.offset != 5 || | ||
675 | var->green.length != 5 || | ||
676 | var->red.offset != 10 || | ||
677 | var->red.length != 5 || | ||
678 | var->transp.offset != 15 || var->transp.length != 1) { | ||
679 | vmlfb_set_pref_pixel_format(&v); | ||
680 | } | ||
681 | break; | ||
682 | case 32: | ||
683 | if (var->blue.offset != 0 || | ||
684 | var->blue.length != 8 || | ||
685 | var->green.offset != 8 || | ||
686 | var->green.length != 8 || | ||
687 | var->red.offset != 16 || | ||
688 | var->red.length != 8 || | ||
689 | (var->transp.length != 0 && var->transp.length != 8) || | ||
690 | (var->transp.length == 8 && var->transp.offset != 24)) { | ||
691 | vmlfb_set_pref_pixel_format(&v); | ||
692 | } | ||
693 | break; | ||
694 | default: | ||
695 | return -EINVAL; | ||
696 | } | ||
697 | |||
698 | *var = v; | ||
699 | |||
700 | return 0; | ||
701 | } | ||
702 | |||
703 | static int vmlfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | ||
704 | { | ||
705 | struct vml_info *vinfo = container_of(info, struct vml_info, info); | ||
706 | int ret; | ||
707 | |||
708 | mutex_lock(&vml_mutex); | ||
709 | ret = vmlfb_check_var_locked(var, vinfo); | ||
710 | mutex_unlock(&vml_mutex); | ||
711 | |||
712 | return ret; | ||
713 | } | ||
714 | |||
715 | static void vml_wait_vblank(struct vml_info *vinfo) | ||
716 | { | ||
717 | /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */ | ||
718 | mdelay(20); | ||
719 | } | ||
720 | |||
721 | static void vmlfb_disable_pipe(struct vml_info *vinfo) | ||
722 | { | ||
723 | struct vml_par *par = vinfo->par; | ||
724 | |||
725 | /* Disable the MDVO pad */ | ||
726 | VML_WRITE32(par, VML_RCOMPSTAT, 0); | ||
727 | while (!(VML_READ32(par, VML_RCOMPSTAT) & VML_MDVO_VDC_I_RCOMP)) ; | ||
728 | |||
729 | /* Disable display planes */ | ||
730 | VML_WRITE32(par, VML_DSPCCNTR, | ||
731 | VML_READ32(par, VML_DSPCCNTR) & ~VML_GFX_ENABLE); | ||
732 | (void)VML_READ32(par, VML_DSPCCNTR); | ||
733 | /* Wait for vblank for the disable to take effect */ | ||
734 | vml_wait_vblank(vinfo); | ||
735 | |||
736 | /* Next, disable display pipes */ | ||
737 | VML_WRITE32(par, VML_PIPEACONF, 0); | ||
738 | (void)VML_READ32(par, VML_PIPEACONF); | ||
739 | |||
740 | vinfo->pipe_disabled = 1; | ||
741 | } | ||
742 | |||
743 | #ifdef VERMILION_DEBUG | ||
744 | static void vml_dump_regs(struct vml_info *vinfo) | ||
745 | { | ||
746 | struct vml_par *par = vinfo->par; | ||
747 | |||
748 | printk(KERN_DEBUG MODULE_NAME ": Modesetting register dump:\n"); | ||
749 | printk(KERN_DEBUG MODULE_NAME ": \tHTOTAL_A : 0x%08x\n", | ||
750 | (unsigned)VML_READ32(par, VML_HTOTAL_A)); | ||
751 | printk(KERN_DEBUG MODULE_NAME ": \tHBLANK_A : 0x%08x\n", | ||
752 | (unsigned)VML_READ32(par, VML_HBLANK_A)); | ||
753 | printk(KERN_DEBUG MODULE_NAME ": \tHSYNC_A : 0x%08x\n", | ||
754 | (unsigned)VML_READ32(par, VML_HSYNC_A)); | ||
755 | printk(KERN_DEBUG MODULE_NAME ": \tVTOTAL_A : 0x%08x\n", | ||
756 | (unsigned)VML_READ32(par, VML_VTOTAL_A)); | ||
757 | printk(KERN_DEBUG MODULE_NAME ": \tVBLANK_A : 0x%08x\n", | ||
758 | (unsigned)VML_READ32(par, VML_VBLANK_A)); | ||
759 | printk(KERN_DEBUG MODULE_NAME ": \tVSYNC_A : 0x%08x\n", | ||
760 | (unsigned)VML_READ32(par, VML_VSYNC_A)); | ||
761 | printk(KERN_DEBUG MODULE_NAME ": \tDSPCSTRIDE : 0x%08x\n", | ||
762 | (unsigned)VML_READ32(par, VML_DSPCSTRIDE)); | ||
763 | printk(KERN_DEBUG MODULE_NAME ": \tDSPCSIZE : 0x%08x\n", | ||
764 | (unsigned)VML_READ32(par, VML_DSPCSIZE)); | ||
765 | printk(KERN_DEBUG MODULE_NAME ": \tDSPCPOS : 0x%08x\n", | ||
766 | (unsigned)VML_READ32(par, VML_DSPCPOS)); | ||
767 | printk(KERN_DEBUG MODULE_NAME ": \tDSPARB : 0x%08x\n", | ||
768 | (unsigned)VML_READ32(par, VML_DSPARB)); | ||
769 | printk(KERN_DEBUG MODULE_NAME ": \tDSPCADDR : 0x%08x\n", | ||
770 | (unsigned)VML_READ32(par, VML_DSPCADDR)); | ||
771 | printk(KERN_DEBUG MODULE_NAME ": \tBCLRPAT_A : 0x%08x\n", | ||
772 | (unsigned)VML_READ32(par, VML_BCLRPAT_A)); | ||
773 | printk(KERN_DEBUG MODULE_NAME ": \tCANVSCLR_A : 0x%08x\n", | ||
774 | (unsigned)VML_READ32(par, VML_CANVSCLR_A)); | ||
775 | printk(KERN_DEBUG MODULE_NAME ": \tPIPEASRC : 0x%08x\n", | ||
776 | (unsigned)VML_READ32(par, VML_PIPEASRC)); | ||
777 | printk(KERN_DEBUG MODULE_NAME ": \tPIPEACONF : 0x%08x\n", | ||
778 | (unsigned)VML_READ32(par, VML_PIPEACONF)); | ||
779 | printk(KERN_DEBUG MODULE_NAME ": \tDSPCCNTR : 0x%08x\n", | ||
780 | (unsigned)VML_READ32(par, VML_DSPCCNTR)); | ||
781 | printk(KERN_DEBUG MODULE_NAME ": \tRCOMPSTAT : 0x%08x\n", | ||
782 | (unsigned)VML_READ32(par, VML_RCOMPSTAT)); | ||
783 | printk(KERN_DEBUG MODULE_NAME ": End of modesetting register dump.\n"); | ||
784 | } | ||
785 | #endif | ||
786 | |||
787 | static int vmlfb_set_par_locked(struct vml_info *vinfo) | ||
788 | { | ||
789 | struct vml_par *par = vinfo->par; | ||
790 | struct fb_info *info = &vinfo->info; | ||
791 | struct fb_var_screeninfo *var = &info->var; | ||
792 | u32 htotal, hactive, hblank_start, hblank_end, hsync_start, hsync_end; | ||
793 | u32 vtotal, vactive, vblank_start, vblank_end, vsync_start, vsync_end; | ||
794 | u32 dspcntr; | ||
795 | int clock; | ||
796 | |||
797 | vinfo->bytes_per_pixel = var->bits_per_pixel >> 3; | ||
798 | vinfo->stride = | ||
799 | __ALIGN_MASK(var->xres_virtual * vinfo->bytes_per_pixel, 0x3F); | ||
800 | info->fix.line_length = vinfo->stride; | ||
801 | |||
802 | if (!subsys) | ||
803 | return 0; | ||
804 | |||
805 | htotal = | ||
806 | var->xres + var->right_margin + var->hsync_len + var->left_margin; | ||
807 | hactive = var->xres; | ||
808 | hblank_start = var->xres; | ||
809 | hblank_end = htotal; | ||
810 | hsync_start = hactive + var->right_margin; | ||
811 | hsync_end = hsync_start + var->hsync_len; | ||
812 | |||
813 | vtotal = | ||
814 | var->yres + var->lower_margin + var->vsync_len + var->upper_margin; | ||
815 | vactive = var->yres; | ||
816 | vblank_start = var->yres; | ||
817 | vblank_end = vtotal; | ||
818 | vsync_start = vactive + var->lower_margin; | ||
819 | vsync_end = vsync_start + var->vsync_len; | ||
820 | |||
821 | dspcntr = VML_GFX_ENABLE | VML_GFX_GAMMABYPASS; | ||
822 | clock = PICOS2KHZ(var->pixclock); | ||
823 | |||
824 | if (subsys->nearest_clock) { | ||
825 | clock = subsys->nearest_clock(subsys, clock); | ||
826 | } else { | ||
827 | clock = vml_nearest_clock(clock); | ||
828 | } | ||
829 | printk(KERN_DEBUG MODULE_NAME | ||
830 | ": Set mode Hfreq : %d kHz, Vfreq : %d Hz.\n", clock / htotal, | ||
831 | ((clock / htotal) * 1000) / vtotal); | ||
832 | |||
833 | switch (var->bits_per_pixel) { | ||
834 | case 16: | ||
835 | dspcntr |= VML_GFX_ARGB1555; | ||
836 | break; | ||
837 | case 32: | ||
838 | if (var->transp.length == 8) | ||
839 | dspcntr |= VML_GFX_ARGB8888 | VML_GFX_ALPHAMULT; | ||
840 | else | ||
841 | dspcntr |= VML_GFX_RGB0888; | ||
842 | break; | ||
843 | default: | ||
844 | return -EINVAL; | ||
845 | } | ||
846 | |||
847 | vmlfb_disable_pipe(vinfo); | ||
848 | mb(); | ||
849 | |||
850 | if (subsys->set_clock) | ||
851 | subsys->set_clock(subsys, clock); | ||
852 | else | ||
853 | return -EINVAL; | ||
854 | |||
855 | VML_WRITE32(par, VML_HTOTAL_A, ((htotal - 1) << 16) | (hactive - 1)); | ||
856 | VML_WRITE32(par, VML_HBLANK_A, | ||
857 | ((hblank_end - 1) << 16) | (hblank_start - 1)); | ||
858 | VML_WRITE32(par, VML_HSYNC_A, | ||
859 | ((hsync_end - 1) << 16) | (hsync_start - 1)); | ||
860 | VML_WRITE32(par, VML_VTOTAL_A, ((vtotal - 1) << 16) | (vactive - 1)); | ||
861 | VML_WRITE32(par, VML_VBLANK_A, | ||
862 | ((vblank_end - 1) << 16) | (vblank_start - 1)); | ||
863 | VML_WRITE32(par, VML_VSYNC_A, | ||
864 | ((vsync_end - 1) << 16) | (vsync_start - 1)); | ||
865 | VML_WRITE32(par, VML_DSPCSTRIDE, vinfo->stride); | ||
866 | VML_WRITE32(par, VML_DSPCSIZE, | ||
867 | ((var->yres - 1) << 16) | (var->xres - 1)); | ||
868 | VML_WRITE32(par, VML_DSPCPOS, 0x00000000); | ||
869 | VML_WRITE32(par, VML_DSPARB, VML_FIFO_DEFAULT); | ||
870 | VML_WRITE32(par, VML_BCLRPAT_A, 0x00000000); | ||
871 | VML_WRITE32(par, VML_CANVSCLR_A, 0x00000000); | ||
872 | VML_WRITE32(par, VML_PIPEASRC, | ||
873 | ((var->xres - 1) << 16) | (var->yres - 1)); | ||
874 | |||
875 | wmb(); | ||
876 | VML_WRITE32(par, VML_PIPEACONF, VML_PIPE_ENABLE); | ||
877 | wmb(); | ||
878 | VML_WRITE32(par, VML_DSPCCNTR, dspcntr); | ||
879 | wmb(); | ||
880 | VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start + | ||
881 | var->yoffset * vinfo->stride + | ||
882 | var->xoffset * vinfo->bytes_per_pixel); | ||
883 | |||
884 | VML_WRITE32(par, VML_RCOMPSTAT, VML_MDVO_PAD_ENABLE); | ||
885 | |||
886 | while (!(VML_READ32(par, VML_RCOMPSTAT) & | ||
887 | (VML_MDVO_VDC_I_RCOMP | VML_MDVO_PAD_ENABLE))) ; | ||
888 | |||
889 | vinfo->pipe_disabled = 0; | ||
890 | #ifdef VERMILION_DEBUG | ||
891 | vml_dump_regs(vinfo); | ||
892 | #endif | ||
893 | |||
894 | return 0; | ||
895 | } | ||
896 | |||
897 | static int vmlfb_set_par(struct fb_info *info) | ||
898 | { | ||
899 | struct vml_info *vinfo = container_of(info, struct vml_info, info); | ||
900 | int ret; | ||
901 | |||
902 | mutex_lock(&vml_mutex); | ||
903 | list_del(&vinfo->head); | ||
904 | list_add(&vinfo->head, (subsys) ? &global_has_mode : &global_no_mode); | ||
905 | ret = vmlfb_set_par_locked(vinfo); | ||
906 | |||
907 | mutex_unlock(&vml_mutex); | ||
908 | return ret; | ||
909 | } | ||
910 | |||
911 | static int vmlfb_blank_locked(struct vml_info *vinfo) | ||
912 | { | ||
913 | struct vml_par *par = vinfo->par; | ||
914 | u32 cur = VML_READ32(par, VML_PIPEACONF); | ||
915 | |||
916 | switch (vinfo->cur_blank_mode) { | ||
917 | case FB_BLANK_UNBLANK: | ||
918 | if (vinfo->pipe_disabled) { | ||
919 | vmlfb_set_par_locked(vinfo); | ||
920 | } | ||
921 | VML_WRITE32(par, VML_PIPEACONF, cur & ~VML_PIPE_FORCE_BORDER); | ||
922 | (void)VML_READ32(par, VML_PIPEACONF); | ||
923 | break; | ||
924 | case FB_BLANK_NORMAL: | ||
925 | if (vinfo->pipe_disabled) { | ||
926 | vmlfb_set_par_locked(vinfo); | ||
927 | } | ||
928 | VML_WRITE32(par, VML_PIPEACONF, cur | VML_PIPE_FORCE_BORDER); | ||
929 | (void)VML_READ32(par, VML_PIPEACONF); | ||
930 | break; | ||
931 | case FB_BLANK_VSYNC_SUSPEND: | ||
932 | case FB_BLANK_HSYNC_SUSPEND: | ||
933 | if (!vinfo->pipe_disabled) { | ||
934 | vmlfb_disable_pipe(vinfo); | ||
935 | } | ||
936 | break; | ||
937 | case FB_BLANK_POWERDOWN: | ||
938 | if (!vinfo->pipe_disabled) { | ||
939 | vmlfb_disable_pipe(vinfo); | ||
940 | } | ||
941 | break; | ||
942 | default: | ||
943 | return -EINVAL; | ||
944 | } | ||
945 | |||
946 | return 0; | ||
947 | } | ||
948 | |||
949 | static int vmlfb_blank(int blank_mode, struct fb_info *info) | ||
950 | { | ||
951 | struct vml_info *vinfo = container_of(info, struct vml_info, info); | ||
952 | int ret; | ||
953 | |||
954 | mutex_lock(&vml_mutex); | ||
955 | vinfo->cur_blank_mode = blank_mode; | ||
956 | ret = vmlfb_blank_locked(vinfo); | ||
957 | mutex_unlock(&vml_mutex); | ||
958 | return ret; | ||
959 | } | ||
960 | |||
961 | static int vmlfb_pan_display(struct fb_var_screeninfo *var, | ||
962 | struct fb_info *info) | ||
963 | { | ||
964 | struct vml_info *vinfo = container_of(info, struct vml_info, info); | ||
965 | struct vml_par *par = vinfo->par; | ||
966 | |||
967 | mutex_lock(&vml_mutex); | ||
968 | VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start + | ||
969 | var->yoffset * vinfo->stride + | ||
970 | var->xoffset * vinfo->bytes_per_pixel); | ||
971 | (void)VML_READ32(par, VML_DSPCADDR); | ||
972 | mutex_unlock(&vml_mutex); | ||
973 | |||
974 | return 0; | ||
975 | } | ||
976 | |||
977 | static int vmlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | ||
978 | u_int transp, struct fb_info *info) | ||
979 | { | ||
980 | u32 v; | ||
981 | |||
982 | if (regno >= 16) | ||
983 | return -EINVAL; | ||
984 | |||
985 | if (info->var.grayscale) { | ||
986 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; | ||
987 | } | ||
988 | |||
989 | if (info->fix.visual != FB_VISUAL_TRUECOLOR) | ||
990 | return -EINVAL; | ||
991 | |||
992 | red = VML_TOHW(red, info->var.red.length); | ||
993 | blue = VML_TOHW(blue, info->var.blue.length); | ||
994 | green = VML_TOHW(green, info->var.green.length); | ||
995 | transp = VML_TOHW(transp, info->var.transp.length); | ||
996 | |||
997 | v = (red << info->var.red.offset) | | ||
998 | (green << info->var.green.offset) | | ||
999 | (blue << info->var.blue.offset) | | ||
1000 | (transp << info->var.transp.offset); | ||
1001 | |||
1002 | switch (info->var.bits_per_pixel) { | ||
1003 | case 16: | ||
1004 | ((u32 *) info->pseudo_palette)[regno] = v; | ||
1005 | break; | ||
1006 | case 24: | ||
1007 | case 32: | ||
1008 | ((u32 *) info->pseudo_palette)[regno] = v; | ||
1009 | break; | ||
1010 | } | ||
1011 | return 0; | ||
1012 | } | ||
1013 | |||
1014 | static int vmlfb_mmap(struct fb_info *info, struct vm_area_struct *vma) | ||
1015 | { | ||
1016 | struct vml_info *vinfo = container_of(info, struct vml_info, info); | ||
1017 | unsigned long size = vma->vm_end - vma->vm_start; | ||
1018 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; | ||
1019 | int ret; | ||
1020 | |||
1021 | if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) | ||
1022 | return -EINVAL; | ||
1023 | if (offset + size > vinfo->vram_contig_size) | ||
1024 | return -EINVAL; | ||
1025 | ret = vmlfb_vram_offset(vinfo, offset); | ||
1026 | if (ret) | ||
1027 | return -EINVAL; | ||
1028 | offset += vinfo->vram_start; | ||
1029 | pgprot_val(vma->vm_page_prot) |= _PAGE_PCD; | ||
1030 | pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT; | ||
1031 | vma->vm_flags |= VM_RESERVED | VM_IO; | ||
1032 | if (remap_pfn_range(vma, vma->vm_start, offset >> PAGE_SHIFT, | ||
1033 | size, vma->vm_page_prot)) | ||
1034 | return -EAGAIN; | ||
1035 | return 0; | ||
1036 | } | ||
1037 | |||
1038 | static int vmlfb_sync(struct fb_info *info) | ||
1039 | { | ||
1040 | return 0; | ||
1041 | } | ||
1042 | |||
1043 | static int vmlfb_cursor(struct fb_info *info, struct fb_cursor *cursor) | ||
1044 | { | ||
1045 | return -EINVAL; /* just to force soft_cursor() call */ | ||
1046 | } | ||
1047 | |||
1048 | static struct fb_ops vmlfb_ops = { | ||
1049 | .owner = THIS_MODULE, | ||
1050 | .fb_open = vmlfb_open, | ||
1051 | .fb_release = vmlfb_release, | ||
1052 | .fb_check_var = vmlfb_check_var, | ||
1053 | .fb_set_par = vmlfb_set_par, | ||
1054 | .fb_blank = vmlfb_blank, | ||
1055 | .fb_pan_display = vmlfb_pan_display, | ||
1056 | .fb_fillrect = cfb_fillrect, | ||
1057 | .fb_copyarea = cfb_copyarea, | ||
1058 | .fb_imageblit = cfb_imageblit, | ||
1059 | .fb_cursor = vmlfb_cursor, | ||
1060 | .fb_sync = vmlfb_sync, | ||
1061 | .fb_mmap = vmlfb_mmap, | ||
1062 | .fb_setcolreg = vmlfb_setcolreg | ||
1063 | }; | ||
1064 | |||
1065 | static struct pci_device_id vml_ids[] = { | ||
1066 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, VML_DEVICE_VDC)}, | ||
1067 | {0} | ||
1068 | }; | ||
1069 | |||
1070 | static struct pci_driver vmlfb_pci_driver = { | ||
1071 | .name = "vmlfb", | ||
1072 | .id_table = vml_ids, | ||
1073 | .probe = vml_pci_probe, | ||
1074 | .remove = __devexit_p(vml_pci_remove) | ||
1075 | }; | ||
1076 | |||
1077 | static void __exit vmlfb_cleanup(void) | ||
1078 | { | ||
1079 | pci_unregister_driver(&vmlfb_pci_driver); | ||
1080 | } | ||
1081 | |||
1082 | static int __init vmlfb_init(void) | ||
1083 | { | ||
1084 | |||
1085 | #ifndef MODULE | ||
1086 | char *option = NULL; | ||
1087 | |||
1088 | if (fb_get_options(MODULE_NAME, &option)) | ||
1089 | return -ENODEV; | ||
1090 | #endif | ||
1091 | |||
1092 | printk(KERN_DEBUG MODULE_NAME ": initializing\n"); | ||
1093 | mutex_init(&vml_mutex); | ||
1094 | INIT_LIST_HEAD(&global_no_mode); | ||
1095 | INIT_LIST_HEAD(&global_has_mode); | ||
1096 | |||
1097 | return pci_register_driver(&vmlfb_pci_driver); | ||
1098 | } | ||
1099 | |||
1100 | int vmlfb_register_subsys(struct vml_sys *sys) | ||
1101 | { | ||
1102 | struct vml_info *entry; | ||
1103 | struct list_head *list; | ||
1104 | u32 save_activate; | ||
1105 | |||
1106 | mutex_lock(&vml_mutex); | ||
1107 | if (subsys != NULL) { | ||
1108 | subsys->restore(subsys); | ||
1109 | } | ||
1110 | subsys = sys; | ||
1111 | subsys->save(subsys); | ||
1112 | |||
1113 | /* | ||
1114 | * We need to restart list traversal for each item, since we | ||
1115 | * release the list mutex in the loop. | ||
1116 | */ | ||
1117 | |||
1118 | list = global_no_mode.next; | ||
1119 | while (list != &global_no_mode) { | ||
1120 | list_del_init(list); | ||
1121 | entry = list_entry(list, struct vml_info, head); | ||
1122 | |||
1123 | /* | ||
1124 | * First, try the current mode which might not be | ||
1125 | * completely validated with respect to the pixel clock. | ||
1126 | */ | ||
1127 | |||
1128 | if (!vmlfb_check_var_locked(&entry->info.var, entry)) { | ||
1129 | vmlfb_set_par_locked(entry); | ||
1130 | list_add_tail(list, &global_has_mode); | ||
1131 | } else { | ||
1132 | |||
1133 | /* | ||
1134 | * Didn't work. Try to find another mode, | ||
1135 | * that matches this subsys. | ||
1136 | */ | ||
1137 | |||
1138 | mutex_unlock(&vml_mutex); | ||
1139 | save_activate = entry->info.var.activate; | ||
1140 | entry->info.var.bits_per_pixel = 16; | ||
1141 | vmlfb_set_pref_pixel_format(&entry->info.var); | ||
1142 | if (fb_find_mode(&entry->info.var, | ||
1143 | &entry->info, | ||
1144 | vml_default_mode, NULL, 0, NULL, 16)) { | ||
1145 | entry->info.var.activate |= | ||
1146 | FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW; | ||
1147 | fb_set_var(&entry->info, &entry->info.var); | ||
1148 | } else { | ||
1149 | printk(KERN_ERR MODULE_NAME | ||
1150 | ": Sorry. no mode found for this subsys.\n"); | ||
1151 | } | ||
1152 | entry->info.var.activate = save_activate; | ||
1153 | mutex_lock(&vml_mutex); | ||
1154 | } | ||
1155 | vmlfb_blank_locked(entry); | ||
1156 | list = global_no_mode.next; | ||
1157 | } | ||
1158 | mutex_unlock(&vml_mutex); | ||
1159 | |||
1160 | printk(KERN_DEBUG MODULE_NAME ": Registered %s subsystem.\n", | ||
1161 | subsys->name ? subsys->name : "unknown"); | ||
1162 | return 0; | ||
1163 | } | ||
1164 | |||
1165 | EXPORT_SYMBOL_GPL(vmlfb_register_subsys); | ||
1166 | |||
1167 | void vmlfb_unregister_subsys(struct vml_sys *sys) | ||
1168 | { | ||
1169 | struct vml_info *entry, *next; | ||
1170 | |||
1171 | mutex_lock(&vml_mutex); | ||
1172 | if (subsys != sys) { | ||
1173 | mutex_unlock(&vml_mutex); | ||
1174 | return; | ||
1175 | } | ||
1176 | subsys->restore(subsys); | ||
1177 | subsys = NULL; | ||
1178 | list_for_each_entry_safe(entry, next, &global_has_mode, head) { | ||
1179 | printk(KERN_DEBUG MODULE_NAME ": subsys disable pipe\n"); | ||
1180 | vmlfb_disable_pipe(entry); | ||
1181 | list_del(&entry->head); | ||
1182 | list_add_tail(&entry->head, &global_no_mode); | ||
1183 | } | ||
1184 | mutex_unlock(&vml_mutex); | ||
1185 | } | ||
1186 | |||
1187 | EXPORT_SYMBOL_GPL(vmlfb_unregister_subsys); | ||
1188 | |||
1189 | module_init(vmlfb_init); | ||
1190 | module_exit(vmlfb_cleanup); | ||
1191 | |||
1192 | MODULE_AUTHOR("Tungsten Graphics"); | ||
1193 | MODULE_DESCRIPTION("Initialization of the Vermilion display devices"); | ||
1194 | MODULE_VERSION("1.0.0"); | ||
1195 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/vermilion/vermilion.h b/drivers/video/vermilion/vermilion.h new file mode 100644 index 00000000000..1fc6695a49d --- /dev/null +++ b/drivers/video/vermilion/vermilion.h | |||
@@ -0,0 +1,260 @@ | |||
1 | /* | ||
2 | * Copyright (c) Intel Corp. 2007. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
6 | * develop this driver. | ||
7 | * | ||
8 | * This file is part of the Vermilion Range fb driver. | ||
9 | * The Vermilion Range fb driver is free software; | ||
10 | * you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * The Vermilion Range fb driver is distributed | ||
16 | * in the hope that it will be useful, | ||
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
19 | * GNU General Public License for more details. | ||
20 | * | ||
21 | * You should have received a copy of the GNU General Public License | ||
22 | * along with this driver; if not, write to the Free Software | ||
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
24 | * | ||
25 | * Authors: | ||
26 | * Thomas Hellstr�m <thomas-at-tungstengraphics-dot-com> | ||
27 | */ | ||
28 | |||
29 | #ifndef _VERMILION_H_ | ||
30 | #define _VERMILION_H_ | ||
31 | |||
32 | #include <linux/kernel.h> | ||
33 | #include <linux/version.h> | ||
34 | #include <linux/pci.h> | ||
35 | #include <asm/atomic.h> | ||
36 | #include <linux/mutex.h> | ||
37 | |||
38 | #define VML_DEVICE_GPU 0x5002 | ||
39 | #define VML_DEVICE_VDC 0x5009 | ||
40 | |||
41 | #define VML_VRAM_AREAS 3 | ||
42 | #define VML_MAX_XRES 1024 | ||
43 | #define VML_MAX_YRES 768 | ||
44 | #define VML_MAX_XRES_VIRTUAL 1040 | ||
45 | |||
46 | /* | ||
47 | * Display controller registers: | ||
48 | */ | ||
49 | |||
50 | /* Display controller 10-bit color representation */ | ||
51 | |||
52 | #define VML_R_MASK 0x3FF00000 | ||
53 | #define VML_R_SHIFT 20 | ||
54 | #define VML_G_MASK 0x000FFC00 | ||
55 | #define VML_G_SHIFT 10 | ||
56 | #define VML_B_MASK 0x000003FF | ||
57 | #define VML_B_SHIFT 0 | ||
58 | |||
59 | /* Graphics plane control */ | ||
60 | #define VML_DSPCCNTR 0x00072180 | ||
61 | #define VML_GFX_ENABLE 0x80000000 | ||
62 | #define VML_GFX_GAMMABYPASS 0x40000000 | ||
63 | #define VML_GFX_ARGB1555 0x0C000000 | ||
64 | #define VML_GFX_RGB0888 0x18000000 | ||
65 | #define VML_GFX_ARGB8888 0x1C000000 | ||
66 | #define VML_GFX_ALPHACONST 0x02000000 | ||
67 | #define VML_GFX_ALPHAMULT 0x01000000 | ||
68 | #define VML_GFX_CONST_ALPHA 0x000000FF | ||
69 | |||
70 | /* Graphics plane start address. Pixel aligned. */ | ||
71 | #define VML_DSPCADDR 0x00072184 | ||
72 | |||
73 | /* Graphics plane stride register. */ | ||
74 | #define VML_DSPCSTRIDE 0x00072188 | ||
75 | |||
76 | /* Graphics plane position register. */ | ||
77 | #define VML_DSPCPOS 0x0007218C | ||
78 | #define VML_POS_YMASK 0x0FFF0000 | ||
79 | #define VML_POS_YSHIFT 16 | ||
80 | #define VML_POS_XMASK 0x00000FFF | ||
81 | #define VML_POS_XSHIFT 0 | ||
82 | |||
83 | /* Graphics plane height and width */ | ||
84 | #define VML_DSPCSIZE 0x00072190 | ||
85 | #define VML_SIZE_HMASK 0x0FFF0000 | ||
86 | #define VML_SIZE_HSHIFT 16 | ||
87 | #define VML_SISE_WMASK 0x00000FFF | ||
88 | #define VML_SIZE_WSHIFT 0 | ||
89 | |||
90 | /* Graphics plane gamma correction lookup table registers (129 * 32 bits) */ | ||
91 | #define VML_DSPCGAMLUT 0x00072200 | ||
92 | |||
93 | /* Pixel video output configuration register */ | ||
94 | #define VML_PVOCONFIG 0x00061140 | ||
95 | #define VML_CONFIG_BASE 0x80000000 | ||
96 | #define VML_CONFIG_PIXEL_SWAP 0x04000000 | ||
97 | #define VML_CONFIG_DE_INV 0x01000000 | ||
98 | #define VML_CONFIG_HREF_INV 0x00400000 | ||
99 | #define VML_CONFIG_VREF_INV 0x00100000 | ||
100 | #define VML_CONFIG_CLK_INV 0x00040000 | ||
101 | #define VML_CONFIG_CLK_DIV2 0x00010000 | ||
102 | #define VML_CONFIG_ESTRB_INV 0x00008000 | ||
103 | |||
104 | /* Pipe A Horizontal total register */ | ||
105 | #define VML_HTOTAL_A 0x00060000 | ||
106 | #define VML_HTOTAL_MASK 0x1FFF0000 | ||
107 | #define VML_HTOTAL_SHIFT 16 | ||
108 | #define VML_HTOTAL_VAL 8192 | ||
109 | #define VML_HACTIVE_MASK 0x000007FF | ||
110 | #define VML_HACTIVE_SHIFT 0 | ||
111 | #define VML_HACTIVE_VAL 4096 | ||
112 | |||
113 | /* Pipe A Horizontal Blank register */ | ||
114 | #define VML_HBLANK_A 0x00060004 | ||
115 | #define VML_HBLANK_END_MASK 0x1FFF0000 | ||
116 | #define VML_HBLANK_END_SHIFT 16 | ||
117 | #define VML_HBLANK_END_VAL 8192 | ||
118 | #define VML_HBLANK_START_MASK 0x00001FFF | ||
119 | #define VML_HBLANK_START_SHIFT 0 | ||
120 | #define VML_HBLANK_START_VAL 8192 | ||
121 | |||
122 | /* Pipe A Horizontal Sync register */ | ||
123 | #define VML_HSYNC_A 0x00060008 | ||
124 | #define VML_HSYNC_END_MASK 0x1FFF0000 | ||
125 | #define VML_HSYNC_END_SHIFT 16 | ||
126 | #define VML_HSYNC_END_VAL 8192 | ||
127 | #define VML_HSYNC_START_MASK 0x00001FFF | ||
128 | #define VML_HSYNC_START_SHIFT 0 | ||
129 | #define VML_HSYNC_START_VAL 8192 | ||
130 | |||
131 | /* Pipe A Vertical total register */ | ||
132 | #define VML_VTOTAL_A 0x0006000C | ||
133 | #define VML_VTOTAL_MASK 0x1FFF0000 | ||
134 | #define VML_VTOTAL_SHIFT 16 | ||
135 | #define VML_VTOTAL_VAL 8192 | ||
136 | #define VML_VACTIVE_MASK 0x000007FF | ||
137 | #define VML_VACTIVE_SHIFT 0 | ||
138 | #define VML_VACTIVE_VAL 4096 | ||
139 | |||
140 | /* Pipe A Vertical Blank register */ | ||
141 | #define VML_VBLANK_A 0x00060010 | ||
142 | #define VML_VBLANK_END_MASK 0x1FFF0000 | ||
143 | #define VML_VBLANK_END_SHIFT 16 | ||
144 | #define VML_VBLANK_END_VAL 8192 | ||
145 | #define VML_VBLANK_START_MASK 0x00001FFF | ||
146 | #define VML_VBLANK_START_SHIFT 0 | ||
147 | #define VML_VBLANK_START_VAL 8192 | ||
148 | |||
149 | /* Pipe A Vertical Sync register */ | ||
150 | #define VML_VSYNC_A 0x00060014 | ||
151 | #define VML_VSYNC_END_MASK 0x1FFF0000 | ||
152 | #define VML_VSYNC_END_SHIFT 16 | ||
153 | #define VML_VSYNC_END_VAL 8192 | ||
154 | #define VML_VSYNC_START_MASK 0x00001FFF | ||
155 | #define VML_VSYNC_START_SHIFT 0 | ||
156 | #define VML_VSYNC_START_VAL 8192 | ||
157 | |||
158 | /* Pipe A Source Image size (minus one - equal to active size) | ||
159 | * Programmable while pipe is enabled. | ||
160 | */ | ||
161 | #define VML_PIPEASRC 0x0006001C | ||
162 | #define VML_PIPEASRC_HMASK 0x0FFF0000 | ||
163 | #define VML_PIPEASRC_HSHIFT 16 | ||
164 | #define VML_PIPEASRC_VMASK 0x00000FFF | ||
165 | #define VML_PIPEASRC_VSHIFT 0 | ||
166 | |||
167 | /* Pipe A Border Color Pattern register (10 bit color) */ | ||
168 | #define VML_BCLRPAT_A 0x00060020 | ||
169 | |||
170 | /* Pipe A Canvas Color register (10 bit color) */ | ||
171 | #define VML_CANVSCLR_A 0x00060024 | ||
172 | |||
173 | /* Pipe A Configuration register */ | ||
174 | #define VML_PIPEACONF 0x00070008 | ||
175 | #define VML_PIPE_BASE 0x00000000 | ||
176 | #define VML_PIPE_ENABLE 0x80000000 | ||
177 | #define VML_PIPE_FORCE_BORDER 0x02000000 | ||
178 | #define VML_PIPE_PLANES_OFF 0x00080000 | ||
179 | #define VML_PIPE_ARGB_OUTPUT_MODE 0x00040000 | ||
180 | |||
181 | /* Pipe A FIFO setting */ | ||
182 | #define VML_DSPARB 0x00070030 | ||
183 | #define VML_FIFO_DEFAULT 0x00001D9C | ||
184 | |||
185 | /* MDVO rcomp status & pads control register */ | ||
186 | #define VML_RCOMPSTAT 0x00070048 | ||
187 | #define VML_MDVO_VDC_I_RCOMP 0x80000000 | ||
188 | #define VML_MDVO_POWERSAVE_OFF 0x00000008 | ||
189 | #define VML_MDVO_PAD_ENABLE 0x00000004 | ||
190 | #define VML_MDVO_PULLDOWN_ENABLE 0x00000001 | ||
191 | |||
192 | struct vml_par { | ||
193 | struct pci_dev *vdc; | ||
194 | u64 vdc_mem_base; | ||
195 | u64 vdc_mem_size; | ||
196 | char __iomem *vdc_mem; | ||
197 | |||
198 | struct pci_dev *gpu; | ||
199 | u64 gpu_mem_base; | ||
200 | u64 gpu_mem_size; | ||
201 | char __iomem *gpu_mem; | ||
202 | |||
203 | atomic_t refcount; | ||
204 | }; | ||
205 | |||
206 | struct vram_area { | ||
207 | unsigned long logical; | ||
208 | unsigned long phys; | ||
209 | unsigned long size; | ||
210 | unsigned order; | ||
211 | }; | ||
212 | |||
213 | struct vml_info { | ||
214 | struct fb_info info; | ||
215 | struct vml_par *par; | ||
216 | struct list_head head; | ||
217 | struct vram_area vram[VML_VRAM_AREAS]; | ||
218 | u64 vram_start; | ||
219 | u64 vram_contig_size; | ||
220 | u32 num_areas; | ||
221 | void __iomem *vram_logical; | ||
222 | u32 pseudo_palette[16]; | ||
223 | u32 stride; | ||
224 | u32 bytes_per_pixel; | ||
225 | atomic_t vmas; | ||
226 | int cur_blank_mode; | ||
227 | int pipe_disabled; | ||
228 | }; | ||
229 | |||
230 | /* | ||
231 | * Subsystem | ||
232 | */ | ||
233 | |||
234 | struct vml_sys { | ||
235 | char *name; | ||
236 | |||
237 | /* | ||
238 | * Save / Restore; | ||
239 | */ | ||
240 | |||
241 | int (*save) (struct vml_sys * sys); | ||
242 | int (*restore) (struct vml_sys * sys); | ||
243 | |||
244 | /* | ||
245 | * PLL programming; | ||
246 | */ | ||
247 | |||
248 | int (*set_clock) (struct vml_sys * sys, int clock); | ||
249 | int (*nearest_clock) (const struct vml_sys * sys, int clock); | ||
250 | }; | ||
251 | |||
252 | extern int vmlfb_register_subsys(struct vml_sys *sys); | ||
253 | extern void vmlfb_unregister_subsys(struct vml_sys *sys); | ||
254 | |||
255 | #define VML_READ32(_par, _offset) \ | ||
256 | (ioread32((_par)->vdc_mem + (_offset))) | ||
257 | #define VML_WRITE32(_par, _offset, _value) \ | ||
258 | iowrite32(_value, (_par)->vdc_mem + (_offset)) | ||
259 | |||
260 | #endif | ||
diff --git a/drivers/video/vfb.c b/drivers/video/vfb.c index a9b99b01bd8..64ee78c3c12 100644 --- a/drivers/video/vfb.c +++ b/drivers/video/vfb.c | |||
@@ -84,13 +84,15 @@ static int vfb_mmap(struct fb_info *info, | |||
84 | struct vm_area_struct *vma); | 84 | struct vm_area_struct *vma); |
85 | 85 | ||
86 | static struct fb_ops vfb_ops = { | 86 | static struct fb_ops vfb_ops = { |
87 | .fb_read = fb_sys_read, | ||
88 | .fb_write = fb_sys_write, | ||
87 | .fb_check_var = vfb_check_var, | 89 | .fb_check_var = vfb_check_var, |
88 | .fb_set_par = vfb_set_par, | 90 | .fb_set_par = vfb_set_par, |
89 | .fb_setcolreg = vfb_setcolreg, | 91 | .fb_setcolreg = vfb_setcolreg, |
90 | .fb_pan_display = vfb_pan_display, | 92 | .fb_pan_display = vfb_pan_display, |
91 | .fb_fillrect = cfb_fillrect, | 93 | .fb_fillrect = sys_fillrect, |
92 | .fb_copyarea = cfb_copyarea, | 94 | .fb_copyarea = sys_copyarea, |
93 | .fb_imageblit = cfb_imageblit, | 95 | .fb_imageblit = sys_imageblit, |
94 | .fb_mmap = vfb_mmap, | 96 | .fb_mmap = vfb_mmap, |
95 | }; | 97 | }; |
96 | 98 | ||
diff --git a/drivers/video/vga16fb.c b/drivers/video/vga16fb.c index ec4c7dc54a6..2a14d28c416 100644 --- a/drivers/video/vga16fb.c +++ b/drivers/video/vga16fb.c | |||
@@ -1378,6 +1378,8 @@ static int __init vga16fb_probe(struct platform_device *dev) | |||
1378 | info->fbops = &vga16fb_ops; | 1378 | info->fbops = &vga16fb_ops; |
1379 | info->var = vga16fb_defined; | 1379 | info->var = vga16fb_defined; |
1380 | info->fix = vga16fb_fix; | 1380 | info->fix = vga16fb_fix; |
1381 | /* supports rectangles with widths of multiples of 8 */ | ||
1382 | info->pixmap.blit_x = 1 << 7 | 1 << 15 | 1 << 23 | 1 << 31; | ||
1381 | info->flags = FBINFO_FLAG_DEFAULT | | 1383 | info->flags = FBINFO_FLAG_DEFAULT | |
1382 | FBINFO_HWACCEL_YPAN; | 1384 | FBINFO_HWACCEL_YPAN; |
1383 | 1385 | ||
diff --git a/drivers/video/vgastate.c b/drivers/video/vgastate.c index d94efafc77b..b91c466225b 100644 --- a/drivers/video/vgastate.c +++ b/drivers/video/vgastate.c | |||
@@ -50,23 +50,28 @@ static void save_vga_text(struct vgastate *state, void __iomem *fbbase) | |||
50 | struct regstate *saved = (struct regstate *) state->vidstate; | 50 | struct regstate *saved = (struct regstate *) state->vidstate; |
51 | int i; | 51 | int i; |
52 | u8 misc, attr10, gr4, gr5, gr6, seq1, seq2, seq4; | 52 | u8 misc, attr10, gr4, gr5, gr6, seq1, seq2, seq4; |
53 | unsigned short iobase; | ||
53 | 54 | ||
54 | /* if in graphics mode, no need to save */ | 55 | /* if in graphics mode, no need to save */ |
56 | misc = vga_r(state->vgabase, VGA_MIS_R); | ||
57 | iobase = (misc & 1) ? 0x3d0 : 0x3b0; | ||
58 | |||
59 | vga_r(state->vgabase, iobase + 0xa); | ||
60 | vga_w(state->vgabase, VGA_ATT_W, 0x00); | ||
55 | attr10 = vga_rattr(state->vgabase, 0x10); | 61 | attr10 = vga_rattr(state->vgabase, 0x10); |
62 | vga_r(state->vgabase, iobase + 0xa); | ||
63 | vga_w(state->vgabase, VGA_ATT_W, 0x20); | ||
64 | |||
56 | if (attr10 & 1) | 65 | if (attr10 & 1) |
57 | return; | 66 | return; |
58 | 67 | ||
59 | /* save regs */ | 68 | /* save regs */ |
60 | misc = vga_r(state->vgabase, VGA_MIS_R); | ||
61 | gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ); | 69 | gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ); |
62 | gr5 = vga_rgfx(state->vgabase, VGA_GFX_MODE); | 70 | gr5 = vga_rgfx(state->vgabase, VGA_GFX_MODE); |
63 | gr6 = vga_rgfx(state->vgabase, VGA_GFX_MISC); | 71 | gr6 = vga_rgfx(state->vgabase, VGA_GFX_MISC); |
64 | seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE); | 72 | seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE); |
65 | seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE); | 73 | seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE); |
66 | 74 | ||
67 | /* force graphics mode */ | ||
68 | vga_w(state->vgabase, VGA_MIS_W, misc | 1); | ||
69 | |||
70 | /* blank screen */ | 75 | /* blank screen */ |
71 | seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE); | 76 | seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE); |
72 | vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); | 77 | vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); |
@@ -115,15 +120,12 @@ static void save_vga_text(struct vgastate *state, void __iomem *fbbase) | |||
115 | } | 120 | } |
116 | 121 | ||
117 | /* restore regs */ | 122 | /* restore regs */ |
118 | vga_wattr(state->vgabase, 0x10, attr10); | ||
119 | |||
120 | vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, seq2); | 123 | vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, seq2); |
121 | vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, seq4); | 124 | vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, seq4); |
122 | 125 | ||
123 | vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4); | 126 | vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4); |
124 | vga_wgfx(state->vgabase, VGA_GFX_MODE, gr5); | 127 | vga_wgfx(state->vgabase, VGA_GFX_MODE, gr5); |
125 | vga_wgfx(state->vgabase, VGA_GFX_MISC, gr6); | 128 | vga_wgfx(state->vgabase, VGA_GFX_MISC, gr6); |
126 | vga_w(state->vgabase, VGA_MIS_W, misc); | ||
127 | 129 | ||
128 | /* unblank screen */ | 130 | /* unblank screen */ |
129 | vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); | 131 | vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); |
@@ -137,11 +139,10 @@ static void restore_vga_text(struct vgastate *state, void __iomem *fbbase) | |||
137 | { | 139 | { |
138 | struct regstate *saved = (struct regstate *) state->vidstate; | 140 | struct regstate *saved = (struct regstate *) state->vidstate; |
139 | int i; | 141 | int i; |
140 | u8 misc, gr1, gr3, gr4, gr5, gr6, gr8; | 142 | u8 gr1, gr3, gr4, gr5, gr6, gr8; |
141 | u8 seq1, seq2, seq4; | 143 | u8 seq1, seq2, seq4; |
142 | 144 | ||
143 | /* save regs */ | 145 | /* save regs */ |
144 | misc = vga_r(state->vgabase, VGA_MIS_R); | ||
145 | gr1 = vga_rgfx(state->vgabase, VGA_GFX_SR_ENABLE); | 146 | gr1 = vga_rgfx(state->vgabase, VGA_GFX_SR_ENABLE); |
146 | gr3 = vga_rgfx(state->vgabase, VGA_GFX_DATA_ROTATE); | 147 | gr3 = vga_rgfx(state->vgabase, VGA_GFX_DATA_ROTATE); |
147 | gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ); | 148 | gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ); |
@@ -151,9 +152,6 @@ static void restore_vga_text(struct vgastate *state, void __iomem *fbbase) | |||
151 | seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE); | 152 | seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE); |
152 | seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE); | 153 | seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE); |
153 | 154 | ||
154 | /* force graphics mode */ | ||
155 | vga_w(state->vgabase, VGA_MIS_W, misc | 1); | ||
156 | |||
157 | /* blank screen */ | 155 | /* blank screen */ |
158 | seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE); | 156 | seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE); |
159 | vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); | 157 | vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); |
@@ -213,8 +211,6 @@ static void restore_vga_text(struct vgastate *state, void __iomem *fbbase) | |||
213 | vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3); | 211 | vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3); |
214 | 212 | ||
215 | /* restore regs */ | 213 | /* restore regs */ |
216 | vga_w(state->vgabase, VGA_MIS_W, misc); | ||
217 | |||
218 | vga_wgfx(state->vgabase, VGA_GFX_SR_ENABLE, gr1); | 214 | vga_wgfx(state->vgabase, VGA_GFX_SR_ENABLE, gr1); |
219 | vga_wgfx(state->vgabase, VGA_GFX_DATA_ROTATE, gr3); | 215 | vga_wgfx(state->vgabase, VGA_GFX_DATA_ROTATE, gr3); |
220 | vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4); | 216 | vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4); |
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c new file mode 100644 index 00000000000..1d29a89a86b --- /dev/null +++ b/drivers/video/xilinxfb.c | |||
@@ -0,0 +1,381 @@ | |||
1 | /* | ||
2 | * xilinxfb.c | ||
3 | * | ||
4 | * Xilinx TFT LCD frame buffer driver | ||
5 | * | ||
6 | * Author: MontaVista Software, Inc. | ||
7 | * source@mvista.com | ||
8 | * | ||
9 | * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the | ||
10 | * terms of the GNU General Public License version 2. This program is licensed | ||
11 | * "as is" without any warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | /* | ||
15 | * This driver was based on au1100fb.c by MontaVista rewritten for 2.6 | ||
16 | * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn | ||
17 | * was based on skeletonfb.c, Skeleton for a frame buffer device by | ||
18 | * Geert Uytterhoeven. | ||
19 | */ | ||
20 | |||
21 | #include <linux/module.h> | ||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/version.h> | ||
24 | #include <linux/errno.h> | ||
25 | #include <linux/string.h> | ||
26 | #include <linux/mm.h> | ||
27 | #include <linux/fb.h> | ||
28 | #include <linux/init.h> | ||
29 | #include <linux/dma-mapping.h> | ||
30 | #include <linux/platform_device.h> | ||
31 | |||
32 | #include <asm/io.h> | ||
33 | #include <syslib/virtex_devices.h> | ||
34 | |||
35 | #define DRIVER_NAME "xilinxfb" | ||
36 | #define DRIVER_DESCRIPTION "Xilinx TFT LCD frame buffer driver" | ||
37 | |||
38 | /* | ||
39 | * Xilinx calls it "PLB TFT LCD Controller" though it can also be used for | ||
40 | * the VGA port on the Xilinx ML40x board. This is a hardware display controller | ||
41 | * for a 640x480 resolution TFT or VGA screen. | ||
42 | * | ||
43 | * The interface to the framebuffer is nice and simple. There are two | ||
44 | * control registers. The first tells the LCD interface where in memory | ||
45 | * the frame buffer is (only the 11 most significant bits are used, so | ||
46 | * don't start thinking about scrolling). The second allows the LCD to | ||
47 | * be turned on or off as well as rotated 180 degrees. | ||
48 | */ | ||
49 | #define NUM_REGS 2 | ||
50 | #define REG_FB_ADDR 0 | ||
51 | #define REG_CTRL 1 | ||
52 | #define REG_CTRL_ENABLE 0x0001 | ||
53 | #define REG_CTRL_ROTATE 0x0002 | ||
54 | |||
55 | /* | ||
56 | * The hardware only handles a single mode: 640x480 24 bit true | ||
57 | * color. Each pixel gets a word (32 bits) of memory. Within each word, | ||
58 | * the 8 most significant bits are ignored, the next 8 bits are the red | ||
59 | * level, the next 8 bits are the green level and the 8 least | ||
60 | * significant bits are the blue level. Each row of the LCD uses 1024 | ||
61 | * words, but only the first 640 pixels are displayed with the other 384 | ||
62 | * words being ignored. There are 480 rows. | ||
63 | */ | ||
64 | #define BYTES_PER_PIXEL 4 | ||
65 | #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8) | ||
66 | #define XRES 640 | ||
67 | #define YRES 480 | ||
68 | #define XRES_VIRTUAL 1024 | ||
69 | #define YRES_VIRTUAL YRES | ||
70 | #define LINE_LENGTH (XRES_VIRTUAL * BYTES_PER_PIXEL) | ||
71 | #define FB_SIZE (YRES_VIRTUAL * LINE_LENGTH) | ||
72 | |||
73 | #define RED_SHIFT 16 | ||
74 | #define GREEN_SHIFT 8 | ||
75 | #define BLUE_SHIFT 0 | ||
76 | |||
77 | #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */ | ||
78 | |||
79 | /* | ||
80 | * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures | ||
81 | */ | ||
82 | static struct fb_fix_screeninfo xilinx_fb_fix __initdata = { | ||
83 | .id = "Xilinx", | ||
84 | .type = FB_TYPE_PACKED_PIXELS, | ||
85 | .visual = FB_VISUAL_TRUECOLOR, | ||
86 | .smem_len = FB_SIZE, | ||
87 | .line_length = LINE_LENGTH, | ||
88 | .accel = FB_ACCEL_NONE | ||
89 | }; | ||
90 | |||
91 | static struct fb_var_screeninfo xilinx_fb_var __initdata = { | ||
92 | .xres = XRES, | ||
93 | .yres = YRES, | ||
94 | .xres_virtual = XRES_VIRTUAL, | ||
95 | .yres_virtual = YRES_VIRTUAL, | ||
96 | |||
97 | .bits_per_pixel = BITS_PER_PIXEL, | ||
98 | |||
99 | .red = { RED_SHIFT, 8, 0 }, | ||
100 | .green = { GREEN_SHIFT, 8, 0 }, | ||
101 | .blue = { BLUE_SHIFT, 8, 0 }, | ||
102 | .transp = { 0, 0, 0 }, | ||
103 | |||
104 | .activate = FB_ACTIVATE_NOW | ||
105 | }; | ||
106 | |||
107 | struct xilinxfb_drvdata { | ||
108 | |||
109 | struct fb_info info; /* FB driver info record */ | ||
110 | |||
111 | u32 regs_phys; /* phys. address of the control registers */ | ||
112 | u32 __iomem *regs; /* virt. address of the control registers */ | ||
113 | |||
114 | unsigned char __iomem *fb_virt; /* virt. address of the frame buffer */ | ||
115 | dma_addr_t fb_phys; /* phys. address of the frame buffer */ | ||
116 | |||
117 | u32 reg_ctrl_default; | ||
118 | |||
119 | u32 pseudo_palette[PALETTE_ENTRIES_NO]; | ||
120 | /* Fake palette of 16 colors */ | ||
121 | }; | ||
122 | |||
123 | #define to_xilinxfb_drvdata(_info) \ | ||
124 | container_of(_info, struct xilinxfb_drvdata, info) | ||
125 | |||
126 | /* | ||
127 | * The LCD controller has DCR interface to its registers, but all | ||
128 | * the boards and configurations the driver has been tested with | ||
129 | * use opb2dcr bridge. So the registers are seen as memory mapped. | ||
130 | * This macro is to make it simple to add the direct DCR access | ||
131 | * when it's needed. | ||
132 | */ | ||
133 | #define xilinx_fb_out_be32(driverdata, offset, val) \ | ||
134 | out_be32(driverdata->regs + offset, val) | ||
135 | |||
136 | static int | ||
137 | xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, | ||
138 | unsigned transp, struct fb_info *fbi) | ||
139 | { | ||
140 | u32 *palette = fbi->pseudo_palette; | ||
141 | |||
142 | if (regno >= PALETTE_ENTRIES_NO) | ||
143 | return -EINVAL; | ||
144 | |||
145 | if (fbi->var.grayscale) { | ||
146 | /* Convert color to grayscale. | ||
147 | * grayscale = 0.30*R + 0.59*G + 0.11*B */ | ||
148 | red = green = blue = | ||
149 | (red * 77 + green * 151 + blue * 28 + 127) >> 8; | ||
150 | } | ||
151 | |||
152 | /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */ | ||
153 | |||
154 | /* We only handle 8 bits of each color. */ | ||
155 | red >>= 8; | ||
156 | green >>= 8; | ||
157 | blue >>= 8; | ||
158 | palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) | | ||
159 | (blue << BLUE_SHIFT); | ||
160 | |||
161 | return 0; | ||
162 | } | ||
163 | |||
164 | static int | ||
165 | xilinx_fb_blank(int blank_mode, struct fb_info *fbi) | ||
166 | { | ||
167 | struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi); | ||
168 | |||
169 | switch (blank_mode) { | ||
170 | case FB_BLANK_UNBLANK: | ||
171 | /* turn on panel */ | ||
172 | xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); | ||
173 | break; | ||
174 | |||
175 | case FB_BLANK_NORMAL: | ||
176 | case FB_BLANK_VSYNC_SUSPEND: | ||
177 | case FB_BLANK_HSYNC_SUSPEND: | ||
178 | case FB_BLANK_POWERDOWN: | ||
179 | /* turn off panel */ | ||
180 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | ||
181 | default: | ||
182 | break; | ||
183 | |||
184 | } | ||
185 | return 0; /* success */ | ||
186 | } | ||
187 | |||
188 | static struct fb_ops xilinxfb_ops = | ||
189 | { | ||
190 | .owner = THIS_MODULE, | ||
191 | .fb_setcolreg = xilinx_fb_setcolreg, | ||
192 | .fb_blank = xilinx_fb_blank, | ||
193 | .fb_fillrect = cfb_fillrect, | ||
194 | .fb_copyarea = cfb_copyarea, | ||
195 | .fb_imageblit = cfb_imageblit, | ||
196 | }; | ||
197 | |||
198 | /* === The device driver === */ | ||
199 | |||
200 | static int | ||
201 | xilinxfb_drv_probe(struct device *dev) | ||
202 | { | ||
203 | struct platform_device *pdev; | ||
204 | struct xilinxfb_platform_data *pdata; | ||
205 | struct xilinxfb_drvdata *drvdata; | ||
206 | struct resource *regs_res; | ||
207 | int retval; | ||
208 | |||
209 | if (!dev) | ||
210 | return -EINVAL; | ||
211 | |||
212 | pdev = to_platform_device(dev); | ||
213 | pdata = pdev->dev.platform_data; | ||
214 | |||
215 | if (pdata == NULL) { | ||
216 | printk(KERN_ERR "Couldn't find platform data.\n"); | ||
217 | return -EFAULT; | ||
218 | } | ||
219 | |||
220 | drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); | ||
221 | if (!drvdata) { | ||
222 | printk(KERN_ERR "Couldn't allocate device private record\n"); | ||
223 | return -ENOMEM; | ||
224 | } | ||
225 | dev_set_drvdata(dev, drvdata); | ||
226 | |||
227 | /* Map the control registers in */ | ||
228 | regs_res = platform_get_resource(pdev, IORESOURCE_IO, 0); | ||
229 | if (!regs_res || (regs_res->end - regs_res->start + 1 < 8)) { | ||
230 | printk(KERN_ERR "Couldn't get registers resource\n"); | ||
231 | retval = -EFAULT; | ||
232 | goto failed1; | ||
233 | } | ||
234 | |||
235 | if (!request_mem_region(regs_res->start, 8, DRIVER_NAME)) { | ||
236 | printk(KERN_ERR | ||
237 | "Couldn't lock memory region at 0x%08X\n", | ||
238 | regs_res->start); | ||
239 | retval = -EBUSY; | ||
240 | goto failed1; | ||
241 | } | ||
242 | drvdata->regs = (u32 __iomem*) ioremap(regs_res->start, 8); | ||
243 | drvdata->regs_phys = regs_res->start; | ||
244 | |||
245 | /* Allocate the framebuffer memory */ | ||
246 | drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(FB_SIZE), | ||
247 | &drvdata->fb_phys, GFP_KERNEL); | ||
248 | if (!drvdata->fb_virt) { | ||
249 | printk(KERN_ERR "Could not allocate frame buffer memory\n"); | ||
250 | retval = -ENOMEM; | ||
251 | goto failed2; | ||
252 | } | ||
253 | |||
254 | /* Clear (turn to black) the framebuffer */ | ||
255 | memset_io((void *) drvdata->fb_virt, 0, FB_SIZE); | ||
256 | |||
257 | /* Tell the hardware where the frame buffer is */ | ||
258 | xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys); | ||
259 | |||
260 | /* Turn on the display */ | ||
261 | if (pdata->rotate_screen) { | ||
262 | drvdata->reg_ctrl_default = REG_CTRL_ENABLE | REG_CTRL_ROTATE; | ||
263 | } else { | ||
264 | drvdata->reg_ctrl_default = REG_CTRL_ENABLE; | ||
265 | } | ||
266 | xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); | ||
267 | |||
268 | /* Fill struct fb_info */ | ||
269 | drvdata->info.device = dev; | ||
270 | drvdata->info.screen_base = drvdata->fb_virt; | ||
271 | drvdata->info.fbops = &xilinxfb_ops; | ||
272 | drvdata->info.fix = xilinx_fb_fix; | ||
273 | drvdata->info.fix.smem_start = drvdata->fb_phys; | ||
274 | drvdata->info.pseudo_palette = drvdata->pseudo_palette; | ||
275 | |||
276 | if (fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0) < 0) { | ||
277 | printk(KERN_ERR "Fail to allocate colormap (%d entries)\n", | ||
278 | PALETTE_ENTRIES_NO); | ||
279 | retval = -EFAULT; | ||
280 | goto failed3; | ||
281 | } | ||
282 | |||
283 | drvdata->info.flags = FBINFO_DEFAULT; | ||
284 | xilinx_fb_var.height = pdata->screen_height_mm; | ||
285 | xilinx_fb_var.width = pdata->screen_width_mm; | ||
286 | drvdata->info.var = xilinx_fb_var; | ||
287 | |||
288 | /* Register new frame buffer */ | ||
289 | if (register_framebuffer(&drvdata->info) < 0) { | ||
290 | printk(KERN_ERR "Could not register frame buffer\n"); | ||
291 | retval = -EINVAL; | ||
292 | goto failed4; | ||
293 | } | ||
294 | |||
295 | return 0; /* success */ | ||
296 | |||
297 | failed4: | ||
298 | fb_dealloc_cmap(&drvdata->info.cmap); | ||
299 | |||
300 | failed3: | ||
301 | dma_free_coherent(dev, PAGE_ALIGN(FB_SIZE), drvdata->fb_virt, | ||
302 | drvdata->fb_phys); | ||
303 | |||
304 | /* Turn off the display */ | ||
305 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | ||
306 | iounmap(drvdata->regs); | ||
307 | |||
308 | failed2: | ||
309 | release_mem_region(regs_res->start, 8); | ||
310 | |||
311 | failed1: | ||
312 | kfree(drvdata); | ||
313 | dev_set_drvdata(dev, NULL); | ||
314 | |||
315 | return retval; | ||
316 | } | ||
317 | |||
318 | static int | ||
319 | xilinxfb_drv_remove(struct device *dev) | ||
320 | { | ||
321 | struct xilinxfb_drvdata *drvdata; | ||
322 | |||
323 | if (!dev) | ||
324 | return -ENODEV; | ||
325 | |||
326 | drvdata = (struct xilinxfb_drvdata *) dev_get_drvdata(dev); | ||
327 | |||
328 | #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) | ||
329 | xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info); | ||
330 | #endif | ||
331 | |||
332 | unregister_framebuffer(&drvdata->info); | ||
333 | |||
334 | fb_dealloc_cmap(&drvdata->info.cmap); | ||
335 | |||
336 | dma_free_coherent(dev, PAGE_ALIGN(FB_SIZE), drvdata->fb_virt, | ||
337 | drvdata->fb_phys); | ||
338 | |||
339 | /* Turn off the display */ | ||
340 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | ||
341 | iounmap(drvdata->regs); | ||
342 | |||
343 | release_mem_region(drvdata->regs_phys, 8); | ||
344 | |||
345 | kfree(drvdata); | ||
346 | dev_set_drvdata(dev, NULL); | ||
347 | |||
348 | return 0; | ||
349 | } | ||
350 | |||
351 | |||
352 | static struct device_driver xilinxfb_driver = { | ||
353 | .name = DRIVER_NAME, | ||
354 | .bus = &platform_bus_type, | ||
355 | |||
356 | .probe = xilinxfb_drv_probe, | ||
357 | .remove = xilinxfb_drv_remove | ||
358 | }; | ||
359 | |||
360 | static int __init | ||
361 | xilinxfb_init(void) | ||
362 | { | ||
363 | /* | ||
364 | * No kernel boot options used, | ||
365 | * so we just need to register the driver | ||
366 | */ | ||
367 | return driver_register(&xilinxfb_driver); | ||
368 | } | ||
369 | |||
370 | static void __exit | ||
371 | xilinxfb_cleanup(void) | ||
372 | { | ||
373 | driver_unregister(&xilinxfb_driver); | ||
374 | } | ||
375 | |||
376 | module_init(xilinxfb_init); | ||
377 | module_exit(xilinxfb_cleanup); | ||
378 | |||
379 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | ||
380 | MODULE_DESCRIPTION(DRIVER_DESCRIPTION); | ||
381 | MODULE_LICENSE("GPL"); | ||