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path: root/drivers/net/wireless/ath9k/mac.c
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Diffstat (limited to 'drivers/net/wireless/ath9k/mac.c')
-rw-r--r--drivers/net/wireless/ath9k/mac.c66
1 files changed, 26 insertions, 40 deletions
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
index 36955e0b184..8d2b139818e 100644
--- a/drivers/net/wireless/ath9k/mac.c
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -25,10 +25,10 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
25 struct ath_hal_5416 *ahp = AH5416(ah); 25 struct ath_hal_5416 *ahp = AH5416(ah);
26 26
27 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 27 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
28 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 28 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
29 __func__, ahp->ah_txOkInterruptMask, 29 ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask,
30 ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask, 30 ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask,
31 ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask); 31 ahp->ah_txUrnInterruptMask);
32 32
33 REG_WRITE(ah, AR_IMR_S0, 33 REG_WRITE(ah, AR_IMR_S0,
34 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) 34 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
@@ -126,7 +126,7 @@ bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp)
126 126
127bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) 127bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
128{ 128{
129 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); 129 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
130 130
131 REG_WRITE(ah, AR_Q_TXE, 1 << q); 131 REG_WRITE(ah, AR_Q_TXE, 1 << q);
132 132
@@ -207,9 +207,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
207 break; 207 break;
208 208
209 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 209 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
210 "%s: TSF have moved while trying to set " 210 "TSF have moved while trying to set "
211 "quiet time TSF: 0x%08x\n", 211 "quiet time TSF: 0x%08x\n", tsfLow);
212 __func__, tsfLow);
213 } 212 }
214 213
215 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 214 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
@@ -222,9 +221,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
222 while (ath9k_hw_numtxpending(ah, q)) { 221 while (ath9k_hw_numtxpending(ah, q)) {
223 if ((--wait) == 0) { 222 if ((--wait) == 0) {
224 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 223 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
225 "%s: Failed to stop Tx DMA in 100 " 224 "Failed to stop Tx DMA in 100 "
226 "msec after killing last frame\n", 225 "msec after killing last frame\n");
227 __func__);
228 break; 226 break;
229 } 227 }
230 udelay(100); 228 udelay(100);
@@ -523,19 +521,17 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
523 struct ath9k_tx_queue_info *qi; 521 struct ath9k_tx_queue_info *qi;
524 522
525 if (q >= pCap->total_queues) { 523 if (q >= pCap->total_queues) {
526 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 524 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
527 __func__, q);
528 return false; 525 return false;
529 } 526 }
530 527
531 qi = &ahp->ah_txq[q]; 528 qi = &ahp->ah_txq[q];
532 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 529 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
533 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", 530 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
534 __func__);
535 return false; 531 return false;
536 } 532 }
537 533
538 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi); 534 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %p\n", qi);
539 535
540 qi->tqi_ver = qinfo->tqi_ver; 536 qi->tqi_ver = qinfo->tqi_ver;
541 qi->tqi_subtype = qinfo->tqi_subtype; 537 qi->tqi_subtype = qinfo->tqi_subtype;
@@ -593,15 +589,13 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
593 struct ath9k_tx_queue_info *qi; 589 struct ath9k_tx_queue_info *qi;
594 590
595 if (q >= pCap->total_queues) { 591 if (q >= pCap->total_queues) {
596 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 592 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
597 __func__, q);
598 return false; 593 return false;
599 } 594 }
600 595
601 qi = &ahp->ah_txq[q]; 596 qi = &ahp->ah_txq[q];
602 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 597 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
603 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", 598 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
604 __func__);
605 return false; 599 return false;
606 } 600 }
607 601
@@ -651,22 +645,21 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
651 break; 645 break;
652 if (q == pCap->total_queues) { 646 if (q == pCap->total_queues) {
653 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 647 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
654 "%s: no available tx queue\n", __func__); 648 "no available tx queue\n");
655 return -1; 649 return -1;
656 } 650 }
657 break; 651 break;
658 default: 652 default:
659 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n", 653 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "bad tx queue type %u\n", type);
660 __func__, type);
661 return -1; 654 return -1;
662 } 655 }
663 656
664 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); 657 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
665 658
666 qi = &ahp->ah_txq[q]; 659 qi = &ahp->ah_txq[q];
667 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 660 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
668 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 661 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
669 "%s: tx queue %u already active\n", __func__, q); 662 "tx queue %u already active\n", q);
670 return -1; 663 return -1;
671 } 664 }
672 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 665 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -697,19 +690,16 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
697 struct ath9k_tx_queue_info *qi; 690 struct ath9k_tx_queue_info *qi;
698 691
699 if (q >= pCap->total_queues) { 692 if (q >= pCap->total_queues) {
700 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 693 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
701 __func__, q);
702 return false; 694 return false;
703 } 695 }
704 qi = &ahp->ah_txq[q]; 696 qi = &ahp->ah_txq[q];
705 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 697 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
706 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", 698 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
707 __func__, q);
708 return false; 699 return false;
709 } 700 }
710 701
711 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n", 702 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q);
712 __func__, q);
713 703
714 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 704 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
715 ahp->ah_txOkInterruptMask &= ~(1 << q); 705 ahp->ah_txOkInterruptMask &= ~(1 << q);
@@ -731,19 +721,17 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
731 u32 cwMin, chanCwMin, value; 721 u32 cwMin, chanCwMin, value;
732 722
733 if (q >= pCap->total_queues) { 723 if (q >= pCap->total_queues) {
734 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 724 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
735 __func__, q);
736 return false; 725 return false;
737 } 726 }
738 727
739 qi = &ahp->ah_txq[q]; 728 qi = &ahp->ah_txq[q];
740 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 729 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
741 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", 730 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
742 __func__, q);
743 return true; 731 return true;
744 } 732 }
745 733
746 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q); 734 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "reset queue %u\n", q);
747 735
748 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 736 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
749 if (chan && IS_CHAN_B(chan)) 737 if (chan && IS_CHAN_B(chan))
@@ -976,8 +964,7 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
976 964
977 reg = REG_READ(ah, AR_OBS_BUS_1); 965 reg = REG_READ(ah, AR_OBS_BUS_1);
978 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 966 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
979 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", 967 "rx failed to go idle in 10 ms RXSM=0x%x\n", reg);
980 __func__, reg);
981 968
982 return false; 969 return false;
983 } 970 }
@@ -1022,9 +1009,8 @@ bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
1022 1009
1023 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) { 1010 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
1024 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 1011 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1025 "%s: dma failed to stop in 10ms\n" 1012 "dma failed to stop in 10ms\n"
1026 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 1013 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
1027 __func__,
1028 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); 1014 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
1029 return false; 1015 return false;
1030 } else { 1016 } else {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 18:26:45 -0500