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-rw-r--r--drivers/net/atl1e/Makefile2
-rw-r--r--drivers/net/atl1e/atl1e.h503
-rw-r--r--drivers/net/atl1e/atl1e_ethtool.c405
-rw-r--r--drivers/net/atl1e/atl1e_hw.c664
-rw-r--r--drivers/net/atl1e/atl1e_hw.h793
-rw-r--r--drivers/net/atl1e/atl1e_main.c2599
-rw-r--r--drivers/net/atl1e/atl1e_param.c263
7 files changed, 5229 insertions, 0 deletions
diff --git a/drivers/net/atl1e/Makefile b/drivers/net/atl1e/Makefile
new file mode 100644
index 00000000000..bc11be824e7
--- /dev/null
+++ b/drivers/net/atl1e/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_ATL1E) += atl1e.o
2atl1e-objs += atl1e_main.o atl1e_hw.o atl1e_ethtool.o atl1e_param.o
diff --git a/drivers/net/atl1e/atl1e.h b/drivers/net/atl1e/atl1e.h
new file mode 100644
index 00000000000..b645fa0f3f6
--- /dev/null
+++ b/drivers/net/atl1e/atl1e.h
@@ -0,0 +1,503 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#ifndef _ATL1E_H_
24#define _ATL1E_H_
25
26#include <linux/version.h>
27#include <linux/init.h>
28#include <linux/types.h>
29#include <linux/errno.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/list.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/udp.h>
44#include <linux/mii.h>
45#include <linux/io.h>
46#include <linux/vmalloc.h>
47#include <linux/pagemap.h>
48#include <linux/tcp.h>
49#include <linux/mii.h>
50#include <linux/ethtool.h>
51#include <linux/if_vlan.h>
52#include <linux/workqueue.h>
53#include <net/checksum.h>
54#include <net/ip6_checksum.h>
55
56#include "atl1e_hw.h"
57
58#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
59#define CMD_IO_SPACE 0x0001
60#define CMD_MEMORY_SPACE 0x0002
61#define CMD_BUS_MASTER 0x0004
62
63#define BAR_0 0
64#define BAR_1 1
65#define BAR_5 5
66
67/* Wake Up Filter Control */
68#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
69#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
70#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
71#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
72#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
73
74#define SPEED_0 0xffff
75#define HALF_DUPLEX 1
76#define FULL_DUPLEX 2
77
78/* Error Codes */
79#define AT_ERR_EEPROM 1
80#define AT_ERR_PHY 2
81#define AT_ERR_CONFIG 3
82#define AT_ERR_PARAM 4
83#define AT_ERR_MAC_TYPE 5
84#define AT_ERR_PHY_TYPE 6
85#define AT_ERR_PHY_SPEED 7
86#define AT_ERR_PHY_RES 8
87#define AT_ERR_TIMEOUT 9
88
89#define MAX_JUMBO_FRAME_SIZE 0x2000
90
91#define AT_VLAN_TAG_TO_TPD_TAG(_vlan, _tpd) \
92 _tpd = (((_vlan) << (4)) | (((_vlan) >> 13) & 7) |\
93 (((_vlan) >> 9) & 8))
94
95#define AT_TPD_TAG_TO_VLAN_TAG(_tpd, _vlan) \
96 _vlan = (((_tpd) >> 8) | (((_tpd) & 0x77) << 9) |\
97 (((_tdp) & 0x88) << 5))
98
99#define AT_MAX_RECEIVE_QUEUE 4
100#define AT_PAGE_NUM_PER_QUEUE 2
101
102#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
103#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
104
105#define AT_TX_WATCHDOG (5 * HZ)
106#define AT_MAX_INT_WORK 10
107#define AT_TWSI_EEPROM_TIMEOUT 100
108#define AT_HW_MAX_IDLE_DELAY 10
109#define AT_SUSPEND_LINK_TIMEOUT 28
110
111#define AT_REGS_LEN 75
112#define AT_EEPROM_LEN 512
113#define AT_ADV_MASK (ADVERTISE_10_HALF |\
114 ADVERTISE_10_FULL |\
115 ADVERTISE_100_HALF |\
116 ADVERTISE_100_FULL |\
117 ADVERTISE_1000_FULL)
118
119/* tpd word 2 */
120#define TPD_BUFLEN_MASK 0x3FFF
121#define TPD_BUFLEN_SHIFT 0
122#define TPD_DMAINT_MASK 0x0001
123#define TPD_DMAINT_SHIFT 14
124#define TPD_PKTNT_MASK 0x0001
125#define TPD_PKTINT_SHIFT 15
126#define TPD_VLANTAG_MASK 0xFFFF
127#define TPD_VLAN_SHIFT 16
128
129/* tpd word 3 bits 0:4 */
130#define TPD_EOP_MASK 0x0001
131#define TPD_EOP_SHIFT 0
132#define TPD_IP_VERSION_MASK 0x0001
133#define TPD_IP_VERSION_SHIFT 1 /* 0 : IPV4, 1 : IPV6 */
134#define TPD_INS_VL_TAG_MASK 0x0001
135#define TPD_INS_VL_TAG_SHIFT 2
136#define TPD_CC_SEGMENT_EN_MASK 0x0001
137#define TPD_CC_SEGMENT_EN_SHIFT 3
138#define TPD_SEGMENT_EN_MASK 0x0001
139#define TPD_SEGMENT_EN_SHIFT 4
140
141/* tdp word 3 bits 5:7 if ip version is 0 */
142#define TPD_IP_CSUM_MASK 0x0001
143#define TPD_IP_CSUM_SHIFT 5
144#define TPD_TCP_CSUM_MASK 0x0001
145#define TPD_TCP_CSUM_SHIFT 6
146#define TPD_UDP_CSUM_MASK 0x0001
147#define TPD_UDP_CSUM_SHIFT 7
148
149/* tdp word 3 bits 5:7 if ip version is 1 */
150#define TPD_V6_IPHLLO_MASK 0x0007
151#define TPD_V6_IPHLLO_SHIFT 7
152
153/* tpd word 3 bits 8:9 bit */
154#define TPD_VL_TAGGED_MASK 0x0001
155#define TPD_VL_TAGGED_SHIFT 8
156#define TPD_ETHTYPE_MASK 0x0001
157#define TPD_ETHTYPE_SHIFT 9
158
159/* tdp word 3 bits 10:13 if ip version is 0 */
160#define TDP_V4_IPHL_MASK 0x000F
161#define TPD_V4_IPHL_SHIFT 10
162
163/* tdp word 3 bits 10:13 if ip version is 1 */
164#define TPD_V6_IPHLHI_MASK 0x000F
165#define TPD_V6_IPHLHI_SHIFT 10
166
167/* tpd word 3 bit 14:31 if segment enabled */
168#define TPD_TCPHDRLEN_MASK 0x000F
169#define TPD_TCPHDRLEN_SHIFT 14
170#define TPD_HDRFLAG_MASK 0x0001
171#define TPD_HDRFLAG_SHIFT 18
172#define TPD_MSS_MASK 0x1FFF
173#define TPD_MSS_SHIFT 19
174
175/* tdp word 3 bit 16:31 if custom csum enabled */
176#define TPD_PLOADOFFSET_MASK 0x00FF
177#define TPD_PLOADOFFSET_SHIFT 16
178#define TPD_CCSUMOFFSET_MASK 0x00FF
179#define TPD_CCSUMOFFSET_SHIFT 24
180
181struct atl1e_tpd_desc {
182 __le64 buffer_addr;
183 __le32 word2;
184 __le32 word3;
185};
186
187/* how about 0x2000 */
188#define MAX_TX_BUF_LEN 0x2000
189#define MAX_TX_BUF_SHIFT 13
190/*#define MAX_TX_BUF_LEN 0x3000 */
191
192/* rrs word 1 bit 0:31 */
193#define RRS_RX_CSUM_MASK 0xFFFF
194#define RRS_RX_CSUM_SHIFT 0
195#define RRS_PKT_SIZE_MASK 0x3FFF
196#define RRS_PKT_SIZE_SHIFT 16
197#define RRS_CPU_NUM_MASK 0x0003
198#define RRS_CPU_NUM_SHIFT 30
199
200#define RRS_IS_RSS_IPV4 0x0001
201#define RRS_IS_RSS_IPV4_TCP 0x0002
202#define RRS_IS_RSS_IPV6 0x0004
203#define RRS_IS_RSS_IPV6_TCP 0x0008
204#define RRS_IS_IPV6 0x0010
205#define RRS_IS_IP_FRAG 0x0020
206#define RRS_IS_IP_DF 0x0040
207#define RRS_IS_802_3 0x0080
208#define RRS_IS_VLAN_TAG 0x0100
209#define RRS_IS_ERR_FRAME 0x0200
210#define RRS_IS_IPV4 0x0400
211#define RRS_IS_UDP 0x0800
212#define RRS_IS_TCP 0x1000
213#define RRS_IS_BCAST 0x2000
214#define RRS_IS_MCAST 0x4000
215#define RRS_IS_PAUSE 0x8000
216
217#define RRS_ERR_BAD_CRC 0x0001
218#define RRS_ERR_CODE 0x0002
219#define RRS_ERR_DRIBBLE 0x0004
220#define RRS_ERR_RUNT 0x0008
221#define RRS_ERR_RX_OVERFLOW 0x0010
222#define RRS_ERR_TRUNC 0x0020
223#define RRS_ERR_IP_CSUM 0x0040
224#define RRS_ERR_L4_CSUM 0x0080
225#define RRS_ERR_LENGTH 0x0100
226#define RRS_ERR_DES_ADDR 0x0200
227
228struct atl1e_recv_ret_status {
229 u16 seq_num;
230 u16 hash_lo;
231 __le32 word1;
232 u16 pkt_flag;
233 u16 err_flag;
234 u16 hash_hi;
235 u16 vtag;
236};
237
238enum atl1e_dma_req_block {
239 atl1e_dma_req_128 = 0,
240 atl1e_dma_req_256 = 1,
241 atl1e_dma_req_512 = 2,
242 atl1e_dma_req_1024 = 3,
243 atl1e_dma_req_2048 = 4,
244 atl1e_dma_req_4096 = 5
245};
246
247enum atl1e_rrs_type {
248 atl1e_rrs_disable = 0,
249 atl1e_rrs_ipv4 = 1,
250 atl1e_rrs_ipv4_tcp = 2,
251 atl1e_rrs_ipv6 = 4,
252 atl1e_rrs_ipv6_tcp = 8
253};
254
255enum atl1e_nic_type {
256 athr_l1e = 0,
257 athr_l2e_revA = 1,
258 athr_l2e_revB = 2
259};
260
261struct atl1e_hw_stats {
262 /* rx */
263 unsigned long rx_ok; /* The number of good packet received. */
264 unsigned long rx_bcast; /* The number of good broadcast packet received. */
265 unsigned long rx_mcast; /* The number of good multicast packet received. */
266 unsigned long rx_pause; /* The number of Pause packet received. */
267 unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */
268 unsigned long rx_fcs_err; /* The number of packets with bad FCS. */
269 unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */
270 unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
271 unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
272 unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
273 unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
274 unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
275 unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
276 unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
277 unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
278 unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
279 unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
280 unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
281 unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
282 unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
283 unsigned long rx_align_err; /* Alignment Error */
284 unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
285 unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
286 unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */
287
288 /* tx */
289 unsigned long tx_ok; /* The number of good packet transmitted. */
290 unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */
291 unsigned long tx_mcast; /* The number of good multicast packet transmitted. */
292 unsigned long tx_pause; /* The number of Pause packet transmitted. */
293 unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
294 unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
295 unsigned long tx_defer; /* The number of packets transmitted that is deferred. */
296 unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
297 unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
298 unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
299 unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
300 unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
301 unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
302 unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
303 unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
304 unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
305 unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
306 unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */
307 unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
308 unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
309 unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
310 unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
311 unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
312 unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
313 unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
314};
315
316struct atl1e_hw {
317 u8 __iomem *hw_addr; /* inner register address */
318 resource_size_t mem_rang;
319 struct atl1e_adapter *adapter;
320 enum atl1e_nic_type nic_type;
321 u16 device_id;
322 u16 vendor_id;
323 u16 subsystem_id;
324 u16 subsystem_vendor_id;
325 u8 revision_id;
326 u16 pci_cmd_word;
327 u8 mac_addr[ETH_ALEN];
328 u8 perm_mac_addr[ETH_ALEN];
329 u8 preamble_len;
330 u16 max_frame_size;
331 u16 rx_jumbo_th;
332 u16 tx_jumbo_th;
333
334 u16 media_type;
335#define MEDIA_TYPE_AUTO_SENSOR 0
336#define MEDIA_TYPE_100M_FULL 1
337#define MEDIA_TYPE_100M_HALF 2
338#define MEDIA_TYPE_10M_FULL 3
339#define MEDIA_TYPE_10M_HALF 4
340
341 u16 autoneg_advertised;
342#define ADVERTISE_10_HALF 0x0001
343#define ADVERTISE_10_FULL 0x0002
344#define ADVERTISE_100_HALF 0x0004
345#define ADVERTISE_100_FULL 0x0008
346#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
347#define ADVERTISE_1000_FULL 0x0020
348 u16 mii_autoneg_adv_reg;
349 u16 mii_1000t_ctrl_reg;
350
351 u16 imt; /* Interrupt Moderator timer ( 2us resolution) */
352 u16 ict; /* Interrupt Clear timer (2us resolution) */
353 u32 smb_timer;
354 u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
355 interrupt request */
356 u16 tpd_thresh;
357 u16 rx_count_down; /* 2us resolution */
358 u16 tx_count_down;
359
360 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
361 enum atl1e_rrs_type rrs_type;
362 u32 base_cpu;
363 u32 indirect_tab;
364
365 enum atl1e_dma_req_block dmar_block;
366 enum atl1e_dma_req_block dmaw_block;
367 u8 dmaw_dly_cnt;
368 u8 dmar_dly_cnt;
369
370 bool phy_configured;
371 bool re_autoneg;
372 bool emi_ca;
373};
374
375/*
376 * wrapper around a pointer to a socket buffer,
377 * so a DMA handle can be stored along with the buffer
378 */
379struct atl1e_tx_buffer {
380 struct sk_buff *skb;
381 u16 length;
382 dma_addr_t dma;
383};
384
385struct atl1e_rx_page {
386 dma_addr_t dma; /* receive rage DMA address */
387 u8 *addr; /* receive rage virtual address */
388 dma_addr_t write_offset_dma; /* the DMA address which contain the
389 receive data offset in the page */
390 u32 *write_offset_addr; /* the virtaul address which contain
391 the receive data offset in the page */
392 u32 read_offset; /* the offset where we have read */
393};
394
395struct atl1e_rx_page_desc {
396 struct atl1e_rx_page rx_page[AT_PAGE_NUM_PER_QUEUE];
397 u8 rx_using;
398 u16 rx_nxseq;
399};
400
401/* transmit packet descriptor (tpd) ring */
402struct atl1e_tx_ring {
403 struct atl1e_tpd_desc *desc; /* descriptor ring virtual address */
404 dma_addr_t dma; /* descriptor ring physical address */
405 u16 count; /* the count of transmit rings */
406 rwlock_t tx_lock;
407 u16 next_to_use;
408 atomic_t next_to_clean;
409 struct atl1e_tx_buffer *tx_buffer;
410 dma_addr_t cmb_dma;
411 u32 *cmb;
412};
413
414/* receive packet descriptor ring */
415struct atl1e_rx_ring {
416 void *desc;
417 dma_addr_t dma;
418 int size;
419 u32 page_size; /* bytes length of rxf page */
420 u32 real_page_size; /* real_page_size = page_size + jumbo + aliagn */
421 struct atl1e_rx_page_desc rx_page_desc[AT_MAX_RECEIVE_QUEUE];
422};
423
424/* board specific private data structure */
425struct atl1e_adapter {
426 struct net_device *netdev;
427 struct pci_dev *pdev;
428 struct vlan_group *vlgrp;
429 struct napi_struct napi;
430 struct mii_if_info mii; /* MII interface info */
431 struct atl1e_hw hw;
432 struct atl1e_hw_stats hw_stats;
433 struct net_device_stats net_stats;
434
435 bool have_msi;
436 u32 wol;
437 u16 link_speed;
438 u16 link_duplex;
439
440 spinlock_t mdio_lock;
441 spinlock_t tx_lock;
442 atomic_t irq_sem;
443
444 struct work_struct reset_task;
445 struct work_struct link_chg_task;
446 struct timer_list watchdog_timer;
447 struct timer_list phy_config_timer;
448
449 /* All Descriptor memory */
450 dma_addr_t ring_dma;
451 void *ring_vir_addr;
452 int ring_size;
453
454 struct atl1e_tx_ring tx_ring;
455 struct atl1e_rx_ring rx_ring;
456 int num_rx_queues;
457 unsigned long flags;
458#define __AT_TESTING 0x0001
459#define __AT_RESETTING 0x0002
460#define __AT_DOWN 0x0003
461
462 u32 bd_number; /* board number;*/
463 u32 pci_state[16];
464 u32 *config_space;
465};
466
467#define AT_WRITE_REG(a, reg, value) ( \
468 writel((value), ((a)->hw_addr + reg)))
469
470#define AT_WRITE_FLUSH(a) (\
471 readl((a)->hw_addr))
472
473#define AT_READ_REG(a, reg) ( \
474 readl((a)->hw_addr + reg))
475
476#define AT_WRITE_REGB(a, reg, value) (\
477 writeb((value), ((a)->hw_addr + reg)))
478
479#define AT_READ_REGB(a, reg) (\
480 readb((a)->hw_addr + reg))
481
482#define AT_WRITE_REGW(a, reg, value) (\
483 writew((value), ((a)->hw_addr + reg)))
484
485#define AT_READ_REGW(a, reg) (\
486 readw((a)->hw_addr + reg))
487
488#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
489 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
490
491#define AT_READ_REG_ARRAY(a, reg, offset) ( \
492 readl(((a)->hw_addr + reg) + ((offset) << 2)))
493
494extern char atl1e_driver_name[];
495extern char atl1e_driver_version[];
496
497extern void atl1e_check_options(struct atl1e_adapter *adapter);
498extern int atl1e_up(struct atl1e_adapter *adapter);
499extern void atl1e_down(struct atl1e_adapter *adapter);
500extern void atl1e_reinit_locked(struct atl1e_adapter *adapter);
501extern s32 atl1e_reset_hw(struct atl1e_hw *hw);
502extern void atl1e_set_ethtool_ops(struct net_device *netdev);
503#endif /* _ATL1_E_H_ */
diff --git a/drivers/net/atl1e/atl1e_ethtool.c b/drivers/net/atl1e/atl1e_ethtool.c
new file mode 100644
index 00000000000..cdc3b85b10b
--- /dev/null
+++ b/drivers/net/atl1e/atl1e_ethtool.c
@@ -0,0 +1,405 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 */
22
23#include <linux/netdevice.h>
24#include <linux/ethtool.h>
25
26#include "atl1e.h"
27
28static int atl1e_get_settings(struct net_device *netdev,
29 struct ethtool_cmd *ecmd)
30{
31 struct atl1e_adapter *adapter = netdev_priv(netdev);
32 struct atl1e_hw *hw = &adapter->hw;
33
34 ecmd->supported = (SUPPORTED_10baseT_Half |
35 SUPPORTED_10baseT_Full |
36 SUPPORTED_100baseT_Half |
37 SUPPORTED_100baseT_Full |
38 SUPPORTED_Autoneg |
39 SUPPORTED_TP);
40 if (hw->nic_type == athr_l1e)
41 ecmd->supported |= SUPPORTED_1000baseT_Full;
42
43 ecmd->advertising = ADVERTISED_TP;
44
45 ecmd->advertising |= ADVERTISED_Autoneg;
46 ecmd->advertising |= hw->autoneg_advertised;
47
48 ecmd->port = PORT_TP;
49 ecmd->phy_address = 0;
50 ecmd->transceiver = XCVR_INTERNAL;
51
52 if (adapter->link_speed != SPEED_0) {
53 ecmd->speed = adapter->link_speed;
54 if (adapter->link_duplex == FULL_DUPLEX)
55 ecmd->duplex = DUPLEX_FULL;
56 else
57 ecmd->duplex = DUPLEX_HALF;
58 } else {
59 ecmd->speed = -1;
60 ecmd->duplex = -1;
61 }
62
63 ecmd->autoneg = AUTONEG_ENABLE;
64 return 0;
65}
66
67static int atl1e_set_settings(struct net_device *netdev,
68 struct ethtool_cmd *ecmd)
69{
70 struct atl1e_adapter *adapter = netdev_priv(netdev);
71 struct atl1e_hw *hw = &adapter->hw;
72
73 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
74 msleep(1);
75
76 if (ecmd->autoneg == AUTONEG_ENABLE) {
77 u16 adv4, adv9;
78
79 if ((ecmd->advertising&ADVERTISE_1000_FULL)) {
80 if (hw->nic_type == athr_l1e) {
81 hw->autoneg_advertised =
82 ecmd->advertising & AT_ADV_MASK;
83 } else {
84 clear_bit(__AT_RESETTING, &adapter->flags);
85 return -EINVAL;
86 }
87 } else if (ecmd->advertising&ADVERTISE_1000_HALF) {
88 clear_bit(__AT_RESETTING, &adapter->flags);
89 return -EINVAL;
90 } else {
91 hw->autoneg_advertised =
92 ecmd->advertising & AT_ADV_MASK;
93 }
94 ecmd->advertising = hw->autoneg_advertised |
95 ADVERTISED_TP | ADVERTISED_Autoneg;
96
97 adv4 = hw->mii_autoneg_adv_reg & ~MII_AR_SPEED_MASK;
98 adv9 = hw->mii_1000t_ctrl_reg & ~MII_AT001_CR_1000T_SPEED_MASK;
99 if (hw->autoneg_advertised & ADVERTISE_10_HALF)
100 adv4 |= MII_AR_10T_HD_CAPS;
101 if (hw->autoneg_advertised & ADVERTISE_10_FULL)
102 adv4 |= MII_AR_10T_FD_CAPS;
103 if (hw->autoneg_advertised & ADVERTISE_100_HALF)
104 adv4 |= MII_AR_100TX_HD_CAPS;
105 if (hw->autoneg_advertised & ADVERTISE_100_FULL)
106 adv4 |= MII_AR_100TX_FD_CAPS;
107 if (hw->autoneg_advertised & ADVERTISE_1000_FULL)
108 adv9 |= MII_AT001_CR_1000T_FD_CAPS;
109
110 if (adv4 != hw->mii_autoneg_adv_reg ||
111 adv9 != hw->mii_1000t_ctrl_reg) {
112 hw->mii_autoneg_adv_reg = adv4;
113 hw->mii_1000t_ctrl_reg = adv9;
114 hw->re_autoneg = true;
115 }
116
117 } else {
118 clear_bit(__AT_RESETTING, &adapter->flags);
119 return -EINVAL;
120 }
121
122 /* reset the link */
123
124 if (netif_running(adapter->netdev)) {
125 atl1e_down(adapter);
126 atl1e_up(adapter);
127 } else
128 atl1e_reset_hw(&adapter->hw);
129
130 clear_bit(__AT_RESETTING, &adapter->flags);
131 return 0;
132}
133
134static u32 atl1e_get_tx_csum(struct net_device *netdev)
135{
136 return (netdev->features & NETIF_F_HW_CSUM) != 0;
137}
138
139static u32 atl1e_get_msglevel(struct net_device *netdev)
140{
141#ifdef DBG
142 return 1;
143#else
144 return 0;
145#endif
146}
147
148static void atl1e_set_msglevel(struct net_device *netdev, u32 data)
149{
150}
151
152static int atl1e_get_regs_len(struct net_device *netdev)
153{
154 return AT_REGS_LEN * sizeof(u32);
155}
156
157static void atl1e_get_regs(struct net_device *netdev,
158 struct ethtool_regs *regs, void *p)
159{
160 struct atl1e_adapter *adapter = netdev_priv(netdev);
161 struct atl1e_hw *hw = &adapter->hw;
162 u32 *regs_buff = p;
163 u16 phy_data;
164
165 memset(p, 0, AT_REGS_LEN * sizeof(u32));
166
167 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
168
169 regs_buff[0] = AT_READ_REG(hw, REG_VPD_CAP);
170 regs_buff[1] = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
171 regs_buff[2] = AT_READ_REG(hw, REG_SPI_FLASH_CONFIG);
172 regs_buff[3] = AT_READ_REG(hw, REG_TWSI_CTRL);
173 regs_buff[4] = AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
174 regs_buff[5] = AT_READ_REG(hw, REG_MASTER_CTRL);
175 regs_buff[6] = AT_READ_REG(hw, REG_MANUAL_TIMER_INIT);
176 regs_buff[7] = AT_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
177 regs_buff[8] = AT_READ_REG(hw, REG_GPHY_CTRL);
178 regs_buff[9] = AT_READ_REG(hw, REG_CMBDISDMA_TIMER);
179 regs_buff[10] = AT_READ_REG(hw, REG_IDLE_STATUS);
180 regs_buff[11] = AT_READ_REG(hw, REG_MDIO_CTRL);
181 regs_buff[12] = AT_READ_REG(hw, REG_SERDES_LOCK);
182 regs_buff[13] = AT_READ_REG(hw, REG_MAC_CTRL);
183 regs_buff[14] = AT_READ_REG(hw, REG_MAC_IPG_IFG);
184 regs_buff[15] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
185 regs_buff[16] = AT_READ_REG(hw, REG_MAC_STA_ADDR+4);
186 regs_buff[17] = AT_READ_REG(hw, REG_RX_HASH_TABLE);
187 regs_buff[18] = AT_READ_REG(hw, REG_RX_HASH_TABLE+4);
188 regs_buff[19] = AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
189 regs_buff[20] = AT_READ_REG(hw, REG_MTU);
190 regs_buff[21] = AT_READ_REG(hw, REG_WOL_CTRL);
191 regs_buff[22] = AT_READ_REG(hw, REG_SRAM_TRD_ADDR);
192 regs_buff[23] = AT_READ_REG(hw, REG_SRAM_TRD_LEN);
193 regs_buff[24] = AT_READ_REG(hw, REG_SRAM_RXF_ADDR);
194 regs_buff[25] = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
195 regs_buff[26] = AT_READ_REG(hw, REG_SRAM_TXF_ADDR);
196 regs_buff[27] = AT_READ_REG(hw, REG_SRAM_TXF_LEN);
197 regs_buff[28] = AT_READ_REG(hw, REG_SRAM_TCPH_ADDR);
198 regs_buff[29] = AT_READ_REG(hw, REG_SRAM_PKTH_ADDR);
199
200 atl1e_read_phy_reg(hw, MII_BMCR, &phy_data);
201 regs_buff[73] = (u32)phy_data;
202 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
203 regs_buff[74] = (u32)phy_data;
204}
205
206static int atl1e_get_eeprom_len(struct net_device *netdev)
207{
208 struct atl1e_adapter *adapter = netdev_priv(netdev);
209
210 if (!atl1e_check_eeprom_exist(&adapter->hw))
211 return AT_EEPROM_LEN;
212 else
213 return 0;
214}
215
216static int atl1e_get_eeprom(struct net_device *netdev,
217 struct ethtool_eeprom *eeprom, u8 *bytes)
218{
219 struct atl1e_adapter *adapter = netdev_priv(netdev);
220 struct atl1e_hw *hw = &adapter->hw;
221 u32 *eeprom_buff;
222 int first_dword, last_dword;
223 int ret_val = 0;
224 int i;
225
226 if (eeprom->len == 0)
227 return -EINVAL;
228
229 if (atl1e_check_eeprom_exist(hw)) /* not exist */
230 return -EINVAL;
231
232 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
233
234 first_dword = eeprom->offset >> 2;
235 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
236
237 eeprom_buff = kmalloc(sizeof(u32) *
238 (last_dword - first_dword + 1), GFP_KERNEL);
239 if (eeprom_buff == NULL)
240 return -ENOMEM;
241
242 for (i = first_dword; i < last_dword; i++) {
243 if (!atl1e_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) {
244 kfree(eeprom_buff);
245 return -EIO;
246 }
247 }
248
249 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
250 eeprom->len);
251 kfree(eeprom_buff);
252
253 return ret_val;
254}
255
256static int atl1e_set_eeprom(struct net_device *netdev,
257 struct ethtool_eeprom *eeprom, u8 *bytes)
258{
259 struct atl1e_adapter *adapter = netdev_priv(netdev);
260 struct atl1e_hw *hw = &adapter->hw;
261 u32 *eeprom_buff;
262 u32 *ptr;
263 int first_dword, last_dword;
264 int ret_val = 0;
265 int i;
266
267 if (eeprom->len == 0)
268 return -EOPNOTSUPP;
269
270 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
271 return -EINVAL;
272
273 first_dword = eeprom->offset >> 2;
274 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
275 eeprom_buff = kmalloc(AT_EEPROM_LEN, GFP_KERNEL);
276 if (eeprom_buff == NULL)
277 return -ENOMEM;
278
279 ptr = (u32 *)eeprom_buff;
280
281 if (eeprom->offset & 3) {
282 /* need read/modify/write of first changed EEPROM word */
283 /* only the second byte of the word is being modified */
284 if (!atl1e_read_eeprom(hw, first_dword * 4, &(eeprom_buff[0]))) {
285 ret_val = -EIO;
286 goto out;
287 }
288 ptr++;
289 }
290 if (((eeprom->offset + eeprom->len) & 3)) {
291 /* need read/modify/write of last changed EEPROM word */
292 /* only the first byte of the word is being modified */
293
294 if (!atl1e_read_eeprom(hw, last_dword * 4,
295 &(eeprom_buff[last_dword - first_dword]))) {
296 ret_val = -EIO;
297 goto out;
298 }
299 }
300
301 /* Device's eeprom is always little-endian, word addressable */
302 memcpy(ptr, bytes, eeprom->len);
303
304 for (i = 0; i < last_dword - first_dword + 1; i++) {
305 if (!atl1e_write_eeprom(hw, ((first_dword + i) * 4),
306 eeprom_buff[i])) {
307 ret_val = -EIO;
308 goto out;
309 }
310 }
311out:
312 kfree(eeprom_buff);
313 return ret_val;
314}
315
316static void atl1e_get_drvinfo(struct net_device *netdev,
317 struct ethtool_drvinfo *drvinfo)
318{
319 struct atl1e_adapter *adapter = netdev_priv(netdev);
320
321 strncpy(drvinfo->driver, atl1e_driver_name, 32);
322 strncpy(drvinfo->version, atl1e_driver_version, 32);
323 strncpy(drvinfo->fw_version, "L1e", 32);
324 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
325 drvinfo->n_stats = 0;
326 drvinfo->testinfo_len = 0;
327 drvinfo->regdump_len = atl1e_get_regs_len(netdev);
328 drvinfo->eedump_len = atl1e_get_eeprom_len(netdev);
329}
330
331static void atl1e_get_wol(struct net_device *netdev,
332 struct ethtool_wolinfo *wol)
333{
334 struct atl1e_adapter *adapter = netdev_priv(netdev);
335
336 wol->supported = WAKE_MAGIC | WAKE_PHY;
337 wol->wolopts = 0;
338
339 if (adapter->wol & AT_WUFC_EX)
340 wol->wolopts |= WAKE_UCAST;
341 if (adapter->wol & AT_WUFC_MC)
342 wol->wolopts |= WAKE_MCAST;
343 if (adapter->wol & AT_WUFC_BC)
344 wol->wolopts |= WAKE_BCAST;
345 if (adapter->wol & AT_WUFC_MAG)
346 wol->wolopts |= WAKE_MAGIC;
347 if (adapter->wol & AT_WUFC_LNKC)
348 wol->wolopts |= WAKE_PHY;
349
350 return;
351}
352
353static int atl1e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
354{
355 struct atl1e_adapter *adapter = netdev_priv(netdev);
356
357 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
358 WAKE_MCAST | WAKE_BCAST | WAKE_MCAST))
359 return -EOPNOTSUPP;
360 /* these settings will always override what we currently have */
361 adapter->wol = 0;
362
363 if (wol->wolopts & WAKE_MAGIC)
364 adapter->wol |= AT_WUFC_MAG;
365 if (wol->wolopts & WAKE_PHY)
366 adapter->wol |= AT_WUFC_LNKC;
367
368 return 0;
369}
370
371static int atl1e_nway_reset(struct net_device *netdev)
372{
373 struct atl1e_adapter *adapter = netdev_priv(netdev);
374 if (netif_running(netdev))
375 atl1e_reinit_locked(adapter);
376 return 0;
377}
378
379static struct ethtool_ops atl1e_ethtool_ops = {
380 .get_settings = atl1e_get_settings,
381 .set_settings = atl1e_set_settings,
382 .get_drvinfo = atl1e_get_drvinfo,
383 .get_regs_len = atl1e_get_regs_len,
384 .get_regs = atl1e_get_regs,
385 .get_wol = atl1e_get_wol,
386 .set_wol = atl1e_set_wol,
387 .get_msglevel = atl1e_get_msglevel,
388 .set_msglevel = atl1e_set_msglevel,
389 .nway_reset = atl1e_nway_reset,
390 .get_link = ethtool_op_get_link,
391 .get_eeprom_len = atl1e_get_eeprom_len,
392 .get_eeprom = atl1e_get_eeprom,
393 .set_eeprom = atl1e_set_eeprom,
394 .get_tx_csum = atl1e_get_tx_csum,
395 .get_sg = ethtool_op_get_sg,
396 .set_sg = ethtool_op_set_sg,
397#ifdef NETIF_F_TSO
398 .get_tso = ethtool_op_get_tso,
399#endif
400};
401
402void atl1e_set_ethtool_ops(struct net_device *netdev)
403{
404 SET_ETHTOOL_OPS(netdev, &atl1e_ethtool_ops);
405}
diff --git a/drivers/net/atl1e/atl1e_hw.c b/drivers/net/atl1e/atl1e_hw.c
new file mode 100644
index 00000000000..949e75358bf
--- /dev/null
+++ b/drivers/net/atl1e/atl1e_hw.c
@@ -0,0 +1,664 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/mii.h>
24#include <linux/crc32.h>
25
26#include "atl1e.h"
27
28/*
29 * check_eeprom_exist
30 * return 0 if eeprom exist
31 */
32int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
33{
34 u32 value;
35
36 value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
37 if (value & SPI_FLASH_CTRL_EN_VPD) {
38 value &= ~SPI_FLASH_CTRL_EN_VPD;
39 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
40 }
41 value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
42 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
43}
44
45void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
46{
47 u32 value;
48 /*
49 * 00-0B-6A-F6-00-DC
50 * 0: 6AF600DC 1: 000B
51 * low dword
52 */
53 value = (((u32)hw->mac_addr[2]) << 24) |
54 (((u32)hw->mac_addr[3]) << 16) |
55 (((u32)hw->mac_addr[4]) << 8) |
56 (((u32)hw->mac_addr[5])) ;
57 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
58 /* hight dword */
59 value = (((u32)hw->mac_addr[0]) << 8) |
60 (((u32)hw->mac_addr[1])) ;
61 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
62}
63
64/*
65 * atl1e_get_permanent_address
66 * return 0 if get valid mac address,
67 */
68static int atl1e_get_permanent_address(struct atl1e_hw *hw)
69{
70 u32 addr[2];
71 u32 i;
72 u32 twsi_ctrl_data;
73 u8 eth_addr[ETH_ALEN];
74
75 if (is_valid_ether_addr(hw->perm_mac_addr))
76 return 0;
77
78 /* init */
79 addr[0] = addr[1] = 0;
80
81 if (!atl1e_check_eeprom_exist(hw)) {
82 /* eeprom exist */
83 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
84 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
85 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
86 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
87 msleep(10);
88 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
89 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
90 break;
91 }
92 if (i >= AT_TWSI_EEPROM_TIMEOUT)
93 return AT_ERR_TIMEOUT;
94 }
95
96 /* maybe MAC-address is from BIOS */
97 addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
98 addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
99 *(u32 *) &eth_addr[2] = swab32(addr[0]);
100 *(u16 *) &eth_addr[0] = swab16(*(u16 *)&addr[1]);
101
102 if (is_valid_ether_addr(eth_addr)) {
103 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
104 return 0;
105 }
106
107 return AT_ERR_EEPROM;
108}
109
110bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value)
111{
112 return true;
113}
114
115bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value)
116{
117 int i;
118 u32 control;
119
120 if (offset & 3)
121 return false; /* address do not align */
122
123 AT_WRITE_REG(hw, REG_VPD_DATA, 0);
124 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
125 AT_WRITE_REG(hw, REG_VPD_CAP, control);
126
127 for (i = 0; i < 10; i++) {
128 msleep(2);
129 control = AT_READ_REG(hw, REG_VPD_CAP);
130 if (control & VPD_CAP_VPD_FLAG)
131 break;
132 }
133 if (control & VPD_CAP_VPD_FLAG) {
134 *p_value = AT_READ_REG(hw, REG_VPD_DATA);
135 return true;
136 }
137 return false; /* timeout */
138}
139
140void atl1e_force_ps(struct atl1e_hw *hw)
141{
142 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
143 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
144}
145
146/*
147 * Reads the adapter's MAC address from the EEPROM
148 *
149 * hw - Struct containing variables accessed by shared code
150 */
151int atl1e_read_mac_addr(struct atl1e_hw *hw)
152{
153 int err = 0;
154
155 err = atl1e_get_permanent_address(hw);
156 if (err)
157 return AT_ERR_EEPROM;
158 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
159 return 0;
160}
161
162/*
163 * atl1e_hash_mc_addr
164 * purpose
165 * set hash value for a multicast address
166 * hash calcu processing :
167 * 1. calcu 32bit CRC for multicast address
168 * 2. reverse crc with MSB to LSB
169 */
170u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr)
171{
172 u32 crc32;
173 u32 value = 0;
174 int i;
175
176 crc32 = ether_crc_le(6, mc_addr);
177 crc32 = ~crc32;
178 for (i = 0; i < 32; i++)
179 value |= (((crc32 >> i) & 1) << (31 - i));
180
181 return value;
182}
183
184/*
185 * Sets the bit in the multicast table corresponding to the hash value.
186 * hw - Struct containing variables accessed by shared code
187 * hash_value - Multicast address hash value
188 */
189void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value)
190{
191 u32 hash_bit, hash_reg;
192 u32 mta;
193
194 /*
195 * The HASH Table is a register array of 2 32-bit registers.
196 * It is treated like an array of 64 bits. We want to set
197 * bit BitArray[hash_value]. So we figure out what register
198 * the bit is in, read it, OR in the new bit, then write
199 * back the new value. The register is determined by the
200 * upper 7 bits of the hash value and the bit within that
201 * register are determined by the lower 5 bits of the value.
202 */
203 hash_reg = (hash_value >> 31) & 0x1;
204 hash_bit = (hash_value >> 26) & 0x1F;
205
206 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
207
208 mta |= (1 << hash_bit);
209
210 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
211}
212/*
213 * Reads the value from a PHY register
214 * hw - Struct containing variables accessed by shared code
215 * reg_addr - address of the PHY register to read
216 */
217int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
218{
219 u32 val;
220 int i;
221
222 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
223 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
224 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
225
226 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
227
228 wmb();
229
230 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
231 udelay(2);
232 val = AT_READ_REG(hw, REG_MDIO_CTRL);
233 if (!(val & (MDIO_START | MDIO_BUSY)))
234 break;
235 wmb();
236 }
237 if (!(val & (MDIO_START | MDIO_BUSY))) {
238 *phy_data = (u16)val;
239 return 0;
240 }
241
242 return AT_ERR_PHY;
243}
244
245/*
246 * Writes a value to a PHY register
247 * hw - Struct containing variables accessed by shared code
248 * reg_addr - address of the PHY register to write
249 * data - data to write to the PHY
250 */
251int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
252{
253 int i;
254 u32 val;
255
256 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
257 (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
258 MDIO_SUP_PREAMBLE |
259 MDIO_START |
260 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
261
262 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
263 wmb();
264
265 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
266 udelay(2);
267 val = AT_READ_REG(hw, REG_MDIO_CTRL);
268 if (!(val & (MDIO_START | MDIO_BUSY)))
269 break;
270 wmb();
271 }
272
273 if (!(val & (MDIO_START | MDIO_BUSY)))
274 return 0;
275
276 return AT_ERR_PHY;
277}
278
279/*
280 * atl1e_init_pcie - init PCIE module
281 */
282static void atl1e_init_pcie(struct atl1e_hw *hw)
283{
284 u32 value;
285 /* comment 2lines below to save more power when sususpend
286 value = LTSSM_TEST_MODE_DEF;
287 AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
288 */
289
290 /* pcie flow control mode change */
291 value = AT_READ_REG(hw, 0x1008);
292 value |= 0x8000;
293 AT_WRITE_REG(hw, 0x1008, value);
294}
295/*
296 * Configures PHY autoneg and flow control advertisement settings
297 *
298 * hw - Struct containing variables accessed by shared code
299 */
300static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
301{
302 s32 ret_val;
303 u16 mii_autoneg_adv_reg;
304 u16 mii_1000t_ctrl_reg;
305
306 if (0 != hw->mii_autoneg_adv_reg)
307 return 0;
308 /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */
309 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
310 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
311
312 /*
313 * Need to parse autoneg_advertised and set up
314 * the appropriate PHY registers. First we will parse for
315 * autoneg_advertised software override. Since we can advertise
316 * a plethora of combinations, we need to check each bit
317 * individually.
318 */
319
320 /*
321 * First we clear all the 10/100 mb speed bits in the Auto-Neg
322 * Advertisement Register (Address 4) and the 1000 mb speed bits in
323 * the 1000Base-T control Register (Address 9).
324 */
325 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
326 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
327
328 /*
329 * Need to parse MediaType and setup the
330 * appropriate PHY registers.
331 */
332 switch (hw->media_type) {
333 case MEDIA_TYPE_AUTO_SENSOR:
334 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
335 MII_AR_10T_FD_CAPS |
336 MII_AR_100TX_HD_CAPS |
337 MII_AR_100TX_FD_CAPS);
338 hw->autoneg_advertised = ADVERTISE_10_HALF |
339 ADVERTISE_10_FULL |
340 ADVERTISE_100_HALF |
341 ADVERTISE_100_FULL;
342 if (hw->nic_type == athr_l1e) {
343 mii_1000t_ctrl_reg |=
344 MII_AT001_CR_1000T_FD_CAPS;
345 hw->autoneg_advertised |= ADVERTISE_1000_FULL;
346 }
347 break;
348
349 case MEDIA_TYPE_100M_FULL:
350 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
351 hw->autoneg_advertised = ADVERTISE_100_FULL;
352 break;
353
354 case MEDIA_TYPE_100M_HALF:
355 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
356 hw->autoneg_advertised = ADVERTISE_100_HALF;
357 break;
358
359 case MEDIA_TYPE_10M_FULL:
360 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
361 hw->autoneg_advertised = ADVERTISE_10_FULL;
362 break;
363
364 default:
365 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
366 hw->autoneg_advertised = ADVERTISE_10_HALF;
367 break;
368 }
369
370 /* flow control fixed to enable all */
371 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
372
373 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
374 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
375
376 ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
377 if (ret_val)
378 return ret_val;
379
380 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
381 ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR,
382 mii_1000t_ctrl_reg);
383 if (ret_val)
384 return ret_val;
385 }
386
387 return 0;
388}
389
390
391/*
392 * Resets the PHY and make all config validate
393 *
394 * hw - Struct containing variables accessed by shared code
395 *
396 * Sets bit 15 and 12 of the MII control regiser (for F001 bug)
397 */
398int atl1e_phy_commit(struct atl1e_hw *hw)
399{
400 struct atl1e_adapter *adapter = (struct atl1e_adapter *)hw->adapter;
401 struct pci_dev *pdev = adapter->pdev;
402 int ret_val;
403 u16 phy_data;
404
405 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
406
407 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
408 if (ret_val) {
409 u32 val;
410 int i;
411 /**************************************
412 * pcie serdes link may be down !
413 **************************************/
414 for (i = 0; i < 25; i++) {
415 msleep(1);
416 val = AT_READ_REG(hw, REG_MDIO_CTRL);
417 if (!(val & (MDIO_START | MDIO_BUSY)))
418 break;
419 }
420
421 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
422 dev_err(&pdev->dev,
423 "pcie linkdown at least for 25ms\n");
424 return ret_val;
425 }
426
427 dev_err(&pdev->dev, "pcie linkup after %d ms\n", i);
428 }
429 return 0;
430}
431
432int atl1e_phy_init(struct atl1e_hw *hw)
433{
434 struct atl1e_adapter *adapter = (struct atl1e_adapter *)hw->adapter;
435 struct pci_dev *pdev = adapter->pdev;
436 s32 ret_val;
437 u16 phy_val;
438
439 if (hw->phy_configured) {
440 if (hw->re_autoneg) {
441 hw->re_autoneg = false;
442 return atl1e_restart_autoneg(hw);
443 }
444 return 0;
445 }
446
447 /* RESET GPHY Core */
448 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
449 msleep(2);
450 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
451 GPHY_CTRL_EXT_RESET);
452 msleep(2);
453
454 /* patches */
455 /* p1. eable hibernation mode */
456 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
457 if (ret_val)
458 return ret_val;
459 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
460 if (ret_val)
461 return ret_val;
462 /* p2. set Class A/B for all modes */
463 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
464 if (ret_val)
465 return ret_val;
466 phy_val = 0x02ef;
467 /* remove Class AB */
468 /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
469 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
470 if (ret_val)
471 return ret_val;
472 /* p3. 10B ??? */
473 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
474 if (ret_val)
475 return ret_val;
476 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
477 if (ret_val)
478 return ret_val;
479 /* p4. 1000T power */
480 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
481 if (ret_val)
482 return ret_val;
483 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
484 if (ret_val)
485 return ret_val;
486
487 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
488 if (ret_val)
489 return ret_val;
490 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
491 if (ret_val)
492 return ret_val;
493
494 msleep(1);
495
496 /*Enable PHY LinkChange Interrupt */
497 ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
498 if (ret_val) {
499 dev_err(&pdev->dev, "Error enable PHY linkChange Interrupt\n");
500 return ret_val;
501 }
502 /* setup AutoNeg parameters */
503 ret_val = atl1e_phy_setup_autoneg_adv(hw);
504 if (ret_val) {
505 dev_err(&pdev->dev, "Error Setting up Auto-Negotiation\n");
506 return ret_val;
507 }
508 /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
509 dev_dbg(&pdev->dev, "Restarting Auto-Neg");
510 ret_val = atl1e_phy_commit(hw);
511 if (ret_val) {
512 dev_err(&pdev->dev, "Error Resetting the phy");
513 return ret_val;
514 }
515
516 hw->phy_configured = true;
517
518 return 0;
519}
520
521/*
522 * Reset the transmit and receive units; mask and clear all interrupts.
523 * hw - Struct containing variables accessed by shared code
524 * return : 0 or idle status (if error)
525 */
526int atl1e_reset_hw(struct atl1e_hw *hw)
527{
528 struct atl1e_adapter *adapter = (struct atl1e_adapter *)hw->adapter;
529 struct pci_dev *pdev = adapter->pdev;
530
531 u32 idle_status_data = 0;
532 u16 pci_cfg_cmd_word = 0;
533 int timeout = 0;
534
535 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
536 pci_read_config_word(pdev, PCI_REG_COMMAND, &pci_cfg_cmd_word);
537 if ((pci_cfg_cmd_word & (CMD_IO_SPACE |
538 CMD_MEMORY_SPACE | CMD_BUS_MASTER))
539 != (CMD_IO_SPACE | CMD_MEMORY_SPACE | CMD_BUS_MASTER)) {
540 pci_cfg_cmd_word |= (CMD_IO_SPACE |
541 CMD_MEMORY_SPACE | CMD_BUS_MASTER);
542 pci_write_config_word(pdev, PCI_REG_COMMAND, pci_cfg_cmd_word);
543 }
544
545 /*
546 * Issue Soft Reset to the MAC. This will reset the chip's
547 * transmit, receive, DMA. It will not effect
548 * the current PCI configuration. The global reset bit is self-
549 * clearing, and should clear within a microsecond.
550 */
551 AT_WRITE_REG(hw, REG_MASTER_CTRL,
552 MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST);
553 wmb();
554 msleep(1);
555
556 /* Wait at least 10ms for All module to be Idle */
557 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
558 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
559 if (idle_status_data == 0)
560 break;
561 msleep(1);
562 cpu_relax();
563 }
564
565 if (timeout >= AT_HW_MAX_IDLE_DELAY) {
566 dev_err(&pdev->dev,
567 "MAC state machine cann't be idle since"
568 " disabled for 10ms second\n");
569 return AT_ERR_TIMEOUT;
570 }
571
572 return 0;
573}
574
575
576/*
577 * Performs basic configuration of the adapter.
578 *
579 * hw - Struct containing variables accessed by shared code
580 * Assumes that the controller has previously been reset and is in a
581 * post-reset uninitialized state. Initializes multicast table,
582 * and Calls routines to setup link
583 * Leaves the transmit and receive units disabled and uninitialized.
584 */
585int atl1e_init_hw(struct atl1e_hw *hw)
586{
587 s32 ret_val = 0;
588
589 atl1e_init_pcie(hw);
590
591 /* Zero out the Multicast HASH table */
592 /* clear the old settings from the multicast hash table */
593 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
594 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
595
596 ret_val = atl1e_phy_init(hw);
597
598 return ret_val;
599}
600
601/*
602 * Detects the current speed and duplex settings of the hardware.
603 *
604 * hw - Struct containing variables accessed by shared code
605 * speed - Speed of the connection
606 * duplex - Duplex setting of the connection
607 */
608int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
609{
610 int err;
611 u16 phy_data;
612
613 /* Read PHY Specific Status Register (17) */
614 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
615 if (err)
616 return err;
617
618 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
619 return AT_ERR_PHY_RES;
620
621 switch (phy_data & MII_AT001_PSSR_SPEED) {
622 case MII_AT001_PSSR_1000MBS:
623 *speed = SPEED_1000;
624 break;
625 case MII_AT001_PSSR_100MBS:
626 *speed = SPEED_100;
627 break;
628 case MII_AT001_PSSR_10MBS:
629 *speed = SPEED_10;
630 break;
631 default:
632 return AT_ERR_PHY_SPEED;
633 break;
634 }
635
636 if (phy_data & MII_AT001_PSSR_DPLX)
637 *duplex = FULL_DUPLEX;
638 else
639 *duplex = HALF_DUPLEX;
640
641 return 0;
642}
643
644int atl1e_restart_autoneg(struct atl1e_hw *hw)
645{
646 int err = 0;
647
648 err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
649 if (err)
650 return err;
651
652 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
653 err = atl1e_write_phy_reg(hw, MII_AT001_CR,
654 hw->mii_1000t_ctrl_reg);
655 if (err)
656 return err;
657 }
658
659 err = atl1e_write_phy_reg(hw, MII_BMCR,
660 MII_CR_RESET | MII_CR_AUTO_NEG_EN |
661 MII_CR_RESTART_AUTO_NEG);
662 return err;
663}
664
diff --git a/drivers/net/atl1e/atl1e_hw.h b/drivers/net/atl1e/atl1e_hw.h
new file mode 100644
index 00000000000..5ea2f4d86cf
--- /dev/null
+++ b/drivers/net/atl1e/atl1e_hw.h
@@ -0,0 +1,793 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATHL1E_HW_H_
23#define _ATHL1E_HW_H_
24
25#include <linux/types.h>
26#include <linux/mii.h>
27
28struct atl1e_adapter;
29struct atl1e_hw;
30
31/* function prototype */
32s32 atl1e_reset_hw(struct atl1e_hw *hw);
33s32 atl1e_read_mac_addr(struct atl1e_hw *hw);
34s32 atl1e_init_hw(struct atl1e_hw *hw);
35s32 atl1e_phy_commit(struct atl1e_hw *hw);
36s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex);
37u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex);
38u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr);
39void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value);
40s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data);
41s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data);
42s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw);
43void atl1e_hw_set_mac_addr(struct atl1e_hw *hw);
44bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value);
45bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value);
46s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw);
47s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw);
48s32 atl1e_phy_init(struct atl1e_hw *hw);
49int atl1e_check_eeprom_exist(struct atl1e_hw *hw);
50void atl1e_force_ps(struct atl1e_hw *hw);
51s32 atl1e_restart_autoneg(struct atl1e_hw *hw);
52
53/* register definition */
54#define REG_PM_CTRLSTAT 0x44
55
56#define REG_PCIE_CAP_LIST 0x58
57
58#define REG_DEVICE_CAP 0x5C
59#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
60#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
61
62#define REG_DEVICE_CTRL 0x60
63#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
64#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
65#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
66#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
67
68#define REG_VPD_CAP 0x6C
69#define VPD_CAP_ID_MASK 0xff
70#define VPD_CAP_ID_SHIFT 0
71#define VPD_CAP_NEXT_PTR_MASK 0xFF
72#define VPD_CAP_NEXT_PTR_SHIFT 8
73#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
74#define VPD_CAP_VPD_ADDR_SHIFT 16
75#define VPD_CAP_VPD_FLAG 0x80000000
76
77#define REG_VPD_DATA 0x70
78
79#define REG_SPI_FLASH_CTRL 0x200
80#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
81#define SPI_FLASH_CTRL_STS_WEN 0x2
82#define SPI_FLASH_CTRL_STS_WPEN 0x80
83#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
84#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
85#define SPI_FLASH_CTRL_INS_MASK 0x7
86#define SPI_FLASH_CTRL_INS_SHIFT 8
87#define SPI_FLASH_CTRL_START 0x800
88#define SPI_FLASH_CTRL_EN_VPD 0x2000
89#define SPI_FLASH_CTRL_LDSTART 0x8000
90#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
91#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
92#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
93#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
94#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
95#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
96#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
97#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
98#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
99#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
100#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
101#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
102#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
103
104#define REG_SPI_ADDR 0x204
105
106#define REG_SPI_DATA 0x208
107
108#define REG_SPI_FLASH_CONFIG 0x20C
109#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
110#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
111#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
112#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
113#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
114
115
116#define REG_SPI_FLASH_OP_PROGRAM 0x210
117#define REG_SPI_FLASH_OP_SC_ERASE 0x211
118#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
119#define REG_SPI_FLASH_OP_RDID 0x213
120#define REG_SPI_FLASH_OP_WREN 0x214
121#define REG_SPI_FLASH_OP_RDSR 0x215
122#define REG_SPI_FLASH_OP_WRSR 0x216
123#define REG_SPI_FLASH_OP_READ 0x217
124
125#define REG_TWSI_CTRL 0x218
126#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
127#define TWSI_CTRL_LD_OFFSET_SHIFT 0
128#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
129#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
130#define TWSI_CTRL_SW_LDSTART 0x800
131#define TWSI_CTRL_HW_LDSTART 0x1000
132#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F
133#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
134#define TWSI_CTRL_LD_EXIST 0x400000
135#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
136#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
137#define TWSI_CTRL_FREQ_SEL_100K 0
138#define TWSI_CTRL_FREQ_SEL_200K 1
139#define TWSI_CTRL_FREQ_SEL_300K 2
140#define TWSI_CTRL_FREQ_SEL_400K 3
141#define TWSI_CTRL_SMB_SLV_ADDR
142#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
143#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
144
145
146#define REG_PCIE_DEV_MISC_CTRL 0x21C
147#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
148#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
149#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
150#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
151#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
152
153#define REG_PCIE_PHYMISC 0x1000
154#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
155
156#define REG_LTSSM_TEST_MODE 0x12FC
157#define LTSSM_TEST_MODE_DEF 0xE000
158
159/* Selene Master Control Register */
160#define REG_MASTER_CTRL 0x1400
161#define MASTER_CTRL_SOFT_RST 0x1
162#define MASTER_CTRL_MTIMER_EN 0x2
163#define MASTER_CTRL_ITIMER_EN 0x4
164#define MASTER_CTRL_MANUAL_INT 0x8
165#define MASTER_CTRL_ITIMER2_EN 0x20
166#define MASTER_CTRL_INT_RDCLR 0x40
167#define MASTER_CTRL_LED_MODE 0x200
168#define MASTER_CTRL_REV_NUM_SHIFT 16
169#define MASTER_CTRL_REV_NUM_MASK 0xff
170#define MASTER_CTRL_DEV_ID_SHIFT 24
171#define MASTER_CTRL_DEV_ID_MASK 0xff
172
173/* Timer Initial Value Register */
174#define REG_MANUAL_TIMER_INIT 0x1404
175
176
177/* IRQ ModeratorTimer Initial Value Register */
178#define REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */
179#define REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */
180
181
182#define REG_GPHY_CTRL 0x140C
183#define GPHY_CTRL_EXT_RESET 1
184#define GPHY_CTRL_PIPE_MOD 2
185#define GPHY_CTRL_TEST_MODE_MASK 3
186#define GPHY_CTRL_TEST_MODE_SHIFT 2
187#define GPHY_CTRL_BERT_START 0x10
188#define GPHY_CTRL_GATE_25M_EN 0x20
189#define GPHY_CTRL_LPW_EXIT 0x40
190#define GPHY_CTRL_PHY_IDDQ 0x80
191#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
192#define GPHY_CTRL_PCLK_SEL_DIS 0x200
193#define GPHY_CTRL_HIB_EN 0x400
194#define GPHY_CTRL_HIB_PULSE 0x800
195#define GPHY_CTRL_SEL_ANA_RST 0x1000
196#define GPHY_CTRL_PHY_PLL_ON 0x2000
197#define GPHY_CTRL_PWDOWN_HW 0x4000
198#define GPHY_CTRL_DEFAULT (\
199 GPHY_CTRL_PHY_PLL_ON |\
200 GPHY_CTRL_SEL_ANA_RST |\
201 GPHY_CTRL_HIB_PULSE |\
202 GPHY_CTRL_HIB_EN)
203
204#define GPHY_CTRL_PW_WOL_DIS (\
205 GPHY_CTRL_PHY_PLL_ON |\
206 GPHY_CTRL_SEL_ANA_RST |\
207 GPHY_CTRL_HIB_PULSE |\
208 GPHY_CTRL_HIB_EN |\
209 GPHY_CTRL_PWDOWN_HW |\
210 GPHY_CTRL_PCLK_SEL_DIS |\
211 GPHY_CTRL_PHY_IDDQ)
212
213/* IRQ Anti-Lost Timer Initial Value Register */
214#define REG_CMBDISDMA_TIMER 0x140E
215
216
217/* Block IDLE Status Register */
218#define REG_IDLE_STATUS 0x1410
219#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
220#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
221#define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */
222#define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */
223#define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */
224#define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */
225#define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */
226#define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */
227
228/* MDIO Control Register */
229#define REG_MDIO_CTRL 0x1414
230#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
231#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
232#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
233#define MDIO_REG_ADDR_SHIFT 16
234#define MDIO_RW 0x200000 /* 1: read, 0: write */
235#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
236#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/
237#define MDIO_CLK_SEL_SHIFT 24
238#define MDIO_CLK_25_4 0
239#define MDIO_CLK_25_6 2
240#define MDIO_CLK_25_8 3
241#define MDIO_CLK_25_10 4
242#define MDIO_CLK_25_14 5
243#define MDIO_CLK_25_20 6
244#define MDIO_CLK_25_28 7
245#define MDIO_BUSY 0x8000000
246#define MDIO_AP_EN 0x10000000
247#define MDIO_WAIT_TIMES 10
248
249/* MII PHY Status Register */
250#define REG_PHY_STATUS 0x1418
251#define PHY_STATUS_100M 0x20000
252#define PHY_STATUS_EMI_CA 0x40000
253
254/* BIST Control and Status Register0 (for the Packet Memory) */
255#define REG_BIST0_CTRL 0x141c
256#define BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
257/* BIST process and reset to zero when BIST is done */
258#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
259/* decoder failure or more than 1 cell stuck-to-x failure */
260#define BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */
261
262/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
263#define REG_BIST1_CTRL 0x1420
264#define BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
265/* BIST process and reset to zero when BIST is done */
266#define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
267/* decoder failure or more than 1 cell stuck-to-x failure.*/
268#define BIST1_FUSE_FLAG 0x4
269
270/* SerDes Lock Detect Control and Status Register */
271#define REG_SERDES_LOCK 0x1424
272#define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */
273#define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */
274
275/* MAC Control Register */
276#define REG_MAC_CTRL 0x1480
277#define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */
278#define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */
279#define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */
280#define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */
281#define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */
282#define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
283#define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
284#define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
285#define MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */
286#define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */
287#define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */
288#define MAC_CTRL_PRMLEN_MASK 0xf
289#define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */
290#define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */
291#define MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */
292#define MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */
293#define MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */
294#define MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */
295#define MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */
296#define MAC_CTRL_SPEED_MASK 0x300000
297#define MAC_CTRL_SPEED_1000 2
298#define MAC_CTRL_SPEED_10_100 1
299#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */
300#define MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */
301#define MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */
302#define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */
303#define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */
304#define MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */
305
306/* MAC IPG/IFG Control Register */
307#define REG_MAC_IPG_IFG 0x1484
308#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */
309#define MAC_IPG_IFG_IPGT_MASK 0x7f
310#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */
311#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
312#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
313#define MAC_IPG_IFG_IPGR1_MASK 0x7f
314#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
315#define MAC_IPG_IFG_IPGR2_MASK 0x7f
316
317/* MAC STATION ADDRESS */
318#define REG_MAC_STA_ADDR 0x1488
319
320/* Hash table for multicast address */
321#define REG_RX_HASH_TABLE 0x1490
322
323
324/* MAC Half-Duplex Control Register */
325#define REG_MAC_HALF_DUPLX_CTRL 0x1498
326#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
327#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
328#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */
329#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
330#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
331#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */
332#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
333#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
334#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
335#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
336#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
337#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
338
339/* Maximum Frame Length Control Register */
340#define REG_MTU 0x149c
341
342/* Wake-On-Lan control register */
343#define REG_WOL_CTRL 0x14a0
344#define WOL_PATTERN_EN 0x00000001
345#define WOL_PATTERN_PME_EN 0x00000002
346#define WOL_MAGIC_EN 0x00000004
347#define WOL_MAGIC_PME_EN 0x00000008
348#define WOL_LINK_CHG_EN 0x00000010
349#define WOL_LINK_CHG_PME_EN 0x00000020
350#define WOL_PATTERN_ST 0x00000100
351#define WOL_MAGIC_ST 0x00000200
352#define WOL_LINKCHG_ST 0x00000400
353#define WOL_CLK_SWITCH_EN 0x00008000
354#define WOL_PT0_EN 0x00010000
355#define WOL_PT1_EN 0x00020000
356#define WOL_PT2_EN 0x00040000
357#define WOL_PT3_EN 0x00080000
358#define WOL_PT4_EN 0x00100000
359#define WOL_PT5_EN 0x00200000
360#define WOL_PT6_EN 0x00400000
361/* WOL Length ( 2 DWORD ) */
362#define REG_WOL_PATTERN_LEN 0x14a4
363#define WOL_PT_LEN_MASK 0x7f
364#define WOL_PT0_LEN_SHIFT 0
365#define WOL_PT1_LEN_SHIFT 8
366#define WOL_PT2_LEN_SHIFT 16
367#define WOL_PT3_LEN_SHIFT 24
368#define WOL_PT4_LEN_SHIFT 0
369#define WOL_PT5_LEN_SHIFT 8
370#define WOL_PT6_LEN_SHIFT 16
371
372/* Internal SRAM Partition Register */
373#define REG_SRAM_TRD_ADDR 0x1518
374#define REG_SRAM_TRD_LEN 0x151C
375#define REG_SRAM_RXF_ADDR 0x1520
376#define REG_SRAM_RXF_LEN 0x1524
377#define REG_SRAM_TXF_ADDR 0x1528
378#define REG_SRAM_TXF_LEN 0x152C
379#define REG_SRAM_TCPH_ADDR 0x1530
380#define REG_SRAM_PKTH_ADDR 0x1532
381
382/* Load Ptr Register */
383#define REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */
384
385/*
386 * addresses of all descriptors, as well as the following descriptor
387 * control register, which triggers each function block to load the head
388 * pointer to prepare for the operation. This bit is then self-cleared
389 * after one cycle.
390 */
391
392/* Descriptor Control register */
393#define REG_RXF3_BASE_ADDR_HI 0x153C
394#define REG_DESC_BASE_ADDR_HI 0x1540
395#define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */
396#define REG_HOST_RXF0_PAGE0_LO 0x1544
397#define REG_HOST_RXF0_PAGE1_LO 0x1548
398#define REG_TPD_BASE_ADDR_LO 0x154C
399#define REG_RXF1_BASE_ADDR_HI 0x1550
400#define REG_RXF2_BASE_ADDR_HI 0x1554
401#define REG_HOST_RXFPAGE_SIZE 0x1558
402#define REG_TPD_RING_SIZE 0x155C
403/* RSS about */
404#define REG_RSS_KEY0 0x14B0
405#define REG_RSS_KEY1 0x14B4
406#define REG_RSS_KEY2 0x14B8
407#define REG_RSS_KEY3 0x14BC
408#define REG_RSS_KEY4 0x14C0
409#define REG_RSS_KEY5 0x14C4
410#define REG_RSS_KEY6 0x14C8
411#define REG_RSS_KEY7 0x14CC
412#define REG_RSS_KEY8 0x14D0
413#define REG_RSS_KEY9 0x14D4
414#define REG_IDT_TABLE4 0x14E0
415#define REG_IDT_TABLE5 0x14E4
416#define REG_IDT_TABLE6 0x14E8
417#define REG_IDT_TABLE7 0x14EC
418#define REG_IDT_TABLE0 0x1560
419#define REG_IDT_TABLE1 0x1564
420#define REG_IDT_TABLE2 0x1568
421#define REG_IDT_TABLE3 0x156C
422#define REG_IDT_TABLE REG_IDT_TABLE0
423#define REG_RSS_HASH_VALUE 0x1570
424#define REG_RSS_HASH_FLAG 0x1574
425#define REG_BASE_CPU_NUMBER 0x157C
426
427
428/* TXQ Control Register */
429#define REG_TXQ_CTRL 0x1580
430#define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF
431#define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0
432#define TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */
433#define TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */
434#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
435#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
436
437/* Jumbo packet Threshold for task offload */
438#define REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */
439/* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */
440#define TX_TX_EARLY_TH_MASK 0x7ff
441#define TX_TX_EARLY_TH_SHIFT 0
442
443
444/* RXQ Control Register */
445#define REG_RXQ_CTRL 0x15A0
446#define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */
447#define RXQ_CTRL_PBA_ALIGN_64 1
448#define RXQ_CTRL_PBA_ALIGN_128 2
449#define RXQ_CTRL_PBA_ALIGN_256 3
450#define RXQ_CTRL_Q1_EN 0x10
451#define RXQ_CTRL_Q2_EN 0x20
452#define RXQ_CTRL_Q3_EN 0x40
453#define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80
454#define RXQ_CTRL_HASH_TLEN_SHIFT 8
455#define RXQ_CTRL_HASH_TLEN_MASK 0xFF
456#define RXQ_CTRL_HASH_TYPE_IPV4 0x10000
457#define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000
458#define RXQ_CTRL_HASH_TYPE_IPV6 0x40000
459#define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000
460#define RXQ_CTRL_RSS_MODE_DISABLE 0
461#define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000
462#define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000
463#define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000
464#define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000
465#define RXQ_CTRL_HASH_ENABLE 0x20000000
466#define RXQ_CTRL_CUT_THRU_EN 0x40000000
467#define RXQ_CTRL_EN 0x80000000
468
469/* Rx jumbo packet threshold and rrd retirement timer */
470#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
471/*
472 * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit.
473 * When the packet length greater than or equal to this value, RXQ
474 * shall start cut-through forwarding of the received packet.
475 */
476#define RXQ_JMBOSZ_TH_MASK 0x7ff
477#define RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/
478#define RXQ_JMBO_LKAH_MASK 0xf
479#define RXQ_JMBO_LKAH_SHIFT 11
480
481/* RXF flow control register */
482#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
483#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
484#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
485#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
486#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
487
488
489/* DMA Engine Control Register */
490#define REG_DMA_CTRL 0x15C0
491#define DMA_CTRL_DMAR_IN_ORDER 0x1
492#define DMA_CTRL_DMAR_ENH_ORDER 0x2
493#define DMA_CTRL_DMAR_OUT_ORDER 0x4
494#define DMA_CTRL_RCB_VALUE 0x8
495#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
496#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
497#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
498#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
499#define DMA_CTRL_DMAR_REQ_PRI 0x400
500#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F
501#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
502#define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF
503#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
504#define DMA_CTRL_TXCMB_EN 0x100000
505#define DMA_CTRL_RXCMB_EN 0x200000
506
507
508/* CMB/SMB Control Register */
509#define REG_SMB_STAT_TIMER 0x15C4
510#define REG_TRIG_RRD_THRESH 0x15CA
511#define REG_TRIG_TPD_THRESH 0x15C8
512#define REG_TRIG_TXTIMER 0x15CC
513#define REG_TRIG_RXTIMER 0x15CE
514
515/* HOST RXF Page 1,2,3 address */
516#define REG_HOST_RXF1_PAGE0_LO 0x15D0
517#define REG_HOST_RXF1_PAGE1_LO 0x15D4
518#define REG_HOST_RXF2_PAGE0_LO 0x15D8
519#define REG_HOST_RXF2_PAGE1_LO 0x15DC
520#define REG_HOST_RXF3_PAGE0_LO 0x15E0
521#define REG_HOST_RXF3_PAGE1_LO 0x15E4
522
523/* Mail box */
524#define REG_MB_RXF1_RADDR 0x15B4
525#define REG_MB_RXF2_RADDR 0x15B8
526#define REG_MB_RXF3_RADDR 0x15BC
527#define REG_MB_TPD_PROD_IDX 0x15F0
528
529/* RXF-Page 0-3 PageNo & Valid bit */
530#define REG_HOST_RXF0_PAGE0_VLD 0x15F4
531#define HOST_RXF_VALID 1
532#define HOST_RXF_PAGENO_SHIFT 1
533#define HOST_RXF_PAGENO_MASK 0x7F
534#define REG_HOST_RXF0_PAGE1_VLD 0x15F5
535#define REG_HOST_RXF1_PAGE0_VLD 0x15F6
536#define REG_HOST_RXF1_PAGE1_VLD 0x15F7
537#define REG_HOST_RXF2_PAGE0_VLD 0x15F8
538#define REG_HOST_RXF2_PAGE1_VLD 0x15F9
539#define REG_HOST_RXF3_PAGE0_VLD 0x15FA
540#define REG_HOST_RXF3_PAGE1_VLD 0x15FB
541
542/* Interrupt Status Register */
543#define REG_ISR 0x1600
544#define ISR_SMB 1
545#define ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */
546/*
547 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
548 * in Table 51 Selene Master Control Register (Offset 0x1400).
549 */
550#define ISR_MANUAL 4
551#define ISR_HW_RXF_OV 8 /* RXF overflow interrupt */
552#define ISR_HOST_RXF0_OV 0x10
553#define ISR_HOST_RXF1_OV 0x20
554#define ISR_HOST_RXF2_OV 0x40
555#define ISR_HOST_RXF3_OV 0x80
556#define ISR_TXF_UN 0x100
557#define ISR_RX0_PAGE_FULL 0x200
558#define ISR_DMAR_TO_RST 0x400
559#define ISR_DMAW_TO_RST 0x800
560#define ISR_GPHY 0x1000
561#define ISR_TX_CREDIT 0x2000
562#define ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */
563#define ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */
564#define ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */
565#define ISR_TX_DMA 0x40000
566#define ISR_RX_PKT_1 0x80000
567#define ISR_RX_PKT_2 0x100000
568#define ISR_RX_PKT_3 0x200000
569#define ISR_MAC_RX 0x400000
570#define ISR_MAC_TX 0x800000
571#define ISR_UR_DETECTED 0x1000000
572#define ISR_FERR_DETECTED 0x2000000
573#define ISR_NFERR_DETECTED 0x4000000
574#define ISR_CERR_DETECTED 0x8000000
575#define ISR_PHY_LINKDOWN 0x10000000
576#define ISR_DIS_INT 0x80000000
577
578
579/* Interrupt Mask Register */
580#define REG_IMR 0x1604
581
582
583#define IMR_NORMAL_MASK (\
584 ISR_SMB |\
585 ISR_TXF_UN |\
586 ISR_HW_RXF_OV |\
587 ISR_HOST_RXF0_OV|\
588 ISR_MANUAL |\
589 ISR_GPHY |\
590 ISR_GPHY_LPW |\
591 ISR_DMAR_TO_RST |\
592 ISR_DMAW_TO_RST |\
593 ISR_PHY_LINKDOWN|\
594 ISR_RX_PKT |\
595 ISR_TX_PKT)
596
597#define ISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT)
598#define ISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)
599
600#define REG_MAC_RX_STATUS_BIN 0x1700
601#define REG_MAC_RX_STATUS_END 0x175c
602#define REG_MAC_TX_STATUS_BIN 0x1760
603#define REG_MAC_TX_STATUS_END 0x17c0
604
605/* Hardware Offset Register */
606#define REG_HOST_RXF0_PAGEOFF 0x1800
607#define REG_TPD_CONS_IDX 0x1804
608#define REG_HOST_RXF1_PAGEOFF 0x1808
609#define REG_HOST_RXF2_PAGEOFF 0x180C
610#define REG_HOST_RXF3_PAGEOFF 0x1810
611
612/* RXF-Page 0-3 Offset DMA Address */
613#define REG_HOST_RXF0_MB0_LO 0x1820
614#define REG_HOST_RXF0_MB1_LO 0x1824
615#define REG_HOST_RXF1_MB0_LO 0x1828
616#define REG_HOST_RXF1_MB1_LO 0x182C
617#define REG_HOST_RXF2_MB0_LO 0x1830
618#define REG_HOST_RXF2_MB1_LO 0x1834
619#define REG_HOST_RXF3_MB0_LO 0x1838
620#define REG_HOST_RXF3_MB1_LO 0x183C
621
622/* Tpd CMB DMA Address */
623#define REG_HOST_TX_CMB_LO 0x1840
624#define REG_HOST_SMB_ADDR_LO 0x1844
625
626/* DEBUG ADDR */
627#define REG_DEBUG_DATA0 0x1900
628#define REG_DEBUG_DATA1 0x1904
629
630/***************************** MII definition ***************************************/
631/* PHY Common Register */
632#define MII_BMCR 0x00
633#define MII_BMSR 0x01
634#define MII_PHYSID1 0x02
635#define MII_PHYSID2 0x03
636#define MII_ADVERTISE 0x04
637#define MII_LPA 0x05
638#define MII_EXPANSION 0x06
639#define MII_AT001_CR 0x09
640#define MII_AT001_SR 0x0A
641#define MII_AT001_ESR 0x0F
642#define MII_AT001_PSCR 0x10
643#define MII_AT001_PSSR 0x11
644#define MII_INT_CTRL 0x12
645#define MII_INT_STATUS 0x13
646#define MII_SMARTSPEED 0x14
647#define MII_RERRCOUNTER 0x15
648#define MII_SREVISION 0x16
649#define MII_RESV1 0x17
650#define MII_LBRERROR 0x18
651#define MII_PHYADDR 0x19
652#define MII_RESV2 0x1a
653#define MII_TPISTATUS 0x1b
654#define MII_NCONFIG 0x1c
655
656#define MII_DBG_ADDR 0x1D
657#define MII_DBG_DATA 0x1E
658
659
660/* PHY Control Register */
661#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
662#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
663#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
664#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
665#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
666#define MII_CR_POWER_DOWN 0x0800 /* Power down */
667#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
668#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
669#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
670#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
671#define MII_CR_SPEED_MASK 0x2040
672#define MII_CR_SPEED_1000 0x0040
673#define MII_CR_SPEED_100 0x2000
674#define MII_CR_SPEED_10 0x0000
675
676
677/* PHY Status Register */
678#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
679#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
680#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
681#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
682#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
683#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
684#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
685#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
686#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
687#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
688#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
689#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
690#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
691#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
692#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
693
694/* Link partner ability register. */
695#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
696#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
697#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
698#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
699#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
700#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
701#define MII_LPA_PAUSE 0x0400 /* PAUSE */
702#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
703#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
704#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
705#define MII_LPA_NPAGE 0x8000 /* Next page bit */
706
707/* Autoneg Advertisement Register */
708#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
709#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
710#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
711#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
712#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
713#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
714#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
715#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
716#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
717#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
718#define MII_AR_SPEED_MASK 0x01E0
719#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
720
721/* 1000BASE-T Control Register */
722#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
723#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
724#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
725/* 0=DTE device */
726#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
727/* 0=Configure PHY as Slave */
728#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
729/* 0=Automatic Master/Slave config */
730#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
731#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
732#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
733#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
734#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
735#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
736#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
737
738/* 1000BASE-T Status Register */
739#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
740#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
741#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
742#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
743#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
744#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
745#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
746#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
747
748/* Extended Status Register */
749#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
750#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
751#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
752#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
753
754/* AT001 PHY Specific Control Register */
755#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
756#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
757#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
758#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
759#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
760 * 0=CLK125 toggling
761 */
762#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
763/* Manual MDI configuration */
764#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
765#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
766 * 100BASE-TX/10BASE-T:
767 * MDI Mode
768 */
769#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
770 * all speeds.
771 */
772#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080
773/* 1=Enable Extended 10BASE-T distance
774 * (Lower 10BASE-T RX Threshold)
775 * 0=Normal 10BASE-T RX Threshold */
776#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100
777/* 1=5-Bit interface in 100BASE-TX
778 * 0=MII interface in 100BASE-TX */
779#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
780#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
781#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
782#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
783#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
784#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
785/* AT001 PHY Specific Status Register */
786#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
787#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
788#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
789#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
790#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
791#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
792
793#endif /*_ATHL1E_HW_H_*/
diff --git a/drivers/net/atl1e/atl1e_main.c b/drivers/net/atl1e/atl1e_main.c
new file mode 100644
index 00000000000..367c7275063
--- /dev/null
+++ b/drivers/net/atl1e/atl1e_main.c
@@ -0,0 +1,2599 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "atl1e.h"
23
24#define DRV_VERSION "1.0.0.7-NAPI"
25
26char atl1e_driver_name[] = "ATL1E";
27char atl1e_driver_version[] = DRV_VERSION;
28#define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
29/*
30 * atl1e_pci_tbl - PCI Device ID Table
31 *
32 * Wildcard entries (PCI_ANY_ID) should come last
33 * Last entry must be all 0s
34 *
35 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
36 * Class, Class Mask, private data (not used) }
37 */
38static struct pci_device_id atl1e_pci_tbl[] = {
39 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1E)},
40 /* required last entry */
41 { 0 }
42};
43MODULE_DEVICE_TABLE(pci, atl1e_pci_tbl);
44
45MODULE_AUTHOR("Atheros Corporation, <xiong.huang@atheros.com>, Jie Yang <jie.yang@atheros.com>");
46MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
47MODULE_LICENSE("GPL");
48MODULE_VERSION(DRV_VERSION);
49
50static inline void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
51
52static const u16
53atl1e_rx_page_vld_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
54{
55 {REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD},
56 {REG_HOST_RXF1_PAGE0_VLD, REG_HOST_RXF1_PAGE1_VLD},
57 {REG_HOST_RXF2_PAGE0_VLD, REG_HOST_RXF2_PAGE1_VLD},
58 {REG_HOST_RXF3_PAGE0_VLD, REG_HOST_RXF3_PAGE1_VLD}
59};
60
61static const u16 atl1e_rx_page_hi_addr_regs[AT_MAX_RECEIVE_QUEUE] =
62{
63 REG_RXF0_BASE_ADDR_HI,
64 REG_RXF1_BASE_ADDR_HI,
65 REG_RXF2_BASE_ADDR_HI,
66 REG_RXF3_BASE_ADDR_HI
67};
68
69static const u16
70atl1e_rx_page_lo_addr_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
71{
72 {REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO},
73 {REG_HOST_RXF1_PAGE0_LO, REG_HOST_RXF1_PAGE1_LO},
74 {REG_HOST_RXF2_PAGE0_LO, REG_HOST_RXF2_PAGE1_LO},
75 {REG_HOST_RXF3_PAGE0_LO, REG_HOST_RXF3_PAGE1_LO}
76};
77
78static const u16
79atl1e_rx_page_write_offset_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
80{
81 {REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO},
82 {REG_HOST_RXF1_MB0_LO, REG_HOST_RXF1_MB1_LO},
83 {REG_HOST_RXF2_MB0_LO, REG_HOST_RXF2_MB1_LO},
84 {REG_HOST_RXF3_MB0_LO, REG_HOST_RXF3_MB1_LO}
85};
86
87static const u16 atl1e_pay_load_size[] = {
88 128, 256, 512, 1024, 2048, 4096,
89};
90
91/*
92 * atl1e_irq_enable - Enable default interrupt generation settings
93 * @adapter: board private structure
94 */
95static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
96{
97 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
98 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
99 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
100 AT_WRITE_FLUSH(&adapter->hw);
101 }
102}
103
104/*
105 * atl1e_irq_disable - Mask off interrupt generation on the NIC
106 * @adapter: board private structure
107 */
108static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
109{
110 atomic_inc(&adapter->irq_sem);
111 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
112 AT_WRITE_FLUSH(&adapter->hw);
113 synchronize_irq(adapter->pdev->irq);
114}
115
116/*
117 * atl1e_irq_reset - reset interrupt confiure on the NIC
118 * @adapter: board private structure
119 */
120static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
121{
122 atomic_set(&adapter->irq_sem, 0);
123 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
124 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
125 AT_WRITE_FLUSH(&adapter->hw);
126}
127
128/*
129 * atl1e_phy_config - Timer Call-back
130 * @data: pointer to netdev cast into an unsigned long
131 */
132static void atl1e_phy_config(unsigned long data)
133{
134 struct atl1e_adapter *adapter = (struct atl1e_adapter *) data;
135 struct atl1e_hw *hw = &adapter->hw;
136 unsigned long flags;
137
138 spin_lock_irqsave(&adapter->mdio_lock, flags);
139 atl1e_restart_autoneg(hw);
140 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
141}
142
143void atl1e_reinit_locked(struct atl1e_adapter *adapter)
144{
145
146 WARN_ON(in_interrupt());
147 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
148 msleep(1);
149 atl1e_down(adapter);
150 atl1e_up(adapter);
151 clear_bit(__AT_RESETTING, &adapter->flags);
152}
153
154static void atl1e_reset_task(struct work_struct *work)
155{
156 struct atl1e_adapter *adapter;
157 adapter = container_of(work, struct atl1e_adapter, reset_task);
158
159 atl1e_reinit_locked(adapter);
160}
161
162static int atl1e_check_link(struct atl1e_adapter *adapter)
163{
164 struct atl1e_hw *hw = &adapter->hw;
165 struct net_device *netdev = adapter->netdev;
166 struct pci_dev *pdev = adapter->pdev;
167 int err = 0;
168 u16 speed, duplex, phy_data;
169
170 /* MII_BMSR must read twise */
171 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
173 if ((phy_data & BMSR_LSTATUS) == 0) {
174 /* link down */
175 if (netif_carrier_ok(netdev)) { /* old link state: Up */
176 u32 value;
177 /* disable rx */
178 value = AT_READ_REG(hw, REG_MAC_CTRL);
179 value &= ~MAC_CTRL_RX_EN;
180 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
181 adapter->link_speed = SPEED_0;
182 netif_carrier_off(netdev);
183 netif_stop_queue(netdev);
184 }
185 } else {
186 /* Link Up */
187 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
188 if (unlikely(err))
189 return err;
190
191 /* link result is our setting */
192 if (adapter->link_speed != speed ||
193 adapter->link_duplex != duplex) {
194 adapter->link_speed = speed;
195 adapter->link_duplex = duplex;
196 atl1e_setup_mac_ctrl(adapter);
197 dev_info(&pdev->dev,
198 "%s: %s NIC Link is Up<%d Mbps %s>\n",
199 atl1e_driver_name, netdev->name,
200 adapter->link_speed,
201 adapter->link_duplex == FULL_DUPLEX ?
202 "Full Duplex" : "Half Duplex");
203 }
204
205 if (!netif_carrier_ok(netdev)) {
206 /* Link down -> Up */
207 netif_carrier_on(netdev);
208 netif_wake_queue(netdev);
209 }
210 }
211 return 0;
212}
213
214/*
215 * atl1e_link_chg_task - deal with link change event Out of interrupt context
216 * @netdev: network interface device structure
217 */
218static void atl1e_link_chg_task(struct work_struct *work)
219{
220 struct atl1e_adapter *adapter;
221 unsigned long flags;
222
223 adapter = container_of(work, struct atl1e_adapter, link_chg_task);
224 spin_lock_irqsave(&adapter->mdio_lock, flags);
225 atl1e_check_link(adapter);
226 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
227}
228
229static void atl1e_link_chg_event(struct atl1e_adapter *adapter)
230{
231 struct net_device *netdev = adapter->netdev;
232 struct pci_dev *pdev = adapter->pdev;
233 u16 phy_data = 0;
234 u16 link_up = 0;
235
236 spin_lock(&adapter->mdio_lock);
237 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
238 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
239 spin_unlock(&adapter->mdio_lock);
240 link_up = phy_data & BMSR_LSTATUS;
241 /* notify upper layer link down ASAP */
242 if (!link_up) {
243 if (netif_carrier_ok(netdev)) {
244 /* old link state: Up */
245 dev_info(&pdev->dev, "%s: %s NIC Link is Down\n",
246 atl1e_driver_name, netdev->name);
247 adapter->link_speed = SPEED_0;
248 netif_stop_queue(netdev);
249 }
250 }
251 schedule_work(&adapter->link_chg_task);
252}
253
254static void atl1e_del_timer(struct atl1e_adapter *adapter)
255{
256 del_timer_sync(&adapter->phy_config_timer);
257}
258
259static void atl1e_cancel_work(struct atl1e_adapter *adapter)
260{
261 cancel_work_sync(&adapter->reset_task);
262 cancel_work_sync(&adapter->link_chg_task);
263}
264
265/*
266 * atl1e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 */
269static void atl1e_tx_timeout(struct net_device *netdev)
270{
271 struct atl1e_adapter *adapter = netdev_priv(netdev);
272
273 /* Do the reset outside of interrupt context */
274 schedule_work(&adapter->reset_task);
275}
276
277/*
278 * atl1e_set_multi - Multicast and Promiscuous mode set
279 * @netdev: network interface device structure
280 *
281 * The set_multi entry point is called whenever the multicast address
282 * list or the network interface flags are updated. This routine is
283 * responsible for configuring the hardware for proper multicast,
284 * promiscuous mode, and all-multi behavior.
285 */
286static void atl1e_set_multi(struct net_device *netdev)
287{
288 struct atl1e_adapter *adapter = netdev_priv(netdev);
289 struct atl1e_hw *hw = &adapter->hw;
290 struct dev_mc_list *mc_ptr;
291 u32 mac_ctrl_data = 0;
292 u32 hash_value;
293
294 /* Check for Promiscuous and All Multicast modes */
295 mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
296
297 if (netdev->flags & IFF_PROMISC) {
298 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
299 } else if (netdev->flags & IFF_ALLMULTI) {
300 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
301 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
302 } else {
303 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
304 }
305
306 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
307
308 /* clear the old settings from the multicast hash table */
309 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
310 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
311
312 /* comoute mc addresses' hash value ,and put it into hash table */
313 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
314 hash_value = atl1e_hash_mc_addr(hw, mc_ptr->dmi_addr);
315 atl1e_hash_set(hw, hash_value);
316 }
317}
318
319static void atl1e_vlan_rx_register(struct net_device *netdev,
320 struct vlan_group *grp)
321{
322 struct atl1e_adapter *adapter = netdev_priv(netdev);
323 struct pci_dev *pdev = adapter->pdev;
324 u32 mac_ctrl_data = 0;
325
326 dev_dbg(&pdev->dev, "atl1e_vlan_rx_register\n");
327
328 atl1e_irq_disable(adapter);
329
330 adapter->vlgrp = grp;
331 mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
332
333 if (grp) {
334 /* enable VLAN tag insert/strip */
335 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
336 } else {
337 /* disable VLAN tag insert/strip */
338 mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
339 }
340
341 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
342 atl1e_irq_enable(adapter);
343}
344
345static void atl1e_restore_vlan(struct atl1e_adapter *adapter)
346{
347 struct pci_dev *pdev = adapter->pdev;
348
349 dev_dbg(&pdev->dev, "atl1e_restore_vlan !");
350 atl1e_vlan_rx_register(adapter->netdev, adapter->vlgrp);
351}
352/*
353 * atl1e_set_mac - Change the Ethernet Address of the NIC
354 * @netdev: network interface device structure
355 * @p: pointer to an address structure
356 *
357 * Returns 0 on success, negative on failure
358 */
359static int atl1e_set_mac_addr(struct net_device *netdev, void *p)
360{
361 struct atl1e_adapter *adapter = netdev_priv(netdev);
362 struct sockaddr *addr = p;
363
364 if (!is_valid_ether_addr(addr->sa_data))
365 return -EADDRNOTAVAIL;
366
367 if (netif_running(netdev))
368 return -EBUSY;
369
370 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
371 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
372
373 atl1e_hw_set_mac_addr(&adapter->hw);
374
375 return 0;
376}
377
378/*
379 * atl1e_change_mtu - Change the Maximum Transfer Unit
380 * @netdev: network interface device structure
381 * @new_mtu: new value for maximum frame size
382 *
383 * Returns 0 on success, negative on failure
384 */
385static int atl1e_change_mtu(struct net_device *netdev, int new_mtu)
386{
387 struct atl1e_adapter *adapter = netdev_priv(netdev);
388 int old_mtu = netdev->mtu;
389 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
390
391 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
392 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
393 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
394 return -EINVAL;
395 }
396 /* set MTU */
397 if (old_mtu != new_mtu && netif_running(netdev)) {
398 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
399 msleep(1);
400 netdev->mtu = new_mtu;
401 adapter->hw.max_frame_size = new_mtu;
402 adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
403 atl1e_down(adapter);
404 atl1e_up(adapter);
405 clear_bit(__AT_RESETTING, &adapter->flags);
406 }
407 return 0;
408}
409
410/*
411 * caller should hold mdio_lock
412 */
413static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
414{
415 struct atl1e_adapter *adapter = netdev_priv(netdev);
416 u16 result;
417
418 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
419 return result;
420}
421
422static void atl1e_mdio_write(struct net_device *netdev, int phy_id,
423 int reg_num, int val)
424{
425 struct atl1e_adapter *adapter = netdev_priv(netdev);
426
427 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
428}
429
430/*
431 * atl1e_mii_ioctl -
432 * @netdev:
433 * @ifreq:
434 * @cmd:
435 */
436static int atl1e_mii_ioctl(struct net_device *netdev,
437 struct ifreq *ifr, int cmd)
438{
439 struct atl1e_adapter *adapter = netdev_priv(netdev);
440 struct pci_dev *pdev = adapter->pdev;
441 struct mii_ioctl_data *data = if_mii(ifr);
442 unsigned long flags;
443 int retval = 0;
444
445 if (!netif_running(netdev))
446 return -EINVAL;
447
448 spin_lock_irqsave(&adapter->mdio_lock, flags);
449 switch (cmd) {
450 case SIOCGMIIPHY:
451 data->phy_id = 0;
452 break;
453
454 case SIOCGMIIREG:
455 if (!capable(CAP_NET_ADMIN)) {
456 retval = -EPERM;
457 goto out;
458 }
459 if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
460 &data->val_out)) {
461 retval = -EIO;
462 goto out;
463 }
464 break;
465
466 case SIOCSMIIREG:
467 if (!capable(CAP_NET_ADMIN)) {
468 retval = -EPERM;
469 goto out;
470 }
471 if (data->reg_num & ~(0x1F)) {
472 retval = -EFAULT;
473 goto out;
474 }
475
476 dev_dbg(&pdev->dev, "<atl1e_mii_ioctl> write %x %x",
477 data->reg_num, data->val_in);
478 if (atl1e_write_phy_reg(&adapter->hw,
479 data->reg_num, data->val_in)) {
480 retval = -EIO;
481 goto out;
482 }
483 break;
484
485 default:
486 retval = -EOPNOTSUPP;
487 break;
488 }
489out:
490 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
491 return retval;
492
493}
494
495/*
496 * atl1e_ioctl -
497 * @netdev:
498 * @ifreq:
499 * @cmd:
500 */
501static int atl1e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
502{
503 switch (cmd) {
504 case SIOCGMIIPHY:
505 case SIOCGMIIREG:
506 case SIOCSMIIREG:
507 return atl1e_mii_ioctl(netdev, ifr, cmd);
508 default:
509 return -EOPNOTSUPP;
510 }
511}
512
513static void atl1e_setup_pcicmd(struct pci_dev *pdev)
514{
515 u16 cmd;
516
517 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
518 cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
519 cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
520 pci_write_config_word(pdev, PCI_COMMAND, cmd);
521
522 /*
523 * some motherboards BIOS(PXE/EFI) driver may set PME
524 * while they transfer control to OS (Windows/Linux)
525 * so we should clear this bit before NIC work normally
526 */
527 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
528 msleep(1);
529}
530
531/*
532 * atl1e_alloc_queues - Allocate memory for all rings
533 * @adapter: board private structure to initialize
534 *
535 */
536static int __devinit atl1e_alloc_queues(struct atl1e_adapter *adapter)
537{
538 return 0;
539}
540
541/*
542 * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
543 * @adapter: board private structure to initialize
544 *
545 * atl1e_sw_init initializes the Adapter private data structure.
546 * Fields are initialized based on PCI device information and
547 * OS network device settings (MTU size).
548 */
549static int __devinit atl1e_sw_init(struct atl1e_adapter *adapter)
550{
551 struct atl1e_hw *hw = &adapter->hw;
552 struct pci_dev *pdev = adapter->pdev;
553 u32 phy_status_data = 0;
554
555 adapter->wol = 0;
556 adapter->link_speed = SPEED_0; /* hardware init */
557 adapter->link_duplex = FULL_DUPLEX;
558 adapter->num_rx_queues = 1;
559
560 /* PCI config space info */
561 hw->vendor_id = pdev->vendor;
562 hw->device_id = pdev->device;
563 hw->subsystem_vendor_id = pdev->subsystem_vendor;
564 hw->subsystem_id = pdev->subsystem_device;
565
566 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
567 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
568
569 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
570 /* nic type */
571 if (hw->revision_id >= 0xF0) {
572 hw->nic_type = athr_l2e_revB;
573 } else {
574 if (phy_status_data & PHY_STATUS_100M)
575 hw->nic_type = athr_l1e;
576 else
577 hw->nic_type = athr_l2e_revA;
578 }
579
580 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
581
582 if (phy_status_data & PHY_STATUS_EMI_CA)
583 hw->emi_ca = true;
584 else
585 hw->emi_ca = false;
586
587 hw->phy_configured = false;
588 hw->preamble_len = 7;
589 hw->max_frame_size = adapter->netdev->mtu;
590 hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
591 VLAN_HLEN + ETH_FCS_LEN + 7) >> 3;
592
593 hw->rrs_type = atl1e_rrs_disable;
594 hw->indirect_tab = 0;
595 hw->base_cpu = 0;
596
597 /* need confirm */
598
599 hw->ict = 50000; /* 100ms */
600 hw->smb_timer = 200000; /* 200ms */
601 hw->tpd_burst = 5;
602 hw->rrd_thresh = 1;
603 hw->tpd_thresh = adapter->tx_ring.count / 2;
604 hw->rx_count_down = 4; /* 2us resolution */
605 hw->tx_count_down = hw->imt * 4 / 3;
606 hw->dmar_block = atl1e_dma_req_1024;
607 hw->dmaw_block = atl1e_dma_req_1024;
608 hw->dmar_dly_cnt = 15;
609 hw->dmaw_dly_cnt = 4;
610
611 if (atl1e_alloc_queues(adapter)) {
612 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
613 return -ENOMEM;
614 }
615
616 atomic_set(&adapter->irq_sem, 1);
617 spin_lock_init(&adapter->mdio_lock);
618 spin_lock_init(&adapter->tx_lock);
619
620 set_bit(__AT_DOWN, &adapter->flags);
621
622 return 0;
623}
624
625/*
626 * atl1e_clean_tx_ring - Free Tx-skb
627 * @adapter: board private structure
628 */
629static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
630{
631 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
632 &adapter->tx_ring;
633 struct atl1e_tx_buffer *tx_buffer = NULL;
634 struct pci_dev *pdev = adapter->pdev;
635 u16 index, ring_count;
636
637 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
638 return;
639
640 ring_count = tx_ring->count;
641 /* first unmmap dma */
642 for (index = 0; index < ring_count; index++) {
643 tx_buffer = &tx_ring->tx_buffer[index];
644 if (tx_buffer->dma) {
645 pci_unmap_page(pdev, tx_buffer->dma,
646 tx_buffer->length, PCI_DMA_TODEVICE);
647 tx_buffer->dma = 0;
648 }
649 }
650 /* second free skb */
651 for (index = 0; index < ring_count; index++) {
652 tx_buffer = &tx_ring->tx_buffer[index];
653 if (tx_buffer->skb) {
654 dev_kfree_skb_any(tx_buffer->skb);
655 tx_buffer->skb = NULL;
656 }
657 }
658 /* Zero out Tx-buffers */
659 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
660 ring_count);
661 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
662 ring_count);
663}
664
665/*
666 * atl1e_clean_rx_ring - Free rx-reservation skbs
667 * @adapter: board private structure
668 */
669static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
670{
671 struct atl1e_rx_ring *rx_ring =
672 (struct atl1e_rx_ring *)&adapter->rx_ring;
673 struct atl1e_rx_page_desc *rx_page_desc = rx_ring->rx_page_desc;
674 u16 i, j;
675
676
677 if (adapter->ring_vir_addr == NULL)
678 return;
679 /* Zero out the descriptor ring */
680 for (i = 0; i < adapter->num_rx_queues; i++) {
681 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
682 if (rx_page_desc[i].rx_page[j].addr != NULL) {
683 memset(rx_page_desc[i].rx_page[j].addr, 0,
684 rx_ring->real_page_size);
685 }
686 }
687 }
688}
689
690static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
691{
692 *ring_size = ((u32)(adapter->tx_ring.count *
693 sizeof(struct atl1e_tpd_desc) + 7
694 /* tx ring, qword align */
695 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE *
696 adapter->num_rx_queues + 31
697 /* rx ring, 32 bytes align */
698 + (1 + AT_PAGE_NUM_PER_QUEUE * adapter->num_rx_queues) *
699 sizeof(u32) + 3));
700 /* tx, rx cmd, dword align */
701}
702
703static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
704{
705 struct atl1e_tx_ring *tx_ring = NULL;
706 struct atl1e_rx_ring *rx_ring = NULL;
707
708 tx_ring = &adapter->tx_ring;
709 rx_ring = &adapter->rx_ring;
710
711 rx_ring->real_page_size = adapter->rx_ring.page_size
712 + adapter->hw.max_frame_size
713 + ETH_HLEN + VLAN_HLEN
714 + ETH_FCS_LEN;
715 rx_ring->real_page_size = roundup(rx_ring->real_page_size, 32);
716 atl1e_cal_ring_size(adapter, &adapter->ring_size);
717
718 adapter->ring_vir_addr = NULL;
719 adapter->rx_ring.desc = NULL;
720 rwlock_init(&adapter->tx_ring.tx_lock);
721
722 return;
723}
724
725/*
726 * Read / Write Ptr Initialize:
727 */
728static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
729{
730 struct atl1e_tx_ring *tx_ring = NULL;
731 struct atl1e_rx_ring *rx_ring = NULL;
732 struct atl1e_rx_page_desc *rx_page_desc = NULL;
733 int i, j;
734
735 tx_ring = &adapter->tx_ring;
736 rx_ring = &adapter->rx_ring;
737 rx_page_desc = rx_ring->rx_page_desc;
738
739 tx_ring->next_to_use = 0;
740 atomic_set(&tx_ring->next_to_clean, 0);
741
742 for (i = 0; i < adapter->num_rx_queues; i++) {
743 rx_page_desc[i].rx_using = 0;
744 rx_page_desc[i].rx_nxseq = 0;
745 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
746 *rx_page_desc[i].rx_page[j].write_offset_addr = 0;
747 rx_page_desc[i].rx_page[j].read_offset = 0;
748 }
749 }
750}
751
752/*
753 * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
754 * @adapter: board private structure
755 *
756 * Free all transmit software resources
757 */
758static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
759{
760 struct pci_dev *pdev = adapter->pdev;
761
762 atl1e_clean_tx_ring(adapter);
763 atl1e_clean_rx_ring(adapter);
764
765 if (adapter->ring_vir_addr) {
766 pci_free_consistent(pdev, adapter->ring_size,
767 adapter->ring_vir_addr, adapter->ring_dma);
768 adapter->ring_vir_addr = NULL;
769 }
770
771 if (adapter->tx_ring.tx_buffer) {
772 kfree(adapter->tx_ring.tx_buffer);
773 adapter->tx_ring.tx_buffer = NULL;
774 }
775}
776
777/*
778 * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
779 * @adapter: board private structure
780 *
781 * Return 0 on success, negative on failure
782 */
783static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
784{
785 struct pci_dev *pdev = adapter->pdev;
786 struct atl1e_tx_ring *tx_ring;
787 struct atl1e_rx_ring *rx_ring;
788 struct atl1e_rx_page_desc *rx_page_desc;
789 int size, i, j;
790 u32 offset = 0;
791 int err = 0;
792
793 if (adapter->ring_vir_addr != NULL)
794 return 0; /* alloced already */
795
796 tx_ring = &adapter->tx_ring;
797 rx_ring = &adapter->rx_ring;
798
799 /* real ring DMA buffer */
800
801 size = adapter->ring_size;
802 adapter->ring_vir_addr = pci_alloc_consistent(pdev,
803 adapter->ring_size, &adapter->ring_dma);
804
805 if (adapter->ring_vir_addr == NULL) {
806 dev_err(&pdev->dev, "pci_alloc_consistent failed, "
807 "size = D%d", size);
808 return -ENOMEM;
809 }
810
811 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
812
813 rx_page_desc = rx_ring->rx_page_desc;
814
815 /* Init TPD Ring */
816 tx_ring->dma = roundup(adapter->ring_dma, 8);
817 offset = tx_ring->dma - adapter->ring_dma;
818 tx_ring->desc = (struct atl1e_tpd_desc *)
819 (adapter->ring_vir_addr + offset);
820 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
821 tx_ring->tx_buffer = kzalloc(size, GFP_KERNEL);
822 if (tx_ring->tx_buffer == NULL) {
823 dev_err(&pdev->dev, "kzalloc failed , size = D%d", size);
824 err = -ENOMEM;
825 goto failed;
826 }
827
828 /* Init RXF-Pages */
829 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
830 offset = roundup(offset, 32);
831
832 for (i = 0; i < adapter->num_rx_queues; i++) {
833 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
834 rx_page_desc[i].rx_page[j].dma =
835 adapter->ring_dma + offset;
836 rx_page_desc[i].rx_page[j].addr =
837 adapter->ring_vir_addr + offset;
838 offset += rx_ring->real_page_size;
839 }
840 }
841
842 /* Init CMB dma address */
843 tx_ring->cmb_dma = adapter->ring_dma + offset;
844 tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset);
845 offset += sizeof(u32);
846
847 for (i = 0; i < adapter->num_rx_queues; i++) {
848 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
849 rx_page_desc[i].rx_page[j].write_offset_dma =
850 adapter->ring_dma + offset;
851 rx_page_desc[i].rx_page[j].write_offset_addr =
852 adapter->ring_vir_addr + offset;
853 offset += sizeof(u32);
854 }
855 }
856
857 if (unlikely(offset > adapter->ring_size)) {
858 dev_err(&pdev->dev, "offset(%d) > ring size(%d) !!\n",
859 offset, adapter->ring_size);
860 err = -1;
861 goto failed;
862 }
863
864 return 0;
865failed:
866 if (adapter->ring_vir_addr != NULL) {
867 pci_free_consistent(pdev, adapter->ring_size,
868 adapter->ring_vir_addr, adapter->ring_dma);
869 adapter->ring_vir_addr = NULL;
870 }
871 return err;
872}
873
874static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
875{
876
877 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
878 struct atl1e_rx_ring *rx_ring =
879 (struct atl1e_rx_ring *)&adapter->rx_ring;
880 struct atl1e_tx_ring *tx_ring =
881 (struct atl1e_tx_ring *)&adapter->tx_ring;
882 struct atl1e_rx_page_desc *rx_page_desc = NULL;
883 int i, j;
884
885 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
886 (u32)((adapter->ring_dma & AT_DMA_HI_ADDR_MASK) >> 32));
887 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
888 (u32)((tx_ring->dma) & AT_DMA_LO_ADDR_MASK));
889 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
890 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
891 (u32)((tx_ring->cmb_dma) & AT_DMA_LO_ADDR_MASK));
892
893 rx_page_desc = rx_ring->rx_page_desc;
894 /* RXF Page Physical address / Page Length */
895 for (i = 0; i < AT_MAX_RECEIVE_QUEUE; i++) {
896 AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
897 (u32)((adapter->ring_dma &
898 AT_DMA_HI_ADDR_MASK) >> 32));
899 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
900 u32 page_phy_addr;
901 u32 offset_phy_addr;
902
903 page_phy_addr = rx_page_desc[i].rx_page[j].dma;
904 offset_phy_addr =
905 rx_page_desc[i].rx_page[j].write_offset_dma;
906
907 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
908 page_phy_addr & AT_DMA_LO_ADDR_MASK);
909 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
910 offset_phy_addr & AT_DMA_LO_ADDR_MASK);
911 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
912 }
913 }
914 /* Page Length */
915 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
916 /* Load all of base address above */
917 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
918
919 return;
920}
921
922static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
923{
924 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
925 u32 dev_ctrl_data = 0;
926 u32 max_pay_load = 0;
927 u32 jumbo_thresh = 0;
928 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
929
930 /* configure TXQ param */
931 if (hw->nic_type != athr_l2e_revB) {
932 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
933 if (hw->max_frame_size <= 1500) {
934 jumbo_thresh = hw->max_frame_size + extra_size;
935 } else if (hw->max_frame_size < 6*1024) {
936 jumbo_thresh =
937 (hw->max_frame_size + extra_size) * 2 / 3;
938 } else {
939 jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
940 }
941 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
942 }
943
944 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
945
946 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
947 DEVICE_CTRL_MAX_PAYLOAD_MASK;
948
949 hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
950
951 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
952 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
953 hw->dmar_block = min(max_pay_load, hw->dmar_block);
954
955 if (hw->nic_type != athr_l2e_revB)
956 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
957 atl1e_pay_load_size[hw->dmar_block]);
958 /* enable TXQ */
959 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
960 (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
961 << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
962 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
963 return;
964}
965
966static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
967{
968 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
969 u32 rxf_len = 0;
970 u32 rxf_low = 0;
971 u32 rxf_high = 0;
972 u32 rxf_thresh_data = 0;
973 u32 rxq_ctrl_data = 0;
974
975 if (hw->nic_type != athr_l2e_revB) {
976 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
977 (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
978 RXQ_JMBOSZ_TH_SHIFT |
979 (1 & RXQ_JMBO_LKAH_MASK) <<
980 RXQ_JMBO_LKAH_SHIFT));
981
982 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
983 rxf_high = rxf_len * 4 / 5;
984 rxf_low = rxf_len / 5;
985 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
986 << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
987 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
988 << RXQ_RXF_PAUSE_TH_LO_SHIFT);
989
990 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
991 }
992
993 /* RRS */
994 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
995 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
996
997 if (hw->rrs_type & atl1e_rrs_ipv4)
998 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4;
999
1000 if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
1001 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4_TCP;
1002
1003 if (hw->rrs_type & atl1e_rrs_ipv6)
1004 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6;
1005
1006 if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
1007 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6_TCP;
1008
1009 if (hw->rrs_type != atl1e_rrs_disable)
1010 rxq_ctrl_data |=
1011 (RXQ_CTRL_HASH_ENABLE | RXQ_CTRL_RSS_MODE_MQUESINT);
1012
1013 rxq_ctrl_data |= RXQ_CTRL_IPV6_XSUM_VERIFY_EN | RXQ_CTRL_PBA_ALIGN_32 |
1014 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
1015
1016 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1017 return;
1018}
1019
1020static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
1021{
1022 struct atl1e_hw *hw = &adapter->hw;
1023 u32 dma_ctrl_data = 0;
1024
1025 dma_ctrl_data = DMA_CTRL_RXCMB_EN;
1026 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1027 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1028 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1029 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1030 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
1031 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1032 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1033 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1034 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1035
1036 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1037 return;
1038}
1039
1040static inline void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
1041{
1042 u32 value;
1043 struct atl1e_hw *hw = &adapter->hw;
1044 struct net_device *netdev = adapter->netdev;
1045
1046 /* Config MAC CTRL Register */
1047 value = MAC_CTRL_TX_EN |
1048 MAC_CTRL_RX_EN ;
1049
1050 if (FULL_DUPLEX == adapter->link_duplex)
1051 value |= MAC_CTRL_DUPLX;
1052
1053 value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
1054 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1055 MAC_CTRL_SPEED_SHIFT);
1056 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1057
1058 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1059 value |= (((u32)adapter->hw.preamble_len &
1060 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1061
1062 if (adapter->vlgrp)
1063 value |= MAC_CTRL_RMV_VLAN;
1064
1065 value |= MAC_CTRL_BC_EN;
1066 if (netdev->flags & IFF_PROMISC)
1067 value |= MAC_CTRL_PROMIS_EN;
1068 if (netdev->flags & IFF_ALLMULTI)
1069 value |= MAC_CTRL_MC_ALL_EN;
1070
1071 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
1072}
1073
1074/*
1075 * atl1e_configure - Configure Transmit&Receive Unit after Reset
1076 * @adapter: board private structure
1077 *
1078 * Configure the Tx /Rx unit of the MAC after a reset.
1079 */
1080static int atl1e_configure(struct atl1e_adapter *adapter)
1081{
1082 struct atl1e_hw *hw = &adapter->hw;
1083 struct pci_dev *pdev = adapter->pdev;
1084
1085 u32 intr_status_data = 0;
1086
1087 /* clear interrupt status */
1088 AT_WRITE_REG(hw, REG_ISR, ~0);
1089
1090 /* 1. set MAC Address */
1091 atl1e_hw_set_mac_addr(hw);
1092
1093 /* 2. Init the Multicast HASH table done by set_muti */
1094
1095 /* 3. Clear any WOL status */
1096 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1097
1098 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
1099 * TPD Ring/SMB/RXF0 Page CMBs, they use the same
1100 * High 32bits memory */
1101 atl1e_configure_des_ring(adapter);
1102
1103 /* 5. set Interrupt Moderator Timer */
1104 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
1105 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
1106 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
1107 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
1108
1109 /* 6. rx/tx threshold to trig interrupt */
1110 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
1111 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
1112 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
1113 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
1114
1115 /* 7. set Interrupt Clear Timer */
1116 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
1117
1118 /* 8. set MTU */
1119 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1120 VLAN_HLEN + ETH_FCS_LEN);
1121
1122 /* 9. config TXQ early tx threshold */
1123 atl1e_configure_tx(adapter);
1124
1125 /* 10. config RXQ */
1126 atl1e_configure_rx(adapter);
1127
1128 /* 11. config DMA Engine */
1129 atl1e_configure_dma(adapter);
1130
1131 /* 12. smb timer to trig interrupt */
1132 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
1133
1134 intr_status_data = AT_READ_REG(hw, REG_ISR);
1135 if (unlikely((intr_status_data & ISR_PHY_LINKDOWN) != 0)) {
1136 dev_err(&pdev->dev, "atl1e_configure failed,"
1137 "PCIE phy link down\n");
1138 return -1;
1139 }
1140
1141 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
1142 return 0;
1143}
1144
1145/*
1146 * atl1e_get_stats - Get System Network Statistics
1147 * @netdev: network interface device structure
1148 *
1149 * Returns the address of the device statistics structure.
1150 * The statistics are actually updated from the timer callback.
1151 */
1152static struct net_device_stats *atl1e_get_stats(struct net_device *netdev)
1153{
1154 struct atl1e_adapter *adapter = netdev_priv(netdev);
1155 struct atl1e_hw_stats *hw_stats = &adapter->hw_stats;
1156 struct net_device_stats *net_stats = &adapter->net_stats;
1157
1158 net_stats->rx_packets = hw_stats->rx_ok;
1159 net_stats->tx_packets = hw_stats->tx_ok;
1160 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1161 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1162 net_stats->multicast = hw_stats->rx_mcast;
1163 net_stats->collisions = hw_stats->tx_1_col +
1164 hw_stats->tx_2_col * 2 +
1165 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1166
1167 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1168 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1169 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1170 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1171 net_stats->rx_length_errors = hw_stats->rx_len_err;
1172 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1173 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1174 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1175
1176 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1177
1178 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1179 hw_stats->tx_underrun + hw_stats->tx_trunc;
1180 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1181 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1182 net_stats->tx_window_errors = hw_stats->tx_late_col;
1183
1184 return &adapter->net_stats;
1185}
1186
1187static void atl1e_update_hw_stats(struct atl1e_adapter *adapter)
1188{
1189 u16 hw_reg_addr = 0;
1190 unsigned long *stats_item = NULL;
1191
1192 /* update rx status */
1193 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1194 stats_item = &adapter->hw_stats.rx_ok;
1195 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1196 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1197 stats_item++;
1198 hw_reg_addr += 4;
1199 }
1200 /* update tx status */
1201 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1202 stats_item = &adapter->hw_stats.tx_ok;
1203 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1204 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1205 stats_item++;
1206 hw_reg_addr += 4;
1207 }
1208}
1209
1210static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
1211{
1212 u16 phy_data;
1213
1214 spin_lock(&adapter->mdio_lock);
1215 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
1216 spin_unlock(&adapter->mdio_lock);
1217}
1218
1219static bool atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
1220{
1221 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
1222 &adapter->tx_ring;
1223 struct atl1e_tx_buffer *tx_buffer = NULL;
1224 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
1225 u16 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1226
1227 while (next_to_clean != hw_next_to_clean) {
1228 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
1229 if (tx_buffer->dma) {
1230 pci_unmap_page(adapter->pdev, tx_buffer->dma,
1231 tx_buffer->length, PCI_DMA_TODEVICE);
1232 tx_buffer->dma = 0;
1233 }
1234
1235 if (tx_buffer->skb) {
1236 dev_kfree_skb_irq(tx_buffer->skb);
1237 tx_buffer->skb = NULL;
1238 }
1239
1240 if (++next_to_clean == tx_ring->count)
1241 next_to_clean = 0;
1242 }
1243
1244 atomic_set(&tx_ring->next_to_clean, next_to_clean);
1245
1246 if (netif_queue_stopped(adapter->netdev) &&
1247 netif_carrier_ok(adapter->netdev)) {
1248 netif_wake_queue(adapter->netdev);
1249 }
1250
1251 return true;
1252}
1253
1254/*
1255 * atl1e_intr - Interrupt Handler
1256 * @irq: interrupt number
1257 * @data: pointer to a network interface device structure
1258 * @pt_regs: CPU registers structure
1259 */
1260static irqreturn_t atl1e_intr(int irq, void *data)
1261{
1262 struct net_device *netdev = data;
1263 struct atl1e_adapter *adapter = netdev_priv(netdev);
1264 struct pci_dev *pdev = adapter->pdev;
1265 struct atl1e_hw *hw = &adapter->hw;
1266 int max_ints = AT_MAX_INT_WORK;
1267 int handled = IRQ_NONE;
1268 u32 status;
1269
1270 do {
1271 status = AT_READ_REG(hw, REG_ISR);
1272 if ((status & IMR_NORMAL_MASK) == 0 ||
1273 (status & ISR_DIS_INT) != 0) {
1274 if (max_ints != AT_MAX_INT_WORK)
1275 handled = IRQ_HANDLED;
1276 break;
1277 }
1278 /* link event */
1279 if (status & ISR_GPHY)
1280 atl1e_clear_phy_int(adapter);
1281 /* Ack ISR */
1282 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1283
1284 handled = IRQ_HANDLED;
1285 /* check if PCIE PHY Link down */
1286 if (status & ISR_PHY_LINKDOWN) {
1287 dev_err(&pdev->dev,
1288 "pcie phy linkdown %x\n", status);
1289 if (netif_running(adapter->netdev)) {
1290 /* reset MAC */
1291 atl1e_irq_reset(adapter);
1292 schedule_work(&adapter->reset_task);
1293 break;
1294 }
1295 }
1296
1297 /* check if DMA read/write error */
1298 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
1299 dev_err(&pdev->dev,
1300 "PCIE DMA RW error (status = 0x%x)\n",
1301 status);
1302 atl1e_irq_reset(adapter);
1303 schedule_work(&adapter->reset_task);
1304 break;
1305 }
1306
1307 if (status & ISR_SMB)
1308 atl1e_update_hw_stats(adapter);
1309
1310 /* link event */
1311 if (status & (ISR_GPHY | ISR_MANUAL)) {
1312 adapter->net_stats.tx_carrier_errors++;
1313 atl1e_link_chg_event(adapter);
1314 break;
1315 }
1316
1317 /* transmit event */
1318 if (status & ISR_TX_EVENT)
1319 atl1e_clean_tx_irq(adapter);
1320
1321 if (status & ISR_RX_EVENT) {
1322 /*
1323 * disable rx interrupts, without
1324 * the synchronize_irq bit
1325 */
1326 AT_WRITE_REG(hw, REG_IMR,
1327 IMR_NORMAL_MASK & ~ISR_RX_EVENT);
1328 AT_WRITE_FLUSH(hw);
1329 if (likely(netif_rx_schedule_prep(netdev,
1330 &adapter->napi)))
1331 __netif_rx_schedule(netdev, &adapter->napi);
1332 }
1333 } while (--max_ints > 0);
1334 /* re-enable Interrupt*/
1335 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1336
1337 return handled;
1338}
1339
1340static inline void atl1e_rx_checksum(struct atl1e_adapter *adapter,
1341 struct sk_buff *skb, struct atl1e_recv_ret_status *prrs)
1342{
1343 u8 *packet = (u8 *)(prrs + 1);
1344 struct iphdr *iph;
1345 u16 head_len = ETH_HLEN;
1346 u16 pkt_flags;
1347 u16 err_flags;
1348
1349 skb->ip_summed = CHECKSUM_NONE;
1350 pkt_flags = prrs->pkt_flag;
1351 err_flags = prrs->err_flag;
1352 if (((pkt_flags & RRS_IS_IPV4) || (pkt_flags & RRS_IS_IPV6)) &&
1353 ((pkt_flags & RRS_IS_TCP) || (pkt_flags & RRS_IS_UDP))) {
1354 if (pkt_flags & RRS_IS_IPV4) {
1355 if (pkt_flags & RRS_IS_802_3)
1356 head_len += 8;
1357 iph = (struct iphdr *) (packet + head_len);
1358 if (iph->frag_off != 0 && !(pkt_flags & RRS_IS_IP_DF))
1359 goto hw_xsum;
1360 }
1361 if (!(err_flags & (RRS_ERR_IP_CSUM | RRS_ERR_L4_CSUM))) {
1362 skb->ip_summed = CHECKSUM_UNNECESSARY;
1363 return;
1364 }
1365 }
1366
1367hw_xsum :
1368 return;
1369}
1370
1371static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter,
1372 u8 que)
1373{
1374 struct atl1e_rx_page_desc *rx_page_desc =
1375 (struct atl1e_rx_page_desc *) adapter->rx_ring.rx_page_desc;
1376 u8 rx_using = rx_page_desc[que].rx_using;
1377
1378 return (struct atl1e_rx_page *)&(rx_page_desc[que].rx_page[rx_using]);
1379}
1380
1381static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que,
1382 int *work_done, int work_to_do)
1383{
1384 struct pci_dev *pdev = adapter->pdev;
1385 struct net_device *netdev = adapter->netdev;
1386 struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *)
1387 &adapter->rx_ring;
1388 struct atl1e_rx_page_desc *rx_page_desc =
1389 (struct atl1e_rx_page_desc *) rx_ring->rx_page_desc;
1390 struct sk_buff *skb = NULL;
1391 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter, que);
1392 u32 packet_size, write_offset;
1393 struct atl1e_recv_ret_status *prrs;
1394
1395 write_offset = *(rx_page->write_offset_addr);
1396 if (likely(rx_page->read_offset < write_offset)) {
1397 do {
1398 if (*work_done >= work_to_do)
1399 break;
1400 (*work_done)++;
1401 /* get new packet's rrs */
1402 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
1403 rx_page->read_offset);
1404 /* check sequence number */
1405 if (prrs->seq_num != rx_page_desc[que].rx_nxseq) {
1406 dev_err(&pdev->dev,
1407 "rx sequence number"
1408 " error (rx=%d) (expect=%d)\n",
1409 prrs->seq_num,
1410 rx_page_desc[que].rx_nxseq);
1411 rx_page_desc[que].rx_nxseq++;
1412 /* just for debug use */
1413 AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
1414 (((u32)prrs->seq_num) << 16) |
1415 rx_page_desc[que].rx_nxseq);
1416 goto fatal_err;
1417 }
1418 rx_page_desc[que].rx_nxseq++;
1419
1420 /* error packet */
1421 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
1422 if (prrs->err_flag & (RRS_ERR_BAD_CRC |
1423 RRS_ERR_DRIBBLE | RRS_ERR_CODE |
1424 RRS_ERR_TRUNC)) {
1425 /* hardware error, discard this packet*/
1426 dev_err(&pdev->dev,
1427 "rx packet desc error %x\n",
1428 *((u32 *)prrs + 1));
1429 goto skip_pkt;
1430 }
1431 }
1432
1433 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1434 RRS_PKT_SIZE_MASK) - 4; /* CRC */
1435 skb = netdev_alloc_skb(netdev,
1436 packet_size + NET_IP_ALIGN);
1437 if (skb == NULL) {
1438 dev_warn(&pdev->dev, "%s: Memory squeeze,"
1439 "deferring packet.\n", netdev->name);
1440 goto skip_pkt;
1441 }
1442 skb_reserve(skb, NET_IP_ALIGN);
1443 skb->dev = netdev;
1444 memcpy(skb->data, (u8 *)(prrs + 1), packet_size);
1445 skb_put(skb, packet_size);
1446 skb->protocol = eth_type_trans(skb, netdev);
1447 atl1e_rx_checksum(adapter, skb, prrs);
1448
1449 if (unlikely(adapter->vlgrp &&
1450 (prrs->pkt_flag & RRS_IS_VLAN_TAG))) {
1451 u16 vlan_tag = (prrs->vtag >> 4) |
1452 ((prrs->vtag & 7) << 13) |
1453 ((prrs->vtag & 8) << 9);
1454 dev_dbg(&pdev->dev,
1455 "RXD VLAN TAG<RRD>=0x%04x\n",
1456 prrs->vtag);
1457 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
1458 vlan_tag);
1459 } else {
1460 netif_receive_skb(skb);
1461 }
1462
1463 netdev->last_rx = jiffies;
1464skip_pkt:
1465 /* skip current packet whether it's ok or not. */
1466 rx_page->read_offset +=
1467 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1468 RRS_PKT_SIZE_MASK) +
1469 sizeof(struct atl1e_recv_ret_status) + 31) &
1470 0xFFFFFFE0);
1471
1472 if (rx_page->read_offset >= rx_ring->page_size) {
1473 /* mark this page clean */
1474 u16 reg_addr;
1475 u8 rx_using;
1476
1477 rx_page->read_offset =
1478 *(rx_page->write_offset_addr) = 0;
1479 rx_using = rx_page_desc[que].rx_using;
1480 reg_addr =
1481 atl1e_rx_page_vld_regs[que][rx_using];
1482 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
1483 rx_page_desc[que].rx_using ^= 1;
1484 rx_page = atl1e_get_rx_page(adapter, que);
1485 }
1486 write_offset = *(rx_page->write_offset_addr);
1487 } while (rx_page->read_offset < write_offset);
1488 }
1489
1490 return;
1491
1492fatal_err:
1493 if (!test_bit(__AT_DOWN, &adapter->flags))
1494 schedule_work(&adapter->reset_task);
1495}
1496
1497/*
1498 * atl1e_clean - NAPI Rx polling callback
1499 * @adapter: board private structure
1500 */
1501static int atl1e_clean(struct napi_struct *napi, int budget)
1502{
1503 struct atl1e_adapter *adapter =
1504 container_of(napi, struct atl1e_adapter, napi);
1505 struct net_device *netdev = adapter->netdev;
1506 struct pci_dev *pdev = adapter->pdev;
1507 u32 imr_data;
1508 int work_done = 0;
1509
1510 /* Keep link state information with original netdev */
1511 if (!netif_carrier_ok(adapter->netdev))
1512 goto quit_polling;
1513
1514 atl1e_clean_rx_irq(adapter, 0, &work_done, budget);
1515
1516 /* If no Tx and not enough Rx work done, exit the polling mode */
1517 if (work_done < budget) {
1518quit_polling:
1519 netif_rx_complete(netdev, napi);
1520 imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
1521 AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
1522 /* test debug */
1523 if (test_bit(__AT_DOWN, &adapter->flags)) {
1524 atomic_dec(&adapter->irq_sem);
1525 dev_err(&pdev->dev,
1526 "atl1e_clean is called when AT_DOWN\n");
1527 }
1528 /* reenable RX intr */
1529 /*atl1e_irq_enable(adapter); */
1530
1531 }
1532 return work_done;
1533}
1534
1535#ifdef CONFIG_NET_POLL_CONTROLLER
1536
1537/*
1538 * Polling 'interrupt' - used by things like netconsole to send skbs
1539 * without having to re-enable interrupts. It's not called while
1540 * the interrupt routine is executing.
1541 */
1542static void atl1e_netpoll(struct net_device *netdev)
1543{
1544 struct atl1e_adapter *adapter = netdev_priv(netdev);
1545
1546 disable_irq(adapter->pdev->irq);
1547 atl1e_intr(adapter->pdev->irq, netdev);
1548 enable_irq(adapter->pdev->irq);
1549}
1550#endif
1551
1552static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
1553{
1554 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1555 u16 next_to_use = 0;
1556 u16 next_to_clean = 0;
1557
1558 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1559 next_to_use = tx_ring->next_to_use;
1560
1561 return (u16)(next_to_clean > next_to_use) ?
1562 (next_to_clean - next_to_use - 1) :
1563 (tx_ring->count + next_to_clean - next_to_use - 1);
1564}
1565
1566/*
1567 * get next usable tpd
1568 * Note: should call atl1e_tdp_avail to make sure
1569 * there is enough tpd to use
1570 */
1571static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
1572{
1573 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1574 u16 next_to_use = 0;
1575
1576 next_to_use = tx_ring->next_to_use;
1577 if (++tx_ring->next_to_use == tx_ring->count)
1578 tx_ring->next_to_use = 0;
1579
1580 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
1581 return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
1582}
1583
1584static struct atl1e_tx_buffer *
1585atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
1586{
1587 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1588
1589 return &tx_ring->tx_buffer[tpd - tx_ring->desc];
1590}
1591
1592/* Calculate the transmit packet descript needed*/
1593static u16 atl1e_cal_tdp_req(const struct sk_buff *skb)
1594{
1595 int i = 0;
1596 u16 tpd_req = 1;
1597 u16 fg_size = 0;
1598 u16 proto_hdr_len = 0;
1599
1600 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1601 fg_size = skb_shinfo(skb)->frags[i].size;
1602 tpd_req += ((fg_size + MAX_TX_BUF_LEN - 1) >> MAX_TX_BUF_SHIFT);
1603 }
1604
1605 if (skb_is_gso(skb)) {
1606 if (skb->protocol == ntohs(ETH_P_IP) ||
1607 (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) {
1608 proto_hdr_len = skb_transport_offset(skb) +
1609 tcp_hdrlen(skb);
1610 if (proto_hdr_len < skb_headlen(skb)) {
1611 tpd_req += ((skb_headlen(skb) - proto_hdr_len +
1612 MAX_TX_BUF_LEN - 1) >>
1613 MAX_TX_BUF_SHIFT);
1614 }
1615 }
1616
1617 }
1618 return tpd_req;
1619}
1620
1621static int atl1e_tso_csum(struct atl1e_adapter *adapter,
1622 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1623{
1624 struct pci_dev *pdev = adapter->pdev;
1625 u8 hdr_len;
1626 u32 real_len;
1627 unsigned short offload_type;
1628 int err;
1629
1630 if (skb_is_gso(skb)) {
1631 if (skb_header_cloned(skb)) {
1632 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1633 if (unlikely(err))
1634 return -1;
1635 }
1636 offload_type = skb_shinfo(skb)->gso_type;
1637
1638 if (offload_type & SKB_GSO_TCPV4) {
1639 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
1640 + ntohs(ip_hdr(skb)->tot_len));
1641
1642 if (real_len < skb->len)
1643 pskb_trim(skb, real_len);
1644
1645 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1646 if (unlikely(skb->len == hdr_len)) {
1647 /* only xsum need */
1648 dev_warn(&pdev->dev,
1649 "IPV4 tso with zero data??\n");
1650 goto check_sum;
1651 } else {
1652 ip_hdr(skb)->check = 0;
1653 ip_hdr(skb)->tot_len = 0;
1654 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
1655 ip_hdr(skb)->saddr,
1656 ip_hdr(skb)->daddr,
1657 0, IPPROTO_TCP, 0);
1658 tpd->word3 |= (ip_hdr(skb)->ihl &
1659 TDP_V4_IPHL_MASK) <<
1660 TPD_V4_IPHL_SHIFT;
1661 tpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
1662 TPD_TCPHDRLEN_MASK) <<
1663 TPD_TCPHDRLEN_SHIFT;
1664 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1665 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1666 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1667 }
1668 return 0;
1669 }
1670
1671 if (offload_type & SKB_GSO_TCPV6) {
1672 real_len = (((unsigned char *)ipv6_hdr(skb) - skb->data)
1673 + ntohs(ipv6_hdr(skb)->payload_len));
1674 if (real_len < skb->len)
1675 pskb_trim(skb, real_len);
1676
1677 /* check payload == 0 byte ? */
1678 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1679 if (unlikely(skb->len == hdr_len)) {
1680 /* only xsum need */
1681 dev_warn(&pdev->dev,
1682 "IPV6 tso with zero data??\n");
1683 goto check_sum;
1684 } else {
1685 tcp_hdr(skb)->check = ~csum_ipv6_magic(
1686 &ipv6_hdr(skb)->saddr,
1687 &ipv6_hdr(skb)->daddr,
1688 0, IPPROTO_TCP, 0);
1689 tpd->word3 |= 1 << TPD_IP_VERSION_SHIFT;
1690 hdr_len >>= 1;
1691 tpd->word3 |= (hdr_len & TPD_V6_IPHLLO_MASK) <<
1692 TPD_V6_IPHLLO_SHIFT;
1693 tpd->word3 |= ((hdr_len >> 3) &
1694 TPD_V6_IPHLHI_MASK) <<
1695 TPD_V6_IPHLHI_SHIFT;
1696 tpd->word3 |= (tcp_hdrlen(skb) >> 2 &
1697 TPD_TCPHDRLEN_MASK) <<
1698 TPD_TCPHDRLEN_SHIFT;
1699 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1700 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1701 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1702 }
1703 }
1704 return 0;
1705 }
1706
1707check_sum:
1708 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1709 u8 css, cso;
1710
1711 cso = skb_transport_offset(skb);
1712 if (unlikely(cso & 0x1)) {
1713 dev_err(&adapter->pdev->dev,
1714 "pay load offset should not ant event number\n");
1715 return -1;
1716 } else {
1717 css = cso + skb->csum_offset;
1718 tpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
1719 TPD_PLOADOFFSET_SHIFT;
1720 tpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
1721 TPD_CCSUMOFFSET_SHIFT;
1722 tpd->word3 |= 1 << TPD_CC_SEGMENT_EN_SHIFT;
1723 }
1724 }
1725
1726 return 0;
1727}
1728
1729static void atl1e_tx_map(struct atl1e_adapter *adapter,
1730 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1731{
1732 struct atl1e_tpd_desc *use_tpd = NULL;
1733 struct atl1e_tx_buffer *tx_buffer = NULL;
1734 u16 buf_len = skb->len - skb->data_len;
1735 u16 map_len = 0;
1736 u16 mapped_len = 0;
1737 u16 hdr_len = 0;
1738 u16 nr_frags;
1739 u16 f;
1740 int segment;
1741
1742 nr_frags = skb_shinfo(skb)->nr_frags;
1743 segment = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
1744 if (segment) {
1745 /* TSO */
1746 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1747 use_tpd = tpd;
1748
1749 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1750 tx_buffer->length = map_len;
1751 tx_buffer->dma = pci_map_single(adapter->pdev,
1752 skb->data, hdr_len, PCI_DMA_TODEVICE);
1753 mapped_len += map_len;
1754 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1755 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1756 ((cpu_to_le32(tx_buffer->length) &
1757 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1758 }
1759
1760 while (mapped_len < buf_len) {
1761 /* mapped_len == 0, means we should use the first tpd,
1762 which is given by caller */
1763 if (mapped_len == 0) {
1764 use_tpd = tpd;
1765 } else {
1766 use_tpd = atl1e_get_tpd(adapter);
1767 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1768 }
1769 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1770 tx_buffer->skb = NULL;
1771
1772 tx_buffer->length = map_len =
1773 ((buf_len - mapped_len) >= MAX_TX_BUF_LEN) ?
1774 MAX_TX_BUF_LEN : (buf_len - mapped_len);
1775 tx_buffer->dma =
1776 pci_map_single(adapter->pdev, skb->data + mapped_len,
1777 map_len, PCI_DMA_TODEVICE);
1778 mapped_len += map_len;
1779 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1780 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1781 ((cpu_to_le32(tx_buffer->length) &
1782 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1783 }
1784
1785 for (f = 0; f < nr_frags; f++) {
1786 struct skb_frag_struct *frag;
1787 u16 i;
1788 u16 seg_num;
1789
1790 frag = &skb_shinfo(skb)->frags[f];
1791 buf_len = frag->size;
1792
1793 seg_num = (buf_len + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1794 for (i = 0; i < seg_num; i++) {
1795 use_tpd = atl1e_get_tpd(adapter);
1796 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1797
1798 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1799 if (tx_buffer->skb)
1800 BUG();
1801
1802 tx_buffer->skb = NULL;
1803 tx_buffer->length =
1804 (buf_len > MAX_TX_BUF_LEN) ?
1805 MAX_TX_BUF_LEN : buf_len;
1806 buf_len -= tx_buffer->length;
1807
1808 tx_buffer->dma =
1809 pci_map_page(adapter->pdev, frag->page,
1810 frag->page_offset +
1811 (i * MAX_TX_BUF_LEN),
1812 tx_buffer->length,
1813 PCI_DMA_TODEVICE);
1814 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1815 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1816 ((cpu_to_le32(tx_buffer->length) &
1817 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1818 }
1819 }
1820
1821 if ((tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK)
1822 /* note this one is a tcp header */
1823 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
1824 /* The last tpd */
1825
1826 use_tpd->word3 |= 1 << TPD_EOP_SHIFT;
1827 /* The last buffer info contain the skb address,
1828 so it will be free after unmap */
1829 tx_buffer->skb = skb;
1830}
1831
1832static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count,
1833 struct atl1e_tpd_desc *tpd)
1834{
1835 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1836 /* Force memory writes to complete before letting h/w
1837 * know there are new descriptors to fetch. (Only
1838 * applicable for weak-ordered memory model archs,
1839 * such as IA-64). */
1840 wmb();
1841 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
1842}
1843
1844static int atl1e_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1845{
1846 struct atl1e_adapter *adapter = netdev_priv(netdev);
1847 unsigned long flags;
1848 u16 tpd_req = 1;
1849 struct atl1e_tpd_desc *tpd;
1850
1851 if (test_bit(__AT_DOWN, &adapter->flags)) {
1852 dev_kfree_skb_any(skb);
1853 return NETDEV_TX_OK;
1854 }
1855
1856 if (unlikely(skb->len <= 0)) {
1857 dev_kfree_skb_any(skb);
1858 return NETDEV_TX_OK;
1859 }
1860 tpd_req = atl1e_cal_tdp_req(skb);
1861 if (!spin_trylock_irqsave(&adapter->tx_lock, flags))
1862 return NETDEV_TX_LOCKED;
1863
1864 if (atl1e_tpd_avail(adapter) < tpd_req) {
1865 /* no enough descriptor, just stop queue */
1866 netif_stop_queue(netdev);
1867 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1868 return NETDEV_TX_BUSY;
1869 }
1870
1871 tpd = atl1e_get_tpd(adapter);
1872
1873 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1874 u16 vlan_tag = vlan_tx_tag_get(skb);
1875 u16 atl1e_vlan_tag;
1876
1877 tpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
1878 AT_VLAN_TAG_TO_TPD_TAG(vlan_tag, atl1e_vlan_tag);
1879 tpd->word2 |= (atl1e_vlan_tag & TPD_VLANTAG_MASK) <<
1880 TPD_VLAN_SHIFT;
1881 }
1882
1883 if (skb->protocol == ntohs(ETH_P_8021Q))
1884 tpd->word3 |= 1 << TPD_VL_TAGGED_SHIFT;
1885
1886 if (skb_network_offset(skb) != ETH_HLEN)
1887 tpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; /* 802.3 frame */
1888
1889 /* do TSO and check sum */
1890 if (atl1e_tso_csum(adapter, skb, tpd) != 0) {
1891 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1892 dev_kfree_skb_any(skb);
1893 return NETDEV_TX_OK;
1894 }
1895
1896 atl1e_tx_map(adapter, skb, tpd);
1897 atl1e_tx_queue(adapter, tpd_req, tpd);
1898
1899 netdev->trans_start = jiffies;
1900 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1901 return NETDEV_TX_OK;
1902}
1903
1904static void atl1e_free_irq(struct atl1e_adapter *adapter)
1905{
1906 struct net_device *netdev = adapter->netdev;
1907
1908 free_irq(adapter->pdev->irq, netdev);
1909
1910 if (adapter->have_msi)
1911 pci_disable_msi(adapter->pdev);
1912}
1913
1914static int atl1e_request_irq(struct atl1e_adapter *adapter)
1915{
1916 struct pci_dev *pdev = adapter->pdev;
1917 struct net_device *netdev = adapter->netdev;
1918 int flags = 0;
1919 int err = 0;
1920
1921 adapter->have_msi = true;
1922 err = pci_enable_msi(adapter->pdev);
1923 if (err) {
1924 dev_dbg(&pdev->dev,
1925 "Unable to allocate MSI interrupt Error: %d\n", err);
1926 adapter->have_msi = false;
1927 } else
1928 netdev->irq = pdev->irq;
1929
1930
1931 if (!adapter->have_msi)
1932 flags |= IRQF_SHARED;
1933 err = request_irq(adapter->pdev->irq, &atl1e_intr, flags,
1934 netdev->name, netdev);
1935 if (err) {
1936 dev_dbg(&pdev->dev,
1937 "Unable to allocate interrupt Error: %d\n", err);
1938 if (adapter->have_msi)
1939 pci_disable_msi(adapter->pdev);
1940 return err;
1941 }
1942 dev_dbg(&pdev->dev, "atl1e_request_irq OK\n");
1943 return err;
1944}
1945
1946int atl1e_up(struct atl1e_adapter *adapter)
1947{
1948 struct net_device *netdev = adapter->netdev;
1949 int err = 0;
1950 u32 val;
1951
1952 /* hardware has been reset, we need to reload some things */
1953 err = atl1e_init_hw(&adapter->hw);
1954 if (err) {
1955 err = -EIO;
1956 return err;
1957 }
1958 atl1e_init_ring_ptrs(adapter);
1959 atl1e_set_multi(netdev);
1960 atl1e_restore_vlan(adapter);
1961
1962 if (atl1e_configure(adapter)) {
1963 err = -EIO;
1964 goto err_up;
1965 }
1966
1967 clear_bit(__AT_DOWN, &adapter->flags);
1968 napi_enable(&adapter->napi);
1969 atl1e_irq_enable(adapter);
1970 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1971 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1972 val | MASTER_CTRL_MANUAL_INT);
1973
1974err_up:
1975 return err;
1976}
1977
1978void atl1e_down(struct atl1e_adapter *adapter)
1979{
1980 struct net_device *netdev = adapter->netdev;
1981
1982 /* signal that we're down so the interrupt handler does not
1983 * reschedule our watchdog timer */
1984 set_bit(__AT_DOWN, &adapter->flags);
1985
1986#ifdef NETIF_F_LLTX
1987 netif_stop_queue(netdev);
1988#else
1989 netif_tx_disable(netdev);
1990#endif
1991
1992 /* reset MAC to disable all RX/TX */
1993 atl1e_reset_hw(&adapter->hw);
1994 msleep(1);
1995
1996 napi_disable(&adapter->napi);
1997 atl1e_del_timer(adapter);
1998 atl1e_irq_disable(adapter);
1999
2000 netif_carrier_off(netdev);
2001 adapter->link_speed = SPEED_0;
2002 adapter->link_duplex = -1;
2003 atl1e_clean_tx_ring(adapter);
2004 atl1e_clean_rx_ring(adapter);
2005}
2006
2007/*
2008 * atl1e_open - Called when a network interface is made active
2009 * @netdev: network interface device structure
2010 *
2011 * Returns 0 on success, negative value on failure
2012 *
2013 * The open entry point is called when a network interface is made
2014 * active by the system (IFF_UP). At this point all resources needed
2015 * for transmit and receive operations are allocated, the interrupt
2016 * handler is registered with the OS, the watchdog timer is started,
2017 * and the stack is notified that the interface is ready.
2018 */
2019static int atl1e_open(struct net_device *netdev)
2020{
2021 struct atl1e_adapter *adapter = netdev_priv(netdev);
2022 int err;
2023
2024 /* disallow open during test */
2025 if (test_bit(__AT_TESTING, &adapter->flags))
2026 return -EBUSY;
2027
2028 /* allocate rx/tx dma buffer & descriptors */
2029 atl1e_init_ring_resources(adapter);
2030 err = atl1e_setup_ring_resources(adapter);
2031 if (unlikely(err))
2032 return err;
2033
2034 err = atl1e_request_irq(adapter);
2035 if (unlikely(err))
2036 goto err_req_irq;
2037
2038 err = atl1e_up(adapter);
2039 if (unlikely(err))
2040 goto err_up;
2041
2042 return 0;
2043
2044err_up:
2045 atl1e_free_irq(adapter);
2046err_req_irq:
2047 atl1e_free_ring_resources(adapter);
2048 atl1e_reset_hw(&adapter->hw);
2049
2050 return err;
2051}
2052
2053/*
2054 * atl1e_close - Disables a network interface
2055 * @netdev: network interface device structure
2056 *
2057 * Returns 0, this is not allowed to fail
2058 *
2059 * The close entry point is called when an interface is de-activated
2060 * by the OS. The hardware is still under the drivers control, but
2061 * needs to be disabled. A global MAC reset is issued to stop the
2062 * hardware, and all transmit and receive resources are freed.
2063 */
2064static int atl1e_close(struct net_device *netdev)
2065{
2066 struct atl1e_adapter *adapter = netdev_priv(netdev);
2067
2068 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2069 atl1e_down(adapter);
2070 atl1e_free_irq(adapter);
2071 atl1e_free_ring_resources(adapter);
2072
2073 return 0;
2074}
2075
2076#ifdef CONFIG_PM
2077static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
2078{
2079 struct net_device *netdev = pci_get_drvdata(pdev);
2080 struct atl1e_adapter *adapter = netdev_priv(netdev);
2081 struct atl1e_hw *hw = &adapter->hw;
2082 u32 ctrl = 0;
2083 u32 mac_ctrl_data = 0;
2084 u32 wol_ctrl_data = 0;
2085 u16 mii_advertise_data = 0;
2086 u16 mii_bmsr_data = 0;
2087 u16 mii_intr_status_data = 0;
2088 u32 wufc = adapter->wol;
2089 u32 i;
2090#ifdef CONFIG_PM
2091 int retval = 0;
2092#endif
2093
2094 if (netif_running(netdev)) {
2095 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2096 atl1e_down(adapter);
2097 }
2098 netif_device_detach(netdev);
2099
2100#ifdef CONFIG_PM
2101 retval = pci_save_state(pdev);
2102 if (retval)
2103 return retval;
2104#endif
2105
2106 if (wufc) {
2107 /* get link status */
2108 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2109 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2110
2111 mii_advertise_data = MII_AR_10T_HD_CAPS;
2112
2113 if ((atl1e_write_phy_reg(hw, MII_AT001_CR, 0) != 0) ||
2114 (atl1e_write_phy_reg(hw,
2115 MII_ADVERTISE, mii_advertise_data) != 0) ||
2116 (atl1e_phy_commit(hw)) != 0) {
2117 dev_dbg(&pdev->dev, "set phy register failed\n");
2118 goto wol_dis;
2119 }
2120
2121 hw->phy_configured = false; /* re-init PHY when resume */
2122
2123 /* turn on magic packet wol */
2124 if (wufc & AT_WUFC_MAG)
2125 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2126
2127 if (wufc & AT_WUFC_LNKC) {
2128 /* if orignal link status is link, just wait for retrive link */
2129 if (mii_bmsr_data & BMSR_LSTATUS) {
2130 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
2131 msleep(100);
2132 atl1e_read_phy_reg(hw, MII_BMSR,
2133 (u16 *)&mii_bmsr_data);
2134 if (mii_bmsr_data & BMSR_LSTATUS)
2135 break;
2136 }
2137
2138 if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
2139 dev_dbg(&pdev->dev,
2140 "%s: Link may change"
2141 "when suspend\n",
2142 atl1e_driver_name);
2143 }
2144 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2145 /* only link up can wake up */
2146 if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
2147 dev_dbg(&pdev->dev, "%s: read write phy "
2148 "register failed.\n",
2149 atl1e_driver_name);
2150 goto wol_dis;
2151 }
2152 }
2153 /* clear phy interrupt */
2154 atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
2155 /* Config MAC Ctrl register */
2156 mac_ctrl_data = MAC_CTRL_RX_EN;
2157 /* set to 10/100M halt duplex */
2158 mac_ctrl_data |= MAC_CTRL_SPEED_10_100 << MAC_CTRL_SPEED_SHIFT;
2159 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2160 MAC_CTRL_PRMLEN_MASK) <<
2161 MAC_CTRL_PRMLEN_SHIFT);
2162
2163 if (adapter->vlgrp)
2164 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
2165
2166 /* magic packet maybe Broadcast&multicast&Unicast frame */
2167 if (wufc & AT_WUFC_MAG)
2168 mac_ctrl_data |= MAC_CTRL_BC_EN;
2169
2170 dev_dbg(&pdev->dev,
2171 "%s: suspend MAC=0x%x\n",
2172 atl1e_driver_name, mac_ctrl_data);
2173
2174 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2175 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2176 /* pcie patch */
2177 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2178 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2179 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2180 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2181 goto suspend_exit;
2182 }
2183wol_dis:
2184
2185 /* WOL disabled */
2186 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2187
2188 /* pcie patch */
2189 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2190 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2191 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2192
2193 atl1e_force_ps(hw);
2194 hw->phy_configured = false; /* re-init PHY when resume */
2195
2196 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2197
2198suspend_exit:
2199
2200 if (netif_running(netdev))
2201 atl1e_free_irq(adapter);
2202
2203 pci_disable_device(pdev);
2204
2205 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2206
2207 return 0;
2208}
2209
2210static int atl1e_resume(struct pci_dev *pdev)
2211{
2212 struct net_device *netdev = pci_get_drvdata(pdev);
2213 struct atl1e_adapter *adapter = netdev_priv(netdev);
2214 u32 err;
2215
2216 pci_set_power_state(pdev, PCI_D0);
2217 pci_restore_state(pdev);
2218
2219 err = pci_enable_device(pdev);
2220 if (err) {
2221 dev_err(&pdev->dev, "ATL1e: Cannot enable PCI"
2222 " device from suspend\n");
2223 return err;
2224 }
2225
2226 pci_set_master(pdev);
2227
2228 AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
2229
2230 pci_enable_wake(pdev, PCI_D3hot, 0);
2231 pci_enable_wake(pdev, PCI_D3cold, 0);
2232
2233 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2234
2235 if (netif_running(netdev))
2236 err = atl1e_request_irq(adapter);
2237 if (err)
2238 return err;
2239
2240 atl1e_reset_hw(&adapter->hw);
2241
2242 if (netif_running(netdev))
2243 atl1e_up(adapter);
2244
2245 netif_device_attach(netdev);
2246
2247 return 0;
2248}
2249#endif
2250
2251static void atl1e_shutdown(struct pci_dev *pdev)
2252{
2253 atl1e_suspend(pdev, PMSG_SUSPEND);
2254}
2255
2256static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2257{
2258 SET_NETDEV_DEV(netdev, &pdev->dev);
2259 pci_set_drvdata(pdev, netdev);
2260
2261 netdev->irq = pdev->irq;
2262 netdev->open = &atl1e_open;
2263 netdev->stop = &atl1e_close;
2264 netdev->hard_start_xmit = &atl1e_xmit_frame;
2265 netdev->get_stats = &atl1e_get_stats;
2266 netdev->set_multicast_list = &atl1e_set_multi;
2267 netdev->set_mac_address = &atl1e_set_mac_addr;
2268 netdev->change_mtu = &atl1e_change_mtu;
2269 netdev->do_ioctl = &atl1e_ioctl;
2270 netdev->tx_timeout = &atl1e_tx_timeout;
2271 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2272 netdev->vlan_rx_register = atl1e_vlan_rx_register;
2273#ifdef CONFIG_NET_POLL_CONTROLLER
2274 netdev->poll_controller = atl1e_netpoll;
2275#endif
2276 atl1e_set_ethtool_ops(netdev);
2277
2278 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM |
2279 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2280 netdev->features |= NETIF_F_LLTX;
2281 netdev->features |= NETIF_F_TSO;
2282 netdev->features |= NETIF_F_TSO6;
2283
2284 return 0;
2285}
2286
2287/*
2288 * atl1e_probe - Device Initialization Routine
2289 * @pdev: PCI device information struct
2290 * @ent: entry in atl1e_pci_tbl
2291 *
2292 * Returns 0 on success, negative on failure
2293 *
2294 * atl1e_probe initializes an adapter identified by a pci_dev structure.
2295 * The OS initialization, configuring of the adapter private structure,
2296 * and a hardware reset occur.
2297 */
2298static int __devinit atl1e_probe(struct pci_dev *pdev,
2299 const struct pci_device_id *ent)
2300{
2301 struct net_device *netdev;
2302 struct atl1e_adapter *adapter = NULL;
2303 static int cards_found;
2304
2305 int err = 0;
2306
2307 err = pci_enable_device(pdev);
2308 if (err) {
2309 dev_err(&pdev->dev, "cannot enable PCI device\n");
2310 return err;
2311 }
2312
2313 /*
2314 * The atl1e chip can DMA to 64-bit addresses, but it uses a single
2315 * shared register for the high 32 bits, so only a single, aligned,
2316 * 4 GB physical address range can be used at a time.
2317 *
2318 * Supporting 64-bit DMA on this hardware is more trouble than it's
2319 * worth. It is far easier to limit to 32-bit DMA than update
2320 * various kernel subsystems to support the mechanics required by a
2321 * fixed-high-32-bit system.
2322 */
2323 if ((pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) ||
2324 (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK) != 0)) {
2325 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2326 goto err_dma;
2327 }
2328
2329 err = pci_request_regions(pdev, atl1e_driver_name);
2330 if (err) {
2331 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2332 goto err_pci_reg;
2333 }
2334
2335 pci_set_master(pdev);
2336
2337 netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
2338 if (netdev == NULL) {
2339 err = -ENOMEM;
2340 dev_err(&pdev->dev, "etherdev alloc failed\n");
2341 goto err_alloc_etherdev;
2342 }
2343
2344 err = atl1e_init_netdev(netdev, pdev);
2345 if (err) {
2346 dev_err(&pdev->dev, "init netdevice failed\n");
2347 goto err_init_netdev;
2348 }
2349 adapter = netdev_priv(netdev);
2350 adapter->bd_number = cards_found;
2351 adapter->netdev = netdev;
2352 adapter->pdev = pdev;
2353 adapter->hw.adapter = adapter;
2354 adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
2355 if (!adapter->hw.hw_addr) {
2356 err = -EIO;
2357 dev_err(&pdev->dev, "cannot map device registers\n");
2358 goto err_ioremap;
2359 }
2360 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2361
2362 /* init mii data */
2363 adapter->mii.dev = netdev;
2364 adapter->mii.mdio_read = atl1e_mdio_read;
2365 adapter->mii.mdio_write = atl1e_mdio_write;
2366 adapter->mii.phy_id_mask = 0x1f;
2367 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2368
2369 netif_napi_add(netdev, &adapter->napi, atl1e_clean, 64);
2370
2371 init_timer(&adapter->phy_config_timer);
2372 adapter->phy_config_timer.function = &atl1e_phy_config;
2373 adapter->phy_config_timer.data = (unsigned long) adapter;
2374
2375 /* get user settings */
2376 atl1e_check_options(adapter);
2377 /*
2378 * Mark all PCI regions associated with PCI device
2379 * pdev as being reserved by owner atl1e_driver_name
2380 * Enables bus-mastering on the device and calls
2381 * pcibios_set_master to do the needed arch specific settings
2382 */
2383 atl1e_setup_pcicmd(pdev);
2384 /* setup the private structure */
2385 err = atl1e_sw_init(adapter);
2386 if (err) {
2387 dev_err(&pdev->dev, "net device private data init failed\n");
2388 goto err_sw_init;
2389 }
2390
2391 /* Init GPHY as early as possible due to power saving issue */
2392 spin_lock(&adapter->mdio_lock);
2393 atl1e_phy_init(&adapter->hw);
2394 spin_unlock(&adapter->mdio_lock);
2395 /* reset the controller to
2396 * put the device in a known good starting state */
2397 err = atl1e_reset_hw(&adapter->hw);
2398 if (err) {
2399 err = -EIO;
2400 goto err_reset;
2401 }
2402
2403 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
2404 err = -EIO;
2405 dev_err(&pdev->dev, "get mac address failed\n");
2406 goto err_eeprom;
2407 }
2408
2409 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2410 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2411 dev_dbg(&pdev->dev, "mac address : %02x-%02x-%02x-%02x-%02x-%02x\n",
2412 adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
2413 adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
2414 adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
2415
2416 INIT_WORK(&adapter->reset_task, atl1e_reset_task);
2417 INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
2418 err = register_netdev(netdev);
2419 if (err) {
2420 dev_err(&pdev->dev, "register netdevice failed\n");
2421 goto err_register;
2422 }
2423
2424 /* assume we have no link for now */
2425 netif_stop_queue(netdev);
2426 netif_carrier_off(netdev);
2427
2428 cards_found++;
2429
2430 return 0;
2431
2432err_reset:
2433err_register:
2434err_sw_init:
2435err_eeprom:
2436 iounmap(adapter->hw.hw_addr);
2437err_init_netdev:
2438err_ioremap:
2439 free_netdev(netdev);
2440err_alloc_etherdev:
2441 pci_release_regions(pdev);
2442err_pci_reg:
2443err_dma:
2444 pci_disable_device(pdev);
2445 return err;
2446}
2447
2448/*
2449 * atl1e_remove - Device Removal Routine
2450 * @pdev: PCI device information struct
2451 *
2452 * atl1e_remove is called by the PCI subsystem to alert the driver
2453 * that it should release a PCI device. The could be caused by a
2454 * Hot-Plug event, or because the driver is going to be removed from
2455 * memory.
2456 */
2457static void __devexit atl1e_remove(struct pci_dev *pdev)
2458{
2459 struct net_device *netdev = pci_get_drvdata(pdev);
2460 struct atl1e_adapter *adapter = netdev_priv(netdev);
2461
2462 /*
2463 * flush_scheduled work may reschedule our watchdog task, so
2464 * explicitly disable watchdog tasks from being rescheduled
2465 */
2466 set_bit(__AT_DOWN, &adapter->flags);
2467
2468 atl1e_del_timer(adapter);
2469 atl1e_cancel_work(adapter);
2470
2471 unregister_netdev(netdev);
2472 atl1e_free_ring_resources(adapter);
2473 atl1e_force_ps(&adapter->hw);
2474 iounmap(adapter->hw.hw_addr);
2475 pci_release_regions(pdev);
2476 free_netdev(netdev);
2477 pci_disable_device(pdev);
2478}
2479
2480/*
2481 * atl1e_io_error_detected - called when PCI error is detected
2482 * @pdev: Pointer to PCI device
2483 * @state: The current pci connection state
2484 *
2485 * This function is called after a PCI bus error affecting
2486 * this device has been detected.
2487 */
2488static pci_ers_result_t
2489atl1e_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2490{
2491 struct net_device *netdev = pci_get_drvdata(pdev);
2492 struct atl1e_adapter *adapter = netdev->priv;
2493
2494 netif_device_detach(netdev);
2495
2496 if (netif_running(netdev))
2497 atl1e_down(adapter);
2498
2499 pci_disable_device(pdev);
2500
2501 /* Request a slot slot reset. */
2502 return PCI_ERS_RESULT_NEED_RESET;
2503}
2504
2505/*
2506 * atl1e_io_slot_reset - called after the pci bus has been reset.
2507 * @pdev: Pointer to PCI device
2508 *
2509 * Restart the card from scratch, as if from a cold-boot. Implementation
2510 * resembles the first-half of the e1000_resume routine.
2511 */
2512static pci_ers_result_t atl1e_io_slot_reset(struct pci_dev *pdev)
2513{
2514 struct net_device *netdev = pci_get_drvdata(pdev);
2515 struct atl1e_adapter *adapter = netdev->priv;
2516
2517 if (pci_enable_device(pdev)) {
2518 dev_err(&pdev->dev,
2519 "ATL1e: Cannot re-enable PCI device after reset.\n");
2520 return PCI_ERS_RESULT_DISCONNECT;
2521 }
2522 pci_set_master(pdev);
2523
2524 pci_enable_wake(pdev, PCI_D3hot, 0);
2525 pci_enable_wake(pdev, PCI_D3cold, 0);
2526
2527 atl1e_reset_hw(&adapter->hw);
2528
2529 return PCI_ERS_RESULT_RECOVERED;
2530}
2531
2532/*
2533 * atl1e_io_resume - called when traffic can start flowing again.
2534 * @pdev: Pointer to PCI device
2535 *
2536 * This callback is called when the error recovery driver tells us that
2537 * its OK to resume normal operation. Implementation resembles the
2538 * second-half of the atl1e_resume routine.
2539 */
2540static void atl1e_io_resume(struct pci_dev *pdev)
2541{
2542 struct net_device *netdev = pci_get_drvdata(pdev);
2543 struct atl1e_adapter *adapter = netdev->priv;
2544
2545 if (netif_running(netdev)) {
2546 if (atl1e_up(adapter)) {
2547 dev_err(&pdev->dev,
2548 "ATL1e: can't bring device back up after reset\n");
2549 return;
2550 }
2551 }
2552
2553 netif_device_attach(netdev);
2554}
2555
2556static struct pci_error_handlers atl1e_err_handler = {
2557 .error_detected = atl1e_io_error_detected,
2558 .slot_reset = atl1e_io_slot_reset,
2559 .resume = atl1e_io_resume,
2560};
2561
2562static struct pci_driver atl1e_driver = {
2563 .name = atl1e_driver_name,
2564 .id_table = atl1e_pci_tbl,
2565 .probe = atl1e_probe,
2566 .remove = __devexit_p(atl1e_remove),
2567 /* Power Managment Hooks */
2568#ifdef CONFIG_PM
2569 .suspend = atl1e_suspend,
2570 .resume = atl1e_resume,
2571#endif
2572 .shutdown = atl1e_shutdown,
2573 .err_handler = &atl1e_err_handler
2574};
2575
2576/*
2577 * atl1e_init_module - Driver Registration Routine
2578 *
2579 * atl1e_init_module is the first routine called when the driver is
2580 * loaded. All it does is register with the PCI subsystem.
2581 */
2582static int __init atl1e_init_module(void)
2583{
2584 return pci_register_driver(&atl1e_driver);
2585}
2586
2587/*
2588 * atl1e_exit_module - Driver Exit Cleanup Routine
2589 *
2590 * atl1e_exit_module is called just before the driver is removed
2591 * from memory.
2592 */
2593static void __exit atl1e_exit_module(void)
2594{
2595 pci_unregister_driver(&atl1e_driver);
2596}
2597
2598module_init(atl1e_init_module);
2599module_exit(atl1e_exit_module);
diff --git a/drivers/net/atl1e/atl1e_param.c b/drivers/net/atl1e/atl1e_param.c
new file mode 100644
index 00000000000..f72abb34b0c
--- /dev/null
+++ b/drivers/net/atl1e/atl1e_param.c
@@ -0,0 +1,263 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include <linux/netdevice.h>
23
24#include "atl1e.h"
25
26/* This is the only thing that needs to be changed to adjust the
27 * maximum number of ports that the driver can manage.
28 */
29
30#define ATL1E_MAX_NIC 32
31
32#define OPTION_UNSET -1
33#define OPTION_DISABLED 0
34#define OPTION_ENABLED 1
35
36/* All parameters are treated the same, as an integer array of values.
37 * This macro just reduces the need to repeat the same declaration code
38 * over and over (plus this helps to avoid typo bugs).
39 */
40#define ATL1E_PARAM_INIT { [0 ... ATL1E_MAX_NIC] = OPTION_UNSET }
41
42#define ATL1E_PARAM(x, desc) \
43 static int __devinitdata x[ATL1E_MAX_NIC + 1] = ATL1E_PARAM_INIT; \
44 static int num_##x; \
45 module_param_array_named(x, x, int, &num_##x, 0); \
46 MODULE_PARM_DESC(x, desc);
47
48/* Transmit Memory count
49 *
50 * Valid Range: 64-2048
51 *
52 * Default Value: 128
53 */
54#define ATL1E_MIN_TX_DESC_CNT 32
55#define ATL1E_MAX_TX_DESC_CNT 1020
56#define ATL1E_DEFAULT_TX_DESC_CNT 128
57ATL1E_PARAM(tx_desc_cnt, "Transmit description count");
58
59/* Receive Memory Block Count
60 *
61 * Valid Range: 16-512
62 *
63 * Default Value: 128
64 */
65#define ATL1E_MIN_RX_MEM_SIZE 8 /* 8KB */
66#define ATL1E_MAX_RX_MEM_SIZE 1024 /* 1MB */
67#define ATL1E_DEFAULT_RX_MEM_SIZE 256 /* 128KB */
68ATL1E_PARAM(rx_mem_size, "memory size of rx buffer(KB)");
69
70/* User Specified MediaType Override
71 *
72 * Valid Range: 0-5
73 * - 0 - auto-negotiate at all supported speeds
74 * - 1 - only link at 100Mbps Full Duplex
75 * - 2 - only link at 100Mbps Half Duplex
76 * - 3 - only link at 10Mbps Full Duplex
77 * - 4 - only link at 10Mbps Half Duplex
78 * Default Value: 0
79 */
80
81ATL1E_PARAM(media_type, "MediaType Select");
82
83/* Interrupt Moderate Timer in units of 2 us
84 *
85 * Valid Range: 10-65535
86 *
87 * Default Value: 45000(90ms)
88 */
89#define INT_MOD_DEFAULT_CNT 100 /* 200us */
90#define INT_MOD_MAX_CNT 65000
91#define INT_MOD_MIN_CNT 50
92ATL1E_PARAM(int_mod_timer, "Interrupt Moderator Timer");
93
94#define AUTONEG_ADV_DEFAULT 0x2F
95#define AUTONEG_ADV_MASK 0x2F
96#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
97
98#define FLASH_VENDOR_DEFAULT 0
99#define FLASH_VENDOR_MIN 0
100#define FLASH_VENDOR_MAX 2
101
102struct atl1e_option {
103 enum { enable_option, range_option, list_option } type;
104 char *name;
105 char *err;
106 int def;
107 union {
108 struct { /* range_option info */
109 int min;
110 int max;
111 } r;
112 struct { /* list_option info */
113 int nr;
114 struct atl1e_opt_list { int i; char *str; } *p;
115 } l;
116 } arg;
117};
118
119static int __devinit atl1e_validate_option(int *value, struct atl1e_option *opt, struct pci_dev *pdev)
120{
121 if (*value == OPTION_UNSET) {
122 *value = opt->def;
123 return 0;
124 }
125
126 switch (opt->type) {
127 case enable_option:
128 switch (*value) {
129 case OPTION_ENABLED:
130 dev_info(&pdev->dev, "%s Enabled\n", opt->name);
131 return 0;
132 case OPTION_DISABLED:
133 dev_info(&pdev->dev, "%s Disabled\n", opt->name);
134 return 0;
135 }
136 break;
137 case range_option:
138 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
139 dev_info(&pdev->dev, "%s set to %i\n", opt->name, *value);
140 return 0;
141 }
142 break;
143 case list_option:{
144 int i;
145 struct atl1e_opt_list *ent;
146
147 for (i = 0; i < opt->arg.l.nr; i++) {
148 ent = &opt->arg.l.p[i];
149 if (*value == ent->i) {
150 if (ent->str[0] != '\0')
151 dev_info(&pdev->dev, "%s\n",
152 ent->str);
153 return 0;
154 }
155 }
156 break;
157 }
158 default:
159 BUG();
160 }
161
162 dev_info(&pdev->dev, "Invalid %s specified (%i) %s\n",
163 opt->name, *value, opt->err);
164 *value = opt->def;
165 return -1;
166}
167
168/*
169 * atl1e_check_options - Range Checking for Command Line Parameters
170 * @adapter: board private structure
171 *
172 * This routine checks all command line parameters for valid user
173 * input. If an invalid value is given, or if no user specified
174 * value exists, a default value is used. The final value is stored
175 * in a variable in the adapter structure.
176 */
177void __devinit atl1e_check_options(struct atl1e_adapter *adapter)
178{
179 struct pci_dev *pdev = adapter->pdev;
180 int bd = adapter->bd_number;
181 if (bd >= ATL1E_MAX_NIC) {
182 dev_notice(&pdev->dev, "no configuration for board #%i\n", bd);
183 dev_notice(&pdev->dev, "Using defaults for all values\n");
184 }
185
186 { /* Transmit Ring Size */
187 struct atl1e_option opt = {
188 .type = range_option,
189 .name = "Transmit Ddescription Count",
190 .err = "using default of "
191 __MODULE_STRING(ATL1E_DEFAULT_TX_DESC_CNT),
192 .def = ATL1E_DEFAULT_TX_DESC_CNT,
193 .arg = { .r = { .min = ATL1E_MIN_TX_DESC_CNT,
194 .max = ATL1E_MAX_TX_DESC_CNT} }
195 };
196 int val;
197 if (num_tx_desc_cnt > bd) {
198 val = tx_desc_cnt[bd];
199 atl1e_validate_option(&val, &opt, pdev);
200 adapter->tx_ring.count = (u16) val & 0xFFFC;
201 } else
202 adapter->tx_ring.count = (u16)opt.def;
203 }
204
205 { /* Receive Memory Block Count */
206 struct atl1e_option opt = {
207 .type = range_option,
208 .name = "Memory size of rx buffer(KB)",
209 .err = "using default of "
210 __MODULE_STRING(ATL1E_DEFAULT_RX_MEM_SIZE),
211 .def = ATL1E_DEFAULT_RX_MEM_SIZE,
212 .arg = { .r = { .min = ATL1E_MIN_RX_MEM_SIZE,
213 .max = ATL1E_MAX_RX_MEM_SIZE} }
214 };
215 int val;
216 if (num_rx_mem_size > bd) {
217 val = rx_mem_size[bd];
218 atl1e_validate_option(&val, &opt, pdev);
219 adapter->rx_ring.page_size = (u32)val * 1024;
220 } else {
221 adapter->rx_ring.page_size = (u32)opt.def * 1024;
222 }
223 }
224
225 { /* Interrupt Moderate Timer */
226 struct atl1e_option opt = {
227 .type = range_option,
228 .name = "Interrupt Moderate Timer",
229 .err = "using default of "
230 __MODULE_STRING(INT_MOD_DEFAULT_CNT),
231 .def = INT_MOD_DEFAULT_CNT,
232 .arg = { .r = { .min = INT_MOD_MIN_CNT,
233 .max = INT_MOD_MAX_CNT} }
234 } ;
235 int val;
236 if (num_int_mod_timer > bd) {
237 val = int_mod_timer[bd];
238 atl1e_validate_option(&val, &opt, pdev);
239 adapter->hw.imt = (u16) val;
240 } else
241 adapter->hw.imt = (u16)(opt.def);
242 }
243
244 { /* MediaType */
245 struct atl1e_option opt = {
246 .type = range_option,
247 .name = "Speed/Duplex Selection",
248 .err = "using default of "
249 __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR),
250 .def = MEDIA_TYPE_AUTO_SENSOR,
251 .arg = { .r = { .min = MEDIA_TYPE_AUTO_SENSOR,
252 .max = MEDIA_TYPE_10M_HALF} }
253 } ;
254 int val;
255 if (num_media_type > bd) {
256 val = media_type[bd];
257 atl1e_validate_option(&val, &opt, pdev);
258 adapter->hw.media_type = (u16) val;
259 } else
260 adapter->hw.media_type = (u16)(opt.def);
261
262 }
263}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 21:33:58 -0500