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path: root/drivers/gpu/drm/nouveau/nv50_fifo.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_fifo.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c85
1 files changed, 42 insertions, 43 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 9201f35d827..4fc8b59cc41 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -27,13 +27,14 @@
27#include "drmP.h" 27#include "drmP.h"
28#include "drm.h" 28#include "drm.h"
29#include "nouveau_drv.h" 29#include "nouveau_drv.h"
30#include "nouveau_ramht.h"
30 31
31static void 32static void
32nv50_fifo_playlist_update(struct drm_device *dev) 33nv50_fifo_playlist_update(struct drm_device *dev)
33{ 34{
34 struct drm_nouveau_private *dev_priv = dev->dev_private; 35 struct drm_nouveau_private *dev_priv = dev->dev_private;
35 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; 36 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
36 struct nouveau_gpuobj_ref *cur; 37 struct nouveau_gpuobj *cur;
37 int i, nr; 38 int i, nr;
38 39
39 NV_DEBUG(dev, "\n"); 40 NV_DEBUG(dev, "\n");
@@ -44,13 +45,13 @@ nv50_fifo_playlist_update(struct drm_device *dev)
44 /* We never schedule channel 0 or 127 */ 45 /* We never schedule channel 0 or 127 */
45 for (i = 1, nr = 0; i < 127; i++) { 46 for (i = 1, nr = 0; i < 127; i++) {
46 if (dev_priv->fifos[i] && dev_priv->fifos[i]->ramfc) { 47 if (dev_priv->fifos[i] && dev_priv->fifos[i]->ramfc) {
47 nv_wo32(cur->gpuobj, (nr * 4), i); 48 nv_wo32(cur, (nr * 4), i);
48 nr++; 49 nr++;
49 } 50 }
50 } 51 }
51 dev_priv->engine.instmem.flush(dev); 52 dev_priv->engine.instmem.flush(dev);
52 53
53 nv_wr32(dev, 0x32f4, cur->instance >> 12); 54 nv_wr32(dev, 0x32f4, cur->vinst >> 12);
54 nv_wr32(dev, 0x32ec, nr); 55 nv_wr32(dev, 0x32ec, nr);
55 nv_wr32(dev, 0x2500, 0x101); 56 nv_wr32(dev, 0x2500, 0x101);
56} 57}
@@ -65,9 +66,9 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel)
65 NV_DEBUG(dev, "ch%d\n", channel); 66 NV_DEBUG(dev, "ch%d\n", channel);
66 67
67 if (dev_priv->chipset == 0x50) 68 if (dev_priv->chipset == 0x50)
68 inst = chan->ramfc->instance >> 12; 69 inst = chan->ramfc->vinst >> 12;
69 else 70 else
70 inst = chan->ramfc->instance >> 8; 71 inst = chan->ramfc->vinst >> 8;
71 72
72 nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst | 73 nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst |
73 NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); 74 NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
@@ -165,19 +166,19 @@ nv50_fifo_init(struct drm_device *dev)
165 goto just_reset; 166 goto just_reset;
166 } 167 }
167 168
168 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000, 169 ret = nouveau_gpuobj_new(dev, NULL, 128*4, 0x1000,
169 NVOBJ_FLAG_ZERO_ALLOC, 170 NVOBJ_FLAG_ZERO_ALLOC,
170 &pfifo->playlist[0]); 171 &pfifo->playlist[0]);
171 if (ret) { 172 if (ret) {
172 NV_ERROR(dev, "error creating playlist 0: %d\n", ret); 173 NV_ERROR(dev, "error creating playlist 0: %d\n", ret);
173 return ret; 174 return ret;
174 } 175 }
175 176
176 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000, 177 ret = nouveau_gpuobj_new(dev, NULL, 128*4, 0x1000,
177 NVOBJ_FLAG_ZERO_ALLOC, 178 NVOBJ_FLAG_ZERO_ALLOC,
178 &pfifo->playlist[1]); 179 &pfifo->playlist[1]);
179 if (ret) { 180 if (ret) {
180 nouveau_gpuobj_ref_del(dev, &pfifo->playlist[0]); 181 nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
181 NV_ERROR(dev, "error creating playlist 1: %d\n", ret); 182 NV_ERROR(dev, "error creating playlist 1: %d\n", ret);
182 return ret; 183 return ret;
183 } 184 }
@@ -205,8 +206,8 @@ nv50_fifo_takedown(struct drm_device *dev)
205 if (!pfifo->playlist[0]) 206 if (!pfifo->playlist[0])
206 return; 207 return;
207 208
208 nouveau_gpuobj_ref_del(dev, &pfifo->playlist[0]); 209 nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
209 nouveau_gpuobj_ref_del(dev, &pfifo->playlist[1]); 210 nouveau_gpuobj_ref(NULL, &pfifo->playlist[1]);
210} 211}
211 212
212int 213int
@@ -228,42 +229,39 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
228 NV_DEBUG(dev, "ch%d\n", chan->id); 229 NV_DEBUG(dev, "ch%d\n", chan->id);
229 230
230 if (dev_priv->chipset == 0x50) { 231 if (dev_priv->chipset == 0x50) {
231 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->gpuobj->pinst, 232 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
232 chan->ramin->gpuobj->vinst, 0x100, 233 chan->ramin->vinst, 0x100,
233 NVOBJ_FLAG_ZERO_ALLOC | 234 NVOBJ_FLAG_ZERO_ALLOC |
234 NVOBJ_FLAG_ZERO_FREE, &ramfc, 235 NVOBJ_FLAG_ZERO_FREE,
235 &chan->ramfc); 236 &chan->ramfc);
236 if (ret) 237 if (ret)
237 return ret; 238 return ret;
238 239
239 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->gpuobj->pinst + 240 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst + 0x0400,
240 0x0400, 241 chan->ramin->vinst + 0x0400,
241 chan->ramin->gpuobj->vinst + 242 4096, 0, &chan->cache);
242 0x0400, 4096, 0, NULL,
243 &chan->cache);
244 if (ret) 243 if (ret)
245 return ret; 244 return ret;
246 } else { 245 } else {
247 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256, 246 ret = nouveau_gpuobj_new(dev, chan, 0x100, 256,
248 NVOBJ_FLAG_ZERO_ALLOC | 247 NVOBJ_FLAG_ZERO_ALLOC |
249 NVOBJ_FLAG_ZERO_FREE, 248 NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
250 &chan->ramfc);
251 if (ret) 249 if (ret)
252 return ret; 250 return ret;
253 ramfc = chan->ramfc->gpuobj;
254 251
255 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024, 252 ret = nouveau_gpuobj_new(dev, chan, 4096, 1024,
256 0, &chan->cache); 253 0, &chan->cache);
257 if (ret) 254 if (ret)
258 return ret; 255 return ret;
259 } 256 }
257 ramfc = chan->ramfc;
260 258
261 spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 259 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
262 260
263 nv_wo32(ramfc, 0x48, chan->pushbuf->instance >> 4); 261 nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4);
264 nv_wo32(ramfc, 0x80, (0 << 27) /* 4KiB */ | 262 nv_wo32(ramfc, 0x80, (0 << 27) /* 4KiB */ |
265 (4 << 24) /* SEARCH_FULL */ | 263 (4 << 24) /* SEARCH_FULL */ |
266 (chan->ramht->instance >> 4)); 264 (chan->ramht->gpuobj->cinst >> 4));
267 nv_wo32(ramfc, 0x44, 0x2101ffff); 265 nv_wo32(ramfc, 0x44, 0x2101ffff);
268 nv_wo32(ramfc, 0x60, 0x7fffffff); 266 nv_wo32(ramfc, 0x60, 0x7fffffff);
269 nv_wo32(ramfc, 0x40, 0x00000000); 267 nv_wo32(ramfc, 0x40, 0x00000000);
@@ -274,11 +272,11 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
274 nv_wo32(ramfc, 0x54, drm_order(chan->dma.ib_max + 1) << 16); 272 nv_wo32(ramfc, 0x54, drm_order(chan->dma.ib_max + 1) << 16);
275 273
276 if (dev_priv->chipset != 0x50) { 274 if (dev_priv->chipset != 0x50) {
277 nv_wo32(chan->ramin->gpuobj, 0, chan->id); 275 nv_wo32(chan->ramin, 0, chan->id);
278 nv_wo32(chan->ramin->gpuobj, 4, chan->ramfc->instance >> 8); 276 nv_wo32(chan->ramin, 4, chan->ramfc->vinst >> 8);
279 277
280 nv_wo32(ramfc, 0x88, chan->cache->instance >> 10); 278 nv_wo32(ramfc, 0x88, chan->cache->vinst >> 10);
281 nv_wo32(ramfc, 0x98, chan->ramin->instance >> 12); 279 nv_wo32(ramfc, 0x98, chan->ramin->vinst >> 12);
282 } 280 }
283 281
284 dev_priv->engine.instmem.flush(dev); 282 dev_priv->engine.instmem.flush(dev);
@@ -293,12 +291,13 @@ void
293nv50_fifo_destroy_context(struct nouveau_channel *chan) 291nv50_fifo_destroy_context(struct nouveau_channel *chan)
294{ 292{
295 struct drm_device *dev = chan->dev; 293 struct drm_device *dev = chan->dev;
296 struct nouveau_gpuobj_ref *ramfc = chan->ramfc; 294 struct nouveau_gpuobj *ramfc = NULL;
297 295
298 NV_DEBUG(dev, "ch%d\n", chan->id); 296 NV_DEBUG(dev, "ch%d\n", chan->id);
299 297
300 /* This will ensure the channel is seen as disabled. */ 298 /* This will ensure the channel is seen as disabled. */
301 chan->ramfc = NULL; 299 nouveau_gpuobj_ref(chan->ramfc, &ramfc);
300 nouveau_gpuobj_ref(NULL, &chan->ramfc);
302 nv50_fifo_channel_disable(dev, chan->id); 301 nv50_fifo_channel_disable(dev, chan->id);
303 302
304 /* Dummy channel, also used on ch 127 */ 303 /* Dummy channel, also used on ch 127 */
@@ -306,8 +305,8 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
306 nv50_fifo_channel_disable(dev, 127); 305 nv50_fifo_channel_disable(dev, 127);
307 nv50_fifo_playlist_update(dev); 306 nv50_fifo_playlist_update(dev);
308 307
309 nouveau_gpuobj_ref_del(dev, &ramfc); 308 nouveau_gpuobj_ref(NULL, &ramfc);
310 nouveau_gpuobj_ref_del(dev, &chan->cache); 309 nouveau_gpuobj_ref(NULL, &chan->cache);
311} 310}
312 311
313int 312int
@@ -315,8 +314,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
315{ 314{
316 struct drm_device *dev = chan->dev; 315 struct drm_device *dev = chan->dev;
317 struct drm_nouveau_private *dev_priv = dev->dev_private; 316 struct drm_nouveau_private *dev_priv = dev->dev_private;
318 struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj; 317 struct nouveau_gpuobj *ramfc = chan->ramfc;
319 struct nouveau_gpuobj *cache = chan->cache->gpuobj; 318 struct nouveau_gpuobj *cache = chan->cache;
320 int ptr, cnt; 319 int ptr, cnt;
321 320
322 NV_DEBUG(dev, "ch%d\n", chan->id); 321 NV_DEBUG(dev, "ch%d\n", chan->id);
@@ -399,8 +398,8 @@ nv50_fifo_unload_context(struct drm_device *dev)
399 return -EINVAL; 398 return -EINVAL;
400 } 399 }
401 NV_DEBUG(dev, "ch%d\n", chan->id); 400 NV_DEBUG(dev, "ch%d\n", chan->id);
402 ramfc = chan->ramfc->gpuobj; 401 ramfc = chan->ramfc;
403 cache = chan->cache->gpuobj; 402 cache = chan->cache;
404 403
405 nv_wo32(ramfc, 0x00, nv_rd32(dev, 0x3330)); 404 nv_wo32(ramfc, 0x00, nv_rd32(dev, 0x3330));
406 nv_wo32(ramfc, 0x04, nv_rd32(dev, 0x3334)); 405 nv_wo32(ramfc, 0x04, nv_rd32(dev, 0x3334));
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 05:10:31 -0500