diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1a51ee07de3..9ab8708ac6b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -1138,18 +1138,14 @@ static bool | |||
1138 | intel_dp_set_link_train(struct intel_dp *intel_dp, | 1138 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
1139 | uint32_t dp_reg_value, | 1139 | uint32_t dp_reg_value, |
1140 | uint8_t dp_train_pat, | 1140 | uint8_t dp_train_pat, |
1141 | uint8_t train_set[4], | 1141 | uint8_t train_set[4]) |
1142 | bool first) | ||
1143 | { | 1142 | { |
1144 | struct drm_device *dev = intel_dp->base.enc.dev; | 1143 | struct drm_device *dev = intel_dp->base.enc.dev; |
1145 | struct drm_i915_private *dev_priv = dev->dev_private; | 1144 | struct drm_i915_private *dev_priv = dev->dev_private; |
1146 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc); | ||
1147 | int ret; | 1145 | int ret; |
1148 | 1146 | ||
1149 | I915_WRITE(intel_dp->output_reg, dp_reg_value); | 1147 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1150 | POSTING_READ(intel_dp->output_reg); | 1148 | POSTING_READ(intel_dp->output_reg); |
1151 | if (first) | ||
1152 | intel_wait_for_vblank(dev, intel_crtc->pipe); | ||
1153 | 1149 | ||
1154 | intel_dp_aux_native_write_1(intel_dp, | 1150 | intel_dp_aux_native_write_1(intel_dp, |
1155 | DP_TRAINING_PATTERN_SET, | 1151 | DP_TRAINING_PATTERN_SET, |
@@ -1174,10 +1170,15 @@ intel_dp_link_train(struct intel_dp *intel_dp) | |||
1174 | uint8_t voltage; | 1170 | uint8_t voltage; |
1175 | bool clock_recovery = false; | 1171 | bool clock_recovery = false; |
1176 | bool channel_eq = false; | 1172 | bool channel_eq = false; |
1177 | bool first = true; | ||
1178 | int tries; | 1173 | int tries; |
1179 | u32 reg; | 1174 | u32 reg; |
1180 | uint32_t DP = intel_dp->DP; | 1175 | uint32_t DP = intel_dp->DP; |
1176 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc); | ||
1177 | |||
1178 | /* Enable output, wait for it to become active */ | ||
1179 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | ||
1180 | POSTING_READ(intel_dp->output_reg); | ||
1181 | intel_wait_for_vblank(dev, intel_crtc->pipe); | ||
1181 | 1182 | ||
1182 | /* Write the link configuration data */ | 1183 | /* Write the link configuration data */ |
1183 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | 1184 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
@@ -1210,9 +1211,8 @@ intel_dp_link_train(struct intel_dp *intel_dp) | |||
1210 | reg = DP | DP_LINK_TRAIN_PAT_1; | 1211 | reg = DP | DP_LINK_TRAIN_PAT_1; |
1211 | 1212 | ||
1212 | if (!intel_dp_set_link_train(intel_dp, reg, | 1213 | if (!intel_dp_set_link_train(intel_dp, reg, |
1213 | DP_TRAINING_PATTERN_1, train_set, first)) | 1214 | DP_TRAINING_PATTERN_1, train_set)) |
1214 | break; | 1215 | break; |
1215 | first = false; | ||
1216 | /* Set training pattern 1 */ | 1216 | /* Set training pattern 1 */ |
1217 | 1217 | ||
1218 | udelay(100); | 1218 | udelay(100); |
@@ -1266,8 +1266,7 @@ intel_dp_link_train(struct intel_dp *intel_dp) | |||
1266 | 1266 | ||
1267 | /* channel eq pattern */ | 1267 | /* channel eq pattern */ |
1268 | if (!intel_dp_set_link_train(intel_dp, reg, | 1268 | if (!intel_dp_set_link_train(intel_dp, reg, |
1269 | DP_TRAINING_PATTERN_2, train_set, | 1269 | DP_TRAINING_PATTERN_2, train_set)) |
1270 | false)) | ||
1271 | break; | 1270 | break; |
1272 | 1271 | ||
1273 | udelay(400); | 1272 | udelay(400); |