diff options
Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 430598e1fa6..9c10141845e 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -38,7 +38,7 @@ | |||
38 | 38 | ||
39 | #define DRIVER_NAME "radeon" | 39 | #define DRIVER_NAME "radeon" |
40 | #define DRIVER_DESC "ATI Radeon" | 40 | #define DRIVER_DESC "ATI Radeon" |
41 | #define DRIVER_DATE "20050720" | 41 | #define DRIVER_DATE "20050911" |
42 | 42 | ||
43 | /* Interface history: | 43 | /* Interface history: |
44 | * | 44 | * |
@@ -87,9 +87,10 @@ | |||
87 | * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces | 87 | * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces |
88 | * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR | 88 | * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR |
89 | * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) | 89 | * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) |
90 | * 1.19- Add support for gart table in FB memory and PCIE r300 | ||
90 | */ | 91 | */ |
91 | #define DRIVER_MAJOR 1 | 92 | #define DRIVER_MAJOR 1 |
92 | #define DRIVER_MINOR 18 | 93 | #define DRIVER_MINOR 19 |
93 | #define DRIVER_PATCHLEVEL 0 | 94 | #define DRIVER_PATCHLEVEL 0 |
94 | 95 | ||
95 | #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) | 96 | #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) |
@@ -134,6 +135,7 @@ enum radeon_chip_flags { | |||
134 | CHIP_SINGLE_CRTC = 0x00040000UL, | 135 | CHIP_SINGLE_CRTC = 0x00040000UL, |
135 | CHIP_IS_AGP = 0x00080000UL, | 136 | CHIP_IS_AGP = 0x00080000UL, |
136 | CHIP_HAS_HIERZ = 0x00100000UL, | 137 | CHIP_HAS_HIERZ = 0x00100000UL, |
138 | CHIP_IS_PCIE = 0x00200000UL, | ||
137 | }; | 139 | }; |
138 | 140 | ||
139 | typedef struct drm_radeon_freelist { | 141 | typedef struct drm_radeon_freelist { |
@@ -213,8 +215,6 @@ typedef struct drm_radeon_private { | |||
213 | int microcode_version; | 215 | int microcode_version; |
214 | 216 | ||
215 | int is_pci; | 217 | int is_pci; |
216 | unsigned long phys_pci_gart; | ||
217 | dma_addr_t bus_pci_gart; | ||
218 | 218 | ||
219 | struct { | 219 | struct { |
220 | u32 boxes; | 220 | u32 boxes; |
@@ -270,6 +270,9 @@ typedef struct drm_radeon_private { | |||
270 | struct radeon_surface surfaces[RADEON_MAX_SURFACES]; | 270 | struct radeon_surface surfaces[RADEON_MAX_SURFACES]; |
271 | struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; | 271 | struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; |
272 | 272 | ||
273 | unsigned long pcigart_offset; | ||
274 | drm_ati_pcigart_info gart_info; | ||
275 | |||
273 | /* starting from here on, data is preserved accross an open */ | 276 | /* starting from here on, data is preserved accross an open */ |
274 | uint32_t flags; /* see radeon_chip_flags */ | 277 | uint32_t flags; /* see radeon_chip_flags */ |
275 | } drm_radeon_private_t; | 278 | } drm_radeon_private_t; |
@@ -373,6 +376,25 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, | |||
373 | #define RADEON_CRTC2_OFFSET 0x0324 | 376 | #define RADEON_CRTC2_OFFSET 0x0324 |
374 | #define RADEON_CRTC2_OFFSET_CNTL 0x0328 | 377 | #define RADEON_CRTC2_OFFSET_CNTL 0x0328 |
375 | 378 | ||
379 | #define RADEON_PCIE_INDEX 0x0030 | ||
380 | #define RADEON_PCIE_DATA 0x0034 | ||
381 | #define RADEON_PCIE_TX_GART_CNTL 0x10 | ||
382 | # define RADEON_PCIE_TX_GART_EN (1 << 0) | ||
383 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) | ||
384 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) | ||
385 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) | ||
386 | # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) | ||
387 | # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) | ||
388 | # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) | ||
389 | # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) | ||
390 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 | ||
391 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 | ||
392 | #define RADEON_PCIE_TX_GART_BASE 0x13 | ||
393 | #define RADEON_PCIE_TX_GART_START_LO 0x14 | ||
394 | #define RADEON_PCIE_TX_GART_START_HI 0x15 | ||
395 | #define RADEON_PCIE_TX_GART_END_LO 0x16 | ||
396 | #define RADEON_PCIE_TX_GART_END_HI 0x17 | ||
397 | |||
376 | #define RADEON_MPP_TB_CONFIG 0x01c0 | 398 | #define RADEON_MPP_TB_CONFIG 0x01c0 |
377 | #define RADEON_MEM_CNTL 0x0140 | 399 | #define RADEON_MEM_CNTL 0x0140 |
378 | #define RADEON_MEM_SDRAM_MODE_REG 0x0158 | 400 | #define RADEON_MEM_SDRAM_MODE_REG 0x0158 |
@@ -878,6 +900,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, | |||
878 | 900 | ||
879 | #define RADEON_RING_HIGH_MARK 128 | 901 | #define RADEON_RING_HIGH_MARK 128 |
880 | 902 | ||
903 | #define RADEON_PCIGART_TABLE_SIZE (32*1024) | ||
904 | |||
881 | #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) | 905 | #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) |
882 | #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) | 906 | #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) |
883 | #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) | 907 | #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) |
@@ -890,6 +914,13 @@ do { \ | |||
890 | RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ | 914 | RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ |
891 | } while (0) | 915 | } while (0) |
892 | 916 | ||
917 | #define RADEON_WRITE_PCIE( addr, val ) \ | ||
918 | do { \ | ||
919 | RADEON_WRITE8( RADEON_PCIE_INDEX, \ | ||
920 | ((addr) & 0xff)); \ | ||
921 | RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ | ||
922 | } while (0) | ||
923 | |||
893 | #define CP_PACKET0( reg, n ) \ | 924 | #define CP_PACKET0( reg, n ) \ |
894 | (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) | 925 | (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
895 | #define CP_PACKET0_TABLE( reg, n ) \ | 926 | #define CP_PACKET0_TABLE( reg, n ) \ |