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-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h2
-rw-r--r--arch/arm/plat-omap/devices.c21
-rw-r--r--arch/avr32/boards/atngw100/setup.c19
-rw-r--r--arch/avr32/boards/atstk1000/atstk1002.c23
-rw-r--r--arch/avr32/boards/atstk1000/atstk1003.c15
-rw-r--r--arch/avr32/boards/atstk1000/atstk1004.c18
-rw-r--r--arch/avr32/include/asm/atmel-mci.h32
-rw-r--r--arch/avr32/include/asm/byteorder.h22
-rw-r--r--arch/avr32/include/asm/io.h8
-rw-r--r--arch/avr32/kernel/process.c3
-rw-r--r--arch/avr32/kernel/setup.c19
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c460
-rw-r--r--arch/avr32/mach-at32ap/clock.c52
-rw-r--r--arch/avr32/mach-at32ap/clock.h8
-rw-r--r--arch/avr32/mach-at32ap/include/mach/at32ap700x.h128
-rw-r--r--arch/avr32/mach-at32ap/include/mach/board.h2
-rw-r--r--arch/avr32/mach-at32ap/include/mach/io.h3
-rw-r--r--arch/avr32/mach-at32ap/include/mach/portmux.h5
-rw-r--r--arch/avr32/mach-at32ap/pdc.c3
-rw-r--r--arch/avr32/mach-at32ap/pio.c63
-rw-r--r--arch/avr32/oprofile/Makefile2
-rw-r--r--arch/avr32/oprofile/backtrace.c81
-rw-r--r--arch/avr32/oprofile/op_model_avr32.c4
-rw-r--r--arch/sparc/Kconfig26
-rw-r--r--arch/sparc/include/asm/Kbuild2
-rw-r--r--arch/sparc/include/asm/asmmacro.h5
-rw-r--r--arch/sparc/include/asm/bpp.h73
-rw-r--r--arch/sparc/include/asm/bugs.h7
-rw-r--r--arch/sparc/include/asm/cpudata_64.h1
-rw-r--r--arch/sparc/include/asm/dma-mapping_32.h59
-rw-r--r--arch/sparc/include/asm/dma.h141
-rw-r--r--arch/sparc/include/asm/dma_32.h288
-rw-r--r--arch/sparc/include/asm/dma_64.h205
-rw-r--r--arch/sparc/include/asm/ebus.h8
-rw-r--r--arch/sparc/include/asm/ebus_32.h99
-rw-r--r--arch/sparc/include/asm/ebus_64.h95
-rw-r--r--arch/sparc/include/asm/ebus_dma.h35
-rw-r--r--arch/sparc/include/asm/elf_32.h7
-rw-r--r--arch/sparc/include/asm/fhc.h43
-rw-r--r--arch/sparc/include/asm/floppy_32.h16
-rw-r--r--arch/sparc/include/asm/floppy_64.h130
-rw-r--r--arch/sparc/include/asm/gpio.h36
-rw-r--r--arch/sparc/include/asm/io-unit.h4
-rw-r--r--arch/sparc/include/asm/io_32.h19
-rw-r--r--arch/sparc/include/asm/io_64.h22
-rw-r--r--arch/sparc/include/asm/iommu_64.h3
-rw-r--r--arch/sparc/include/asm/irq_64.h1
-rw-r--r--arch/sparc/include/asm/mc146818rtc_64.h10
-rw-r--r--arch/sparc/include/asm/memctrl.h9
-rw-r--r--arch/sparc/include/asm/mostek.h8
-rw-r--r--arch/sparc/include/asm/mostek_32.h171
-rw-r--r--arch/sparc/include/asm/mostek_64.h143
-rw-r--r--arch/sparc/include/asm/obio.h11
-rw-r--r--arch/sparc/include/asm/of_device.h2
-rw-r--r--arch/sparc/include/asm/of_platform.h3
-rw-r--r--arch/sparc/include/asm/oplib_32.h1
-rw-r--r--arch/sparc/include/asm/page_32.h5
-rw-r--r--arch/sparc/include/asm/page_64.h2
-rw-r--r--arch/sparc/include/asm/parport.h4
-rw-r--r--arch/sparc/include/asm/pci_32.h2
-rw-r--r--arch/sparc/include/asm/pgtable_32.h4
-rw-r--r--arch/sparc/include/asm/pgtable_64.h2
-rw-r--r--arch/sparc/include/asm/prom.h12
-rw-r--r--arch/sparc/include/asm/ptrace_64.h3
-rw-r--r--arch/sparc/include/asm/reboot.h6
-rw-r--r--arch/sparc/include/asm/rtc.h26
-rw-r--r--arch/sparc/include/asm/sbus.h8
-rw-r--r--arch/sparc/include/asm/sbus_32.h153
-rw-r--r--arch/sparc/include/asm/sbus_64.h190
-rw-r--r--arch/sparc/include/asm/spinlock_32.h2
-rw-r--r--arch/sparc/include/asm/spinlock_64.h2
-rw-r--r--arch/sparc/include/asm/sstate.h13
-rw-r--r--arch/sparc/include/asm/starfire.h1
-rw-r--r--arch/sparc/include/asm/sun4paddr.h56
-rw-r--r--arch/sparc/include/asm/sun4prom.h83
-rw-r--r--arch/sparc/include/asm/system_32.h9
-rw-r--r--arch/sparc/include/asm/system_64.h6
-rw-r--r--arch/sparc/include/asm/thread_info_32.h4
-rw-r--r--arch/sparc/include/asm/timer_32.h87
-rw-r--r--arch/sparc/include/asm/vac-ops.h7
-rw-r--r--arch/sparc/include/asm/vfc_ioctls.h58
-rw-r--r--arch/sparc/include/asm/visasm.h1
-rw-r--r--arch/sparc/kernel/Makefile4
-rw-r--r--arch/sparc/kernel/apc.c72
-rw-r--r--arch/sparc/kernel/auxio.c6
-rw-r--r--arch/sparc/kernel/devices.c2
-rw-r--r--arch/sparc/kernel/dma.c227
-rw-r--r--arch/sparc/kernel/dma.h14
-rw-r--r--arch/sparc/kernel/ebus.c393
-rw-r--r--arch/sparc/kernel/entry.S94
-rw-r--r--arch/sparc/kernel/head.S28
-rw-r--r--arch/sparc/kernel/idprom.c7
-rw-r--r--arch/sparc/kernel/ioport.c227
-rw-r--r--arch/sparc/kernel/irq.h6
-rw-r--r--arch/sparc/kernel/of_device.c74
-rw-r--r--arch/sparc/kernel/pcic.c15
-rw-r--r--arch/sparc/kernel/pmc.c59
-rw-r--r--arch/sparc/kernel/process.c2
-rw-r--r--arch/sparc/kernel/prom.c7
-rw-r--r--arch/sparc/kernel/setup.c32
-rw-r--r--arch/sparc/kernel/sparc_ksyms.c25
-rw-r--r--arch/sparc/kernel/sun4c_irq.c156
-rw-r--r--arch/sparc/kernel/sun4d_irq.c286
-rw-r--r--arch/sparc/kernel/sun4d_smp.c12
-rw-r--r--arch/sparc/kernel/sun4m_irq.c495
-rw-r--r--arch/sparc/kernel/sun4m_smp.c4
-rw-r--r--arch/sparc/kernel/sun4setup.c75
-rw-r--r--arch/sparc/kernel/sys_sparc.c8
-rw-r--r--arch/sparc/kernel/tick14.c47
-rw-r--r--arch/sparc/kernel/time.c382
-rw-r--r--arch/sparc/kernel/traps.c17
-rw-r--r--arch/sparc/mm/Makefile9
-rw-r--r--arch/sparc/mm/btfixup.c6
-rw-r--r--arch/sparc/mm/fault.c2
-rw-r--r--arch/sparc/mm/init.c14
-rw-r--r--arch/sparc/mm/io-unit.c136
-rw-r--r--arch/sparc/mm/iommu.c113
-rw-r--r--arch/sparc/mm/nosrmmu.c59
-rw-r--r--arch/sparc/mm/srmmu.c1
-rw-r--r--arch/sparc/mm/sun4c.c204
-rw-r--r--arch/sparc/prom/Makefile2
-rw-r--r--arch/sparc/prom/bootstr.c4
-rw-r--r--arch/sparc/prom/console.c3
-rw-r--r--arch/sparc/prom/init.c12
-rw-r--r--arch/sparc/prom/memory.c14
-rw-r--r--arch/sparc/prom/ranges.c1
-rw-r--r--arch/sparc/prom/sun4prom.c161
-rw-r--r--arch/sparc64/Kconfig23
-rw-r--r--arch/sparc64/Makefile2
-rw-r--r--arch/sparc64/kernel/Makefile9
-rw-r--r--arch/sparc64/kernel/auxio.c2
-rw-r--r--arch/sparc64/kernel/central.c617
-rw-r--r--arch/sparc64/kernel/chmc.c817
-rw-r--r--arch/sparc64/kernel/cpu.c208
-rw-r--r--arch/sparc64/kernel/ds.c4
-rw-r--r--arch/sparc64/kernel/ebus.c299
-rw-r--r--arch/sparc64/kernel/entry.h7
-rw-r--r--arch/sparc64/kernel/head.S1
-rw-r--r--arch/sparc64/kernel/hvapi.c3
-rw-r--r--arch/sparc64/kernel/hvcalls.S354
-rw-r--r--arch/sparc64/kernel/irq.c1
-rw-r--r--arch/sparc64/kernel/of_device.c62
-rw-r--r--arch/sparc64/kernel/pci.c172
-rw-r--r--arch/sparc64/kernel/pci_common.c8
-rw-r--r--arch/sparc64/kernel/pci_fire.c254
-rw-r--r--arch/sparc64/kernel/pci_impl.h27
-rw-r--r--arch/sparc64/kernel/pci_msi.c18
-rw-r--r--arch/sparc64/kernel/pci_psycho.c750
-rw-r--r--arch/sparc64/kernel/pci_sabre.c507
-rw-r--r--arch/sparc64/kernel/pci_schizo.c368
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c197
-rw-r--r--arch/sparc64/kernel/pci_sun4v_asm.S99
-rw-r--r--arch/sparc64/kernel/power.c55
-rw-r--r--arch/sparc64/kernel/process.c35
-rw-r--r--arch/sparc64/kernel/prom.c91
-rw-r--r--arch/sparc64/kernel/psycho_common.c470
-rw-r--r--arch/sparc64/kernel/psycho_common.h48
-rw-r--r--arch/sparc64/kernel/ptrace.c38
-rw-r--r--arch/sparc64/kernel/reboot.c53
-rw-r--r--arch/sparc64/kernel/sbus.c166
-rw-r--r--arch/sparc64/kernel/sparc64_ksyms.c23
-rw-r--r--arch/sparc64/kernel/sstate.c67
-rw-r--r--arch/sparc64/kernel/starfire.c5
-rw-r--r--arch/sparc64/kernel/sys_sparc32.c8
-rw-r--r--arch/sparc64/kernel/syscalls.S20
-rw-r--r--arch/sparc64/kernel/systbls.S2
-rw-r--r--arch/sparc64/kernel/time.c1187
-rw-r--r--arch/sparc64/kernel/traps.c69
-rw-r--r--arch/sparc64/kernel/vio.c8
-rw-r--r--arch/sparc64/kernel/visemul.c12
-rw-r--r--arch/sparc64/mm/fault.c37
-rw-r--r--arch/sparc64/mm/init.c84
-rw-r--r--arch/sparc64/mm/init.h49
-rw-r--r--arch/sparc64/mm/tlb.c2
174 files changed, 5320 insertions, 8957 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index e67c843baa0..9f5ce1ce584 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -157,9 +157,11 @@
157#define CPU_CONF ORION5X_BRIDGE_REG(0x100) 157#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
158#define CPU_CTRL ORION5X_BRIDGE_REG(0x104) 158#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
159#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) 159#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
160#define WDT_RESET 0x0002
160#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) 161#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
161#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) 162#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
162#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) 163#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
164#define WDT_INT_REQ 0x0008
163#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) 165#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
164#define BRIDGE_INT_TIMER0 0x0002 166#define BRIDGE_INT_TIMER0 0x0002
165#define BRIDGE_INT_TIMER1 0x0004 167#define BRIDGE_INT_TIMER1 0x0004
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index a716ecd1db2..97187fa0ae5 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -441,16 +441,8 @@ static inline void omap_init_uwire(void) {}
441 441
442#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) 442#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
443 443
444#ifdef CONFIG_ARCH_OMAP24XX
445#define OMAP_WDT_BASE 0x48022000
446#else
447#define OMAP_WDT_BASE 0xfffeb000
448#endif
449
450static struct resource wdt_resources[] = { 444static struct resource wdt_resources[] = {
451 { 445 {
452 .start = OMAP_WDT_BASE,
453 .end = OMAP_WDT_BASE + 0x4f,
454 .flags = IORESOURCE_MEM, 446 .flags = IORESOURCE_MEM,
455 }, 447 },
456}; 448};
@@ -464,6 +456,19 @@ static struct platform_device omap_wdt_device = {
464 456
465static void omap_init_wdt(void) 457static void omap_init_wdt(void)
466{ 458{
459 if (cpu_is_omap16xx())
460 wdt_resources[0].start = 0xfffeb000;
461 else if (cpu_is_omap2420())
462 wdt_resources[0].start = 0x48022000; /* WDT2 */
463 else if (cpu_is_omap2430())
464 wdt_resources[0].start = 0x49016000; /* WDT2 */
465 else if (cpu_is_omap343x())
466 wdt_resources[0].start = 0x48314000; /* WDT2 */
467 else
468 return;
469
470 wdt_resources[0].end = wdt_resources[0].start + 0x4f;
471
467 (void) platform_device_register(&omap_wdt_device); 472 (void) platform_device_register(&omap_wdt_device);
468} 473}
469#else 474#else
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index b8286f1ce85..6c54580a66d 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -9,6 +9,7 @@
9 */ 9 */
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/etherdevice.h> 11#include <linux/etherdevice.h>
12#include <linux/gpio.h>
12#include <linux/irq.h> 13#include <linux/irq.h>
13#include <linux/i2c.h> 14#include <linux/i2c.h>
14#include <linux/i2c-gpio.h> 15#include <linux/i2c-gpio.h>
@@ -53,8 +54,11 @@ static struct spi_board_info spi0_board_info[] __initdata = {
53}; 54};
54 55
55static struct mci_platform_data __initdata mci0_data = { 56static struct mci_platform_data __initdata mci0_data = {
56 .detect_pin = GPIO_PIN_PC(25), 57 .slot[0] = {
57 .wp_pin = GPIO_PIN_PE(0), 58 .bus_width = 4,
59 .detect_pin = GPIO_PIN_PC(25),
60 .wp_pin = GPIO_PIN_PE(0),
61 },
58}; 62};
59 63
60/* 64/*
@@ -190,7 +194,7 @@ static int __init atngw100_init(void)
190 * PB28/EXTINT3 doesn't; it should be SMBALERT# (for PMBus), 194 * PB28/EXTINT3 doesn't; it should be SMBALERT# (for PMBus),
191 * but it's not available off-board. 195 * but it's not available off-board.
192 */ 196 */
193 at32_select_periph(GPIO_PIN_PB(28), 0, AT32_GPIOF_PULLUP); 197 at32_select_periph(GPIO_PIOB_BASE, 1 << 28, 0, AT32_GPIOF_PULLUP);
194 at32_select_gpio(i2c_gpio_data.sda_pin, 198 at32_select_gpio(i2c_gpio_data.sda_pin,
195 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); 199 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
196 at32_select_gpio(i2c_gpio_data.scl_pin, 200 at32_select_gpio(i2c_gpio_data.scl_pin,
@@ -204,6 +208,15 @@ postcore_initcall(atngw100_init);
204 208
205static int __init atngw100_arch_init(void) 209static int __init atngw100_arch_init(void)
206{ 210{
211 /* PB30 is the otherwise unused jumper on the mainboard, with an
212 * external pullup; the jumper grounds it. Use it however you
213 * like, including letting U-Boot or Linux tweak boot sequences.
214 */
215 at32_select_gpio(GPIO_PIN_PB(30), 0);
216 gpio_request(GPIO_PIN_PB(30), "j15");
217 gpio_direction_input(GPIO_PIN_PB(30));
218 gpio_export(GPIO_PIN_PB(30), false);
219
207 /* set_irq_type() after the arch_initcall for EIC has run, and 220 /* set_irq_type() after the arch_initcall for EIC has run, and
208 * before the I2C subsystem could try using this IRQ. 221 * before the I2C subsystem could try using this IRQ.
209 */ 222 */
diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index dfc3443e23a..29e5b51a7fd 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -232,7 +232,7 @@ static void __init atstk1002_setup_extdac(void)
232 goto err_set_clk; 232 goto err_set_clk;
233 } 233 }
234 234
235 at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0); 235 at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
236 at73c213_data.dac_clk = gclk; 236 at73c213_data.dac_clk = gclk;
237 237
238err_set_clk: 238err_set_clk:
@@ -264,16 +264,20 @@ void __init setup_board(void)
264 264
265#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 265#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
266 266
267static struct mci_platform_data __initdata mci0_data = {
268 .slot[0] = {
269 .bus_width = 4,
270
267/* MMC card detect requires MACB0 *NOT* be used */ 271/* MMC card detect requires MACB0 *NOT* be used */
268#ifdef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM 272#ifdef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
269static struct mci_platform_data __initdata mci0_data = { 273 .detect_pin = GPIO_PIN_PC(14), /* gpio30/sdcd */
270 .detect_pin = GPIO_PIN_PC(14), /* gpio30/sdcd */ 274 .wp_pin = GPIO_PIN_PC(15), /* gpio31/sdwp */
271 .wp_pin = GPIO_PIN_PC(15), /* gpio31/sdwp */
272};
273#define MCI_PDATA &mci0_data
274#else 275#else
275#define MCI_PDATA NULL 276 .detect_pin = -ENODEV,
277 .wp_pin = -ENODEV,
276#endif /* SW6 for sd{cd,wp} routing */ 278#endif /* SW6 for sd{cd,wp} routing */
279 },
280};
277 281
278#endif /* SW2 for MMC signal routing */ 282#endif /* SW2 for MMC signal routing */
279 283
@@ -326,13 +330,14 @@ static int __init atstk1002_init(void)
326 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info)); 330 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
327#endif 331#endif
328#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 332#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
329 at32_add_device_mci(0, MCI_PDATA); 333 at32_add_device_mci(0, &mci0_data);
330#endif 334#endif
331#ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM 335#ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
332 set_hw_addr(at32_add_device_eth(1, &eth_data[1])); 336 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
333#else 337#else
334 at32_add_device_lcdc(0, &atstk1000_lcdc_data, 338 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
335 fbmem_start, fbmem_size, 0); 339 fbmem_start, fbmem_size,
340 ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL);
336#endif 341#endif
337 at32_add_device_usba(0, NULL); 342 at32_add_device_usba(0, NULL);
338#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM 343#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
diff --git a/arch/avr32/boards/atstk1000/atstk1003.c b/arch/avr32/boards/atstk1000/atstk1003.c
index 0cf664174c1..be089d7f37e 100644
--- a/arch/avr32/boards/atstk1000/atstk1003.c
+++ b/arch/avr32/boards/atstk1000/atstk1003.c
@@ -19,6 +19,7 @@
19#include <linux/spi/spi.h> 19#include <linux/spi/spi.h>
20 20
21#include <asm/setup.h> 21#include <asm/setup.h>
22#include <asm/atmel-mci.h>
22 23
23#include <mach/at32ap700x.h> 24#include <mach/at32ap700x.h>
24#include <mach/board.h> 25#include <mach/board.h>
@@ -66,6 +67,16 @@ static struct spi_board_info spi1_board_info[] __initdata = { {
66} }; 67} };
67#endif 68#endif
68 69
70#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
71static struct mci_platform_data __initdata mci0_data = {
72 .slot[0] = {
73 .bus_width = 4,
74 .detect_pin = -ENODEV,
75 .wp_pin = -ENODEV,
76 },
77};
78#endif
79
69#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC 80#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
70static void __init atstk1003_setup_extdac(void) 81static void __init atstk1003_setup_extdac(void)
71{ 82{
@@ -84,7 +95,7 @@ static void __init atstk1003_setup_extdac(void)
84 goto err_set_clk; 95 goto err_set_clk;
85 } 96 }
86 97
87 at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0); 98 at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
88 at73c213_data.dac_clk = gclk; 99 at73c213_data.dac_clk = gclk;
89 100
90err_set_clk: 101err_set_clk:
@@ -154,7 +165,7 @@ static int __init atstk1003_init(void)
154 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info)); 165 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
155#endif 166#endif
156#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 167#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
157 at32_add_device_mci(0, NULL); 168 at32_add_device_mci(0, &mci0_data);
158#endif 169#endif
159 at32_add_device_usba(0, NULL); 170 at32_add_device_usba(0, NULL);
160#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM 171#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
diff --git a/arch/avr32/boards/atstk1000/atstk1004.c b/arch/avr32/boards/atstk1000/atstk1004.c
index 50a5273e591..248ef237c16 100644
--- a/arch/avr32/boards/atstk1000/atstk1004.c
+++ b/arch/avr32/boards/atstk1000/atstk1004.c
@@ -21,6 +21,7 @@
21#include <video/atmel_lcdc.h> 21#include <video/atmel_lcdc.h>
22 22
23#include <asm/setup.h> 23#include <asm/setup.h>
24#include <asm/atmel-mci.h>
24 25
25#include <mach/at32ap700x.h> 26#include <mach/at32ap700x.h>
26#include <mach/board.h> 27#include <mach/board.h>
@@ -71,6 +72,16 @@ static struct spi_board_info spi1_board_info[] __initdata = { {
71} }; 72} };
72#endif 73#endif
73 74
75#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
76static struct mci_platform_data __initdata mci0_data = {
77 .slot[0] = {
78 .bus_width = 4,
79 .detect_pin = -ENODEV,
80 .wp_pin = -ENODEV,
81 },
82};
83#endif
84
74#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC 85#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
75static void __init atstk1004_setup_extdac(void) 86static void __init atstk1004_setup_extdac(void)
76{ 87{
@@ -89,7 +100,7 @@ static void __init atstk1004_setup_extdac(void)
89 goto err_set_clk; 100 goto err_set_clk;
90 } 101 }
91 102
92 at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0); 103 at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
93 at73c213_data.dac_clk = gclk; 104 at73c213_data.dac_clk = gclk;
94 105
95err_set_clk: 106err_set_clk:
@@ -137,10 +148,11 @@ static int __init atstk1004_init(void)
137 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info)); 148 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
138#endif 149#endif
139#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 150#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
140 at32_add_device_mci(0, NULL); 151 at32_add_device_mci(0, &mci0_data);
141#endif 152#endif
142 at32_add_device_lcdc(0, &atstk1000_lcdc_data, 153 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
143 fbmem_start, fbmem_size, 0); 154 fbmem_start, fbmem_size,
155 ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL);
144 at32_add_device_usba(0, NULL); 156 at32_add_device_usba(0, NULL);
145#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM 157#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
146 at32_add_device_ssc(0, ATMEL_SSC_TX); 158 at32_add_device_ssc(0, ATMEL_SSC_TX);
diff --git a/arch/avr32/include/asm/atmel-mci.h b/arch/avr32/include/asm/atmel-mci.h
index c2ea6e1c9aa..59f3fadd0b6 100644
--- a/arch/avr32/include/asm/atmel-mci.h
+++ b/arch/avr32/include/asm/atmel-mci.h
@@ -1,9 +1,39 @@
1#ifndef __ASM_AVR32_ATMEL_MCI_H 1#ifndef __ASM_AVR32_ATMEL_MCI_H
2#define __ASM_AVR32_ATMEL_MCI_H 2#define __ASM_AVR32_ATMEL_MCI_H
3 3
4struct mci_platform_data { 4#define ATMEL_MCI_MAX_NR_SLOTS 2
5
6struct dma_slave;
7
8/**
9 * struct mci_slot_pdata - board-specific per-slot configuration
10 * @bus_width: Number of data lines wired up the slot
11 * @detect_pin: GPIO pin wired to the card detect switch
12 * @wp_pin: GPIO pin wired to the write protect sensor
13 *
14 * If a given slot is not present on the board, @bus_width should be
15 * set to 0. The other fields are ignored in this case.
16 *
17 * Any pins that aren't available should be set to a negative value.
18 *
19 * Note that support for multiple slots is experimental -- some cards
20 * might get upset if we don't get the clock management exactly right.
21 * But in most cases, it should work just fine.
22 */
23struct mci_slot_pdata {
24 unsigned int bus_width;
5 int detect_pin; 25 int detect_pin;
6 int wp_pin; 26 int wp_pin;
7}; 27};
8 28
29/**
30 * struct mci_platform_data - board-specific MMC/SDcard configuration
31 * @dma_slave: DMA slave interface to use in data transfers, or NULL.
32 * @slot: Per-slot configuration data.
33 */
34struct mci_platform_data {
35 struct dma_slave *dma_slave;
36 struct mci_slot_pdata slot[ATMEL_MCI_MAX_NR_SLOTS];
37};
38
9#endif /* __ASM_AVR32_ATMEL_MCI_H */ 39#endif /* __ASM_AVR32_ATMEL_MCI_H */
diff --git a/arch/avr32/include/asm/byteorder.h b/arch/avr32/include/asm/byteorder.h
index d77b48ba733..8e3af02076d 100644
--- a/arch/avr32/include/asm/byteorder.h
+++ b/arch/avr32/include/asm/byteorder.h
@@ -7,6 +7,9 @@
7#include <asm/types.h> 7#include <asm/types.h>
8#include <linux/compiler.h> 8#include <linux/compiler.h>
9 9
10#define __BIG_ENDIAN
11#define __SWAB_64_THRU_32__
12
10#ifdef __CHECKER__ 13#ifdef __CHECKER__
11extern unsigned long __builtin_bswap_32(unsigned long x); 14extern unsigned long __builtin_bswap_32(unsigned long x);
12extern unsigned short __builtin_bswap_16(unsigned short x); 15extern unsigned short __builtin_bswap_16(unsigned short x);
@@ -17,15 +20,18 @@ extern unsigned short __builtin_bswap_16(unsigned short x);
17 * the result. 20 * the result.
18 */ 21 */
19#if !(__GNUC__ == 4 && __GNUC_MINOR__ < 2) 22#if !(__GNUC__ == 4 && __GNUC_MINOR__ < 2)
20#define __arch__swab32(x) __builtin_bswap_32(x) 23static inline __attribute_const__ __u16 __arch_swab16(__u16 val)
21#define __arch__swab16(x) __builtin_bswap_16(x) 24{
22#endif 25 return __builtin_bswap_16(val);
26}
27#define __arch_swab16 __arch_swab16
23 28
24#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) 29static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
25# define __BYTEORDER_HAS_U64__ 30{
26# define __SWAB_64_THRU_32__ 31 return __builtin_bswap_32(val);
32}
33#define __arch_swab32 __arch_swab32
27#endif 34#endif
28 35
29#include <linux/byteorder/big_endian.h> 36#include <linux/byteorder.h>
30
31#endif /* __ASM_AVR32_BYTEORDER_H */ 37#endif /* __ASM_AVR32_BYTEORDER_H */
diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h
index a520f77ead9..22c97ef9220 100644
--- a/arch/avr32/include/asm/io.h
+++ b/arch/avr32/include/asm/io.h
@@ -160,6 +160,14 @@ BUILDIO_IOPORT(l, u32)
160#define readw_relaxed readw 160#define readw_relaxed readw
161#define readl_relaxed readl 161#define readl_relaxed readl
162 162
163#define readb_be __raw_readb
164#define readw_be __raw_readw
165#define readl_be __raw_readl
166
167#define writeb_be __raw_writeb
168#define writew_be __raw_writew
169#define writel_be __raw_writel
170
163#define __BUILD_MEMORY_STRING(bwl, type) \ 171#define __BUILD_MEMORY_STRING(bwl, type) \
164static inline void writes##bwl(volatile void __iomem *addr, \ 172static inline void writes##bwl(volatile void __iomem *addr, \
165 const void *data, unsigned int count) \ 173 const void *data, unsigned int count) \
diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
index 2c08ac992ac..134d5302b6d 100644
--- a/arch/avr32/kernel/process.c
+++ b/arch/avr32/kernel/process.c
@@ -9,6 +9,7 @@
9#include <linux/module.h> 9#include <linux/module.h>
10#include <linux/kallsyms.h> 10#include <linux/kallsyms.h>
11#include <linux/fs.h> 11#include <linux/fs.h>
12#include <linux/pm.h>
12#include <linux/ptrace.h> 13#include <linux/ptrace.h>
13#include <linux/reboot.h> 14#include <linux/reboot.h>
14#include <linux/tick.h> 15#include <linux/tick.h>
@@ -20,7 +21,7 @@
20 21
21#include <mach/pm.h> 22#include <mach/pm.h>
22 23
23void (*pm_power_off)(void) = NULL; 24void (*pm_power_off)(void);
24EXPORT_SYMBOL(pm_power_off); 25EXPORT_SYMBOL(pm_power_off);
25 26
26/* 27/*
diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c
index d8e623c426c..5c7083916c3 100644
--- a/arch/avr32/kernel/setup.c
+++ b/arch/avr32/kernel/setup.c
@@ -283,6 +283,25 @@ static int __init early_parse_fbmem(char *p)
283} 283}
284early_param("fbmem", early_parse_fbmem); 284early_param("fbmem", early_parse_fbmem);
285 285
286/*
287 * Pick out the memory size. We look for mem=size@start,
288 * where start and size are "size[KkMmGg]"
289 */
290static int __init early_mem(char *p)
291{
292 resource_size_t size, start;
293
294 start = system_ram->start;
295 size = memparse(p, &p);
296 if (*p == '@')
297 start = memparse(p + 1, &p);
298
299 system_ram->start = start;
300 system_ram->end = system_ram->start + size - 1;
301 return 0;
302}
303early_param("mem", early_mem);
304
286static int __init parse_tag_core(struct tag *tag) 305static int __init parse_tag_core(struct tag *tag)
287{ 306{
288 if (tag->hdr.size > 2) { 307 if (tag->hdr.size > 2) {
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index e01dbe4ebb4..813b6844cdf 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -82,8 +82,9 @@ static struct platform_device _name##_id##_device = { \
82 .num_resources = ARRAY_SIZE(_name##_id##_resource), \ 82 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
83} 83}
84 84
85#define select_peripheral(pin, periph, flags) \ 85#define select_peripheral(port, pin_mask, periph, flags) \
86 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags) 86 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
87 GPIO_##periph, flags)
87 88
88#define DEV_CLK(_name, devname, bus, _index) \ 89#define DEV_CLK(_name, devname, bus, _index) \
89static struct clk devname##_##_name = { \ 90static struct clk devname##_##_name = { \
@@ -871,6 +872,7 @@ static struct clk atmel_psif1_pclk = {
871struct platform_device *__init at32_add_device_psif(unsigned int id) 872struct platform_device *__init at32_add_device_psif(unsigned int id)
872{ 873{
873 struct platform_device *pdev; 874 struct platform_device *pdev;
875 u32 pin_mask;
874 876
875 if (!(id == 0 || id == 1)) 877 if (!(id == 0 || id == 1))
876 return NULL; 878 return NULL;
@@ -881,20 +883,22 @@ struct platform_device *__init at32_add_device_psif(unsigned int id)
881 883
882 switch (id) { 884 switch (id) {
883 case 0: 885 case 0:
886 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
887
884 if (platform_device_add_resources(pdev, atmel_psif0_resource, 888 if (platform_device_add_resources(pdev, atmel_psif0_resource,
885 ARRAY_SIZE(atmel_psif0_resource))) 889 ARRAY_SIZE(atmel_psif0_resource)))
886 goto err_add_resources; 890 goto err_add_resources;
887 atmel_psif0_pclk.dev = &pdev->dev; 891 atmel_psif0_pclk.dev = &pdev->dev;
888 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */ 892 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
889 select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
890 break; 893 break;
891 case 1: 894 case 1:
895 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
896
892 if (platform_device_add_resources(pdev, atmel_psif1_resource, 897 if (platform_device_add_resources(pdev, atmel_psif1_resource,
893 ARRAY_SIZE(atmel_psif1_resource))) 898 ARRAY_SIZE(atmel_psif1_resource)))
894 goto err_add_resources; 899 goto err_add_resources;
895 atmel_psif1_pclk.dev = &pdev->dev; 900 atmel_psif1_pclk.dev = &pdev->dev;
896 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */ 901 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
897 select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
898 break; 902 break;
899 default: 903 default:
900 return NULL; 904 return NULL;
@@ -958,26 +962,30 @@ DEV_CLK(usart, atmel_usart3, pba, 6);
958 962
959static inline void configure_usart0_pins(void) 963static inline void configure_usart0_pins(void)
960{ 964{
961 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */ 965 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
962 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */ 966
967 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
963} 968}
964 969
965static inline void configure_usart1_pins(void) 970static inline void configure_usart1_pins(void)
966{ 971{
967 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */ 972 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
968 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */ 973
974 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
969} 975}
970 976
971static inline void configure_usart2_pins(void) 977static inline void configure_usart2_pins(void)
972{ 978{
973 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */ 979 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
974 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */ 980
981 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
975} 982}
976 983
977static inline void configure_usart3_pins(void) 984static inline void configure_usart3_pins(void)
978{ 985{
979 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */ 986 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
980 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */ 987
988 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
981} 989}
982 990
983static struct platform_device *__initdata at32_usarts[4]; 991static struct platform_device *__initdata at32_usarts[4];
@@ -1057,59 +1065,69 @@ struct platform_device *__init
1057at32_add_device_eth(unsigned int id, struct eth_platform_data *data) 1065at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1058{ 1066{
1059 struct platform_device *pdev; 1067 struct platform_device *pdev;
1068 u32 pin_mask;
1060 1069
1061 switch (id) { 1070 switch (id) {
1062 case 0: 1071 case 0:
1063 pdev = &macb0_device; 1072 pdev = &macb0_device;
1064 1073
1065 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */ 1074 pin_mask = (1 << 3); /* TXD0 */
1066 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */ 1075 pin_mask |= (1 << 4); /* TXD1 */
1067 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */ 1076 pin_mask |= (1 << 7); /* TXEN */
1068 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */ 1077 pin_mask |= (1 << 8); /* TXCK */
1069 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */ 1078 pin_mask |= (1 << 9); /* RXD0 */
1070 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */ 1079 pin_mask |= (1 << 10); /* RXD1 */
1071 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */ 1080 pin_mask |= (1 << 13); /* RXER */
1072 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */ 1081 pin_mask |= (1 << 15); /* RXDV */
1073 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */ 1082 pin_mask |= (1 << 16); /* MDC */
1074 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */ 1083 pin_mask |= (1 << 17); /* MDIO */
1075 1084
1076 if (!data->is_rmii) { 1085 if (!data->is_rmii) {
1077 select_peripheral(PC(0), PERIPH_A, 0); /* COL */ 1086 pin_mask |= (1 << 0); /* COL */
1078 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */ 1087 pin_mask |= (1 << 1); /* CRS */
1079 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */ 1088 pin_mask |= (1 << 2); /* TXER */
1080 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */ 1089 pin_mask |= (1 << 5); /* TXD2 */
1081 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */ 1090 pin_mask |= (1 << 6); /* TXD3 */
1082 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */ 1091 pin_mask |= (1 << 11); /* RXD2 */
1083 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */ 1092 pin_mask |= (1 << 12); /* RXD3 */
1084 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */ 1093 pin_mask |= (1 << 14); /* RXCK */
1085 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */ 1094 pin_mask |= (1 << 18); /* SPD */
1086 } 1095 }
1096
1097 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1098
1087 break; 1099 break;
1088 1100
1089 case 1: 1101 case 1:
1090 pdev = &macb1_device; 1102 pdev = &macb1_device;
1091 1103
1092 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */ 1104 pin_mask = (1 << 13); /* TXD0 */
1093 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */ 1105 pin_mask |= (1 << 14); /* TXD1 */
1094 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */ 1106 pin_mask |= (1 << 11); /* TXEN */
1095 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */ 1107 pin_mask |= (1 << 12); /* TXCK */
1096 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */ 1108 pin_mask |= (1 << 10); /* RXD0 */
1097 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */ 1109 pin_mask |= (1 << 6); /* RXD1 */
1098 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */ 1110 pin_mask |= (1 << 5); /* RXER */
1099 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */ 1111 pin_mask |= (1 << 4); /* RXDV */
1100 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */ 1112 pin_mask |= (1 << 3); /* MDC */
1101 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */ 1113 pin_mask |= (1 << 2); /* MDIO */
1114
1115 if (!data->is_rmii)
1116 pin_mask |= (1 << 15); /* SPD */
1117
1118 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1102 1119
1103 if (!data->is_rmii) { 1120 if (!data->is_rmii) {
1104 select_peripheral(PC(19), PERIPH_B, 0); /* COL */ 1121 pin_mask = (1 << 19); /* COL */
1105 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */ 1122 pin_mask |= (1 << 23); /* CRS */
1106 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */ 1123 pin_mask |= (1 << 26); /* TXER */
1107 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */ 1124 pin_mask |= (1 << 27); /* TXD2 */
1108 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */ 1125 pin_mask |= (1 << 28); /* TXD3 */
1109 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */ 1126 pin_mask |= (1 << 29); /* RXD2 */
1110 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */ 1127 pin_mask |= (1 << 30); /* RXD3 */
1111 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */ 1128 pin_mask |= (1 << 24); /* RXCK */
1112 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */ 1129
1130 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1113 } 1131 }
1114 break; 1132 break;
1115 1133
@@ -1177,23 +1195,28 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1177 { GPIO_PIN_PB(2), GPIO_PIN_PB(3), 1195 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1178 GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; 1196 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1179 struct platform_device *pdev; 1197 struct platform_device *pdev;
1198 u32 pin_mask;
1180 1199
1181 switch (id) { 1200 switch (id) {
1182 case 0: 1201 case 0:
1183 pdev = &atmel_spi0_device; 1202 pdev = &atmel_spi0_device;
1203 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
1204
1184 /* pullup MISO so a level is always defined */ 1205 /* pullup MISO so a level is always defined */
1185 select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP); 1206 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1186 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ 1207 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1187 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ 1208
1188 at32_spi_setup_slaves(0, b, n, spi0_pins); 1209 at32_spi_setup_slaves(0, b, n, spi0_pins);
1189 break; 1210 break;
1190 1211
1191 case 1: 1212 case 1:
1192 pdev = &atmel_spi1_device; 1213 pdev = &atmel_spi1_device;
1214 pin_mask = (1 << 1) | (1 << 5); /* MOSI */
1215
1193 /* pullup MISO so a level is always defined */ 1216 /* pullup MISO so a level is always defined */
1194 select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP); 1217 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1195 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ 1218 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1196 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ 1219
1197 at32_spi_setup_slaves(1, b, n, spi1_pins); 1220 at32_spi_setup_slaves(1, b, n, spi1_pins);
1198 break; 1221 break;
1199 1222
@@ -1226,6 +1249,7 @@ struct platform_device *__init at32_add_device_twi(unsigned int id,
1226 unsigned int n) 1249 unsigned int n)
1227{ 1250{
1228 struct platform_device *pdev; 1251 struct platform_device *pdev;
1252 u32 pin_mask;
1229 1253
1230 if (id != 0) 1254 if (id != 0)
1231 return NULL; 1255 return NULL;
@@ -1238,8 +1262,9 @@ struct platform_device *__init at32_add_device_twi(unsigned int id,
1238 ARRAY_SIZE(atmel_twi0_resource))) 1262 ARRAY_SIZE(atmel_twi0_resource)))
1239 goto err_add_resources; 1263 goto err_add_resources;
1240 1264
1241 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */ 1265 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
1242 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */ 1266
1267 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1243 1268
1244 atmel_twi0_pclk.dev = &pdev->dev; 1269 atmel_twi0_pclk.dev = &pdev->dev;
1245 1270
@@ -1272,10 +1297,16 @@ static struct clk atmel_mci0_pclk = {
1272struct platform_device *__init 1297struct platform_device *__init
1273at32_add_device_mci(unsigned int id, struct mci_platform_data *data) 1298at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1274{ 1299{
1275 struct mci_platform_data _data;
1276 struct platform_device *pdev; 1300 struct platform_device *pdev;
1301 struct dw_dma_slave *dws;
1302 u32 pioa_mask;
1303 u32 piob_mask;
1277 1304
1278 if (id != 0) 1305 if (id != 0 || !data)
1306 return NULL;
1307
1308 /* Must have at least one usable slot */
1309 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1279 return NULL; 1310 return NULL;
1280 1311
1281 pdev = platform_device_alloc("atmel_mci", id); 1312 pdev = platform_device_alloc("atmel_mci", id);
@@ -1286,28 +1317,80 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1286 ARRAY_SIZE(atmel_mci0_resource))) 1317 ARRAY_SIZE(atmel_mci0_resource)))
1287 goto fail; 1318 goto fail;
1288 1319
1289 if (!data) { 1320 if (data->dma_slave)
1290 data = &_data; 1321 dws = kmemdup(to_dw_dma_slave(data->dma_slave),
1291 memset(data, -1, sizeof(struct mci_platform_data)); 1322 sizeof(struct dw_dma_slave), GFP_KERNEL);
1292 data->detect_pin = GPIO_PIN_NONE; 1323 else
1293 data->wp_pin = GPIO_PIN_NONE; 1324 dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
1294 } 1325
1326 dws->slave.dev = &pdev->dev;
1327 dws->slave.dma_dev = &dw_dmac0_device.dev;
1328 dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
1329 dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
1330 | DWC_CFGH_DST_PER(1));
1331 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1332 | DWC_CFGL_HS_SRC_POL);
1333
1334 data->dma_slave = &dws->slave;
1295 1335
1296 if (platform_device_add_data(pdev, data, 1336 if (platform_device_add_data(pdev, data,
1297 sizeof(struct mci_platform_data))) 1337 sizeof(struct mci_platform_data)))
1298 goto fail; 1338 goto fail;
1299 1339
1300 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */ 1340 /* CLK line is common to both slots */
1301 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ 1341 pioa_mask = 1 << 10;
1302 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1303 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1304 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1305 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1306 1342
1307 if (gpio_is_valid(data->detect_pin)) 1343 switch (data->slot[0].bus_width) {
1308 at32_select_gpio(data->detect_pin, 0); 1344 case 4:
1309 if (gpio_is_valid(data->wp_pin)) 1345 pioa_mask |= 1 << 13; /* DATA1 */
1310 at32_select_gpio(data->wp_pin, 0); 1346 pioa_mask |= 1 << 14; /* DATA2 */
1347 pioa_mask |= 1 << 15; /* DATA3 */
1348 /* fall through */
1349 case 1:
1350 pioa_mask |= 1 << 11; /* CMD */
1351 pioa_mask |= 1 << 12; /* DATA0 */
1352
1353 if (gpio_is_valid(data->slot[0].detect_pin))
1354 at32_select_gpio(data->slot[0].detect_pin, 0);
1355 if (gpio_is_valid(data->slot[0].wp_pin))
1356 at32_select_gpio(data->slot[0].wp_pin, 0);
1357 break;
1358 case 0:
1359 /* Slot is unused */
1360 break;
1361 default:
1362 goto fail;
1363 }
1364
1365 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1366 piob_mask = 0;
1367
1368 switch (data->slot[1].bus_width) {
1369 case 4:
1370 piob_mask |= 1 << 8; /* DATA1 */
1371 piob_mask |= 1 << 9; /* DATA2 */
1372 piob_mask |= 1 << 10; /* DATA3 */
1373 /* fall through */
1374 case 1:
1375 piob_mask |= 1 << 6; /* CMD */
1376 piob_mask |= 1 << 7; /* DATA0 */
1377 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1378
1379 if (gpio_is_valid(data->slot[1].detect_pin))
1380 at32_select_gpio(data->slot[1].detect_pin, 0);
1381 if (gpio_is_valid(data->slot[1].wp_pin))
1382 at32_select_gpio(data->slot[1].wp_pin, 0);
1383 break;
1384 case 0:
1385 /* Slot is unused */
1386 break;
1387 default:
1388 if (!data->slot[0].bus_width)
1389 goto fail;
1390
1391 data->slot[1].bus_width = 0;
1392 break;
1393 }
1311 1394
1312 atmel_mci0_pclk.dev = &pdev->dev; 1395 atmel_mci0_pclk.dev = &pdev->dev;
1313 1396
@@ -1353,13 +1436,14 @@ static struct clk atmel_lcdfb0_pixclk = {
1353struct platform_device *__init 1436struct platform_device *__init
1354at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, 1437at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1355 unsigned long fbmem_start, unsigned long fbmem_len, 1438 unsigned long fbmem_start, unsigned long fbmem_len,
1356 unsigned int pin_config) 1439 u64 pin_mask)
1357{ 1440{
1358 struct platform_device *pdev; 1441 struct platform_device *pdev;
1359 struct atmel_lcdfb_info *info; 1442 struct atmel_lcdfb_info *info;
1360 struct fb_monspecs *monspecs; 1443 struct fb_monspecs *monspecs;
1361 struct fb_videomode *modedb; 1444 struct fb_videomode *modedb;
1362 unsigned int modedb_size; 1445 unsigned int modedb_size;
1446 u32 portc_mask, portd_mask, porte_mask;
1363 1447
1364 /* 1448 /*
1365 * Do a deep copy of the fb data, monspecs and modedb. Make 1449 * Do a deep copy of the fb data, monspecs and modedb. Make
@@ -1381,76 +1465,21 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1381 case 0: 1465 case 0:
1382 pdev = &atmel_lcdfb0_device; 1466 pdev = &atmel_lcdfb0_device;
1383 1467
1384 switch (pin_config) { 1468 if (pin_mask == 0ULL)
1385 case 0: 1469 /* Default to "full" lcdc control signals and 24bit */
1386 select_peripheral(PC(19), PERIPH_A, 0); /* CC */ 1470 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1387 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ 1471
1388 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ 1472 /* LCDC on port C */
1389 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ 1473 portc_mask = (pin_mask & 0xfff80000) >> 19;
1390 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */ 1474 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1391 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */ 1475
1392 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ 1476 /* LCDC on port D */
1393 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */ 1477 portd_mask = pin_mask & 0x0003ffff;
1394 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */ 1478 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1395 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */ 1479
1396 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */ 1480 /* LCDC on port E */
1397 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */ 1481 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1398 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ 1482 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1399 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1400 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1401 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1402 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1403 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1404 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1405 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1406 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1407 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1408 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1409 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1410 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1411 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1412 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1413 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1414 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1415 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1416 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1417 break;
1418 case 1:
1419 select_peripheral(PE(0), PERIPH_B, 0); /* CC */
1420 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1421 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1422 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1423 select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
1424 select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
1425 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1426 select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
1427 select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
1428 select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
1429 select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
1430 select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
1431 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1432 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1433 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1434 select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
1435 select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
1436 select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1437 select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1438 select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1439 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1440 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1441 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1442 select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1443 select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1444 select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1445 select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1446 select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1447 select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1448 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1449 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1450 break;
1451 default:
1452 goto err_invalid_id;
1453 }
1454 1483
1455 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); 1484 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1456 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); 1485 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
@@ -1499,6 +1528,7 @@ static struct clk atmel_pwm0_mck = {
1499struct platform_device *__init at32_add_device_pwm(u32 mask) 1528struct platform_device *__init at32_add_device_pwm(u32 mask)
1500{ 1529{
1501 struct platform_device *pdev; 1530 struct platform_device *pdev;
1531 u32 pin_mask;
1502 1532
1503 if (!mask) 1533 if (!mask)
1504 return NULL; 1534 return NULL;
@@ -1514,14 +1544,21 @@ struct platform_device *__init at32_add_device_pwm(u32 mask)
1514 if (platform_device_add_data(pdev, &mask, sizeof(mask))) 1544 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1515 goto out_free_pdev; 1545 goto out_free_pdev;
1516 1546
1547 pin_mask = 0;
1517 if (mask & (1 << 0)) 1548 if (mask & (1 << 0))
1518 select_peripheral(PA(28), PERIPH_A, 0); 1549 pin_mask |= (1 << 28);
1519 if (mask & (1 << 1)) 1550 if (mask & (1 << 1))
1520 select_peripheral(PA(29), PERIPH_A, 0); 1551 pin_mask |= (1 << 29);
1552 if (pin_mask > 0)
1553 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1554
1555 pin_mask = 0;
1521 if (mask & (1 << 2)) 1556 if (mask & (1 << 2))
1522 select_peripheral(PA(21), PERIPH_B, 0); 1557 pin_mask |= (1 << 21);
1523 if (mask & (1 << 3)) 1558 if (mask & (1 << 3))
1524 select_peripheral(PA(22), PERIPH_B, 0); 1559 pin_mask |= (1 << 22);
1560 if (pin_mask > 0)
1561 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1525 1562
1526 atmel_pwm0_mck.dev = &pdev->dev; 1563 atmel_pwm0_mck.dev = &pdev->dev;
1527 1564
@@ -1562,52 +1599,65 @@ struct platform_device *__init
1562at32_add_device_ssc(unsigned int id, unsigned int flags) 1599at32_add_device_ssc(unsigned int id, unsigned int flags)
1563{ 1600{
1564 struct platform_device *pdev; 1601 struct platform_device *pdev;
1602 u32 pin_mask = 0;
1565 1603
1566 switch (id) { 1604 switch (id) {
1567 case 0: 1605 case 0:
1568 pdev = &ssc0_device; 1606 pdev = &ssc0_device;
1569 if (flags & ATMEL_SSC_RF) 1607 if (flags & ATMEL_SSC_RF)
1570 select_peripheral(PA(21), PERIPH_A, 0); /* RF */ 1608 pin_mask |= (1 << 21); /* RF */
1571 if (flags & ATMEL_SSC_RK) 1609 if (flags & ATMEL_SSC_RK)
1572 select_peripheral(PA(22), PERIPH_A, 0); /* RK */ 1610 pin_mask |= (1 << 22); /* RK */
1573 if (flags & ATMEL_SSC_TK) 1611 if (flags & ATMEL_SSC_TK)
1574 select_peripheral(PA(23), PERIPH_A, 0); /* TK */ 1612 pin_mask |= (1 << 23); /* TK */
1575 if (flags & ATMEL_SSC_TF) 1613 if (flags & ATMEL_SSC_TF)
1576 select_peripheral(PA(24), PERIPH_A, 0); /* TF */ 1614 pin_mask |= (1 << 24); /* TF */
1577 if (flags & ATMEL_SSC_TD) 1615 if (flags & ATMEL_SSC_TD)
1578 select_peripheral(PA(25), PERIPH_A, 0); /* TD */ 1616 pin_mask |= (1 << 25); /* TD */
1579 if (flags & ATMEL_SSC_RD) 1617 if (flags & ATMEL_SSC_RD)
1580 select_peripheral(PA(26), PERIPH_A, 0); /* RD */ 1618 pin_mask |= (1 << 26); /* RD */
1619
1620 if (pin_mask > 0)
1621 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1622
1581 break; 1623 break;
1582 case 1: 1624 case 1:
1583 pdev = &ssc1_device; 1625 pdev = &ssc1_device;
1584 if (flags & ATMEL_SSC_RF) 1626 if (flags & ATMEL_SSC_RF)
1585 select_peripheral(PA(0), PERIPH_B, 0); /* RF */ 1627 pin_mask |= (1 << 0); /* RF */
1586 if (flags & ATMEL_SSC_RK) 1628 if (flags & ATMEL_SSC_RK)
1587 select_peripheral(PA(1), PERIPH_B, 0); /* RK */ 1629 pin_mask |= (1 << 1); /* RK */
1588 if (flags & ATMEL_SSC_TK) 1630 if (flags & ATMEL_SSC_TK)
1589 select_peripheral(PA(2), PERIPH_B, 0); /* TK */ 1631 pin_mask |= (1 << 2); /* TK */
1590 if (flags & ATMEL_SSC_TF) 1632 if (flags & ATMEL_SSC_TF)
1591 select_peripheral(PA(3), PERIPH_B, 0); /* TF */ 1633 pin_mask |= (1 << 3); /* TF */
1592 if (flags & ATMEL_SSC_TD) 1634 if (flags & ATMEL_SSC_TD)
1593 select_peripheral(PA(4), PERIPH_B, 0); /* TD */ 1635 pin_mask |= (1 << 4); /* TD */
1594 if (flags & ATMEL_SSC_RD) 1636 if (flags & ATMEL_SSC_RD)
1595 select_peripheral(PA(5), PERIPH_B, 0); /* RD */ 1637 pin_mask |= (1 << 5); /* RD */
1638
1639 if (pin_mask > 0)
1640 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1641
1596 break; 1642 break;
1597 case 2: 1643 case 2:
1598 pdev = &ssc2_device; 1644 pdev = &ssc2_device;
1599 if (flags & ATMEL_SSC_TD) 1645 if (flags & ATMEL_SSC_TD)
1600 select_peripheral(PB(13), PERIPH_A, 0); /* TD */ 1646 pin_mask |= (1 << 13); /* TD */
1601 if (flags & ATMEL_SSC_RD) 1647 if (flags & ATMEL_SSC_RD)
1602 select_peripheral(PB(14), PERIPH_A, 0); /* RD */ 1648 pin_mask |= (1 << 14); /* RD */
1603 if (flags & ATMEL_SSC_TK) 1649 if (flags & ATMEL_SSC_TK)
1604 select_peripheral(PB(15), PERIPH_A, 0); /* TK */ 1650 pin_mask |= (1 << 15); /* TK */
1605 if (flags & ATMEL_SSC_TF) 1651 if (flags & ATMEL_SSC_TF)
1606 select_peripheral(PB(16), PERIPH_A, 0); /* TF */ 1652 pin_mask |= (1 << 16); /* TF */
1607 if (flags & ATMEL_SSC_RF) 1653 if (flags & ATMEL_SSC_RF)
1608 select_peripheral(PB(17), PERIPH_A, 0); /* RF */ 1654 pin_mask |= (1 << 17); /* RF */
1609 if (flags & ATMEL_SSC_RK) 1655 if (flags & ATMEL_SSC_RK)
1610 select_peripheral(PB(18), PERIPH_A, 0); /* RK */ 1656 pin_mask |= (1 << 18); /* RK */
1657
1658 if (pin_mask > 0)
1659 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1660
1611 break; 1661 break;
1612 default: 1662 default:
1613 return NULL; 1663 return NULL;
@@ -1745,14 +1795,15 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1745 unsigned int cs, unsigned int extint) 1795 unsigned int cs, unsigned int extint)
1746{ 1796{
1747 static unsigned int extint_pin_map[4] __initdata = { 1797 static unsigned int extint_pin_map[4] __initdata = {
1748 GPIO_PIN_PB(25), 1798 (1 << 25),
1749 GPIO_PIN_PB(26), 1799 (1 << 26),
1750 GPIO_PIN_PB(27), 1800 (1 << 27),
1751 GPIO_PIN_PB(28), 1801 (1 << 28),
1752 }; 1802 };
1753 static bool common_pins_initialized __initdata = false; 1803 static bool common_pins_initialized __initdata = false;
1754 unsigned int extint_pin; 1804 unsigned int extint_pin;
1755 int ret; 1805 int ret;
1806 u32 pin_mask;
1756 1807
1757 if (extint >= ARRAY_SIZE(extint_pin_map)) 1808 if (extint >= ARRAY_SIZE(extint_pin_map))
1758 return -EINVAL; 1809 return -EINVAL;
@@ -1766,7 +1817,8 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1766 if (ret) 1817 if (ret)
1767 return ret; 1818 return ret;
1768 1819
1769 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */ 1820 /* NCS4 -> OE_N */
1821 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1770 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE); 1822 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1771 break; 1823 break;
1772 case 5: 1824 case 5:
@@ -1776,7 +1828,8 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1776 if (ret) 1828 if (ret)
1777 return ret; 1829 return ret;
1778 1830
1779 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */ 1831 /* NCS5 -> OE_N */
1832 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1780 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE); 1833 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1781 break; 1834 break;
1782 default: 1835 default:
@@ -1784,14 +1837,17 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1784 } 1837 }
1785 1838
1786 if (!common_pins_initialized) { 1839 if (!common_pins_initialized) {
1787 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */ 1840 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
1788 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */ 1841 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
1789 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */ 1842 pin_mask |= (1 << 23); /* CFRNW -> DIR */
1790 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */ 1843 pin_mask |= (1 << 24); /* NWAIT <- IORDY */
1844
1845 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1846
1791 common_pins_initialized = true; 1847 common_pins_initialized = true;
1792 } 1848 }
1793 1849
1794 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); 1850 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1795 1851
1796 pdev->resource[1].start = EIM_IRQ_BASE + extint; 1852 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1797 pdev->resource[1].end = pdev->resource[1].start; 1853 pdev->resource[1].end = pdev->resource[1].start;
@@ -1930,6 +1986,7 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1930{ 1986{
1931 struct platform_device *pdev; 1987 struct platform_device *pdev;
1932 struct ac97c_platform_data _data; 1988 struct ac97c_platform_data _data;
1989 u32 pin_mask;
1933 1990
1934 if (id != 0) 1991 if (id != 0)
1935 return NULL; 1992 return NULL;
@@ -1956,10 +2013,10 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1956 sizeof(struct ac97c_platform_data))) 2013 sizeof(struct ac97c_platform_data)))
1957 goto fail; 2014 goto fail;
1958 2015
1959 select_peripheral(PB(20), PERIPH_B, 0); /* SDO */ 2016 pin_mask = (1 << 20) | (1 << 21); /* SDO & SYNC */
1960 select_peripheral(PB(21), PERIPH_B, 0); /* SYNC */ 2017 pin_mask |= (1 << 22) | (1 << 23); /* SCLK & SDI */
1961 select_peripheral(PB(22), PERIPH_B, 0); /* SCLK */ 2018
1962 select_peripheral(PB(23), PERIPH_B, 0); /* SDI */ 2019 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1963 2020
1964 /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */ 2021 /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
1965 if (data->reset_pin != GPIO_PIN_NONE) 2022 if (data->reset_pin != GPIO_PIN_NONE)
@@ -2001,6 +2058,7 @@ static struct clk abdac0_sample_clk = {
2001struct platform_device *__init at32_add_device_abdac(unsigned int id) 2058struct platform_device *__init at32_add_device_abdac(unsigned int id)
2002{ 2059{
2003 struct platform_device *pdev; 2060 struct platform_device *pdev;
2061 u32 pin_mask;
2004 2062
2005 if (id != 0) 2063 if (id != 0)
2006 return NULL; 2064 return NULL;
@@ -2013,10 +2071,10 @@ struct platform_device *__init at32_add_device_abdac(unsigned int id)
2013 ARRAY_SIZE(abdac0_resource))) 2071 ARRAY_SIZE(abdac0_resource)))
2014 goto err_add_resources; 2072 goto err_add_resources;
2015 2073
2016 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */ 2074 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2017 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */ 2075 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2018 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */ 2076
2019 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */ 2077 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2020 2078
2021 abdac0_pclk.dev = &pdev->dev; 2079 abdac0_pclk.dev = &pdev->dev;
2022 abdac0_sample_clk.dev = &pdev->dev; 2080 abdac0_sample_clk.dev = &pdev->dev;
@@ -2073,7 +2131,7 @@ static struct clk gclk4 = {
2073 .index = 4, 2131 .index = 4,
2074}; 2132};
2075 2133
2076struct clk *at32_clock_list[] = { 2134static __initdata struct clk *init_clocks[] = {
2077 &osc32k, 2135 &osc32k,
2078 &osc0, 2136 &osc0,
2079 &osc1, 2137 &osc1,
@@ -2137,7 +2195,6 @@ struct clk *at32_clock_list[] = {
2137 &gclk3, 2195 &gclk3,
2138 &gclk4, 2196 &gclk4,
2139}; 2197};
2140unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2141 2198
2142void __init setup_platform(void) 2199void __init setup_platform(void)
2143{ 2200{
@@ -2168,14 +2225,19 @@ void __init setup_platform(void)
2168 genclk_init_parent(&abdac0_sample_clk); 2225 genclk_init_parent(&abdac0_sample_clk);
2169 2226
2170 /* 2227 /*
2171 * Turn on all clocks that have at least one user already, and 2228 * Build initial dynamic clock list by registering all clocks
2172 * turn off everything else. We only do this for module 2229 * from the array.
2173 * clocks, and even though it isn't particularly pretty to 2230 * At the same time, turn on all clocks that have at least one
2174 * check the address of the mode function, it should do the 2231 * user already, and turn off everything else. We only do this
2175 * trick... 2232 * for module clocks, and even though it isn't particularly
2233 * pretty to check the address of the mode function, it should
2234 * do the trick...
2176 */ 2235 */
2177 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) { 2236 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2178 struct clk *clk = at32_clock_list[i]; 2237 struct clk *clk = init_clocks[i];
2238
2239 /* first, register clock */
2240 at32_clk_register(clk);
2179 2241
2180 if (clk->users == 0) 2242 if (clk->users == 0)
2181 continue; 2243 continue;
diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c
index 6c27ddac5ad..138a00a2a2d 100644
--- a/arch/avr32/mach-at32ap/clock.c
+++ b/arch/avr32/mach-at32ap/clock.c
@@ -15,24 +15,40 @@
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/string.h> 17#include <linux/string.h>
18#include <linux/list.h>
18 19
19#include <mach/chip.h> 20#include <mach/chip.h>
20 21
21#include "clock.h" 22#include "clock.h"
22 23
24/* at32 clock list */
25static LIST_HEAD(at32_clock_list);
26
23static DEFINE_SPINLOCK(clk_lock); 27static DEFINE_SPINLOCK(clk_lock);
28static DEFINE_SPINLOCK(clk_list_lock);
29
30void at32_clk_register(struct clk *clk)
31{
32 spin_lock(&clk_list_lock);
33 /* add the new item to the end of the list */
34 list_add_tail(&clk->list, &at32_clock_list);
35 spin_unlock(&clk_list_lock);
36}
24 37
25struct clk *clk_get(struct device *dev, const char *id) 38struct clk *clk_get(struct device *dev, const char *id)
26{ 39{
27 int i; 40 struct clk *clk;
28 41
29 for (i = 0; i < at32_nr_clocks; i++) { 42 spin_lock(&clk_list_lock);
30 struct clk *clk = at32_clock_list[i];
31 43
32 if (clk->dev == dev && strcmp(id, clk->name) == 0) 44 list_for_each_entry(clk, &at32_clock_list, list) {
45 if (clk->dev == dev && strcmp(id, clk->name) == 0) {
46 spin_unlock(&clk_list_lock);
33 return clk; 47 return clk;
48 }
34 } 49 }
35 50
51 spin_unlock(&clk_list_lock);
36 return ERR_PTR(-ENOENT); 52 return ERR_PTR(-ENOENT);
37} 53}
38EXPORT_SYMBOL(clk_get); 54EXPORT_SYMBOL(clk_get);
@@ -203,8 +219,8 @@ dump_clock(struct clk *parent, struct clkinf *r)
203 219
204 /* cost of this scan is small, but not linear... */ 220 /* cost of this scan is small, but not linear... */
205 r->nest = nest + NEST_DELTA; 221 r->nest = nest + NEST_DELTA;
206 for (i = 3; i < at32_nr_clocks; i++) { 222
207 clk = at32_clock_list[i]; 223 list_for_each_entry(clk, &at32_clock_list, list) {
208 if (clk->parent == parent) 224 if (clk->parent == parent)
209 dump_clock(clk, r); 225 dump_clock(clk, r);
210 } 226 }
@@ -215,6 +231,7 @@ static int clk_show(struct seq_file *s, void *unused)
215{ 231{
216 struct clkinf r; 232 struct clkinf r;
217 int i; 233 int i;
234 struct clk *clk;
218 235
219 /* show all the power manager registers */ 236 /* show all the power manager registers */
220 seq_printf(s, "MCCTRL = %8x\n", pm_readl(MCCTRL)); 237 seq_printf(s, "MCCTRL = %8x\n", pm_readl(MCCTRL));
@@ -234,14 +251,25 @@ static int clk_show(struct seq_file *s, void *unused)
234 251
235 seq_printf(s, "\n"); 252 seq_printf(s, "\n");
236 253
237 /* show clock tree as derived from the three oscillators
238 * we "know" are at the head of the list
239 */
240 r.s = s; 254 r.s = s;
241 r.nest = 0; 255 r.nest = 0;
242 dump_clock(at32_clock_list[0], &r); 256 /* protected from changes on the list while dumping */
243 dump_clock(at32_clock_list[1], &r); 257 spin_lock(&clk_list_lock);
244 dump_clock(at32_clock_list[2], &r); 258
259 /* show clock tree as derived from the three oscillators */
260 clk = clk_get(NULL, "osc32k");
261 dump_clock(clk, &r);
262 clk_put(clk);
263
264 clk = clk_get(NULL, "osc0");
265 dump_clock(clk, &r);
266 clk_put(clk);
267
268 clk = clk_get(NULL, "osc1");
269 dump_clock(clk, &r);
270 clk_put(clk);
271
272 spin_unlock(&clk_list_lock);
245 273
246 return 0; 274 return 0;
247} 275}
diff --git a/arch/avr32/mach-at32ap/clock.h b/arch/avr32/mach-at32ap/clock.h
index bb8e1f29583..623bf0e9a1e 100644
--- a/arch/avr32/mach-at32ap/clock.h
+++ b/arch/avr32/mach-at32ap/clock.h
@@ -12,8 +12,13 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/list.h>
16
17
18void at32_clk_register(struct clk *clk);
15 19
16struct clk { 20struct clk {
21 struct list_head list; /* linking element */
17 const char *name; /* Clock name/function */ 22 const char *name; /* Clock name/function */
18 struct device *dev; /* Device the clock is used by */ 23 struct device *dev; /* Device the clock is used by */
19 struct clk *parent; /* Parent clock, if any */ 24 struct clk *parent; /* Parent clock, if any */
@@ -25,6 +30,3 @@ struct clk {
25 u16 users; /* Enabled if non-zero */ 30 u16 users; /* Enabled if non-zero */
26 u16 index; /* Sibling index */ 31 u16 index; /* Sibling index */
27}; 32};
28
29extern struct clk *at32_clock_list[];
30extern unsigned int at32_nr_clocks;
diff --git a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
index 1e9852d65cc..a77d372f6f3 100644
--- a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
+++ b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
@@ -83,4 +83,132 @@
83#define HMATRIX_BASE 0xfff00800 83#define HMATRIX_BASE 0xfff00800
84#define SDRAMC_BASE 0xfff03800 84#define SDRAMC_BASE 0xfff03800
85 85
86/* LCDC on port C */
87#define ATMEL_LCDC_PC_CC (1ULL << 19)
88#define ATMEL_LCDC_PC_HSYNC (1ULL << 20)
89#define ATMEL_LCDC_PC_PCLK (1ULL << 21)
90#define ATMEL_LCDC_PC_VSYNC (1ULL << 22)
91#define ATMEL_LCDC_PC_DVAL (1ULL << 23)
92#define ATMEL_LCDC_PC_MODE (1ULL << 24)
93#define ATMEL_LCDC_PC_PWR (1ULL << 25)
94#define ATMEL_LCDC_PC_DATA0 (1ULL << 26)
95#define ATMEL_LCDC_PC_DATA1 (1ULL << 27)
96#define ATMEL_LCDC_PC_DATA2 (1ULL << 28)
97#define ATMEL_LCDC_PC_DATA3 (1ULL << 29)
98#define ATMEL_LCDC_PC_DATA4 (1ULL << 30)
99#define ATMEL_LCDC_PC_DATA5 (1ULL << 31)
100
101/* LCDC on port D */
102#define ATMEL_LCDC_PD_DATA6 (1ULL << 0)
103#define ATMEL_LCDC_PD_DATA7 (1ULL << 1)
104#define ATMEL_LCDC_PD_DATA8 (1ULL << 2)
105#define ATMEL_LCDC_PD_DATA9 (1ULL << 3)
106#define ATMEL_LCDC_PD_DATA10 (1ULL << 4)
107#define ATMEL_LCDC_PD_DATA11 (1ULL << 5)
108#define ATMEL_LCDC_PD_DATA12 (1ULL << 6)
109#define ATMEL_LCDC_PD_DATA13 (1ULL << 7)
110#define ATMEL_LCDC_PD_DATA14 (1ULL << 8)
111#define ATMEL_LCDC_PD_DATA15 (1ULL << 9)
112#define ATMEL_LCDC_PD_DATA16 (1ULL << 10)
113#define ATMEL_LCDC_PD_DATA17 (1ULL << 11)
114#define ATMEL_LCDC_PD_DATA18 (1ULL << 12)
115#define ATMEL_LCDC_PD_DATA19 (1ULL << 13)
116#define ATMEL_LCDC_PD_DATA20 (1ULL << 14)
117#define ATMEL_LCDC_PD_DATA21 (1ULL << 15)
118#define ATMEL_LCDC_PD_DATA22 (1ULL << 16)
119#define ATMEL_LCDC_PD_DATA23 (1ULL << 17)
120
121/* LCDC on port E */
122#define ATMEL_LCDC_PE_CC (1ULL << (32 + 0))
123#define ATMEL_LCDC_PE_DVAL (1ULL << (32 + 1))
124#define ATMEL_LCDC_PE_MODE (1ULL << (32 + 2))
125#define ATMEL_LCDC_PE_DATA0 (1ULL << (32 + 3))
126#define ATMEL_LCDC_PE_DATA1 (1ULL << (32 + 4))
127#define ATMEL_LCDC_PE_DATA2 (1ULL << (32 + 5))
128#define ATMEL_LCDC_PE_DATA3 (1ULL << (32 + 6))
129#define ATMEL_LCDC_PE_DATA4 (1ULL << (32 + 7))
130#define ATMEL_LCDC_PE_DATA8 (1ULL << (32 + 8))
131#define ATMEL_LCDC_PE_DATA9 (1ULL << (32 + 9))
132#define ATMEL_LCDC_PE_DATA10 (1ULL << (32 + 10))
133#define ATMEL_LCDC_PE_DATA11 (1ULL << (32 + 11))
134#define ATMEL_LCDC_PE_DATA12 (1ULL << (32 + 12))
135#define ATMEL_LCDC_PE_DATA16 (1ULL << (32 + 13))
136#define ATMEL_LCDC_PE_DATA17 (1ULL << (32 + 14))
137#define ATMEL_LCDC_PE_DATA18 (1ULL << (32 + 15))
138#define ATMEL_LCDC_PE_DATA19 (1ULL << (32 + 16))
139#define ATMEL_LCDC_PE_DATA20 (1ULL << (32 + 17))
140#define ATMEL_LCDC_PE_DATA21 (1ULL << (32 + 18))
141
142
143#define ATMEL_LCDC(PORT, PIN) (ATMEL_LCDC_##PORT##_##PIN)
144
145
146#define ATMEL_LCDC_PRI_24B_DATA ( \
147 ATMEL_LCDC(PC, DATA0) | ATMEL_LCDC(PC, DATA1) | \
148 ATMEL_LCDC(PC, DATA2) | ATMEL_LCDC(PC, DATA3) | \
149 ATMEL_LCDC(PC, DATA4) | ATMEL_LCDC(PC, DATA5) | \
150 ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \
151 ATMEL_LCDC(PD, DATA8) | ATMEL_LCDC(PD, DATA9) | \
152 ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) | \
153 ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) | \
154 ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \
155 ATMEL_LCDC(PD, DATA16) | ATMEL_LCDC(PD, DATA17) | \
156 ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) | \
157 ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) | \
158 ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
159
160#define ATMEL_LCDC_ALT_24B_DATA ( \
161 ATMEL_LCDC(PE, DATA0) | ATMEL_LCDC(PE, DATA1) | \
162 ATMEL_LCDC(PE, DATA2) | ATMEL_LCDC(PE, DATA3) | \
163 ATMEL_LCDC(PE, DATA4) | ATMEL_LCDC(PC, DATA5) | \
164 ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \
165 ATMEL_LCDC(PE, DATA8) | ATMEL_LCDC(PE, DATA9) | \
166 ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) | \
167 ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) | \
168 ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \
169 ATMEL_LCDC(PE, DATA16) | ATMEL_LCDC(PE, DATA17) | \
170 ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) | \
171 ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) | \
172 ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
173
174#define ATMEL_LCDC_PRI_15B_DATA ( \
175 ATMEL_LCDC(PC, DATA0) | ATMEL_LCDC(PC, DATA1) | \
176 ATMEL_LCDC(PC, DATA2) | ATMEL_LCDC(PC, DATA3) | \
177 ATMEL_LCDC(PC, DATA4) | ATMEL_LCDC(PC, DATA5) | \
178 ATMEL_LCDC(PD, DATA8) | ATMEL_LCDC(PD, DATA9) | \
179 ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) | \
180 ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA16) | \
181 ATMEL_LCDC(PD, DATA17) | ATMEL_LCDC(PD, DATA18) | \
182 ATMEL_LCDC(PD, DATA19) | ATMEL_LCDC(PD, DATA20))
183
184#define ATMEL_LCDC_ALT_15B_DATA ( \
185 ATMEL_LCDC(PE, DATA0) | ATMEL_LCDC(PE, DATA1) | \
186 ATMEL_LCDC(PE, DATA2) | ATMEL_LCDC(PE, DATA3) | \
187 ATMEL_LCDC(PE, DATA4) | ATMEL_LCDC(PC, DATA5) | \
188 ATMEL_LCDC(PE, DATA8) | ATMEL_LCDC(PE, DATA9) | \
189 ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) | \
190 ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PE, DATA16) | \
191 ATMEL_LCDC(PE, DATA17) | ATMEL_LCDC(PE, DATA18) | \
192 ATMEL_LCDC(PE, DATA19) | ATMEL_LCDC(PE, DATA20))
193
194#define ATMEL_LCDC_PRI_CONTROL ( \
195 ATMEL_LCDC(PC, CC) | ATMEL_LCDC(PC, DVAL) | \
196 ATMEL_LCDC(PC, MODE) | ATMEL_LCDC(PC, PWR))
197
198#define ATMEL_LCDC_ALT_CONTROL ( \
199 ATMEL_LCDC(PE, CC) | ATMEL_LCDC(PE, DVAL) | \
200 ATMEL_LCDC(PE, MODE) | ATMEL_LCDC(PC, PWR))
201
202#define ATMEL_LCDC_CONTROL ( \
203 ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) | \
204 ATMEL_LCDC(PC, PCLK))
205
206#define ATMEL_LCDC_PRI_24BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_24B_DATA)
207
208#define ATMEL_LCDC_ALT_24BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_24B_DATA)
209
210#define ATMEL_LCDC_PRI_15BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_15B_DATA)
211
212#define ATMEL_LCDC_ALT_15BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
213
86#endif /* __ASM_ARCH_AT32AP700X_H__ */ 214#endif /* __ASM_ARCH_AT32AP700X_H__ */
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index e60e9076544..c48386d66bc 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -43,7 +43,7 @@ struct atmel_lcdfb_info;
43struct platform_device * 43struct platform_device *
44at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, 44at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
45 unsigned long fbmem_start, unsigned long fbmem_len, 45 unsigned long fbmem_start, unsigned long fbmem_len,
46 unsigned int pin_config); 46 u64 pin_mask);
47 47
48struct usba_platform_data; 48struct usba_platform_data;
49struct platform_device * 49struct platform_device *
diff --git a/arch/avr32/mach-at32ap/include/mach/io.h b/arch/avr32/mach-at32ap/include/mach/io.h
index 4ec6abc68ea..22ea79b7405 100644
--- a/arch/avr32/mach-at32ap/include/mach/io.h
+++ b/arch/avr32/mach-at32ap/include/mach/io.h
@@ -1,8 +1,7 @@
1#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H 1#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
2#define __ASM_AVR32_ARCH_AT32AP_IO_H 2#define __ASM_AVR32_ARCH_AT32AP_IO_H
3 3
4/* For "bizarre" halfword swapping */ 4#include <linux/swab.h>
5#include <linux/byteorder/swabb.h>
6 5
7#if defined(CONFIG_AP700X_32_BIT_SMC) 6#if defined(CONFIG_AP700X_32_BIT_SMC)
8# define __swizzle_addr_b(addr) (addr ^ 3UL) 7# define __swizzle_addr_b(addr) (addr ^ 3UL)
diff --git a/arch/avr32/mach-at32ap/include/mach/portmux.h b/arch/avr32/mach-at32ap/include/mach/portmux.h
index b1abe6b4e4e..21c79373b53 100644
--- a/arch/avr32/mach-at32ap/include/mach/portmux.h
+++ b/arch/avr32/mach-at32ap/include/mach/portmux.h
@@ -21,9 +21,10 @@
21#define AT32_GPIOF_DEGLITCH 0x00000008 /* (IN) Filter glitches */ 21#define AT32_GPIOF_DEGLITCH 0x00000008 /* (IN) Filter glitches */
22#define AT32_GPIOF_MULTIDRV 0x00000010 /* Enable multidriver option */ 22#define AT32_GPIOF_MULTIDRV 0x00000010 /* Enable multidriver option */
23 23
24void at32_select_periph(unsigned int pin, unsigned int periph, 24void at32_select_periph(unsigned int port, unsigned int pin,
25 unsigned long flags); 25 unsigned int periph, unsigned long flags);
26void at32_select_gpio(unsigned int pin, unsigned long flags); 26void at32_select_gpio(unsigned int pin, unsigned long flags);
27void at32_deselect_pin(unsigned int pin);
27void at32_reserve_pin(unsigned int pin); 28void at32_reserve_pin(unsigned int pin);
28 29
29#endif /* __ASM_ARCH_PORTMUX_H__ */ 30#endif /* __ASM_ARCH_PORTMUX_H__ */
diff --git a/arch/avr32/mach-at32ap/pdc.c b/arch/avr32/mach-at32ap/pdc.c
index 1040bda4fda..61ab15aae97 100644
--- a/arch/avr32/mach-at32ap/pdc.c
+++ b/arch/avr32/mach-at32ap/pdc.c
@@ -35,7 +35,6 @@ static int __init pdc_probe(struct platform_device *pdev)
35} 35}
36 36
37static struct platform_driver pdc_driver = { 37static struct platform_driver pdc_driver = {
38 .probe = pdc_probe,
39 .driver = { 38 .driver = {
40 .name = "pdc", 39 .name = "pdc",
41 }, 40 },
@@ -43,6 +42,6 @@ static struct platform_driver pdc_driver = {
43 42
44static int __init pdc_init(void) 43static int __init pdc_init(void)
45{ 44{
46 return platform_driver_register(&pdc_driver); 45 return platform_driver_probe(&pdc_driver, pdc_probe);
47} 46}
48arch_initcall(pdc_init); 47arch_initcall(pdc_init);
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
index 405ee6bad4c..ed81a8bcb22 100644
--- a/arch/avr32/mach-at32ap/pio.c
+++ b/arch/avr32/mach-at32ap/pio.c
@@ -50,35 +50,48 @@ static struct pio_device *gpio_to_pio(unsigned int gpio)
50} 50}
51 51
52/* Pin multiplexing API */ 52/* Pin multiplexing API */
53static DEFINE_SPINLOCK(pio_lock);
53 54
54void __init at32_select_periph(unsigned int pin, unsigned int periph, 55void __init at32_select_periph(unsigned int port, u32 pin_mask,
55 unsigned long flags) 56 unsigned int periph, unsigned long flags)
56{ 57{
57 struct pio_device *pio; 58 struct pio_device *pio;
58 unsigned int pin_index = pin & 0x1f;
59 u32 mask = 1 << pin_index;
60 59
61 pio = gpio_to_pio(pin); 60 /* assign and verify pio */
61 pio = gpio_to_pio(port);
62 if (unlikely(!pio)) { 62 if (unlikely(!pio)) {
63 printk("pio: invalid pin %u\n", pin); 63 printk(KERN_WARNING "pio: invalid port %u\n", port);
64 goto fail; 64 goto fail;
65 } 65 }
66 66
67 if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask) 67 /* Test if any of the requested pins is already muxed */
68 || gpiochip_is_requested(&pio->chip, pin_index))) { 68 spin_lock(&pio_lock);
69 printk("%s: pin %u is busy\n", pio->name, pin_index); 69 if (unlikely(pio->pinmux_mask & pin_mask)) {
70 printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
71 pio->name, pin_mask, pio->pinmux_mask & pin_mask);
72 spin_unlock(&pio_lock);
70 goto fail; 73 goto fail;
71 } 74 }
72 75
73 pio_writel(pio, PUER, mask); 76 pio->pinmux_mask |= pin_mask;
77
78 /* enable pull ups */
79 pio_writel(pio, PUER, pin_mask);
80
81 /* select either peripheral A or B */
74 if (periph) 82 if (periph)
75 pio_writel(pio, BSR, mask); 83 pio_writel(pio, BSR, pin_mask);
76 else 84 else
77 pio_writel(pio, ASR, mask); 85 pio_writel(pio, ASR, pin_mask);
86
87 /* enable peripheral control */
88 pio_writel(pio, PDR, pin_mask);
78 89
79 pio_writel(pio, PDR, mask); 90 /* Disable pull ups if not requested. */
80 if (!(flags & AT32_GPIOF_PULLUP)) 91 if (!(flags & AT32_GPIOF_PULLUP))
81 pio_writel(pio, PUDR, mask); 92 pio_writel(pio, PUDR, pin_mask);
93
94 spin_unlock(&pio_lock);
82 95
83 return; 96 return;
84 97
@@ -134,6 +147,25 @@ fail:
134 dump_stack(); 147 dump_stack();
135} 148}
136 149
150/*
151 * Undo a previous pin reservation. Will not affect the hardware
152 * configuration.
153 */
154void at32_deselect_pin(unsigned int pin)
155{
156 struct pio_device *pio;
157 unsigned int pin_index = pin & 0x1f;
158
159 pio = gpio_to_pio(pin);
160 if (unlikely(!pio)) {
161 printk("pio: invalid pin %u\n", pin);
162 dump_stack();
163 return;
164 }
165
166 clear_bit(pin_index, &pio->pinmux_mask);
167}
168
137/* Reserve a pin, preventing anyone else from changing its configuration. */ 169/* Reserve a pin, preventing anyone else from changing its configuration. */
138void __init at32_reserve_pin(unsigned int pin) 170void __init at32_reserve_pin(unsigned int pin)
139{ 171{
@@ -382,7 +414,6 @@ static int __init pio_probe(struct platform_device *pdev)
382} 414}
383 415
384static struct platform_driver pio_driver = { 416static struct platform_driver pio_driver = {
385 .probe = pio_probe,
386 .driver = { 417 .driver = {
387 .name = "pio", 418 .name = "pio",
388 }, 419 },
@@ -390,7 +421,7 @@ static struct platform_driver pio_driver = {
390 421
391static int __init pio_init(void) 422static int __init pio_init(void)
392{ 423{
393 return platform_driver_register(&pio_driver); 424 return platform_driver_probe(&pio_driver, pio_probe);
394} 425}
395postcore_initcall(pio_init); 426postcore_initcall(pio_init);
396 427
diff --git a/arch/avr32/oprofile/Makefile b/arch/avr32/oprofile/Makefile
index 1fe81c3c1e8..e0eb520e028 100644
--- a/arch/avr32/oprofile/Makefile
+++ b/arch/avr32/oprofile/Makefile
@@ -5,4 +5,4 @@ oprofile-y := $(addprefix ../../../drivers/oprofile/, \
5 event_buffer.o oprofile_files.o \ 5 event_buffer.o oprofile_files.o \
6 oprofilefs.o oprofile_stats.o \ 6 oprofilefs.o oprofile_stats.o \
7 timer_int.o) 7 timer_int.o)
8oprofile-y += op_model_avr32.o 8oprofile-y += op_model_avr32.o backtrace.o
diff --git a/arch/avr32/oprofile/backtrace.c b/arch/avr32/oprofile/backtrace.c
new file mode 100644
index 00000000000..75d9ad6f99c
--- /dev/null
+++ b/arch/avr32/oprofile/backtrace.c
@@ -0,0 +1,81 @@
1/*
2 * AVR32 specific backtracing code for oprofile
3 *
4 * Copyright 2008 Weinmann GmbH
5 *
6 * Author: Nikolaus Voss <n.voss@weinmann.de>
7 *
8 * Based on i386 oprofile backtrace code by John Levon and David Smith
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/oprofile.h>
17#include <linux/sched.h>
18#include <linux/uaccess.h>
19
20/* The first two words of each frame on the stack look like this if we have
21 * frame pointers */
22struct frame_head {
23 unsigned long lr;
24 struct frame_head *fp;
25};
26
27/* copied from arch/avr32/kernel/process.c */
28static inline int valid_stack_ptr(struct thread_info *tinfo, unsigned long p)
29{
30 return (p > (unsigned long)tinfo)
31 && (p < (unsigned long)tinfo + THREAD_SIZE - 3);
32}
33
34/* copied from arch/x86/oprofile/backtrace.c */
35static struct frame_head *dump_user_backtrace(struct frame_head *head)
36{
37 struct frame_head bufhead[2];
38
39 /* Also check accessibility of one struct frame_head beyond */
40 if (!access_ok(VERIFY_READ, head, sizeof(bufhead)))
41 return NULL;
42 if (__copy_from_user_inatomic(bufhead, head, sizeof(bufhead)))
43 return NULL;
44
45 oprofile_add_trace(bufhead[0].lr);
46
47 /* frame pointers should strictly progress back up the stack
48 * (towards higher addresses) */
49 if (bufhead[0].fp <= head)
50 return NULL;
51
52 return bufhead[0].fp;
53}
54
55void avr32_backtrace(struct pt_regs * const regs, unsigned int depth)
56{
57 /* Get first frame pointer */
58 struct frame_head *head = (struct frame_head *)(regs->r7);
59
60 if (!user_mode(regs)) {
61#ifdef CONFIG_FRAME_POINTER
62 /*
63 * Traverse the kernel stack from frame to frame up to
64 * "depth" steps.
65 */
66 while (depth-- && valid_stack_ptr(task_thread_info(current),
67 (unsigned long)head)) {
68 oprofile_add_trace(head->lr);
69 if (head->fp <= head)
70 break;
71 head = head->fp;
72 }
73#endif
74 } else {
75 /* Assume we have frame pointers in user mode process */
76 while (depth-- && head)
77 head = dump_user_backtrace(head);
78 }
79}
80
81
diff --git a/arch/avr32/oprofile/op_model_avr32.c b/arch/avr32/oprofile/op_model_avr32.c
index df42325c7f8..a3e9b3c4845 100644
--- a/arch/avr32/oprofile/op_model_avr32.c
+++ b/arch/avr32/oprofile/op_model_avr32.c
@@ -22,6 +22,8 @@
22#define AVR32_PERFCTR_IRQ_GROUP 0 22#define AVR32_PERFCTR_IRQ_GROUP 0
23#define AVR32_PERFCTR_IRQ_LINE 1 23#define AVR32_PERFCTR_IRQ_LINE 1
24 24
25void avr32_backtrace(struct pt_regs * const regs, unsigned int depth);
26
25enum { PCCNT, PCNT0, PCNT1, NR_counter }; 27enum { PCCNT, PCNT0, PCNT1, NR_counter };
26 28
27struct avr32_perf_counter { 29struct avr32_perf_counter {
@@ -223,6 +225,8 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
223 memcpy(ops, &avr32_perf_counter_ops, 225 memcpy(ops, &avr32_perf_counter_ops,
224 sizeof(struct oprofile_operations)); 226 sizeof(struct oprofile_operations));
225 227
228 ops->backtrace = avr32_backtrace;
229
226 printk(KERN_INFO "oprofile: using AVR32 performance monitoring.\n"); 230 printk(KERN_INFO "oprofile: using AVR32 performance monitoring.\n");
227 231
228 return 0; 232 return 0;
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index a214002114e..97671dac12a 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -20,6 +20,11 @@ config GENERIC_ISA_DMA
20 bool 20 bool
21 default y 21 default y
22 22
23config GENERIC_GPIO
24 bool
25 help
26 Generic GPIO API support
27
23config ARCH_NO_VIRT_TO_BUS 28config ARCH_NO_VIRT_TO_BUS
24 def_bool y 29 def_bool y
25 30
@@ -69,6 +74,9 @@ config SPARC
69 select HAVE_OPROFILE 74 select HAVE_OPROFILE
70 select HAVE_ARCH_KGDB if !SMP 75 select HAVE_ARCH_KGDB if !SMP
71 select HAVE_ARCH_TRACEHOOK 76 select HAVE_ARCH_TRACEHOOK
77 select ARCH_WANT_OPTIONAL_GPIOLIB
78 select RTC_CLASS
79 select RTC_DRV_M48T59
72 80
73# Identify this as a Sparc32 build 81# Identify this as a Sparc32 build
74config SPARC32 82config SPARC32
@@ -204,17 +212,6 @@ config SUN_PM
204 Enable power management and CPU standby features on supported 212 Enable power management and CPU standby features on supported
205 SPARC platforms. 213 SPARC platforms.
206 214
207config SUN4
208 bool "Support for SUN4 machines (disables SUN4[CDM] support)"
209 depends on !SMP
210 default n
211 help
212 Say Y here if, and only if, your machine is a sun4. Note that
213 a kernel compiled with this option will run only on sun4.
214 (And the current version will probably work only on sun4/330.)
215
216if !SUN4
217
218config PCI 215config PCI
219 bool "Support for PCI and PS/2 keyboard/mouse" 216 bool "Support for PCI and PS/2 keyboard/mouse"
220 help 217 help
@@ -227,11 +224,6 @@ config PCI_SYSCALL
227 224
228source "drivers/pci/Kconfig" 225source "drivers/pci/Kconfig"
229 226
230endif
231
232config NO_DMA
233 def_bool !PCI
234
235config SUN_OPENPROMFS 227config SUN_OPENPROMFS
236 tristate "Openprom tree appears in /proc/openprom" 228 tristate "Openprom tree appears in /proc/openprom"
237 help 229 help
@@ -263,9 +255,7 @@ source "net/Kconfig"
263 255
264source "drivers/Kconfig" 256source "drivers/Kconfig"
265 257
266if !SUN4
267source "drivers/sbus/char/Kconfig" 258source "drivers/sbus/char/Kconfig"
268endif
269 259
270# This one must be before the filesystem configs. -DaveM 260# This one must be before the filesystem configs. -DaveM
271 261
diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild
index a5f0ce734ff..2ba7183bc1f 100644
--- a/arch/sparc/include/asm/Kbuild
+++ b/arch/sparc/include/asm/Kbuild
@@ -22,7 +22,6 @@ header-y += unistd_64.h
22 22
23header-y += apc.h 23header-y += apc.h
24header-y += asi.h 24header-y += asi.h
25header-y += bpp.h
26header-y += display7seg.h 25header-y += display7seg.h
27header-y += envctrl.h 26header-y += envctrl.h
28header-y += fbio.h 27header-y += fbio.h
@@ -41,5 +40,4 @@ header-y += reg_64.h
41header-y += traps.h 40header-y += traps.h
42header-y += uctx.h 41header-y += uctx.h
43header-y += utrap.h 42header-y += utrap.h
44header-y += vfc_ioctls.h
45header-y += watchdog.h 43header-y += watchdog.h
diff --git a/arch/sparc/include/asm/asmmacro.h b/arch/sparc/include/asm/asmmacro.h
index a619a4d97aa..a995bf8aba3 100644
--- a/arch/sparc/include/asm/asmmacro.h
+++ b/arch/sparc/include/asm/asmmacro.h
@@ -34,12 +34,7 @@
34/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+ 34/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+
35 likes byte accesses. These are to avoid ifdef mania. */ 35 likes byte accesses. These are to avoid ifdef mania. */
36 36
37#ifdef CONFIG_SUN4
38#define lduXa lduha
39#define stXa stha
40#else
41#define lduXa lduba 37#define lduXa lduba
42#define stXa stba 38#define stXa stba
43#endif
44 39
45#endif /* !(_SPARC_ASMMACRO_H) */ 40#endif /* !(_SPARC_ASMMACRO_H) */
diff --git a/arch/sparc/include/asm/bpp.h b/arch/sparc/include/asm/bpp.h
deleted file mode 100644
index 31f515e499a..00000000000
--- a/arch/sparc/include/asm/bpp.h
+++ /dev/null
@@ -1,73 +0,0 @@
1#ifndef _SPARC_BPP_H
2#define _SPARC_BPP_H
3
4/*
5 * Copyright (c) 1995 Picture Elements
6 * Stephen Williams
7 * Gus Baldauf
8 *
9 * Linux/SPARC port by Peter Zaitcev.
10 * Integration into SPARC tree by Tom Dyas.
11 */
12
13#include <linux/ioctl.h>
14
15/*
16 * This is a driver that supports IEEE Std 1284-1994 communications
17 * with compliant or compatible devices. It will use whatever features
18 * the device supports, prefering those that are typically faster.
19 *
20 * When the device is opened, it is left in COMPATIBILITY mode, and
21 * writes work like any printer device. The driver only attempt to
22 * negotiate 1284 modes when needed so that plugs can be pulled,
23 * switch boxes switched, etc., without disrupting things. It will
24 * also leave the device in compatibility mode when closed.
25 */
26
27
28
29/*
30 * This driver also supplies ioctls to manually manipulate the
31 * pins. This is great for testing devices, or writing code to deal
32 * with bizzarro-mode of the ACME Special TurboThingy Plus.
33 *
34 * NOTE: These ioctl currently do not interact well with
35 * read/write. Caveat emptor.
36 *
37 * PUT_PINS allows us to assign the sense of all the pins, including
38 * the data pins if being driven by the host. The GET_PINS returns the
39 * pins that the peripheral drives, including data if appropriate.
40 */
41
42# define BPP_PUT_PINS _IOW('B', 1, int)
43# define BPP_GET_PINS _IOR('B', 2, char) /* that's bogus - should've been _IO */
44# define BPP_PUT_DATA _IOW('B', 3, int)
45# define BPP_GET_DATA _IOR('B', 4, char) /* ditto */
46
47/*
48 * Set the data bus to input mode. Disengage the data bin driver and
49 * be prepared to read values from the peripheral. If the arg is 0,
50 * then revert the bus to output mode.
51 */
52# define BPP_SET_INPUT _IOW('B', 5, int)
53
54/*
55 * These bits apply to the PUT operation...
56 */
57# define BPP_PP_nStrobe 0x0001
58# define BPP_PP_nAutoFd 0x0002
59# define BPP_PP_nInit 0x0004
60# define BPP_PP_nSelectIn 0x0008
61
62/*
63 * These apply to the GET operation, which also reads the current value
64 * of the previously put values. A bit mask of these will be returned
65 * as a bit mask in the return code of the ioctl().
66 */
67# define BPP_GP_nAck 0x0100
68# define BPP_GP_Busy 0x0200
69# define BPP_GP_PError 0x0400
70# define BPP_GP_Select 0x0800
71# define BPP_GP_nFault 0x1000
72
73#endif
diff --git a/arch/sparc/include/asm/bugs.h b/arch/sparc/include/asm/bugs.h
index e179bc12f64..61d86bbbe2b 100644
--- a/arch/sparc/include/asm/bugs.h
+++ b/arch/sparc/include/asm/bugs.h
@@ -7,10 +7,6 @@
7#include <asm/cpudata.h> 7#include <asm/cpudata.h>
8#endif 8#endif
9 9
10#ifdef CONFIG_SPARC64
11#include <asm/sstate.h>
12#endif
13
14extern unsigned long loops_per_jiffy; 10extern unsigned long loops_per_jiffy;
15 11
16static void __init check_bugs(void) 12static void __init check_bugs(void)
@@ -18,7 +14,4 @@ static void __init check_bugs(void)
18#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP) 14#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP)
19 cpu_data(0).udelay_val = loops_per_jiffy; 15 cpu_data(0).udelay_val = loops_per_jiffy;
20#endif 16#endif
21#ifdef CONFIG_SPARC64
22 sstate_running();
23#endif
24} 17}
diff --git a/arch/sparc/include/asm/cpudata_64.h b/arch/sparc/include/asm/cpudata_64.h
index 532975ecfe1..7da7c13d23c 100644
--- a/arch/sparc/include/asm/cpudata_64.h
+++ b/arch/sparc/include/asm/cpudata_64.h
@@ -86,7 +86,6 @@ extern struct trap_per_cpu trap_block[NR_CPUS];
86extern void init_cur_cpu_trap(struct thread_info *); 86extern void init_cur_cpu_trap(struct thread_info *);
87extern void setup_tba(void); 87extern void setup_tba(void);
88extern int ncpus_probed; 88extern int ncpus_probed;
89extern void __init cpu_probe(void);
90extern const struct seq_operations cpuinfo_op; 89extern const struct seq_operations cpuinfo_op;
91 90
92extern unsigned long real_hard_smp_processor_id(void); 91extern unsigned long real_hard_smp_processor_id(void);
diff --git a/arch/sparc/include/asm/dma-mapping_32.h b/arch/sparc/include/asm/dma-mapping_32.h
index f3a641e6b2c..8a57ea0573e 100644
--- a/arch/sparc/include/asm/dma-mapping_32.h
+++ b/arch/sparc/include/asm/dma-mapping_32.h
@@ -1,11 +1,60 @@
1#ifndef _ASM_SPARC_DMA_MAPPING_H 1#ifndef _ASM_SPARC_DMA_MAPPING_H
2#define _ASM_SPARC_DMA_MAPPING_H 2#define _ASM_SPARC_DMA_MAPPING_H
3 3
4#include <linux/types.h>
4 5
5#ifdef CONFIG_PCI 6struct device;
6#include <asm-generic/dma-mapping.h> 7struct scatterlist;
7#else 8struct page;
8#include <asm-generic/dma-mapping-broken.h> 9
9#endif /* PCI */ 10#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
11
12extern int dma_supported(struct device *dev, u64 mask);
13extern int dma_set_mask(struct device *dev, u64 dma_mask);
14extern void *dma_alloc_coherent(struct device *dev, size_t size,
15 dma_addr_t *dma_handle, gfp_t flag);
16extern void dma_free_coherent(struct device *dev, size_t size,
17 void *cpu_addr, dma_addr_t dma_handle);
18extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
19 size_t size,
20 enum dma_data_direction direction);
21extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
22 size_t size,
23 enum dma_data_direction direction);
24extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
25 unsigned long offset, size_t size,
26 enum dma_data_direction direction);
27extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
28 size_t size, enum dma_data_direction direction);
29extern int dma_map_sg(struct device *dev, struct scatterlist *sg,
30 int nents, enum dma_data_direction direction);
31extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
32 int nents, enum dma_data_direction direction);
33extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
34 size_t size,
35 enum dma_data_direction direction);
36extern void dma_sync_single_for_device(struct device *dev,
37 dma_addr_t dma_handle,
38 size_t size,
39 enum dma_data_direction direction);
40extern void dma_sync_single_range_for_cpu(struct device *dev,
41 dma_addr_t dma_handle,
42 unsigned long offset,
43 size_t size,
44 enum dma_data_direction direction);
45extern void dma_sync_single_range_for_device(struct device *dev,
46 dma_addr_t dma_handle,
47 unsigned long offset, size_t size,
48 enum dma_data_direction direction);
49extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
50 int nelems, enum dma_data_direction direction);
51extern void dma_sync_sg_for_device(struct device *dev,
52 struct scatterlist *sg, int nelems,
53 enum dma_data_direction direction);
54extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
55extern int dma_get_cache_alignment(void);
56
57#define dma_alloc_noncoherent dma_alloc_coherent
58#define dma_free_noncoherent dma_free_coherent
10 59
11#endif /* _ASM_SPARC_DMA_MAPPING_H */ 60#endif /* _ASM_SPARC_DMA_MAPPING_H */
diff --git a/arch/sparc/include/asm/dma.h b/arch/sparc/include/asm/dma.h
index aa1d90ac04c..b554927bbaf 100644
--- a/arch/sparc/include/asm/dma.h
+++ b/arch/sparc/include/asm/dma.h
@@ -1,8 +1,139 @@
1#ifndef ___ASM_SPARC_DMA_H 1#ifndef _ASM_SPARC_DMA_H
2#define ___ASM_SPARC_DMA_H 2#define _ASM_SPARC_DMA_H
3#if defined(__sparc__) && defined(__arch64__) 3
4#include <asm/dma_64.h> 4/* These are irrelevant for Sparc DMA, but we leave it in so that
5 * things can compile.
6 */
7#define MAX_DMA_CHANNELS 8
8#define DMA_MODE_READ 1
9#define DMA_MODE_WRITE 2
10#define MAX_DMA_ADDRESS (~0UL)
11
12/* Useful constants */
13#define SIZE_16MB (16*1024*1024)
14#define SIZE_64K (64*1024)
15
16/* SBUS DMA controller reg offsets */
17#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
18#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
19#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
20#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
21
22/* Fields in the cond_reg register */
23/* First, the version identification bits */
24#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
25#define DMA_VERS0 0x00000000 /* Sunray DMA version */
26#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
27#define DMA_VERS1 0x80000000 /* DMA rev 1 */
28#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
29#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
30#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
31
32#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
33#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
34#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
35#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
36#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
37#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
38#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
39#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
40#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
41#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
42#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
43#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
44#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
45#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
46#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
47#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
48#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
49#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
50#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
51#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
52#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
53#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
54#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
55#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
56#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
57#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
58#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
59#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
60#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
61#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
62#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
63#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
64#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
65#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
66#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
67#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
68#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
69#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
70#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
71#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
72#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
73
74/* Values describing the burst-size property from the PROM */
75#define DMA_BURST1 0x01
76#define DMA_BURST2 0x02
77#define DMA_BURST4 0x04
78#define DMA_BURST8 0x08
79#define DMA_BURST16 0x10
80#define DMA_BURST32 0x20
81#define DMA_BURST64 0x40
82#define DMA_BURSTBITS 0x7f
83
84/* From PCI */
85
86#ifdef CONFIG_PCI
87extern int isa_dma_bridge_buggy;
5#else 88#else
6#include <asm/dma_32.h> 89#define isa_dma_bridge_buggy (0)
7#endif 90#endif
91
92#ifdef CONFIG_SPARC32
93
94/* Routines for data transfer buffers. */
95BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
96BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
97
98#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
99#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
100
101struct page;
102struct device;
103struct scatterlist;
104
105/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
106BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, struct device *, char *, unsigned long)
107BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct device *, struct scatterlist *, int)
108BTFIXUPDEF_CALL(void, mmu_release_scsi_one, struct device *, __u32, unsigned long)
109BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct device *, struct scatterlist *, int)
110
111#define mmu_get_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_get_scsi_one)(dev,vaddr,len)
112#define mmu_get_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_get_scsi_sgl)(dev,sg,sz)
113#define mmu_release_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_release_scsi_one)(dev,vaddr,len)
114#define mmu_release_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_release_scsi_sgl)(dev,sg,sz)
115
116/*
117 * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
118 *
119 * The mmu_map_dma_area establishes two mappings in one go.
120 * These mappings point to pages normally mapped at 'va' (linear address).
121 * First mapping is for CPU visible address at 'a', uncached.
122 * This is an alias, but it works because it is an uncached mapping.
123 * Second mapping is for device visible address, or "bus" address.
124 * The bus address is returned at '*pba'.
125 *
126 * These functions seem distinct, but are hard to split. On sun4c,
127 * at least for now, 'a' is equal to bus address, and retured in *pba.
128 * On sun4m, page attributes depend on the CPU type, so we have to
129 * know if we are mapping RAM or I/O, so it has to be an additional argument
130 * to a separate mapping function for CPU visible mappings.
131 */
132BTFIXUPDEF_CALL(int, mmu_map_dma_area, struct device *, dma_addr_t *, unsigned long, unsigned long, int len)
133BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, struct device *, unsigned long busa, int len)
134
135#define mmu_map_dma_area(dev,pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(dev,pba,va,a,len)
136#define mmu_unmap_dma_area(dev,ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(dev,ba,len)
8#endif 137#endif
138
139#endif /* !(_ASM_SPARC_DMA_H) */
diff --git a/arch/sparc/include/asm/dma_32.h b/arch/sparc/include/asm/dma_32.h
deleted file mode 100644
index cf7189c0079..00000000000
--- a/arch/sparc/include/asm/dma_32.h
+++ /dev/null
@@ -1,288 +0,0 @@
1/* include/asm/dma.h
2 *
3 * Copyright 1995 (C) David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _ASM_SPARC_DMA_H
7#define _ASM_SPARC_DMA_H
8
9#include <linux/kernel.h>
10#include <linux/types.h>
11
12#include <asm/vac-ops.h> /* for invalidate's, etc. */
13#include <asm/sbus.h>
14#include <asm/delay.h>
15#include <asm/oplib.h>
16#include <asm/system.h>
17#include <asm/io.h>
18#include <linux/spinlock.h>
19
20struct page;
21extern spinlock_t dma_spin_lock;
22
23static inline unsigned long claim_dma_lock(void)
24{
25 unsigned long flags;
26 spin_lock_irqsave(&dma_spin_lock, flags);
27 return flags;
28}
29
30static inline void release_dma_lock(unsigned long flags)
31{
32 spin_unlock_irqrestore(&dma_spin_lock, flags);
33}
34
35/* These are irrelevant for Sparc DMA, but we leave it in so that
36 * things can compile.
37 */
38#define MAX_DMA_CHANNELS 8
39#define MAX_DMA_ADDRESS (~0UL)
40#define DMA_MODE_READ 1
41#define DMA_MODE_WRITE 2
42
43/* Useful constants */
44#define SIZE_16MB (16*1024*1024)
45#define SIZE_64K (64*1024)
46
47/* SBUS DMA controller reg offsets */
48#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
49#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
50#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
51#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
52
53/* DVMA chip revisions */
54enum dvma_rev {
55 dvmarev0,
56 dvmaesc1,
57 dvmarev1,
58 dvmarev2,
59 dvmarev3,
60 dvmarevplus,
61 dvmahme
62};
63
64#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
65
66/* Linux DMA information structure, filled during probe. */
67struct sbus_dma {
68 struct sbus_dma *next;
69 struct sbus_dev *sdev;
70 void __iomem *regs;
71
72 /* Status, misc info */
73 int node; /* Prom node for this DMA device */
74 int running; /* Are we doing DMA now? */
75 int allocated; /* Are we "owned" by anyone yet? */
76
77 /* Transfer information. */
78 unsigned long addr; /* Start address of current transfer */
79 int nbytes; /* Size of current transfer */
80 int realbytes; /* For splitting up large transfers, etc. */
81
82 /* DMA revision */
83 enum dvma_rev revision;
84};
85
86extern struct sbus_dma *dma_chain;
87
88/* Broken hardware... */
89#ifdef CONFIG_SUN4
90/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
91 * Or is rev0 present only on sun4 boxes? -jj */
92#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
93#else
94#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
95#endif
96#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
97
98/* Main routines in dma.c */
99extern void dvma_init(struct sbus_bus *);
100
101/* Fields in the cond_reg register */
102/* First, the version identification bits */
103#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
104#define DMA_VERS0 0x00000000 /* Sunray DMA version */
105#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
106#define DMA_VERS1 0x80000000 /* DMA rev 1 */
107#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
108#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
109#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
110
111#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
112#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
113#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
114#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
115#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
116#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
117#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
118#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
119#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
120#define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */
121#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
122#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
123#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
124#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
125#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
126#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
127#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
128#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
129#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
130#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
131#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
132#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
133#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
134#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
135#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
136#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
137#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
138#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
139#define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */
140#define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */
141#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
142#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
143#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
144#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
145#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
146#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
147#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
148#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
149#define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */
150#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
151#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
152#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
153#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
154
155/* Values describing the burst-size property from the PROM */
156#define DMA_BURST1 0x01
157#define DMA_BURST2 0x02
158#define DMA_BURST4 0x04
159#define DMA_BURST8 0x08
160#define DMA_BURST16 0x10
161#define DMA_BURST32 0x20
162#define DMA_BURST64 0x40
163#define DMA_BURSTBITS 0x7f
164
165/* Determine highest possible final transfer address given a base */
166#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
167
168/* Yes, I hack a lot of elisp in my spare time... */
169#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
170#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
171#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
172#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
173#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
174#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
175#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
176#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
177#define DMA_BEGINDMA_W(regs) \
178 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
179#define DMA_BEGINDMA_R(regs) \
180 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
181
182/* For certain DMA chips, we need to disable ints upon irq entry
183 * and turn them back on when we are done. So in any ESP interrupt
184 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
185 * when leaving the handler. You have been warned...
186 */
187#define DMA_IRQ_ENTRY(dma, dregs) do { \
188 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
189 } while (0)
190
191#define DMA_IRQ_EXIT(dma, dregs) do { \
192 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
193 } while(0)
194
195#if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
196/* Pause until counter runs out or BIT isn't set in the DMA condition
197 * register.
198 */
199static inline void sparc_dma_pause(struct sparc_dma_registers *regs,
200 unsigned long bit)
201{
202 int ctr = 50000; /* Let's find some bugs ;) */
203
204 /* Busy wait until the bit is not set any more */
205 while((regs->cond_reg&bit) && (ctr>0)) {
206 ctr--;
207 __delay(5);
208 }
209
210 /* Check for bogus outcome. */
211 if(!ctr)
212 panic("DMA timeout");
213}
214
215/* Reset the friggin' thing... */
216#define DMA_RESET(dma) do { \
217 struct sparc_dma_registers *regs = dma->regs; \
218 /* Let the current FIFO drain itself */ \
219 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
220 /* Reset the logic */ \
221 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
222 __delay(400); /* let the bits set ;) */ \
223 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
224 sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
225 /* Enable FAST transfers if available */ \
226 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
227 dma->running = 0; \
228} while(0)
229#endif
230
231#define for_each_dvma(dma) \
232 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
233
234extern int get_dma_list(char *);
235extern int request_dma(unsigned int, __const__ char *);
236extern void free_dma(unsigned int);
237
238/* From PCI */
239
240#ifdef CONFIG_PCI
241extern int isa_dma_bridge_buggy;
242#else
243#define isa_dma_bridge_buggy (0)
244#endif
245
246/* Routines for data transfer buffers. */
247BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
248BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
249
250#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
251#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
252
253/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
254BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
255BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
256BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
257BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
258
259#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
260#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
261#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
262#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
263
264/*
265 * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
266 *
267 * The mmu_map_dma_area establishes two mappings in one go.
268 * These mappings point to pages normally mapped at 'va' (linear address).
269 * First mapping is for CPU visible address at 'a', uncached.
270 * This is an alias, but it works because it is an uncached mapping.
271 * Second mapping is for device visible address, or "bus" address.
272 * The bus address is returned at '*pba'.
273 *
274 * These functions seem distinct, but are hard to split. On sun4c,
275 * at least for now, 'a' is equal to bus address, and retured in *pba.
276 * On sun4m, page attributes depend on the CPU type, so we have to
277 * know if we are mapping RAM or I/O, so it has to be an additional argument
278 * to a separate mapping function for CPU visible mappings.
279 */
280BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
281BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
282BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len)
283
284#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
285#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
286#define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba)
287
288#endif /* !(_ASM_SPARC_DMA_H) */
diff --git a/arch/sparc/include/asm/dma_64.h b/arch/sparc/include/asm/dma_64.h
deleted file mode 100644
index 46a8aecffc0..00000000000
--- a/arch/sparc/include/asm/dma_64.h
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * include/asm/dma.h
3 *
4 * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _ASM_SPARC64_DMA_H
8#define _ASM_SPARC64_DMA_H
9
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/spinlock.h>
13
14#include <asm/sbus.h>
15#include <asm/delay.h>
16#include <asm/oplib.h>
17
18/* These are irrelevant for Sparc DMA, but we leave it in so that
19 * things can compile.
20 */
21#define MAX_DMA_CHANNELS 8
22#define DMA_MODE_READ 1
23#define DMA_MODE_WRITE 2
24#define MAX_DMA_ADDRESS (~0UL)
25
26/* Useful constants */
27#define SIZE_16MB (16*1024*1024)
28#define SIZE_64K (64*1024)
29
30/* SBUS DMA controller reg offsets */
31#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
32#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
33#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
34#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
35
36/* DVMA chip revisions */
37enum dvma_rev {
38 dvmarev0,
39 dvmaesc1,
40 dvmarev1,
41 dvmarev2,
42 dvmarev3,
43 dvmarevplus,
44 dvmahme
45};
46
47#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
48
49/* Linux DMA information structure, filled during probe. */
50struct sbus_dma {
51 struct sbus_dma *next;
52 struct sbus_dev *sdev;
53 void __iomem *regs;
54
55 /* Status, misc info */
56 int node; /* Prom node for this DMA device */
57 int running; /* Are we doing DMA now? */
58 int allocated; /* Are we "owned" by anyone yet? */
59
60 /* Transfer information. */
61 u32 addr; /* Start address of current transfer */
62 int nbytes; /* Size of current transfer */
63 int realbytes; /* For splitting up large transfers, etc. */
64
65 /* DMA revision */
66 enum dvma_rev revision;
67};
68
69extern struct sbus_dma *dma_chain;
70
71/* Broken hardware... */
72#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
73#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
74
75/* Main routines in dma.c */
76extern void dvma_init(struct sbus_bus *);
77
78/* Fields in the cond_reg register */
79/* First, the version identification bits */
80#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
81#define DMA_VERS0 0x00000000 /* Sunray DMA version */
82#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
83#define DMA_VERS1 0x80000000 /* DMA rev 1 */
84#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
85#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
86#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
87
88#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
89#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
90#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
91#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
92#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
93#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
94#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
95#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
96#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
97#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
98#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
99#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
100#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
101#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
102#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
103#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
104#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
105#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
106#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
107#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
108#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
109#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
110#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
111#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
112#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
113#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
114#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
115#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
116#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
117#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
118#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
119#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
120#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
121#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
122#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
123#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
124#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
125#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
126#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
127#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
128#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
129
130/* Values describing the burst-size property from the PROM */
131#define DMA_BURST1 0x01
132#define DMA_BURST2 0x02
133#define DMA_BURST4 0x04
134#define DMA_BURST8 0x08
135#define DMA_BURST16 0x10
136#define DMA_BURST32 0x20
137#define DMA_BURST64 0x40
138#define DMA_BURSTBITS 0x7f
139
140/* Determine highest possible final transfer address given a base */
141#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
142
143/* Yes, I hack a lot of elisp in my spare time... */
144#define DMA_ERROR_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
145#define DMA_IRQ_P(regs) ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
146#define DMA_WRITE_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
147#define DMA_OFF(__regs) \
148do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
149 tmp &= ~DMA_ENABLE; \
150 sbus_writel(tmp, (__regs) + DMA_CSR); \
151} while(0)
152#define DMA_INTSOFF(__regs) \
153do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
154 tmp &= ~DMA_INT_ENAB; \
155 sbus_writel(tmp, (__regs) + DMA_CSR); \
156} while(0)
157#define DMA_INTSON(__regs) \
158do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
159 tmp |= DMA_INT_ENAB; \
160 sbus_writel(tmp, (__regs) + DMA_CSR); \
161} while(0)
162#define DMA_PUNTFIFO(__regs) \
163do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
164 tmp |= DMA_FIFO_INV; \
165 sbus_writel(tmp, (__regs) + DMA_CSR); \
166} while(0)
167#define DMA_SETSTART(__regs, __addr) \
168 sbus_writel((u32)(__addr), (__regs) + DMA_ADDR);
169#define DMA_BEGINDMA_W(__regs) \
170do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
171 tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \
172 sbus_writel(tmp, (__regs) + DMA_CSR); \
173} while(0)
174#define DMA_BEGINDMA_R(__regs) \
175do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
176 tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
177 tmp &= ~DMA_ST_WRITE; \
178 sbus_writel(tmp, (__regs) + DMA_CSR); \
179} while(0)
180
181/* For certain DMA chips, we need to disable ints upon irq entry
182 * and turn them back on when we are done. So in any ESP interrupt
183 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
184 * when leaving the handler. You have been warned...
185 */
186#define DMA_IRQ_ENTRY(dma, dregs) do { \
187 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
188 } while (0)
189
190#define DMA_IRQ_EXIT(dma, dregs) do { \
191 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
192 } while(0)
193
194#define for_each_dvma(dma) \
195 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
196
197/* From PCI */
198
199#ifdef CONFIG_PCI
200extern int isa_dma_bridge_buggy;
201#else
202#define isa_dma_bridge_buggy (0)
203#endif
204
205#endif /* !(_ASM_SPARC64_DMA_H) */
diff --git a/arch/sparc/include/asm/ebus.h b/arch/sparc/include/asm/ebus.h
deleted file mode 100644
index 83a6d16c22e..00000000000
--- a/arch/sparc/include/asm/ebus.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_EBUS_H
2#define ___ASM_SPARC_EBUS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm/ebus_64.h>
5#else
6#include <asm/ebus_32.h>
7#endif
8#endif
diff --git a/arch/sparc/include/asm/ebus_32.h b/arch/sparc/include/asm/ebus_32.h
deleted file mode 100644
index f91f0b267ce..00000000000
--- a/arch/sparc/include/asm/ebus_32.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * ebus.h: PCI to Ebus pseudo driver software state.
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 *
6 * Adopted for sparc by V. Roganov and G. Raiko.
7 */
8
9#ifndef __SPARC_EBUS_H
10#define __SPARC_EBUS_H
11
12#ifndef _LINUX_IOPORT_H
13#include <linux/ioport.h>
14#endif
15#include <linux/of_device.h>
16#include <asm/oplib.h>
17#include <asm/prom.h>
18
19struct linux_ebus_child {
20 struct linux_ebus_child *next;
21 struct linux_ebus_device *parent;
22 struct linux_ebus *bus;
23 struct device_node *prom_node;
24 struct resource resource[PROMREG_MAX];
25 int num_addrs;
26 unsigned int irqs[PROMINTR_MAX];
27 int num_irqs;
28};
29
30struct linux_ebus_device {
31 struct of_device ofdev;
32 struct linux_ebus_device *next;
33 struct linux_ebus_child *children;
34 struct linux_ebus *bus;
35 struct device_node *prom_node;
36 struct resource resource[PROMREG_MAX];
37 int num_addrs;
38 unsigned int irqs[PROMINTR_MAX];
39 int num_irqs;
40};
41#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
42
43struct linux_ebus {
44 struct of_device ofdev;
45 struct linux_ebus *next;
46 struct linux_ebus_device *devices;
47 struct linux_pbm_info *parent;
48 struct pci_dev *self;
49 struct device_node *prom_node;
50};
51#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
52
53struct linux_ebus_dma {
54 unsigned int dcsr;
55 unsigned int dacr;
56 unsigned int dbcr;
57};
58
59#define EBUS_DCSR_INT_PEND 0x00000001
60#define EBUS_DCSR_ERR_PEND 0x00000002
61#define EBUS_DCSR_DRAIN 0x00000004
62#define EBUS_DCSR_INT_EN 0x00000010
63#define EBUS_DCSR_RESET 0x00000080
64#define EBUS_DCSR_WRITE 0x00000100
65#define EBUS_DCSR_EN_DMA 0x00000200
66#define EBUS_DCSR_CYC_PEND 0x00000400
67#define EBUS_DCSR_DIAG_RD_DONE 0x00000800
68#define EBUS_DCSR_DIAG_WR_DONE 0x00001000
69#define EBUS_DCSR_EN_CNT 0x00002000
70#define EBUS_DCSR_TC 0x00004000
71#define EBUS_DCSR_DIS_CSR_DRN 0x00010000
72#define EBUS_DCSR_BURST_SZ_MASK 0x000c0000
73#define EBUS_DCSR_BURST_SZ_1 0x00080000
74#define EBUS_DCSR_BURST_SZ_4 0x00000000
75#define EBUS_DCSR_BURST_SZ_8 0x00040000
76#define EBUS_DCSR_BURST_SZ_16 0x000c0000
77#define EBUS_DCSR_DIAG_EN 0x00100000
78#define EBUS_DCSR_DIS_ERR_PEND 0x00400000
79#define EBUS_DCSR_TCI_DIS 0x00800000
80#define EBUS_DCSR_EN_NEXT 0x01000000
81#define EBUS_DCSR_DMA_ON 0x02000000
82#define EBUS_DCSR_A_LOADED 0x04000000
83#define EBUS_DCSR_NA_LOADED 0x08000000
84#define EBUS_DCSR_DEV_ID_MASK 0xf0000000
85
86extern struct linux_ebus *ebus_chain;
87
88extern void ebus_init(void);
89
90#define for_each_ebus(bus) \
91 for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
92
93#define for_each_ebusdev(dev, bus) \
94 for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
95
96#define for_each_edevchild(dev, child) \
97 for((child) = (dev)->children; (child); (child) = (child)->next)
98
99#endif /* !(__SPARC_EBUS_H) */
diff --git a/arch/sparc/include/asm/ebus_64.h b/arch/sparc/include/asm/ebus_64.h
deleted file mode 100644
index 14c6a111f60..00000000000
--- a/arch/sparc/include/asm/ebus_64.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * ebus.h: PCI to Ebus pseudo driver software state.
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
6 */
7
8#ifndef __SPARC64_EBUS_H
9#define __SPARC64_EBUS_H
10
11#include <linux/of_device.h>
12
13#include <asm/oplib.h>
14#include <asm/prom.h>
15
16struct linux_ebus_child {
17 struct linux_ebus_child *next;
18 struct linux_ebus_device *parent;
19 struct linux_ebus *bus;
20 struct device_node *prom_node;
21 struct resource resource[PROMREG_MAX];
22 int num_addrs;
23 unsigned int irqs[PROMINTR_MAX];
24 int num_irqs;
25};
26
27struct linux_ebus_device {
28 struct of_device ofdev;
29 struct linux_ebus_device *next;
30 struct linux_ebus_child *children;
31 struct linux_ebus *bus;
32 struct device_node *prom_node;
33 struct resource resource[PROMREG_MAX];
34 int num_addrs;
35 unsigned int irqs[PROMINTR_MAX];
36 int num_irqs;
37};
38#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
39
40struct linux_ebus {
41 struct of_device ofdev;
42 struct linux_ebus *next;
43 struct linux_ebus_device *devices;
44 struct pci_dev *self;
45 int index;
46 int is_rio;
47 struct device_node *prom_node;
48};
49#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
50
51struct ebus_dma_info {
52 spinlock_t lock;
53 void __iomem *regs;
54
55 unsigned int flags;
56#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER 0x00000001
57#define EBUS_DMA_FLAG_TCI_DISABLE 0x00000002
58
59 /* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
60 * set.
61 */
62 void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
63 void *client_cookie;
64 unsigned int irq;
65#define EBUS_DMA_EVENT_ERROR 1
66#define EBUS_DMA_EVENT_DMA 2
67#define EBUS_DMA_EVENT_DEVICE 4
68
69 unsigned char name[64];
70};
71
72extern int ebus_dma_register(struct ebus_dma_info *p);
73extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
74extern void ebus_dma_unregister(struct ebus_dma_info *p);
75extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
76 size_t len);
77extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
78extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
79extern unsigned int ebus_dma_addr(struct ebus_dma_info *p);
80extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
81
82extern struct linux_ebus *ebus_chain;
83
84extern void ebus_init(void);
85
86#define for_each_ebus(bus) \
87 for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
88
89#define for_each_ebusdev(dev, bus) \
90 for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
91
92#define for_each_edevchild(dev, child) \
93 for((child) = (dev)->children; (child); (child) = (child)->next)
94
95#endif /* !(__SPARC64_EBUS_H) */
diff --git a/arch/sparc/include/asm/ebus_dma.h b/arch/sparc/include/asm/ebus_dma.h
new file mode 100644
index 00000000000..f07a5b541c9
--- /dev/null
+++ b/arch/sparc/include/asm/ebus_dma.h
@@ -0,0 +1,35 @@
1#ifndef __ASM_SPARC_EBUS_DMA_H
2#define __ASM_SPARC_EBUS_DMA_H
3
4struct ebus_dma_info {
5 spinlock_t lock;
6 void __iomem *regs;
7
8 unsigned int flags;
9#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER 0x00000001
10#define EBUS_DMA_FLAG_TCI_DISABLE 0x00000002
11
12 /* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
13 * set.
14 */
15 void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
16 void *client_cookie;
17 unsigned int irq;
18#define EBUS_DMA_EVENT_ERROR 1
19#define EBUS_DMA_EVENT_DMA 2
20#define EBUS_DMA_EVENT_DEVICE 4
21
22 unsigned char name[64];
23};
24
25extern int ebus_dma_register(struct ebus_dma_info *p);
26extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
27extern void ebus_dma_unregister(struct ebus_dma_info *p);
28extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
29 size_t len);
30extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
31extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
32extern unsigned int ebus_dma_addr(struct ebus_dma_info *p);
33extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
34
35#endif /* __ASM_SPARC_EBUS_DMA_H */
diff --git a/arch/sparc/include/asm/elf_32.h b/arch/sparc/include/asm/elf_32.h
index d043f80bc2f..b7ab6054782 100644
--- a/arch/sparc/include/asm/elf_32.h
+++ b/arch/sparc/include/asm/elf_32.h
@@ -105,11 +105,8 @@ typedef struct {
105#define ELF_DATA ELFDATA2MSB 105#define ELF_DATA ELFDATA2MSB
106 106
107#define USE_ELF_CORE_DUMP 107#define USE_ELF_CORE_DUMP
108#ifndef CONFIG_SUN4 108
109#define ELF_EXEC_PAGESIZE 4096 109#define ELF_EXEC_PAGESIZE 4096
110#else
111#define ELF_EXEC_PAGESIZE 8192
112#endif
113 110
114 111
115/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 112/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
@@ -126,7 +123,7 @@ typedef struct {
126/* Sun4c has none of the capabilities, most sun4m's have them all. 123/* Sun4c has none of the capabilities, most sun4m's have them all.
127 * XXX This is gross, set some global variable at boot time. -DaveM 124 * XXX This is gross, set some global variable at boot time. -DaveM
128 */ 125 */
129#define ELF_HWCAP ((ARCH_SUN4C_SUN4) ? 0 : \ 126#define ELF_HWCAP ((ARCH_SUN4C) ? 0 : \
130 (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \ 127 (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
131 HWCAP_SPARC_SWAP | \ 128 HWCAP_SPARC_SWAP | \
132 ((srmmu_modtype != Cypress && \ 129 ((srmmu_modtype != Cypress && \
diff --git a/arch/sparc/include/asm/fhc.h b/arch/sparc/include/asm/fhc.h
index 788cbc46a11..57f1b303ad5 100644
--- a/arch/sparc/include/asm/fhc.h
+++ b/arch/sparc/include/asm/fhc.h
@@ -1,5 +1,4 @@
1/* 1/* fhc.h: FHC and Clock board register definitions.
2 * fhc.h: Structures for central/fhc pseudo driver on Sunfire/Starfire/Wildfire.
3 * 2 *
4 * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com) 3 * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
5 */ 4 */
@@ -7,14 +6,6 @@
7#ifndef _SPARC64_FHC_H 6#ifndef _SPARC64_FHC_H
8#define _SPARC64_FHC_H 7#define _SPARC64_FHC_H
9 8
10#include <linux/timer.h>
11
12#include <asm/oplib.h>
13#include <asm/prom.h>
14#include <asm/upa.h>
15
16struct linux_fhc;
17
18/* Clock board register offsets. */ 9/* Clock board register offsets. */
19#define CLOCK_CTRL 0x00UL /* Main control */ 10#define CLOCK_CTRL 0x00UL /* Main control */
20#define CLOCK_STAT1 0x10UL /* Status one */ 11#define CLOCK_STAT1 0x10UL /* Status one */
@@ -29,21 +20,7 @@ struct linux_fhc;
29#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */ 20#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
30#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */ 21#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
31 22
32struct linux_central {
33 struct linux_fhc *child;
34 unsigned long cfreg;
35 unsigned long clkregs;
36 unsigned long clkver;
37 int slots;
38 struct device_node *prom_node;
39
40 struct linux_prom_ranges central_ranges[PROMREG_MAX];
41 int num_central_ranges;
42};
43
44/* Firehose controller register offsets */ 23/* Firehose controller register offsets */
45struct fhc_regs {
46 unsigned long pregs; /* FHC internal regs */
47#define FHC_PREGS_ID 0x00UL /* FHC ID */ 24#define FHC_PREGS_ID 0x00UL /* FHC ID */
48#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */ 25#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */
49#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */ 26#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */
@@ -90,32 +67,14 @@ struct fhc_regs {
90#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */ 67#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
91#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */ 68#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
92#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */ 69#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */
93 unsigned long ireg; /* FHC IGN reg */
94#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */ 70#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */
95 unsigned long ffregs; /* FHC fanfail regs */
96#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */ 71#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */
97#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */ 72#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */
98 unsigned long sregs; /* FHC system regs */
99#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */ 73#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */
100#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */ 74#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */
101 unsigned long uregs; /* FHC uart regs */
102#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */ 75#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */
103#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */ 76#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */
104 unsigned long tregs; /* FHC TOD regs */
105#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */ 77#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */
106#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */ 78#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */
107};
108
109struct linux_fhc {
110 struct linux_fhc *next;
111 struct linux_central *parent; /* NULL if not central FHC */
112 struct fhc_regs fhc_regs;
113 int board;
114 int jtag_master;
115 struct device_node *prom_node;
116
117 struct linux_prom_ranges fhc_ranges[PROMREG_MAX];
118 int num_fhc_ranges;
119};
120 79
121#endif /* !(_SPARC64_FHC_H) */ 80#endif /* !(_SPARC64_FHC_H) */
diff --git a/arch/sparc/include/asm/floppy_32.h b/arch/sparc/include/asm/floppy_32.h
index ae3f00bf22f..c792830636d 100644
--- a/arch/sparc/include/asm/floppy_32.h
+++ b/arch/sparc/include/asm/floppy_32.h
@@ -6,6 +6,9 @@
6#ifndef __ASM_SPARC_FLOPPY_H 6#ifndef __ASM_SPARC_FLOPPY_H
7#define __ASM_SPARC_FLOPPY_H 7#define __ASM_SPARC_FLOPPY_H
8 8
9#include <linux/of.h>
10#include <linux/of_device.h>
11
9#include <asm/page.h> 12#include <asm/page.h>
10#include <asm/pgtable.h> 13#include <asm/pgtable.h>
11#include <asm/system.h> 14#include <asm/system.h>
@@ -343,7 +346,7 @@ static int sun_floppy_init(void)
343 r.flags = fd_regs[0].which_io; 346 r.flags = fd_regs[0].which_io;
344 r.start = fd_regs[0].phys_addr; 347 r.start = fd_regs[0].phys_addr;
345 sun_fdc = (struct sun_flpy_controller *) 348 sun_fdc = (struct sun_flpy_controller *)
346 sbus_ioremap(&r, 0, fd_regs[0].reg_size, "floppy"); 349 of_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
347 350
348 /* Last minute sanity check... */ 351 /* Last minute sanity check... */
349 if(sun_fdc->status_82072 == 0xff) { 352 if(sun_fdc->status_82072 == 0xff) {
@@ -385,4 +388,15 @@ static int sparc_eject(void)
385 388
386#define EXTRA_FLOPPY_PARAMS 389#define EXTRA_FLOPPY_PARAMS
387 390
391static DEFINE_SPINLOCK(dma_spin_lock);
392
393#define claim_dma_lock() \
394({ unsigned long flags; \
395 spin_lock_irqsave(&dma_spin_lock, flags); \
396 flags; \
397})
398
399#define release_dma_lock(__flags) \
400 spin_unlock_irqrestore(&dma_spin_lock, __flags);
401
388#endif /* !(__ASM_SPARC_FLOPPY_H) */ 402#endif /* !(__ASM_SPARC_FLOPPY_H) */
diff --git a/arch/sparc/include/asm/floppy_64.h b/arch/sparc/include/asm/floppy_64.h
index c39db1060bc..36439d67ad7 100644
--- a/arch/sparc/include/asm/floppy_64.h
+++ b/arch/sparc/include/asm/floppy_64.h
@@ -1,6 +1,6 @@
1/* floppy.h: Sparc specific parts of the Floppy driver. 1/* floppy.h: Sparc specific parts of the Floppy driver.
2 * 2 *
3 * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 1996, 2007, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 4 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * 5 *
6 * Ultra/PCI support added: Sep 1997 Eddie C. Dost (ecd@skynet.be) 6 * Ultra/PCI support added: Sep 1997 Eddie C. Dost (ecd@skynet.be)
@@ -9,18 +9,11 @@
9#ifndef __ASM_SPARC64_FLOPPY_H 9#ifndef __ASM_SPARC64_FLOPPY_H
10#define __ASM_SPARC64_FLOPPY_H 10#define __ASM_SPARC64_FLOPPY_H
11 11
12#include <linux/init.h> 12#include <linux/of.h>
13#include <linux/pci.h> 13#include <linux/of_device.h>
14#include <linux/dma-mapping.h>
14 15
15#include <asm/page.h>
16#include <asm/pgtable.h>
17#include <asm/system.h>
18#include <asm/idprom.h>
19#include <asm/oplib.h>
20#include <asm/auxio.h> 16#include <asm/auxio.h>
21#include <asm/sbus.h>
22#include <asm/irq.h>
23
24 17
25/* 18/*
26 * Define this to enable exchanging drive 0 and 1 if only drive 1 is 19 * Define this to enable exchanging drive 0 and 1 if only drive 1 is
@@ -50,7 +43,7 @@ struct sun_flpy_controller {
50/* You'll only ever find one controller on an Ultra anyways. */ 43/* You'll only ever find one controller on an Ultra anyways. */
51static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1; 44static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1;
52unsigned long fdc_status; 45unsigned long fdc_status;
53static struct sbus_dev *floppy_sdev = NULL; 46static struct of_device *floppy_op = NULL;
54 47
55struct sun_floppy_ops { 48struct sun_floppy_ops {
56 unsigned char (*fd_inb) (unsigned long port); 49 unsigned char (*fd_inb) (unsigned long port);
@@ -291,12 +284,11 @@ static int sun_fd_eject(int drive)
291 return 0; 284 return 0;
292} 285}
293 286
294#ifdef CONFIG_PCI 287#include <asm/ebus_dma.h>
295#include <asm/ebus.h>
296#include <asm/ns87303.h> 288#include <asm/ns87303.h>
297 289
298static struct ebus_dma_info sun_pci_fd_ebus_dma; 290static struct ebus_dma_info sun_pci_fd_ebus_dma;
299static struct pci_dev *sun_pci_ebus_dev; 291static struct device *sun_floppy_dev;
300static int sun_pci_broken_drive = -1; 292static int sun_pci_broken_drive = -1;
301 293
302struct sun_pci_dma_op { 294struct sun_pci_dma_op {
@@ -377,7 +369,7 @@ static void sun_pci_fd_enable_dma(void)
377 sun_pci_dma_pending.addr = -1U; 369 sun_pci_dma_pending.addr = -1U;
378 370
379 sun_pci_dma_current.addr = 371 sun_pci_dma_current.addr =
380 pci_map_single(sun_pci_ebus_dev, 372 dma_map_single(sun_floppy_dev,
381 sun_pci_dma_current.buf, 373 sun_pci_dma_current.buf,
382 sun_pci_dma_current.len, 374 sun_pci_dma_current.len,
383 sun_pci_dma_current.direction); 375 sun_pci_dma_current.direction);
@@ -394,7 +386,7 @@ static void sun_pci_fd_disable_dma(void)
394{ 386{
395 ebus_dma_enable(&sun_pci_fd_ebus_dma, 0); 387 ebus_dma_enable(&sun_pci_fd_ebus_dma, 0);
396 if (sun_pci_dma_current.addr != -1U) 388 if (sun_pci_dma_current.addr != -1U)
397 pci_unmap_single(sun_pci_ebus_dev, 389 dma_unmap_single(sun_floppy_dev,
398 sun_pci_dma_current.addr, 390 sun_pci_dma_current.addr,
399 sun_pci_dma_current.len, 391 sun_pci_dma_current.len,
400 sun_pci_dma_current.direction); 392 sun_pci_dma_current.direction);
@@ -404,9 +396,9 @@ static void sun_pci_fd_disable_dma(void)
404static void sun_pci_fd_set_dma_mode(int mode) 396static void sun_pci_fd_set_dma_mode(int mode)
405{ 397{
406 if (mode == DMA_MODE_WRITE) 398 if (mode == DMA_MODE_WRITE)
407 sun_pci_dma_pending.direction = PCI_DMA_TODEVICE; 399 sun_pci_dma_pending.direction = DMA_TO_DEVICE;
408 else 400 else
409 sun_pci_dma_pending.direction = PCI_DMA_FROMDEVICE; 401 sun_pci_dma_pending.direction = DMA_FROM_DEVICE;
410 402
411 ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE); 403 ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE);
412} 404}
@@ -538,80 +530,84 @@ static int sun_pci_fd_test_drive(unsigned long port, int drive)
538#undef MSR 530#undef MSR
539#undef DOR 531#undef DOR
540 532
541#endif /* CONFIG_PCI */ 533static int __init ebus_fdthree_p(struct device_node *dp)
542
543#ifdef CONFIG_PCI
544static int __init ebus_fdthree_p(struct linux_ebus_device *edev)
545{ 534{
546 if (!strcmp(edev->prom_node->name, "fdthree")) 535 if (!strcmp(dp->name, "fdthree"))
547 return 1; 536 return 1;
548 if (!strcmp(edev->prom_node->name, "floppy")) { 537 if (!strcmp(dp->name, "floppy")) {
549 const char *compat; 538 const char *compat;
550 539
551 compat = of_get_property(edev->prom_node, 540 compat = of_get_property(dp, "compatible", NULL);
552 "compatible", NULL);
553 if (compat && !strcmp(compat, "fdthree")) 541 if (compat && !strcmp(compat, "fdthree"))
554 return 1; 542 return 1;
555 } 543 }
556 return 0; 544 return 0;
557} 545}
558#endif
559 546
560static unsigned long __init sun_floppy_init(void) 547static unsigned long __init sun_floppy_init(void)
561{ 548{
562 char state[128];
563 struct sbus_bus *bus;
564 struct sbus_dev *sdev = NULL;
565 static int initialized = 0; 549 static int initialized = 0;
550 struct device_node *dp;
551 struct of_device *op;
552 const char *prop;
553 char state[128];
566 554
567 if (initialized) 555 if (initialized)
568 return sun_floppy_types[0]; 556 return sun_floppy_types[0];
569 initialized = 1; 557 initialized = 1;
570 558
571 for_all_sbusdev (sdev, bus) { 559 op = NULL;
572 if (!strcmp(sdev->prom_name, "SUNW,fdtwo")) 560
561 for_each_node_by_name(dp, "SUNW,fdtwo") {
562 if (strcmp(dp->parent->name, "sbus"))
563 continue;
564 op = of_find_device_by_node(dp);
565 if (op)
573 break; 566 break;
574 } 567 }
575 if(sdev) { 568 if (op) {
576 floppy_sdev = sdev; 569 floppy_op = op;
577 FLOPPY_IRQ = sdev->irqs[0]; 570 FLOPPY_IRQ = op->irqs[0];
578 } else { 571 } else {
579#ifdef CONFIG_PCI 572 struct device_node *ebus_dp;
580 struct linux_ebus *ebus;
581 struct linux_ebus_device *edev = NULL;
582 unsigned long config = 0;
583 void __iomem *auxio_reg; 573 void __iomem *auxio_reg;
584 const char *state_prop; 574 const char *state_prop;
575 unsigned long config;
585 576
586 for_each_ebus(ebus) { 577 dp = NULL;
587 for_each_ebusdev(edev, ebus) { 578 for_each_node_by_name(ebus_dp, "ebus") {
588 if (ebus_fdthree_p(edev)) 579 for (dp = ebus_dp->child; dp; dp = dp->sibling) {
589 goto ebus_done; 580 if (ebus_fdthree_p(dp))
581 goto found_fdthree;
590 } 582 }
591 } 583 }
592 ebus_done: 584 found_fdthree:
593 if (!edev) 585 if (!dp)
586 return 0;
587
588 op = of_find_device_by_node(dp);
589 if (!op)
594 return 0; 590 return 0;
595 591
596 state_prop = of_get_property(edev->prom_node, "status", NULL); 592 state_prop = of_get_property(op->node, "status", NULL);
597 if (state_prop && !strncmp(state_prop, "disabled", 8)) 593 if (state_prop && !strncmp(state_prop, "disabled", 8))
598 return 0; 594 return 0;
599 595
600 FLOPPY_IRQ = edev->irqs[0]; 596 FLOPPY_IRQ = op->irqs[0];
601 597
602 /* Make sure the high density bit is set, some systems 598 /* Make sure the high density bit is set, some systems
603 * (most notably Ultra5/Ultra10) come up with it clear. 599 * (most notably Ultra5/Ultra10) come up with it clear.
604 */ 600 */
605 auxio_reg = (void __iomem *) edev->resource[2].start; 601 auxio_reg = (void __iomem *) op->resource[2].start;
606 writel(readl(auxio_reg)|0x2, auxio_reg); 602 writel(readl(auxio_reg)|0x2, auxio_reg);
607 603
608 sun_pci_ebus_dev = ebus->self; 604 sun_floppy_dev = &op->dev;
609 605
610 spin_lock_init(&sun_pci_fd_ebus_dma.lock); 606 spin_lock_init(&sun_pci_fd_ebus_dma.lock);
611 607
612 /* XXX ioremap */ 608 /* XXX ioremap */
613 sun_pci_fd_ebus_dma.regs = (void __iomem *) 609 sun_pci_fd_ebus_dma.regs = (void __iomem *)
614 edev->resource[1].start; 610 op->resource[1].start;
615 if (!sun_pci_fd_ebus_dma.regs) 611 if (!sun_pci_fd_ebus_dma.regs)
616 return 0; 612 return 0;
617 613
@@ -625,7 +621,7 @@ static unsigned long __init sun_floppy_init(void)
625 return 0; 621 return 0;
626 622
627 /* XXX ioremap */ 623 /* XXX ioremap */
628 sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start; 624 sun_fdc = (struct sun_flpy_controller *) op->resource[0].start;
629 625
630 sun_fdops.fd_inb = sun_pci_fd_inb; 626 sun_fdops.fd_inb = sun_pci_fd_inb;
631 sun_fdops.fd_outb = sun_pci_fd_outb; 627 sun_fdops.fd_outb = sun_pci_fd_outb;
@@ -662,12 +658,15 @@ static unsigned long __init sun_floppy_init(void)
662 /* 658 /*
663 * Find NS87303 SuperIO config registers (through ecpp). 659 * Find NS87303 SuperIO config registers (through ecpp).
664 */ 660 */
665 for_each_ebus(ebus) { 661 config = 0;
666 for_each_ebusdev(edev, ebus) { 662 for (dp = ebus_dp->child; dp; dp = dp->sibling) {
667 if (!strcmp(edev->prom_node->name, "ecpp")) { 663 if (!strcmp(dp->name, "ecpp")) {
668 config = edev->resource[1].start; 664 struct of_device *ecpp_op;
669 goto config_done; 665
670 } 666 ecpp_op = of_find_device_by_node(dp);
667 if (ecpp_op)
668 config = ecpp_op->resource[1].start;
669 goto config_done;
671 } 670 }
672 } 671 }
673 config_done: 672 config_done:
@@ -716,26 +715,23 @@ static unsigned long __init sun_floppy_init(void)
716#endif /* PCI_FDC_SWAP_DRIVES */ 715#endif /* PCI_FDC_SWAP_DRIVES */
717 716
718 return sun_floppy_types[0]; 717 return sun_floppy_types[0];
719#else
720 return 0;
721#endif
722 } 718 }
723 prom_getproperty(sdev->prom_node, "status", state, sizeof(state)); 719 prop = of_get_property(op->node, "status", NULL);
724 if(!strncmp(state, "disabled", 8)) 720 if (prop && !strncmp(state, "disabled", 8))
725 return 0; 721 return 0;
726 722
727 /* 723 /*
728 * We cannot do sbus_ioremap here: it does request_region, 724 * We cannot do of_ioremap here: it does request_region,
729 * which the generic floppy driver tries to do once again. 725 * which the generic floppy driver tries to do once again.
730 * But we must use the sdev resource values as they have 726 * But we must use the sdev resource values as they have
731 * had parent ranges applied. 727 * had parent ranges applied.
732 */ 728 */
733 sun_fdc = (struct sun_flpy_controller *) 729 sun_fdc = (struct sun_flpy_controller *)
734 (sdev->resource[0].start + 730 (op->resource[0].start +
735 ((sdev->resource[0].flags & 0x1ffUL) << 32UL)); 731 ((op->resource[0].flags & 0x1ffUL) << 32UL));
736 732
737 /* Last minute sanity check... */ 733 /* Last minute sanity check... */
738 if(sbus_readb(&sun_fdc->status1_82077) == 0xff) { 734 if (sbus_readb(&sun_fdc->status1_82077) == 0xff) {
739 sun_fdc = (struct sun_flpy_controller *)-1; 735 sun_fdc = (struct sun_flpy_controller *)-1;
740 return 0; 736 return 0;
741 } 737 }
diff --git a/arch/sparc/include/asm/gpio.h b/arch/sparc/include/asm/gpio.h
new file mode 100644
index 00000000000..a0e3ac0af59
--- /dev/null
+++ b/arch/sparc/include/asm/gpio.h
@@ -0,0 +1,36 @@
1#ifndef __ASM_SPARC_GPIO_H
2#define __ASM_SPARC_GPIO_H
3
4#include <linux/errno.h>
5#include <asm-generic/gpio.h>
6
7#ifdef CONFIG_GPIOLIB
8
9static inline int gpio_get_value(unsigned int gpio)
10{
11 return __gpio_get_value(gpio);
12}
13
14static inline void gpio_set_value(unsigned int gpio, int value)
15{
16 __gpio_set_value(gpio, value);
17}
18
19static inline int gpio_cansleep(unsigned int gpio)
20{
21 return __gpio_cansleep(gpio);
22}
23
24static inline int gpio_to_irq(unsigned int gpio)
25{
26 return -ENOSYS;
27}
28
29static inline int irq_to_gpio(unsigned int irq)
30{
31 return -EINVAL;
32}
33
34#endif /* CONFIG_GPIOLIB */
35
36#endif /* __ASM_SPARC_GPIO_H */
diff --git a/arch/sparc/include/asm/io-unit.h b/arch/sparc/include/asm/io-unit.h
index 96823b47fd4..01ab2f613e9 100644
--- a/arch/sparc/include/asm/io-unit.h
+++ b/arch/sparc/include/asm/io-unit.h
@@ -55,8 +55,4 @@ struct iounit_struct {
55#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END 55#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END
56#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT) 56#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
57 57
58extern __u32 iounit_map_dma_init(struct sbus_bus *, int);
59#define iounit_map_dma_finish(sbus, addr, len) mmu_release_scsi_one(addr, len, sbus)
60extern __u32 iounit_map_dma_page(__u32, void *, struct sbus_bus *);
61
62#endif /* !(_SPARC_IO_UNIT_H) */ 58#endif /* !(_SPARC_IO_UNIT_H) */
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index 10d7da45007..93fe21e02c8 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -293,14 +293,6 @@ extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
293extern void pci_iounmap(struct pci_dev *dev, void __iomem *); 293extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
294 294
295/* 295/*
296 * Bus number may be in res->flags... somewhere.
297 */
298extern void __iomem *sbus_ioremap(struct resource *res, unsigned long offset,
299 unsigned long size, char *name);
300extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
301
302
303/*
304 * At the moment, we do not use CMOS_READ anywhere outside of rtc.c, 296 * At the moment, we do not use CMOS_READ anywhere outside of rtc.c,
305 * so rtc_port is static in it. This should not change unless a new 297 * so rtc_port is static in it. This should not change unless a new
306 * hardware pops up. 298 * hardware pops up.
@@ -308,6 +300,17 @@ extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
308#define RTC_PORT(x) (rtc_port + (x)) 300#define RTC_PORT(x) (rtc_port + (x))
309#define RTC_ALWAYS_BCD 0 301#define RTC_ALWAYS_BCD 0
310 302
303static inline int sbus_can_dma_64bit(void)
304{
305 return 0; /* actually, sparc_cpu_model==sun4d */
306}
307static inline int sbus_can_burst64(void)
308{
309 return 0; /* actually, sparc_cpu_model==sun4d */
310}
311struct device;
312extern void sbus_set_sbus64(struct device *, int);
313
311#endif 314#endif
312 315
313#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1 316#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 0bff078ffdd..4aee21dc9c6 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -482,18 +482,16 @@ struct pci_dev;
482extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); 482extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
483extern void pci_iounmap(struct pci_dev *dev, void __iomem *); 483extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
484 484
485/* Similarly for SBUS. */ 485static inline int sbus_can_dma_64bit(void)
486#define sbus_ioremap(__res, __offset, __size, __name) \ 486{
487({ unsigned long __ret; \ 487 return 1;
488 __ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \ 488}
489 __ret += (unsigned long) (__offset); \ 489static inline int sbus_can_burst64(void)
490 if (! request_region((__ret), (__size), (__name))) \ 490{
491 __ret = 0UL; \ 491 return 1;
492 (void __iomem *) __ret; \ 492}
493}) 493struct device;
494 494extern void sbus_set_sbus64(struct device *, int);
495#define sbus_iounmap(__addr, __size) \
496 release_region((unsigned long)(__addr), (__size))
497 495
498/* 496/*
499 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 497 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/arch/sparc/include/asm/iommu_64.h b/arch/sparc/include/asm/iommu_64.h
index d7b9afcba08..caf798b5619 100644
--- a/arch/sparc/include/asm/iommu_64.h
+++ b/arch/sparc/include/asm/iommu_64.h
@@ -48,6 +48,9 @@ struct strbuf {
48 unsigned long strbuf_control; 48 unsigned long strbuf_control;
49 unsigned long strbuf_pflush; 49 unsigned long strbuf_pflush;
50 unsigned long strbuf_fsync; 50 unsigned long strbuf_fsync;
51 unsigned long strbuf_err_stat;
52 unsigned long strbuf_tag_diag;
53 unsigned long strbuf_line_diag;
51 unsigned long strbuf_ctxflush; 54 unsigned long strbuf_ctxflush;
52 unsigned long strbuf_ctxmatch_base; 55 unsigned long strbuf_ctxmatch_base;
53 unsigned long strbuf_flushflag_pa; 56 unsigned long strbuf_flushflag_pa;
diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h
index e3dd9303643..71673eca366 100644
--- a/arch/sparc/include/asm/irq_64.h
+++ b/arch/sparc/include/asm/irq_64.h
@@ -56,7 +56,6 @@ extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
56 unsigned long imap_base, 56 unsigned long imap_base,
57 unsigned long iclr_base); 57 unsigned long iclr_base);
58extern void sun4u_destroy_msi(unsigned int virt_irq); 58extern void sun4u_destroy_msi(unsigned int virt_irq);
59extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
60 59
61extern unsigned char virt_irq_alloc(unsigned int dev_handle, 60extern unsigned char virt_irq_alloc(unsigned int dev_handle,
62 unsigned int dev_ino); 61 unsigned int dev_ino);
diff --git a/arch/sparc/include/asm/mc146818rtc_64.h b/arch/sparc/include/asm/mc146818rtc_64.h
index e9c0fcc25c6..7238d174e0e 100644
--- a/arch/sparc/include/asm/mc146818rtc_64.h
+++ b/arch/sparc/include/asm/mc146818rtc_64.h
@@ -7,12 +7,8 @@
7#include <asm/io.h> 7#include <asm/io.h>
8 8
9#ifndef RTC_PORT 9#ifndef RTC_PORT
10#ifdef CONFIG_PCI 10extern unsigned long cmos_regs;
11extern unsigned long ds1287_regs; 11#define RTC_PORT(x) (cmos_regs + (x))
12#else
13#define ds1287_regs (0UL)
14#endif
15#define RTC_PORT(x) (ds1287_regs + (x))
16#define RTC_ALWAYS_BCD 0 12#define RTC_ALWAYS_BCD 0
17#endif 13#endif
18 14
@@ -29,6 +25,4 @@ outb_p((addr),RTC_PORT(0)); \
29outb_p((val),RTC_PORT(1)); \ 25outb_p((val),RTC_PORT(1)); \
30}) 26})
31 27
32#define RTC_IRQ 8
33
34#endif /* __ASM_SPARC64_MC146818RTC_H */ 28#endif /* __ASM_SPARC64_MC146818RTC_H */
diff --git a/arch/sparc/include/asm/memctrl.h b/arch/sparc/include/asm/memctrl.h
new file mode 100644
index 00000000000..4065c56af7b
--- /dev/null
+++ b/arch/sparc/include/asm/memctrl.h
@@ -0,0 +1,9 @@
1#ifndef _SPARC_MEMCTRL_H
2#define _SPARC_MEMCTRL_H
3
4typedef int (*dimm_printer_t)(int synd_code, unsigned long paddr, char *buf, int buflen);
5
6int register_dimm_printer(dimm_printer_t func);
7void unregister_dimm_printer(dimm_printer_t func);
8
9#endif /* _SPARC_MEMCTRL_H */
diff --git a/arch/sparc/include/asm/mostek.h b/arch/sparc/include/asm/mostek.h
deleted file mode 100644
index 433be3e0a69..00000000000
--- a/arch/sparc/include/asm/mostek.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_MOSTEK_H
2#define ___ASM_SPARC_MOSTEK_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm/mostek_64.h>
5#else
6#include <asm/mostek_32.h>
7#endif
8#endif
diff --git a/arch/sparc/include/asm/mostek_32.h b/arch/sparc/include/asm/mostek_32.h
deleted file mode 100644
index a99590c4c50..00000000000
--- a/arch/sparc/include/asm/mostek_32.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * mostek.h: Describes the various Mostek time of day clock registers.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
6 * Added intersil code 05/25/98 Chris Davis (cdavis@cois.on.ca)
7 */
8
9#ifndef _SPARC_MOSTEK_H
10#define _SPARC_MOSTEK_H
11
12#include <asm/idprom.h>
13#include <asm/io.h>
14
15/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
16 *
17 * Data
18 * Address Function
19 * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
20 * 7ff - - - - - - - - Year 00-99
21 * 7fe 0 0 0 - - - - - Month 01-12
22 * 7fd 0 0 - - - - - - Date 01-31
23 * 7fc 0 FT 0 0 0 - - - Day 01-07
24 * 7fb KS 0 - - - - - - Hours 00-23
25 * 7fa 0 - - - - - - - Minutes 00-59
26 * 7f9 ST - - - - - - - Seconds 00-59
27 * 7f8 W R S - - - - - Control
28 *
29 * * ST is STOP BIT
30 * * W is WRITE BIT
31 * * R is READ BIT
32 * * S is SIGN BIT
33 * * FT is FREQ TEST BIT
34 * * KS is KICK START BIT
35 */
36
37/* The Mostek 48t02 real time clock and NVRAM chip. The registers
38 * other than the control register are in binary coded decimal. Some
39 * control bits also live outside the control register.
40 */
41#define mostek_read(_addr) readb(_addr)
42#define mostek_write(_addr,_val) writeb(_val, _addr)
43#define MOSTEK_EEPROM 0x0000UL
44#define MOSTEK_IDPROM 0x07d8UL
45#define MOSTEK_CREG 0x07f8UL
46#define MOSTEK_SEC 0x07f9UL
47#define MOSTEK_MIN 0x07faUL
48#define MOSTEK_HOUR 0x07fbUL
49#define MOSTEK_DOW 0x07fcUL
50#define MOSTEK_DOM 0x07fdUL
51#define MOSTEK_MONTH 0x07feUL
52#define MOSTEK_YEAR 0x07ffUL
53
54struct mostek48t02 {
55 volatile char eeprom[2008]; /* This is the eeprom, don't touch! */
56 struct idprom idprom; /* The idprom lives here. */
57 volatile unsigned char creg; /* Control register */
58 volatile unsigned char sec; /* Seconds (0-59) */
59 volatile unsigned char min; /* Minutes (0-59) */
60 volatile unsigned char hour; /* Hour (0-23) */
61 volatile unsigned char dow; /* Day of the week (1-7) */
62 volatile unsigned char dom; /* Day of the month (1-31) */
63 volatile unsigned char month; /* Month of year (1-12) */
64 volatile unsigned char year; /* Year (0-99) */
65};
66
67extern spinlock_t mostek_lock;
68extern void __iomem *mstk48t02_regs;
69
70/* Control register values. */
71#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
72#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
73#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
74
75/* Control bits that live in the other registers. */
76#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
77#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
78#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
79
80#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
81#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
82
83/* Masks that define how much space each value takes up. */
84#define MSTK_SEC_MASK 0x7f
85#define MSTK_MIN_MASK 0x7f
86#define MSTK_HOUR_MASK 0x3f
87#define MSTK_DOW_MASK 0x07
88#define MSTK_DOM_MASK 0x3f
89#define MSTK_MONTH_MASK 0x1f
90#define MSTK_YEAR_MASK 0xffU
91
92/* Binary coded decimal conversion macros. */
93#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
94#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
95
96/* Generic register set and get macros for internal use. */
97#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(((struct mostek48t02 *)regs)->var & MSTK_ ## mask ## _MASK))
98#define MSTK_SET(regs,var,value,mask) do { ((struct mostek48t02 *)regs)->var &= ~(MSTK_ ## mask ## _MASK); ((struct mostek48t02 *)regs)->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0)
99
100/* Macros to make register access easier on our fingers. These give you
101 * the decimal value of the register requested if applicable. You pass
102 * the a pointer to a 'struct mostek48t02'.
103 */
104#define MSTK_REG_CREG(regs) (((struct mostek48t02 *)regs)->creg)
105#define MSTK_REG_SEC(regs) MSTK_GET(regs,sec,SEC)
106#define MSTK_REG_MIN(regs) MSTK_GET(regs,min,MIN)
107#define MSTK_REG_HOUR(regs) MSTK_GET(regs,hour,HOUR)
108#define MSTK_REG_DOW(regs) MSTK_GET(regs,dow,DOW)
109#define MSTK_REG_DOM(regs) MSTK_GET(regs,dom,DOM)
110#define MSTK_REG_MONTH(regs) MSTK_GET(regs,month,MONTH)
111#define MSTK_REG_YEAR(regs) MSTK_GET(regs,year,YEAR)
112
113#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,sec,value,SEC)
114#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,min,value,MIN)
115#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,hour,value,HOUR)
116#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,dow,value,DOW)
117#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,dom,value,DOM)
118#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,month,value,MONTH)
119#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,year,value,YEAR)
120
121
122/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
123 * same (basically) layout of the 48t02 chip except for the extra
124 * NVRAM on board (8 KB against the 48t02's 2 KB).
125 */
126struct mostek48t08 {
127 char offset[6*1024]; /* Magic things may be here, who knows? */
128 struct mostek48t02 regs; /* Here is what we are interested in. */
129};
130
131#ifdef CONFIG_SUN4
132enum sparc_clock_type { MSTK48T02, MSTK48T08, \
133INTERSIL, MSTK_INVALID };
134#else
135enum sparc_clock_type { MSTK48T02, MSTK48T08, \
136MSTK_INVALID };
137#endif
138
139#ifdef CONFIG_SUN4
140/* intersil on a sun 4/260 code data from harris doc */
141struct intersil_dt {
142 volatile unsigned char int_csec;
143 volatile unsigned char int_hour;
144 volatile unsigned char int_min;
145 volatile unsigned char int_sec;
146 volatile unsigned char int_month;
147 volatile unsigned char int_day;
148 volatile unsigned char int_year;
149 volatile unsigned char int_dow;
150};
151
152struct intersil {
153 struct intersil_dt clk;
154 struct intersil_dt cmp;
155 volatile unsigned char int_intr_reg;
156 volatile unsigned char int_cmd_reg;
157};
158
159#define INTERSIL_STOP 0x0
160#define INTERSIL_START 0x8
161#define INTERSIL_INTR_DISABLE 0x0
162#define INTERSIL_INTR_ENABLE 0x10
163#define INTERSIL_32K 0x0
164#define INTERSIL_NORMAL 0x0
165#define INTERSIL_24H 0x4
166#define INTERSIL_INT_100HZ 0x2
167
168/* end of intersil info */
169#endif
170
171#endif /* !(_SPARC_MOSTEK_H) */
diff --git a/arch/sparc/include/asm/mostek_64.h b/arch/sparc/include/asm/mostek_64.h
deleted file mode 100644
index c5652de2ace..00000000000
--- a/arch/sparc/include/asm/mostek_64.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/* mostek.h: Describes the various Mostek time of day clock registers.
2 *
3 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 */
6
7#ifndef _SPARC64_MOSTEK_H
8#define _SPARC64_MOSTEK_H
9
10#include <asm/idprom.h>
11
12/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
13 *
14 * Data
15 * Address Function
16 * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
17 * 7ff - - - - - - - - Year 00-99
18 * 7fe 0 0 0 - - - - - Month 01-12
19 * 7fd 0 0 - - - - - - Date 01-31
20 * 7fc 0 FT 0 0 0 - - - Day 01-07
21 * 7fb KS 0 - - - - - - Hours 00-23
22 * 7fa 0 - - - - - - - Minutes 00-59
23 * 7f9 ST - - - - - - - Seconds 00-59
24 * 7f8 W R S - - - - - Control
25 *
26 * * ST is STOP BIT
27 * * W is WRITE BIT
28 * * R is READ BIT
29 * * S is SIGN BIT
30 * * FT is FREQ TEST BIT
31 * * KS is KICK START BIT
32 */
33
34/* The Mostek 48t02 real time clock and NVRAM chip. The registers
35 * other than the control register are in binary coded decimal. Some
36 * control bits also live outside the control register.
37 *
38 * We now deal with physical addresses for I/O to the chip. -DaveM
39 */
40static inline u8 mostek_read(void __iomem *addr)
41{
42 u8 ret;
43
44 __asm__ __volatile__("lduba [%1] %2, %0"
45 : "=r" (ret)
46 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
47 return ret;
48}
49
50static inline void mostek_write(void __iomem *addr, u8 val)
51{
52 __asm__ __volatile__("stba %0, [%1] %2"
53 : /* no outputs */
54 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
55}
56
57#define MOSTEK_EEPROM 0x0000UL
58#define MOSTEK_IDPROM 0x07d8UL
59#define MOSTEK_CREG 0x07f8UL
60#define MOSTEK_SEC 0x07f9UL
61#define MOSTEK_MIN 0x07faUL
62#define MOSTEK_HOUR 0x07fbUL
63#define MOSTEK_DOW 0x07fcUL
64#define MOSTEK_DOM 0x07fdUL
65#define MOSTEK_MONTH 0x07feUL
66#define MOSTEK_YEAR 0x07ffUL
67
68extern spinlock_t mostek_lock;
69extern void __iomem *mstk48t02_regs;
70
71/* Control register values. */
72#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
73#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
74#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
75
76/* Control bits that live in the other registers. */
77#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
78#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
79#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
80
81#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
82#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
83
84/* Masks that define how much space each value takes up. */
85#define MSTK_SEC_MASK 0x7f
86#define MSTK_MIN_MASK 0x7f
87#define MSTK_HOUR_MASK 0x3f
88#define MSTK_DOW_MASK 0x07
89#define MSTK_DOM_MASK 0x3f
90#define MSTK_MONTH_MASK 0x1f
91#define MSTK_YEAR_MASK 0xffU
92
93/* Binary coded decimal conversion macros. */
94#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
95#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
96
97/* Generic register set and get macros for internal use. */
98#define MSTK_GET(regs,name) \
99 (MSTK_REGVAL_TO_DECIMAL(mostek_read(regs + MOSTEK_ ## name) & MSTK_ ## name ## _MASK))
100#define MSTK_SET(regs,name,value) \
101do { u8 __val = mostek_read(regs + MOSTEK_ ## name); \
102 __val &= ~(MSTK_ ## name ## _MASK); \
103 __val |= (MSTK_DECIMAL_TO_REGVAL(value) & \
104 (MSTK_ ## name ## _MASK)); \
105 mostek_write(regs + MOSTEK_ ## name, __val); \
106} while(0)
107
108/* Macros to make register access easier on our fingers. These give you
109 * the decimal value of the register requested if applicable. You pass
110 * the a pointer to a 'struct mostek48t02'.
111 */
112#define MSTK_REG_CREG(regs) (mostek_read((regs) + MOSTEK_CREG))
113#define MSTK_REG_SEC(regs) MSTK_GET(regs,SEC)
114#define MSTK_REG_MIN(regs) MSTK_GET(regs,MIN)
115#define MSTK_REG_HOUR(regs) MSTK_GET(regs,HOUR)
116#define MSTK_REG_DOW(regs) MSTK_GET(regs,DOW)
117#define MSTK_REG_DOM(regs) MSTK_GET(regs,DOM)
118#define MSTK_REG_MONTH(regs) MSTK_GET(regs,MONTH)
119#define MSTK_REG_YEAR(regs) MSTK_GET(regs,YEAR)
120
121#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,SEC,value)
122#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,MIN,value)
123#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,HOUR,value)
124#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,DOW,value)
125#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,DOM,value)
126#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,MONTH,value)
127#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,YEAR,value)
128
129
130/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
131 * same (basically) layout of the 48t02 chip except for the extra
132 * NVRAM on board (8 KB against the 48t02's 2 KB).
133 */
134#define MOSTEK_48T08_OFFSET 0x0000UL /* Lower NVRAM portions */
135#define MOSTEK_48T08_48T02 0x1800UL /* Offset to 48T02 chip */
136
137/* SUN5 systems usually have 48t59 model clock chipsets. But we keep the older
138 * clock chip definitions around just in case.
139 */
140#define MOSTEK_48T59_OFFSET 0x0000UL /* Lower NVRAM portions */
141#define MOSTEK_48T59_48T02 0x1800UL /* Offset to 48T02 chip */
142
143#endif /* !(_SPARC64_MOSTEK_H) */
diff --git a/arch/sparc/include/asm/obio.h b/arch/sparc/include/asm/obio.h
index 1a7544ceb57..4ade0c8a2c7 100644
--- a/arch/sparc/include/asm/obio.h
+++ b/arch/sparc/include/asm/obio.h
@@ -155,17 +155,6 @@ static inline void bw_set_ctrl(int cpu, unsigned ctrl)
155 "i" (ASI_M_CTL)); 155 "i" (ASI_M_CTL));
156} 156}
157 157
158extern unsigned char cpu_leds[32];
159
160static inline void show_leds(int cpuid)
161{
162 cpuid &= 0x1e;
163 __asm__ __volatile__ ("stba %0, [%1] %2" : :
164 "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
165 "r" (ECSR_BASE(cpuid) | BB_LEDS),
166 "i" (ASI_M_CTL));
167}
168
169static inline unsigned cc_get_ipen(void) 158static inline unsigned cc_get_ipen(void)
170{ 159{
171 unsigned pending; 160 unsigned pending;
diff --git a/arch/sparc/include/asm/of_device.h b/arch/sparc/include/asm/of_device.h
index bba777a416d..a5d9811f969 100644
--- a/arch/sparc/include/asm/of_device.h
+++ b/arch/sparc/include/asm/of_device.h
@@ -30,6 +30,8 @@ struct of_device
30extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name); 30extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
31extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size); 31extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
32 32
33extern void of_propagate_archdata(struct of_device *bus);
34
33/* This is just here during the transition */ 35/* This is just here during the transition */
34#include <linux/of_platform.h> 36#include <linux/of_platform.h>
35 37
diff --git a/arch/sparc/include/asm/of_platform.h b/arch/sparc/include/asm/of_platform.h
index 2348ab90a57..90da99059f8 100644
--- a/arch/sparc/include/asm/of_platform.h
+++ b/arch/sparc/include/asm/of_platform.h
@@ -13,9 +13,6 @@
13 * 13 *
14 */ 14 */
15 15
16extern struct bus_type ebus_bus_type;
17extern struct bus_type sbus_bus_type;
18
19#define of_bus_type of_platform_bus_type /* for compatibility */ 16#define of_bus_type of_platform_bus_type /* for compatibility */
20 17
21#endif 18#endif
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h
index b2631da259e..699da05235c 100644
--- a/arch/sparc/include/asm/oplib_32.h
+++ b/arch/sparc/include/asm/oplib_32.h
@@ -21,7 +21,6 @@ enum prom_major_version {
21 PROM_V2, /* sun4c and early sun4m V2 prom */ 21 PROM_V2, /* sun4c and early sun4m V2 prom */
22 PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */ 22 PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */
23 PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */ 23 PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */
24 PROM_SUN4, /* Old sun4 proms are totally different, but we'll shoehorn it to make it fit */
25}; 24};
26 25
27extern enum prom_major_version prom_vers; 26extern enum prom_major_version prom_vers;
diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h
index cf5fb70ca1c..d1806edc095 100644
--- a/arch/sparc/include/asm/page_32.h
+++ b/arch/sparc/include/asm/page_32.h
@@ -8,11 +8,8 @@
8#ifndef _SPARC_PAGE_H 8#ifndef _SPARC_PAGE_H
9#define _SPARC_PAGE_H 9#define _SPARC_PAGE_H
10 10
11#ifdef CONFIG_SUN4
12#define PAGE_SHIFT 13
13#else
14#define PAGE_SHIFT 12 11#define PAGE_SHIFT 12
15#endif 12
16#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
17/* I have my suspicions... -DaveM */ 14/* I have my suspicions... -DaveM */
18#define PAGE_SIZE (1UL << PAGE_SHIFT) 15#define PAGE_SIZE (1UL << PAGE_SHIFT)
diff --git a/arch/sparc/include/asm/page_64.h b/arch/sparc/include/asm/page_64.h
index b579b910ef5..4274ed13ddb 100644
--- a/arch/sparc/include/asm/page_64.h
+++ b/arch/sparc/include/asm/page_64.h
@@ -38,6 +38,8 @@
38 38
39#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
40 40
41#define WANT_PAGE_VIRTUAL
42
41extern void _clear_page(void *page); 43extern void _clear_page(void *page);
42#define clear_page(X) _clear_page((void *)(X)) 44#define clear_page(X) _clear_page((void *)(X))
43struct page; 45struct page;
diff --git a/arch/sparc/include/asm/parport.h b/arch/sparc/include/asm/parport.h
index d9830621c90..dff3f0253aa 100644
--- a/arch/sparc/include/asm/parport.h
+++ b/arch/sparc/include/asm/parport.h
@@ -8,7 +8,7 @@
8 8
9#include <linux/of_device.h> 9#include <linux/of_device.h>
10 10
11#include <asm/ebus.h> 11#include <asm/ebus_dma.h>
12#include <asm/ns87303.h> 12#include <asm/ns87303.h>
13#include <asm/prom.h> 13#include <asm/prom.h>
14 14
@@ -215,7 +215,7 @@ static int __devexit ecpp_remove(struct of_device *op)
215 return 0; 215 return 0;
216} 216}
217 217
218static struct of_device_id ecpp_match[] = { 218static const struct of_device_id ecpp_match[] = {
219 { 219 {
220 .name = "ecpp", 220 .name = "ecpp",
221 }, 221 },
diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h
index 0ee949d220c..b41c4c19815 100644
--- a/arch/sparc/include/asm/pci_32.h
+++ b/arch/sparc/include/asm/pci_32.h
@@ -3,6 +3,8 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#include <linux/dma-mapping.h>
7
6/* Can be used to override the logic in pci_scan_bus for skipping 8/* Can be used to override the logic in pci_scan_bus for skipping
7 * already-configured bus numbers - to be used for buggy BIOSes 9 * already-configured bus numbers - to be used for buggy BIOSes
8 * or architectures with incomplete PCI setup by the loader. 10 * or architectures with incomplete PCI setup by the loader.
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index 08237fda887..e0cabe790ec 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -14,11 +14,7 @@
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/swap.h> 15#include <linux/swap.h>
16#include <asm/types.h> 16#include <asm/types.h>
17#ifdef CONFIG_SUN4
18#include <asm/pgtsun4.h>
19#else
20#include <asm/pgtsun4c.h> 17#include <asm/pgtsun4c.h>
21#endif
22#include <asm/pgtsrmmu.h> 18#include <asm/pgtsrmmu.h>
23#include <asm/vac-ops.h> 19#include <asm/vac-ops.h>
24#include <asm/oplib.h> 20#include <asm/oplib.h>
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index bb9ec2cce35..b049abf9902 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -770,6 +770,8 @@ extern void sun4v_patch_tlb_handlers(void);
770 770
771extern unsigned long cmdline_memory_size; 771extern unsigned long cmdline_memory_size;
772 772
773extern asmlinkage void do_sparc64_fault(struct pt_regs *regs);
774
773#endif /* !(__ASSEMBLY__) */ 775#endif /* !(__ASSEMBLY__) */
774 776
775#endif /* !(_SPARC64_PGTABLE_H) */ 777#endif /* !(_SPARC64_PGTABLE_H) */
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
index fd55522481c..900d44714f8 100644
--- a/arch/sparc/include/asm/prom.h
+++ b/arch/sparc/include/asm/prom.h
@@ -18,6 +18,7 @@
18 */ 18 */
19#include <linux/types.h> 19#include <linux/types.h>
20#include <linux/proc_fs.h> 20#include <linux/proc_fs.h>
21#include <linux/mutex.h>
21#include <asm/atomic.h> 22#include <asm/atomic.h>
22 23
23#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2 24#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2
@@ -73,6 +74,7 @@ struct of_irq_controller {
73 74
74extern struct device_node *of_find_node_by_cpuid(int cpuid); 75extern struct device_node *of_find_node_by_cpuid(int cpuid);
75extern int of_set_property(struct device_node *node, const char *name, void *val, int len); 76extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
77extern struct mutex of_set_property_mutex;
76extern int of_getintprop_default(struct device_node *np, 78extern int of_getintprop_default(struct device_node *np,
77 const char *name, 79 const char *name,
78 int def); 80 int def);
@@ -94,6 +96,16 @@ static inline void of_node_put(struct device_node *node)
94{ 96{
95} 97}
96 98
99/* These routines are here to provide compatibility with how powerpc
100 * handles IRQ mapping for OF device nodes. We precompute and permanently
101 * register them in the of_device objects, whereas powerpc computes them
102 * on request.
103 */
104extern unsigned int irq_of_parse_and_map(struct device_node *node, int index);
105static inline void irq_dispose_mapping(unsigned int virq)
106{
107}
108
97/* 109/*
98 * NB: This is here while we transition from using asm/prom.h 110 * NB: This is here while we transition from using asm/prom.h
99 * to linux/of.h 111 * to linux/of.h
diff --git a/arch/sparc/include/asm/ptrace_64.h b/arch/sparc/include/asm/ptrace_64.h
index 06e4914c13f..3d3e9c161d8 100644
--- a/arch/sparc/include/asm/ptrace_64.h
+++ b/arch/sparc/include/asm/ptrace_64.h
@@ -113,6 +113,8 @@ struct sparc_trapf {
113 113
114#ifdef __KERNEL__ 114#ifdef __KERNEL__
115 115
116#include <linux/threads.h>
117
116static inline int pt_regs_trap_type(struct pt_regs *regs) 118static inline int pt_regs_trap_type(struct pt_regs *regs)
117{ 119{
118 return regs->magic & 0x1ff; 120 return regs->magic & 0x1ff;
@@ -138,6 +140,7 @@ struct global_reg_snapshot {
138 struct thread_info *thread; 140 struct thread_info *thread;
139 unsigned long pad1; 141 unsigned long pad1;
140}; 142};
143extern struct global_reg_snapshot global_reg_snapshot[NR_CPUS];
141 144
142#define __ARCH_WANT_COMPAT_SYS_PTRACE 145#define __ARCH_WANT_COMPAT_SYS_PTRACE
143 146
diff --git a/arch/sparc/include/asm/reboot.h b/arch/sparc/include/asm/reboot.h
deleted file mode 100644
index 3f3f43f5be5..00000000000
--- a/arch/sparc/include/asm/reboot.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _SPARC64_REBOOT_H
2#define _SPARC64_REBOOT_H
3
4extern void machine_alt_power_off(void);
5
6#endif /* _SPARC64_REBOOT_H */
diff --git a/arch/sparc/include/asm/rtc.h b/arch/sparc/include/asm/rtc.h
deleted file mode 100644
index f9ecb1fe2ec..00000000000
--- a/arch/sparc/include/asm/rtc.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * rtc.h: Definitions for access to the Mostek real time clock
3 *
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 */
6
7#ifndef _RTC_H
8#define _RTC_H
9
10#include <linux/ioctl.h>
11
12struct rtc_time
13{
14 int sec; /* Seconds (0-59) */
15 int min; /* Minutes (0-59) */
16 int hour; /* Hour (0-23) */
17 int dow; /* Day of the week (1-7) */
18 int dom; /* Day of the month (1-31) */
19 int month; /* Month of year (1-12) */
20 int year; /* Year (0-99) */
21};
22
23#define RTCGET _IOR('p', 20, struct rtc_time)
24#define RTCSET _IOW('p', 21, struct rtc_time)
25
26#endif
diff --git a/arch/sparc/include/asm/sbus.h b/arch/sparc/include/asm/sbus.h
deleted file mode 100644
index f82481ab44d..00000000000
--- a/arch/sparc/include/asm/sbus.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SBUS_H
2#define ___ASM_SPARC_SBUS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm/sbus_64.h>
5#else
6#include <asm/sbus_32.h>
7#endif
8#endif
diff --git a/arch/sparc/include/asm/sbus_32.h b/arch/sparc/include/asm/sbus_32.h
deleted file mode 100644
index a7b4fa21931..00000000000
--- a/arch/sparc/include/asm/sbus_32.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * sbus.h: Defines for the Sun SBus.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_SBUS_H
8#define _SPARC_SBUS_H
9
10#include <linux/dma-mapping.h>
11#include <linux/ioport.h>
12#include <linux/of_device.h>
13
14#include <asm/oplib.h>
15#include <asm/prom.h>
16#include <asm/scatterlist.h>
17
18/* We scan which devices are on the SBus using the PROM node device
19 * tree. SBus devices are described in two different ways. You can
20 * either get an absolute address at which to access the device, or
21 * you can get a SBus 'slot' number and an offset within that slot.
22 */
23
24/* The base address at which to calculate device OBIO addresses. */
25#define SUN_SBUS_BVADDR 0xf8000000
26#define SBUS_OFF_MASK 0x01ffffff
27
28/* These routines are used to calculate device address from slot
29 * numbers + offsets, and vice versa.
30 */
31
32static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
33{
34 return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<25)+(offset));
35}
36
37static inline int sbus_dev_slot(unsigned long dev_addr)
38{
39 return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>25);
40}
41
42struct sbus_bus;
43
44/* Linux SBUS device tables */
45struct sbus_dev {
46 struct of_device ofdev;
47 struct sbus_bus *bus;
48 struct sbus_dev *next;
49 struct sbus_dev *child;
50 struct sbus_dev *parent;
51 int prom_node;
52 char prom_name[64];
53 int slot;
54
55 struct resource resource[PROMREG_MAX];
56
57 struct linux_prom_registers reg_addrs[PROMREG_MAX];
58 int num_registers;
59
60 struct linux_prom_ranges device_ranges[PROMREG_MAX];
61 int num_device_ranges;
62
63 unsigned int irqs[4];
64 int num_irqs;
65};
66#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
67
68/* This struct describes the SBus(s) found on this machine. */
69struct sbus_bus {
70 struct of_device ofdev;
71 struct sbus_dev *devices; /* Link to devices on this SBus */
72 struct sbus_bus *next; /* next SBus, if more than one SBus */
73 int prom_node; /* PROM device tree node for this SBus */
74 char prom_name[64]; /* Usually "sbus" or "sbi" */
75 int clock_freq;
76
77 struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
78 int num_sbus_ranges;
79
80 int devid;
81 int board;
82};
83#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
84
85extern struct sbus_bus *sbus_root;
86
87static inline int
88sbus_is_slave(struct sbus_dev *dev)
89{
90 /* XXX Have to write this for sun4c's */
91 return 0;
92}
93
94/* Device probing routines could find these handy */
95#define for_each_sbus(bus) \
96 for((bus) = sbus_root; (bus); (bus)=(bus)->next)
97
98#define for_each_sbusdev(device, bus) \
99 for((device) = (bus)->devices; (device); (device)=(device)->next)
100
101#define for_all_sbusdev(device, bus) \
102 for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
103 for ((device) = (bus)->devices; (device); (device) = (device)->next)
104
105/* Driver DVMA interfaces. */
106#define sbus_can_dma_64bit(sdev) (0) /* actually, sparc_cpu_model==sun4d */
107#define sbus_can_burst64(sdev) (0) /* actually, sparc_cpu_model==sun4d */
108extern void sbus_set_sbus64(struct sbus_dev *, int);
109extern void sbus_fill_device_irq(struct sbus_dev *);
110
111/* These yield IOMMU mappings in consistent mode. */
112extern void *sbus_alloc_consistent(struct sbus_dev *, long, u32 *dma_addrp);
113extern void sbus_free_consistent(struct sbus_dev *, long, void *, u32);
114void prom_adjust_ranges(struct linux_prom_ranges *, int,
115 struct linux_prom_ranges *, int);
116
117#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
118#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
119#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
120#define SBUS_DMA_NONE DMA_NONE
121
122/* All the rest use streaming mode mappings. */
123extern dma_addr_t sbus_map_single(struct sbus_dev *, void *, size_t, int);
124extern void sbus_unmap_single(struct sbus_dev *, dma_addr_t, size_t, int);
125extern int sbus_map_sg(struct sbus_dev *, struct scatterlist *, int, int);
126extern void sbus_unmap_sg(struct sbus_dev *, struct scatterlist *, int, int);
127
128/* Finally, allow explicit synchronization of streamable mappings. */
129extern void sbus_dma_sync_single_for_cpu(struct sbus_dev *, dma_addr_t, size_t, int);
130#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
131extern void sbus_dma_sync_single_for_device(struct sbus_dev *, dma_addr_t, size_t, int);
132extern void sbus_dma_sync_sg_for_cpu(struct sbus_dev *, struct scatterlist *, int, int);
133#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
134extern void sbus_dma_sync_sg_for_device(struct sbus_dev *, struct scatterlist *, int, int);
135
136/* Eric Brower (ebrower@usa.net)
137 * Translate SBus interrupt levels to ino values--
138 * this is used when converting sbus "interrupts" OBP
139 * node values to "intr" node values, and is platform
140 * dependent. If only we could call OBP with
141 * "sbus-intr>cpu (sbint -- ino)" from kernel...
142 * See .../drivers/sbus/sbus.c for details.
143 */
144BTFIXUPDEF_CALL(unsigned int, sbint_to_irq, struct sbus_dev *sdev, unsigned int)
145#define sbint_to_irq(sdev, sbint) BTFIXUP_CALL(sbint_to_irq)(sdev, sbint)
146
147extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
148extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
149extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
150extern int sbus_arch_preinit(void);
151extern void sbus_arch_postinit(void);
152
153#endif /* !(_SPARC_SBUS_H) */
diff --git a/arch/sparc/include/asm/sbus_64.h b/arch/sparc/include/asm/sbus_64.h
deleted file mode 100644
index b606c14343f..00000000000
--- a/arch/sparc/include/asm/sbus_64.h
+++ /dev/null
@@ -1,190 +0,0 @@
1/* sbus.h: Defines for the Sun SBus.
2 *
3 * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC64_SBUS_H
7#define _SPARC64_SBUS_H
8
9#include <linux/dma-mapping.h>
10#include <linux/ioport.h>
11#include <linux/of_device.h>
12
13#include <asm/oplib.h>
14#include <asm/prom.h>
15#include <asm/iommu.h>
16#include <asm/scatterlist.h>
17
18/* We scan which devices are on the SBus using the PROM node device
19 * tree. SBus devices are described in two different ways. You can
20 * either get an absolute address at which to access the device, or
21 * you can get a SBus 'slot' number and an offset within that slot.
22 */
23
24/* The base address at which to calculate device OBIO addresses. */
25#define SUN_SBUS_BVADDR 0x00000000
26#define SBUS_OFF_MASK 0x0fffffff
27
28/* These routines are used to calculate device address from slot
29 * numbers + offsets, and vice versa.
30 */
31
32static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
33{
34 return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset));
35}
36
37static inline int sbus_dev_slot(unsigned long dev_addr)
38{
39 return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28);
40}
41
42struct sbus_bus;
43
44/* Linux SBUS device tables */
45struct sbus_dev {
46 struct of_device ofdev;
47 struct sbus_bus *bus;
48 struct sbus_dev *next;
49 struct sbus_dev *child;
50 struct sbus_dev *parent;
51 int prom_node;
52 char prom_name[64];
53 int slot;
54
55 struct resource resource[PROMREG_MAX];
56
57 struct linux_prom_registers reg_addrs[PROMREG_MAX];
58 int num_registers;
59
60 struct linux_prom_ranges device_ranges[PROMREG_MAX];
61 int num_device_ranges;
62
63 unsigned int irqs[4];
64 int num_irqs;
65};
66#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
67
68/* This struct describes the SBus(s) found on this machine. */
69struct sbus_bus {
70 struct of_device ofdev;
71 struct sbus_dev *devices; /* Tree of SBUS devices */
72 struct sbus_bus *next; /* Next SBUS in system */
73 int prom_node; /* OBP node of SBUS */
74 char prom_name[64]; /* Usually "sbus" or "sbi" */
75 int clock_freq;
76
77 struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
78 int num_sbus_ranges;
79
80 int portid;
81};
82#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
83
84extern struct sbus_bus *sbus_root;
85
86/* Device probing routines could find these handy */
87#define for_each_sbus(bus) \
88 for((bus) = sbus_root; (bus); (bus)=(bus)->next)
89
90#define for_each_sbusdev(device, bus) \
91 for((device) = (bus)->devices; (device); (device)=(device)->next)
92
93#define for_all_sbusdev(device, bus) \
94 for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
95 for ((device) = (bus)->devices; (device); (device) = (device)->next)
96
97/* Driver DVMA interfaces. */
98#define sbus_can_dma_64bit(sdev) (1)
99#define sbus_can_burst64(sdev) (1)
100extern void sbus_set_sbus64(struct sbus_dev *, int);
101extern void sbus_fill_device_irq(struct sbus_dev *);
102
103static inline void *sbus_alloc_consistent(struct sbus_dev *sdev , size_t size,
104 dma_addr_t *dma_handle)
105{
106 return dma_alloc_coherent(&sdev->ofdev.dev, size,
107 dma_handle, GFP_ATOMIC);
108}
109
110static inline void sbus_free_consistent(struct sbus_dev *sdev, size_t size,
111 void *vaddr, dma_addr_t dma_handle)
112{
113 return dma_free_coherent(&sdev->ofdev.dev, size, vaddr, dma_handle);
114}
115
116#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
117#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
118#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
119#define SBUS_DMA_NONE DMA_NONE
120
121/* All the rest use streaming mode mappings. */
122static inline dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr,
123 size_t size, int direction)
124{
125 return dma_map_single(&sdev->ofdev.dev, ptr, size,
126 (enum dma_data_direction) direction);
127}
128
129static inline void sbus_unmap_single(struct sbus_dev *sdev,
130 dma_addr_t dma_addr, size_t size,
131 int direction)
132{
133 dma_unmap_single(&sdev->ofdev.dev, dma_addr, size,
134 (enum dma_data_direction) direction);
135}
136
137static inline int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg,
138 int nents, int direction)
139{
140 return dma_map_sg(&sdev->ofdev.dev, sg, nents,
141 (enum dma_data_direction) direction);
142}
143
144static inline void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg,
145 int nents, int direction)
146{
147 dma_unmap_sg(&sdev->ofdev.dev, sg, nents,
148 (enum dma_data_direction) direction);
149}
150
151/* Finally, allow explicit synchronization of streamable mappings. */
152static inline void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev,
153 dma_addr_t dma_handle,
154 size_t size, int direction)
155{
156 dma_sync_single_for_cpu(&sdev->ofdev.dev, dma_handle, size,
157 (enum dma_data_direction) direction);
158}
159#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
160
161static inline void sbus_dma_sync_single_for_device(struct sbus_dev *sdev,
162 dma_addr_t dma_handle,
163 size_t size, int direction)
164{
165 /* No flushing needed to sync cpu writes to the device. */
166}
167
168static inline void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev,
169 struct scatterlist *sg,
170 int nents, int direction)
171{
172 dma_sync_sg_for_cpu(&sdev->ofdev.dev, sg, nents,
173 (enum dma_data_direction) direction);
174}
175#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
176
177static inline void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev,
178 struct scatterlist *sg,
179 int nents, int direction)
180{
181 /* No flushing needed to sync cpu writes to the device. */
182}
183
184extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
185extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
186extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
187extern int sbus_arch_preinit(void);
188extern void sbus_arch_postinit(void);
189
190#endif /* !(_SPARC64_SBUS_H) */
diff --git a/arch/sparc/include/asm/spinlock_32.h b/arch/sparc/include/asm/spinlock_32.h
index de2249b267c..bf2d532593e 100644
--- a/arch/sparc/include/asm/spinlock_32.h
+++ b/arch/sparc/include/asm/spinlock_32.h
@@ -6,8 +6,6 @@
6#ifndef __SPARC_SPINLOCK_H 6#ifndef __SPARC_SPINLOCK_H
7#define __SPARC_SPINLOCK_H 7#define __SPARC_SPINLOCK_H
8 8
9#include <linux/threads.h> /* For NR_CPUS */
10
11#ifndef __ASSEMBLY__ 9#ifndef __ASSEMBLY__
12 10
13#include <asm/psr.h> 11#include <asm/psr.h>
diff --git a/arch/sparc/include/asm/spinlock_64.h b/arch/sparc/include/asm/spinlock_64.h
index 0006fe9f8c7..120cfe4577c 100644
--- a/arch/sparc/include/asm/spinlock_64.h
+++ b/arch/sparc/include/asm/spinlock_64.h
@@ -6,8 +6,6 @@
6#ifndef __SPARC64_SPINLOCK_H 6#ifndef __SPARC64_SPINLOCK_H
7#define __SPARC64_SPINLOCK_H 7#define __SPARC64_SPINLOCK_H
8 8
9#include <linux/threads.h> /* For NR_CPUS */
10
11#ifndef __ASSEMBLY__ 9#ifndef __ASSEMBLY__
12 10
13/* To get debugging spinlocks which detect and catch 11/* To get debugging spinlocks which detect and catch
diff --git a/arch/sparc/include/asm/sstate.h b/arch/sparc/include/asm/sstate.h
deleted file mode 100644
index a7c35dbcb28..00000000000
--- a/arch/sparc/include/asm/sstate.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef _SPARC64_SSTATE_H
2#define _SPARC64_SSTATE_H
3
4extern void sstate_booting(void);
5extern void sstate_running(void);
6extern void sstate_halt(void);
7extern void sstate_poweroff(void);
8extern void sstate_panic(void);
9extern void sstate_reboot(void);
10
11extern void sun4v_sstate_init(void);
12
13#endif /* _SPARC64_SSTATE_H */
diff --git a/arch/sparc/include/asm/starfire.h b/arch/sparc/include/asm/starfire.h
index 07bafd31e33..d56ce60a599 100644
--- a/arch/sparc/include/asm/starfire.h
+++ b/arch/sparc/include/asm/starfire.h
@@ -12,7 +12,6 @@
12extern int this_is_starfire; 12extern int this_is_starfire;
13 13
14extern void check_if_starfire(void); 14extern void check_if_starfire(void);
15extern void starfire_cpu_setup(void);
16extern int starfire_hard_smp_processor_id(void); 15extern int starfire_hard_smp_processor_id(void);
17extern void starfire_hookup(int); 16extern void starfire_hookup(int);
18extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid); 17extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid);
diff --git a/arch/sparc/include/asm/sun4paddr.h b/arch/sparc/include/asm/sun4paddr.h
deleted file mode 100644
index d52985f19f4..00000000000
--- a/arch/sparc/include/asm/sun4paddr.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * sun4paddr.h: Various physical addresses on sun4 machines
3 *
4 * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
5 * Copyright (C) 1998 Chris Davis (cdavis@cois.on.ca)
6 *
7 * Now supports more sun4's
8 */
9
10#ifndef _SPARC_SUN4PADDR_H
11#define _SPARC_SUN4PADDR_H
12
13#define SUN4_IE_PHYSADDR 0xf5000000
14#define SUN4_UNUSED_PHYSADDR 0
15
16/* these work for me */
17#define SUN4_200_MEMREG_PHYSADDR 0xf4000000
18#define SUN4_200_CLOCK_PHYSADDR 0xf3000000
19#define SUN4_200_BWTWO_PHYSADDR 0xfd000000
20#define SUN4_200_ETH_PHYSADDR 0xf6000000
21#define SUN4_200_SI_PHYSADDR 0xff200000
22
23/* these were here before */
24#define SUN4_300_MEMREG_PHYSADDR 0xf4000000
25#define SUN4_300_CLOCK_PHYSADDR 0xf2000000
26#define SUN4_300_TIMER_PHYSADDR 0xef000000
27#define SUN4_300_ETH_PHYSADDR 0xf9000000
28#define SUN4_300_BWTWO_PHYSADDR 0xfb400000
29#define SUN4_300_DMA_PHYSADDR 0xfa001000
30#define SUN4_300_ESP_PHYSADDR 0xfa000000
31
32/* Are these right? */
33#define SUN4_400_MEMREG_PHYSADDR 0xf4000000
34#define SUN4_400_CLOCK_PHYSADDR 0xf2000000
35#define SUN4_400_TIMER_PHYSADDR 0xef000000
36#define SUN4_400_ETH_PHYSADDR 0xf9000000
37#define SUN4_400_BWTWO_PHYSADDR 0xfb400000
38#define SUN4_400_DMA_PHYSADDR 0xfa001000
39#define SUN4_400_ESP_PHYSADDR 0xfa000000
40
41/*
42 these are the actual values set and used in the code. Unused items set
43 to SUN_UNUSED_PHYSADDR
44 */
45
46extern int sun4_memreg_physaddr; /* memory register (ecc?) */
47extern int sun4_clock_physaddr; /* system clock */
48extern int sun4_timer_physaddr; /* timer, where applicable */
49extern int sun4_eth_physaddr; /* onboard ethernet (ie/le) */
50extern int sun4_si_physaddr; /* sun3 scsi adapter */
51extern int sun4_bwtwo_physaddr; /* onboard bw2 */
52extern int sun4_dma_physaddr; /* scsi dma */
53extern int sun4_esp_physaddr; /* esp scsi */
54extern int sun4_ie_physaddr; /* interrupt enable */
55
56#endif /* !(_SPARC_SUN4PADDR_H) */
diff --git a/arch/sparc/include/asm/sun4prom.h b/arch/sparc/include/asm/sun4prom.h
deleted file mode 100644
index 9c8b4cbf629..00000000000
--- a/arch/sparc/include/asm/sun4prom.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * sun4prom.h -- interface to sun4 PROM monitor. We don't use most of this,
3 * so most of these are just placeholders.
4 */
5
6#ifndef _SUN4PROM_H_
7#define _SUN4PROM_H_
8
9/*
10 * Although this looks similar to an romvec for a OpenProm machine, it is
11 * actually closer to what was used in the Sun2 and Sun3.
12 *
13 * V2 entries exist only in version 2 PROMs and later, V3 in version 3 and later.
14 *
15 * Many of the function prototypes are guesses. Some are certainly wrong.
16 * Use with care.
17 */
18
19typedef struct {
20 char *initSP; /* Initial system stack ptr */
21 void (*startmon)(void); /* Initial PC for hardware */
22 int *diagberr; /* Bus err handler for diags */
23 struct linux_arguments_v0 **bootParam; /* Info for bootstrapped pgm */
24 unsigned int *memorysize; /* Usable memory in bytes */
25 unsigned char (*getchar)(void); /* Get char from input device */
26 void (*putchar)(char); /* Put char to output device */
27 int (*mayget)(void); /* Maybe get char, or -1 */
28 int (*mayput)(int); /* Maybe put char, or -1 */
29 unsigned char *echo; /* Should getchar echo? */
30 unsigned char *insource; /* Input source selector */
31 unsigned char *outsink; /* Output sink selector */
32 int (*getkey)(void); /* Get next key if one exists */
33 void (*initgetkey)(void); /* Initialize get key */
34 unsigned int *translation; /* Kbd translation selector */
35 unsigned char *keybid; /* Keyboard ID byte */
36 int *screen_x; /* V2: Screen x pos (r/o) */
37 int *screen_y; /* V2: Screen y pos (r/o) */
38 struct keybuf *keybuf; /* Up/down keycode buffer */
39 char *monid; /* Monitor version ID */
40 void (*fbwritechar)(char); /* Write a character to FB */
41 int *fbAddr; /* Address of frame buffer */
42 char **font; /* Font table for FB */
43 void (*fbwritestr)(char *); /* Write string to FB */
44 void (*reboot)(char *); /* e.g. reboot("sd()vmlinux") */
45 unsigned char *linebuf; /* The line input buffer */
46 unsigned char **lineptr; /* Cur pointer into linebuf */
47 int *linesize; /* length of line in linebuf */
48 void (*getline)(char *); /* Get line from user */
49 unsigned char (*getnextchar)(void); /* Get next char from linebuf */
50 unsigned char (*peeknextchar)(void); /* Peek at next char */
51 int *fbthere; /* =1 if frame buffer there */
52 int (*getnum)(void); /* Grab hex num from line */
53 int (*printf)(char *, ...); /* See prom_printf() instead */
54 void (*printhex)(int); /* Format N digits in hex */
55 unsigned char *leds; /* RAM copy of LED register */
56 void (*setLEDs)(unsigned char *); /* Sets LED's and RAM copy */
57 void (*NMIaddr)(void *); /* Addr for level 7 vector */
58 void (*abortentry)(void); /* Entry for keyboard abort */
59 int *nmiclock; /* Counts up in msec */
60 int *FBtype; /* Frame buffer type */
61 unsigned int romvecversion; /* Version number for this romvec */
62 struct globram *globram; /* monitor global variables ??? */
63 void * kbdaddr; /* Addr of keyboard in use */
64 int *keyrinit; /* ms before kbd repeat */
65 unsigned char *keyrtick; /* ms between repetitions */
66 unsigned int *memoryavail; /* V1: Main mem usable size */
67 long *resetaddr; /* where to jump on a reset */
68 long *resetmap; /* pgmap entry for resetaddr */
69 void (*exittomon)(void); /* Exit from user program */
70 unsigned char **memorybitmap; /* V1: &{0 or &bits} */
71 void (*setcxsegmap)(int ctxt, char *va, int pmeg); /* Set seg in any context */
72 void (**vector_cmd)(void *); /* V2: Handler for 'v' cmd */
73 unsigned long *expectedtrapsig; /* V3: Location of the expected trap signal */
74 unsigned long *trapvectorbasetable; /* V3: Address of the trap vector table */
75 int unused1;
76 int unused2;
77 int unused3;
78 int unused4;
79} linux_sun4_romvec;
80
81extern linux_sun4_romvec *sun4_romvec;
82
83#endif /* _SUN4PROM_H_ */
diff --git a/arch/sparc/include/asm/system_32.h b/arch/sparc/include/asm/system_32.h
index b4b024445fc..8623fc48fe2 100644
--- a/arch/sparc/include/asm/system_32.h
+++ b/arch/sparc/include/asm/system_32.h
@@ -34,13 +34,7 @@ enum sparc_cpu {
34 34
35extern enum sparc_cpu sparc_cpu_model; 35extern enum sparc_cpu sparc_cpu_model;
36 36
37#ifndef CONFIG_SUN4 37#define ARCH_SUN4C (sparc_cpu_model==sun4c)
38#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
39#define ARCH_SUN4 0
40#else
41#define ARCH_SUN4C_SUN4 1
42#define ARCH_SUN4 1
43#endif
44 38
45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */ 39#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
46 40
@@ -55,6 +49,7 @@ extern unsigned long empty_zero_page;
55extern void sun_do_break(void); 49extern void sun_do_break(void);
56extern int serial_console; 50extern int serial_console;
57extern int stop_a_enabled; 51extern int stop_a_enabled;
52extern int scons_pwroff;
58 53
59static inline int con_is_present(void) 54static inline int con_is_present(void)
60{ 55{
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h
index db9e742a406..8759f2a1b83 100644
--- a/arch/sparc/include/asm/system_64.h
+++ b/arch/sparc/include/asm/system_64.h
@@ -26,9 +26,8 @@ enum sparc_cpu {
26 26
27#define sparc_cpu_model sun4u 27#define sparc_cpu_model sun4u
28 28
29/* This cannot ever be a sun4c nor sun4 :) That's just history. */ 29/* This cannot ever be a sun4c :) That's just history. */
30#define ARCH_SUN4C_SUN4 0 30#define ARCH_SUN4C 0
31#define ARCH_SUN4 0
32 31
33extern char reboot_command[]; 32extern char reboot_command[];
34 33
@@ -118,6 +117,7 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
118 117
119extern void sun_do_break(void); 118extern void sun_do_break(void);
120extern int stop_a_enabled; 119extern int stop_a_enabled;
120extern int scons_pwroff;
121 121
122extern void fault_in_user_windows(void); 122extern void fault_in_user_windows(void);
123extern void synchronize_user_stack(void); 123extern void synchronize_user_stack(void);
diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h
index cbb892d0dff..29899fd5b1b 100644
--- a/arch/sparc/include/asm/thread_info_32.h
+++ b/arch/sparc/include/asm/thread_info_32.h
@@ -80,11 +80,7 @@ register struct thread_info *current_thread_info_reg asm("g6");
80/* 80/*
81 * thread information allocation 81 * thread information allocation
82 */ 82 */
83#if PAGE_SHIFT == 13
84#define THREAD_INFO_ORDER 0
85#else /* PAGE_SHIFT */
86#define THREAD_INFO_ORDER 1 83#define THREAD_INFO_ORDER 1
87#endif
88 84
89#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 85#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
90 86
diff --git a/arch/sparc/include/asm/timer_32.h b/arch/sparc/include/asm/timer_32.h
index 361e53898dd..2ec030ef381 100644
--- a/arch/sparc/include/asm/timer_32.h
+++ b/arch/sparc/include/asm/timer_32.h
@@ -9,96 +9,9 @@
9#define _SPARC_TIMER_H 9#define _SPARC_TIMER_H
10 10
11#include <asm/system.h> /* For SUN4M_NCPUS */ 11#include <asm/system.h> /* For SUN4M_NCPUS */
12#include <asm/sun4paddr.h>
13#include <asm/btfixup.h> 12#include <asm/btfixup.h>
14 13
15/* Timer structures. The interrupt timer has two properties which
16 * are the counter (which is handled in do_timer in sched.c) and the limit.
17 * This limit is where the timer's counter 'wraps' around. Oddly enough,
18 * the sun4c timer when it hits the limit wraps back to 1 and not zero
19 * thus when calculating the value at which it will fire a microsecond you
20 * must adjust by one. Thanks SUN for designing such great hardware ;(
21 */
22
23/* Note that I am only going to use the timer that interrupts at
24 * Sparc IRQ 10. There is another one available that can fire at
25 * IRQ 14. Currently it is left untouched, we keep the PROM's limit
26 * register value and let the prom take these interrupts. This allows
27 * L1-A to work.
28 */
29
30struct sun4c_timer_info {
31 __volatile__ unsigned int cur_count10;
32 __volatile__ unsigned int timer_limit10;
33 __volatile__ unsigned int cur_count14;
34 __volatile__ unsigned int timer_limit14;
35};
36
37#define SUN4C_TIMER_PHYSADDR 0xf3000000
38#ifdef CONFIG_SUN4
39#define SUN_TIMER_PHYSADDR SUN4_300_TIMER_PHYSADDR
40#else
41#define SUN_TIMER_PHYSADDR SUN4C_TIMER_PHYSADDR
42#endif
43
44/* A sun4m has two blocks of registers which are probably of the same
45 * structure. LSI Logic's L64851 is told to _decrement_ from the limit
46 * value. Aurora behaves similarly but its limit value is compacted in
47 * other fashion (it's wider). Documented fields are defined here.
48 */
49
50/* As with the interrupt register, we have two classes of timer registers
51 * which are per-cpu and master. Per-cpu timers only hit that cpu and are
52 * only level 14 ticks, master timer hits all cpus and is level 10.
53 */
54
55#define SUN4M_PRM_CNT_L 0x80000000
56#define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00
57
58struct sun4m_timer_percpu_info {
59 __volatile__ unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
60 __volatile__ unsigned int l14_cur_count;
61
62 /* This register appears to be write only and/or inaccessible
63 * on Uni-Processor sun4m machines.
64 */
65 __volatile__ unsigned int l14_limit_noclear; /* Data access error is here */
66
67 __volatile__ unsigned int cntrl; /* =1 after POST on Aurora */
68 __volatile__ unsigned char space[PAGE_SIZE - 16];
69};
70
71struct sun4m_timer_regs {
72 struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS];
73 volatile unsigned int l10_timer_limit;
74 volatile unsigned int l10_cur_count;
75
76 /* Again, this appears to be write only and/or inaccessible
77 * on uni-processor sun4m machines.
78 */
79 volatile unsigned int l10_limit_noclear;
80
81 /* This register too, it must be magic. */
82 volatile unsigned int foobar;
83
84 volatile unsigned int cfg; /* equals zero at boot time... */
85};
86
87#define SUN4D_PRM_CNT_L 0x80000000
88#define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00
89
90struct sun4d_timer_regs {
91 volatile unsigned int l10_timer_limit;
92 volatile unsigned int l10_cur_countx;
93 volatile unsigned int l10_limit_noclear;
94 volatile unsigned int ctrl;
95 volatile unsigned int l10_cur_count;
96};
97
98extern struct sun4d_timer_regs *sun4d_timers;
99
100extern __volatile__ unsigned int *master_l10_counter; 14extern __volatile__ unsigned int *master_l10_counter;
101extern __volatile__ unsigned int *master_l10_limit;
102 15
103/* FIXME: Make do_[gs]ettimeofday btfixup calls */ 16/* FIXME: Make do_[gs]ettimeofday btfixup calls */
104BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv) 17BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv)
diff --git a/arch/sparc/include/asm/vac-ops.h b/arch/sparc/include/asm/vac-ops.h
index d10527611f1..a63e88ef042 100644
--- a/arch/sparc/include/asm/vac-ops.h
+++ b/arch/sparc/include/asm/vac-ops.h
@@ -76,11 +76,7 @@
76 * cacheable bit in the pte's of all such pages. 76 * cacheable bit in the pte's of all such pages.
77 */ 77 */
78 78
79#ifdef CONFIG_SUN4
80#define S4CVAC_BADBITS 0x0001e000
81#else
82#define S4CVAC_BADBITS 0x0000f000 79#define S4CVAC_BADBITS 0x0000f000
83#endif
84 80
85/* The following is true if vaddr1 and vaddr2 would cause 81/* The following is true if vaddr1 and vaddr2 would cause
86 * a 'bad alias'. 82 * a 'bad alias'.
@@ -94,10 +90,7 @@
94 */ 90 */
95struct sun4c_vac_props { 91struct sun4c_vac_props {
96 unsigned int num_bytes; /* Size of the cache */ 92 unsigned int num_bytes; /* Size of the cache */
97 unsigned int num_lines; /* Number of cache lines */
98 unsigned int do_hwflushes; /* Hardware flushing available? */ 93 unsigned int do_hwflushes; /* Hardware flushing available? */
99 enum { VAC_NONE, VAC_WRITE_THROUGH,
100 VAC_WRITE_BACK } type; /* What type of VAC? */
101 unsigned int linesize; /* Size of each line in bytes */ 94 unsigned int linesize; /* Size of each line in bytes */
102 unsigned int log2lsize; /* log2(linesize) */ 95 unsigned int log2lsize; /* log2(linesize) */
103 unsigned int on; /* VAC is enabled */ 96 unsigned int on; /* VAC is enabled */
diff --git a/arch/sparc/include/asm/vfc_ioctls.h b/arch/sparc/include/asm/vfc_ioctls.h
deleted file mode 100644
index af8b69007b2..00000000000
--- a/arch/sparc/include/asm/vfc_ioctls.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/* Copyright (c) 1996 by Manish Vachharajani */
2
3#ifndef _LINUX_VFC_IOCTLS_H_
4#define _LINUX_VFC_IOCTLS_H_
5
6 /* IOCTLs */
7#define VFC_IOCTL(a) (('j' << 8) | a)
8#define VFCGCTRL (VFC_IOCTL (0)) /* get vfc attributes */
9#define VFCSCTRL (VFC_IOCTL (1)) /* set vfc attributes */
10#define VFCGVID (VFC_IOCTL (2)) /* get video decoder attributes */
11#define VFCSVID (VFC_IOCTL (3)) /* set video decoder attributes */
12#define VFCHUE (VFC_IOCTL (4)) /* set hue */
13#define VFCPORTCHG (VFC_IOCTL (5)) /* change port */
14#define VFCRDINFO (VFC_IOCTL (6)) /* read info */
15
16 /* Options for setting the vfc attributes and status */
17#define MEMPRST 0x1 /* reset FIFO ptr. */
18#define CAPTRCMD 0x2 /* start capture and wait */
19#define DIAGMODE 0x3 /* diag mode */
20#define NORMMODE 0x4 /* normal mode */
21#define CAPTRSTR 0x5 /* start capture */
22#define CAPTRWAIT 0x6 /* wait for capture to finish */
23
24
25 /* Options for the decoder */
26#define STD_NTSC 0x1 /* NTSC mode */
27#define STD_PAL 0x2 /* PAL mode */
28#define COLOR_ON 0x3 /* force color ON */
29#define MONO 0x4 /* force color OFF */
30
31 /* Values returned by ioctl 2 */
32
33#define NO_LOCK 1
34#define NTSC_COLOR 2
35#define NTSC_NOCOLOR 3
36#define PAL_COLOR 4
37#define PAL_NOCOLOR 5
38
39/* Not too sure what this does yet */
40 /* Options for setting Field number */
41#define ODD_FIELD 0x1
42#define EVEN_FIELD 0x0
43#define ACTIVE_ONLY 0x2
44#define NON_ACTIVE 0x0
45
46/* Debug options */
47#define VFC_I2C_SEND 0
48#define VFC_I2C_RECV 1
49
50struct vfc_debug_inout
51{
52 unsigned long addr;
53 unsigned long ret;
54 unsigned long len;
55 unsigned char __user *buffer;
56};
57
58#endif /* _LINUX_VFC_IOCTLS_H_ */
diff --git a/arch/sparc/include/asm/visasm.h b/arch/sparc/include/asm/visasm.h
index de797b9bf55..39ca301920d 100644
--- a/arch/sparc/include/asm/visasm.h
+++ b/arch/sparc/include/asm/visasm.h
@@ -57,6 +57,7 @@ static inline void save_and_clear_fpu(void) {
57" " : : "i" (FPRS_FEF|FPRS_DU) : 57" " : : "i" (FPRS_FEF|FPRS_DU) :
58 "o5", "g1", "g2", "g3", "g7", "cc"); 58 "o5", "g1", "g2", "g3", "g7", "cc");
59} 59}
60extern int vis_emul(struct pt_regs *, unsigned int);
60#endif 61#endif
61 62
62#endif /* _SPARC64_ASI_H */ 63#endif /* _SPARC64_ASI_H */
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 6e03a2a7863..2d658209509 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -13,15 +13,13 @@ obj-y := entry.o wof.o wuf.o etrap.o rtrap.o traps.o $(IRQ_OBJS) \
13 time.o windows.o cpu.o devices.o \ 13 time.o windows.o cpu.o devices.o \
14 tadpole.o tick14.o ptrace.o \ 14 tadpole.o tick14.o ptrace.o \
15 unaligned.o una_asm.o muldiv.o \ 15 unaligned.o una_asm.o muldiv.o \
16 prom.o of_device.o devres.o 16 prom.o of_device.o devres.o dma.o
17 17
18devres-y = ../../../kernel/irq/devres.o 18devres-y = ../../../kernel/irq/devres.o
19 19
20obj-$(CONFIG_PCI) += pcic.o 20obj-$(CONFIG_PCI) += pcic.o
21obj-$(CONFIG_SUN4) += sun4setup.o
22obj-$(CONFIG_SMP) += trampoline.o smp.o sun4m_smp.o sun4d_smp.o 21obj-$(CONFIG_SMP) += trampoline.o smp.o sun4m_smp.o sun4d_smp.o
23obj-$(CONFIG_SUN_AUXIO) += auxio.o 22obj-$(CONFIG_SUN_AUXIO) += auxio.o
24obj-$(CONFIG_PCI) += ebus.o
25obj-$(CONFIG_SUN_PM) += apc.o pmc.o 23obj-$(CONFIG_SUN_PM) += apc.o pmc.o
26obj-$(CONFIG_MODULES) += module.o sparc_ksyms.o 24obj-$(CONFIG_MODULES) += module.o sparc_ksyms.o
27obj-$(CONFIG_SPARC_LED) += led.o 25obj-$(CONFIG_SPARC_LED) += led.o
diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c
index 5267d48fb2c..4dd1ba752ce 100644
--- a/arch/sparc/kernel/apc.c
+++ b/arch/sparc/kernel/apc.c
@@ -12,9 +12,10 @@
12#include <linux/miscdevice.h> 12#include <linux/miscdevice.h>
13#include <linux/smp_lock.h> 13#include <linux/smp_lock.h>
14#include <linux/pm.h> 14#include <linux/pm.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
15 17
16#include <asm/io.h> 18#include <asm/io.h>
17#include <asm/sbus.h>
18#include <asm/oplib.h> 19#include <asm/oplib.h>
19#include <asm/uaccess.h> 20#include <asm/uaccess.h>
20#include <asm/auxio.h> 21#include <asm/auxio.h>
@@ -29,11 +30,10 @@
29#define APC_OBPNAME "power-management" 30#define APC_OBPNAME "power-management"
30#define APC_DEVNAME "apc" 31#define APC_DEVNAME "apc"
31 32
32volatile static u8 __iomem *regs; 33static u8 __iomem *regs;
33static int apc_regsize;
34static int apc_no_idle __initdata = 0; 34static int apc_no_idle __initdata = 0;
35 35
36#define apc_readb(offs) (sbus_readb(regs+offs)) 36#define apc_readb(offs) (sbus_readb(regs+offs))
37#define apc_writeb(val, offs) (sbus_writeb(val, regs+offs)) 37#define apc_writeb(val, offs) (sbus_writeb(val, regs+offs))
38 38
39/* Specify "apc=noidle" on the kernel command line to 39/* Specify "apc=noidle" on the kernel command line to
@@ -69,9 +69,9 @@ static void apc_swift_idle(void)
69#endif 69#endif
70} 70}
71 71
72static inline void apc_free(void) 72static inline void apc_free(struct of_device *op)
73{ 73{
74 sbus_iounmap(regs, apc_regsize); 74 of_iounmap(&op->resource[0], regs, resource_size(&op->resource[0]));
75} 75}
76 76
77static int apc_open(struct inode *inode, struct file *f) 77static int apc_open(struct inode *inode, struct file *f)
@@ -153,52 +153,56 @@ static const struct file_operations apc_fops = {
153 153
154static struct miscdevice apc_miscdev = { APC_MINOR, APC_DEVNAME, &apc_fops }; 154static struct miscdevice apc_miscdev = { APC_MINOR, APC_DEVNAME, &apc_fops };
155 155
156static int __init apc_probe(void) 156static int __devinit apc_probe(struct of_device *op,
157 const struct of_device_id *match)
157{ 158{
158 struct sbus_bus *sbus = NULL; 159 int err;
159 struct sbus_dev *sdev = NULL;
160 int iTmp = 0;
161
162 for_each_sbus(sbus) {
163 for_each_sbusdev(sdev, sbus) {
164 if (!strcmp(sdev->prom_name, APC_OBPNAME)) {
165 goto sbus_done;
166 }
167 }
168 }
169 160
170sbus_done: 161 regs = of_ioremap(&op->resource[0], 0,
171 if (!sdev) { 162 resource_size(&op->resource[0]), APC_OBPNAME);
172 return -ENODEV; 163 if (!regs) {
173 }
174
175 apc_regsize = sdev->reg_addrs[0].reg_size;
176 regs = sbus_ioremap(&sdev->resource[0], 0,
177 apc_regsize, APC_OBPNAME);
178 if(!regs) {
179 printk(KERN_ERR "%s: unable to map registers\n", APC_DEVNAME); 164 printk(KERN_ERR "%s: unable to map registers\n", APC_DEVNAME);
180 return -ENODEV; 165 return -ENODEV;
181 } 166 }
182 167
183 iTmp = misc_register(&apc_miscdev); 168 err = misc_register(&apc_miscdev);
184 if (iTmp != 0) { 169 if (err) {
185 printk(KERN_ERR "%s: unable to register device\n", APC_DEVNAME); 170 printk(KERN_ERR "%s: unable to register device\n", APC_DEVNAME);
186 apc_free(); 171 apc_free(op);
187 return -ENODEV; 172 return -ENODEV;
188 } 173 }
189 174
190 /* Assign power management IDLE handler */ 175 /* Assign power management IDLE handler */
191 if(!apc_no_idle) 176 if (!apc_no_idle)
192 pm_idle = apc_swift_idle; 177 pm_idle = apc_swift_idle;
193 178
194 printk(KERN_INFO "%s: power management initialized%s\n", 179 printk(KERN_INFO "%s: power management initialized%s\n",
195 APC_DEVNAME, apc_no_idle ? " (CPU idle disabled)" : ""); 180 APC_DEVNAME, apc_no_idle ? " (CPU idle disabled)" : "");
181
196 return 0; 182 return 0;
197} 183}
198 184
185static struct of_device_id __initdata apc_match[] = {
186 {
187 .name = APC_OBPNAME,
188 },
189 {},
190};
191MODULE_DEVICE_TABLE(of, apc_match);
192
193static struct of_platform_driver apc_driver = {
194 .name = "apc",
195 .match_table = apc_match,
196 .probe = apc_probe,
197};
198
199static int __init apc_init(void)
200{
201 return of_register_driver(&apc_driver, &of_bus_type);
202}
203
199/* This driver is not critical to the boot process 204/* This driver is not critical to the boot process
200 * and is easiest to ioremap when SBus is already 205 * and is easiest to ioremap when SBus is already
201 * initialized, so we install ourselves thusly: 206 * initialized, so we install ourselves thusly:
202 */ 207 */
203__initcall(apc_probe); 208__initcall(apc_init);
204
diff --git a/arch/sparc/kernel/auxio.c b/arch/sparc/kernel/auxio.c
index baf4ed3fb0f..09c857215a5 100644
--- a/arch/sparc/kernel/auxio.c
+++ b/arch/sparc/kernel/auxio.c
@@ -6,6 +6,8 @@
6#include <linux/stddef.h> 6#include <linux/stddef.h>
7#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/spinlock.h> 8#include <linux/spinlock.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
9#include <asm/oplib.h> 11#include <asm/oplib.h>
10#include <asm/io.h> 12#include <asm/io.h>
11#include <asm/auxio.h> 13#include <asm/auxio.h>
@@ -59,7 +61,7 @@ void __init auxio_probe(void)
59 r.flags = auxregs[0].which_io & 0xF; 61 r.flags = auxregs[0].which_io & 0xF;
60 r.start = auxregs[0].phys_addr; 62 r.start = auxregs[0].phys_addr;
61 r.end = auxregs[0].phys_addr + auxregs[0].reg_size - 1; 63 r.end = auxregs[0].phys_addr + auxregs[0].reg_size - 1;
62 auxio_register = sbus_ioremap(&r, 0, auxregs[0].reg_size, "auxio"); 64 auxio_register = of_ioremap(&r, 0, auxregs[0].reg_size, "auxio");
63 /* Fix the address on sun4m and sun4c. */ 65 /* Fix the address on sun4m and sun4c. */
64 if((((unsigned long) auxregs[0].phys_addr) & 3) == 3 || 66 if((((unsigned long) auxregs[0].phys_addr) & 3) == 3 ||
65 sparc_cpu_model == sun4c) 67 sparc_cpu_model == sun4c)
@@ -128,7 +130,7 @@ void __init auxio_power_probe(void)
128 r.flags = regs.which_io & 0xF; 130 r.flags = regs.which_io & 0xF;
129 r.start = regs.phys_addr; 131 r.start = regs.phys_addr;
130 r.end = regs.phys_addr + regs.reg_size - 1; 132 r.end = regs.phys_addr + regs.reg_size - 1;
131 auxio_power_register = (unsigned char *) sbus_ioremap(&r, 0, 133 auxio_power_register = (unsigned char *) of_ioremap(&r, 0,
132 regs.reg_size, "auxpower"); 134 regs.reg_size, "auxpower");
133 135
134 /* Display a quick message on the console. */ 136 /* Display a quick message on the console. */
diff --git a/arch/sparc/kernel/devices.c b/arch/sparc/kernel/devices.c
index b240b8863fd..ad656b044b8 100644
--- a/arch/sparc/kernel/devices.c
+++ b/arch/sparc/kernel/devices.c
@@ -143,7 +143,7 @@ void __init device_scan(void)
143#endif 143#endif
144 clock_stop_probe(); 144 clock_stop_probe();
145 145
146 if (ARCH_SUN4C_SUN4) 146 if (ARCH_SUN4C)
147 sun4c_probe_memerr_reg(); 147 sun4c_probe_memerr_reg();
148 148
149 return; 149 return;
diff --git a/arch/sparc/kernel/dma.c b/arch/sparc/kernel/dma.c
new file mode 100644
index 00000000000..ebc8403b035
--- /dev/null
+++ b/arch/sparc/kernel/dma.c
@@ -0,0 +1,227 @@
1/* dma.c: PCI and SBUS DMA accessors for 32-bit sparc.
2 *
3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
4 */
5
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/dma-mapping.h>
9#include <linux/scatterlist.h>
10#include <linux/mm.h>
11
12#ifdef CONFIG_PCI
13#include <linux/pci.h>
14#endif
15
16#include "dma.h"
17
18int dma_supported(struct device *dev, u64 mask)
19{
20#ifdef CONFIG_PCI
21 if (dev->bus == &pci_bus_type)
22 return pci_dma_supported(to_pci_dev(dev), mask);
23#endif
24 return 0;
25}
26EXPORT_SYMBOL(dma_supported);
27
28int dma_set_mask(struct device *dev, u64 dma_mask)
29{
30#ifdef CONFIG_PCI
31 if (dev->bus == &pci_bus_type)
32 return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
33#endif
34 return -EOPNOTSUPP;
35}
36EXPORT_SYMBOL(dma_set_mask);
37
38void *dma_alloc_coherent(struct device *dev, size_t size,
39 dma_addr_t *dma_handle, gfp_t flag)
40{
41#ifdef CONFIG_PCI
42 if (dev->bus == &pci_bus_type)
43 return pci_alloc_consistent(to_pci_dev(dev), size, dma_handle);
44#endif
45 return sbus_alloc_consistent(dev, size, dma_handle);
46}
47EXPORT_SYMBOL(dma_alloc_coherent);
48
49void dma_free_coherent(struct device *dev, size_t size,
50 void *cpu_addr, dma_addr_t dma_handle)
51{
52#ifdef CONFIG_PCI
53 if (dev->bus == &pci_bus_type) {
54 pci_free_consistent(to_pci_dev(dev), size,
55 cpu_addr, dma_handle);
56 return;
57 }
58#endif
59 sbus_free_consistent(dev, size, cpu_addr, dma_handle);
60}
61EXPORT_SYMBOL(dma_free_coherent);
62
63dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
64 size_t size, enum dma_data_direction direction)
65{
66#ifdef CONFIG_PCI
67 if (dev->bus == &pci_bus_type)
68 return pci_map_single(to_pci_dev(dev), cpu_addr,
69 size, (int)direction);
70#endif
71 return sbus_map_single(dev, cpu_addr, size, (int)direction);
72}
73EXPORT_SYMBOL(dma_map_single);
74
75void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
76 size_t size,
77 enum dma_data_direction direction)
78{
79#ifdef CONFIG_PCI
80 if (dev->bus == &pci_bus_type) {
81 pci_unmap_single(to_pci_dev(dev), dma_addr,
82 size, (int)direction);
83 return;
84 }
85#endif
86 sbus_unmap_single(dev, dma_addr, size, (int)direction);
87}
88EXPORT_SYMBOL(dma_unmap_single);
89
90dma_addr_t dma_map_page(struct device *dev, struct page *page,
91 unsigned long offset, size_t size,
92 enum dma_data_direction direction)
93{
94#ifdef CONFIG_PCI
95 if (dev->bus == &pci_bus_type)
96 return pci_map_page(to_pci_dev(dev), page, offset,
97 size, (int)direction);
98#endif
99 return sbus_map_single(dev, page_address(page) + offset,
100 size, (int)direction);
101}
102EXPORT_SYMBOL(dma_map_page);
103
104void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
105 size_t size, enum dma_data_direction direction)
106{
107#ifdef CONFIG_PCI
108 if (dev->bus == &pci_bus_type) {
109 pci_unmap_page(to_pci_dev(dev), dma_address,
110 size, (int)direction);
111 return;
112 }
113#endif
114 sbus_unmap_single(dev, dma_address, size, (int)direction);
115}
116EXPORT_SYMBOL(dma_unmap_page);
117
118int dma_map_sg(struct device *dev, struct scatterlist *sg,
119 int nents, enum dma_data_direction direction)
120{
121#ifdef CONFIG_PCI
122 if (dev->bus == &pci_bus_type)
123 return pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction);
124#endif
125 return sbus_map_sg(dev, sg, nents, direction);
126}
127EXPORT_SYMBOL(dma_map_sg);
128
129void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
130 int nents, enum dma_data_direction direction)
131{
132#ifdef CONFIG_PCI
133 if (dev->bus == &pci_bus_type) {
134 pci_unmap_sg(to_pci_dev(dev), sg, nents, (int)direction);
135 return;
136 }
137#endif
138 sbus_unmap_sg(dev, sg, nents, (int)direction);
139}
140EXPORT_SYMBOL(dma_unmap_sg);
141
142void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
143 size_t size, enum dma_data_direction direction)
144{
145#ifdef CONFIG_PCI
146 if (dev->bus == &pci_bus_type) {
147 pci_dma_sync_single_for_cpu(to_pci_dev(dev), dma_handle,
148 size, (int)direction);
149 return;
150 }
151#endif
152 sbus_dma_sync_single_for_cpu(dev, dma_handle, size, (int) direction);
153}
154EXPORT_SYMBOL(dma_sync_single_for_cpu);
155
156void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
157 size_t size, enum dma_data_direction direction)
158{
159#ifdef CONFIG_PCI
160 if (dev->bus == &pci_bus_type) {
161 pci_dma_sync_single_for_device(to_pci_dev(dev), dma_handle,
162 size, (int)direction);
163 return;
164 }
165#endif
166 sbus_dma_sync_single_for_device(dev, dma_handle, size, (int) direction);
167}
168EXPORT_SYMBOL(dma_sync_single_for_device);
169
170void dma_sync_single_range_for_cpu(struct device *dev,
171 dma_addr_t dma_handle,
172 unsigned long offset,
173 size_t size,
174 enum dma_data_direction direction)
175{
176 dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
177}
178EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
179
180void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
181 unsigned long offset, size_t size,
182 enum dma_data_direction direction)
183{
184 dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
185}
186EXPORT_SYMBOL(dma_sync_single_range_for_device);
187
188void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
189 int nelems, enum dma_data_direction direction)
190{
191#ifdef CONFIG_PCI
192 if (dev->bus == &pci_bus_type) {
193 pci_dma_sync_sg_for_cpu(to_pci_dev(dev), sg,
194 nelems, (int)direction);
195 return;
196 }
197#endif
198 BUG();
199}
200EXPORT_SYMBOL(dma_sync_sg_for_cpu);
201
202void dma_sync_sg_for_device(struct device *dev,
203 struct scatterlist *sg, int nelems,
204 enum dma_data_direction direction)
205{
206#ifdef CONFIG_PCI
207 if (dev->bus == &pci_bus_type) {
208 pci_dma_sync_sg_for_device(to_pci_dev(dev), sg,
209 nelems, (int)direction);
210 return;
211 }
212#endif
213 BUG();
214}
215EXPORT_SYMBOL(dma_sync_sg_for_device);
216
217int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
218{
219 return (dma_addr == DMA_ERROR_CODE);
220}
221EXPORT_SYMBOL(dma_mapping_error);
222
223int dma_get_cache_alignment(void)
224{
225 return 32;
226}
227EXPORT_SYMBOL(dma_get_cache_alignment);
diff --git a/arch/sparc/kernel/dma.h b/arch/sparc/kernel/dma.h
new file mode 100644
index 00000000000..f8d8951adb5
--- /dev/null
+++ b/arch/sparc/kernel/dma.h
@@ -0,0 +1,14 @@
1void *sbus_alloc_consistent(struct device *dev, long len, u32 *dma_addrp);
2void sbus_free_consistent(struct device *dev, long n, void *p, u32 ba);
3dma_addr_t sbus_map_single(struct device *dev, void *va,
4 size_t len, int direction);
5void sbus_unmap_single(struct device *dev, dma_addr_t ba,
6 size_t n, int direction);
7int sbus_map_sg(struct device *dev, struct scatterlist *sg,
8 int n, int direction);
9void sbus_unmap_sg(struct device *dev, struct scatterlist *sg,
10 int n, int direction);
11void sbus_dma_sync_single_for_cpu(struct device *dev, dma_addr_t ba,
12 size_t size, int direction);
13void sbus_dma_sync_single_for_device(struct device *dev, dma_addr_t ba,
14 size_t size, int direction);
diff --git a/arch/sparc/kernel/ebus.c b/arch/sparc/kernel/ebus.c
deleted file mode 100644
index 97294232259..00000000000
--- a/arch/sparc/kernel/ebus.c
+++ /dev/null
@@ -1,393 +0,0 @@
1/*
2 * ebus.c: PCI to EBus bridge device.
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 *
6 * Adopted for sparc by V. Roganov and G. Raiko.
7 * Fixes for different platforms by Pete Zaitcev.
8 */
9
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
14#include <linux/string.h>
15
16#include <asm/system.h>
17#include <asm/page.h>
18#include <asm/pbm.h>
19#include <asm/ebus.h>
20#include <asm/io.h>
21#include <asm/oplib.h>
22#include <asm/prom.h>
23#include <asm/bpp.h>
24
25struct linux_ebus *ebus_chain = NULL;
26
27/* We are together with pcic.c under CONFIG_PCI. */
28extern unsigned int pcic_pin_to_irq(unsigned int, const char *name);
29
30/*
31 * IRQ Blacklist
32 * Here we list PROMs and systems that are known to supply crap as IRQ numbers.
33 */
34struct ebus_device_irq {
35 char *name;
36 unsigned int pin;
37};
38
39struct ebus_system_entry {
40 char *esname;
41 struct ebus_device_irq *ipt;
42};
43
44static struct ebus_device_irq je1_1[] = {
45 { "8042", 3 },
46 { "SUNW,CS4231", 0 },
47 { "parallel", 0 },
48 { "se", 2 },
49 { NULL, 0 }
50};
51
52/*
53 * Gleb's JE1 supplied reasonable pin numbers, but mine did not (OBP 2.32).
54 * Blacklist the sucker... Note that Gleb's system will work.
55 */
56static struct ebus_system_entry ebus_blacklist[] = {
57 { "SUNW,JavaEngine1", je1_1 },
58 { NULL, NULL }
59};
60
61static struct ebus_device_irq *ebus_blackp = NULL;
62
63/*
64 */
65static inline unsigned long ebus_alloc(size_t size)
66{
67 return (unsigned long)kmalloc(size, GFP_ATOMIC);
68}
69
70/*
71 */
72static int __init ebus_blacklist_irq(const char *name)
73{
74 struct ebus_device_irq *dp;
75
76 if ((dp = ebus_blackp) != NULL) {
77 for (; dp->name != NULL; dp++) {
78 if (strcmp(name, dp->name) == 0) {
79 return pcic_pin_to_irq(dp->pin, name);
80 }
81 }
82 }
83 return 0;
84}
85
86static void __init fill_ebus_child(struct device_node *dp,
87 struct linux_ebus_child *dev)
88{
89 const int *regs;
90 const int *irqs;
91 int i, len;
92
93 dev->prom_node = dp;
94 regs = of_get_property(dp, "reg", &len);
95 if (!regs)
96 len = 0;
97 dev->num_addrs = len / sizeof(regs[0]);
98
99 for (i = 0; i < dev->num_addrs; i++) {
100 if (regs[i] >= dev->parent->num_addrs) {
101 prom_printf("UGH: property for %s was %d, need < %d\n",
102 dev->prom_node->name, len,
103 dev->parent->num_addrs);
104 panic(__func__);
105 }
106
107 /* XXX resource */
108 dev->resource[i].start =
109 dev->parent->resource[regs[i]].start;
110 }
111
112 for (i = 0; i < PROMINTR_MAX; i++)
113 dev->irqs[i] = PCI_IRQ_NONE;
114
115 if ((dev->irqs[0] = ebus_blacklist_irq(dev->prom_node->name)) != 0) {
116 dev->num_irqs = 1;
117 } else {
118 irqs = of_get_property(dp, "interrupts", &len);
119 if (!irqs) {
120 dev->num_irqs = 0;
121 dev->irqs[0] = 0;
122 if (dev->parent->num_irqs != 0) {
123 dev->num_irqs = 1;
124 dev->irqs[0] = dev->parent->irqs[0];
125 }
126 } else {
127 dev->num_irqs = len / sizeof(irqs[0]);
128 if (irqs[0] == 0 || irqs[0] >= 8) {
129 /*
130 * XXX Zero is a valid pin number...
131 * This works as long as Ebus is not wired
132 * to INTA#.
133 */
134 printk("EBUS: %s got bad irq %d from PROM\n",
135 dev->prom_node->name, irqs[0]);
136 dev->num_irqs = 0;
137 dev->irqs[0] = 0;
138 } else {
139 dev->irqs[0] =
140 pcic_pin_to_irq(irqs[0],
141 dev->prom_node->name);
142 }
143 }
144 }
145}
146
147static void __init fill_ebus_device(struct device_node *dp,
148 struct linux_ebus_device *dev)
149{
150 const struct linux_prom_registers *regs;
151 struct linux_ebus_child *child;
152 struct dev_archdata *sd;
153 const int *irqs;
154 int i, n, len;
155 unsigned long baseaddr;
156
157 dev->prom_node = dp;
158
159 regs = of_get_property(dp, "reg", &len);
160 if (!regs)
161 len = 0;
162 if (len % sizeof(struct linux_prom_registers)) {
163 prom_printf("UGH: proplen for %s was %d, need multiple of %d\n",
164 dev->prom_node->name, len,
165 (int)sizeof(struct linux_prom_registers));
166 panic(__func__);
167 }
168 dev->num_addrs = len / sizeof(struct linux_prom_registers);
169
170 for (i = 0; i < dev->num_addrs; i++) {
171 /*
172 * XXX Collect JE-1 PROM
173 *
174 * Example - JS-E with 3.11:
175 * /ebus
176 * regs
177 * 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000,
178 * 0x82000010, 0x0, 0xf0000000, 0x0, 0x01000000,
179 * 0x82000014, 0x0, 0x38800000, 0x0, 0x00800000,
180 * ranges
181 * 0x00, 0x00000000, 0x02000010, 0x0, 0x0, 0x01000000,
182 * 0x01, 0x01000000, 0x02000014, 0x0, 0x0, 0x00800000,
183 * /ebus/8042
184 * regs
185 * 0x00000001, 0x00300060, 0x00000008,
186 * 0x00000001, 0x00300060, 0x00000008,
187 */
188 n = regs[i].which_io;
189 if (n >= 4) {
190 /* XXX This is copied from old JE-1 by Gleb. */
191 n = (regs[i].which_io - 0x10) >> 2;
192 } else {
193 ;
194 }
195
196/*
197 * XXX Now as we have regions, why don't we make an on-demand allocation...
198 */
199 dev->resource[i].start = 0;
200 if ((baseaddr = dev->bus->self->resource[n].start +
201 regs[i].phys_addr) != 0) {
202 /* dev->resource[i].name = dev->prom_name; */
203 if ((baseaddr = (unsigned long) ioremap(baseaddr,
204 regs[i].reg_size)) == 0) {
205 panic("ebus: unable to remap dev %s",
206 dev->prom_node->name);
207 }
208 }
209 dev->resource[i].start = baseaddr; /* XXX Unaligned */
210 }
211
212 for (i = 0; i < PROMINTR_MAX; i++)
213 dev->irqs[i] = PCI_IRQ_NONE;
214
215 if ((dev->irqs[0] = ebus_blacklist_irq(dev->prom_node->name)) != 0) {
216 dev->num_irqs = 1;
217 } else {
218 irqs = of_get_property(dp, "interrupts", &len);
219 if (!irqs) {
220 dev->num_irqs = 0;
221 if ((dev->irqs[0] = dev->bus->self->irq) != 0) {
222 dev->num_irqs = 1;
223/* P3 */ /* printk("EBUS: child %s irq %d from parent\n", dev->prom_name, dev->irqs[0]); */
224 }
225 } else {
226 dev->num_irqs = 1; /* dev->num_irqs = len / sizeof(irqs[0]); */
227 if (irqs[0] == 0 || irqs[0] >= 8) {
228 /* See above for the parent. XXX */
229 printk("EBUS: %s got bad irq %d from PROM\n",
230 dev->prom_node->name, irqs[0]);
231 dev->num_irqs = 0;
232 dev->irqs[0] = 0;
233 } else {
234 dev->irqs[0] =
235 pcic_pin_to_irq(irqs[0],
236 dev->prom_node->name);
237 }
238 }
239 }
240
241 sd = &dev->ofdev.dev.archdata;
242 sd->prom_node = dp;
243 sd->op = &dev->ofdev;
244 sd->iommu = dev->bus->ofdev.dev.parent->archdata.iommu;
245
246 dev->ofdev.node = dp;
247 dev->ofdev.dev.parent = &dev->bus->ofdev.dev;
248 dev->ofdev.dev.bus = &ebus_bus_type;
249 sprintf(dev->ofdev.dev.bus_id, "ebus[%08x]", dp->node);
250
251 /* Register with core */
252 if (of_device_register(&dev->ofdev) != 0)
253 printk(KERN_DEBUG "ebus: device registration error for %s!\n",
254 dp->path_component_name);
255
256 if ((dp = dp->child) != NULL) {
257 dev->children = (struct linux_ebus_child *)
258 ebus_alloc(sizeof(struct linux_ebus_child));
259
260 child = dev->children;
261 child->next = NULL;
262 child->parent = dev;
263 child->bus = dev->bus;
264 fill_ebus_child(dp, child);
265
266 while ((dp = dp->sibling) != NULL) {
267 child->next = (struct linux_ebus_child *)
268 ebus_alloc(sizeof(struct linux_ebus_child));
269
270 child = child->next;
271 child->next = NULL;
272 child->parent = dev;
273 child->bus = dev->bus;
274 fill_ebus_child(dp, child);
275 }
276 }
277}
278
279void __init ebus_init(void)
280{
281 const struct linux_prom_pci_registers *regs;
282 struct linux_pbm_info *pbm;
283 struct linux_ebus_device *dev;
284 struct linux_ebus *ebus;
285 struct ebus_system_entry *sp;
286 struct pci_dev *pdev;
287 struct pcidev_cookie *cookie;
288 struct device_node *dp;
289 struct resource *p;
290 unsigned short pci_command;
291 int len, reg, nreg;
292 int num_ebus = 0;
293
294 dp = of_find_node_by_path("/");
295 for (sp = ebus_blacklist; sp->esname != NULL; sp++) {
296 if (strcmp(dp->name, sp->esname) == 0) {
297 ebus_blackp = sp->ipt;
298 break;
299 }
300 }
301
302 pdev = pci_get_device(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_EBUS, NULL);
303 if (!pdev)
304 return;
305
306 cookie = pdev->sysdata;
307 dp = cookie->prom_node;
308
309 ebus_chain = ebus = (struct linux_ebus *)
310 ebus_alloc(sizeof(struct linux_ebus));
311 ebus->next = NULL;
312
313 while (dp) {
314 struct device_node *nd;
315
316 ebus->prom_node = dp;
317 ebus->self = pdev;
318 ebus->parent = pbm = cookie->pbm;
319
320 /* Enable BUS Master. */
321 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
322 pci_command |= PCI_COMMAND_MASTER;
323 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
324
325 regs = of_get_property(dp, "reg", &len);
326 if (!regs) {
327 prom_printf("%s: can't find reg property\n",
328 __func__);
329 prom_halt();
330 }
331 nreg = len / sizeof(struct linux_prom_pci_registers);
332
333 p = &ebus->self->resource[0];
334 for (reg = 0; reg < nreg; reg++) {
335 if (!(regs[reg].which_io & 0x03000000))
336 continue;
337
338 (p++)->start = regs[reg].phys_lo;
339 }
340
341 ebus->ofdev.node = dp;
342 ebus->ofdev.dev.parent = &pdev->dev;
343 ebus->ofdev.dev.bus = &ebus_bus_type;
344 sprintf(ebus->ofdev.dev.bus_id, "ebus%d", num_ebus);
345
346 /* Register with core */
347 if (of_device_register(&ebus->ofdev) != 0)
348 printk(KERN_DEBUG "ebus: device registration error for %s!\n",
349 dp->path_component_name);
350
351
352 nd = dp->child;
353 if (!nd)
354 goto next_ebus;
355
356 ebus->devices = (struct linux_ebus_device *)
357 ebus_alloc(sizeof(struct linux_ebus_device));
358
359 dev = ebus->devices;
360 dev->next = NULL;
361 dev->children = NULL;
362 dev->bus = ebus;
363 fill_ebus_device(nd, dev);
364
365 while ((nd = nd->sibling) != NULL) {
366 dev->next = (struct linux_ebus_device *)
367 ebus_alloc(sizeof(struct linux_ebus_device));
368
369 dev = dev->next;
370 dev->next = NULL;
371 dev->children = NULL;
372 dev->bus = ebus;
373 fill_ebus_device(nd, dev);
374 }
375
376 next_ebus:
377 pdev = pci_get_device(PCI_VENDOR_ID_SUN,
378 PCI_DEVICE_ID_SUN_EBUS, pdev);
379 if (!pdev)
380 break;
381
382 cookie = pdev->sysdata;
383 dp = cookie->prom_node;
384
385 ebus->next = (struct linux_ebus *)
386 ebus_alloc(sizeof(struct linux_ebus));
387 ebus = ebus->next;
388 ebus->next = NULL;
389 ++num_ebus;
390 }
391 if (pdev)
392 pci_dev_put(pdev);
393}
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index e8cdf715a54..faf9ccd9ef5 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -20,11 +20,7 @@
20#include <asm/memreg.h> 20#include <asm/memreg.h>
21#include <asm/page.h> 21#include <asm/page.h>
22#include <asm/pgtable.h> 22#include <asm/pgtable.h>
23#ifdef CONFIG_SUN4
24#include <asm/pgtsun4.h>
25#else
26#include <asm/pgtsun4c.h> 23#include <asm/pgtsun4c.h>
27#endif
28#include <asm/winmacro.h> 24#include <asm/winmacro.h>
29#include <asm/signal.h> 25#include <asm/signal.h>
30#include <asm/obio.h> 26#include <asm/obio.h>
@@ -276,17 +272,18 @@ smp4m_ticker:
276 */ 272 */
277maybe_smp4m_msg: 273maybe_smp4m_msg:
278 GET_PROCESSOR4M_ID(o3) 274 GET_PROCESSOR4M_ID(o3)
279 set sun4m_interrupts, %l5 275 sethi %hi(sun4m_irq_percpu), %l5
280 ld [%l5], %o5 276 sll %o3, 2, %o3
277 or %l5, %lo(sun4m_irq_percpu), %o5
281 sethi %hi(0x40000000), %o2 278 sethi %hi(0x40000000), %o2
282 sll %o3, 12, %o3
283 ld [%o5 + %o3], %o1 279 ld [%o5 + %o3], %o1
284 andcc %o1, %o2, %g0 280 ld [%o1 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
281 andcc %o3, %o2, %g0
285 be,a smp4m_ticker 282 be,a smp4m_ticker
286 cmp %l7, 14 283 cmp %l7, 14
287 st %o2, [%o5 + 0x4] 284 st %o2, [%o1 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x40000000
288 WRITE_PAUSE 285 WRITE_PAUSE
289 ld [%o5], %g0 286 ld [%o1 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
290 WRITE_PAUSE 287 WRITE_PAUSE
291 or %l0, PSR_PIL, %l4 288 or %l0, PSR_PIL, %l4
292 wr %l4, 0x0, %psr 289 wr %l4, 0x0, %psr
@@ -304,16 +301,16 @@ linux_trap_ipi15_sun4m:
304 SAVE_ALL 301 SAVE_ALL
305 sethi %hi(0x80000000), %o2 302 sethi %hi(0x80000000), %o2
306 GET_PROCESSOR4M_ID(o0) 303 GET_PROCESSOR4M_ID(o0)
307 set sun4m_interrupts, %l5 304 sethi %hi(sun4m_irq_percpu), %l5
308 ld [%l5], %o5 305 or %l5, %lo(sun4m_irq_percpu), %o5
309 sll %o0, 12, %o0 306 sll %o0, 2, %o0
310 add %o5, %o0, %o5 307 ld [%o5 + %o0], %o5
311 ld [%o5], %o3 308 ld [%o5 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
312 andcc %o3, %o2, %g0 309 andcc %o3, %o2, %g0
313 be 1f ! Must be an NMI async memory error 310 be 1f ! Must be an NMI async memory error
314 st %o2, [%o5 + 4] 311 st %o2, [%o5 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x80000000
315 WRITE_PAUSE 312 WRITE_PAUSE
316 ld [%o5], %g0 313 ld [%o5 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
317 WRITE_PAUSE 314 WRITE_PAUSE
318 or %l0, PSR_PIL, %l4 315 or %l0, PSR_PIL, %l4
319 wr %l4, 0x0, %psr 316 wr %l4, 0x0, %psr
@@ -327,12 +324,11 @@ linux_trap_ipi15_sun4m:
3271: 3241:
328 /* NMI async memory error handling. */ 325 /* NMI async memory error handling. */
329 sethi %hi(0x80000000), %l4 326 sethi %hi(0x80000000), %l4
330 sethi %hi(0x4000), %o3 327 sethi %hi(sun4m_irq_global), %o5
331 sub %o5, %o0, %o5 328 ld [%o5 + %lo(sun4m_irq_global)], %l5
332 add %o5, %o3, %l5 329 st %l4, [%l5 + 0x0c] ! sun4m_irq_global->mask_set=0x80000000
333 st %l4, [%l5 + 0xc]
334 WRITE_PAUSE 330 WRITE_PAUSE
335 ld [%l5], %g0 331 ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
336 WRITE_PAUSE 332 WRITE_PAUSE
337 or %l0, PSR_PIL, %l4 333 or %l0, PSR_PIL, %l4
338 wr %l4, 0x0, %psr 334 wr %l4, 0x0, %psr
@@ -341,9 +337,9 @@ linux_trap_ipi15_sun4m:
341 WRITE_PAUSE 337 WRITE_PAUSE
342 call sun4m_nmi 338 call sun4m_nmi
343 nop 339 nop
344 st %l4, [%l5 + 0x8] 340 st %l4, [%l5 + 0x08] ! sun4m_irq_global->mask_clear=0x80000000
345 WRITE_PAUSE 341 WRITE_PAUSE
346 ld [%l5], %g0 342 ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
347 WRITE_PAUSE 343 WRITE_PAUSE
348 RESTORE_ALL 344 RESTORE_ALL
349 345
@@ -775,11 +771,7 @@ vac_linesize_patch_32: subcc %l7, 32, %l7
775 * Ugly, but we cant use hardware flushing on the sun4 and we'd require 771 * Ugly, but we cant use hardware flushing on the sun4 and we'd require
776 * two instructions (Anton) 772 * two instructions (Anton)
777 */ 773 */
778#ifdef CONFIG_SUN4
779vac_hwflush_patch1_on: nop
780#else
781vac_hwflush_patch1_on: addcc %l7, -PAGE_SIZE, %l7 774vac_hwflush_patch1_on: addcc %l7, -PAGE_SIZE, %l7
782#endif
783 775
784vac_hwflush_patch2_on: sta %g0, [%l3 + %l7] ASI_HWFLUSHSEG 776vac_hwflush_patch2_on: sta %g0, [%l3 + %l7] ASI_HWFLUSHSEG
785 777
@@ -798,42 +790,10 @@ vac_hwflush_patch2_on: sta %g0, [%l3 + %l7] ASI_HWFLUSHSEG
798! %l7 = 1 for textfault 790! %l7 = 1 for textfault
799! We want error in %l5, vaddr in %l6 791! We want error in %l5, vaddr in %l6
800sun4c_fault: 792sun4c_fault:
801#ifdef CONFIG_SUN4
802 sethi %hi(sun4c_memerr_reg), %l4
803 ld [%l4+%lo(sun4c_memerr_reg)], %l4 ! memerr ctrl reg addr
804 ld [%l4], %l6 ! memerr ctrl reg
805 ld [%l4 + 4], %l5 ! memerr vaddr reg
806 andcc %l6, 0x80, %g0 ! check for error type
807 st %g0, [%l4 + 4] ! clear the error
808 be 0f ! normal error
809 sethi %hi(AC_BUS_ERROR), %l4 ! bus err reg addr
810
811 call prom_halt ! something weird happened
812 ! what exactly did happen?
813 ! what should we do here?
814
8150: or %l4, %lo(AC_BUS_ERROR), %l4 ! bus err reg addr
816 lduba [%l4] ASI_CONTROL, %l6 ! bus err reg
817
818 cmp %l7, 1 ! text fault?
819 be 1f ! yes
820 nop
821
822 ld [%l1], %l4 ! load instruction that caused fault
823 srl %l4, 21, %l4
824 andcc %l4, 1, %g0 ! store instruction?
825
826 be 1f ! no
827 sethi %hi(SUN4C_SYNC_BADWRITE), %l4 ! yep
828 ! %lo(SUN4C_SYNC_BADWRITE) = 0
829 or %l4, %l6, %l6 ! set write bit to emulate sun4c
8301:
831#else
832 sethi %hi(AC_SYNC_ERR), %l4 793 sethi %hi(AC_SYNC_ERR), %l4
833 add %l4, 0x4, %l6 ! AC_SYNC_VA in %l6 794 add %l4, 0x4, %l6 ! AC_SYNC_VA in %l6
834 lda [%l6] ASI_CONTROL, %l5 ! Address 795 lda [%l6] ASI_CONTROL, %l5 ! Address
835 lda [%l4] ASI_CONTROL, %l6 ! Error, retained for a bit 796 lda [%l4] ASI_CONTROL, %l6 ! Error, retained for a bit
836#endif
837 797
838 andn %l5, 0xfff, %l5 ! Encode all info into l7 798 andn %l5, 0xfff, %l5 ! Encode all info into l7
839 srl %l6, 14, %l4 799 srl %l6, 14, %l4
@@ -880,12 +840,7 @@ sun4c_fault:
880 or %l4, %lo(swapper_pg_dir), %l4 840 or %l4, %lo(swapper_pg_dir), %l4
881 sll %l6, 2, %l6 841 sll %l6, 2, %l6
882 ld [%l4 + %l6], %l4 842 ld [%l4 + %l6], %l4
883#ifdef CONFIG_SUN4
884 sethi %hi(PAGE_MASK), %l6
885 andcc %l4, %l6, %g0
886#else
887 andcc %l4, PAGE_MASK, %g0 843 andcc %l4, PAGE_MASK, %g0
888#endif
889 be sun4c_fault_fromuser 844 be sun4c_fault_fromuser
890 lduXa [%l5] ASI_SEGMAP, %l4 845 lduXa [%l5] ASI_SEGMAP, %l4
891 846
@@ -937,11 +892,7 @@ invalid_segment_patch1:
937 ld [%l6 + 0x08], %l3 ! tmp = entry->vaddr 892 ld [%l6 + 0x08], %l3 ! tmp = entry->vaddr
938 893
939 ! Flush segment from the cache. 894 ! Flush segment from the cache.
940#ifdef CONFIG_SUN4
941 sethi %hi((128 * 1024)), %l7
942#else
943 sethi %hi((64 * 1024)), %l7 895 sethi %hi((64 * 1024)), %l7
944#endif
9459: 8969:
946vac_hwflush_patch1: 897vac_hwflush_patch1:
947vac_linesize_patch: 898vac_linesize_patch:
@@ -1029,12 +980,7 @@ invalid_segment_patch2:
1029 or %l4, %lo(swapper_pg_dir), %l4 980 or %l4, %lo(swapper_pg_dir), %l4
1030 sll %l3, 2, %l3 981 sll %l3, 2, %l3
1031 ld [%l4 + %l3], %l4 982 ld [%l4 + %l3], %l4
1032#ifndef CONFIG_SUN4
1033 and %l4, PAGE_MASK, %l4 983 and %l4, PAGE_MASK, %l4
1034#else
1035 sethi %hi(PAGE_MASK), %l6
1036 and %l4, %l6, %l4
1037#endif
1038 984
1039 srl %l5, (PAGE_SHIFT - 2), %l6 985 srl %l5, (PAGE_SHIFT - 2), %l6
1040 and %l6, ((SUN4C_PTRS_PER_PTE - 1) << 2), %l6 986 and %l6, ((SUN4C_PTRS_PER_PTE - 1) << 2), %l6
diff --git a/arch/sparc/kernel/head.S b/arch/sparc/kernel/head.S
index 50d9a16af79..2d325fd8457 100644
--- a/arch/sparc/kernel/head.S
+++ b/arch/sparc/kernel/head.S
@@ -63,15 +63,9 @@ cputypvar_sun4m:
63 63
64 .align 4 64 .align 4
65 65
66#ifndef CONFIG_SUN4
67sun4_notsup: 66sun4_notsup:
68 .asciz "Sparc-Linux sun4 needs a specially compiled kernel, turn CONFIG_SUN4 on.\n\n" 67 .asciz "Sparc-Linux sun4 support does no longer exist.\n\n"
69 .align 4 68 .align 4
70#else
71sun4cdm_notsup:
72 .asciz "Kernel compiled with CONFIG_SUN4 cannot run on SUN4C/SUN4M/SUN4D\nTurn CONFIG_SUN4 off.\n\n"
73 .align 4
74#endif
75 69
76sun4e_notsup: 70sun4e_notsup:
77 .asciz "Sparc-Linux sun4e support does not exist\n\n" 71 .asciz "Sparc-Linux sun4e support does not exist\n\n"
@@ -780,15 +774,6 @@ execute_in_high_mem:
780 nop 774 nop
781 775
782found_version: 776found_version:
783#ifdef CONFIG_SUN4
784/* For people who try sun4 kernels, even if Configure.help advises them. */
785 ld [%g7 + 0x68], %o1
786 set sun4cdm_notsup, %o0
787 call %o1
788 nop
789 b halt_me
790 nop
791#endif
792/* Get the machine type via the mysterious romvec node operations. */ 777/* Get the machine type via the mysterious romvec node operations. */
793 778
794 add %g7, 0x1c, %l1 779 add %g7, 0x1c, %l1
@@ -1150,15 +1135,6 @@ sun4c_continue_boot:
1150 nop 1135 nop
1151 1136
1152sun4_init: 1137sun4_init:
1153#ifdef CONFIG_SUN4
1154/* There, happy now Adrian? */
1155 set cputypval, %o2 ! Let everyone know we
1156 set ' ', %o0 ! are a "sun4 " architecture
1157 stb %o0, [%o2 + 0x4]
1158
1159 b got_prop
1160 nop
1161#else
1162 sethi %hi(SUN4_PROM_VECTOR+0x84), %o1 1138 sethi %hi(SUN4_PROM_VECTOR+0x84), %o1
1163 ld [%o1 + %lo(SUN4_PROM_VECTOR+0x84)], %o1 1139 ld [%o1 + %lo(SUN4_PROM_VECTOR+0x84)], %o1
1164 set sun4_notsup, %o0 1140 set sun4_notsup, %o0
@@ -1170,7 +1146,7 @@ sun4_init:
1170 nop 1146 nop
11711: ba 1b ! Cannot exit into KMON 11471: ba 1b ! Cannot exit into KMON
1172 nop 1148 nop
1173#endif 1149
1174no_sun4e_here: 1150no_sun4e_here:
1175 ld [%g7 + 0x68], %o1 1151 ld [%g7 + 0x68], %o1
1176 set sun4e_notsup, %o0 1152 set sun4e_notsup, %o0
diff --git a/arch/sparc/kernel/idprom.c b/arch/sparc/kernel/idprom.c
index fc511f3c4c1..223a6582e1e 100644
--- a/arch/sparc/kernel/idprom.c
+++ b/arch/sparc/kernel/idprom.c
@@ -12,10 +12,6 @@
12#include <asm/oplib.h> 12#include <asm/oplib.h>
13#include <asm/idprom.h> 13#include <asm/idprom.h>
14#include <asm/machines.h> /* Fun with Sun released architectures. */ 14#include <asm/machines.h> /* Fun with Sun released architectures. */
15#ifdef CONFIG_SUN4
16#include <asm/sun4paddr.h>
17extern void sun4setup(void);
18#endif
19 15
20struct idprom *idprom; 16struct idprom *idprom;
21static struct idprom idprom_buffer; 17static struct idprom idprom_buffer;
@@ -101,7 +97,4 @@ void __init idprom_init(void)
101 idprom->id_ethaddr[0], idprom->id_ethaddr[1], 97 idprom->id_ethaddr[0], idprom->id_ethaddr[1],
102 idprom->id_ethaddr[2], idprom->id_ethaddr[3], 98 idprom->id_ethaddr[2], idprom->id_ethaddr[3],
103 idprom->id_ethaddr[4], idprom->id_ethaddr[5]); 99 idprom->id_ethaddr[4], idprom->id_ethaddr[5]);
104#ifdef CONFIG_SUN4
105 sun4setup();
106#endif
107} 100}
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 2a8a847764d..4f025b36934 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -42,10 +42,13 @@
42#include <asm/vaddrs.h> 42#include <asm/vaddrs.h>
43#include <asm/oplib.h> 43#include <asm/oplib.h>
44#include <asm/prom.h> 44#include <asm/prom.h>
45#include <asm/sbus.h>
46#include <asm/page.h> 45#include <asm/page.h>
47#include <asm/pgalloc.h> 46#include <asm/pgalloc.h>
48#include <asm/dma.h> 47#include <asm/dma.h>
48#include <asm/iommu.h>
49#include <asm/io-unit.h>
50
51#include "dma.h"
49 52
50#define mmu_inval_dma_area(p, l) /* Anton pulled it out for 2.4.0-xx */ 53#define mmu_inval_dma_area(p, l) /* Anton pulled it out for 2.4.0-xx */
51 54
@@ -139,15 +142,6 @@ void iounmap(volatile void __iomem *virtual)
139 } 142 }
140} 143}
141 144
142/*
143 */
144void __iomem *sbus_ioremap(struct resource *phyres, unsigned long offset,
145 unsigned long size, char *name)
146{
147 return _sparc_alloc_io(phyres->flags & 0xF,
148 phyres->start + offset, size, name);
149}
150
151void __iomem *of_ioremap(struct resource *res, unsigned long offset, 145void __iomem *of_ioremap(struct resource *res, unsigned long offset,
152 unsigned long size, char *name) 146 unsigned long size, char *name)
153{ 147{
@@ -164,13 +158,6 @@ void of_iounmap(struct resource *res, void __iomem *base, unsigned long size)
164EXPORT_SYMBOL(of_iounmap); 158EXPORT_SYMBOL(of_iounmap);
165 159
166/* 160/*
167 */
168void sbus_iounmap(volatile void __iomem *addr, unsigned long size)
169{
170 iounmap(addr);
171}
172
173/*
174 * Meat of mapping 161 * Meat of mapping
175 */ 162 */
176static void __iomem *_sparc_alloc_io(unsigned int busno, unsigned long phys, 163static void __iomem *_sparc_alloc_io(unsigned int busno, unsigned long phys,
@@ -246,63 +233,19 @@ static void _sparc_free_io(struct resource *res)
246 233
247#ifdef CONFIG_SBUS 234#ifdef CONFIG_SBUS
248 235
249void sbus_set_sbus64(struct sbus_dev *sdev, int x) 236void sbus_set_sbus64(struct device *dev, int x)
250{ 237{
251 printk("sbus_set_sbus64: unsupported\n"); 238 printk("sbus_set_sbus64: unsupported\n");
252} 239}
253 240
254extern unsigned int sun4d_build_irq(struct sbus_dev *sdev, int irq);
255void __init sbus_fill_device_irq(struct sbus_dev *sdev)
256{
257 struct linux_prom_irqs irqs[PROMINTR_MAX];
258 int len;
259
260 len = prom_getproperty(sdev->prom_node, "intr",
261 (char *)irqs, sizeof(irqs));
262 if (len != -1) {
263 sdev->num_irqs = len / 8;
264 if (sdev->num_irqs == 0) {
265 sdev->irqs[0] = 0;
266 } else if (sparc_cpu_model == sun4d) {
267 for (len = 0; len < sdev->num_irqs; len++)
268 sdev->irqs[len] =
269 sun4d_build_irq(sdev, irqs[len].pri);
270 } else {
271 for (len = 0; len < sdev->num_irqs; len++)
272 sdev->irqs[len] = irqs[len].pri;
273 }
274 } else {
275 int interrupts[PROMINTR_MAX];
276
277 /* No "intr" node found-- check for "interrupts" node.
278 * This node contains SBus interrupt levels, not IPLs
279 * as in "intr", and no vector values. We convert
280 * SBus interrupt levels to PILs (platform specific).
281 */
282 len = prom_getproperty(sdev->prom_node, "interrupts",
283 (char *)interrupts, sizeof(interrupts));
284 if (len == -1) {
285 sdev->irqs[0] = 0;
286 sdev->num_irqs = 0;
287 } else {
288 sdev->num_irqs = len / sizeof(int);
289 for (len = 0; len < sdev->num_irqs; len++) {
290 sdev->irqs[len] =
291 sbint_to_irq(sdev, interrupts[len]);
292 }
293 }
294 }
295}
296
297/* 241/*
298 * Allocate a chunk of memory suitable for DMA. 242 * Allocate a chunk of memory suitable for DMA.
299 * Typically devices use them for control blocks. 243 * Typically devices use them for control blocks.
300 * CPU may access them without any explicit flushing. 244 * CPU may access them without any explicit flushing.
301 *
302 * XXX Some clever people know that sdev is not used and supply NULL. Watch.
303 */ 245 */
304void *sbus_alloc_consistent(struct sbus_dev *sdev, long len, u32 *dma_addrp) 246void *sbus_alloc_consistent(struct device *dev, long len, u32 *dma_addrp)
305{ 247{
248 struct of_device *op = to_of_device(dev);
306 unsigned long len_total = (len + PAGE_SIZE-1) & PAGE_MASK; 249 unsigned long len_total = (len + PAGE_SIZE-1) & PAGE_MASK;
307 unsigned long va; 250 unsigned long va;
308 struct resource *res; 251 struct resource *res;
@@ -336,13 +279,10 @@ void *sbus_alloc_consistent(struct sbus_dev *sdev, long len, u32 *dma_addrp)
336 * XXX That's where sdev would be used. Currently we load 279 * XXX That's where sdev would be used. Currently we load
337 * all iommu tables with the same translations. 280 * all iommu tables with the same translations.
338 */ 281 */
339 if (mmu_map_dma_area(dma_addrp, va, res->start, len_total) != 0) 282 if (mmu_map_dma_area(dev, dma_addrp, va, res->start, len_total) != 0)
340 goto err_noiommu; 283 goto err_noiommu;
341 284
342 /* Set the resource name, if known. */ 285 res->name = op->node->name;
343 if (sdev) {
344 res->name = sdev->prom_name;
345 }
346 286
347 return (void *)(unsigned long)res->start; 287 return (void *)(unsigned long)res->start;
348 288
@@ -356,7 +296,7 @@ err_nopages:
356 return NULL; 296 return NULL;
357} 297}
358 298
359void sbus_free_consistent(struct sbus_dev *sdev, long n, void *p, u32 ba) 299void sbus_free_consistent(struct device *dev, long n, void *p, u32 ba)
360{ 300{
361 struct resource *res; 301 struct resource *res;
362 struct page *pgv; 302 struct page *pgv;
@@ -383,8 +323,8 @@ void sbus_free_consistent(struct sbus_dev *sdev, long n, void *p, u32 ba)
383 kfree(res); 323 kfree(res);
384 324
385 /* mmu_inval_dma_area(va, n); */ /* it's consistent, isn't it */ 325 /* mmu_inval_dma_area(va, n); */ /* it's consistent, isn't it */
386 pgv = mmu_translate_dvma(ba); 326 pgv = virt_to_page(p);
387 mmu_unmap_dma_area(ba, n); 327 mmu_unmap_dma_area(dev, ba, n);
388 328
389 __free_pages(pgv, get_order(n)); 329 __free_pages(pgv, get_order(n));
390} 330}
@@ -394,7 +334,7 @@ void sbus_free_consistent(struct sbus_dev *sdev, long n, void *p, u32 ba)
394 * CPU view of this memory may be inconsistent with 334 * CPU view of this memory may be inconsistent with
395 * a device view and explicit flushing is necessary. 335 * a device view and explicit flushing is necessary.
396 */ 336 */
397dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *va, size_t len, int direction) 337dma_addr_t sbus_map_single(struct device *dev, void *va, size_t len, int direction)
398{ 338{
399 /* XXX why are some lengths signed, others unsigned? */ 339 /* XXX why are some lengths signed, others unsigned? */
400 if (len <= 0) { 340 if (len <= 0) {
@@ -404,17 +344,17 @@ dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *va, size_t len, int dire
404 if (len > 256*1024) { /* __get_free_pages() limit */ 344 if (len > 256*1024) { /* __get_free_pages() limit */
405 return 0; 345 return 0;
406 } 346 }
407 return mmu_get_scsi_one(va, len, sdev->bus); 347 return mmu_get_scsi_one(dev, va, len);
408} 348}
409 349
410void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t ba, size_t n, int direction) 350void sbus_unmap_single(struct device *dev, dma_addr_t ba, size_t n, int direction)
411{ 351{
412 mmu_release_scsi_one(ba, n, sdev->bus); 352 mmu_release_scsi_one(dev, ba, n);
413} 353}
414 354
415int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, int n, int direction) 355int sbus_map_sg(struct device *dev, struct scatterlist *sg, int n, int direction)
416{ 356{
417 mmu_get_scsi_sgl(sg, n, sdev->bus); 357 mmu_get_scsi_sgl(dev, sg, n);
418 358
419 /* 359 /*
420 * XXX sparc64 can return a partial length here. sun4c should do this 360 * XXX sparc64 can return a partial length here. sun4c should do this
@@ -423,145 +363,28 @@ int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, int n, int direct
423 return n; 363 return n;
424} 364}
425 365
426void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg, int n, int direction) 366void sbus_unmap_sg(struct device *dev, struct scatterlist *sg, int n, int direction)
427{
428 mmu_release_scsi_sgl(sg, n, sdev->bus);
429}
430
431/*
432 */
433void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t ba, size_t size, int direction)
434{
435#if 0
436 unsigned long va;
437 struct resource *res;
438
439 /* We do not need the resource, just print a message if invalid. */
440 res = _sparc_find_resource(&_sparc_dvma, ba);
441 if (res == NULL)
442 panic("sbus_dma_sync_single: 0x%x\n", ba);
443
444 va = page_address(mmu_translate_dvma(ba)); /* XXX higmem */
445 /*
446 * XXX This bogosity will be fixed with the iommu rewrite coming soon
447 * to a kernel near you. - Anton
448 */
449 /* mmu_inval_dma_area(va, (size + PAGE_SIZE-1) & PAGE_MASK); */
450#endif
451}
452
453void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, dma_addr_t ba, size_t size, int direction)
454{ 367{
455#if 0 368 mmu_release_scsi_sgl(dev, sg, n);
456 unsigned long va;
457 struct resource *res;
458
459 /* We do not need the resource, just print a message if invalid. */
460 res = _sparc_find_resource(&_sparc_dvma, ba);
461 if (res == NULL)
462 panic("sbus_dma_sync_single: 0x%x\n", ba);
463
464 va = page_address(mmu_translate_dvma(ba)); /* XXX higmem */
465 /*
466 * XXX This bogosity will be fixed with the iommu rewrite coming soon
467 * to a kernel near you. - Anton
468 */
469 /* mmu_inval_dma_area(va, (size + PAGE_SIZE-1) & PAGE_MASK); */
470#endif
471} 369}
472 370
473void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sg, int n, int direction) 371void sbus_dma_sync_single_for_cpu(struct device *dev, dma_addr_t ba, size_t size, int direction)
474{ 372{
475 printk("sbus_dma_sync_sg_for_cpu: not implemented yet\n");
476} 373}
477 374
478void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev, struct scatterlist *sg, int n, int direction) 375void sbus_dma_sync_single_for_device(struct device *dev, dma_addr_t ba, size_t size, int direction)
479{ 376{
480 printk("sbus_dma_sync_sg_for_device: not implemented yet\n");
481}
482
483/* Support code for sbus_init(). */
484/*
485 * XXX This functions appears to be a distorted version of
486 * prom_sbus_ranges_init(), with all sun4d stuff cut away.
487 * Ask DaveM what is going on here, how is sun4d supposed to work... XXX
488 */
489/* added back sun4d patch from Thomas Bogendoerfer - should be OK (crn) */
490void __init sbus_arch_bus_ranges_init(struct device_node *pn, struct sbus_bus *sbus)
491{
492 int parent_node = pn->node;
493
494 if (sparc_cpu_model == sun4d) {
495 struct linux_prom_ranges iounit_ranges[PROMREG_MAX];
496 int num_iounit_ranges, len;
497
498 len = prom_getproperty(parent_node, "ranges",
499 (char *) iounit_ranges,
500 sizeof (iounit_ranges));
501 if (len != -1) {
502 num_iounit_ranges =
503 (len / sizeof(struct linux_prom_ranges));
504 prom_adjust_ranges(sbus->sbus_ranges,
505 sbus->num_sbus_ranges,
506 iounit_ranges, num_iounit_ranges);
507 }
508 }
509} 377}
510 378
511void __init sbus_setup_iommu(struct sbus_bus *sbus, struct device_node *dp) 379static int __init sparc_register_ioport(void)
512{
513#ifndef CONFIG_SUN4
514 struct device_node *parent = dp->parent;
515
516 if (sparc_cpu_model != sun4d &&
517 parent != NULL &&
518 !strcmp(parent->name, "iommu")) {
519 extern void iommu_init(int iommu_node, struct sbus_bus *sbus);
520
521 iommu_init(parent->node, sbus);
522 }
523
524 if (sparc_cpu_model == sun4d) {
525 extern void iounit_init(int sbi_node, int iounit_node,
526 struct sbus_bus *sbus);
527
528 iounit_init(dp->node, parent->node, sbus);
529 }
530#endif
531}
532
533void __init sbus_setup_arch_props(struct sbus_bus *sbus, struct device_node *dp)
534{
535 if (sparc_cpu_model == sun4d) {
536 struct device_node *parent = dp->parent;
537
538 sbus->devid = of_getintprop_default(parent, "device-id", 0);
539 sbus->board = of_getintprop_default(parent, "board#", 0);
540 }
541}
542
543int __init sbus_arch_preinit(void)
544{ 380{
545 register_proc_sparc_ioport(); 381 register_proc_sparc_ioport();
546 382
547#ifdef CONFIG_SUN4
548 {
549 extern void sun4_dvma_init(void);
550 sun4_dvma_init();
551 }
552 return 1;
553#else
554 return 0; 383 return 0;
555#endif
556} 384}
557 385
558void __init sbus_arch_postinit(void) 386arch_initcall(sparc_register_ioport);
559{ 387
560 if (sparc_cpu_model == sun4d) {
561 extern void sun4d_init_sbi_irq(void);
562 sun4d_init_sbi_irq();
563 }
564}
565#endif /* CONFIG_SBUS */ 388#endif /* CONFIG_SBUS */
566 389
567#ifdef CONFIG_PCI 390#ifdef CONFIG_PCI
diff --git a/arch/sparc/kernel/irq.h b/arch/sparc/kernel/irq.h
index 32ef3ebd0a8..db751388153 100644
--- a/arch/sparc/kernel/irq.h
+++ b/arch/sparc/kernel/irq.h
@@ -13,7 +13,6 @@ BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
13BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int) 13BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
14BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int) 14BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
15BTFIXUPDEF_CALL(void, clear_clock_irq, void) 15BTFIXUPDEF_CALL(void, clear_clock_irq, void)
16BTFIXUPDEF_CALL(void, clear_profile_irq, int)
17BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int) 16BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
18 17
19static inline void __disable_irq(unsigned int irq) 18static inline void __disable_irq(unsigned int irq)
@@ -41,11 +40,6 @@ static inline void clear_clock_irq(void)
41 BTFIXUP_CALL(clear_clock_irq)(); 40 BTFIXUP_CALL(clear_clock_irq)();
42} 41}
43 42
44static inline void clear_profile_irq(int irq)
45{
46 BTFIXUP_CALL(clear_profile_irq)(irq);
47}
48
49static inline void load_profile_irq(int cpu, int limit) 43static inline void load_profile_irq(int cpu, int limit)
50{ 44{
51 BTFIXUP_CALL(load_profile_irq)(cpu, limit); 45 BTFIXUP_CALL(load_profile_irq)(cpu, limit);
diff --git a/arch/sparc/kernel/of_device.c b/arch/sparc/kernel/of_device.c
index f58c537446a..0837bd52e28 100644
--- a/arch/sparc/kernel/of_device.c
+++ b/arch/sparc/kernel/of_device.c
@@ -29,15 +29,38 @@ struct of_device *of_find_device_by_node(struct device_node *dp)
29} 29}
30EXPORT_SYMBOL(of_find_device_by_node); 30EXPORT_SYMBOL(of_find_device_by_node);
31 31
32#ifdef CONFIG_PCI 32unsigned int irq_of_parse_and_map(struct device_node *node, int index)
33struct bus_type ebus_bus_type; 33{
34EXPORT_SYMBOL(ebus_bus_type); 34 struct of_device *op = of_find_device_by_node(node);
35#endif 35
36 if (!op || index >= op->num_irqs)
37 return 0;
38
39 return op->irqs[index];
40}
41EXPORT_SYMBOL(irq_of_parse_and_map);
42
43/* Take the archdata values for IOMMU, STC, and HOSTDATA found in
44 * BUS and propagate to all child of_device objects.
45 */
46void of_propagate_archdata(struct of_device *bus)
47{
48 struct dev_archdata *bus_sd = &bus->dev.archdata;
49 struct device_node *bus_dp = bus->node;
50 struct device_node *dp;
51
52 for (dp = bus_dp->child; dp; dp = dp->sibling) {
53 struct of_device *op = of_find_device_by_node(dp);
36 54
37#ifdef CONFIG_SBUS 55 op->dev.archdata.iommu = bus_sd->iommu;
38struct bus_type sbus_bus_type; 56 op->dev.archdata.stc = bus_sd->stc;
39EXPORT_SYMBOL(sbus_bus_type); 57 op->dev.archdata.host_controller = bus_sd->host_controller;
40#endif 58 op->dev.archdata.numa_node = bus_sd->numa_node;
59
60 if (dp->child)
61 of_propagate_archdata(op);
62 }
63}
41 64
42struct bus_type of_platform_bus_type; 65struct bus_type of_platform_bus_type;
43EXPORT_SYMBOL(of_platform_bus_type); 66EXPORT_SYMBOL(of_platform_bus_type);
@@ -327,6 +350,27 @@ static int __init build_one_resource(struct device_node *parent,
327 return 1; 350 return 1;
328} 351}
329 352
353static int __init use_1to1_mapping(struct device_node *pp)
354{
355 /* If we have a ranges property in the parent, use it. */
356 if (of_find_property(pp, "ranges", NULL) != NULL)
357 return 0;
358
359 /* Some SBUS devices use intermediate nodes to express
360 * hierarchy within the device itself. These aren't
361 * real bus nodes, and don't have a 'ranges' property.
362 * But, we should still pass the translation work up
363 * to the SBUS itself.
364 */
365 if (!strcmp(pp->name, "dma") ||
366 !strcmp(pp->name, "espdma") ||
367 !strcmp(pp->name, "ledma") ||
368 !strcmp(pp->name, "lebuffer"))
369 return 0;
370
371 return 1;
372}
373
330static int of_resource_verbose; 374static int of_resource_verbose;
331 375
332static void __init build_device_resources(struct of_device *op, 376static void __init build_device_resources(struct of_device *op,
@@ -373,10 +417,7 @@ static void __init build_device_resources(struct of_device *op,
373 417
374 flags = bus->get_flags(reg, 0); 418 flags = bus->get_flags(reg, 0);
375 419
376 /* If the immediate parent has no ranges property to apply, 420 if (use_1to1_mapping(pp)) {
377 * just use a 1<->1 mapping.
378 */
379 if (of_find_property(pp, "ranges", NULL) == NULL) {
380 result = of_read_addr(addr, na); 421 result = of_read_addr(addr, na);
381 goto build_res; 422 goto build_res;
382 } 423 }
@@ -565,15 +606,6 @@ static int __init of_bus_driver_init(void)
565 int err; 606 int err;
566 607
567 err = of_bus_type_init(&of_platform_bus_type, "of"); 608 err = of_bus_type_init(&of_platform_bus_type, "of");
568#ifdef CONFIG_PCI
569 if (!err)
570 err = of_bus_type_init(&ebus_bus_type, "ebus");
571#endif
572#ifdef CONFIG_SBUS
573 if (!err)
574 err = of_bus_type_init(&sbus_bus_type, "sbus");
575#endif
576
577 if (!err) 609 if (!err)
578 scan_of_devices(); 610 scan_of_devices();
579 611
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index a6a6f982337..462584e55fb 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -17,8 +17,6 @@
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/jiffies.h> 18#include <linux/jiffies.h>
19 19
20#include <asm/ebus.h>
21#include <asm/sbus.h> /* for sanity check... */
22#include <asm/swift.h> /* for cache flushing. */ 20#include <asm/swift.h> /* for cache flushing. */
23#include <asm/io.h> 21#include <asm/io.h>
24 22
@@ -430,7 +428,6 @@ static int __init pcic_init(void)
430 428
431 pcic_pbm_scan_bus(pcic); 429 pcic_pbm_scan_bus(pcic);
432 430
433 ebus_init();
434 return 0; 431 return 0;
435} 432}
436 433
@@ -493,10 +490,6 @@ static void pcic_map_pci_device(struct linux_pcic *pcic,
493 * do ioremap() before accessing PC-style I/O, 490 * do ioremap() before accessing PC-style I/O,
494 * we supply virtual, ready to access address. 491 * we supply virtual, ready to access address.
495 * 492 *
496 * Ebus devices do not come here even if
497 * CheerIO makes a similar conversion.
498 * See ebus.c for details.
499 *
500 * Note that request_region() 493 * Note that request_region()
501 * works for these devices. 494 * works for these devices.
502 * 495 *
@@ -677,7 +670,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
677} 670}
678 671
679/* 672/*
680 * pcic_pin_to_irq() is exported to ebus.c. 673 * pcic_pin_to_irq() is exported to bus probing code
681 */ 674 */
682unsigned int 675unsigned int
683pcic_pin_to_irq(unsigned int pin, const char *name) 676pcic_pin_to_irq(unsigned int pin, const char *name)
@@ -904,11 +897,6 @@ static void pcic_enable_irq(unsigned int irq_nr)
904 local_irq_restore(flags); 897 local_irq_restore(flags);
905} 898}
906 899
907static void pcic_clear_profile_irq(int cpu)
908{
909 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
910}
911
912static void pcic_load_profile_irq(int cpu, unsigned int limit) 900static void pcic_load_profile_irq(int cpu, unsigned int limit)
913{ 901{
914 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__); 902 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
@@ -934,7 +922,6 @@ void __init sun4m_pci_init_IRQ(void)
934 BTFIXUPSET_CALL(enable_pil_irq, pcic_enable_pil_irq, BTFIXUPCALL_NORM); 922 BTFIXUPSET_CALL(enable_pil_irq, pcic_enable_pil_irq, BTFIXUPCALL_NORM);
935 BTFIXUPSET_CALL(disable_pil_irq, pcic_disable_pil_irq, BTFIXUPCALL_NORM); 923 BTFIXUPSET_CALL(disable_pil_irq, pcic_disable_pil_irq, BTFIXUPCALL_NORM);
936 BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM); 924 BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM);
937 BTFIXUPSET_CALL(clear_profile_irq, pcic_clear_profile_irq, BTFIXUPCALL_NORM);
938 BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM); 925 BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM);
939} 926}
940 927
diff --git a/arch/sparc/kernel/pmc.c b/arch/sparc/kernel/pmc.c
index 7eca8871ff4..2afcfab4f11 100644
--- a/arch/sparc/kernel/pmc.c
+++ b/arch/sparc/kernel/pmc.c
@@ -8,11 +8,11 @@
8#include <linux/fs.h> 8#include <linux/fs.h>
9#include <linux/errno.h> 9#include <linux/errno.h>
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/miscdevice.h>
12#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
13 14
14#include <asm/io.h> 15#include <asm/io.h>
15#include <asm/sbus.h>
16#include <asm/oplib.h> 16#include <asm/oplib.h>
17#include <asm/uaccess.h> 17#include <asm/uaccess.h>
18#include <asm/auxio.h> 18#include <asm/auxio.h>
@@ -23,17 +23,15 @@
23 * #define PMC_NO_IDLE 23 * #define PMC_NO_IDLE
24 */ 24 */
25 25
26#define PMC_MINOR MISC_DYNAMIC_MINOR
27#define PMC_OBPNAME "SUNW,pmc" 26#define PMC_OBPNAME "SUNW,pmc"
28#define PMC_DEVNAME "pmc" 27#define PMC_DEVNAME "pmc"
29 28
30#define PMC_IDLE_REG 0x00 29#define PMC_IDLE_REG 0x00
31#define PMC_IDLE_ON 0x01 30#define PMC_IDLE_ON 0x01
32 31
33volatile static u8 __iomem *regs; 32static u8 __iomem *regs;
34static int pmc_regsize;
35 33
36#define pmc_readb(offs) (sbus_readb(regs+offs)) 34#define pmc_readb(offs) (sbus_readb(regs+offs))
37#define pmc_writeb(val, offs) (sbus_writeb(val, regs+offs)) 35#define pmc_writeb(val, offs) (sbus_writeb(val, regs+offs))
38 36
39/* 37/*
@@ -53,31 +51,11 @@ void pmc_swift_idle(void)
53#endif 51#endif
54} 52}
55 53
56static inline void pmc_free(void) 54static int __devinit pmc_probe(struct of_device *op,
55 const struct of_device_id *match)
57{ 56{
58 sbus_iounmap(regs, pmc_regsize); 57 regs = of_ioremap(&op->resource[0], 0,
59} 58 resource_size(&op->resource[0]), PMC_OBPNAME);
60
61static int __init pmc_probe(void)
62{
63 struct sbus_bus *sbus = NULL;
64 struct sbus_dev *sdev = NULL;
65 for_each_sbus(sbus) {
66 for_each_sbusdev(sdev, sbus) {
67 if (!strcmp(sdev->prom_name, PMC_OBPNAME)) {
68 goto sbus_done;
69 }
70 }
71 }
72
73sbus_done:
74 if (!sdev) {
75 return -ENODEV;
76 }
77
78 pmc_regsize = sdev->reg_addrs[0].reg_size;
79 regs = sbus_ioremap(&sdev->resource[0], 0,
80 pmc_regsize, PMC_OBPNAME);
81 if (!regs) { 59 if (!regs) {
82 printk(KERN_ERR "%s: unable to map registers\n", PMC_DEVNAME); 60 printk(KERN_ERR "%s: unable to map registers\n", PMC_DEVNAME);
83 return -ENODEV; 61 return -ENODEV;
@@ -92,8 +70,27 @@ sbus_done:
92 return 0; 70 return 0;
93} 71}
94 72
73static struct of_device_id __initdata pmc_match[] = {
74 {
75 .name = PMC_OBPNAME,
76 },
77 {},
78};
79MODULE_DEVICE_TABLE(of, pmc_match);
80
81static struct of_platform_driver pmc_driver = {
82 .name = "pmc",
83 .match_table = pmc_match,
84 .probe = pmc_probe,
85};
86
87static int __init pmc_init(void)
88{
89 return of_register_driver(&pmc_driver, &of_bus_type);
90}
91
95/* This driver is not critical to the boot process 92/* This driver is not critical to the boot process
96 * and is easiest to ioremap when SBus is already 93 * and is easiest to ioremap when SBus is already
97 * initialized, so we install ourselves thusly: 94 * initialized, so we install ourselves thusly:
98 */ 95 */
99__initcall(pmc_probe); 96__initcall(pmc_init);
diff --git a/arch/sparc/kernel/process.c b/arch/sparc/kernel/process.c
index 4bb430940a6..e8c43ffe317 100644
--- a/arch/sparc/kernel/process.c
+++ b/arch/sparc/kernel/process.c
@@ -75,7 +75,7 @@ void cpu_idle(void)
75{ 75{
76 /* endless idle loop with no priority at all */ 76 /* endless idle loop with no priority at all */
77 for (;;) { 77 for (;;) {
78 if (ARCH_SUN4C_SUN4) { 78 if (ARCH_SUN4C) {
79 static int count = HZ; 79 static int count = HZ;
80 static unsigned long last_jiffies; 80 static unsigned long last_jiffies;
81 static unsigned long last_faults; 81 static unsigned long last_faults;
diff --git a/arch/sparc/kernel/prom.c b/arch/sparc/kernel/prom.c
index cd4fb79aa3a..eee5efcfe50 100644
--- a/arch/sparc/kernel/prom.c
+++ b/arch/sparc/kernel/prom.c
@@ -54,6 +54,9 @@ int of_getintprop_default(struct device_node *np, const char *name, int def)
54} 54}
55EXPORT_SYMBOL(of_getintprop_default); 55EXPORT_SYMBOL(of_getintprop_default);
56 56
57DEFINE_MUTEX(of_set_property_mutex);
58EXPORT_SYMBOL(of_set_property_mutex);
59
57int of_set_property(struct device_node *dp, const char *name, void *val, int len) 60int of_set_property(struct device_node *dp, const char *name, void *val, int len)
58{ 61{
59 struct property **prevp; 62 struct property **prevp;
@@ -77,7 +80,10 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
77 void *old_val = prop->value; 80 void *old_val = prop->value;
78 int ret; 81 int ret;
79 82
83 mutex_lock(&of_set_property_mutex);
80 ret = prom_setprop(dp->node, (char *) name, val, len); 84 ret = prom_setprop(dp->node, (char *) name, val, len);
85 mutex_unlock(&of_set_property_mutex);
86
81 err = -EINVAL; 87 err = -EINVAL;
82 if (ret >= 0) { 88 if (ret >= 0) {
83 prop->value = new_val; 89 prop->value = new_val;
@@ -436,7 +442,6 @@ static void __init of_console_init(void)
436 442
437 switch (prom_vers) { 443 switch (prom_vers) {
438 case PROM_V0: 444 case PROM_V0:
439 case PROM_SUN4:
440 skip = 0; 445 skip = 0;
441 switch (*romvec->pv_stdout) { 446 switch (*romvec->pv_stdout) {
442 case PROMDEV_SCREEN: 447 case PROMDEV_SCREEN:
diff --git a/arch/sparc/kernel/setup.c b/arch/sparc/kernel/setup.c
index 9e451b21202..24fe3078bd4 100644
--- a/arch/sparc/kernel/setup.c
+++ b/arch/sparc/kernel/setup.c
@@ -213,23 +213,25 @@ void __init setup_arch(char **cmdline_p)
213 /* Initialize PROM console and command line. */ 213 /* Initialize PROM console and command line. */
214 *cmdline_p = prom_getbootargs(); 214 *cmdline_p = prom_getbootargs();
215 strcpy(boot_command_line, *cmdline_p); 215 strcpy(boot_command_line, *cmdline_p);
216 parse_early_param();
216 217
217 /* Set sparc_cpu_model */ 218 /* Set sparc_cpu_model */
218 sparc_cpu_model = sun_unknown; 219 sparc_cpu_model = sun_unknown;
219 if(!strcmp(&cputypval,"sun4 ")) { sparc_cpu_model=sun4; } 220 if (!strcmp(&cputypval,"sun4 "))
220 if(!strcmp(&cputypval,"sun4c")) { sparc_cpu_model=sun4c; } 221 sparc_cpu_model = sun4;
221 if(!strcmp(&cputypval,"sun4m")) { sparc_cpu_model=sun4m; } 222 if (!strcmp(&cputypval,"sun4c"))
222 if(!strcmp(&cputypval,"sun4s")) { sparc_cpu_model=sun4m; } /* CP-1200 with PROM 2.30 -E */ 223 sparc_cpu_model = sun4c;
223 if(!strcmp(&cputypval,"sun4d")) { sparc_cpu_model=sun4d; } 224 if (!strcmp(&cputypval,"sun4m"))
224 if(!strcmp(&cputypval,"sun4e")) { sparc_cpu_model=sun4e; } 225 sparc_cpu_model = sun4m;
225 if(!strcmp(&cputypval,"sun4u")) { sparc_cpu_model=sun4u; } 226 if (!strcmp(&cputypval,"sun4s"))
226 227 sparc_cpu_model = sun4m; /* CP-1200 with PROM 2.30 -E */
227#ifdef CONFIG_SUN4 228 if (!strcmp(&cputypval,"sun4d"))
228 if (sparc_cpu_model != sun4) { 229 sparc_cpu_model = sun4d;
229 prom_printf("This kernel is for Sun4 architecture only.\n"); 230 if (!strcmp(&cputypval,"sun4e"))
230 prom_halt(); 231 sparc_cpu_model = sun4e;
231 } 232 if (!strcmp(&cputypval,"sun4u"))
232#endif 233 sparc_cpu_model = sun4u;
234
233 printk("ARCH: "); 235 printk("ARCH: ");
234 switch(sparc_cpu_model) { 236 switch(sparc_cpu_model) {
235 case sun4: 237 case sun4:
@@ -263,7 +265,7 @@ void __init setup_arch(char **cmdline_p)
263 boot_flags_init(*cmdline_p); 265 boot_flags_init(*cmdline_p);
264 266
265 idprom_init(); 267 idprom_init();
266 if (ARCH_SUN4C_SUN4) 268 if (ARCH_SUN4C)
267 sun4c_probe_vac(); 269 sun4c_probe_vac();
268 load_mmu(); 270 load_mmu();
269 271
diff --git a/arch/sparc/kernel/sparc_ksyms.c b/arch/sparc/kernel/sparc_ksyms.c
index b23cea5ca5d..b0dfff84865 100644
--- a/arch/sparc/kernel/sparc_ksyms.c
+++ b/arch/sparc/kernel/sparc_ksyms.c
@@ -38,17 +38,12 @@
38#include <asm/idprom.h> 38#include <asm/idprom.h>
39#include <asm/head.h> 39#include <asm/head.h>
40#include <asm/smp.h> 40#include <asm/smp.h>
41#include <asm/mostek.h>
42#include <asm/ptrace.h> 41#include <asm/ptrace.h>
43#include <asm/uaccess.h> 42#include <asm/uaccess.h>
44#include <asm/checksum.h> 43#include <asm/checksum.h>
45#ifdef CONFIG_SBUS 44#ifdef CONFIG_SBUS
46#include <asm/sbus.h>
47#include <asm/dma.h> 45#include <asm/dma.h>
48#endif 46#endif
49#ifdef CONFIG_PCI
50#include <asm/ebus.h>
51#endif
52#include <asm/io-unit.h> 47#include <asm/io-unit.h>
53#include <asm/bug.h> 48#include <asm/bug.h>
54 49
@@ -127,16 +122,11 @@ EXPORT_SYMBOL(phys_cpu_present_map);
127EXPORT_SYMBOL(__udelay); 122EXPORT_SYMBOL(__udelay);
128EXPORT_SYMBOL(__ndelay); 123EXPORT_SYMBOL(__ndelay);
129EXPORT_SYMBOL(rtc_lock); 124EXPORT_SYMBOL(rtc_lock);
130EXPORT_SYMBOL(mostek_lock);
131EXPORT_SYMBOL(mstk48t02_regs);
132#ifdef CONFIG_SUN_AUXIO 125#ifdef CONFIG_SUN_AUXIO
133EXPORT_SYMBOL(set_auxio); 126EXPORT_SYMBOL(set_auxio);
134EXPORT_SYMBOL(get_auxio); 127EXPORT_SYMBOL(get_auxio);
135#endif 128#endif
136EXPORT_SYMBOL(io_remap_pfn_range); 129EXPORT_SYMBOL(io_remap_pfn_range);
137 /* P3: iounit_xxx may be needed, sun4d users */
138/* EXPORT_SYMBOL(iounit_map_dma_init); */
139/* EXPORT_SYMBOL(iounit_map_dma_page); */
140 130
141#ifndef CONFIG_SMP 131#ifndef CONFIG_SMP
142EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32)); 132EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32));
@@ -153,24 +143,9 @@ EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_one));
153EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached)); 143EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached));
154 144
155#ifdef CONFIG_SBUS 145#ifdef CONFIG_SBUS
156EXPORT_SYMBOL(sbus_root);
157EXPORT_SYMBOL(dma_chain);
158EXPORT_SYMBOL(sbus_set_sbus64); 146EXPORT_SYMBOL(sbus_set_sbus64);
159EXPORT_SYMBOL(sbus_alloc_consistent);
160EXPORT_SYMBOL(sbus_free_consistent);
161EXPORT_SYMBOL(sbus_map_single);
162EXPORT_SYMBOL(sbus_unmap_single);
163EXPORT_SYMBOL(sbus_map_sg);
164EXPORT_SYMBOL(sbus_unmap_sg);
165EXPORT_SYMBOL(sbus_dma_sync_single_for_cpu);
166EXPORT_SYMBOL(sbus_dma_sync_single_for_device);
167EXPORT_SYMBOL(sbus_dma_sync_sg_for_cpu);
168EXPORT_SYMBOL(sbus_dma_sync_sg_for_device);
169EXPORT_SYMBOL(sbus_iounmap);
170EXPORT_SYMBOL(sbus_ioremap);
171#endif 147#endif
172#ifdef CONFIG_PCI 148#ifdef CONFIG_PCI
173EXPORT_SYMBOL(ebus_chain);
174EXPORT_SYMBOL(insb); 149EXPORT_SYMBOL(insb);
175EXPORT_SYMBOL(outsb); 150EXPORT_SYMBOL(outsb);
176EXPORT_SYMBOL(insw); 151EXPORT_SYMBOL(insw);
diff --git a/arch/sparc/kernel/sun4c_irq.c b/arch/sparc/kernel/sun4c_irq.c
index 340fc395fe2..5dc8a576948 100644
--- a/arch/sparc/kernel/sun4c_irq.c
+++ b/arch/sparc/kernel/sun4c_irq.c
@@ -18,6 +18,8 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
21#include "irq.h" 23#include "irq.h"
22 24
23#include <asm/ptrace.h> 25#include <asm/ptrace.h>
@@ -31,15 +33,8 @@
31#include <asm/traps.h> 33#include <asm/traps.h>
32#include <asm/irq.h> 34#include <asm/irq.h>
33#include <asm/io.h> 35#include <asm/io.h>
34#include <asm/sun4paddr.h>
35#include <asm/idprom.h> 36#include <asm/idprom.h>
36#include <asm/machines.h> 37#include <asm/machines.h>
37#include <asm/sbus.h>
38
39#if 0
40static struct resource sun4c_timer_eb = { "sun4c_timer" };
41static struct resource sun4c_intr_eb = { "sun4c_intr" };
42#endif
43 38
44/* 39/*
45 * Bit field defines for the interrupt registers on various 40 * Bit field defines for the interrupt registers on various
@@ -64,19 +59,7 @@ static struct resource sun4c_intr_eb = { "sun4c_intr" };
64 * 59 *
65 * so don't go making it static, like I tried. sigh. 60 * so don't go making it static, like I tried. sigh.
66 */ 61 */
67unsigned char *interrupt_enable = NULL; 62unsigned char __iomem *interrupt_enable = NULL;
68
69static int sun4c_pil_map[] = { 0, 1, 2, 3, 5, 7, 8, 9 };
70
71static unsigned int sun4c_sbint_to_irq(struct sbus_dev *sdev,
72 unsigned int sbint)
73{
74 if (sbint >= sizeof(sun4c_pil_map)) {
75 printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
76 BUG();
77 }
78 return sun4c_pil_map[sbint];
79}
80 63
81static void sun4c_disable_irq(unsigned int irq_nr) 64static void sun4c_disable_irq(unsigned int irq_nr)
82{ 65{
@@ -85,7 +68,7 @@ static void sun4c_disable_irq(unsigned int irq_nr)
85 68
86 local_irq_save(flags); 69 local_irq_save(flags);
87 irq_nr &= (NR_IRQS - 1); 70 irq_nr &= (NR_IRQS - 1);
88 current_mask = *interrupt_enable; 71 current_mask = sbus_readb(interrupt_enable);
89 switch(irq_nr) { 72 switch(irq_nr) {
90 case 1: 73 case 1:
91 new_mask = ((current_mask) & (~(SUN4C_INT_E1))); 74 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
@@ -103,7 +86,7 @@ static void sun4c_disable_irq(unsigned int irq_nr)
103 local_irq_restore(flags); 86 local_irq_restore(flags);
104 return; 87 return;
105 } 88 }
106 *interrupt_enable = new_mask; 89 sbus_writeb(new_mask, interrupt_enable);
107 local_irq_restore(flags); 90 local_irq_restore(flags);
108} 91}
109 92
@@ -114,7 +97,7 @@ static void sun4c_enable_irq(unsigned int irq_nr)
114 97
115 local_irq_save(flags); 98 local_irq_save(flags);
116 irq_nr &= (NR_IRQS - 1); 99 irq_nr &= (NR_IRQS - 1);
117 current_mask = *interrupt_enable; 100 current_mask = sbus_readb(interrupt_enable);
118 switch(irq_nr) { 101 switch(irq_nr) {
119 case 1: 102 case 1:
120 new_mask = ((current_mask) | SUN4C_INT_E1); 103 new_mask = ((current_mask) | SUN4C_INT_E1);
@@ -132,37 +115,22 @@ static void sun4c_enable_irq(unsigned int irq_nr)
132 local_irq_restore(flags); 115 local_irq_restore(flags);
133 return; 116 return;
134 } 117 }
135 *interrupt_enable = new_mask; 118 sbus_writeb(new_mask, interrupt_enable);
136 local_irq_restore(flags); 119 local_irq_restore(flags);
137} 120}
138 121
139#define TIMER_IRQ 10 /* Also at level 14, but we ignore that one. */ 122struct sun4c_timer_info {
140#define PROFILE_IRQ 14 /* Level14 ticker.. used by OBP for polling */ 123 u32 l10_count;
141 124 u32 l10_limit;
142volatile struct sun4c_timer_info *sun4c_timers; 125 u32 l14_count;
126 u32 l14_limit;
127};
143 128
144#ifdef CONFIG_SUN4 129static struct sun4c_timer_info __iomem *sun4c_timers;
145/* This is an ugly hack to work around the
146 current timer code, and make it work with
147 the sun4/260 intersil
148 */
149volatile struct sun4c_timer_info sun4_timer;
150#endif
151 130
152static void sun4c_clear_clock_irq(void) 131static void sun4c_clear_clock_irq(void)
153{ 132{
154 volatile unsigned int clear_intr; 133 sbus_readl(&sun4c_timers->l10_limit);
155#ifdef CONFIG_SUN4
156 if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
157 clear_intr = sun4_timer.timer_limit10;
158 else
159#endif
160 clear_intr = sun4c_timers->timer_limit10;
161}
162
163static void sun4c_clear_profile_irq(int cpu)
164{
165 /* Errm.. not sure how to do this.. */
166} 134}
167 135
168static void sun4c_load_profile_irq(int cpu, unsigned int limit) 136static void sun4c_load_profile_irq(int cpu, unsigned int limit)
@@ -172,41 +140,48 @@ static void sun4c_load_profile_irq(int cpu, unsigned int limit)
172 140
173static void __init sun4c_init_timers(irq_handler_t counter_fn) 141static void __init sun4c_init_timers(irq_handler_t counter_fn)
174{ 142{
175 int irq; 143 const struct linux_prom_irqs *irq;
144 struct device_node *dp;
145 const u32 *addr;
146 int err;
147
148 dp = of_find_node_by_name(NULL, "counter-timer");
149 if (!dp) {
150 prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
151 prom_halt();
152 }
176 153
177 /* Map the Timer chip, this is implemented in hardware inside 154 addr = of_get_property(dp, "address", NULL);
178 * the cache chip on the sun4c. 155 if (!addr) {
179 */ 156 prom_printf("sun4c_init_timers: No address property\n");
180#ifdef CONFIG_SUN4 157 prom_halt();
181 if (idprom->id_machtype == (SM_SUN4 | SM_4_260)) 158 }
182 sun4c_timers = &sun4_timer; 159
183 else 160 sun4c_timers = (void __iomem *) (unsigned long) addr[0];
184#endif 161
185 sun4c_timers = ioremap(SUN_TIMER_PHYSADDR, 162 irq = of_get_property(dp, "intr", NULL);
186 sizeof(struct sun4c_timer_info)); 163 if (!irq) {
164 prom_printf("sun4c_init_timers: No intr property\n");
165 prom_halt();
166 }
187 167
188 /* Have the level 10 timer tick at 100HZ. We don't touch the 168 /* Have the level 10 timer tick at 100HZ. We don't touch the
189 * level 14 timer limit since we are letting the prom handle 169 * level 14 timer limit since we are letting the prom handle
190 * them until we have a real console driver so L1-A works. 170 * them until we have a real console driver so L1-A works.
191 */ 171 */
192 sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10); 172 sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
193 master_l10_counter = &sun4c_timers->cur_count10;
194 master_l10_limit = &sun4c_timers->timer_limit10;
195 173
196 irq = request_irq(TIMER_IRQ, 174 master_l10_counter = &sun4c_timers->l10_count;
197 counter_fn, 175
176 err = request_irq(irq[0].pri, counter_fn,
198 (IRQF_DISABLED | SA_STATIC_ALLOC), 177 (IRQF_DISABLED | SA_STATIC_ALLOC),
199 "timer", NULL); 178 "timer", NULL);
200 if (irq) { 179 if (err) {
201 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ); 180 prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
202 prom_halt(); 181 prom_halt();
203 } 182 }
204 183
205#if 0 184 sun4c_disable_irq(irq[1].pri);
206 /* This does not work on 4/330 */
207 sun4c_enable_irq(10);
208#endif
209 claim_ticker14(NULL, PROFILE_IRQ, 0);
210} 185}
211 186
212#ifdef CONFIG_SMP 187#ifdef CONFIG_SMP
@@ -215,41 +190,28 @@ static void sun4c_nop(void) {}
215 190
216void __init sun4c_init_IRQ(void) 191void __init sun4c_init_IRQ(void)
217{ 192{
218 struct linux_prom_registers int_regs[2]; 193 struct device_node *dp;
219 int ie_node; 194 const u32 *addr;
220 195
221 if (ARCH_SUN4) { 196 dp = of_find_node_by_name(NULL, "interrupt-enable");
222 interrupt_enable = (char *) 197 if (!dp) {
223 ioremap(sun4_ie_physaddr, PAGE_SIZE); 198 prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
224 } else { 199 prom_halt();
225 struct resource phyres; 200 }
226
227 ie_node = prom_searchsiblings (prom_getchild(prom_root_node),
228 "interrupt-enable");
229 if(ie_node == 0)
230 panic("Cannot find /interrupt-enable node");
231 201
232 /* Depending on the "address" property is bad news... */ 202 addr = of_get_property(dp, "address", NULL);
233 interrupt_enable = NULL; 203 if (!addr) {
234 if (prom_getproperty(ie_node, "reg", (char *) int_regs, 204 prom_printf("sun4c_init_IRQ: No address property\n");
235 sizeof(int_regs)) != -1) { 205 prom_halt();
236 memset(&phyres, 0, sizeof(struct resource));
237 phyres.flags = int_regs[0].which_io;
238 phyres.start = int_regs[0].phys_addr;
239 interrupt_enable = (char *) sbus_ioremap(&phyres, 0,
240 int_regs[0].reg_size, "sun4c_intr");
241 }
242 } 206 }
243 if (!interrupt_enable)
244 panic("Cannot map interrupt_enable");
245 207
246 BTFIXUPSET_CALL(sbint_to_irq, sun4c_sbint_to_irq, BTFIXUPCALL_NORM); 208 interrupt_enable = (void __iomem *) (unsigned long) addr[0];
209
247 BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM); 210 BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
248 BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM); 211 BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
249 BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM); 212 BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
250 BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM); 213 BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
251 BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM); 214 BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
252 BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP);
253 BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP); 215 BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
254 sparc_init_timers = sun4c_init_timers; 216 sparc_init_timers = sun4c_init_timers;
255#ifdef CONFIG_SMP 217#ifdef CONFIG_SMP
@@ -257,6 +219,6 @@ void __init sun4c_init_IRQ(void)
257 BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP); 219 BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
258 BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP); 220 BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
259#endif 221#endif
260 *interrupt_enable = (SUN4C_INT_ENABLE); 222 sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
261 /* Cannot enable interrupts until OBP ticker is disabled. */ 223 /* Cannot enable interrupts until OBP ticker is disabled. */
262} 224}
diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c
index 1290b5998f8..d3cb76ce418 100644
--- a/arch/sparc/kernel/sun4d_irq.c
+++ b/arch/sparc/kernel/sun4d_irq.c
@@ -19,6 +19,8 @@
19#include <linux/smp.h> 19#include <linux/smp.h>
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21#include <linux/seq_file.h> 21#include <linux/seq_file.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
22 24
23#include <asm/ptrace.h> 25#include <asm/ptrace.h>
24#include <asm/processor.h> 26#include <asm/processor.h>
@@ -34,7 +36,6 @@
34#include <asm/io.h> 36#include <asm/io.h>
35#include <asm/pgalloc.h> 37#include <asm/pgalloc.h>
36#include <asm/pgtable.h> 38#include <asm/pgtable.h>
37#include <asm/sbus.h>
38#include <asm/sbi.h> 39#include <asm/sbi.h>
39#include <asm/cacheflush.h> 40#include <asm/cacheflush.h>
40#include <asm/irq_regs.h> 41#include <asm/irq_regs.h>
@@ -44,16 +45,22 @@
44/* If you trust current SCSI layer to handle different SCSI IRQs, enable this. I don't trust it... -jj */ 45/* If you trust current SCSI layer to handle different SCSI IRQs, enable this. I don't trust it... -jj */
45/* #define DISTRIBUTE_IRQS */ 46/* #define DISTRIBUTE_IRQS */
46 47
47struct sun4d_timer_regs *sun4d_timers; 48struct sun4d_timer_regs {
49 u32 l10_timer_limit;
50 u32 l10_cur_countx;
51 u32 l10_limit_noclear;
52 u32 ctrl;
53 u32 l10_cur_count;
54};
55
56static struct sun4d_timer_regs __iomem *sun4d_timers;
57
48#define TIMER_IRQ 10 58#define TIMER_IRQ 10
49 59
50#define MAX_STATIC_ALLOC 4 60#define MAX_STATIC_ALLOC 4
51extern struct irqaction static_irqaction[MAX_STATIC_ALLOC]; 61extern struct irqaction static_irqaction[MAX_STATIC_ALLOC];
52extern int static_irq_count; 62extern int static_irq_count;
53unsigned char cpu_leds[32];
54#ifdef CONFIG_SMP
55static unsigned char sbus_tid[32]; 63static unsigned char sbus_tid[32];
56#endif
57 64
58static struct irqaction *irq_action[NR_IRQS]; 65static struct irqaction *irq_action[NR_IRQS];
59extern spinlock_t irq_action_lock; 66extern spinlock_t irq_action_lock;
@@ -72,9 +79,9 @@ static int sbus_to_pil[] = {
72}; 79};
73 80
74static int nsbi; 81static int nsbi;
75#ifdef CONFIG_SMP 82
83/* Exported for sun4d_smp.c */
76DEFINE_SPINLOCK(sun4d_imsk_lock); 84DEFINE_SPINLOCK(sun4d_imsk_lock);
77#endif
78 85
79int show_sun4d_interrupts(struct seq_file *p, void *v) 86int show_sun4d_interrupts(struct seq_file *p, void *v)
80{ 87{
@@ -257,26 +264,6 @@ void sun4d_handler_irq(int irq, struct pt_regs * regs)
257 set_irq_regs(old_regs); 264 set_irq_regs(old_regs);
258} 265}
259 266
260unsigned int sun4d_build_irq(struct sbus_dev *sdev, int irq)
261{
262 int sbusl = pil_to_sbus[irq];
263
264 if (sbusl)
265 return ((sdev->bus->board + 1) << 5) + (sbusl << 2) + sdev->slot;
266 else
267 return irq;
268}
269
270static unsigned int sun4d_sbint_to_irq(struct sbus_dev *sdev,
271 unsigned int sbint)
272{
273 if (sbint >= sizeof(sbus_to_pil)) {
274 printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
275 BUG();
276 }
277 return sun4d_build_irq(sdev, sbus_to_pil[sbint]);
278}
279
280int sun4d_request_irq(unsigned int irq, 267int sun4d_request_irq(unsigned int irq,
281 irq_handler_t handler, 268 irq_handler_t handler,
282 unsigned long irqflags, const char * devname, void *dev_id) 269 unsigned long irqflags, const char * devname, void *dev_id)
@@ -360,36 +347,28 @@ out:
360 347
361static void sun4d_disable_irq(unsigned int irq) 348static void sun4d_disable_irq(unsigned int irq)
362{ 349{
363#ifdef CONFIG_SMP
364 int tid = sbus_tid[(irq >> 5) - 1]; 350 int tid = sbus_tid[(irq >> 5) - 1];
365 unsigned long flags; 351 unsigned long flags;
366#endif
367 352
368 if (irq < NR_IRQS) return; 353 if (irq < NR_IRQS)
369#ifdef CONFIG_SMP 354 return;
355
370 spin_lock_irqsave(&sun4d_imsk_lock, flags); 356 spin_lock_irqsave(&sun4d_imsk_lock, flags);
371 cc_set_imsk_other(tid, cc_get_imsk_other(tid) | (1 << sbus_to_pil[(irq >> 2) & 7])); 357 cc_set_imsk_other(tid, cc_get_imsk_other(tid) | (1 << sbus_to_pil[(irq >> 2) & 7]));
372 spin_unlock_irqrestore(&sun4d_imsk_lock, flags); 358 spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
373#else
374 cc_set_imsk(cc_get_imsk() | (1 << sbus_to_pil[(irq >> 2) & 7]));
375#endif
376} 359}
377 360
378static void sun4d_enable_irq(unsigned int irq) 361static void sun4d_enable_irq(unsigned int irq)
379{ 362{
380#ifdef CONFIG_SMP
381 int tid = sbus_tid[(irq >> 5) - 1]; 363 int tid = sbus_tid[(irq >> 5) - 1];
382 unsigned long flags; 364 unsigned long flags;
383#endif
384 365
385 if (irq < NR_IRQS) return; 366 if (irq < NR_IRQS)
386#ifdef CONFIG_SMP 367 return;
368
387 spin_lock_irqsave(&sun4d_imsk_lock, flags); 369 spin_lock_irqsave(&sun4d_imsk_lock, flags);
388 cc_set_imsk_other(tid, cc_get_imsk_other(tid) & ~(1 << sbus_to_pil[(irq >> 2) & 7])); 370 cc_set_imsk_other(tid, cc_get_imsk_other(tid) & ~(1 << sbus_to_pil[(irq >> 2) & 7]));
389 spin_unlock_irqrestore(&sun4d_imsk_lock, flags); 371 spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
390#else
391 cc_set_imsk(cc_get_imsk() & ~(1 << sbus_to_pil[(irq >> 2) & 7]));
392#endif
393} 372}
394 373
395#ifdef CONFIG_SMP 374#ifdef CONFIG_SMP
@@ -409,47 +388,55 @@ static void sun4d_set_udt(int cpu)
409/* Setup IRQ distribution scheme. */ 388/* Setup IRQ distribution scheme. */
410void __init sun4d_distribute_irqs(void) 389void __init sun4d_distribute_irqs(void)
411{ 390{
391 struct device_node *dp;
392
412#ifdef DISTRIBUTE_IRQS 393#ifdef DISTRIBUTE_IRQS
413 struct sbus_bus *sbus; 394 cpumask_t sbus_serving_map;
414 unsigned long sbus_serving_map;
415 395
416 sbus_serving_map = cpu_present_map; 396 sbus_serving_map = cpu_present_map;
417 for_each_sbus(sbus) { 397 for_each_node_by_name(dp, "sbi") {
418 if ((sbus->board * 2) == boot_cpu_id && (cpu_present_map & (1 << (sbus->board * 2 + 1)))) 398 int board = of_getintprop_default(dp, "board#", 0);
419 sbus_tid[sbus->board] = (sbus->board * 2 + 1); 399
420 else if (cpu_present_map & (1 << (sbus->board * 2))) 400 if ((board * 2) == boot_cpu_id && cpu_isset(board * 2 + 1, cpu_present_map))
421 sbus_tid[sbus->board] = (sbus->board * 2); 401 sbus_tid[board] = (board * 2 + 1);
422 else if (cpu_present_map & (1 << (sbus->board * 2 + 1))) 402 else if (cpu_isset(board * 2, cpu_present_map))
423 sbus_tid[sbus->board] = (sbus->board * 2 + 1); 403 sbus_tid[board] = (board * 2);
404 else if (cpu_isset(board * 2 + 1, cpu_present_map))
405 sbus_tid[board] = (board * 2 + 1);
424 else 406 else
425 sbus_tid[sbus->board] = 0xff; 407 sbus_tid[board] = 0xff;
426 if (sbus_tid[sbus->board] != 0xff) 408 if (sbus_tid[board] != 0xff)
427 sbus_serving_map &= ~(1 << sbus_tid[sbus->board]); 409 cpu_clear(sbus_tid[board], sbus_serving_map);
428 } 410 }
429 for_each_sbus(sbus) 411 for_each_node_by_name(dp, "sbi") {
430 if (sbus_tid[sbus->board] == 0xff) { 412 int board = of_getintprop_default(dp, "board#", 0);
413 if (sbus_tid[board] == 0xff) {
431 int i = 31; 414 int i = 31;
432 415
433 if (!sbus_serving_map) 416 if (cpus_empty(sbus_serving_map))
434 sbus_serving_map = cpu_present_map; 417 sbus_serving_map = cpu_present_map;
435 while (!(sbus_serving_map & (1 << i))) 418 while (cpu_isset(i, sbus_serving_map))
436 i--; 419 i--;
437 sbus_tid[sbus->board] = i; 420 sbus_tid[board] = i;
438 sbus_serving_map &= ~(1 << i); 421 cpu_clear(i, sbus_serving_map);
439 } 422 }
440 for_each_sbus(sbus) { 423 }
441 printk("sbus%d IRQs directed to CPU%d\n", sbus->board, sbus_tid[sbus->board]); 424 for_each_node_by_name(dp, "sbi") {
442 set_sbi_tid(sbus->devid, sbus_tid[sbus->board] << 3); 425 int devid = of_getintprop_default(dp, "device-id", 0);
426 int board = of_getintprop_default(dp, "board#", 0);
427 printk("sbus%d IRQs directed to CPU%d\n", board, sbus_tid[board]);
428 set_sbi_tid(devid, sbus_tid[board] << 3);
443 } 429 }
444#else 430#else
445 struct sbus_bus *sbus;
446 int cpuid = cpu_logical_map(1); 431 int cpuid = cpu_logical_map(1);
447 432
448 if (cpuid == -1) 433 if (cpuid == -1)
449 cpuid = cpu_logical_map(0); 434 cpuid = cpu_logical_map(0);
450 for_each_sbus(sbus) { 435 for_each_node_by_name(dp, "sbi") {
451 sbus_tid[sbus->board] = cpuid; 436 int devid = of_getintprop_default(dp, "device-id", 0);
452 set_sbi_tid(sbus->devid, cpuid << 3); 437 int board = of_getintprop_default(dp, "board#", 0);
438 sbus_tid[board] = cpuid;
439 set_sbi_tid(devid, cpuid << 3);
453 } 440 }
454 printk("All sbus IRQs directed to CPU%d\n", cpuid); 441 printk("All sbus IRQs directed to CPU%d\n", cpuid);
455#endif 442#endif
@@ -458,13 +445,7 @@ void __init sun4d_distribute_irqs(void)
458 445
459static void sun4d_clear_clock_irq(void) 446static void sun4d_clear_clock_irq(void)
460{ 447{
461 volatile unsigned int clear_intr; 448 sbus_readl(&sun4d_timers->l10_timer_limit);
462 clear_intr = sun4d_timers->l10_timer_limit;
463}
464
465static void sun4d_clear_profile_irq(int cpu)
466{
467 bw_get_prof_limit(cpu);
468} 449}
469 450
470static void sun4d_load_profile_irq(int cpu, unsigned int limit) 451static void sun4d_load_profile_irq(int cpu, unsigned int limit)
@@ -472,98 +453,121 @@ static void sun4d_load_profile_irq(int cpu, unsigned int limit)
472 bw_set_prof_limit(cpu, limit); 453 bw_set_prof_limit(cpu, limit);
473} 454}
474 455
475static void __init sun4d_init_timers(irq_handler_t counter_fn) 456static void __init sun4d_load_profile_irqs(void)
476{ 457{
477 int irq; 458 int cpu = 0, mid;
478 int cpu;
479 struct resource r;
480 int mid;
481 459
482 /* Map the User Timer registers. */ 460 while (!cpu_find_by_instance(cpu, NULL, &mid)) {
483 memset(&r, 0, sizeof(r)); 461 sun4d_load_profile_irq(mid >> 3, 0);
462 cpu++;
463 }
464}
465
466static void __init sun4d_fixup_trap_table(void)
467{
484#ifdef CONFIG_SMP 468#ifdef CONFIG_SMP
485 r.start = CSR_BASE(boot_cpu_id)+BW_TIMER_LIMIT; 469 unsigned long flags;
486#else 470 extern unsigned long lvl14_save[4];
487 r.start = CSR_BASE(0)+BW_TIMER_LIMIT; 471 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
472 extern unsigned int real_irq_entry[], smp4d_ticker[];
473 extern unsigned int patchme_maybe_smp_msg[];
474
475 /* Adjust so that we jump directly to smp4d_ticker */
476 lvl14_save[2] += smp4d_ticker - real_irq_entry;
477
478 /* For SMP we use the level 14 ticker, however the bootup code
479 * has copied the firmware's level 14 vector into the boot cpu's
480 * trap table, we must fix this now or we get squashed.
481 */
482 local_irq_save(flags);
483 patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
484 trap_table->inst_one = lvl14_save[0];
485 trap_table->inst_two = lvl14_save[1];
486 trap_table->inst_three = lvl14_save[2];
487 trap_table->inst_four = lvl14_save[3];
488 local_flush_cache_all();
489 local_irq_restore(flags);
488#endif 490#endif
489 r.flags = 0xf; 491}
490 sun4d_timers = (struct sun4d_timer_regs *) sbus_ioremap(&r, 0,
491 PAGE_SIZE, "user timer");
492 492
493 sun4d_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10); 493static void __init sun4d_init_timers(irq_handler_t counter_fn)
494 master_l10_counter = &sun4d_timers->l10_cur_count; 494{
495 master_l10_limit = &sun4d_timers->l10_timer_limit; 495 struct device_node *dp;
496 struct resource res;
497 const u32 *reg;
498 int err;
499
500 dp = of_find_node_by_name(NULL, "cpu-unit");
501 if (!dp) {
502 prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
503 prom_halt();
504 }
496 505
497 irq = request_irq(TIMER_IRQ, 506 /* Which cpu-unit we use is arbitrary, we can view the bootbus timer
498 counter_fn, 507 * registers via any cpu's mapping. The first 'reg' property is the
499 (IRQF_DISABLED | SA_STATIC_ALLOC), 508 * bootbus.
500 "timer", NULL); 509 */
501 if (irq) { 510 reg = of_get_property(dp, "reg", NULL);
502 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ); 511 if (!reg) {
512 prom_printf("sun4d_init_timers: No reg property\n");
503 prom_halt(); 513 prom_halt();
504 } 514 }
505
506 /* Enable user timer free run for CPU 0 in BW */
507 /* bw_set_ctrl(0, bw_get_ctrl(0) | BW_CTRL_USER_TIMER); */
508 515
509 cpu = 0; 516 res.start = reg[1];
510 while (!cpu_find_by_instance(cpu, NULL, &mid)) { 517 res.end = reg[2] - 1;
511 sun4d_load_profile_irq(mid >> 3, 0); 518 res.flags = reg[0] & 0xff;
512 cpu++; 519 sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
520 sizeof(struct sun4d_timer_regs), "user timer");
521 if (!sun4d_timers) {
522 prom_printf("sun4d_init_timers: Can't map timer regs\n");
523 prom_halt();
513 } 524 }
514 525
515#ifdef CONFIG_SMP 526 sbus_writel((((1000000/HZ) + 1) << 10), &sun4d_timers->l10_timer_limit);
516 { 527
517 unsigned long flags; 528 master_l10_counter = &sun4d_timers->l10_cur_count;
518 extern unsigned long lvl14_save[4]; 529
519 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)]; 530 err = request_irq(TIMER_IRQ, counter_fn,
520 extern unsigned int real_irq_entry[], smp4d_ticker[]; 531 (IRQF_DISABLED | SA_STATIC_ALLOC),
521 extern unsigned int patchme_maybe_smp_msg[]; 532 "timer", NULL);
522 533 if (err) {
523 /* Adjust so that we jump directly to smp4d_ticker */ 534 prom_printf("sun4d_init_timers: request_irq() failed with %d\n", err);
524 lvl14_save[2] += smp4d_ticker - real_irq_entry; 535 prom_halt();
525
526 /* For SMP we use the level 14 ticker, however the bootup code
527 * has copied the firmware's level 14 vector into the boot cpu's
528 * trap table, we must fix this now or we get squashed.
529 */
530 local_irq_save(flags);
531 patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
532 trap_table->inst_one = lvl14_save[0];
533 trap_table->inst_two = lvl14_save[1];
534 trap_table->inst_three = lvl14_save[2];
535 trap_table->inst_four = lvl14_save[3];
536 local_flush_cache_all();
537 local_irq_restore(flags);
538 } 536 }
539#endif 537 sun4d_load_profile_irqs();
538 sun4d_fixup_trap_table();
540} 539}
541 540
542void __init sun4d_init_sbi_irq(void) 541void __init sun4d_init_sbi_irq(void)
543{ 542{
544 struct sbus_bus *sbus; 543 struct device_node *dp;
545 unsigned mask; 544 int target_cpu = 0;
545
546#ifdef CONFIG_SMP
547 target_cpu = boot_cpu_id;
548#endif
546 549
547 nsbi = 0; 550 nsbi = 0;
548 for_each_sbus(sbus) 551 for_each_node_by_name(dp, "sbi")
549 nsbi++; 552 nsbi++;
550 sbus_actions = kzalloc (nsbi * 8 * 4 * sizeof(struct sbus_action), GFP_ATOMIC); 553 sbus_actions = kzalloc (nsbi * 8 * 4 * sizeof(struct sbus_action), GFP_ATOMIC);
551 if (!sbus_actions) { 554 if (!sbus_actions) {
552 prom_printf("SUN4D: Cannot allocate sbus_actions, halting.\n"); 555 prom_printf("SUN4D: Cannot allocate sbus_actions, halting.\n");
553 prom_halt(); 556 prom_halt();
554 } 557 }
555 for_each_sbus(sbus) { 558 for_each_node_by_name(dp, "sbi") {
556#ifdef CONFIG_SMP 559 int devid = of_getintprop_default(dp, "device-id", 0);
557 extern unsigned char boot_cpu_id; 560 int board = of_getintprop_default(dp, "board#", 0);
558 561 unsigned int mask;
559 set_sbi_tid(sbus->devid, boot_cpu_id << 3); 562
560 sbus_tid[sbus->board] = boot_cpu_id; 563 set_sbi_tid(devid, target_cpu << 3);
561#endif 564 sbus_tid[board] = target_cpu;
565
562 /* Get rid of pending irqs from PROM */ 566 /* Get rid of pending irqs from PROM */
563 mask = acquire_sbi(sbus->devid, 0xffffffff); 567 mask = acquire_sbi(devid, 0xffffffff);
564 if (mask) { 568 if (mask) {
565 printk ("Clearing pending IRQs %08x on SBI %d\n", mask, sbus->board); 569 printk ("Clearing pending IRQs %08x on SBI %d\n", mask, board);
566 release_sbi(sbus->devid, mask); 570 release_sbi(devid, mask);
567 } 571 }
568 } 572 }
569} 573}
@@ -572,11 +576,9 @@ void __init sun4d_init_IRQ(void)
572{ 576{
573 local_irq_disable(); 577 local_irq_disable();
574 578
575 BTFIXUPSET_CALL(sbint_to_irq, sun4d_sbint_to_irq, BTFIXUPCALL_NORM);
576 BTFIXUPSET_CALL(enable_irq, sun4d_enable_irq, BTFIXUPCALL_NORM); 579 BTFIXUPSET_CALL(enable_irq, sun4d_enable_irq, BTFIXUPCALL_NORM);
577 BTFIXUPSET_CALL(disable_irq, sun4d_disable_irq, BTFIXUPCALL_NORM); 580 BTFIXUPSET_CALL(disable_irq, sun4d_disable_irq, BTFIXUPCALL_NORM);
578 BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM); 581 BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM);
579 BTFIXUPSET_CALL(clear_profile_irq, sun4d_clear_profile_irq, BTFIXUPCALL_NORM);
580 BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM); 582 BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM);
581 sparc_init_timers = sun4d_init_timers; 583 sparc_init_timers = sun4d_init_timers;
582#ifdef CONFIG_SMP 584#ifdef CONFIG_SMP
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index 446767e8f56..ce3d45db94e 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -30,7 +30,6 @@
30#include <asm/pgalloc.h> 30#include <asm/pgalloc.h>
31#include <asm/pgtable.h> 31#include <asm/pgtable.h>
32#include <asm/oplib.h> 32#include <asm/oplib.h>
33#include <asm/sbus.h>
34#include <asm/sbi.h> 33#include <asm/sbi.h>
35#include <asm/tlbflush.h> 34#include <asm/tlbflush.h>
36#include <asm/cacheflush.h> 35#include <asm/cacheflush.h>
@@ -72,6 +71,17 @@ static void smp_setup_percpu_timer(void);
72extern void cpu_probe(void); 71extern void cpu_probe(void);
73extern void sun4d_distribute_irqs(void); 72extern void sun4d_distribute_irqs(void);
74 73
74static unsigned char cpu_leds[32];
75
76static inline void show_leds(int cpuid)
77{
78 cpuid &= 0x1e;
79 __asm__ __volatile__ ("stba %0, [%1] %2" : :
80 "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
81 "r" (ECSR_BASE(cpuid) | BB_LEDS),
82 "i" (ASI_M_CTL));
83}
84
75void __init smp4d_callin(void) 85void __init smp4d_callin(void)
76{ 86{
77 int cpuid = hard_smp4d_processor_id(); 87 int cpuid = hard_smp4d_processor_id();
diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c
index 94e02de960e..f10317179ee 100644
--- a/arch/sparc/kernel/sun4m_irq.c
+++ b/arch/sparc/kernel/sun4m_irq.c
@@ -20,6 +20,8 @@
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
23 25
24#include <asm/ptrace.h> 26#include <asm/ptrace.h>
25#include <asm/processor.h> 27#include <asm/processor.h>
@@ -35,59 +37,27 @@
35#include <asm/smp.h> 37#include <asm/smp.h>
36#include <asm/irq.h> 38#include <asm/irq.h>
37#include <asm/io.h> 39#include <asm/io.h>
38#include <asm/sbus.h>
39#include <asm/cacheflush.h> 40#include <asm/cacheflush.h>
40 41
41#include "irq.h" 42#include "irq.h"
42 43
43/* On the sun4m, just like the timers, we have both per-cpu and master 44struct sun4m_irq_percpu {
44 * interrupt registers. 45 u32 pending;
45 */ 46 u32 clear;
46 47 u32 set;
47/* These registers are used for sending/receiving irqs from/to
48 * different cpu's.
49 */
50struct sun4m_intreg_percpu {
51 unsigned int tbt; /* Interrupts still pending for this cpu. */
52
53 /* These next two registers are WRITE-ONLY and are only
54 * "on bit" sensitive, "off bits" written have NO affect.
55 */
56 unsigned int clear; /* Clear this cpus irqs here. */
57 unsigned int set; /* Set this cpus irqs here. */
58 unsigned char space[PAGE_SIZE - 12];
59}; 48};
60 49
61/* 50struct sun4m_irq_global {
62 * djhr 51 u32 pending;
63 * Actually the clear and set fields in this struct are misleading.. 52 u32 mask;
64 * according to the SLAVIO manual (and the same applies for the SEC) 53 u32 mask_clear;
65 * the clear field clears bits in the mask which will ENABLE that IRQ 54 u32 mask_set;
66 * the set field sets bits in the mask to DISABLE the IRQ. 55 u32 interrupt_target;
67 *
68 * Also the undirected_xx address in the SLAVIO is defined as
69 * RESERVED and write only..
70 *
71 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
72 * sun4m machines, for MP the layout makes more sense.
73 */
74struct sun4m_intregs {
75 struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
76 unsigned int tbt; /* IRQ's that are still pending. */
77 unsigned int irqs; /* Master IRQ bits. */
78
79 /* Again, like the above, two these registers are WRITE-ONLY. */
80 unsigned int clear; /* Clear master IRQ's by setting bits here. */
81 unsigned int set; /* Set master IRQ's by setting bits here. */
82
83 /* This register is both READ and WRITE. */
84 unsigned int undirected_target; /* Which cpu gets undirected irqs. */
85}; 56};
86 57
87static unsigned long dummy; 58/* Code in entry.S needs to get at these register mappings. */
88 59struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
89struct sun4m_intregs *sun4m_interrupts; 60struct sun4m_irq_global __iomem *sun4m_irq_global;
90unsigned long *irq_rcvreg = &dummy;
91 61
92/* Dave Redman (djhr@tadpole.co.uk) 62/* Dave Redman (djhr@tadpole.co.uk)
93 * The sun4m interrupt registers. 63 * The sun4m interrupt registers.
@@ -101,8 +71,9 @@ unsigned long *irq_rcvreg = &dummy;
101 71
102#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ 72#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
103#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ 73#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
104#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */ 74#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
105#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */ 75#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
76#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
106#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */ 77#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
107#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */ 78#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
108#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */ 79#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
@@ -113,75 +84,126 @@ unsigned long *irq_rcvreg = &dummy;
113#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */ 84#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
114#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */ 85#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
115#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */ 86#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
87#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
88
89#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
90 SUN4M_INT_M2S_WRITE_ERR | \
91 SUN4M_INT_ECC_ERR | \
92 SUN4M_INT_VME_ERR)
116 93
117#define SUN4M_INT_SBUS(x) (1 << (x+7)) 94#define SUN4M_INT_SBUS(x) (1 << (x+7))
118#define SUN4M_INT_VME(x) (1 << (x)) 95#define SUN4M_INT_VME(x) (1 << (x))
119 96
120/* These tables only apply for interrupts greater than 15.. 97/* Interrupt levels used by OBP */
121 * 98#define OBP_INT_LEVEL_SOFT 0x10
122 * any intr value below 0x10 is considered to be a soft-int 99#define OBP_INT_LEVEL_ONBOARD 0x20
123 * this may be useful or it may not.. but that's how I've done it. 100#define OBP_INT_LEVEL_SBUS 0x30
124 * and it won't clash with what OBP is telling us about devices. 101#define OBP_INT_LEVEL_VME 0x40
102
103/* Interrupt level assignment on sun4m:
104 *
105 * level source
106 * ------------------------------------------------------------
107 * 1 softint-1
108 * 2 softint-2, VME/SBUS level 1
109 * 3 softint-3, VME/SBUS level 2
110 * 4 softint-4, onboard SCSI
111 * 5 softint-5, VME/SBUS level 3
112 * 6 softint-6, onboard ETHERNET
113 * 7 softint-7, VME/SBUS level 4
114 * 8 softint-8, onboard VIDEO
115 * 9 softint-9, VME/SBUS level 5, Module Interrupt
116 * 10 softint-10, system counter/timer
117 * 11 softint-11, VME/SBUS level 6, Floppy
118 * 12 softint-12, Keyboard/Mouse, Serial
119 * 13 softint-13, VME/SBUS level 7, ISDN Audio
120 * 14 softint-14, per-processor counter/timer
121 * 15 softint-15, Asynchronous Errors (broadcast)
125 * 122 *
126 * take an encoded intr value and lookup if it's valid 123 * Each interrupt source is masked distinctly in the sun4m interrupt
127 * then get the mask bits that match from irq_mask 124 * registers. The PIL level alone is therefore ambiguous, since multiple
125 * interrupt sources map to a single PIL.
128 * 126 *
129 * P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee. 127 * This ambiguity is resolved in the 'intr' property for device nodes
128 * in the OF device tree. Each 'intr' property entry is composed of
129 * two 32-bit words. The first word is the IRQ priority value, which
130 * is what we're intersted in. The second word is the IRQ vector, which
131 * is unused.
132 *
133 * The low 4 bits of the IRQ priority indicate the PIL, and the upper
134 * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
135 * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
136 *
137 * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
138 * whereas a value of 0x33 is SBUS level 2. Here are some sample
139 * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
140 * Tadpole S3 GX systems.
141 *
142 * esp: 0x24 onboard ESP SCSI
143 * le: 0x26 onboard Lance ETHERNET
144 * p9100: 0x32 SBUS level 1 P9100 video
145 * bpp: 0x33 SBUS level 2 BPP parallel port device
146 * DBRI: 0x39 SBUS level 5 DBRI ISDN audio
147 * SUNW,leo: 0x39 SBUS level 5 LEO video
148 * pcmcia: 0x3b SBUS level 6 PCMCIA controller
149 * uctrl: 0x3b SBUS level 6 UCTRL device
150 * modem: 0x3d SBUS level 7 MODEM
151 * zs: 0x2c onboard keyboard/mouse/serial
152 * floppy: 0x2b onboard Floppy
153 * power: 0x22 onboard power device (XXX unknown mask bit XXX)
130 */ 154 */
131static unsigned char irq_xlate[32] = {
132 /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f */
133 0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 5, 6, 14, 0, 7,
134 0, 0, 8, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 0
135};
136 155
137static unsigned long irq_mask[] = { 156static unsigned long irq_mask[0x50] = {
138 0, /* illegal index */ 157 /* SMP */
139 SUN4M_INT_SCSI, /* 1 irq 4 */ 158 0, SUN4M_SOFT_INT(1),
140 SUN4M_INT_ETHERNET, /* 2 irq 6 */ 159 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
141 SUN4M_INT_VIDEO, /* 3 irq 8 */ 160 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
142 SUN4M_INT_REALTIME, /* 4 irq 10 */ 161 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
143 SUN4M_INT_FLOPPY, /* 5 irq 11 */ 162 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
144 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), /* 6 irq 12 */ 163 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
145 SUN4M_INT_MODULE_ERR, /* 7 irq 15 */ 164 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
146 SUN4M_INT_SBUS(0), /* 8 irq 2 */ 165 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
147 SUN4M_INT_SBUS(1), /* 9 irq 3 */ 166 /* soft */
148 SUN4M_INT_SBUS(2), /* 10 irq 5 */ 167 0, SUN4M_SOFT_INT(1),
149 SUN4M_INT_SBUS(3), /* 11 irq 7 */ 168 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
150 SUN4M_INT_SBUS(4), /* 12 irq 9 */ 169 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
151 SUN4M_INT_SBUS(5), /* 13 irq 11 */ 170 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
152 SUN4M_INT_SBUS(6) /* 14 irq 13 */ 171 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
172 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
173 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
174 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
175 /* onboard */
176 0, 0, 0, 0,
177 SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
178 SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
179 SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
180 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
181 SUN4M_INT_AUDIO, 0, SUN4M_INT_MODULE_ERR,
182 /* sbus */
183 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
184 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
185 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
186 0, SUN4M_INT_SBUS(6), 0, 0,
187 /* vme */
188 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
189 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
190 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
191 0, SUN4M_INT_VME(6), 0, 0
153}; 192};
154 193
155static int sun4m_pil_map[] = { 0, 2, 3, 5, 7, 9, 11, 13 };
156
157static unsigned int sun4m_sbint_to_irq(struct sbus_dev *sdev,
158 unsigned int sbint)
159{
160 if (sbint >= sizeof(sun4m_pil_map)) {
161 printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
162 BUG();
163 }
164 return sun4m_pil_map[sbint] | 0x30;
165}
166
167static unsigned long sun4m_get_irqmask(unsigned int irq) 194static unsigned long sun4m_get_irqmask(unsigned int irq)
168{ 195{
169 unsigned long mask; 196 unsigned long mask;
170 197
171 if (irq > 0x20) { 198 if (irq < 0x50)
172 /* OBIO/SBUS interrupts */ 199 mask = irq_mask[irq];
173 irq &= 0x1f; 200 else
174 mask = irq_mask[irq_xlate[irq]]; 201 mask = 0;
175 if (!mask) 202
176 printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq); 203 if (!mask)
177 } else { 204 printk(KERN_ERR "sun4m_get_irqmask: IRQ%d has no valid mask!\n",
178 /* Soft Interrupts will come here. 205 irq);
179 * Currently there is no way to trigger them but I'm sure 206
180 * something could be cooked up.
181 */
182 irq &= 0xf;
183 mask = SUN4M_SOFT_INT(irq);
184 }
185 return mask; 207 return mask;
186} 208}
187 209
@@ -193,9 +215,9 @@ static void sun4m_disable_irq(unsigned int irq_nr)
193 mask = sun4m_get_irqmask(irq_nr); 215 mask = sun4m_get_irqmask(irq_nr);
194 local_irq_save(flags); 216 local_irq_save(flags);
195 if (irq_nr > 15) 217 if (irq_nr > 15)
196 sun4m_interrupts->set = mask; 218 sbus_writel(mask, &sun4m_irq_global->mask_set);
197 else 219 else
198 sun4m_interrupts->cpu_intregs[cpu].set = mask; 220 sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
199 local_irq_restore(flags); 221 local_irq_restore(flags);
200} 222}
201 223
@@ -212,13 +234,13 @@ static void sun4m_enable_irq(unsigned int irq_nr)
212 mask = sun4m_get_irqmask(irq_nr); 234 mask = sun4m_get_irqmask(irq_nr);
213 local_irq_save(flags); 235 local_irq_save(flags);
214 if (irq_nr > 15) 236 if (irq_nr > 15)
215 sun4m_interrupts->clear = mask; 237 sbus_writel(mask, &sun4m_irq_global->mask_clear);
216 else 238 else
217 sun4m_interrupts->cpu_intregs[cpu].clear = mask; 239 sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
218 local_irq_restore(flags); 240 local_irq_restore(flags);
219 } else { 241 } else {
220 local_irq_save(flags); 242 local_irq_save(flags);
221 sun4m_interrupts->clear = SUN4M_INT_FLOPPY; 243 sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear);
222 local_irq_restore(flags); 244 local_irq_restore(flags);
223 } 245 }
224} 246}
@@ -236,10 +258,10 @@ static unsigned long cpu_pil_to_imask[16] = {
236/*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR, 258/*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
237/*10*/ SUN4M_INT_REALTIME, 259/*10*/ SUN4M_INT_REALTIME,
238/*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY, 260/*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
239/*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS, 261/*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
240/*13*/ SUN4M_INT_AUDIO, 262/*13*/ SUN4M_INT_SBUS(6) | SUN4M_INT_VME(6) | SUN4M_INT_AUDIO,
241/*14*/ SUN4M_INT_E14, 263/*14*/ SUN4M_INT_E14,
242/*15*/ 0x00000000 264/*15*/ SUN4M_INT_ERROR
243}; 265};
244 266
245/* We assume the caller has disabled local interrupts when these are called, 267/* We assume the caller has disabled local interrupts when these are called,
@@ -247,126 +269,141 @@ static unsigned long cpu_pil_to_imask[16] = {
247 */ 269 */
248static void sun4m_disable_pil_irq(unsigned int pil) 270static void sun4m_disable_pil_irq(unsigned int pil)
249{ 271{
250 sun4m_interrupts->set = cpu_pil_to_imask[pil]; 272 sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_set);
251} 273}
252 274
253static void sun4m_enable_pil_irq(unsigned int pil) 275static void sun4m_enable_pil_irq(unsigned int pil)
254{ 276{
255 sun4m_interrupts->clear = cpu_pil_to_imask[pil]; 277 sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_clear);
256} 278}
257 279
258#ifdef CONFIG_SMP 280#ifdef CONFIG_SMP
259static void sun4m_send_ipi(int cpu, int level) 281static void sun4m_send_ipi(int cpu, int level)
260{ 282{
261 unsigned long mask; 283 unsigned long mask = sun4m_get_irqmask(level);
262 284 sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
263 mask = sun4m_get_irqmask(level);
264 sun4m_interrupts->cpu_intregs[cpu].set = mask;
265} 285}
266 286
267static void sun4m_clear_ipi(int cpu, int level) 287static void sun4m_clear_ipi(int cpu, int level)
268{ 288{
269 unsigned long mask; 289 unsigned long mask = sun4m_get_irqmask(level);
270 290 sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
271 mask = sun4m_get_irqmask(level);
272 sun4m_interrupts->cpu_intregs[cpu].clear = mask;
273} 291}
274 292
275static void sun4m_set_udt(int cpu) 293static void sun4m_set_udt(int cpu)
276{ 294{
277 sun4m_interrupts->undirected_target = cpu; 295 sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
278} 296}
279#endif 297#endif
280 298
281#define OBIO_INTR 0x20 299struct sun4m_timer_percpu {
282#define TIMER_IRQ (OBIO_INTR | 10) 300 u32 l14_limit;
283#define PROFILE_IRQ (OBIO_INTR | 14) 301 u32 l14_count;
302 u32 l14_limit_noclear;
303 u32 user_timer_start_stop;
304};
305
306static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
307
308struct sun4m_timer_global {
309 u32 l10_limit;
310 u32 l10_count;
311 u32 l10_limit_noclear;
312 u32 reserved;
313 u32 timer_config;
314};
315
316static struct sun4m_timer_global __iomem *timers_global;
317
318#define TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
284 319
285static struct sun4m_timer_regs *sun4m_timers;
286unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10); 320unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
287 321
288static void sun4m_clear_clock_irq(void) 322static void sun4m_clear_clock_irq(void)
289{ 323{
290 volatile unsigned int clear_intr; 324 sbus_readl(&timers_global->l10_limit);
291 clear_intr = sun4m_timers->l10_timer_limit;
292} 325}
293 326
294static void sun4m_clear_profile_irq(int cpu) 327void sun4m_nmi(struct pt_regs *regs)
295{ 328{
296 volatile unsigned int clear; 329 unsigned long afsr, afar, si;
297 330
298 clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit; 331 printk(KERN_ERR "Aieee: sun4m NMI received!\n");
332 /* XXX HyperSparc hack XXX */
333 __asm__ __volatile__("mov 0x500, %%g1\n\t"
334 "lda [%%g1] 0x4, %0\n\t"
335 "mov 0x600, %%g1\n\t"
336 "lda [%%g1] 0x4, %1\n\t" :
337 "=r" (afsr), "=r" (afar));
338 printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
339 si = sbus_readl(&sun4m_irq_global->pending);
340 printk(KERN_ERR "si=%08lx\n", si);
341 if (si & SUN4M_INT_MODULE_ERR)
342 printk(KERN_ERR "Module async error\n");
343 if (si & SUN4M_INT_M2S_WRITE_ERR)
344 printk(KERN_ERR "MBus/SBus async error\n");
345 if (si & SUN4M_INT_ECC_ERR)
346 printk(KERN_ERR "ECC memory error\n");
347 if (si & SUN4M_INT_VME_ERR)
348 printk(KERN_ERR "VME async error\n");
349 printk(KERN_ERR "you lose buddy boy...\n");
350 show_regs(regs);
351 prom_halt();
352}
353
354/* Exported for sun4m_smp.c */
355void sun4m_clear_profile_irq(int cpu)
356{
357 sbus_readl(&timers_percpu[cpu]->l14_limit);
299} 358}
300 359
301static void sun4m_load_profile_irq(int cpu, unsigned int limit) 360static void sun4m_load_profile_irq(int cpu, unsigned int limit)
302{ 361{
303 sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit; 362 sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
304} 363}
305 364
306static void __init sun4m_init_timers(irq_handler_t counter_fn) 365static void __init sun4m_init_timers(irq_handler_t counter_fn)
307{ 366{
308 int reg_count, irq, cpu; 367 struct device_node *dp = of_find_node_by_name(NULL, "counter");
309 struct linux_prom_registers cnt_regs[PROMREG_MAX]; 368 int i, err, len, num_cpu_timers;
310 int obio_node, cnt_node; 369 const u32 *addr;
311 struct resource r; 370
312 371 if (!dp) {
313 cnt_node = 0; 372 printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
314 if((obio_node = 373 return;
315 prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 ||
316 (obio_node = prom_getchild (obio_node)) == 0 ||
317 (cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
318 prom_printf("Cannot find /obio/counter node\n");
319 prom_halt();
320 } 374 }
321 reg_count = prom_getproperty(cnt_node, "reg", 375
322 (void *) cnt_regs, sizeof(cnt_regs)); 376 addr = of_get_property(dp, "address", &len);
323 reg_count = (reg_count/sizeof(struct linux_prom_registers)); 377 if (!addr) {
324 378 printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
325 /* Apply the obio ranges to the timer registers. */ 379 return;
326 prom_apply_obio_ranges(cnt_regs, reg_count);
327
328 cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
329 cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
330 cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
331 for(obio_node = 1; obio_node < 4; obio_node++) {
332 cnt_regs[obio_node].phys_addr =
333 cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
334 cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
335 cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
336 } 380 }
337 381
338 memset((char*)&r, 0, sizeof(struct resource)); 382 num_cpu_timers = (len / sizeof(u32)) - 1;
339 /* Map the per-cpu Counter registers. */ 383 for (i = 0; i < num_cpu_timers; i++) {
340 r.flags = cnt_regs[0].which_io; 384 timers_percpu[i] = (void __iomem *)
341 r.start = cnt_regs[0].phys_addr; 385 (unsigned long) addr[i];
342 sun4m_timers = (struct sun4m_timer_regs *) sbus_ioremap(&r, 0,
343 PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
344 /* Map the system Counter register. */
345 /* XXX Here we expect consequent calls to yeld adjusent maps. */
346 r.flags = cnt_regs[4].which_io;
347 r.start = cnt_regs[4].phys_addr;
348 sbus_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");
349
350 sun4m_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
351 master_l10_counter = &sun4m_timers->l10_cur_count;
352 master_l10_limit = &sun4m_timers->l10_timer_limit;
353
354 irq = request_irq(TIMER_IRQ,
355 counter_fn,
356 (IRQF_DISABLED | SA_STATIC_ALLOC),
357 "timer", NULL);
358 if (irq) {
359 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
360 prom_halt();
361 } 386 }
362 387 timers_global = (void __iomem *)
363 if (!cpu_find_by_instance(1, NULL, NULL)) { 388 (unsigned long) addr[num_cpu_timers];
364 for(cpu = 0; cpu < 4; cpu++) 389
365 sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0; 390 sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
366 sun4m_interrupts->set = SUN4M_INT_E14; 391
367 } else { 392 master_l10_counter = &timers_global->l10_count;
368 sun4m_timers->cpu_timers[0].l14_timer_limit = 0; 393
394 err = request_irq(TIMER_IRQ, counter_fn,
395 (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
396 if (err) {
397 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
398 err);
399 return;
369 } 400 }
401
402 for (i = 0; i < num_cpu_timers; i++)
403 sbus_writel(0, &timers_percpu[i]->l14_limit);
404 if (num_cpu_timers == 4)
405 sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
406
370#ifdef CONFIG_SMP 407#ifdef CONFIG_SMP
371 { 408 {
372 unsigned long flags; 409 unsigned long flags;
@@ -390,70 +427,43 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
390 427
391void __init sun4m_init_IRQ(void) 428void __init sun4m_init_IRQ(void)
392{ 429{
393 int ie_node,i; 430 struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
394 struct linux_prom_registers int_regs[PROMREG_MAX]; 431 int len, i, mid, num_cpu_iregs;
395 int num_regs; 432 const u32 *addr;
396 struct resource r; 433
397 int mid; 434 if (!dp) {
398 435 printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
399 local_irq_disable(); 436 return;
400 if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 ||
401 (ie_node = prom_getchild (ie_node)) == 0 ||
402 (ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
403 prom_printf("Cannot find /obio/interrupt node\n");
404 prom_halt();
405 } 437 }
406 num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs, 438
407 sizeof(int_regs)); 439 addr = of_get_property(dp, "address", &len);
408 num_regs = (num_regs/sizeof(struct linux_prom_registers)); 440 if (!addr) {
409 441 printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
410 /* Apply the obio ranges to these registers. */ 442 return;
411 prom_apply_obio_ranges(int_regs, num_regs);
412
413 int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
414 int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
415 int_regs[4].which_io = int_regs[num_regs-1].which_io;
416 for(ie_node = 1; ie_node < 4; ie_node++) {
417 int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
418 int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
419 int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
420 } 443 }
421 444
422 memset((char *)&r, 0, sizeof(struct resource)); 445 num_cpu_iregs = (len / sizeof(u32)) - 1;
423 /* Map the interrupt registers for all possible cpus. */ 446 for (i = 0; i < num_cpu_iregs; i++) {
424 r.flags = int_regs[0].which_io; 447 sun4m_irq_percpu[i] = (void __iomem *)
425 r.start = int_regs[0].phys_addr; 448 (unsigned long) addr[i];
426 sun4m_interrupts = (struct sun4m_intregs *) sbus_ioremap(&r, 0, 449 }
427 PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu"); 450 sun4m_irq_global = (void __iomem *)
451 (unsigned long) addr[num_cpu_iregs];
428 452
429 /* Map the system interrupt control registers. */ 453 local_irq_disable();
430 r.flags = int_regs[4].which_io;
431 r.start = int_regs[4].phys_addr;
432 sbus_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");
433 454
434 sun4m_interrupts->set = ~SUN4M_INT_MASKALL; 455 sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
435 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++) 456 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
436 sun4m_interrupts->cpu_intregs[mid].clear = ~0x17fff; 457 sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
437 458
438 if (!cpu_find_by_instance(1, NULL, NULL)) { 459 if (num_cpu_iregs == 4)
439 /* system wide interrupts go to cpu 0, this should always 460 sbus_writel(0, &sun4m_irq_global->interrupt_target);
440 * be safe because it is guaranteed to be fitted or OBP doesn't 461
441 * come up
442 *
443 * Not sure, but writing here on SLAVIO systems may puke
444 * so I don't do it unless there is more than 1 cpu.
445 */
446 irq_rcvreg = (unsigned long *)
447 &sun4m_interrupts->undirected_target;
448 sun4m_interrupts->undirected_target = 0;
449 }
450 BTFIXUPSET_CALL(sbint_to_irq, sun4m_sbint_to_irq, BTFIXUPCALL_NORM);
451 BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM); 462 BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
452 BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM); 463 BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
453 BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM); 464 BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
454 BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM); 465 BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
455 BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM); 466 BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
456 BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
457 BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM); 467 BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
458 sparc_init_timers = sun4m_init_timers; 468 sparc_init_timers = sun4m_init_timers;
459#ifdef CONFIG_SMP 469#ifdef CONFIG_SMP
@@ -461,5 +471,6 @@ void __init sun4m_init_IRQ(void)
461 BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM); 471 BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
462 BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM); 472 BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
463#endif 473#endif
474
464 /* Cannot enable interrupts until OBP ticker is disabled. */ 475 /* Cannot enable interrupts until OBP ticker is disabled. */
465} 476}
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
index 9964890dc1d..0c564ba9e70 100644
--- a/arch/sparc/kernel/sun4m_smp.c
+++ b/arch/sparc/kernel/sun4m_smp.c
@@ -315,6 +315,8 @@ void smp4m_cross_call_irq(void)
315 ccall_info.processors_out[i] = 1; 315 ccall_info.processors_out[i] = 1;
316} 316}
317 317
318extern void sun4m_clear_profile_irq(int cpu);
319
318void smp4m_percpu_timer_interrupt(struct pt_regs *regs) 320void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
319{ 321{
320 struct pt_regs *old_regs; 322 struct pt_regs *old_regs;
@@ -322,7 +324,7 @@ void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
322 324
323 old_regs = set_irq_regs(regs); 325 old_regs = set_irq_regs(regs);
324 326
325 clear_profile_irq(cpu); 327 sun4m_clear_profile_irq(cpu);
326 328
327 profile_tick(CPU_PROFILING); 329 profile_tick(CPU_PROFILING);
328 330
diff --git a/arch/sparc/kernel/sun4setup.c b/arch/sparc/kernel/sun4setup.c
deleted file mode 100644
index 229a52f55f1..00000000000
--- a/arch/sparc/kernel/sun4setup.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/* sun4setup.c: Setup the hardware address of various items in the sun4
2 * architecture. Called from idprom_init
3 *
4 * Copyright (C) 1998 Chris G. Davis (cdavis@cois.on.ca)
5 */
6
7#include <asm/page.h>
8#include <asm/oplib.h>
9#include <asm/idprom.h>
10#include <asm/sun4paddr.h>
11#include <asm/machines.h>
12
13int sun4_memreg_physaddr;
14int sun4_ie_physaddr;
15int sun4_clock_physaddr;
16int sun4_timer_physaddr;
17int sun4_eth_physaddr;
18int sun4_si_physaddr;
19int sun4_bwtwo_physaddr;
20int sun4_zs0_physaddr;
21int sun4_zs1_physaddr;
22int sun4_dma_physaddr;
23int sun4_esp_physaddr;
24int sun4_ie_physaddr;
25
26void __init sun4setup(void)
27{
28 printk("Sun4 Hardware Setup v1.0 18/May/98 Chris Davis (cdavis@cois.on.ca). ");
29 /*
30 setup standard sun4 info
31 */
32 sun4_ie_physaddr=SUN4_IE_PHYSADDR;
33
34 /*
35 setup model specific info
36 */
37 switch(idprom->id_machtype) {
38 case (SM_SUN4 | SM_4_260 ):
39 printk("Setup for a SUN4/260\n");
40 sun4_memreg_physaddr=SUN4_200_MEMREG_PHYSADDR;
41 sun4_clock_physaddr=SUN4_200_CLOCK_PHYSADDR;
42 sun4_timer_physaddr=SUN4_UNUSED_PHYSADDR;
43 sun4_eth_physaddr=SUN4_200_ETH_PHYSADDR;
44 sun4_si_physaddr=SUN4_200_SI_PHYSADDR;
45 sun4_bwtwo_physaddr=SUN4_200_BWTWO_PHYSADDR;
46 sun4_dma_physaddr=SUN4_UNUSED_PHYSADDR;
47 sun4_esp_physaddr=SUN4_UNUSED_PHYSADDR;
48 break;
49 case (SM_SUN4 | SM_4_330 ):
50 printk("Setup for a SUN4/330\n");
51 sun4_memreg_physaddr=SUN4_300_MEMREG_PHYSADDR;
52 sun4_clock_physaddr=SUN4_300_CLOCK_PHYSADDR;
53 sun4_timer_physaddr=SUN4_300_TIMER_PHYSADDR;
54 sun4_eth_physaddr=SUN4_300_ETH_PHYSADDR;
55 sun4_si_physaddr=SUN4_UNUSED_PHYSADDR;
56 sun4_bwtwo_physaddr=SUN4_300_BWTWO_PHYSADDR;
57 sun4_dma_physaddr=SUN4_300_DMA_PHYSADDR;
58 sun4_esp_physaddr=SUN4_300_ESP_PHYSADDR;
59 break;
60 case (SM_SUN4 | SM_4_470 ):
61 printk("Setup for a SUN4/470\n");
62 sun4_memreg_physaddr=SUN4_400_MEMREG_PHYSADDR;
63 sun4_clock_physaddr=SUN4_400_CLOCK_PHYSADDR;
64 sun4_timer_physaddr=SUN4_400_TIMER_PHYSADDR;
65 sun4_eth_physaddr=SUN4_400_ETH_PHYSADDR;
66 sun4_si_physaddr=SUN4_UNUSED_PHYSADDR;
67 sun4_bwtwo_physaddr=SUN4_400_BWTWO_PHYSADDR;
68 sun4_dma_physaddr=SUN4_400_DMA_PHYSADDR;
69 sun4_esp_physaddr=SUN4_400_ESP_PHYSADDR;
70 break;
71 default:
72 ;
73 }
74}
75
diff --git a/arch/sparc/kernel/sys_sparc.c b/arch/sparc/kernel/sys_sparc.c
index 4d73421559c..03035c852a4 100644
--- a/arch/sparc/kernel/sys_sparc.c
+++ b/arch/sparc/kernel/sys_sparc.c
@@ -53,7 +53,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi
53 /* See asm-sparc/uaccess.h */ 53 /* See asm-sparc/uaccess.h */
54 if (len > TASK_SIZE - PAGE_SIZE) 54 if (len > TASK_SIZE - PAGE_SIZE)
55 return -ENOMEM; 55 return -ENOMEM;
56 if (ARCH_SUN4C_SUN4 && len > 0x20000000) 56 if (ARCH_SUN4C && len > 0x20000000)
57 return -ENOMEM; 57 return -ENOMEM;
58 if (!addr) 58 if (!addr)
59 addr = TASK_UNMAPPED_BASE; 59 addr = TASK_UNMAPPED_BASE;
@@ -65,7 +65,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi
65 65
66 for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) { 66 for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) {
67 /* At this point: (!vmm || addr < vmm->vm_end). */ 67 /* At this point: (!vmm || addr < vmm->vm_end). */
68 if (ARCH_SUN4C_SUN4 && addr < 0xe0000000 && 0x20000000 - len < addr) { 68 if (ARCH_SUN4C && addr < 0xe0000000 && 0x20000000 - len < addr) {
69 addr = PAGE_OFFSET; 69 addr = PAGE_OFFSET;
70 vmm = find_vma(current->mm, PAGE_OFFSET); 70 vmm = find_vma(current->mm, PAGE_OFFSET);
71 } 71 }
@@ -81,7 +81,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi
81 81
82asmlinkage unsigned long sparc_brk(unsigned long brk) 82asmlinkage unsigned long sparc_brk(unsigned long brk)
83{ 83{
84 if(ARCH_SUN4C_SUN4) { 84 if(ARCH_SUN4C) {
85 if ((brk & 0xe0000000) != (current->mm->brk & 0xe0000000)) 85 if ((brk & 0xe0000000) != (current->mm->brk & 0xe0000000))
86 return current->mm->brk; 86 return current->mm->brk;
87 } 87 }
@@ -221,7 +221,7 @@ out:
221 221
222int sparc_mmap_check(unsigned long addr, unsigned long len) 222int sparc_mmap_check(unsigned long addr, unsigned long len)
223{ 223{
224 if (ARCH_SUN4C_SUN4 && 224 if (ARCH_SUN4C &&
225 (len > 0x20000000 || 225 (len > 0x20000000 ||
226 (addr < 0xe0000000 && addr + len > 0x20000000))) 226 (addr < 0xe0000000 && addr + len > 0x20000000)))
227 return -EINVAL; 227 return -EINVAL;
diff --git a/arch/sparc/kernel/tick14.c b/arch/sparc/kernel/tick14.c
index 707bfda8657..138bbf5f872 100644
--- a/arch/sparc/kernel/tick14.c
+++ b/arch/sparc/kernel/tick14.c
@@ -1,31 +1,12 @@
1/* tick14.c 1/* tick14.c
2 * linux/arch/sparc/kernel/tick14.c
3 * 2 *
4 * Copyright (C) 1996 David Redman (djhr@tadpole.co.uk) 3 * Copyright (C) 1996 David Redman (djhr@tadpole.co.uk)
5 * 4 *
6 * This file handles the Sparc specific level14 ticker 5 * This file handles the Sparc specific level14 ticker
7 * This is really useful for profiling OBP uses it for keyboard 6 * This is really useful for profiling OBP uses it for keyboard
8 * aborts and other stuff. 7 * aborts and other stuff.
9 *
10 *
11 */ 8 */
12#include <linux/errno.h>
13#include <linux/sched.h>
14#include <linux/kernel.h> 9#include <linux/kernel.h>
15#include <linux/param.h>
16#include <linux/string.h>
17#include <linux/mm.h>
18#include <linux/timex.h>
19#include <linux/interrupt.h>
20
21#include <asm/oplib.h>
22#include <asm/timer.h>
23#include <asm/mostek.h>
24#include <asm/system.h>
25#include <asm/irq.h>
26#include <asm/io.h>
27
28#include "irq.h"
29 10
30extern unsigned long lvl14_save[5]; 11extern unsigned long lvl14_save[5];
31static unsigned long *linux_lvl14 = NULL; 12static unsigned long *linux_lvl14 = NULL;
@@ -56,31 +37,3 @@ void install_obp_ticker(void)
56 linux_lvl14[2] = obp_lvl14[2]; 37 linux_lvl14[2] = obp_lvl14[2];
57 linux_lvl14[3] = obp_lvl14[3]; 38 linux_lvl14[3] = obp_lvl14[3];
58} 39}
59
60void claim_ticker14(irq_handler_t handler,
61 int irq_nr, unsigned int timeout )
62{
63 int cpu = smp_processor_id();
64
65 /* first we copy the obp handler instructions
66 */
67 __disable_irq(irq_nr);
68 if (!handler)
69 return;
70
71 linux_lvl14 = (unsigned long *)lvl14_save[4];
72 obp_lvl14[0] = linux_lvl14[0];
73 obp_lvl14[1] = linux_lvl14[1];
74 obp_lvl14[2] = linux_lvl14[2];
75 obp_lvl14[3] = linux_lvl14[3];
76
77 if (!request_irq(irq_nr,
78 handler,
79 (IRQF_DISABLED | SA_STATIC_ALLOC),
80 "counter14",
81 NULL)) {
82 install_linux_ticker();
83 load_profile_irq(cpu, timeout);
84 __enable_irq(irq_nr);
85 }
86}
diff --git a/arch/sparc/kernel/time.c b/arch/sparc/kernel/time.c
index 0762f5db192..62c1d94cb43 100644
--- a/arch/sparc/kernel/time.c
+++ b/arch/sparc/kernel/time.c
@@ -23,22 +23,24 @@
23#include <linux/mm.h> 23#include <linux/mm.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/time.h> 25#include <linux/time.h>
26#include <linux/rtc.h>
27#include <linux/rtc/m48t59.h>
26#include <linux/timex.h> 28#include <linux/timex.h>
27#include <linux/init.h> 29#include <linux/init.h>
28#include <linux/pci.h> 30#include <linux/pci.h>
29#include <linux/ioport.h> 31#include <linux/ioport.h>
30#include <linux/profile.h> 32#include <linux/profile.h>
33#include <linux/of.h>
31#include <linux/of_device.h> 34#include <linux/of_device.h>
35#include <linux/platform_device.h>
32 36
33#include <asm/oplib.h> 37#include <asm/oplib.h>
34#include <asm/timer.h> 38#include <asm/timer.h>
35#include <asm/mostek.h>
36#include <asm/system.h> 39#include <asm/system.h>
37#include <asm/irq.h> 40#include <asm/irq.h>
38#include <asm/io.h> 41#include <asm/io.h>
39#include <asm/idprom.h> 42#include <asm/idprom.h>
40#include <asm/machines.h> 43#include <asm/machines.h>
41#include <asm/sun4paddr.h>
42#include <asm/page.h> 44#include <asm/page.h>
43#include <asm/pcic.h> 45#include <asm/pcic.h>
44#include <asm/irq_regs.h> 46#include <asm/irq_regs.h>
@@ -46,34 +48,9 @@
46#include "irq.h" 48#include "irq.h"
47 49
48DEFINE_SPINLOCK(rtc_lock); 50DEFINE_SPINLOCK(rtc_lock);
49static enum sparc_clock_type sp_clock_typ;
50DEFINE_SPINLOCK(mostek_lock);
51void __iomem *mstk48t02_regs = NULL;
52static struct mostek48t08 __iomem *mstk48t08_regs = NULL;
53static int set_rtc_mmss(unsigned long); 51static int set_rtc_mmss(unsigned long);
54static int sbus_do_settimeofday(struct timespec *tv); 52static int sbus_do_settimeofday(struct timespec *tv);
55 53
56#ifdef CONFIG_SUN4
57struct intersil *intersil_clock;
58#define intersil_cmd(intersil_reg, intsil_cmd) intersil_reg->int_cmd_reg = \
59 (intsil_cmd)
60
61#define intersil_intr(intersil_reg, intsil_cmd) intersil_reg->int_intr_reg = \
62 (intsil_cmd)
63
64#define intersil_start(intersil_reg) intersil_cmd(intersil_reg, \
65 ( INTERSIL_START | INTERSIL_32K | INTERSIL_NORMAL | INTERSIL_24H |\
66 INTERSIL_INTR_ENABLE))
67
68#define intersil_stop(intersil_reg) intersil_cmd(intersil_reg, \
69 ( INTERSIL_STOP | INTERSIL_32K | INTERSIL_NORMAL | INTERSIL_24H |\
70 INTERSIL_INTR_ENABLE))
71
72#define intersil_read_intr(intersil_reg, towhere) towhere = \
73 intersil_reg->int_intr_reg
74
75#endif
76
77unsigned long profile_pc(struct pt_regs *regs) 54unsigned long profile_pc(struct pt_regs *regs)
78{ 55{
79 extern char __copy_user_begin[], __copy_user_end[]; 56 extern char __copy_user_begin[], __copy_user_end[];
@@ -96,7 +73,6 @@ unsigned long profile_pc(struct pt_regs *regs)
96EXPORT_SYMBOL(profile_pc); 73EXPORT_SYMBOL(profile_pc);
97 74
98__volatile__ unsigned int *master_l10_counter; 75__volatile__ unsigned int *master_l10_counter;
99__volatile__ unsigned int *master_l10_limit;
100 76
101/* 77/*
102 * timer_interrupt() needs to keep up the real-time clock, 78 * timer_interrupt() needs to keep up the real-time clock,
@@ -116,15 +92,7 @@ static irqreturn_t timer_interrupt(int dummy, void *dev_id)
116 92
117 /* Protect counter clear so that do_gettimeoffset works */ 93 /* Protect counter clear so that do_gettimeoffset works */
118 write_seqlock(&xtime_lock); 94 write_seqlock(&xtime_lock);
119#ifdef CONFIG_SUN4 95
120 if((idprom->id_machtype == (SM_SUN4 | SM_4_260)) ||
121 (idprom->id_machtype == (SM_SUN4 | SM_4_110))) {
122 int temp;
123 intersil_read_intr(intersil_clock, temp);
124 /* re-enable the irq */
125 enable_pil_irq(10);
126 }
127#endif
128 clear_clock_irq(); 96 clear_clock_irq();
129 97
130 do_timer(1); 98 do_timer(1);
@@ -147,157 +115,56 @@ static irqreturn_t timer_interrupt(int dummy, void *dev_id)
147 return IRQ_HANDLED; 115 return IRQ_HANDLED;
148} 116}
149 117
150/* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */ 118static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
151static void __devinit kick_start_clock(void)
152{ 119{
153 struct mostek48t02 *regs = (struct mostek48t02 *)mstk48t02_regs; 120 struct platform_device *pdev = to_platform_device(dev);
154 unsigned char sec; 121 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
155 int i, count; 122 void __iomem *regs = pdata->ioaddr;
156 123 unsigned char val = readb(regs + ofs);
157 prom_printf("CLOCK: Clock was stopped. Kick start "); 124
158 125 /* the year 0 is 1968 */
159 spin_lock_irq(&mostek_lock); 126 if (ofs == pdata->offset + M48T59_YEAR) {
160 127 val += 0x68;
161 /* Turn on the kick start bit to start the oscillator. */ 128 if ((val & 0xf) > 9)
162 regs->creg |= MSTK_CREG_WRITE; 129 val += 6;
163 regs->sec &= ~MSTK_STOP;
164 regs->hour |= MSTK_KICK_START;
165 regs->creg &= ~MSTK_CREG_WRITE;
166
167 spin_unlock_irq(&mostek_lock);
168
169 /* Delay to allow the clock oscillator to start. */
170 sec = MSTK_REG_SEC(regs);
171 for (i = 0; i < 3; i++) {
172 while (sec == MSTK_REG_SEC(regs))
173 for (count = 0; count < 100000; count++)
174 /* nothing */ ;
175 prom_printf(".");
176 sec = regs->sec;
177 }
178 prom_printf("\n");
179
180 spin_lock_irq(&mostek_lock);
181
182 /* Turn off kick start and set a "valid" time and date. */
183 regs->creg |= MSTK_CREG_WRITE;
184 regs->hour &= ~MSTK_KICK_START;
185 MSTK_SET_REG_SEC(regs,0);
186 MSTK_SET_REG_MIN(regs,0);
187 MSTK_SET_REG_HOUR(regs,0);
188 MSTK_SET_REG_DOW(regs,5);
189 MSTK_SET_REG_DOM(regs,1);
190 MSTK_SET_REG_MONTH(regs,8);
191 MSTK_SET_REG_YEAR(regs,1996 - MSTK_YEAR_ZERO);
192 regs->creg &= ~MSTK_CREG_WRITE;
193
194 spin_unlock_irq(&mostek_lock);
195
196 /* Ensure the kick start bit is off. If it isn't, turn it off. */
197 while (regs->hour & MSTK_KICK_START) {
198 prom_printf("CLOCK: Kick start still on!\n");
199
200 spin_lock_irq(&mostek_lock);
201 regs->creg |= MSTK_CREG_WRITE;
202 regs->hour &= ~MSTK_KICK_START;
203 regs->creg &= ~MSTK_CREG_WRITE;
204 spin_unlock_irq(&mostek_lock);
205 } 130 }
206 131 return val;
207 prom_printf("CLOCK: Kick start procedure successful.\n");
208}
209
210/* Return nonzero if the clock chip battery is low. */
211static inline int has_low_battery(void)
212{
213 struct mostek48t02 *regs = (struct mostek48t02 *)mstk48t02_regs;
214 unsigned char data1, data2;
215
216 spin_lock_irq(&mostek_lock);
217 data1 = regs->eeprom[0]; /* Read some data. */
218 regs->eeprom[0] = ~data1; /* Write back the complement. */
219 data2 = regs->eeprom[0]; /* Read back the complement. */
220 regs->eeprom[0] = data1; /* Restore the original value. */
221 spin_unlock_irq(&mostek_lock);
222
223 return (data1 == data2); /* Was the write blocked? */
224} 132}
225 133
226static void __devinit mostek_set_system_time(void) 134static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
227{ 135{
228 unsigned int year, mon, day, hour, min, sec; 136 struct platform_device *pdev = to_platform_device(dev);
229 struct mostek48t02 *mregs; 137 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
230 138 void __iomem *regs = pdata->ioaddr;
231 mregs = (struct mostek48t02 *)mstk48t02_regs; 139
232 if(!mregs) { 140 if (ofs == pdata->offset + M48T59_YEAR) {
233 prom_printf("Something wrong, clock regs not mapped yet.\n"); 141 if (val < 0x68)
234 prom_halt(); 142 val += 0x32;
235 } 143 else
236 spin_lock_irq(&mostek_lock); 144 val -= 0x68;
237 mregs->creg |= MSTK_CREG_READ; 145 if ((val & 0xf) > 9)
238 sec = MSTK_REG_SEC(mregs); 146 val += 6;
239 min = MSTK_REG_MIN(mregs); 147 if ((val & 0xf0) > 0x9A)
240 hour = MSTK_REG_HOUR(mregs); 148 val += 0x60;
241 day = MSTK_REG_DOM(mregs); 149 }
242 mon = MSTK_REG_MONTH(mregs); 150 writeb(val, regs + ofs);
243 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
244 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
245 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
246 set_normalized_timespec(&wall_to_monotonic,
247 -xtime.tv_sec, -xtime.tv_nsec);
248 mregs->creg &= ~MSTK_CREG_READ;
249 spin_unlock_irq(&mostek_lock);
250} 151}
251 152
252/* Probe for the real time clock chip on Sun4 */ 153static struct m48t59_plat_data m48t59_data = {
253static inline void sun4_clock_probe(void) 154 .read_byte = mostek_read_byte,
254{ 155 .write_byte = mostek_write_byte,
255#ifdef CONFIG_SUN4 156};
256 int temp;
257 struct resource r;
258
259 memset(&r, 0, sizeof(r));
260 if( idprom->id_machtype == (SM_SUN4 | SM_4_330) ) {
261 sp_clock_typ = MSTK48T02;
262 r.start = sun4_clock_physaddr;
263 mstk48t02_regs = sbus_ioremap(&r, 0,
264 sizeof(struct mostek48t02), NULL);
265 mstk48t08_regs = NULL; /* To catch weirdness */
266 intersil_clock = NULL; /* just in case */
267
268 /* Kick start the clock if it is completely stopped. */
269 if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
270 kick_start_clock();
271 } else if( idprom->id_machtype == (SM_SUN4 | SM_4_260)) {
272 /* intersil setup code */
273 printk("Clock: INTERSIL at %8x ",sun4_clock_physaddr);
274 sp_clock_typ = INTERSIL;
275 r.start = sun4_clock_physaddr;
276 intersil_clock = (struct intersil *)
277 sbus_ioremap(&r, 0, sizeof(*intersil_clock), "intersil");
278 mstk48t02_regs = 0; /* just be sure */
279 mstk48t08_regs = NULL; /* ditto */
280 /* initialise the clock */
281
282 intersil_intr(intersil_clock,INTERSIL_INT_100HZ);
283
284 intersil_start(intersil_clock);
285
286 intersil_read_intr(intersil_clock, temp);
287 while (!(temp & 0x80))
288 intersil_read_intr(intersil_clock, temp);
289
290 intersil_read_intr(intersil_clock, temp);
291 while (!(temp & 0x80))
292 intersil_read_intr(intersil_clock, temp);
293
294 intersil_stop(intersil_clock);
295 157
296 } 158/* resource is set at runtime */
297#endif 159static struct platform_device m48t59_rtc = {
298} 160 .name = "rtc-m48t59",
161 .id = 0,
162 .num_resources = 1,
163 .dev = {
164 .platform_data = &m48t59_data,
165 },
166};
299 167
300#ifndef CONFIG_SUN4
301static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match) 168static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match)
302{ 169{
303 struct device_node *dp = op->node; 170 struct device_node *dp = op->node;
@@ -306,38 +173,26 @@ static int __devinit clock_probe(struct of_device *op, const struct of_device_id
306 if (!model) 173 if (!model)
307 return -ENODEV; 174 return -ENODEV;
308 175
176 m48t59_rtc.resource = &op->resource[0];
309 if (!strcmp(model, "mk48t02")) { 177 if (!strcmp(model, "mk48t02")) {
310 sp_clock_typ = MSTK48T02;
311
312 /* Map the clock register io area read-only */ 178 /* Map the clock register io area read-only */
313 mstk48t02_regs = of_ioremap(&op->resource[0], 0, 179 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
314 sizeof(struct mostek48t02), 180 2048, "rtc-m48t59");
315 "mk48t02"); 181 m48t59_data.type = M48T59RTC_TYPE_M48T02;
316 mstk48t08_regs = NULL; /* To catch weirdness */
317 } else if (!strcmp(model, "mk48t08")) { 182 } else if (!strcmp(model, "mk48t08")) {
318 sp_clock_typ = MSTK48T08; 183 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
319 mstk48t08_regs = of_ioremap(&op->resource[0], 0, 184 8192, "rtc-m48t59");
320 sizeof(struct mostek48t08), 185 m48t59_data.type = M48T59RTC_TYPE_M48T08;
321 "mk48t08");
322
323 mstk48t02_regs = &mstk48t08_regs->regs;
324 } else 186 } else
325 return -ENODEV; 187 return -ENODEV;
326 188
327 /* Report a low battery voltage condition. */ 189 if (platform_device_register(&m48t59_rtc) < 0)
328 if (has_low_battery()) 190 printk(KERN_ERR "Registering RTC device failed\n");
329 printk(KERN_CRIT "NVRAM: Low battery voltage!\n");
330
331 /* Kick start the clock if it is completely stopped. */
332 if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
333 kick_start_clock();
334
335 mostek_set_system_time();
336 191
337 return 0; 192 return 0;
338} 193}
339 194
340static struct of_device_id clock_match[] = { 195static struct of_device_id __initdata clock_match[] = {
341 { 196 {
342 .name = "eeprom", 197 .name = "eeprom",
343 }, 198 },
@@ -348,7 +203,7 @@ static struct of_platform_driver clock_driver = {
348 .match_table = clock_match, 203 .match_table = clock_match,
349 .probe = clock_probe, 204 .probe = clock_probe,
350 .driver = { 205 .driver = {
351 .name = "clock", 206 .name = "rtc",
352 }, 207 },
353}; 208};
354 209
@@ -364,7 +219,6 @@ static int __init clock_init(void)
364 * need to see the clock registers. 219 * need to see the clock registers.
365 */ 220 */
366fs_initcall(clock_init); 221fs_initcall(clock_init);
367#endif /* !CONFIG_SUN4 */
368 222
369static void __init sbus_time_init(void) 223static void __init sbus_time_init(void)
370{ 224{
@@ -372,51 +226,8 @@ static void __init sbus_time_init(void)
372 BTFIXUPSET_CALL(bus_do_settimeofday, sbus_do_settimeofday, BTFIXUPCALL_NORM); 226 BTFIXUPSET_CALL(bus_do_settimeofday, sbus_do_settimeofday, BTFIXUPCALL_NORM);
373 btfixup(); 227 btfixup();
374 228
375 if (ARCH_SUN4)
376 sun4_clock_probe();
377
378 sparc_init_timers(timer_interrupt); 229 sparc_init_timers(timer_interrupt);
379 230
380#ifdef CONFIG_SUN4
381 if(idprom->id_machtype == (SM_SUN4 | SM_4_330)) {
382 mostek_set_system_time();
383 } else if(idprom->id_machtype == (SM_SUN4 | SM_4_260) ) {
384 /* initialise the intersil on sun4 */
385 unsigned int year, mon, day, hour, min, sec;
386 int temp;
387 struct intersil *iregs;
388
389 iregs=intersil_clock;
390 if(!iregs) {
391 prom_printf("Something wrong, clock regs not mapped yet.\n");
392 prom_halt();
393 }
394
395 intersil_intr(intersil_clock,INTERSIL_INT_100HZ);
396 disable_pil_irq(10);
397 intersil_stop(iregs);
398 intersil_read_intr(intersil_clock, temp);
399
400 temp = iregs->clk.int_csec;
401
402 sec = iregs->clk.int_sec;
403 min = iregs->clk.int_min;
404 hour = iregs->clk.int_hour;
405 day = iregs->clk.int_day;
406 mon = iregs->clk.int_month;
407 year = MSTK_CVT_YEAR(iregs->clk.int_year);
408
409 enable_pil_irq(10);
410 intersil_start(iregs);
411
412 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
413 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
414 set_normalized_timespec(&wall_to_monotonic,
415 -xtime.tv_sec, -xtime.tv_nsec);
416 printk("%u/%u/%u %u:%u:%u\n",day,mon,year,hour,min,sec);
417 }
418#endif
419
420 /* Now that OBP ticker has been silenced, it is safe to enable IRQ. */ 231 /* Now that OBP ticker has been silenced, it is safe to enable IRQ. */
421 local_irq_enable(); 232 local_irq_enable();
422} 233}
@@ -522,80 +333,15 @@ static int sbus_do_settimeofday(struct timespec *tv)
522 return 0; 333 return 0;
523} 334}
524 335
525/* 336static int set_rtc_mmss(unsigned long secs)
526 * BUG: This routine does not handle hour overflow properly; it just
527 * sets the minutes. Usually you won't notice until after reboot!
528 */
529static int set_rtc_mmss(unsigned long nowtime)
530{ 337{
531 int real_seconds, real_minutes, mostek_minutes; 338 struct rtc_device *rtc = rtc_class_open("rtc0");
532 struct mostek48t02 *regs = (struct mostek48t02 *)mstk48t02_regs; 339 int err = -1;
533 unsigned long flags;
534#ifdef CONFIG_SUN4
535 struct intersil *iregs = intersil_clock;
536 int temp;
537#endif
538 340
539 /* Not having a register set can lead to trouble. */ 341 if (rtc) {
540 if (!regs) { 342 err = rtc_set_mmss(rtc, secs);
541#ifdef CONFIG_SUN4 343 rtc_class_close(rtc);
542 if(!iregs)
543 return -1;
544 else {
545 temp = iregs->clk.int_csec;
546
547 mostek_minutes = iregs->clk.int_min;
548
549 real_seconds = nowtime % 60;
550 real_minutes = nowtime / 60;
551 if (((abs(real_minutes - mostek_minutes) + 15)/30) & 1)
552 real_minutes += 30; /* correct for half hour time zone */
553 real_minutes %= 60;
554
555 if (abs(real_minutes - mostek_minutes) < 30) {
556 intersil_stop(iregs);
557 iregs->clk.int_sec=real_seconds;
558 iregs->clk.int_min=real_minutes;
559 intersil_start(iregs);
560 } else {
561 printk(KERN_WARNING
562 "set_rtc_mmss: can't update from %d to %d\n",
563 mostek_minutes, real_minutes);
564 return -1;
565 }
566
567 return 0;
568 }
569#endif
570 } 344 }
571 345
572 spin_lock_irqsave(&mostek_lock, flags); 346 return err;
573 /* Read the current RTC minutes. */
574 regs->creg |= MSTK_CREG_READ;
575 mostek_minutes = MSTK_REG_MIN(regs);
576 regs->creg &= ~MSTK_CREG_READ;
577
578 /*
579 * since we're only adjusting minutes and seconds,
580 * don't interfere with hour overflow. This avoids
581 * messing with unknown time zones but requires your
582 * RTC not to be off by more than 15 minutes
583 */
584 real_seconds = nowtime % 60;
585 real_minutes = nowtime / 60;
586 if (((abs(real_minutes - mostek_minutes) + 15)/30) & 1)
587 real_minutes += 30; /* correct for half hour time zone */
588 real_minutes %= 60;
589
590 if (abs(real_minutes - mostek_minutes) < 30) {
591 regs->creg |= MSTK_CREG_WRITE;
592 MSTK_SET_REG_SEC(regs,real_seconds);
593 MSTK_SET_REG_MIN(regs,real_minutes);
594 regs->creg &= ~MSTK_CREG_WRITE;
595 spin_unlock_irqrestore(&mostek_lock, flags);
596 return 0;
597 } else {
598 spin_unlock_irqrestore(&mostek_lock, flags);
599 return -1;
600 }
601} 347}
diff --git a/arch/sparc/kernel/traps.c b/arch/sparc/kernel/traps.c
index 5d45d5fd8c9..2b7d5065903 100644
--- a/arch/sparc/kernel/traps.c
+++ b/arch/sparc/kernel/traps.c
@@ -43,23 +43,6 @@ void syscall_trace_exit(struct pt_regs *regs)
43{ 43{
44} 44}
45 45
46void sun4m_nmi(struct pt_regs *regs)
47{
48 unsigned long afsr, afar;
49
50 printk("Aieee: sun4m NMI received!\n");
51 /* XXX HyperSparc hack XXX */
52 __asm__ __volatile__("mov 0x500, %%g1\n\t"
53 "lda [%%g1] 0x4, %0\n\t"
54 "mov 0x600, %%g1\n\t"
55 "lda [%%g1] 0x4, %1\n\t" :
56 "=r" (afsr), "=r" (afar));
57 printk("afsr=%08lx afar=%08lx\n", afsr, afar);
58 printk("you lose buddy boy...\n");
59 show_regs(regs);
60 prom_halt();
61}
62
63void sun4d_nmi(struct pt_regs *regs) 46void sun4d_nmi(struct pt_regs *regs)
64{ 47{
65 printk("Aieee: sun4d NMI received!\n"); 48 printk("Aieee: sun4d NMI received!\n");
diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile
index 109c8b22cb3..ea88955d97f 100644
--- a/arch/sparc/mm/Makefile
+++ b/arch/sparc/mm/Makefile
@@ -3,13 +3,8 @@
3 3
4EXTRA_AFLAGS := -ansi 4EXTRA_AFLAGS := -ansi
5 5
6obj-y := fault.o init.o loadmmu.o generic.o extable.o btfixup.o 6obj-y := fault.o init.o loadmmu.o generic.o extable.o btfixup.o \
7 7 srmmu.o iommu.o io-unit.o hypersparc.o viking.o tsunami.o swift.o
8ifeq ($(CONFIG_SUN4),y)
9obj-y += nosrmmu.o
10else
11obj-y += srmmu.o iommu.o io-unit.o hypersparc.o viking.o tsunami.o swift.o
12endif
13 8
14ifdef CONFIG_HIGHMEM 9ifdef CONFIG_HIGHMEM
15obj-y += highmem.o 10obj-y += highmem.o
diff --git a/arch/sparc/mm/btfixup.c b/arch/sparc/mm/btfixup.c
index a312d127d47..5175ac2f482 100644
--- a/arch/sparc/mm/btfixup.c
+++ b/arch/sparc/mm/btfixup.c
@@ -20,11 +20,7 @@
20 20
21extern char *srmmu_name; 21extern char *srmmu_name;
22static char version[] __initdata = "Boot time fixup v1.6. 4/Mar/98 Jakub Jelinek (jj@ultra.linux.cz). Patching kernel for "; 22static char version[] __initdata = "Boot time fixup v1.6. 4/Mar/98 Jakub Jelinek (jj@ultra.linux.cz). Patching kernel for ";
23#ifdef CONFIG_SUN4
24static char str_sun4c[] __initdata = "sun4\n";
25#else
26static char str_sun4c[] __initdata = "sun4c\n"; 23static char str_sun4c[] __initdata = "sun4c\n";
27#endif
28static char str_srmmu[] __initdata = "srmmu[%s]/"; 24static char str_srmmu[] __initdata = "srmmu[%s]/";
29static char str_iommu[] __initdata = "iommu\n"; 25static char str_iommu[] __initdata = "iommu\n";
30static char str_iounit[] __initdata = "io-unit\n"; 26static char str_iounit[] __initdata = "io-unit\n";
@@ -86,7 +82,7 @@ void __init btfixup(void)
86 if (!visited) { 82 if (!visited) {
87 visited++; 83 visited++;
88 printk(version); 84 printk(version);
89 if (ARCH_SUN4C_SUN4) 85 if (ARCH_SUN4C)
90 printk(str_sun4c); 86 printk(str_sun4c);
91 else { 87 else {
92 printk(str_srmmu, srmmu_name); 88 printk(str_srmmu, srmmu_name);
diff --git a/arch/sparc/mm/fault.c b/arch/sparc/mm/fault.c
index 3604c2e8670..a507e117466 100644
--- a/arch/sparc/mm/fault.c
+++ b/arch/sparc/mm/fault.c
@@ -191,7 +191,7 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
191 * only copy the information from the master page table, 191 * only copy the information from the master page table,
192 * nothing more. 192 * nothing more.
193 */ 193 */
194 if (!ARCH_SUN4C_SUN4 && address >= TASK_SIZE) 194 if (!ARCH_SUN4C && address >= TASK_SIZE)
195 goto vmalloc_fault; 195 goto vmalloc_fault;
196 196
197 info.si_code = SEGV_MAPERR; 197 info.si_code = SEGV_MAPERR;
diff --git a/arch/sparc/mm/init.c b/arch/sparc/mm/init.c
index e103f1bb377..677c1e187a2 100644
--- a/arch/sparc/mm/init.c
+++ b/arch/sparc/mm/init.c
@@ -23,6 +23,7 @@
23#include <linux/highmem.h> 23#include <linux/highmem.h>
24#include <linux/bootmem.h> 24#include <linux/bootmem.h>
25#include <linux/pagemap.h> 25#include <linux/pagemap.h>
26#include <linux/poison.h>
26 27
27#include <asm/system.h> 28#include <asm/system.h>
28#include <asm/vac-ops.h> 29#include <asm/vac-ops.h>
@@ -480,6 +481,7 @@ void free_initmem (void)
480 for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) { 481 for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
481 struct page *p; 482 struct page *p;
482 483
484 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
483 p = virt_to_page(addr); 485 p = virt_to_page(addr);
484 486
485 ClearPageReserved(p); 487 ClearPageReserved(p);
@@ -488,20 +490,26 @@ void free_initmem (void)
488 totalram_pages++; 490 totalram_pages++;
489 num_physpages++; 491 num_physpages++;
490 } 492 }
491 printk (KERN_INFO "Freeing unused kernel memory: %dk freed\n", (&__init_end - &__init_begin) >> 10); 493 printk(KERN_INFO "Freeing unused kernel memory: %dk freed\n",
494 (&__init_end - &__init_begin) >> 10);
492} 495}
493 496
494#ifdef CONFIG_BLK_DEV_INITRD 497#ifdef CONFIG_BLK_DEV_INITRD
495void free_initrd_mem(unsigned long start, unsigned long end) 498void free_initrd_mem(unsigned long start, unsigned long end)
496{ 499{
497 if (start < end) 500 if (start < end)
498 printk (KERN_INFO "Freeing initrd memory: %ldk freed\n", (end - start) >> 10); 501 printk(KERN_INFO "Freeing initrd memory: %ldk freed\n",
502 (end - start) >> 10);
499 for (; start < end; start += PAGE_SIZE) { 503 for (; start < end; start += PAGE_SIZE) {
500 struct page *p = virt_to_page(start); 504 struct page *p;
505
506 memset((void *)start, POISON_FREE_INITMEM, PAGE_SIZE);
507 p = virt_to_page(start);
501 508
502 ClearPageReserved(p); 509 ClearPageReserved(p);
503 init_page_count(p); 510 init_page_count(p);
504 __free_page(p); 511 __free_page(p);
512 totalram_pages++;
505 num_physpages++; 513 num_physpages++;
506 } 514 }
507} 515}
diff --git a/arch/sparc/mm/io-unit.c b/arch/sparc/mm/io-unit.c
index f167835db3d..daadf5f8805 100644
--- a/arch/sparc/mm/io-unit.c
+++ b/arch/sparc/mm/io-unit.c
@@ -12,10 +12,11 @@
12#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */ 12#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */
13#include <linux/bitops.h> 13#include <linux/bitops.h>
14#include <linux/scatterlist.h> 14#include <linux/scatterlist.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
15 17
16#include <asm/pgalloc.h> 18#include <asm/pgalloc.h>
17#include <asm/pgtable.h> 19#include <asm/pgtable.h>
18#include <asm/sbus.h>
19#include <asm/io.h> 20#include <asm/io.h>
20#include <asm/io-unit.h> 21#include <asm/io-unit.h>
21#include <asm/mxcc.h> 22#include <asm/mxcc.h>
@@ -34,13 +35,10 @@
34#define IOPERM (IOUPTE_CACHE | IOUPTE_WRITE | IOUPTE_VALID) 35#define IOPERM (IOUPTE_CACHE | IOUPTE_WRITE | IOUPTE_VALID)
35#define MKIOPTE(phys) __iopte((((phys)>>4) & IOUPTE_PAGE) | IOPERM) 36#define MKIOPTE(phys) __iopte((((phys)>>4) & IOUPTE_PAGE) | IOPERM)
36 37
37void __init 38static void __init iounit_iommu_init(struct of_device *op)
38iounit_init(int sbi_node, int io_node, struct sbus_bus *sbus)
39{ 39{
40 iopte_t *xpt, *xptend;
41 struct iounit_struct *iounit; 40 struct iounit_struct *iounit;
42 struct linux_prom_registers iommu_promregs[PROMREG_MAX]; 41 iopte_t *xpt, *xptend;
43 struct resource r;
44 42
45 iounit = kzalloc(sizeof(struct iounit_struct), GFP_ATOMIC); 43 iounit = kzalloc(sizeof(struct iounit_struct), GFP_ATOMIC);
46 if (!iounit) { 44 if (!iounit) {
@@ -55,18 +53,13 @@ iounit_init(int sbi_node, int io_node, struct sbus_bus *sbus)
55 iounit->rotor[1] = IOUNIT_BMAP2_START; 53 iounit->rotor[1] = IOUNIT_BMAP2_START;
56 iounit->rotor[2] = IOUNIT_BMAPM_START; 54 iounit->rotor[2] = IOUNIT_BMAPM_START;
57 55
58 xpt = NULL; 56 xpt = of_ioremap(&op->resource[2], 0, PAGE_SIZE * 16, "XPT");
59 if(prom_getproperty(sbi_node, "reg", (void *) iommu_promregs, 57 if (!xpt) {
60 sizeof(iommu_promregs)) != -1) { 58 prom_printf("SUN4D: Cannot map External Page Table.");
61 prom_apply_generic_ranges(io_node, 0, iommu_promregs, 3); 59 prom_halt();
62 memset(&r, 0, sizeof(r));
63 r.flags = iommu_promregs[2].which_io;
64 r.start = iommu_promregs[2].phys_addr;
65 xpt = (iopte_t *) sbus_ioremap(&r, 0, PAGE_SIZE * 16, "XPT");
66 } 60 }
67 if(!xpt) panic("Cannot map External Page Table.");
68 61
69 sbus->ofdev.dev.archdata.iommu = iounit; 62 op->dev.archdata.iommu = iounit;
70 iounit->page_table = xpt; 63 iounit->page_table = xpt;
71 spin_lock_init(&iounit->lock); 64 spin_lock_init(&iounit->lock);
72 65
@@ -75,6 +68,25 @@ iounit_init(int sbi_node, int io_node, struct sbus_bus *sbus)
75 iopte_val(*xpt++) = 0; 68 iopte_val(*xpt++) = 0;
76} 69}
77 70
71static int __init iounit_init(void)
72{
73 extern void sun4d_init_sbi_irq(void);
74 struct device_node *dp;
75
76 for_each_node_by_name(dp, "sbi") {
77 struct of_device *op = of_find_device_by_node(dp);
78
79 iounit_iommu_init(op);
80 of_propagate_archdata(op);
81 }
82
83 sun4d_init_sbi_irq();
84
85 return 0;
86}
87
88subsys_initcall(iounit_init);
89
78/* One has to hold iounit->lock to call this */ 90/* One has to hold iounit->lock to call this */
79static unsigned long iounit_get_area(struct iounit_struct *iounit, unsigned long vaddr, int size) 91static unsigned long iounit_get_area(struct iounit_struct *iounit, unsigned long vaddr, int size)
80{ 92{
@@ -124,10 +136,10 @@ nexti: scan = find_next_zero_bit(iounit->bmap, limit, scan);
124 return vaddr; 136 return vaddr;
125} 137}
126 138
127static __u32 iounit_get_scsi_one(char *vaddr, unsigned long len, struct sbus_bus *sbus) 139static __u32 iounit_get_scsi_one(struct device *dev, char *vaddr, unsigned long len)
128{ 140{
141 struct iounit_struct *iounit = dev->archdata.iommu;
129 unsigned long ret, flags; 142 unsigned long ret, flags;
130 struct iounit_struct *iounit = sbus->ofdev.dev.archdata.iommu;
131 143
132 spin_lock_irqsave(&iounit->lock, flags); 144 spin_lock_irqsave(&iounit->lock, flags);
133 ret = iounit_get_area(iounit, (unsigned long)vaddr, len); 145 ret = iounit_get_area(iounit, (unsigned long)vaddr, len);
@@ -135,10 +147,10 @@ static __u32 iounit_get_scsi_one(char *vaddr, unsigned long len, struct sbus_bus
135 return ret; 147 return ret;
136} 148}
137 149
138static void iounit_get_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_bus *sbus) 150static void iounit_get_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
139{ 151{
152 struct iounit_struct *iounit = dev->archdata.iommu;
140 unsigned long flags; 153 unsigned long flags;
141 struct iounit_struct *iounit = sbus->ofdev.dev.archdata.iommu;
142 154
143 /* FIXME: Cache some resolved pages - often several sg entries are to the same page */ 155 /* FIXME: Cache some resolved pages - often several sg entries are to the same page */
144 spin_lock_irqsave(&iounit->lock, flags); 156 spin_lock_irqsave(&iounit->lock, flags);
@@ -151,10 +163,10 @@ static void iounit_get_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_bus
151 spin_unlock_irqrestore(&iounit->lock, flags); 163 spin_unlock_irqrestore(&iounit->lock, flags);
152} 164}
153 165
154static void iounit_release_scsi_one(__u32 vaddr, unsigned long len, struct sbus_bus *sbus) 166static void iounit_release_scsi_one(struct device *dev, __u32 vaddr, unsigned long len)
155{ 167{
168 struct iounit_struct *iounit = dev->archdata.iommu;
156 unsigned long flags; 169 unsigned long flags;
157 struct iounit_struct *iounit = sbus->ofdev.dev.archdata.iommu;
158 170
159 spin_lock_irqsave(&iounit->lock, flags); 171 spin_lock_irqsave(&iounit->lock, flags);
160 len = ((vaddr & ~PAGE_MASK) + len + (PAGE_SIZE-1)) >> PAGE_SHIFT; 172 len = ((vaddr & ~PAGE_MASK) + len + (PAGE_SIZE-1)) >> PAGE_SHIFT;
@@ -165,11 +177,11 @@ static void iounit_release_scsi_one(__u32 vaddr, unsigned long len, struct sbus_
165 spin_unlock_irqrestore(&iounit->lock, flags); 177 spin_unlock_irqrestore(&iounit->lock, flags);
166} 178}
167 179
168static void iounit_release_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_bus *sbus) 180static void iounit_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
169{ 181{
182 struct iounit_struct *iounit = dev->archdata.iommu;
170 unsigned long flags; 183 unsigned long flags;
171 unsigned long vaddr, len; 184 unsigned long vaddr, len;
172 struct iounit_struct *iounit = sbus->ofdev.dev.archdata.iommu;
173 185
174 spin_lock_irqsave(&iounit->lock, flags); 186 spin_lock_irqsave(&iounit->lock, flags);
175 while (sz != 0) { 187 while (sz != 0) {
@@ -185,12 +197,12 @@ static void iounit_release_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_
185} 197}
186 198
187#ifdef CONFIG_SBUS 199#ifdef CONFIG_SBUS
188static int iounit_map_dma_area(dma_addr_t *pba, unsigned long va, __u32 addr, int len) 200static int iounit_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va, __u32 addr, int len)
189{ 201{
202 struct iounit_struct *iounit = dev->archdata.iommu;
190 unsigned long page, end; 203 unsigned long page, end;
191 pgprot_t dvma_prot; 204 pgprot_t dvma_prot;
192 iopte_t *iopte; 205 iopte_t *iopte;
193 struct sbus_bus *sbus;
194 206
195 *pba = addr; 207 *pba = addr;
196 208
@@ -212,12 +224,8 @@ static int iounit_map_dma_area(dma_addr_t *pba, unsigned long va, __u32 addr, in
212 224
213 i = ((addr - IOUNIT_DMA_BASE) >> PAGE_SHIFT); 225 i = ((addr - IOUNIT_DMA_BASE) >> PAGE_SHIFT);
214 226
215 for_each_sbus(sbus) { 227 iopte = (iopte_t *)(iounit->page_table + i);
216 struct iounit_struct *iounit = sbus->ofdev.dev.archdata.iommu; 228 *iopte = MKIOPTE(__pa(page));
217
218 iopte = (iopte_t *)(iounit->page_table + i);
219 *iopte = MKIOPTE(__pa(page));
220 }
221 } 229 }
222 addr += PAGE_SIZE; 230 addr += PAGE_SIZE;
223 va += PAGE_SIZE; 231 va += PAGE_SIZE;
@@ -228,23 +236,10 @@ static int iounit_map_dma_area(dma_addr_t *pba, unsigned long va, __u32 addr, in
228 return 0; 236 return 0;
229} 237}
230 238
231static void iounit_unmap_dma_area(unsigned long addr, int len) 239static void iounit_unmap_dma_area(struct device *dev, unsigned long addr, int len)
232{ 240{
233 /* XXX Somebody please fill this in */ 241 /* XXX Somebody please fill this in */
234} 242}
235
236/* XXX We do not pass sbus device here, bad. */
237static struct page *iounit_translate_dvma(unsigned long addr)
238{
239 struct sbus_bus *sbus = sbus_root; /* They are all the same */
240 struct iounit_struct *iounit = sbus->ofdev.dev.archdata.iommu;
241 int i;
242 iopte_t *iopte;
243
244 i = ((addr - IOUNIT_DMA_BASE) >> PAGE_SHIFT);
245 iopte = (iopte_t *)(iounit->page_table + i);
246 return pfn_to_page(iopte_val(*iopte) >> (PAGE_SHIFT-4)); /* XXX sun4d guru, help */
247}
248#endif 243#endif
249 244
250static char *iounit_lockarea(char *vaddr, unsigned long len) 245static char *iounit_lockarea(char *vaddr, unsigned long len)
@@ -271,54 +266,5 @@ void __init ld_mmu_iounit(void)
271#ifdef CONFIG_SBUS 266#ifdef CONFIG_SBUS
272 BTFIXUPSET_CALL(mmu_map_dma_area, iounit_map_dma_area, BTFIXUPCALL_NORM); 267 BTFIXUPSET_CALL(mmu_map_dma_area, iounit_map_dma_area, BTFIXUPCALL_NORM);
273 BTFIXUPSET_CALL(mmu_unmap_dma_area, iounit_unmap_dma_area, BTFIXUPCALL_NORM); 268 BTFIXUPSET_CALL(mmu_unmap_dma_area, iounit_unmap_dma_area, BTFIXUPCALL_NORM);
274 BTFIXUPSET_CALL(mmu_translate_dvma, iounit_translate_dvma, BTFIXUPCALL_NORM);
275#endif 269#endif
276} 270}
277
278__u32 iounit_map_dma_init(struct sbus_bus *sbus, int size)
279{
280 int i, j, k, npages;
281 unsigned long rotor, scan, limit;
282 unsigned long flags;
283 __u32 ret;
284 struct iounit_struct *iounit = sbus->ofdev.dev.archdata.iommu;
285
286 npages = (size + (PAGE_SIZE-1)) >> PAGE_SHIFT;
287 i = 0x0213;
288 spin_lock_irqsave(&iounit->lock, flags);
289next: j = (i & 15);
290 rotor = iounit->rotor[j - 1];
291 limit = iounit->limit[j];
292 scan = rotor;
293nexti: scan = find_next_zero_bit(iounit->bmap, limit, scan);
294 if (scan + npages > limit) {
295 if (limit != rotor) {
296 limit = rotor;
297 scan = iounit->limit[j - 1];
298 goto nexti;
299 }
300 i >>= 4;
301 if (!(i & 15))
302 panic("iounit_map_dma_init: Couldn't find free iopte slots for %d bytes\n", size);
303 goto next;
304 }
305 for (k = 1, scan++; k < npages; k++)
306 if (test_bit(scan++, iounit->bmap))
307 goto nexti;
308 iounit->rotor[j - 1] = (scan < limit) ? scan : iounit->limit[j - 1];
309 scan -= npages;
310 ret = IOUNIT_DMA_BASE + (scan << PAGE_SHIFT);
311 for (k = 0; k < npages; k++, scan++)
312 set_bit(scan, iounit->bmap);
313 spin_unlock_irqrestore(&iounit->lock, flags);
314 return ret;
315}
316
317__u32 iounit_map_dma_page(__u32 vaddr, void *addr, struct sbus_bus *sbus)
318{
319 int scan = (vaddr - IOUNIT_DMA_BASE) >> PAGE_SHIFT;
320 struct iounit_struct *iounit = sbus->ofdev.dev.archdata.iommu;
321
322 iounit->page_table[scan] = MKIOPTE(__pa(((unsigned long)addr) & PAGE_MASK));
323 return vaddr + (((unsigned long)addr) & ~PAGE_MASK);
324}
diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c
index 4b934270f05..e7a499e3aa3 100644
--- a/arch/sparc/mm/iommu.c
+++ b/arch/sparc/mm/iommu.c
@@ -13,10 +13,11 @@
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */ 14#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */
15#include <linux/scatterlist.h> 15#include <linux/scatterlist.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
16 18
17#include <asm/pgalloc.h> 19#include <asm/pgalloc.h>
18#include <asm/pgtable.h> 20#include <asm/pgtable.h>
19#include <asm/sbus.h>
20#include <asm/io.h> 21#include <asm/io.h>
21#include <asm/mxcc.h> 22#include <asm/mxcc.h>
22#include <asm/mbus.h> 23#include <asm/mbus.h>
@@ -55,30 +56,21 @@ static pgprot_t dvma_prot; /* Consistent mapping pte flags */
55#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID) 56#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
56#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ) 57#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
57 58
58void __init 59static void __init sbus_iommu_init(struct of_device *op)
59iommu_init(int iommund, struct sbus_bus *sbus)
60{ 60{
61 unsigned int impl, vers;
62 unsigned long tmp;
63 struct iommu_struct *iommu; 61 struct iommu_struct *iommu;
64 struct linux_prom_registers iommu_promregs[PROMREG_MAX]; 62 unsigned int impl, vers;
65 struct resource r;
66 unsigned long *bitmap; 63 unsigned long *bitmap;
64 unsigned long tmp;
67 65
68 iommu = kmalloc(sizeof(struct iommu_struct), GFP_ATOMIC); 66 iommu = kmalloc(sizeof(struct iommu_struct), GFP_ATOMIC);
69 if (!iommu) { 67 if (!iommu) {
70 prom_printf("Unable to allocate iommu structure\n"); 68 prom_printf("Unable to allocate iommu structure\n");
71 prom_halt(); 69 prom_halt();
72 } 70 }
73 iommu->regs = NULL; 71
74 if (prom_getproperty(iommund, "reg", (void *) iommu_promregs, 72 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
75 sizeof(iommu_promregs)) != -1) { 73 "iommu_regs");
76 memset(&r, 0, sizeof(r));
77 r.flags = iommu_promregs[0].which_io;
78 r.start = iommu_promregs[0].phys_addr;
79 iommu->regs = (struct iommu_regs *)
80 sbus_ioremap(&r, 0, PAGE_SIZE * 3, "iommu_regs");
81 }
82 if (!iommu->regs) { 74 if (!iommu->regs) {
83 prom_printf("Cannot map IOMMU registers\n"); 75 prom_printf("Cannot map IOMMU registers\n");
84 prom_halt(); 76 prom_halt();
@@ -128,13 +120,29 @@ iommu_init(int iommund, struct sbus_bus *sbus)
128 else 120 else
129 iommu->usemap.num_colors = 1; 121 iommu->usemap.num_colors = 1;
130 122
131 printk("IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n", 123 printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
132 impl, vers, iommu->page_table, 124 impl, vers, iommu->page_table,
133 (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES); 125 (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
126
127 op->dev.archdata.iommu = iommu;
128}
129
130static int __init iommu_init(void)
131{
132 struct device_node *dp;
133
134 for_each_node_by_name(dp, "iommu") {
135 struct of_device *op = of_find_device_by_node(dp);
136
137 sbus_iommu_init(op);
138 of_propagate_archdata(op);
139 }
134 140
135 sbus->ofdev.dev.archdata.iommu = iommu; 141 return 0;
136} 142}
137 143
144subsys_initcall(iommu_init);
145
138/* This begs to be btfixup-ed by srmmu. */ 146/* This begs to be btfixup-ed by srmmu. */
139/* Flush the iotlb entries to ram. */ 147/* Flush the iotlb entries to ram. */
140/* This could be better if we didn't have to flush whole pages. */ 148/* This could be better if we didn't have to flush whole pages. */
@@ -164,9 +172,9 @@ static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
164 } 172 }
165} 173}
166 174
167static u32 iommu_get_one(struct page *page, int npages, struct sbus_bus *sbus) 175static u32 iommu_get_one(struct device *dev, struct page *page, int npages)
168{ 176{
169 struct iommu_struct *iommu = sbus->ofdev.dev.archdata.iommu; 177 struct iommu_struct *iommu = dev->archdata.iommu;
170 int ioptex; 178 int ioptex;
171 iopte_t *iopte, *iopte0; 179 iopte_t *iopte, *iopte0;
172 unsigned int busa, busa0; 180 unsigned int busa, busa0;
@@ -194,8 +202,7 @@ static u32 iommu_get_one(struct page *page, int npages, struct sbus_bus *sbus)
194 return busa0; 202 return busa0;
195} 203}
196 204
197static u32 iommu_get_scsi_one(char *vaddr, unsigned int len, 205static u32 iommu_get_scsi_one(struct device *dev, char *vaddr, unsigned int len)
198 struct sbus_bus *sbus)
199{ 206{
200 unsigned long off; 207 unsigned long off;
201 int npages; 208 int npages;
@@ -205,22 +212,22 @@ static u32 iommu_get_scsi_one(char *vaddr, unsigned int len,
205 off = (unsigned long)vaddr & ~PAGE_MASK; 212 off = (unsigned long)vaddr & ~PAGE_MASK;
206 npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT; 213 npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
207 page = virt_to_page((unsigned long)vaddr & PAGE_MASK); 214 page = virt_to_page((unsigned long)vaddr & PAGE_MASK);
208 busa = iommu_get_one(page, npages, sbus); 215 busa = iommu_get_one(dev, page, npages);
209 return busa + off; 216 return busa + off;
210} 217}
211 218
212static __u32 iommu_get_scsi_one_noflush(char *vaddr, unsigned long len, struct sbus_bus *sbus) 219static __u32 iommu_get_scsi_one_noflush(struct device *dev, char *vaddr, unsigned long len)
213{ 220{
214 return iommu_get_scsi_one(vaddr, len, sbus); 221 return iommu_get_scsi_one(dev, vaddr, len);
215} 222}
216 223
217static __u32 iommu_get_scsi_one_gflush(char *vaddr, unsigned long len, struct sbus_bus *sbus) 224static __u32 iommu_get_scsi_one_gflush(struct device *dev, char *vaddr, unsigned long len)
218{ 225{
219 flush_page_for_dma(0); 226 flush_page_for_dma(0);
220 return iommu_get_scsi_one(vaddr, len, sbus); 227 return iommu_get_scsi_one(dev, vaddr, len);
221} 228}
222 229
223static __u32 iommu_get_scsi_one_pflush(char *vaddr, unsigned long len, struct sbus_bus *sbus) 230static __u32 iommu_get_scsi_one_pflush(struct device *dev, char *vaddr, unsigned long len)
224{ 231{
225 unsigned long page = ((unsigned long) vaddr) & PAGE_MASK; 232 unsigned long page = ((unsigned long) vaddr) & PAGE_MASK;
226 233
@@ -228,23 +235,23 @@ static __u32 iommu_get_scsi_one_pflush(char *vaddr, unsigned long len, struct sb
228 flush_page_for_dma(page); 235 flush_page_for_dma(page);
229 page += PAGE_SIZE; 236 page += PAGE_SIZE;
230 } 237 }
231 return iommu_get_scsi_one(vaddr, len, sbus); 238 return iommu_get_scsi_one(dev, vaddr, len);
232} 239}
233 240
234static void iommu_get_scsi_sgl_noflush(struct scatterlist *sg, int sz, struct sbus_bus *sbus) 241static void iommu_get_scsi_sgl_noflush(struct device *dev, struct scatterlist *sg, int sz)
235{ 242{
236 int n; 243 int n;
237 244
238 while (sz != 0) { 245 while (sz != 0) {
239 --sz; 246 --sz;
240 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT; 247 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
241 sg->dvma_address = iommu_get_one(sg_page(sg), n, sbus) + sg->offset; 248 sg->dvma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
242 sg->dvma_length = (__u32) sg->length; 249 sg->dvma_length = (__u32) sg->length;
243 sg = sg_next(sg); 250 sg = sg_next(sg);
244 } 251 }
245} 252}
246 253
247static void iommu_get_scsi_sgl_gflush(struct scatterlist *sg, int sz, struct sbus_bus *sbus) 254static void iommu_get_scsi_sgl_gflush(struct device *dev, struct scatterlist *sg, int sz)
248{ 255{
249 int n; 256 int n;
250 257
@@ -252,13 +259,13 @@ static void iommu_get_scsi_sgl_gflush(struct scatterlist *sg, int sz, struct sbu
252 while (sz != 0) { 259 while (sz != 0) {
253 --sz; 260 --sz;
254 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT; 261 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
255 sg->dvma_address = iommu_get_one(sg_page(sg), n, sbus) + sg->offset; 262 sg->dvma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
256 sg->dvma_length = (__u32) sg->length; 263 sg->dvma_length = (__u32) sg->length;
257 sg = sg_next(sg); 264 sg = sg_next(sg);
258 } 265 }
259} 266}
260 267
261static void iommu_get_scsi_sgl_pflush(struct scatterlist *sg, int sz, struct sbus_bus *sbus) 268static void iommu_get_scsi_sgl_pflush(struct device *dev, struct scatterlist *sg, int sz)
262{ 269{
263 unsigned long page, oldpage = 0; 270 unsigned long page, oldpage = 0;
264 int n, i; 271 int n, i;
@@ -283,15 +290,15 @@ static void iommu_get_scsi_sgl_pflush(struct scatterlist *sg, int sz, struct sbu
283 } 290 }
284 } 291 }
285 292
286 sg->dvma_address = iommu_get_one(sg_page(sg), n, sbus) + sg->offset; 293 sg->dvma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
287 sg->dvma_length = (__u32) sg->length; 294 sg->dvma_length = (__u32) sg->length;
288 sg = sg_next(sg); 295 sg = sg_next(sg);
289 } 296 }
290} 297}
291 298
292static void iommu_release_one(u32 busa, int npages, struct sbus_bus *sbus) 299static void iommu_release_one(struct device *dev, u32 busa, int npages)
293{ 300{
294 struct iommu_struct *iommu = sbus->ofdev.dev.archdata.iommu; 301 struct iommu_struct *iommu = dev->archdata.iommu;
295 int ioptex; 302 int ioptex;
296 int i; 303 int i;
297 304
@@ -305,17 +312,17 @@ static void iommu_release_one(u32 busa, int npages, struct sbus_bus *sbus)
305 bit_map_clear(&iommu->usemap, ioptex, npages); 312 bit_map_clear(&iommu->usemap, ioptex, npages);
306} 313}
307 314
308static void iommu_release_scsi_one(__u32 vaddr, unsigned long len, struct sbus_bus *sbus) 315static void iommu_release_scsi_one(struct device *dev, __u32 vaddr, unsigned long len)
309{ 316{
310 unsigned long off; 317 unsigned long off;
311 int npages; 318 int npages;
312 319
313 off = vaddr & ~PAGE_MASK; 320 off = vaddr & ~PAGE_MASK;
314 npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT; 321 npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
315 iommu_release_one(vaddr & PAGE_MASK, npages, sbus); 322 iommu_release_one(dev, vaddr & PAGE_MASK, npages);
316} 323}
317 324
318static void iommu_release_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_bus *sbus) 325static void iommu_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
319{ 326{
320 int n; 327 int n;
321 328
@@ -323,18 +330,18 @@ static void iommu_release_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_b
323 --sz; 330 --sz;
324 331
325 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT; 332 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
326 iommu_release_one(sg->dvma_address & PAGE_MASK, n, sbus); 333 iommu_release_one(dev, sg->dvma_address & PAGE_MASK, n);
327 sg->dvma_address = 0x21212121; 334 sg->dvma_address = 0x21212121;
328 sg = sg_next(sg); 335 sg = sg_next(sg);
329 } 336 }
330} 337}
331 338
332#ifdef CONFIG_SBUS 339#ifdef CONFIG_SBUS
333static int iommu_map_dma_area(dma_addr_t *pba, unsigned long va, 340static int iommu_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va,
334 unsigned long addr, int len) 341 unsigned long addr, int len)
335{ 342{
343 struct iommu_struct *iommu = dev->archdata.iommu;
336 unsigned long page, end; 344 unsigned long page, end;
337 struct iommu_struct *iommu = sbus_root->ofdev.dev.archdata.iommu;
338 iopte_t *iopte = iommu->page_table; 345 iopte_t *iopte = iommu->page_table;
339 iopte_t *first; 346 iopte_t *first;
340 int ioptex; 347 int ioptex;
@@ -397,9 +404,9 @@ static int iommu_map_dma_area(dma_addr_t *pba, unsigned long va,
397 return 0; 404 return 0;
398} 405}
399 406
400static void iommu_unmap_dma_area(unsigned long busa, int len) 407static void iommu_unmap_dma_area(struct device *dev, unsigned long busa, int len)
401{ 408{
402 struct iommu_struct *iommu = sbus_root->ofdev.dev.archdata.iommu; 409 struct iommu_struct *iommu = dev->archdata.iommu;
403 iopte_t *iopte = iommu->page_table; 410 iopte_t *iopte = iommu->page_table;
404 unsigned long end; 411 unsigned long end;
405 int ioptex = (busa - iommu->start) >> PAGE_SHIFT; 412 int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
@@ -417,15 +424,6 @@ static void iommu_unmap_dma_area(unsigned long busa, int len)
417 iommu_invalidate(iommu->regs); 424 iommu_invalidate(iommu->regs);
418 bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT); 425 bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
419} 426}
420
421static struct page *iommu_translate_dvma(unsigned long busa)
422{
423 struct iommu_struct *iommu = sbus_root->ofdev.dev.archdata.iommu;
424 iopte_t *iopte = iommu->page_table;
425
426 iopte += ((busa - iommu->start) >> PAGE_SHIFT);
427 return pfn_to_page((iopte_val(*iopte) & IOPTE_PAGE) >> (PAGE_SHIFT-4));
428}
429#endif 427#endif
430 428
431static char *iommu_lockarea(char *vaddr, unsigned long len) 429static char *iommu_lockarea(char *vaddr, unsigned long len)
@@ -461,7 +459,6 @@ void __init ld_mmu_iommu(void)
461#ifdef CONFIG_SBUS 459#ifdef CONFIG_SBUS
462 BTFIXUPSET_CALL(mmu_map_dma_area, iommu_map_dma_area, BTFIXUPCALL_NORM); 460 BTFIXUPSET_CALL(mmu_map_dma_area, iommu_map_dma_area, BTFIXUPCALL_NORM);
463 BTFIXUPSET_CALL(mmu_unmap_dma_area, iommu_unmap_dma_area, BTFIXUPCALL_NORM); 461 BTFIXUPSET_CALL(mmu_unmap_dma_area, iommu_unmap_dma_area, BTFIXUPCALL_NORM);
464 BTFIXUPSET_CALL(mmu_translate_dvma, iommu_translate_dvma, BTFIXUPCALL_NORM);
465#endif 462#endif
466 463
467 if (viking_mxcc_present || srmmu_modtype == HyperSparc) { 464 if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
diff --git a/arch/sparc/mm/nosrmmu.c b/arch/sparc/mm/nosrmmu.c
deleted file mode 100644
index 3701f70fc30..00000000000
--- a/arch/sparc/mm/nosrmmu.c
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * nosrmmu.c: This file is a bunch of dummies for sun4 compiles,
3 * so that it does not need srmmu and avoid ifdefs.
4 *
5 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/kernel.h>
9#include <linux/mm.h>
10#include <linux/init.h>
11#include <asm/mbus.h>
12#include <asm/sbus.h>
13
14static char shouldnothappen[] __initdata = "SUN4 kernel can only run on SUN4\n";
15
16enum mbus_module srmmu_modtype;
17void *srmmu_nocache_pool;
18
19int vac_cache_size = 0;
20
21static void __init should_not_happen(void)
22{
23 prom_printf(shouldnothappen);
24 prom_halt();
25}
26
27void __init srmmu_frob_mem_map(unsigned long start_mem)
28{
29 should_not_happen();
30}
31
32unsigned long __init srmmu_paging_init(unsigned long start_mem, unsigned long end_mem)
33{
34 should_not_happen();
35 return 0;
36}
37
38void __init ld_mmu_srmmu(void)
39{
40 should_not_happen();
41}
42
43void srmmu_mapioaddr(unsigned long physaddr, unsigned long virt_addr, int bus_type, int rdonly)
44{
45}
46
47void srmmu_unmapioaddr(unsigned long virt_addr)
48{
49}
50
51__u32 iounit_map_dma_init(struct sbus_bus *sbus, int size)
52{
53 return 0;
54}
55
56__u32 iounit_map_dma_page(__u32 vaddr, void *addr, struct sbus_bus *sbus)
57{
58 return 0;
59}
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index ee30462598f..6a5d7cabc04 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -31,7 +31,6 @@
31#include <asm/mbus.h> 31#include <asm/mbus.h>
32#include <asm/cache.h> 32#include <asm/cache.h>
33#include <asm/oplib.h> 33#include <asm/oplib.h>
34#include <asm/sbus.h>
35#include <asm/asi.h> 34#include <asm/asi.h>
36#include <asm/msi.h> 35#include <asm/msi.h>
37#include <asm/mmu_context.h> 36#include <asm/mmu_context.h>
diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c
index d1782f6368b..fe65aeeb394 100644
--- a/arch/sparc/mm/sun4c.c
+++ b/arch/sparc/mm/sun4c.c
@@ -31,7 +31,6 @@
31#include <asm/oplib.h> 31#include <asm/oplib.h>
32#include <asm/openprom.h> 32#include <asm/openprom.h>
33#include <asm/mmu_context.h> 33#include <asm/mmu_context.h>
34#include <asm/sun4paddr.h>
35#include <asm/highmem.h> 34#include <asm/highmem.h>
36#include <asm/btfixup.h> 35#include <asm/btfixup.h>
37#include <asm/cacheflush.h> 36#include <asm/cacheflush.h>
@@ -52,15 +51,11 @@ extern int num_segmaps, num_contexts;
52 51
53extern unsigned long page_kernel; 52extern unsigned long page_kernel;
54 53
55#ifdef CONFIG_SUN4
56#define SUN4C_VAC_SIZE sun4c_vacinfo.num_bytes
57#else
58/* That's it, we prom_halt() on sun4c if the cache size is something other than 65536. 54/* That's it, we prom_halt() on sun4c if the cache size is something other than 65536.
59 * So let's save some cycles and just use that everywhere except for that bootup 55 * So let's save some cycles and just use that everywhere except for that bootup
60 * sanity check. 56 * sanity check.
61 */ 57 */
62#define SUN4C_VAC_SIZE 65536 58#define SUN4C_VAC_SIZE 65536
63#endif
64 59
65#define SUN4C_KERNEL_BUCKETS 32 60#define SUN4C_KERNEL_BUCKETS 32
66 61
@@ -285,75 +280,32 @@ void __init sun4c_probe_vac(void)
285{ 280{
286 sun4c_disable_vac(); 281 sun4c_disable_vac();
287 282
288 if (ARCH_SUN4) { 283 if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) ||
289 switch (idprom->id_machtype) { 284 (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) {
290 285 /* PROM on SS1 lacks this info, to be super safe we
291 case (SM_SUN4|SM_4_110): 286 * hard code it here since this arch is cast in stone.
292 sun4c_vacinfo.type = VAC_NONE; 287 */
293 sun4c_vacinfo.num_bytes = 0; 288 sun4c_vacinfo.num_bytes = 65536;
294 sun4c_vacinfo.linesize = 0; 289 sun4c_vacinfo.linesize = 16;
295 sun4c_vacinfo.do_hwflushes = 0;
296 prom_printf("No VAC. Get some bucks and buy a real computer.");
297 prom_halt();
298 break;
299
300 case (SM_SUN4|SM_4_260):
301 sun4c_vacinfo.type = VAC_WRITE_BACK;
302 sun4c_vacinfo.num_bytes = 128 * 1024;
303 sun4c_vacinfo.linesize = 16;
304 sun4c_vacinfo.do_hwflushes = 0;
305 break;
306
307 case (SM_SUN4|SM_4_330):
308 sun4c_vacinfo.type = VAC_WRITE_THROUGH;
309 sun4c_vacinfo.num_bytes = 128 * 1024;
310 sun4c_vacinfo.linesize = 16;
311 sun4c_vacinfo.do_hwflushes = 0;
312 break;
313
314 case (SM_SUN4|SM_4_470):
315 sun4c_vacinfo.type = VAC_WRITE_BACK;
316 sun4c_vacinfo.num_bytes = 128 * 1024;
317 sun4c_vacinfo.linesize = 32;
318 sun4c_vacinfo.do_hwflushes = 0;
319 break;
320
321 default:
322 prom_printf("Cannot initialize VAC - weird sun4 model idprom->id_machtype = %d", idprom->id_machtype);
323 prom_halt();
324 };
325 } else { 290 } else {
326 sun4c_vacinfo.type = VAC_WRITE_THROUGH; 291 sun4c_vacinfo.num_bytes =
292 prom_getintdefault(prom_root_node, "vac-size", 65536);
293 sun4c_vacinfo.linesize =
294 prom_getintdefault(prom_root_node, "vac-linesize", 16);
295 }
296 sun4c_vacinfo.do_hwflushes =
297 prom_getintdefault(prom_root_node, "vac-hwflush", 0);
327 298
328 if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) || 299 if (sun4c_vacinfo.do_hwflushes == 0)
329 (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) {
330 /* PROM on SS1 lacks this info, to be super safe we
331 * hard code it here since this arch is cast in stone.
332 */
333 sun4c_vacinfo.num_bytes = 65536;
334 sun4c_vacinfo.linesize = 16;
335 } else {
336 sun4c_vacinfo.num_bytes =
337 prom_getintdefault(prom_root_node, "vac-size", 65536);
338 sun4c_vacinfo.linesize =
339 prom_getintdefault(prom_root_node, "vac-linesize", 16);
340 }
341 sun4c_vacinfo.do_hwflushes = 300 sun4c_vacinfo.do_hwflushes =
342 prom_getintdefault(prom_root_node, "vac-hwflush", 0); 301 prom_getintdefault(prom_root_node, "vac_hwflush", 0);
343
344 if (sun4c_vacinfo.do_hwflushes == 0)
345 sun4c_vacinfo.do_hwflushes =
346 prom_getintdefault(prom_root_node, "vac_hwflush", 0);
347 302
348 if (sun4c_vacinfo.num_bytes != 65536) { 303 if (sun4c_vacinfo.num_bytes != 65536) {
349 prom_printf("WEIRD Sun4C VAC cache size, " 304 prom_printf("WEIRD Sun4C VAC cache size, "
350 "tell sparclinux@vger.kernel.org"); 305 "tell sparclinux@vger.kernel.org");
351 prom_halt(); 306 prom_halt();
352 }
353 } 307 }
354 308
355 sun4c_vacinfo.num_lines =
356 (sun4c_vacinfo.num_bytes / sun4c_vacinfo.linesize);
357 switch (sun4c_vacinfo.linesize) { 309 switch (sun4c_vacinfo.linesize) {
358 case 16: 310 case 16:
359 sun4c_vacinfo.log2lsize = 4; 311 sun4c_vacinfo.log2lsize = 4;
@@ -447,49 +399,18 @@ static void __init patch_kernel_fault_handler(void)
447 399
448static void __init sun4c_probe_mmu(void) 400static void __init sun4c_probe_mmu(void)
449{ 401{
450 if (ARCH_SUN4) { 402 if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) ||
451 switch (idprom->id_machtype) { 403 (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) {
452 case (SM_SUN4|SM_4_110): 404 /* Hardcode these just to be safe, PROM on SS1 does
453 prom_printf("No support for 4100 yet\n"); 405 * not have this info available in the root node.
454 prom_halt(); 406 */
455 num_segmaps = 256; 407 num_segmaps = 128;
456 num_contexts = 8; 408 num_contexts = 8;
457 break;
458
459 case (SM_SUN4|SM_4_260):
460 /* should be 512 segmaps. when it get fixed */
461 num_segmaps = 256;
462 num_contexts = 16;
463 break;
464
465 case (SM_SUN4|SM_4_330):
466 num_segmaps = 256;
467 num_contexts = 16;
468 break;
469
470 case (SM_SUN4|SM_4_470):
471 /* should be 1024 segmaps. when it get fixed */
472 num_segmaps = 256;
473 num_contexts = 64;
474 break;
475 default:
476 prom_printf("Invalid SUN4 model\n");
477 prom_halt();
478 };
479 } else { 409 } else {
480 if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) || 410 num_segmaps =
481 (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) { 411 prom_getintdefault(prom_root_node, "mmu-npmg", 128);
482 /* Hardcode these just to be safe, PROM on SS1 does 412 num_contexts =
483 * not have this info available in the root node. 413 prom_getintdefault(prom_root_node, "mmu-nctx", 0x8);
484 */
485 num_segmaps = 128;
486 num_contexts = 8;
487 } else {
488 num_segmaps =
489 prom_getintdefault(prom_root_node, "mmu-npmg", 128);
490 num_contexts =
491 prom_getintdefault(prom_root_node, "mmu-nctx", 0x8);
492 }
493 } 414 }
494 patch_kernel_fault_handler(); 415 patch_kernel_fault_handler();
495} 416}
@@ -501,18 +422,14 @@ void __init sun4c_probe_memerr_reg(void)
501 int node; 422 int node;
502 struct linux_prom_registers regs[1]; 423 struct linux_prom_registers regs[1];
503 424
504 if (ARCH_SUN4) { 425 node = prom_getchild(prom_root_node);
505 sun4c_memerr_reg = ioremap(sun4_memreg_physaddr, PAGE_SIZE); 426 node = prom_searchsiblings(prom_root_node, "memory-error");
506 } else { 427 if (!node)
507 node = prom_getchild(prom_root_node); 428 return;
508 node = prom_searchsiblings(prom_root_node, "memory-error"); 429 if (prom_getproperty(node, "reg", (char *)regs, sizeof(regs)) <= 0)
509 if (!node) 430 return;
510 return; 431 /* hmm I think regs[0].which_io is zero here anyways */
511 if (prom_getproperty(node, "reg", (char *)regs, sizeof(regs)) <= 0) 432 sun4c_memerr_reg = ioremap(regs[0].phys_addr, regs[0].reg_size);
512 return;
513 /* hmm I think regs[0].which_io is zero here anyways */
514 sun4c_memerr_reg = ioremap(regs[0].phys_addr, regs[0].reg_size);
515 }
516} 433}
517 434
518static inline void sun4c_init_ss2_cache_bug(void) 435static inline void sun4c_init_ss2_cache_bug(void)
@@ -521,7 +438,6 @@ static inline void sun4c_init_ss2_cache_bug(void)
521 438
522 if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS2)) || 439 if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS2)) ||
523 (idprom->id_machtype == (SM_SUN4C | SM_4C_IPX)) || 440 (idprom->id_machtype == (SM_SUN4C | SM_4C_IPX)) ||
524 (idprom->id_machtype == (SM_SUN4 | SM_4_330)) ||
525 (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC))) { 441 (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC))) {
526 /* Whee.. */ 442 /* Whee.. */
527 printk("SS2 cache bug detected, uncaching trap table page\n"); 443 printk("SS2 cache bug detected, uncaching trap table page\n");
@@ -532,8 +448,8 @@ static inline void sun4c_init_ss2_cache_bug(void)
532} 448}
533 449
534/* Addr is always aligned on a page boundary for us already. */ 450/* Addr is always aligned on a page boundary for us already. */
535static int sun4c_map_dma_area(dma_addr_t *pba, unsigned long va, 451static int sun4c_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va,
536 unsigned long addr, int len) 452 unsigned long addr, int len)
537{ 453{
538 unsigned long page, end; 454 unsigned long page, end;
539 455
@@ -555,14 +471,7 @@ static int sun4c_map_dma_area(dma_addr_t *pba, unsigned long va,
555 return 0; 471 return 0;
556} 472}
557 473
558static struct page *sun4c_translate_dvma(unsigned long busa) 474static void sun4c_unmap_dma_area(struct device *dev, unsigned long busa, int len)
559{
560 /* Fortunately for us, bus_addr == uncached_virt in sun4c. */
561 unsigned long pte = sun4c_get_pte(busa);
562 return pfn_to_page(pte & SUN4C_PFN_MASK);
563}
564
565static void sun4c_unmap_dma_area(unsigned long busa, int len)
566{ 475{
567 /* Fortunately for us, bus_addr == uncached_virt in sun4c. */ 476 /* Fortunately for us, bus_addr == uncached_virt in sun4c. */
568 /* XXX Implement this */ 477 /* XXX Implement this */
@@ -624,11 +533,7 @@ static inline void sun4c_init_map_kernelprom(unsigned long kernel_end)
624{ 533{
625 unsigned long vaddr; 534 unsigned long vaddr;
626 unsigned char pseg, ctx; 535 unsigned char pseg, ctx;
627#ifdef CONFIG_SUN4 536
628 /* sun4/110 and 260 have no kadb. */
629 if ((idprom->id_machtype != (SM_SUN4 | SM_4_260)) &&
630 (idprom->id_machtype != (SM_SUN4 | SM_4_110))) {
631#endif
632 for (vaddr = KADB_DEBUGGER_BEGVM; 537 for (vaddr = KADB_DEBUGGER_BEGVM;
633 vaddr < LINUX_OPPROM_ENDVM; 538 vaddr < LINUX_OPPROM_ENDVM;
634 vaddr += SUN4C_REAL_PGDIR_SIZE) { 539 vaddr += SUN4C_REAL_PGDIR_SIZE) {
@@ -640,9 +545,7 @@ static inline void sun4c_init_map_kernelprom(unsigned long kernel_end)
640 fix_permissions(vaddr, _SUN4C_PAGE_PRIV, 0); 545 fix_permissions(vaddr, _SUN4C_PAGE_PRIV, 0);
641 } 546 }
642 } 547 }
643#ifdef CONFIG_SUN4 548
644 }
645#endif
646 for (vaddr = KERNBASE; vaddr < kernel_end; vaddr += SUN4C_REAL_PGDIR_SIZE) { 549 for (vaddr = KERNBASE; vaddr < kernel_end; vaddr += SUN4C_REAL_PGDIR_SIZE) {
647 pseg = sun4c_get_segmap(vaddr); 550 pseg = sun4c_get_segmap(vaddr);
648 mmu_entry_pool[pseg].locked = 1; 551 mmu_entry_pool[pseg].locked = 1;
@@ -1048,14 +951,10 @@ static struct thread_info *sun4c_alloc_thread_info(void)
1048 * so we must flush the cache to guarantee consistency. 951 * so we must flush the cache to guarantee consistency.
1049 */ 952 */
1050 sun4c_flush_page(pages); 953 sun4c_flush_page(pages);
1051#ifndef CONFIG_SUN4
1052 sun4c_flush_page(pages + PAGE_SIZE); 954 sun4c_flush_page(pages + PAGE_SIZE);
1053#endif
1054 955
1055 sun4c_put_pte(addr, BUCKET_PTE(pages)); 956 sun4c_put_pte(addr, BUCKET_PTE(pages));
1056#ifndef CONFIG_SUN4
1057 sun4c_put_pte(addr + PAGE_SIZE, BUCKET_PTE(pages + PAGE_SIZE)); 957 sun4c_put_pte(addr + PAGE_SIZE, BUCKET_PTE(pages + PAGE_SIZE));
1058#endif
1059 958
1060#ifdef CONFIG_DEBUG_STACK_USAGE 959#ifdef CONFIG_DEBUG_STACK_USAGE
1061 memset((void *)addr, 0, PAGE_SIZE << THREAD_INFO_ORDER); 960 memset((void *)addr, 0, PAGE_SIZE << THREAD_INFO_ORDER);
@@ -1072,13 +971,11 @@ static void sun4c_free_thread_info(struct thread_info *ti)
1072 971
1073 /* We are deleting a mapping, so the flush here is mandatory. */ 972 /* We are deleting a mapping, so the flush here is mandatory. */
1074 sun4c_flush_page(tiaddr); 973 sun4c_flush_page(tiaddr);
1075#ifndef CONFIG_SUN4
1076 sun4c_flush_page(tiaddr + PAGE_SIZE); 974 sun4c_flush_page(tiaddr + PAGE_SIZE);
1077#endif 975
1078 sun4c_put_pte(tiaddr, 0); 976 sun4c_put_pte(tiaddr, 0);
1079#ifndef CONFIG_SUN4
1080 sun4c_put_pte(tiaddr + PAGE_SIZE, 0); 977 sun4c_put_pte(tiaddr + PAGE_SIZE, 0);
1081#endif 978
1082 sun4c_bucket[entry] = BUCKET_EMPTY; 979 sun4c_bucket[entry] = BUCKET_EMPTY;
1083 if (entry < sun4c_lowbucket_avail) 980 if (entry < sun4c_lowbucket_avail)
1084 sun4c_lowbucket_avail = entry; 981 sun4c_lowbucket_avail = entry;
@@ -1211,7 +1108,7 @@ static void sun4c_unlockarea(char *vaddr, unsigned long size)
1211 * by implication and fool the page locking code above 1108 * by implication and fool the page locking code above
1212 * if passed to by mistake. 1109 * if passed to by mistake.
1213 */ 1110 */
1214static __u32 sun4c_get_scsi_one(char *bufptr, unsigned long len, struct sbus_bus *sbus) 1111static __u32 sun4c_get_scsi_one(struct device *dev, char *bufptr, unsigned long len)
1215{ 1112{
1216 unsigned long page; 1113 unsigned long page;
1217 1114
@@ -1223,7 +1120,7 @@ static __u32 sun4c_get_scsi_one(char *bufptr, unsigned long len, struct sbus_bus
1223 return (__u32)sun4c_lockarea(bufptr, len); 1120 return (__u32)sun4c_lockarea(bufptr, len);
1224} 1121}
1225 1122
1226static void sun4c_get_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_bus *sbus) 1123static void sun4c_get_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
1227{ 1124{
1228 while (sz != 0) { 1125 while (sz != 0) {
1229 --sz; 1126 --sz;
@@ -1233,14 +1130,14 @@ static void sun4c_get_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_bus *
1233 } 1130 }
1234} 1131}
1235 1132
1236static void sun4c_release_scsi_one(__u32 bufptr, unsigned long len, struct sbus_bus *sbus) 1133static void sun4c_release_scsi_one(struct device *dev, __u32 bufptr, unsigned long len)
1237{ 1134{
1238 if (bufptr < sun4c_iobuffer_start) 1135 if (bufptr < sun4c_iobuffer_start)
1239 return; /* On kernel stack or similar, see above */ 1136 return; /* On kernel stack or similar, see above */
1240 sun4c_unlockarea((char *)bufptr, len); 1137 sun4c_unlockarea((char *)bufptr, len);
1241} 1138}
1242 1139
1243static void sun4c_release_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_bus *sbus) 1140static void sun4c_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
1244{ 1141{
1245 while (sz != 0) { 1142 while (sz != 0) {
1246 --sz; 1143 --sz;
@@ -2263,7 +2160,6 @@ void __init ld_mmu_sun4c(void)
2263 2160
2264 BTFIXUPSET_CALL(mmu_map_dma_area, sun4c_map_dma_area, BTFIXUPCALL_NORM); 2161 BTFIXUPSET_CALL(mmu_map_dma_area, sun4c_map_dma_area, BTFIXUPCALL_NORM);
2265 BTFIXUPSET_CALL(mmu_unmap_dma_area, sun4c_unmap_dma_area, BTFIXUPCALL_NORM); 2162 BTFIXUPSET_CALL(mmu_unmap_dma_area, sun4c_unmap_dma_area, BTFIXUPCALL_NORM);
2266 BTFIXUPSET_CALL(mmu_translate_dvma, sun4c_translate_dvma, BTFIXUPCALL_NORM);
2267 2163
2268 BTFIXUPSET_CALL(sparc_mapiorange, sun4c_mapiorange, BTFIXUPCALL_NORM); 2164 BTFIXUPSET_CALL(sparc_mapiorange, sun4c_mapiorange, BTFIXUPCALL_NORM);
2269 BTFIXUPSET_CALL(sparc_unmapiorange, sun4c_unmapiorange, BTFIXUPCALL_NORM); 2165 BTFIXUPSET_CALL(sparc_unmapiorange, sun4c_unmapiorange, BTFIXUPCALL_NORM);
diff --git a/arch/sparc/prom/Makefile b/arch/sparc/prom/Makefile
index 7f5eacfcfbc..8f7e18546c9 100644
--- a/arch/sparc/prom/Makefile
+++ b/arch/sparc/prom/Makefile
@@ -4,5 +4,3 @@
4 4
5lib-y := bootstr.o devmap.o devops.o init.o memory.o misc.o mp.o \ 5lib-y := bootstr.o devmap.o devops.o init.o memory.o misc.o mp.o \
6 palloc.o ranges.o segment.o console.o printf.o tree.o 6 palloc.o ranges.o segment.o console.o printf.o tree.o
7
8lib-$(CONFIG_SUN4) += sun4prom.o
diff --git a/arch/sparc/prom/bootstr.c b/arch/sparc/prom/bootstr.c
index 5a35c768ff7..916831da7e6 100644
--- a/arch/sparc/prom/bootstr.c
+++ b/arch/sparc/prom/bootstr.c
@@ -6,15 +6,12 @@
6 6
7#include <linux/string.h> 7#include <linux/string.h>
8#include <asm/oplib.h> 8#include <asm/oplib.h>
9#include <asm/sun4prom.h>
10#include <linux/init.h> 9#include <linux/init.h>
11 10
12#define BARG_LEN 256 11#define BARG_LEN 256
13static char barg_buf[BARG_LEN] = { 0 }; 12static char barg_buf[BARG_LEN] = { 0 };
14static char fetched __initdata = 0; 13static char fetched __initdata = 0;
15 14
16extern linux_sun4_romvec *sun4_romvec;
17
18char * __init 15char * __init
19prom_getbootargs(void) 16prom_getbootargs(void)
20{ 17{
@@ -28,7 +25,6 @@ prom_getbootargs(void)
28 25
29 switch(prom_vers) { 26 switch(prom_vers) {
30 case PROM_V0: 27 case PROM_V0:
31 case PROM_SUN4:
32 cp = barg_buf; 28 cp = barg_buf;
33 /* Start from 1 and go over fd(0,0,0)kernel */ 29 /* Start from 1 and go over fd(0,0,0)kernel */
34 for(iter = 1; iter < 8; iter++) { 30 for(iter = 1; iter < 8; iter++) {
diff --git a/arch/sparc/prom/console.c b/arch/sparc/prom/console.c
index 790057a3461..b3075d73fc1 100644
--- a/arch/sparc/prom/console.c
+++ b/arch/sparc/prom/console.c
@@ -10,7 +10,6 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/sched.h> 11#include <linux/sched.h>
12#include <asm/openprom.h> 12#include <asm/openprom.h>
13#include <asm/sun4prom.h>
14#include <asm/oplib.h> 13#include <asm/oplib.h>
15#include <asm/system.h> 14#include <asm/system.h>
16#include <linux/string.h> 15#include <linux/string.h>
@@ -30,7 +29,6 @@ prom_nbgetchar(void)
30 spin_lock_irqsave(&prom_lock, flags); 29 spin_lock_irqsave(&prom_lock, flags);
31 switch(prom_vers) { 30 switch(prom_vers) {
32 case PROM_V0: 31 case PROM_V0:
33 case PROM_SUN4:
34 i = (*(romvec->pv_nbgetchar))(); 32 i = (*(romvec->pv_nbgetchar))();
35 break; 33 break;
36 case PROM_V2: 34 case PROM_V2:
@@ -63,7 +61,6 @@ prom_nbputchar(char c)
63 spin_lock_irqsave(&prom_lock, flags); 61 spin_lock_irqsave(&prom_lock, flags);
64 switch(prom_vers) { 62 switch(prom_vers) {
65 case PROM_V0: 63 case PROM_V0:
66 case PROM_SUN4:
67 i = (*(romvec->pv_nbputchar))(c); 64 i = (*(romvec->pv_nbputchar))(c);
68 break; 65 break;
69 case PROM_V2: 66 case PROM_V2:
diff --git a/arch/sparc/prom/init.c b/arch/sparc/prom/init.c
index 729f8706694..873217c6d82 100644
--- a/arch/sparc/prom/init.c
+++ b/arch/sparc/prom/init.c
@@ -11,12 +11,10 @@
11 11
12#include <asm/openprom.h> 12#include <asm/openprom.h>
13#include <asm/oplib.h> 13#include <asm/oplib.h>
14#include <asm/sun4prom.h>
15 14
16struct linux_romvec *romvec; 15struct linux_romvec *romvec;
17enum prom_major_version prom_vers; 16enum prom_major_version prom_vers;
18unsigned int prom_rev, prom_prev; 17unsigned int prom_rev, prom_prev;
19linux_sun4_romvec *sun4_romvec;
20 18
21/* The root node of the prom device tree. */ 19/* The root node of the prom device tree. */
22int prom_root_node; 20int prom_root_node;
@@ -34,10 +32,6 @@ extern void prom_ranges_init(void);
34 32
35void __init prom_init(struct linux_romvec *rp) 33void __init prom_init(struct linux_romvec *rp)
36{ 34{
37#ifdef CONFIG_SUN4
38 extern struct linux_romvec *sun4_prom_init(void);
39 rp = sun4_prom_init();
40#endif
41 romvec = rp; 35 romvec = rp;
42 36
43 switch(romvec->pv_romvers) { 37 switch(romvec->pv_romvers) {
@@ -50,9 +44,6 @@ void __init prom_init(struct linux_romvec *rp)
50 case 3: 44 case 3:
51 prom_vers = PROM_V3; 45 prom_vers = PROM_V3;
52 break; 46 break;
53 case 40:
54 prom_vers = PROM_SUN4;
55 break;
56 default: 47 default:
57 prom_printf("PROMLIB: Bad PROM version %d\n", 48 prom_printf("PROMLIB: Bad PROM version %d\n",
58 romvec->pv_romvers); 49 romvec->pv_romvers);
@@ -76,11 +67,8 @@ void __init prom_init(struct linux_romvec *rp)
76 67
77 prom_ranges_init(); 68 prom_ranges_init();
78 69
79#ifndef CONFIG_SUN4
80 /* SUN4 prints this in sun4_prom_init */
81 printk("PROMLIB: Sun Boot Prom Version %d Revision %d\n", 70 printk("PROMLIB: Sun Boot Prom Version %d Revision %d\n",
82 romvec->pv_romvers, prom_rev); 71 romvec->pv_romvers, prom_rev);
83#endif
84 72
85 /* Initialization successful. */ 73 /* Initialization successful. */
86 return; 74 return;
diff --git a/arch/sparc/prom/memory.c b/arch/sparc/prom/memory.c
index 947f047dc95..fac7899a29c 100644
--- a/arch/sparc/prom/memory.c
+++ b/arch/sparc/prom/memory.c
@@ -10,7 +10,6 @@
10#include <linux/init.h> 10#include <linux/init.h>
11 11
12#include <asm/openprom.h> 12#include <asm/openprom.h>
13#include <asm/sun4prom.h>
14#include <asm/oplib.h> 13#include <asm/oplib.h>
15#include <asm/page.h> 14#include <asm/page.h>
16 15
@@ -46,15 +45,6 @@ static int __init prom_meminit_v2(void)
46 return num_ents; 45 return num_ents;
47} 46}
48 47
49static int __init prom_meminit_sun4(void)
50{
51#ifdef CONFIG_SUN4
52 sp_banks[0].base_addr = 0;
53 sp_banks[0].num_bytes = *(sun4_romvec->memoryavail);
54#endif
55 return 1;
56}
57
58static int sp_banks_cmp(const void *a, const void *b) 48static int sp_banks_cmp(const void *a, const void *b)
59{ 49{
60 const struct sparc_phys_banks *x = a, *y = b; 50 const struct sparc_phys_banks *x = a, *y = b;
@@ -81,10 +71,6 @@ void __init prom_meminit(void)
81 num_ents = prom_meminit_v2(); 71 num_ents = prom_meminit_v2();
82 break; 72 break;
83 73
84 case PROM_SUN4:
85 num_ents = prom_meminit_sun4();
86 break;
87
88 default: 74 default:
89 break; 75 break;
90 } 76 }
diff --git a/arch/sparc/prom/ranges.c b/arch/sparc/prom/ranges.c
index f9b7def35f6..64579a37641 100644
--- a/arch/sparc/prom/ranges.c
+++ b/arch/sparc/prom/ranges.c
@@ -9,7 +9,6 @@
9#include <asm/openprom.h> 9#include <asm/openprom.h>
10#include <asm/oplib.h> 10#include <asm/oplib.h>
11#include <asm/types.h> 11#include <asm/types.h>
12#include <asm/sbus.h>
13#include <asm/system.h> 12#include <asm/system.h>
14 13
15struct linux_prom_ranges promlib_obio_ranges[PROMREG_MAX]; 14struct linux_prom_ranges promlib_obio_ranges[PROMREG_MAX];
diff --git a/arch/sparc/prom/sun4prom.c b/arch/sparc/prom/sun4prom.c
deleted file mode 100644
index 00390a2652a..00000000000
--- a/arch/sparc/prom/sun4prom.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/*
2 * Copyright (C) 1996 The Australian National University.
3 * Copyright (C) 1996 Fujitsu Laboratories Limited
4 * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
5 * Copyright (C) 1997 Sun Weenie (ko@ko.reno.nv.us)
6 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 *
8 * This software may be distributed under the terms of the Gnu
9 * Public License version 2 or later
10 *
11 * fake a really simple Sun prom for the SUN4
12 */
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <asm/oplib.h>
17#include <asm/idprom.h>
18#include <asm/machines.h>
19#include <asm/sun4prom.h>
20#include <asm/asi.h>
21#include <asm/contregs.h>
22#include <linux/init.h>
23
24static struct linux_romvec sun4romvec;
25static struct idprom sun4_idprom;
26
27struct property {
28 char *name;
29 char *value;
30 int length;
31};
32
33struct node {
34 int level;
35 struct property *properties;
36};
37
38struct property null_properties = { NULL, NULL, -1 };
39
40struct property root_properties[] = {
41 {"device_type", "cpu", 4},
42 {"idprom", (char *)&sun4_idprom, sizeof(struct idprom)},
43 {NULL, NULL, -1}
44};
45
46struct node nodes[] = {
47 { 0, &null_properties },
48 { 0, root_properties },
49 { -1,&null_properties }
50};
51
52
53static int no_nextnode(int node)
54{
55 if (nodes[node].level == nodes[node+1].level)
56 return node+1;
57 return -1;
58}
59
60static int no_child(int node)
61{
62 if (nodes[node].level == nodes[node+1].level-1)
63 return node+1;
64 return -1;
65}
66
67static struct property *find_property(int node,char *name)
68{
69 struct property *prop = &nodes[node].properties[0];
70 while (prop && prop->name) {
71 if (strcmp(prop->name,name) == 0) return prop;
72 prop++;
73 }
74 return NULL;
75}
76
77static int no_proplen(int node,char *name)
78{
79 struct property *prop = find_property(node,name);
80 if (prop) return prop->length;
81 return -1;
82}
83
84static int no_getprop(int node,char *name,char *value)
85{
86 struct property *prop = find_property(node,name);
87 if (prop) {
88 memcpy(value,prop->value,prop->length);
89 return 1;
90 }
91 return -1;
92}
93
94static int no_setprop(int node,char *name,char *value,int len)
95{
96 return -1;
97}
98
99static char *no_nextprop(int node,char *name)
100{
101 struct property *prop = find_property(node,name);
102 if (prop) return prop[1].name;
103 return NULL;
104}
105
106static struct linux_nodeops sun4_nodeops = {
107 no_nextnode,
108 no_child,
109 no_proplen,
110 no_getprop,
111 no_setprop,
112 no_nextprop
113};
114
115static int synch_hook;
116
117struct linux_romvec * __init sun4_prom_init(void)
118{
119 int i;
120 unsigned char x;
121 char *p;
122
123 p = (char *)&sun4_idprom;
124 for (i = 0; i < sizeof(sun4_idprom); i++) {
125 __asm__ __volatile__ ("lduba [%1] %2, %0" : "=r" (x) :
126 "r" (AC_IDPROM + i), "i" (ASI_CONTROL));
127 *p++ = x;
128 }
129
130 memset(&sun4romvec,0,sizeof(sun4romvec));
131
132 sun4_romvec = (linux_sun4_romvec *) SUN4_PROM_VECTOR;
133
134 sun4romvec.pv_romvers = 40;
135 sun4romvec.pv_nodeops = &sun4_nodeops;
136 sun4romvec.pv_reboot = sun4_romvec->reboot;
137 sun4romvec.pv_abort = sun4_romvec->abortentry;
138 sun4romvec.pv_halt = sun4_romvec->exittomon;
139 sun4romvec.pv_synchook = (void (**)(void))&synch_hook;
140 sun4romvec.pv_setctxt = sun4_romvec->setcxsegmap;
141 sun4romvec.pv_v0bootargs = sun4_romvec->bootParam;
142 sun4romvec.pv_nbgetchar = sun4_romvec->mayget;
143 sun4romvec.pv_nbputchar = sun4_romvec->mayput;
144 sun4romvec.pv_stdin = sun4_romvec->insource;
145 sun4romvec.pv_stdout = sun4_romvec->outsink;
146
147 /*
148 * We turn on the LEDs to let folks without monitors or
149 * terminals know we booted. Nothing too fancy now. They
150 * are all on, except for LED 5, which blinks. When we
151 * have more time, we can teach the penguin to say "By your
152 * command" or "Activating turbo boost, Michael". :-)
153 */
154 sun4_romvec->setLEDs(NULL);
155
156 printk("PROMLIB: Old Sun4 boot PROM monitor %s, romvec version %d\n",
157 sun4_romvec->monid,
158 sun4_romvec->romvecversion);
159
160 return &sun4romvec;
161}
diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig
index 36b4b7ab9cf..5446e2a499b 100644
--- a/arch/sparc64/Kconfig
+++ b/arch/sparc64/Kconfig
@@ -18,6 +18,13 @@ config SPARC64
18 select HAVE_ARCH_KGDB 18 select HAVE_ARCH_KGDB
19 select USE_GENERIC_SMP_HELPERS if SMP 19 select USE_GENERIC_SMP_HELPERS if SMP
20 select HAVE_ARCH_TRACEHOOK 20 select HAVE_ARCH_TRACEHOOK
21 select ARCH_WANT_OPTIONAL_GPIOLIB
22 select RTC_CLASS
23 select RTC_DRV_M48T59
24 select RTC_DRV_CMOS
25 select RTC_DRV_BQ4802
26 select RTC_DRV_SUN4V
27 select RTC_DRV_STARFIRE
21 28
22config GENERIC_TIME 29config GENERIC_TIME
23 bool 30 bool
@@ -31,6 +38,11 @@ config GENERIC_CLOCKEVENTS
31 bool 38 bool
32 default y 39 default y
33 40
41config GENERIC_GPIO
42 bool
43 help
44 Generic GPIO API support
45
34config 64BIT 46config 64BIT
35 def_bool y 47 def_bool y
36 48
@@ -185,6 +197,17 @@ config US2E_FREQ
185 197
186 If in doubt, say N. 198 If in doubt, say N.
187 199
200config US3_MC
201 tristate "UltraSPARC-III Memory Controller driver"
202 default y
203 help
204 This adds a driver for the UltraSPARC-III memory controller.
205 Loading this driver allows exact mnemonic strings to be
206 printed in the event of a memory error, so that the faulty DIMM
207 on the motherboard can be matched to the error.
208
209 If in doubt, say Y, as this information can be very useful.
210
188# Global things across all Sun machines. 211# Global things across all Sun machines.
189config GENERIC_LOCKBREAK 212config GENERIC_LOCKBREAK
190 bool 213 bool
diff --git a/arch/sparc64/Makefile b/arch/sparc64/Makefile
index b785a395b12..c7214abc0d8 100644
--- a/arch/sparc64/Makefile
+++ b/arch/sparc64/Makefile
@@ -7,7 +7,7 @@
7# Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) 7# Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
8# 8#
9 9
10CHECKFLAGS += -D__sparc__ -D__sparc_v9__ -m64 10CHECKFLAGS += -D__sparc__ -D__sparc_v9__ -D__arch64__ -m64
11 11
12# Undefine sparc when processing vmlinux.lds - it is used 12# Undefine sparc when processing vmlinux.lds - it is used
13# And teach CPP we are doing 64 bit builds (for this case) 13# And teach CPP we are doing 64 bit builds (for this case)
diff --git a/arch/sparc64/kernel/Makefile b/arch/sparc64/kernel/Makefile
index 418b5782096..c0b8009ab19 100644
--- a/arch/sparc64/kernel/Makefile
+++ b/arch/sparc64/kernel/Makefile
@@ -7,16 +7,16 @@ EXTRA_CFLAGS := -Werror
7 7
8extra-y := head.o init_task.o vmlinux.lds 8extra-y := head.o init_task.o vmlinux.lds
9 9
10obj-y := process.o setup.o cpu.o idprom.o \ 10obj-y := process.o setup.o cpu.o idprom.o reboot.o \
11 traps.o auxio.o una_asm.o sysfs.o iommu.o \ 11 traps.o auxio.o una_asm.o sysfs.o iommu.o \
12 irq.o ptrace.o time.o sys_sparc.o signal.o \ 12 irq.o ptrace.o time.o sys_sparc.o signal.o \
13 unaligned.o central.o pci.o starfire.o \ 13 unaligned.o central.o starfire.o \
14 power.o sbus.o sparc64_ksyms.o chmc.o \ 14 power.o sbus.o sparc64_ksyms.o ebus.o \
15 visemul.o prom.o of_device.o hvapi.o sstate.o mdesc.o 15 visemul.o prom.o of_device.o hvapi.o sstate.o mdesc.o
16 16
17obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 17obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
18obj-$(CONFIG_STACKTRACE) += stacktrace.o 18obj-$(CONFIG_STACKTRACE) += stacktrace.o
19obj-$(CONFIG_PCI) += ebus.o pci_common.o \ 19obj-$(CONFIG_PCI) += pci.o pci_common.o psycho_common.o \
20 pci_psycho.o pci_sabre.o pci_schizo.o \ 20 pci_psycho.o pci_sabre.o pci_schizo.o \
21 pci_sun4v.o pci_sun4v_asm.o pci_fire.o 21 pci_sun4v.o pci_sun4v_asm.o pci_fire.o
22obj-$(CONFIG_PCI_MSI) += pci_msi.o 22obj-$(CONFIG_PCI_MSI) += pci_msi.o
@@ -25,6 +25,7 @@ obj-$(CONFIG_COMPAT) += sys32.o sys_sparc32.o signal32.o
25obj-$(CONFIG_MODULES) += module.o 25obj-$(CONFIG_MODULES) += module.o
26obj-$(CONFIG_US3_FREQ) += us3_cpufreq.o 26obj-$(CONFIG_US3_FREQ) += us3_cpufreq.o
27obj-$(CONFIG_US2E_FREQ) += us2e_cpufreq.o 27obj-$(CONFIG_US2E_FREQ) += us2e_cpufreq.o
28obj-$(CONFIG_US3_MC) += chmc.o
28obj-$(CONFIG_KPROBES) += kprobes.o 29obj-$(CONFIG_KPROBES) += kprobes.o
29obj-$(CONFIG_SUN_LDOMS) += ldc.o vio.o viohs.o ds.o 30obj-$(CONFIG_SUN_LDOMS) += ldc.o vio.o viohs.o ds.o
30obj-$(CONFIG_AUDIT) += audit.o 31obj-$(CONFIG_AUDIT) += audit.o
diff --git a/arch/sparc64/kernel/auxio.c b/arch/sparc64/kernel/auxio.c
index dd5c7bf8761..858beda8652 100644
--- a/arch/sparc64/kernel/auxio.c
+++ b/arch/sparc64/kernel/auxio.c
@@ -109,7 +109,7 @@ void auxio_set_lte(int on)
109 } 109 }
110} 110}
111 111
112static struct of_device_id auxio_match[] = { 112static struct of_device_id __initdata auxio_match[] = {
113 { 113 {
114 .name = "auxio", 114 .name = "auxio",
115 }, 115 },
diff --git a/arch/sparc64/kernel/central.c b/arch/sparc64/kernel/central.c
index f2e87d0d7e1..05f1c916db0 100644
--- a/arch/sparc64/kernel/central.c
+++ b/arch/sparc64/kernel/central.c
@@ -1,461 +1,268 @@
1/* central.c: Central FHC driver for Sunfire/Starfire/Wildfire. 1/* central.c: Central FHC driver for Sunfire/Starfire/Wildfire.
2 * 2 *
3 * Copyright (C) 1997, 1999 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 1997, 1999, 2008 David S. Miller (davem@davemloft.net)
4 */ 4 */
5 5
6#include <linux/kernel.h> 6#include <linux/kernel.h>
7#include <linux/types.h> 7#include <linux/types.h>
8#include <linux/string.h> 8#include <linux/string.h>
9#include <linux/timer.h>
10#include <linux/sched.h>
11#include <linux/delay.h>
12#include <linux/init.h> 9#include <linux/init.h>
13#include <linux/bootmem.h> 10#include <linux/of_device.h>
11#include <linux/platform_device.h>
14 12
15#include <asm/page.h>
16#include <asm/fhc.h> 13#include <asm/fhc.h>
17#include <asm/starfire.h> 14#include <asm/upa.h>
18 15
19static struct linux_central *central_bus = NULL; 16struct clock_board {
20static struct linux_fhc *fhc_list = NULL; 17 void __iomem *clock_freq_regs;
18 void __iomem *clock_regs;
19 void __iomem *clock_ver_reg;
20 int num_slots;
21 struct resource leds_resource;
22 struct platform_device leds_pdev;
23};
24
25struct fhc {
26 void __iomem *pregs;
27 bool central;
28 bool jtag_master;
29 int board_num;
30 struct resource leds_resource;
31 struct platform_device leds_pdev;
32};
33
34static int __devinit clock_board_calc_nslots(struct clock_board *p)
35{
36 u8 reg = upa_readb(p->clock_regs + CLOCK_STAT1) & 0xc0;
21 37
22#define IS_CENTRAL_FHC(__fhc) ((__fhc) == central_bus->child) 38 switch (reg) {
39 case 0x40:
40 return 16;
23 41
24static void central_probe_failure(int line) 42 case 0xc0:
25{ 43 return 8;
26 prom_printf("CENTRAL: Critical device probe failure at central.c:%d\n",
27 line);
28 prom_halt();
29}
30 44
31static void central_ranges_init(struct linux_central *central) 45 case 0x80:
32{ 46 reg = 0;
33 struct device_node *dp = central->prom_node; 47 if (p->clock_ver_reg)
34 const void *pval; 48 reg = upa_readb(p->clock_ver_reg);
35 int len; 49 if (reg) {
36 50 if (reg & 0x80)
37 central->num_central_ranges = 0; 51 return 4;
38 pval = of_get_property(dp, "ranges", &len); 52 else
39 if (pval) { 53 return 5;
40 memcpy(central->central_ranges, pval, len); 54 }
41 central->num_central_ranges = 55 /* Fallthrough */
42 (len / sizeof(struct linux_prom_ranges)); 56 default:
57 return 4;
43 } 58 }
44} 59}
45 60
46static void fhc_ranges_init(struct linux_fhc *fhc) 61static int __devinit clock_board_probe(struct of_device *op,
62 const struct of_device_id *match)
47{ 63{
48 struct device_node *dp = fhc->prom_node; 64 struct clock_board *p = kzalloc(sizeof(*p), GFP_KERNEL);
49 const void *pval; 65 int err = -ENOMEM;
50 int len;
51
52 fhc->num_fhc_ranges = 0;
53 pval = of_get_property(dp, "ranges", &len);
54 if (pval) {
55 memcpy(fhc->fhc_ranges, pval, len);
56 fhc->num_fhc_ranges =
57 (len / sizeof(struct linux_prom_ranges));
58 }
59}
60 66
61/* Range application routines are exported to various drivers, 67 if (!p) {
62 * so do not __init this. 68 printk(KERN_ERR "clock_board: Cannot allocate struct clock_board\n");
63 */ 69 goto out;
64static void adjust_regs(struct linux_prom_registers *regp, int nregs,
65 struct linux_prom_ranges *rangep, int nranges)
66{
67 int regc, rngc;
68
69 for (regc = 0; regc < nregs; regc++) {
70 for (rngc = 0; rngc < nranges; rngc++)
71 if (regp[regc].which_io == rangep[rngc].ot_child_space)
72 break; /* Fount it */
73 if (rngc == nranges) /* oops */
74 central_probe_failure(__LINE__);
75 regp[regc].which_io = rangep[rngc].ot_parent_space;
76 regp[regc].phys_addr -= rangep[rngc].ot_child_base;
77 regp[regc].phys_addr += rangep[rngc].ot_parent_base;
78 } 70 }
79}
80 71
81/* Apply probed fhc ranges to registers passed, if no ranges return. */ 72 p->clock_freq_regs = of_ioremap(&op->resource[0], 0,
82static void apply_fhc_ranges(struct linux_fhc *fhc, 73 resource_size(&op->resource[0]),
83 struct linux_prom_registers *regs, 74 "clock_board_freq");
84 int nregs) 75 if (!p->clock_freq_regs) {
85{ 76 printk(KERN_ERR "clock_board: Cannot map clock_freq_regs\n");
86 if (fhc->num_fhc_ranges) 77 goto out_free;
87 adjust_regs(regs, nregs, fhc->fhc_ranges, 78 }
88 fhc->num_fhc_ranges);
89}
90 79
91/* Apply probed central ranges to registers passed, if no ranges return. */ 80 p->clock_regs = of_ioremap(&op->resource[1], 0,
92static void apply_central_ranges(struct linux_central *central, 81 resource_size(&op->resource[1]),
93 struct linux_prom_registers *regs, int nregs) 82 "clock_board_regs");
94{ 83 if (!p->clock_regs) {
95 if (central->num_central_ranges) 84 printk(KERN_ERR "clock_board: Cannot map clock_regs\n");
96 adjust_regs(regs, nregs, central->central_ranges, 85 goto out_unmap_clock_freq_regs;
97 central->num_central_ranges); 86 }
98}
99 87
100static void * __init central_alloc_bootmem(unsigned long size) 88 if (op->resource[2].flags) {
101{ 89 p->clock_ver_reg = of_ioremap(&op->resource[2], 0,
102 void *ret; 90 resource_size(&op->resource[2]),
91 "clock_ver_reg");
92 if (!p->clock_ver_reg) {
93 printk(KERN_ERR "clock_board: Cannot map clock_ver_reg\n");
94 goto out_unmap_clock_regs;
95 }
96 }
103 97
104 ret = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL); 98 p->num_slots = clock_board_calc_nslots(p);
105 if (ret != NULL)
106 memset(ret, 0, size);
107 99
108 return ret; 100 p->leds_resource.start = (unsigned long)
109} 101 (p->clock_regs + CLOCK_CTRL);
102 p->leds_resource.end = p->leds_resource.end;
103 p->leds_resource.name = "leds";
110 104
111static unsigned long prom_reg_to_paddr(struct linux_prom_registers *r) 105 p->leds_pdev.name = "sunfire-clockboard-leds";
112{ 106 p->leds_pdev.resource = &p->leds_resource;
113 unsigned long ret = ((unsigned long) r->which_io) << 32; 107 p->leds_pdev.num_resources = 1;
108 p->leds_pdev.dev.parent = &op->dev;
114 109
115 return ret | (unsigned long) r->phys_addr; 110 err = platform_device_register(&p->leds_pdev);
116} 111 if (err) {
117 112 printk(KERN_ERR "clock_board: Could not register LEDS "
118static void __init probe_other_fhcs(void) 113 "platform device\n");
119{ 114 goto out_unmap_clock_ver_reg;
120 struct device_node *dp;
121 const struct linux_prom64_registers *fpregs;
122
123 for_each_node_by_name(dp, "fhc") {
124 struct linux_fhc *fhc;
125 int board;
126 u32 tmp;
127
128 if (dp->parent &&
129 dp->parent->parent != NULL)
130 continue;
131
132 fhc = (struct linux_fhc *)
133 central_alloc_bootmem(sizeof(struct linux_fhc));
134 if (fhc == NULL)
135 central_probe_failure(__LINE__);
136
137 /* Link it into the FHC chain. */
138 fhc->next = fhc_list;
139 fhc_list = fhc;
140
141 /* Toplevel FHCs have no parent. */
142 fhc->parent = NULL;
143
144 fhc->prom_node = dp;
145 fhc_ranges_init(fhc);
146
147 /* Non-central FHC's have 64-bit OBP format registers. */
148 fpregs = of_get_property(dp, "reg", NULL);
149 if (!fpregs)
150 central_probe_failure(__LINE__);
151
152 /* Only central FHC needs special ranges applied. */
153 fhc->fhc_regs.pregs = fpregs[0].phys_addr;
154 fhc->fhc_regs.ireg = fpregs[1].phys_addr;
155 fhc->fhc_regs.ffregs = fpregs[2].phys_addr;
156 fhc->fhc_regs.sregs = fpregs[3].phys_addr;
157 fhc->fhc_regs.uregs = fpregs[4].phys_addr;
158 fhc->fhc_regs.tregs = fpregs[5].phys_addr;
159
160 board = of_getintprop_default(dp, "board#", -1);
161 fhc->board = board;
162
163 tmp = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_JCTRL);
164 if ((tmp & FHC_JTAG_CTRL_MENAB) != 0)
165 fhc->jtag_master = 1;
166 else
167 fhc->jtag_master = 0;
168
169 tmp = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_ID);
170 printk("FHC(board %d): Version[%x] PartID[%x] Manuf[%x] %s\n",
171 board,
172 (tmp & FHC_ID_VERS) >> 28,
173 (tmp & FHC_ID_PARTID) >> 12,
174 (tmp & FHC_ID_MANUF) >> 1,
175 (fhc->jtag_master ? "(JTAG Master)" : ""));
176
177 /* This bit must be set in all non-central FHC's in
178 * the system. When it is clear, this identifies
179 * the central board.
180 */
181 tmp = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
182 tmp |= FHC_CONTROL_IXIST;
183 upa_writel(tmp, fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
184 } 115 }
185}
186 116
187static void probe_clock_board(struct linux_central *central, 117 printk(KERN_INFO "clock_board: Detected %d slot Enterprise system.\n",
188 struct linux_fhc *fhc, 118 p->num_slots);
189 struct device_node *fp)
190{
191 struct device_node *dp;
192 struct linux_prom_registers cregs[3];
193 const struct linux_prom_registers *pr;
194 int nslots, tmp, nregs;
195
196 dp = fp->child;
197 while (dp) {
198 if (!strcmp(dp->name, "clock-board"))
199 break;
200 dp = dp->sibling;
201 }
202 if (!dp)
203 central_probe_failure(__LINE__);
204 119
205 pr = of_get_property(dp, "reg", &nregs); 120 err = 0;
206 if (!pr) 121out:
207 central_probe_failure(__LINE__); 122 return err;
208 123
209 memcpy(cregs, pr, nregs); 124out_unmap_clock_ver_reg:
210 nregs /= sizeof(struct linux_prom_registers); 125 if (p->clock_ver_reg)
126 of_iounmap(&op->resource[2], p->clock_ver_reg,
127 resource_size(&op->resource[2]));
211 128
212 apply_fhc_ranges(fhc, &cregs[0], nregs); 129out_unmap_clock_regs:
213 apply_central_ranges(central, &cregs[0], nregs); 130 of_iounmap(&op->resource[1], p->clock_regs,
214 central->cfreg = prom_reg_to_paddr(&cregs[0]); 131 resource_size(&op->resource[1]));
215 central->clkregs = prom_reg_to_paddr(&cregs[1]);
216 132
217 if (nregs == 2) 133out_unmap_clock_freq_regs:
218 central->clkver = 0UL; 134 of_iounmap(&op->resource[0], p->clock_freq_regs,
219 else 135 resource_size(&op->resource[0]));
220 central->clkver = prom_reg_to_paddr(&cregs[2]);
221 136
222 tmp = upa_readb(central->clkregs + CLOCK_STAT1); 137out_free:
223 tmp &= 0xc0; 138 kfree(p);
224 switch(tmp) { 139 goto out;
225 case 0x40:
226 nslots = 16;
227 break;
228 case 0xc0:
229 nslots = 8;
230 break;
231 case 0x80:
232 if (central->clkver != 0UL &&
233 upa_readb(central->clkver) != 0) {
234 if ((upa_readb(central->clkver) & 0x80) != 0)
235 nslots = 4;
236 else
237 nslots = 5;
238 break;
239 }
240 default:
241 nslots = 4;
242 break;
243 };
244 central->slots = nslots;
245 printk("CENTRAL: Detected %d slot Enterprise system. cfreg[%02x] cver[%02x]\n",
246 central->slots, upa_readb(central->cfreg),
247 (central->clkver ? upa_readb(central->clkver) : 0x00));
248} 140}
249 141
250static void ZAP(unsigned long iclr, unsigned long imap) 142static struct of_device_id __initdata clock_board_match[] = {
143 {
144 .name = "clock-board",
145 },
146 {},
147};
148
149static struct of_platform_driver clock_board_driver = {
150 .match_table = clock_board_match,
151 .probe = clock_board_probe,
152 .driver = {
153 .name = "clock_board",
154 },
155};
156
157static int __devinit fhc_probe(struct of_device *op,
158 const struct of_device_id *match)
251{ 159{
252 u32 imap_tmp; 160 struct fhc *p = kzalloc(sizeof(*p), GFP_KERNEL);
253 161 int err = -ENOMEM;
254 upa_writel(0, iclr); 162 u32 reg;
255 upa_readl(iclr);
256 imap_tmp = upa_readl(imap);
257 imap_tmp &= ~(0x80000000);
258 upa_writel(imap_tmp, imap);
259 upa_readl(imap);
260}
261 163
262static void init_all_fhc_hw(void) 164 if (!p) {
263{ 165 printk(KERN_ERR "fhc: Cannot allocate struct fhc\n");
264 struct linux_fhc *fhc; 166 goto out;
265
266 for (fhc = fhc_list; fhc != NULL; fhc = fhc->next) {
267 u32 tmp;
268
269 /* Clear all of the interrupt mapping registers
270 * just in case OBP left them in a foul state.
271 */
272 ZAP(fhc->fhc_regs.ffregs + FHC_FFREGS_ICLR,
273 fhc->fhc_regs.ffregs + FHC_FFREGS_IMAP);
274 ZAP(fhc->fhc_regs.sregs + FHC_SREGS_ICLR,
275 fhc->fhc_regs.sregs + FHC_SREGS_IMAP);
276 ZAP(fhc->fhc_regs.uregs + FHC_UREGS_ICLR,
277 fhc->fhc_regs.uregs + FHC_UREGS_IMAP);
278 ZAP(fhc->fhc_regs.tregs + FHC_TREGS_ICLR,
279 fhc->fhc_regs.tregs + FHC_TREGS_IMAP);
280
281 /* Setup FHC control register. */
282 tmp = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
283
284 /* All non-central boards have this bit set. */
285 if (! IS_CENTRAL_FHC(fhc))
286 tmp |= FHC_CONTROL_IXIST;
287
288 /* For all FHCs, clear the firmware synchronization
289 * line and both low power mode enables.
290 */
291 tmp &= ~(FHC_CONTROL_AOFF | FHC_CONTROL_BOFF |
292 FHC_CONTROL_SLINE);
293
294 upa_writel(tmp, fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
295 upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
296 } 167 }
297 168
298} 169 if (!strcmp(op->node->parent->name, "central"))
170 p->central = true;
299 171
300void __init central_probe(void) 172 p->pregs = of_ioremap(&op->resource[0], 0,
301{ 173 resource_size(&op->resource[0]),
302 struct linux_prom_registers fpregs[6]; 174 "fhc_pregs");
303 const struct linux_prom_registers *pr; 175 if (!p->pregs) {
304 struct linux_fhc *fhc; 176 printk(KERN_ERR "fhc: Cannot map pregs\n");
305 struct device_node *dp, *fp; 177 goto out_free;
306 int err;
307
308 dp = of_find_node_by_name(NULL, "central");
309 if (!dp) {
310 if (this_is_starfire)
311 starfire_cpu_setup();
312 return;
313 } 178 }
314 179
315 /* Ok we got one, grab some memory for software state. */ 180 if (p->central) {
316 central_bus = (struct linux_central *) 181 reg = upa_readl(p->pregs + FHC_PREGS_BSR);
317 central_alloc_bootmem(sizeof(struct linux_central)); 182 p->board_num = ((reg >> 16) & 1) | ((reg >> 12) & 0x0e);
318 if (central_bus == NULL) 183 } else {
319 central_probe_failure(__LINE__); 184 p->board_num = of_getintprop_default(op->node, "board#", -1);
320 185 if (p->board_num == -1) {
321 fhc = (struct linux_fhc *) 186 printk(KERN_ERR "fhc: No board# property\n");
322 central_alloc_bootmem(sizeof(struct linux_fhc)); 187 goto out_unmap_pregs;
323 if (fhc == NULL) 188 }
324 central_probe_failure(__LINE__); 189 if (upa_readl(p->pregs + FHC_PREGS_JCTRL) & FHC_JTAG_CTRL_MENAB)
325 190 p->jtag_master = true;
326 /* First init central. */
327 central_bus->child = fhc;
328 central_bus->prom_node = dp;
329 central_ranges_init(central_bus);
330
331 /* And then central's FHC. */
332 fhc->next = fhc_list;
333 fhc_list = fhc;
334
335 fhc->parent = central_bus;
336 fp = dp->child;
337 while (fp) {
338 if (!strcmp(fp->name, "fhc"))
339 break;
340 fp = fp->sibling;
341 } 191 }
342 if (!fp)
343 central_probe_failure(__LINE__);
344
345 fhc->prom_node = fp;
346 fhc_ranges_init(fhc);
347
348 /* Now, map in FHC register set. */
349 pr = of_get_property(fp, "reg", NULL);
350 if (!pr)
351 central_probe_failure(__LINE__);
352 memcpy(fpregs, pr, sizeof(fpregs));
353
354 apply_central_ranges(central_bus, &fpregs[0], 6);
355
356 fhc->fhc_regs.pregs = prom_reg_to_paddr(&fpregs[0]);
357 fhc->fhc_regs.ireg = prom_reg_to_paddr(&fpregs[1]);
358 fhc->fhc_regs.ffregs = prom_reg_to_paddr(&fpregs[2]);
359 fhc->fhc_regs.sregs = prom_reg_to_paddr(&fpregs[3]);
360 fhc->fhc_regs.uregs = prom_reg_to_paddr(&fpregs[4]);
361 fhc->fhc_regs.tregs = prom_reg_to_paddr(&fpregs[5]);
362
363 /* Obtain board number from board status register, Central's
364 * FHC lacks "board#" property.
365 */
366 err = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_BSR);
367 fhc->board = (((err >> 16) & 0x01) |
368 ((err >> 12) & 0x0e));
369
370 fhc->jtag_master = 0;
371
372 /* Attach the clock board registers for CENTRAL. */
373 probe_clock_board(central_bus, fhc, fp);
374
375 err = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_ID);
376 printk("FHC(board %d): Version[%x] PartID[%x] Manuf[%x] (CENTRAL)\n",
377 fhc->board,
378 ((err & FHC_ID_VERS) >> 28),
379 ((err & FHC_ID_PARTID) >> 12),
380 ((err & FHC_ID_MANUF) >> 1));
381
382 probe_other_fhcs();
383
384 init_all_fhc_hw();
385}
386 192
387static inline void fhc_ledblink(struct linux_fhc *fhc, int on) 193 if (!p->central) {
388{ 194 p->leds_resource.start = (unsigned long)
389 u32 tmp; 195 (p->pregs + FHC_PREGS_CTRL);
196 p->leds_resource.end = p->leds_resource.end;
197 p->leds_resource.name = "leds";
198
199 p->leds_pdev.name = "sunfire-fhc-leds";
200 p->leds_pdev.resource = &p->leds_resource;
201 p->leds_pdev.num_resources = 1;
202 p->leds_pdev.dev.parent = &op->dev;
203
204 err = platform_device_register(&p->leds_pdev);
205 if (err) {
206 printk(KERN_ERR "fhc: Could not register LEDS "
207 "platform device\n");
208 goto out_unmap_pregs;
209 }
210 }
211 reg = upa_readl(p->pregs + FHC_PREGS_CTRL);
390 212
391 tmp = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL); 213 if (!p->central)
214 reg |= FHC_CONTROL_IXIST;
392 215
393 /* NOTE: reverse logic on this bit */ 216 reg &= ~(FHC_CONTROL_AOFF |
394 if (on) 217 FHC_CONTROL_BOFF |
395 tmp &= ~(FHC_CONTROL_RLED); 218 FHC_CONTROL_SLINE);
396 else
397 tmp |= FHC_CONTROL_RLED;
398 tmp &= ~(FHC_CONTROL_AOFF | FHC_CONTROL_BOFF | FHC_CONTROL_SLINE);
399 219
400 upa_writel(tmp, fhc->fhc_regs.pregs + FHC_PREGS_CTRL); 220 upa_writel(reg, p->pregs + FHC_PREGS_CTRL);
401 upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL); 221 upa_readl(p->pregs + FHC_PREGS_CTRL);
402}
403 222
404static inline void central_ledblink(struct linux_central *central, int on) 223 reg = upa_readl(p->pregs + FHC_PREGS_ID);
405{ 224 printk(KERN_INFO "fhc: Board #%d, Version[%x] PartID[%x] Manuf[%x] %s\n",
406 u8 tmp; 225 p->board_num,
407 226 (reg & FHC_ID_VERS) >> 28,
408 tmp = upa_readb(central->clkregs + CLOCK_CTRL); 227 (reg & FHC_ID_PARTID) >> 12,
228 (reg & FHC_ID_MANUF) >> 1,
229 (p->jtag_master ?
230 "(JTAG Master)" :
231 (p->central ? "(Central)" : "")));
409 232
410 /* NOTE: reverse logic on this bit */ 233 err = 0;
411 if (on)
412 tmp &= ~(CLOCK_CTRL_RLED);
413 else
414 tmp |= CLOCK_CTRL_RLED;
415 234
416 upa_writeb(tmp, central->clkregs + CLOCK_CTRL); 235out:
417 upa_readb(central->clkregs + CLOCK_CTRL); 236 return err;
418}
419 237
420static struct timer_list sftimer; 238out_unmap_pregs:
421static int led_state; 239 of_iounmap(&op->resource[0], p->pregs, resource_size(&op->resource[0]));
422 240
423static void sunfire_timer(unsigned long __ignored) 241out_free:
424{ 242 kfree(p);
425 struct linux_fhc *fhc; 243 goto out;
426
427 central_ledblink(central_bus, led_state);
428 for (fhc = fhc_list; fhc != NULL; fhc = fhc->next)
429 if (! IS_CENTRAL_FHC(fhc))
430 fhc_ledblink(fhc, led_state);
431 led_state = ! led_state;
432 sftimer.expires = jiffies + (HZ >> 1);
433 add_timer(&sftimer);
434} 244}
435 245
436/* After PCI/SBUS busses have been probed, this is called to perform 246static struct of_device_id __initdata fhc_match[] = {
437 * final initialization of all FireHose Controllers in the system. 247 {
438 */ 248 .name = "fhc",
439void firetruck_init(void) 249 },
250 {},
251};
252
253static struct of_platform_driver fhc_driver = {
254 .match_table = fhc_match,
255 .probe = fhc_probe,
256 .driver = {
257 .name = "fhc",
258 },
259};
260
261static int __init sunfire_init(void)
440{ 262{
441 struct linux_central *central = central_bus; 263 (void) of_register_driver(&fhc_driver, &of_platform_bus_type);
442 u8 ctrl; 264 (void) of_register_driver(&clock_board_driver, &of_platform_bus_type);
443 265 return 0;
444 /* No central bus, nothing to do. */
445 if (central == NULL)
446 return;
447
448 /* OBP leaves it on, turn it off so clock board timer LED
449 * is in sync with FHC ones.
450 */
451 ctrl = upa_readb(central->clkregs + CLOCK_CTRL);
452 ctrl &= ~(CLOCK_CTRL_RLED);
453 upa_writeb(ctrl, central->clkregs + CLOCK_CTRL);
454
455 led_state = 0;
456 init_timer(&sftimer);
457 sftimer.data = 0;
458 sftimer.function = &sunfire_timer;
459 sftimer.expires = jiffies + (HZ >> 1);
460 add_timer(&sftimer);
461} 266}
267
268subsys_initcall(sunfire_init);
diff --git a/arch/sparc64/kernel/chmc.c b/arch/sparc64/kernel/chmc.c
index 6d4f02e8a4c..967b0488682 100644
--- a/arch/sparc64/kernel/chmc.c
+++ b/arch/sparc64/kernel/chmc.c
@@ -1,6 +1,6 @@
1/* memctrlr.c: Driver for UltraSPARC-III memory controller. 1/* chmc.c: Driver for UltraSPARC-III memory controller.
2 * 2 *
3 * Copyright (C) 2001, 2007 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */ 4 */
5 5
6#include <linux/module.h> 6#include <linux/module.h>
@@ -13,45 +13,64 @@
13#include <linux/smp.h> 13#include <linux/smp.h>
14#include <linux/errno.h> 14#include <linux/errno.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
16#include <asm/spitfire.h> 18#include <asm/spitfire.h>
17#include <asm/chmctrl.h> 19#include <asm/chmctrl.h>
18#include <asm/cpudata.h> 20#include <asm/cpudata.h>
19#include <asm/oplib.h> 21#include <asm/oplib.h>
20#include <asm/prom.h> 22#include <asm/prom.h>
23#include <asm/head.h>
21#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/memctrl.h>
26
27#define DRV_MODULE_NAME "chmc"
28#define PFX DRV_MODULE_NAME ": "
29#define DRV_MODULE_VERSION "0.2"
30
31MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
32MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
33MODULE_LICENSE("GPL");
34MODULE_VERSION(DRV_MODULE_VERSION);
35
36static int mc_type;
37#define MC_TYPE_SAFARI 1
38#define MC_TYPE_JBUS 2
39
40static dimm_printer_t us3mc_dimm_printer;
22 41
23#define CHMCTRL_NDGRPS 2 42#define CHMCTRL_NDGRPS 2
24#define CHMCTRL_NDIMMS 4 43#define CHMCTRL_NDIMMS 4
25 44
26#define DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS) 45#define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
27 46
28/* OBP memory-layout property format. */ 47/* OBP memory-layout property format. */
29struct obp_map { 48struct chmc_obp_map {
30 unsigned char dimm_map[144]; 49 unsigned char dimm_map[144];
31 unsigned char pin_map[576]; 50 unsigned char pin_map[576];
32}; 51};
33 52
34#define DIMM_LABEL_SZ 8 53#define DIMM_LABEL_SZ 8
35 54
36struct obp_mem_layout { 55struct chmc_obp_mem_layout {
37 /* One max 8-byte string label per DIMM. Usually 56 /* One max 8-byte string label per DIMM. Usually
38 * this matches the label on the motherboard where 57 * this matches the label on the motherboard where
39 * that DIMM resides. 58 * that DIMM resides.
40 */ 59 */
41 char dimm_labels[DIMMS_PER_MC][DIMM_LABEL_SZ]; 60 char dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ];
42 61
43 /* If symmetric use map[0], else it is 62 /* If symmetric use map[0], else it is
44 * asymmetric and map[1] should be used. 63 * asymmetric and map[1] should be used.
45 */ 64 */
46 char symmetric; 65 char symmetric;
47 66
48 struct obp_map map[2]; 67 struct chmc_obp_map map[2];
49}; 68};
50 69
51#define CHMCTRL_NBANKS 4 70#define CHMCTRL_NBANKS 4
52 71
53struct bank_info { 72struct chmc_bank_info {
54 struct mctrl_info *mp; 73 struct chmc *p;
55 int bank_id; 74 int bank_id;
56 75
57 u64 raw_reg; 76 u64 raw_reg;
@@ -65,28 +84,406 @@ struct bank_info {
65 unsigned long size; 84 unsigned long size;
66}; 85};
67 86
68struct mctrl_info { 87struct chmc {
69 struct list_head list; 88 struct list_head list;
70 int portid; 89 int portid;
90
91 struct chmc_obp_mem_layout layout_prop;
92 int layout_size;
93
94 void __iomem *regs;
71 95
72 struct obp_mem_layout layout_prop; 96 u64 timing_control1;
73 int layout_size; 97 u64 timing_control2;
98 u64 timing_control3;
99 u64 timing_control4;
100 u64 memaddr_control;
74 101
75 void __iomem *regs; 102 struct chmc_bank_info logical_banks[CHMCTRL_NBANKS];
103};
104
105#define JBUSMC_REGS_SIZE 8
106
107#define JB_MC_REG1_DIMM2_BANK3 0x8000000000000000UL
108#define JB_MC_REG1_DIMM1_BANK1 0x4000000000000000UL
109#define JB_MC_REG1_DIMM2_BANK2 0x2000000000000000UL
110#define JB_MC_REG1_DIMM1_BANK0 0x1000000000000000UL
111#define JB_MC_REG1_XOR 0x0000010000000000UL
112#define JB_MC_REG1_ADDR_GEN_2 0x000000e000000000UL
113#define JB_MC_REG1_ADDR_GEN_2_SHIFT 37
114#define JB_MC_REG1_ADDR_GEN_1 0x0000001c00000000UL
115#define JB_MC_REG1_ADDR_GEN_1_SHIFT 34
116#define JB_MC_REG1_INTERLEAVE 0x0000000001800000UL
117#define JB_MC_REG1_INTERLEAVE_SHIFT 23
118#define JB_MC_REG1_DIMM2_PTYPE 0x0000000000200000UL
119#define JB_MC_REG1_DIMM2_PTYPE_SHIFT 21
120#define JB_MC_REG1_DIMM1_PTYPE 0x0000000000100000UL
121#define JB_MC_REG1_DIMM1_PTYPE_SHIFT 20
122
123#define PART_TYPE_X8 0
124#define PART_TYPE_X4 1
125
126#define INTERLEAVE_NONE 0
127#define INTERLEAVE_SAME 1
128#define INTERLEAVE_INTERNAL 2
129#define INTERLEAVE_BOTH 3
130
131#define ADDR_GEN_128MB 0
132#define ADDR_GEN_256MB 1
133#define ADDR_GEN_512MB 2
134#define ADDR_GEN_1GB 3
135
136#define JB_NUM_DIMM_GROUPS 2
137#define JB_NUM_DIMMS_PER_GROUP 2
138#define JB_NUM_DIMMS (JB_NUM_DIMM_GROUPS * JB_NUM_DIMMS_PER_GROUP)
139
140struct jbusmc_obp_map {
141 unsigned char dimm_map[18];
142 unsigned char pin_map[144];
143};
144
145struct jbusmc_obp_mem_layout {
146 /* One max 8-byte string label per DIMM. Usually
147 * this matches the label on the motherboard where
148 * that DIMM resides.
149 */
150 char dimm_labels[JB_NUM_DIMMS][DIMM_LABEL_SZ];
151
152 /* If symmetric use map[0], else it is
153 * asymmetric and map[1] should be used.
154 */
155 char symmetric;
156
157 struct jbusmc_obp_map map;
158
159 char _pad;
160};
76 161
77 u64 timing_control1; 162struct jbusmc_dimm_group {
78 u64 timing_control2; 163 struct jbusmc *controller;
79 u64 timing_control3; 164 int index;
80 u64 timing_control4; 165 u64 base_addr;
81 u64 memaddr_control; 166 u64 size;
167};
82 168
83 struct bank_info logical_banks[CHMCTRL_NBANKS]; 169struct jbusmc {
170 void __iomem *regs;
171 u64 mc_reg_1;
172 u32 portid;
173 struct jbusmc_obp_mem_layout layout;
174 int layout_len;
175 int num_dimm_groups;
176 struct jbusmc_dimm_group dimm_groups[JB_NUM_DIMM_GROUPS];
177 struct list_head list;
84}; 178};
85 179
180static DEFINE_SPINLOCK(mctrl_list_lock);
86static LIST_HEAD(mctrl_list); 181static LIST_HEAD(mctrl_list);
87 182
183static void mc_list_add(struct list_head *list)
184{
185 spin_lock(&mctrl_list_lock);
186 list_add(list, &mctrl_list);
187 spin_unlock(&mctrl_list_lock);
188}
189
190static void mc_list_del(struct list_head *list)
191{
192 spin_lock(&mctrl_list_lock);
193 list_del_init(list);
194 spin_unlock(&mctrl_list_lock);
195}
196
197#define SYNDROME_MIN -1
198#define SYNDROME_MAX 144
199
200/* Covert syndrome code into the way the bits are positioned
201 * on the bus.
202 */
203static int syndrome_to_qword_code(int syndrome_code)
204{
205 if (syndrome_code < 128)
206 syndrome_code += 16;
207 else if (syndrome_code < 128 + 9)
208 syndrome_code -= (128 - 7);
209 else if (syndrome_code < (128 + 9 + 3))
210 syndrome_code -= (128 + 9 - 4);
211 else
212 syndrome_code -= (128 + 9 + 3);
213 return syndrome_code;
214}
215
216/* All this magic has to do with how a cache line comes over the wire
217 * on Safari and JBUS. A 64-bit line comes over in 1 or more quadword
218 * cycles, each of which transmit ECC/MTAG info as well as the actual
219 * data.
220 */
221#define L2_LINE_SIZE 64
222#define L2_LINE_ADDR_MSK (L2_LINE_SIZE - 1)
223#define QW_PER_LINE 4
224#define QW_BYTES (L2_LINE_SIZE / QW_PER_LINE)
225#define QW_BITS 144
226#define SAFARI_LAST_BIT (576 - 1)
227#define JBUS_LAST_BIT (144 - 1)
228
229static void get_pin_and_dimm_str(int syndrome_code, unsigned long paddr,
230 int *pin_p, char **dimm_str_p, void *_prop,
231 int base_dimm_offset)
232{
233 int qword_code = syndrome_to_qword_code(syndrome_code);
234 int cache_line_offset;
235 int offset_inverse;
236 int dimm_map_index;
237 int map_val;
238
239 if (mc_type == MC_TYPE_JBUS) {
240 struct jbusmc_obp_mem_layout *p = _prop;
241
242 /* JBUS */
243 cache_line_offset = qword_code;
244 offset_inverse = (JBUS_LAST_BIT - cache_line_offset);
245 dimm_map_index = offset_inverse / 8;
246 map_val = p->map.dimm_map[dimm_map_index];
247 map_val = ((map_val >> ((7 - (offset_inverse & 7)))) & 1);
248 *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];
249 *pin_p = p->map.pin_map[cache_line_offset];
250 } else {
251 struct chmc_obp_mem_layout *p = _prop;
252 struct chmc_obp_map *mp;
253 int qword;
254
255 /* Safari */
256 if (p->symmetric)
257 mp = &p->map[0];
258 else
259 mp = &p->map[1];
260
261 qword = (paddr & L2_LINE_ADDR_MSK) / QW_BYTES;
262 cache_line_offset = ((3 - qword) * QW_BITS) + qword_code;
263 offset_inverse = (SAFARI_LAST_BIT - cache_line_offset);
264 dimm_map_index = offset_inverse >> 2;
265 map_val = mp->dimm_map[dimm_map_index];
266 map_val = ((map_val >> ((3 - (offset_inverse & 3)) << 1)) & 0x3);
267 *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];
268 *pin_p = mp->pin_map[cache_line_offset];
269 }
270}
271
272static struct jbusmc_dimm_group *jbusmc_find_dimm_group(unsigned long phys_addr)
273{
274 struct jbusmc *p;
275
276 list_for_each_entry(p, &mctrl_list, list) {
277 int i;
278
279 for (i = 0; i < p->num_dimm_groups; i++) {
280 struct jbusmc_dimm_group *dp = &p->dimm_groups[i];
281
282 if (phys_addr < dp->base_addr ||
283 (dp->base_addr + dp->size) <= phys_addr)
284 continue;
285
286 return dp;
287 }
288 }
289 return NULL;
290}
291
292static int jbusmc_print_dimm(int syndrome_code,
293 unsigned long phys_addr,
294 char *buf, int buflen)
295{
296 struct jbusmc_obp_mem_layout *prop;
297 struct jbusmc_dimm_group *dp;
298 struct jbusmc *p;
299 int first_dimm;
300
301 dp = jbusmc_find_dimm_group(phys_addr);
302 if (dp == NULL ||
303 syndrome_code < SYNDROME_MIN ||
304 syndrome_code > SYNDROME_MAX) {
305 buf[0] = '?';
306 buf[1] = '?';
307 buf[2] = '?';
308 buf[3] = '\0';
309 }
310 p = dp->controller;
311 prop = &p->layout;
312
313 first_dimm = dp->index * JB_NUM_DIMMS_PER_GROUP;
314
315 if (syndrome_code != SYNDROME_MIN) {
316 char *dimm_str;
317 int pin;
318
319 get_pin_and_dimm_str(syndrome_code, phys_addr, &pin,
320 &dimm_str, prop, first_dimm);
321 sprintf(buf, "%s, pin %3d", dimm_str, pin);
322 } else {
323 int dimm;
324
325 /* Multi-bit error, we just dump out all the
326 * dimm labels associated with this dimm group.
327 */
328 for (dimm = 0; dimm < JB_NUM_DIMMS_PER_GROUP; dimm++) {
329 sprintf(buf, "%s ",
330 prop->dimm_labels[first_dimm + dimm]);
331 buf += strlen(buf);
332 }
333 }
334
335 return 0;
336}
337
338static u64 __devinit jbusmc_dimm_group_size(u64 base,
339 const struct linux_prom64_registers *mem_regs,
340 int num_mem_regs)
341{
342 u64 max = base + (8UL * 1024 * 1024 * 1024);
343 u64 max_seen = base;
344 int i;
345
346 for (i = 0; i < num_mem_regs; i++) {
347 const struct linux_prom64_registers *ent;
348 u64 this_base;
349 u64 this_end;
350
351 ent = &mem_regs[i];
352 this_base = ent->phys_addr;
353 this_end = this_base + ent->reg_size;
354 if (base < this_base || base >= this_end)
355 continue;
356 if (this_end > max)
357 this_end = max;
358 if (this_end > max_seen)
359 max_seen = this_end;
360 }
361
362 return max_seen - base;
363}
364
365static void __devinit jbusmc_construct_one_dimm_group(struct jbusmc *p,
366 unsigned long index,
367 const struct linux_prom64_registers *mem_regs,
368 int num_mem_regs)
369{
370 struct jbusmc_dimm_group *dp = &p->dimm_groups[index];
371
372 dp->controller = p;
373 dp->index = index;
374
375 dp->base_addr = (p->portid * (64UL * 1024 * 1024 * 1024));
376 dp->base_addr += (index * (8UL * 1024 * 1024 * 1024));
377 dp->size = jbusmc_dimm_group_size(dp->base_addr, mem_regs, num_mem_regs);
378}
379
380static void __devinit jbusmc_construct_dimm_groups(struct jbusmc *p,
381 const struct linux_prom64_registers *mem_regs,
382 int num_mem_regs)
383{
384 if (p->mc_reg_1 & JB_MC_REG1_DIMM1_BANK0) {
385 jbusmc_construct_one_dimm_group(p, 0, mem_regs, num_mem_regs);
386 p->num_dimm_groups++;
387 }
388 if (p->mc_reg_1 & JB_MC_REG1_DIMM2_BANK2) {
389 jbusmc_construct_one_dimm_group(p, 1, mem_regs, num_mem_regs);
390 p->num_dimm_groups++;
391 }
392}
393
394static int __devinit jbusmc_probe(struct of_device *op,
395 const struct of_device_id *match)
396{
397 const struct linux_prom64_registers *mem_regs;
398 struct device_node *mem_node;
399 int err, len, num_mem_regs;
400 struct jbusmc *p;
401 const u32 *prop;
402 const void *ml;
403
404 err = -ENODEV;
405 mem_node = of_find_node_by_path("/memory");
406 if (!mem_node) {
407 printk(KERN_ERR PFX "Cannot find /memory node.\n");
408 goto out;
409 }
410 mem_regs = of_get_property(mem_node, "reg", &len);
411 if (!mem_regs) {
412 printk(KERN_ERR PFX "Cannot get reg property of /memory node.\n");
413 goto out;
414 }
415 num_mem_regs = len / sizeof(*mem_regs);
416
417 err = -ENOMEM;
418 p = kzalloc(sizeof(*p), GFP_KERNEL);
419 if (!p) {
420 printk(KERN_ERR PFX "Cannot allocate struct jbusmc.\n");
421 goto out;
422 }
423
424 INIT_LIST_HEAD(&p->list);
425
426 err = -ENODEV;
427 prop = of_get_property(op->node, "portid", &len);
428 if (!prop || len != 4) {
429 printk(KERN_ERR PFX "Cannot find portid.\n");
430 goto out_free;
431 }
432
433 p->portid = *prop;
434
435 prop = of_get_property(op->node, "memory-control-register-1", &len);
436 if (!prop || len != 8) {
437 printk(KERN_ERR PFX "Cannot get memory control register 1.\n");
438 goto out_free;
439 }
440
441 p->mc_reg_1 = ((u64)prop[0] << 32) | (u64) prop[1];
442
443 err = -ENOMEM;
444 p->regs = of_ioremap(&op->resource[0], 0, JBUSMC_REGS_SIZE, "jbusmc");
445 if (!p->regs) {
446 printk(KERN_ERR PFX "Cannot map jbusmc regs.\n");
447 goto out_free;
448 }
449
450 err = -ENODEV;
451 ml = of_get_property(op->node, "memory-layout", &p->layout_len);
452 if (!ml) {
453 printk(KERN_ERR PFX "Cannot get memory layout property.\n");
454 goto out_iounmap;
455 }
456 if (p->layout_len > sizeof(p->layout)) {
457 printk(KERN_ERR PFX "Unexpected memory-layout size %d\n",
458 p->layout_len);
459 goto out_iounmap;
460 }
461 memcpy(&p->layout, ml, p->layout_len);
462
463 jbusmc_construct_dimm_groups(p, mem_regs, num_mem_regs);
464
465 mc_list_add(&p->list);
466
467 printk(KERN_INFO PFX "UltraSPARC-IIIi memory controller at %s\n",
468 op->node->full_name);
469
470 dev_set_drvdata(&op->dev, p);
471
472 err = 0;
473
474out:
475 return err;
476
477out_iounmap:
478 of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
479
480out_free:
481 kfree(p);
482 goto out;
483}
484
88/* Does BANK decode PHYS_ADDR? */ 485/* Does BANK decode PHYS_ADDR? */
89static int bank_match(struct bank_info *bp, unsigned long phys_addr) 486static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr)
90{ 487{
91 unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT; 488 unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
92 unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT; 489 unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
@@ -118,25 +515,18 @@ static int bank_match(struct bank_info *bp, unsigned long phys_addr)
118} 515}
119 516
120/* Given PHYS_ADDR, search memory controller banks for a match. */ 517/* Given PHYS_ADDR, search memory controller banks for a match. */
121static struct bank_info *find_bank(unsigned long phys_addr) 518static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr)
122{ 519{
123 struct list_head *mctrl_head = &mctrl_list; 520 struct chmc *p;
124 struct list_head *mctrl_entry = mctrl_head->next;
125 521
126 for (;;) { 522 list_for_each_entry(p, &mctrl_list, list) {
127 struct mctrl_info *mp =
128 list_entry(mctrl_entry, struct mctrl_info, list);
129 int bank_no; 523 int bank_no;
130 524
131 if (mctrl_entry == mctrl_head)
132 break;
133 mctrl_entry = mctrl_entry->next;
134
135 for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) { 525 for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
136 struct bank_info *bp; 526 struct chmc_bank_info *bp;
137 527
138 bp = &mp->logical_banks[bank_no]; 528 bp = &p->logical_banks[bank_no];
139 if (bank_match(bp, phys_addr)) 529 if (chmc_bank_match(bp, phys_addr))
140 return bp; 530 return bp;
141 } 531 }
142 } 532 }
@@ -145,17 +535,15 @@ static struct bank_info *find_bank(unsigned long phys_addr)
145} 535}
146 536
147/* This is the main purpose of this driver. */ 537/* This is the main purpose of this driver. */
148#define SYNDROME_MIN -1 538static int chmc_print_dimm(int syndrome_code,
149#define SYNDROME_MAX 144 539 unsigned long phys_addr,
150int chmc_getunumber(int syndrome_code, 540 char *buf, int buflen)
151 unsigned long phys_addr,
152 char *buf, int buflen)
153{ 541{
154 struct bank_info *bp; 542 struct chmc_bank_info *bp;
155 struct obp_mem_layout *prop; 543 struct chmc_obp_mem_layout *prop;
156 int bank_in_controller, first_dimm; 544 int bank_in_controller, first_dimm;
157 545
158 bp = find_bank(phys_addr); 546 bp = chmc_find_bank(phys_addr);
159 if (bp == NULL || 547 if (bp == NULL ||
160 syndrome_code < SYNDROME_MIN || 548 syndrome_code < SYNDROME_MIN ||
161 syndrome_code > SYNDROME_MAX) { 549 syndrome_code > SYNDROME_MAX) {
@@ -166,60 +554,18 @@ int chmc_getunumber(int syndrome_code,
166 return 0; 554 return 0;
167 } 555 }
168 556
169 prop = &bp->mp->layout_prop; 557 prop = &bp->p->layout_prop;
170 bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1); 558 bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
171 first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1)); 559 first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
172 first_dimm *= CHMCTRL_NDIMMS; 560 first_dimm *= CHMCTRL_NDIMMS;
173 561
174 if (syndrome_code != SYNDROME_MIN) { 562 if (syndrome_code != SYNDROME_MIN) {
175 struct obp_map *map; 563 char *dimm_str;
176 int qword, where_in_line, where, map_index, map_offset; 564 int pin;
177 unsigned int map_val;
178 565
179 /* Yaay, single bit error so we can figure out 566 get_pin_and_dimm_str(syndrome_code, phys_addr, &pin,
180 * the exact dimm. 567 &dimm_str, prop, first_dimm);
181 */ 568 sprintf(buf, "%s, pin %3d", dimm_str, pin);
182 if (prop->symmetric)
183 map = &prop->map[0];
184 else
185 map = &prop->map[1];
186
187 /* Covert syndrome code into the way the bits are
188 * positioned on the bus.
189 */
190 if (syndrome_code < 144 - 16)
191 syndrome_code += 16;
192 else if (syndrome_code < 144)
193 syndrome_code -= (144 - 7);
194 else if (syndrome_code < (144 + 3))
195 syndrome_code -= (144 + 3 - 4);
196 else
197 syndrome_code -= 144 + 3;
198
199 /* All this magic has to do with how a cache line
200 * comes over the wire on Safari. A 64-bit line
201 * comes over in 4 quadword cycles, each of which
202 * transmit ECC/MTAG info as well as the actual
203 * data. 144 bits per quadword, 576 total.
204 */
205#define LINE_SIZE 64
206#define LINE_ADDR_MSK (LINE_SIZE - 1)
207#define QW_PER_LINE 4
208#define QW_BYTES (LINE_SIZE / QW_PER_LINE)
209#define QW_BITS 144
210#define LAST_BIT (576 - 1)
211
212 qword = (phys_addr & LINE_ADDR_MSK) / QW_BYTES;
213 where_in_line = ((3 - qword) * QW_BITS) + syndrome_code;
214 where = (LAST_BIT - where_in_line);
215 map_index = where >> 2;
216 map_offset = where & 0x3;
217 map_val = map->dimm_map[map_index];
218 map_val = ((map_val >> ((3 - map_offset) << 1)) & (2 - 1));
219
220 sprintf(buf, "%s, pin %3d",
221 prop->dimm_labels[first_dimm + map_val],
222 map->pin_map[where_in_line]);
223 } else { 569 } else {
224 int dimm; 570 int dimm;
225 571
@@ -240,7 +586,7 @@ int chmc_getunumber(int syndrome_code,
240 * the code is executing, you must use special ASI load/store else 586 * the code is executing, you must use special ASI load/store else
241 * you go through the global mapping. 587 * you go through the global mapping.
242 */ 588 */
243static u64 read_mcreg(struct mctrl_info *mp, unsigned long offset) 589static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset)
244{ 590{
245 unsigned long ret, this_cpu; 591 unsigned long ret, this_cpu;
246 592
@@ -248,14 +594,14 @@ static u64 read_mcreg(struct mctrl_info *mp, unsigned long offset)
248 594
249 this_cpu = real_hard_smp_processor_id(); 595 this_cpu = real_hard_smp_processor_id();
250 596
251 if (mp->portid == this_cpu) { 597 if (p->portid == this_cpu) {
252 __asm__ __volatile__("ldxa [%1] %2, %0" 598 __asm__ __volatile__("ldxa [%1] %2, %0"
253 : "=r" (ret) 599 : "=r" (ret)
254 : "r" (offset), "i" (ASI_MCU_CTRL_REG)); 600 : "r" (offset), "i" (ASI_MCU_CTRL_REG));
255 } else { 601 } else {
256 __asm__ __volatile__("ldxa [%1] %2, %0" 602 __asm__ __volatile__("ldxa [%1] %2, %0"
257 : "=r" (ret) 603 : "=r" (ret)
258 : "r" (mp->regs + offset), 604 : "r" (p->regs + offset),
259 "i" (ASI_PHYS_BYPASS_EC_E)); 605 "i" (ASI_PHYS_BYPASS_EC_E));
260 } 606 }
261 607
@@ -265,178 +611,253 @@ static u64 read_mcreg(struct mctrl_info *mp, unsigned long offset)
265} 611}
266 612
267#if 0 /* currently unused */ 613#if 0 /* currently unused */
268static void write_mcreg(struct mctrl_info *mp, unsigned long offset, u64 val) 614static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val)
269{ 615{
270 if (mp->portid == smp_processor_id()) { 616 if (p->portid == smp_processor_id()) {
271 __asm__ __volatile__("stxa %0, [%1] %2" 617 __asm__ __volatile__("stxa %0, [%1] %2"
272 : : "r" (val), 618 : : "r" (val),
273 "r" (offset), "i" (ASI_MCU_CTRL_REG)); 619 "r" (offset), "i" (ASI_MCU_CTRL_REG));
274 } else { 620 } else {
275 __asm__ __volatile__("ldxa %0, [%1] %2" 621 __asm__ __volatile__("ldxa %0, [%1] %2"
276 : : "r" (val), 622 : : "r" (val),
277 "r" (mp->regs + offset), 623 "r" (p->regs + offset),
278 "i" (ASI_PHYS_BYPASS_EC_E)); 624 "i" (ASI_PHYS_BYPASS_EC_E));
279 } 625 }
280} 626}
281#endif 627#endif
282 628
283static void interpret_one_decode_reg(struct mctrl_info *mp, int which_bank, u64 val) 629static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val)
284{ 630{
285 struct bank_info *p = &mp->logical_banks[which_bank]; 631 struct chmc_bank_info *bp = &p->logical_banks[which_bank];
286 632
287 p->mp = mp; 633 bp->p = p;
288 p->bank_id = (CHMCTRL_NBANKS * mp->portid) + which_bank; 634 bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;
289 p->raw_reg = val; 635 bp->raw_reg = val;
290 p->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT; 636 bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
291 p->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT; 637 bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
292 p->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT; 638 bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
293 p->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT; 639 bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
294 p->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT; 640 bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
295 641
296 p->base = (p->um); 642 bp->base = (bp->um);
297 p->base &= ~(p->uk); 643 bp->base &= ~(bp->uk);
298 p->base <<= PA_UPPER_BITS_SHIFT; 644 bp->base <<= PA_UPPER_BITS_SHIFT;
299 645
300 switch(p->lk) { 646 switch(bp->lk) {
301 case 0xf: 647 case 0xf:
302 default: 648 default:
303 p->interleave = 1; 649 bp->interleave = 1;
304 break; 650 break;
305 651
306 case 0xe: 652 case 0xe:
307 p->interleave = 2; 653 bp->interleave = 2;
308 break; 654 break;
309 655
310 case 0xc: 656 case 0xc:
311 p->interleave = 4; 657 bp->interleave = 4;
312 break; 658 break;
313 659
314 case 0x8: 660 case 0x8:
315 p->interleave = 8; 661 bp->interleave = 8;
316 break; 662 break;
317 663
318 case 0x0: 664 case 0x0:
319 p->interleave = 16; 665 bp->interleave = 16;
320 break; 666 break;
321 }; 667 };
322 668
323 /* UK[10] is reserved, and UK[11] is not set for the SDRAM 669 /* UK[10] is reserved, and UK[11] is not set for the SDRAM
324 * bank size definition. 670 * bank size definition.
325 */ 671 */
326 p->size = (((unsigned long)p->uk & 672 bp->size = (((unsigned long)bp->uk &
327 ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT; 673 ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
328 p->size /= p->interleave; 674 bp->size /= bp->interleave;
329} 675}
330 676
331static void fetch_decode_regs(struct mctrl_info *mp) 677static void chmc_fetch_decode_regs(struct chmc *p)
332{ 678{
333 if (mp->layout_size == 0) 679 if (p->layout_size == 0)
334 return; 680 return;
335 681
336 interpret_one_decode_reg(mp, 0, 682 chmc_interpret_one_decode_reg(p, 0,
337 read_mcreg(mp, CHMCTRL_DECODE1)); 683 chmc_read_mcreg(p, CHMCTRL_DECODE1));
338 interpret_one_decode_reg(mp, 1, 684 chmc_interpret_one_decode_reg(p, 1,
339 read_mcreg(mp, CHMCTRL_DECODE2)); 685 chmc_read_mcreg(p, CHMCTRL_DECODE2));
340 interpret_one_decode_reg(mp, 2, 686 chmc_interpret_one_decode_reg(p, 2,
341 read_mcreg(mp, CHMCTRL_DECODE3)); 687 chmc_read_mcreg(p, CHMCTRL_DECODE3));
342 interpret_one_decode_reg(mp, 3, 688 chmc_interpret_one_decode_reg(p, 3,
343 read_mcreg(mp, CHMCTRL_DECODE4)); 689 chmc_read_mcreg(p, CHMCTRL_DECODE4));
344} 690}
345 691
346static int init_one_mctrl(struct device_node *dp) 692static int __devinit chmc_probe(struct of_device *op,
693 const struct of_device_id *match)
347{ 694{
348 struct mctrl_info *mp = kzalloc(sizeof(*mp), GFP_KERNEL); 695 struct device_node *dp = op->node;
349 int portid = of_getintprop_default(dp, "portid", -1); 696 unsigned long ver;
350 const struct linux_prom64_registers *regs;
351 const void *pval; 697 const void *pval;
352 int len; 698 int len, portid;
699 struct chmc *p;
700 int err;
701
702 err = -ENODEV;
703 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
704 if ((ver >> 32UL) == __JALAPENO_ID ||
705 (ver >> 32UL) == __SERRANO_ID)
706 goto out;
353 707
354 if (!mp) 708 portid = of_getintprop_default(dp, "portid", -1);
355 return -1;
356 if (portid == -1) 709 if (portid == -1)
357 goto fail; 710 goto out;
358 711
359 mp->portid = portid;
360 pval = of_get_property(dp, "memory-layout", &len); 712 pval = of_get_property(dp, "memory-layout", &len);
361 mp->layout_size = len; 713 if (pval && len > sizeof(p->layout_prop)) {
362 if (!pval) 714 printk(KERN_ERR PFX "Unexpected memory-layout property "
363 mp->layout_size = 0; 715 "size %d.\n", len);
364 else { 716 goto out;
365 if (mp->layout_size > sizeof(mp->layout_prop))
366 goto fail;
367 memcpy(&mp->layout_prop, pval, len);
368 } 717 }
369 718
370 regs = of_get_property(dp, "reg", NULL); 719 err = -ENOMEM;
371 if (!regs || regs->reg_size != 0x48) 720 p = kzalloc(sizeof(*p), GFP_KERNEL);
372 goto fail; 721 if (!p) {
722 printk(KERN_ERR PFX "Could not allocate struct chmc.\n");
723 goto out;
724 }
373 725
374 mp->regs = ioremap(regs->phys_addr, regs->reg_size); 726 p->portid = portid;
375 if (mp->regs == NULL) 727 p->layout_size = len;
376 goto fail; 728 if (!pval)
729 p->layout_size = 0;
730 else
731 memcpy(&p->layout_prop, pval, len);
732
733 p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
734 if (!p->regs) {
735 printk(KERN_ERR PFX "Could not map registers.\n");
736 goto out_free;
737 }
377 738
378 if (mp->layout_size != 0UL) { 739 if (p->layout_size != 0UL) {
379 mp->timing_control1 = read_mcreg(mp, CHMCTRL_TCTRL1); 740 p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);
380 mp->timing_control2 = read_mcreg(mp, CHMCTRL_TCTRL2); 741 p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);
381 mp->timing_control3 = read_mcreg(mp, CHMCTRL_TCTRL3); 742 p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);
382 mp->timing_control4 = read_mcreg(mp, CHMCTRL_TCTRL4); 743 p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);
383 mp->memaddr_control = read_mcreg(mp, CHMCTRL_MACTRL); 744 p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);
384 } 745 }
385 746
386 fetch_decode_regs(mp); 747 chmc_fetch_decode_regs(p);
387 748
388 list_add(&mp->list, &mctrl_list); 749 mc_list_add(&p->list);
389 750
390 /* Report the device. */ 751 printk(KERN_INFO PFX "UltraSPARC-III memory controller at %s [%s]\n",
391 printk(KERN_INFO "%s: US3 memory controller at %p [%s]\n",
392 dp->full_name, 752 dp->full_name,
393 mp->regs, (mp->layout_size ? "ACTIVE" : "INACTIVE")); 753 (p->layout_size ? "ACTIVE" : "INACTIVE"));
394 754
395 return 0; 755 dev_set_drvdata(&op->dev, p);
756
757 err = 0;
758
759out:
760 return err;
761
762out_free:
763 kfree(p);
764 goto out;
765}
396 766
397fail: 767static int __devinit us3mc_probe(struct of_device *op,
398 if (mp) { 768 const struct of_device_id *match)
399 if (mp->regs != NULL) 769{
400 iounmap(mp->regs); 770 if (mc_type == MC_TYPE_SAFARI)
401 kfree(mp); 771 return chmc_probe(op, match);
772 else if (mc_type == MC_TYPE_JBUS)
773 return jbusmc_probe(op, match);
774 return -ENODEV;
775}
776
777static void __devexit chmc_destroy(struct of_device *op, struct chmc *p)
778{
779 list_del(&p->list);
780 of_iounmap(&op->resource[0], p->regs, 0x48);
781 kfree(p);
782}
783
784static void __devexit jbusmc_destroy(struct of_device *op, struct jbusmc *p)
785{
786 mc_list_del(&p->list);
787 of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
788 kfree(p);
789}
790
791static int __devexit us3mc_remove(struct of_device *op)
792{
793 void *p = dev_get_drvdata(&op->dev);
794
795 if (p) {
796 if (mc_type == MC_TYPE_SAFARI)
797 chmc_destroy(op, p);
798 else if (mc_type == MC_TYPE_JBUS)
799 jbusmc_destroy(op, p);
402 } 800 }
403 return -1; 801 return 0;
802}
803
804static const struct of_device_id us3mc_match[] = {
805 {
806 .name = "memory-controller",
807 },
808 {},
809};
810MODULE_DEVICE_TABLE(of, us3mc_match);
811
812static struct of_platform_driver us3mc_driver = {
813 .name = "us3mc",
814 .match_table = us3mc_match,
815 .probe = us3mc_probe,
816 .remove = __devexit_p(us3mc_remove),
817};
818
819static inline bool us3mc_platform(void)
820{
821 if (tlb_type == cheetah || tlb_type == cheetah_plus)
822 return true;
823 return false;
404} 824}
405 825
406static int __init chmc_init(void) 826static int __init us3mc_init(void)
407{ 827{
408 struct device_node *dp; 828 unsigned long ver;
829 int ret;
409 830
410 /* This driver is only for cheetah platforms. */ 831 if (!us3mc_platform())
411 if (tlb_type != cheetah && tlb_type != cheetah_plus)
412 return -ENODEV; 832 return -ENODEV;
413 833
414 for_each_node_by_name(dp, "memory-controller") 834 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
415 init_one_mctrl(dp); 835 if ((ver >> 32UL) == __JALAPENO_ID ||
836 (ver >> 32UL) == __SERRANO_ID) {
837 mc_type = MC_TYPE_JBUS;
838 us3mc_dimm_printer = jbusmc_print_dimm;
839 } else {
840 mc_type = MC_TYPE_SAFARI;
841 us3mc_dimm_printer = chmc_print_dimm;
842 }
416 843
417 for_each_node_by_name(dp, "mc-us3") 844 ret = register_dimm_printer(us3mc_dimm_printer);
418 init_one_mctrl(dp);
419 845
420 return 0; 846 if (!ret) {
847 ret = of_register_driver(&us3mc_driver, &of_bus_type);
848 if (ret)
849 unregister_dimm_printer(us3mc_dimm_printer);
850 }
851 return ret;
421} 852}
422 853
423static void __exit chmc_cleanup(void) 854static void __exit us3mc_cleanup(void)
424{ 855{
425 struct list_head *head = &mctrl_list; 856 if (us3mc_platform()) {
426 struct list_head *tmp = head->next; 857 unregister_dimm_printer(us3mc_dimm_printer);
427 858 of_unregister_driver(&us3mc_driver);
428 for (;;) {
429 struct mctrl_info *p =
430 list_entry(tmp, struct mctrl_info, list);
431 if (tmp == head)
432 break;
433 tmp = tmp->next;
434
435 list_del(&p->list);
436 iounmap(p->regs);
437 kfree(p);
438 } 859 }
439} 860}
440 861
441module_init(chmc_init); 862module_init(us3mc_init);
442module_exit(chmc_cleanup); 863module_exit(us3mc_cleanup);
diff --git a/arch/sparc64/kernel/cpu.c b/arch/sparc64/kernel/cpu.c
index 0097c08dc60..0c9ac83ed0a 100644
--- a/arch/sparc64/kernel/cpu.c
+++ b/arch/sparc64/kernel/cpu.c
@@ -1,7 +1,7 @@
1/* cpu.c: Dinky routines to look for the kind of Sparc cpu 1/* cpu.c: Dinky routines to look for the kind of Sparc cpu
2 * we are on. 2 * we are on.
3 * 3 *
4 * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net) 4 * Copyright (C) 1996, 2007, 2008 David S. Miller (davem@davemloft.net)
5 */ 5 */
6 6
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -19,53 +19,86 @@
19 19
20DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; 20DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
21 21
22struct cpu_iu_info { 22struct cpu_chip_info {
23 short manuf; 23 unsigned short manuf;
24 short impl; 24 unsigned short impl;
25 char* cpu_name; /* should be enough I hope... */ 25 const char *cpu_name;
26 const char *fp_name;
26}; 27};
27 28
28struct cpu_fp_info { 29static const struct cpu_chip_info cpu_chips[] = {
29 short manuf; 30 {
30 short impl; 31 .manuf = 0x17,
31 char fpu_vers; 32 .impl = 0x10,
32 char* fp_name; 33 .cpu_name = "TI UltraSparc I (SpitFire)",
34 .fp_name = "UltraSparc I integrated FPU",
35 },
36 {
37 .manuf = 0x22,
38 .impl = 0x10,
39 .cpu_name = "TI UltraSparc I (SpitFire)",
40 .fp_name = "UltraSparc I integrated FPU",
41 },
42 {
43 .manuf = 0x17,
44 .impl = 0x11,
45 .cpu_name = "TI UltraSparc II (BlackBird)",
46 .fp_name = "UltraSparc II integrated FPU",
47 },
48 {
49 .manuf = 0x17,
50 .impl = 0x12,
51 .cpu_name = "TI UltraSparc IIi (Sabre)",
52 .fp_name = "UltraSparc IIi integrated FPU",
53 },
54 {
55 .manuf = 0x17,
56 .impl = 0x13,
57 .cpu_name = "TI UltraSparc IIe (Hummingbird)",
58 .fp_name = "UltraSparc IIe integrated FPU",
59 },
60 {
61 .manuf = 0x3e,
62 .impl = 0x14,
63 .cpu_name = "TI UltraSparc III (Cheetah)",
64 .fp_name = "UltraSparc III integrated FPU",
65 },
66 {
67 .manuf = 0x3e,
68 .impl = 0x15,
69 .cpu_name = "TI UltraSparc III+ (Cheetah+)",
70 .fp_name = "UltraSparc III+ integrated FPU",
71 },
72 {
73 .manuf = 0x3e,
74 .impl = 0x16,
75 .cpu_name = "TI UltraSparc IIIi (Jalapeno)",
76 .fp_name = "UltraSparc IIIi integrated FPU",
77 },
78 {
79 .manuf = 0x3e,
80 .impl = 0x18,
81 .cpu_name = "TI UltraSparc IV (Jaguar)",
82 .fp_name = "UltraSparc IV integrated FPU",
83 },
84 {
85 .manuf = 0x3e,
86 .impl = 0x19,
87 .cpu_name = "TI UltraSparc IV+ (Panther)",
88 .fp_name = "UltraSparc IV+ integrated FPU",
89 },
90 {
91 .manuf = 0x3e,
92 .impl = 0x22,
93 .cpu_name = "TI UltraSparc IIIi+ (Serrano)",
94 .fp_name = "UltraSparc IIIi+ integrated FPU",
95 },
33}; 96};
34 97
35static struct cpu_fp_info linux_sparc_fpu[] = { 98#define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips)
36 { 0x17, 0x10, 0, "UltraSparc I integrated FPU"},
37 { 0x22, 0x10, 0, "UltraSparc I integrated FPU"},
38 { 0x17, 0x11, 0, "UltraSparc II integrated FPU"},
39 { 0x17, 0x12, 0, "UltraSparc IIi integrated FPU"},
40 { 0x17, 0x13, 0, "UltraSparc IIe integrated FPU"},
41 { 0x3e, 0x14, 0, "UltraSparc III integrated FPU"},
42 { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
43 { 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
44 { 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
45 { 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},
46 { 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},
47};
48
49#define NSPARCFPU ARRAY_SIZE(linux_sparc_fpu)
50
51static struct cpu_iu_info linux_sparc_chips[] = {
52 { 0x17, 0x10, "TI UltraSparc I (SpitFire)"},
53 { 0x22, 0x10, "TI UltraSparc I (SpitFire)"},
54 { 0x17, 0x11, "TI UltraSparc II (BlackBird)"},
55 { 0x17, 0x12, "TI UltraSparc IIi (Sabre)"},
56 { 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)"},
57 { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
58 { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
59 { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
60 { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
61 { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
62 { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
63};
64 99
65#define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips) 100const char *sparc_cpu_type;
66 101const char *sparc_fpu_type;
67char *sparc_cpu_type;
68char *sparc_fpu_type;
69 102
70static void __init sun4v_cpu_probe(void) 103static void __init sun4v_cpu_probe(void)
71{ 104{
@@ -89,68 +122,45 @@ static void __init sun4v_cpu_probe(void)
89 } 122 }
90} 123}
91 124
92void __init cpu_probe(void) 125static const struct cpu_chip_info * __init find_cpu_chip(unsigned short manuf,
126 unsigned short impl)
93{ 127{
94 unsigned long ver, fpu_vers, manuf, impl, fprs;
95 int i; 128 int i;
96
97 if (tlb_type == hypervisor) {
98 sun4v_cpu_probe();
99 return;
100 }
101 129
102 fprs = fprs_read(); 130 for (i = 0; i < ARRAY_SIZE(cpu_chips); i++) {
103 fprs_write(FPRS_FEF); 131 const struct cpu_chip_info *p = &cpu_chips[i];
104 __asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
105 : "=&r" (ver)
106 : "r" (&fpu_vers));
107 fprs_write(fprs);
108
109 manuf = ((ver >> 48) & 0xffff);
110 impl = ((ver >> 32) & 0xffff);
111
112 fpu_vers = ((fpu_vers >> 17) & 0x7);
113
114retry:
115 for (i = 0; i < NSPARCCHIPS; i++) {
116 if (linux_sparc_chips[i].manuf == manuf) {
117 if (linux_sparc_chips[i].impl == impl) {
118 sparc_cpu_type =
119 linux_sparc_chips[i].cpu_name;
120 break;
121 }
122 }
123 }
124 132
125 if (i == NSPARCCHIPS) { 133 if (p->manuf == manuf && p->impl == impl)
126 /* Maybe it is a cheetah+ derivative, report it as cheetah+ 134 return p;
127 * in that case until we learn the real names.
128 */
129 if (manuf == 0x3e &&
130 impl > 0x15) {
131 impl = 0x15;
132 goto retry;
133 } else {
134 printk("DEBUG: manuf[%lx] impl[%lx]\n",
135 manuf, impl);
136 }
137 sparc_cpu_type = "Unknown CPU";
138 } 135 }
136 return NULL;
137}
139 138
140 for (i = 0; i < NSPARCFPU; i++) { 139static int __init cpu_type_probe(void)
141 if (linux_sparc_fpu[i].manuf == manuf && 140{
142 linux_sparc_fpu[i].impl == impl) { 141 if (tlb_type == hypervisor) {
143 if (linux_sparc_fpu[i].fpu_vers == fpu_vers) { 142 sun4v_cpu_probe();
144 sparc_fpu_type = 143 } else {
145 linux_sparc_fpu[i].fp_name; 144 unsigned long ver, manuf, impl;
146 break; 145 const struct cpu_chip_info *p;
147 } 146
147 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
148
149 manuf = ((ver >> 48) & 0xffff);
150 impl = ((ver >> 32) & 0xffff);
151
152 p = find_cpu_chip(manuf, impl);
153 if (p) {
154 sparc_cpu_type = p->cpu_name;
155 sparc_fpu_type = p->fp_name;
156 } else {
157 printk(KERN_ERR "CPU: Unknown chip, manuf[%lx] impl[%lx]\n",
158 manuf, impl);
159 sparc_cpu_type = "Unknown CPU";
160 sparc_fpu_type = "Unknown FPU";
148 } 161 }
149 } 162 }
150 163 return 0;
151 if (i == NSPARCFPU) {
152 printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
153 manuf, impl, fpu_vers);
154 sparc_fpu_type = "Unknown FPU";
155 }
156} 164}
165
166arch_initcall(cpu_type_probe);
diff --git a/arch/sparc64/kernel/ds.c b/arch/sparc64/kernel/ds.c
index d0fa5aa3893..f52e0534d91 100644
--- a/arch/sparc64/kernel/ds.c
+++ b/arch/sparc64/kernel/ds.c
@@ -1,6 +1,6 @@
1/* ds.c: Domain Services driver for Logical Domains 1/* ds.c: Domain Services driver for Logical Domains
2 * 2 *
3 * Copyright (C) 2007 David S. Miller <davem@davemloft.net> 3 * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net>
4 */ 4 */
5 5
6#include <linux/kernel.h> 6#include <linux/kernel.h>
@@ -1217,7 +1217,7 @@ static int ds_remove(struct vio_dev *vdev)
1217 return 0; 1217 return 0;
1218} 1218}
1219 1219
1220static struct vio_device_id ds_match[] = { 1220static struct vio_device_id __initdata ds_match[] = {
1221 { 1221 {
1222 .type = "domain-services-port", 1222 .type = "domain-services-port",
1223 }, 1223 },
diff --git a/arch/sparc64/kernel/ebus.c b/arch/sparc64/kernel/ebus.c
index 60d36d14255..77dbf6d45fa 100644
--- a/arch/sparc64/kernel/ebus.c
+++ b/arch/sparc64/kernel/ebus.c
@@ -1,5 +1,4 @@
1/* 1/* ebus.c: EBUS DMA library code.
2 * ebus.c: PCI to EBus bridge device.
3 * 2 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 David S. Miller (davem@redhat.com) 4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
@@ -9,23 +8,11 @@
9#include <linux/kernel.h> 8#include <linux/kernel.h>
10#include <linux/types.h> 9#include <linux/types.h>
11#include <linux/init.h> 10#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/string.h>
14#include <linux/interrupt.h> 11#include <linux/interrupt.h>
15#include <linux/delay.h> 12#include <linux/delay.h>
16#include <linux/pci.h>
17#include <linux/of_device.h>
18
19#include <asm/system.h>
20#include <asm/page.h>
21#include <asm/ebus.h>
22#include <asm/oplib.h>
23#include <asm/prom.h>
24#include <asm/bpp.h>
25#include <asm/irq.h>
26#include <asm/io.h>
27 13
28/* EBUS dma library. */ 14#include <asm/ebus_dma.h>
15#include <asm/io.h>
29 16
30#define EBDMA_CSR 0x00UL /* Control/Status */ 17#define EBDMA_CSR 0x00UL /* Control/Status */
31#define EBDMA_ADDR 0x04UL /* DMA Address */ 18#define EBDMA_ADDR 0x04UL /* DMA Address */
@@ -268,283 +255,3 @@ void ebus_dma_enable(struct ebus_dma_info *p, int on)
268 spin_unlock_irqrestore(&p->lock, flags); 255 spin_unlock_irqrestore(&p->lock, flags);
269} 256}
270EXPORT_SYMBOL(ebus_dma_enable); 257EXPORT_SYMBOL(ebus_dma_enable);
271
272struct linux_ebus *ebus_chain = NULL;
273
274static inline void *ebus_alloc(size_t size)
275{
276 void *mem;
277
278 mem = kzalloc(size, GFP_ATOMIC);
279 if (!mem)
280 panic("ebus_alloc: out of memory");
281 return mem;
282}
283
284static void __init fill_ebus_child(struct device_node *dp,
285 struct linux_ebus_child *dev,
286 int non_standard_regs)
287{
288 struct of_device *op;
289 const int *regs;
290 int i, len;
291
292 dev->prom_node = dp;
293 printk(" (%s)", dp->name);
294
295 regs = of_get_property(dp, "reg", &len);
296 if (!regs)
297 dev->num_addrs = 0;
298 else
299 dev->num_addrs = len / sizeof(regs[0]);
300
301 if (non_standard_regs) {
302 /* This is to handle reg properties which are not
303 * in the parent relative format. One example are
304 * children of the i2c device on CompactPCI systems.
305 *
306 * So, for such devices we just record the property
307 * raw in the child resources.
308 */
309 for (i = 0; i < dev->num_addrs; i++)
310 dev->resource[i].start = regs[i];
311 } else {
312 for (i = 0; i < dev->num_addrs; i++) {
313 int rnum = regs[i];
314 if (rnum >= dev->parent->num_addrs) {
315 prom_printf("UGH: property for %s was %d, need < %d\n",
316 dp->name, len, dev->parent->num_addrs);
317 prom_halt();
318 }
319 dev->resource[i].start = dev->parent->resource[i].start;
320 dev->resource[i].end = dev->parent->resource[i].end;
321 dev->resource[i].flags = IORESOURCE_MEM;
322 dev->resource[i].name = dp->name;
323 }
324 }
325
326 op = of_find_device_by_node(dp);
327 if (!op) {
328 dev->num_irqs = 0;
329 } else {
330 dev->num_irqs = op->num_irqs;
331 for (i = 0; i < dev->num_irqs; i++)
332 dev->irqs[i] = op->irqs[i];
333 }
334
335 if (!dev->num_irqs) {
336 /*
337 * Oh, well, some PROMs don't export interrupts
338 * property to children of EBus devices...
339 *
340 * Be smart about PS/2 keyboard and mouse.
341 */
342 if (!strcmp(dev->parent->prom_node->name, "8042")) {
343 if (!strcmp(dev->prom_node->name, "kb_ps2")) {
344 dev->num_irqs = 1;
345 dev->irqs[0] = dev->parent->irqs[0];
346 } else {
347 dev->num_irqs = 1;
348 dev->irqs[0] = dev->parent->irqs[1];
349 }
350 }
351 }
352}
353
354static int __init child_regs_nonstandard(struct linux_ebus_device *dev)
355{
356 if (!strcmp(dev->prom_node->name, "i2c") ||
357 !strcmp(dev->prom_node->name, "SUNW,lombus"))
358 return 1;
359 return 0;
360}
361
362static void __init fill_ebus_device(struct device_node *dp, struct linux_ebus_device *dev)
363{
364 struct linux_ebus_child *child;
365 struct dev_archdata *sd;
366 struct of_device *op;
367 int i, len;
368
369 dev->prom_node = dp;
370
371 printk(" [%s", dp->name);
372
373 op = of_find_device_by_node(dp);
374 if (!op) {
375 dev->num_addrs = 0;
376 dev->num_irqs = 0;
377 } else {
378 const int *regs = of_get_property(dp, "reg", &len);
379
380 if (!regs)
381 len = 0;
382 dev->num_addrs = len / sizeof(struct linux_prom_registers);
383
384 for (i = 0; i < dev->num_addrs; i++)
385 memcpy(&dev->resource[i],
386 &op->resource[i],
387 sizeof(struct resource));
388
389 dev->num_irqs = op->num_irqs;
390 for (i = 0; i < dev->num_irqs; i++)
391 dev->irqs[i] = op->irqs[i];
392 }
393
394 sd = &dev->ofdev.dev.archdata;
395 sd->prom_node = dp;
396 sd->op = &dev->ofdev;
397 sd->iommu = dev->bus->ofdev.dev.parent->archdata.iommu;
398 sd->stc = dev->bus->ofdev.dev.parent->archdata.stc;
399 sd->numa_node = dev->bus->ofdev.dev.parent->archdata.numa_node;
400
401 dev->ofdev.node = dp;
402 dev->ofdev.dev.parent = &dev->bus->ofdev.dev;
403 dev->ofdev.dev.bus = &ebus_bus_type;
404 dev_set_name(&dev->ofdev.dev, "ebus[%08x]", dp->node);
405
406 /* Register with core */
407 if (of_device_register(&dev->ofdev) != 0)
408 printk(KERN_DEBUG "ebus: device registration error for %s!\n",
409 dp->path_component_name);
410
411 dp = dp->child;
412 if (dp) {
413 printk(" ->");
414 dev->children = ebus_alloc(sizeof(struct linux_ebus_child));
415
416 child = dev->children;
417 child->next = NULL;
418 child->parent = dev;
419 child->bus = dev->bus;
420 fill_ebus_child(dp, child,
421 child_regs_nonstandard(dev));
422
423 while ((dp = dp->sibling) != NULL) {
424 child->next = ebus_alloc(sizeof(struct linux_ebus_child));
425
426 child = child->next;
427 child->next = NULL;
428 child->parent = dev;
429 child->bus = dev->bus;
430 fill_ebus_child(dp, child,
431 child_regs_nonstandard(dev));
432 }
433 }
434 printk("]");
435}
436
437static struct pci_dev *find_next_ebus(struct pci_dev *start, int *is_rio_p)
438{
439 struct pci_dev *pdev = start;
440
441 while ((pdev = pci_get_device(PCI_VENDOR_ID_SUN, PCI_ANY_ID, pdev)))
442 if (pdev->device == PCI_DEVICE_ID_SUN_EBUS ||
443 pdev->device == PCI_DEVICE_ID_SUN_RIO_EBUS)
444 break;
445
446 *is_rio_p = !!(pdev && (pdev->device == PCI_DEVICE_ID_SUN_RIO_EBUS));
447
448 return pdev;
449}
450
451void __init ebus_init(void)
452{
453 struct linux_ebus_device *dev;
454 struct linux_ebus *ebus;
455 struct pci_dev *pdev;
456 struct device_node *dp;
457 int is_rio;
458 int num_ebus = 0;
459
460 pdev = find_next_ebus(NULL, &is_rio);
461 if (!pdev) {
462 printk("ebus: No EBus's found.\n");
463 return;
464 }
465
466 dp = pci_device_to_OF_node(pdev);
467
468 ebus_chain = ebus = ebus_alloc(sizeof(struct linux_ebus));
469 ebus->next = NULL;
470 ebus->is_rio = is_rio;
471
472 while (dp) {
473 struct device_node *child;
474
475 /* SUNW,pci-qfe uses four empty ebuses on it.
476 I think we should not consider them here,
477 as they have half of the properties this
478 code expects and once we do PCI hot-plug,
479 we'd have to tweak with the ebus_chain
480 in the runtime after initialization. -jj */
481 if (!dp->child) {
482 pdev = find_next_ebus(pdev, &is_rio);
483 if (!pdev) {
484 if (ebus == ebus_chain) {
485 ebus_chain = NULL;
486 printk("ebus: No EBus's found.\n");
487 return;
488 }
489 break;
490 }
491 ebus->is_rio = is_rio;
492 dp = pci_device_to_OF_node(pdev);
493 continue;
494 }
495 printk("ebus%d:", num_ebus);
496
497 ebus->index = num_ebus;
498 ebus->prom_node = dp;
499 ebus->self = pdev;
500
501 ebus->ofdev.node = dp;
502 ebus->ofdev.dev.parent = &pdev->dev;
503 ebus->ofdev.dev.bus = &ebus_bus_type;
504 dev_set_name(&ebus->ofdev.dev, "ebus%d", num_ebus);
505
506 /* Register with core */
507 if (of_device_register(&ebus->ofdev) != 0)
508 printk(KERN_DEBUG "ebus: device registration error for %s!\n",
509 dp->path_component_name);
510
511
512 child = dp->child;
513 if (!child)
514 goto next_ebus;
515
516 ebus->devices = ebus_alloc(sizeof(struct linux_ebus_device));
517
518 dev = ebus->devices;
519 dev->next = NULL;
520 dev->children = NULL;
521 dev->bus = ebus;
522 fill_ebus_device(child, dev);
523
524 while ((child = child->sibling) != NULL) {
525 dev->next = ebus_alloc(sizeof(struct linux_ebus_device));
526
527 dev = dev->next;
528 dev->next = NULL;
529 dev->children = NULL;
530 dev->bus = ebus;
531 fill_ebus_device(child, dev);
532 }
533
534 next_ebus:
535 printk("\n");
536
537 pdev = find_next_ebus(pdev, &is_rio);
538 if (!pdev)
539 break;
540
541 dp = pci_device_to_OF_node(pdev);
542
543 ebus->next = ebus_alloc(sizeof(struct linux_ebus));
544 ebus = ebus->next;
545 ebus->next = NULL;
546 ebus->is_rio = is_rio;
547 ++num_ebus;
548 }
549 pci_dev_put(pdev); /* XXX for the case, when ebusnd is 0, is it OK? */
550}
diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h
index fc294a29289..34d7ab5e10d 100644
--- a/arch/sparc64/kernel/entry.h
+++ b/arch/sparc64/kernel/entry.h
@@ -5,8 +5,8 @@
5#include <linux/types.h> 5#include <linux/types.h>
6#include <linux/init.h> 6#include <linux/init.h>
7 7
8extern char *sparc_cpu_type; 8extern const char *sparc_cpu_type;
9extern char *sparc_fpu_type; 9extern const char *sparc_fpu_type;
10 10
11extern void __init per_cpu_patch(void); 11extern void __init per_cpu_patch(void);
12extern void __init sun4v_patch(void); 12extern void __init sun4v_patch(void);
@@ -22,7 +22,8 @@ extern void do_notify_resume(struct pt_regs *regs,
22 unsigned long orig_i0, 22 unsigned long orig_i0,
23 unsigned long thread_info_flags); 23 unsigned long thread_info_flags);
24 24
25extern asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p); 25extern asmlinkage int syscall_trace_enter(struct pt_regs *regs);
26extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
26 27
27extern void bad_trap_tl1(struct pt_regs *regs, long lvl); 28extern void bad_trap_tl1(struct pt_regs *regs, long lvl);
28 29
diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index c9afef093d5..353226fa023 100644
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -10,6 +10,7 @@
10#include <linux/errno.h> 10#include <linux/errno.h>
11#include <linux/threads.h> 11#include <linux/threads.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/linkage.h>
13#include <asm/thread_info.h> 14#include <asm/thread_info.h>
14#include <asm/asi.h> 15#include <asm/asi.h>
15#include <asm/pstate.h> 16#include <asm/pstate.h>
diff --git a/arch/sparc64/kernel/hvapi.c b/arch/sparc64/kernel/hvapi.c
index 691760b5b01..1d272c3b574 100644
--- a/arch/sparc64/kernel/hvapi.c
+++ b/arch/sparc64/kernel/hvapi.c
@@ -9,7 +9,6 @@
9 9
10#include <asm/hypervisor.h> 10#include <asm/hypervisor.h>
11#include <asm/oplib.h> 11#include <asm/oplib.h>
12#include <asm/sstate.h>
13 12
14/* If the hypervisor indicates that the API setting 13/* If the hypervisor indicates that the API setting
15 * calls are unsupported, by returning HV_EBADTRAP or 14 * calls are unsupported, by returning HV_EBADTRAP or
@@ -184,8 +183,6 @@ void __init sun4v_hvapi_init(void)
184 if (sun4v_hvapi_register(group, major, &minor)) 183 if (sun4v_hvapi_register(group, major, &minor))
185 goto bad; 184 goto bad;
186 185
187 sun4v_sstate_init();
188
189 return; 186 return;
190 187
191bad: 188bad:
diff --git a/arch/sparc64/kernel/hvcalls.S b/arch/sparc64/kernel/hvcalls.S
index a2810f3ac70..e066269d159 100644
--- a/arch/sparc64/kernel/hvcalls.S
+++ b/arch/sparc64/kernel/hvcalls.S
@@ -3,89 +3,75 @@
3 * 3 *
4 * returns %o0: sysino 4 * returns %o0: sysino
5 */ 5 */
6 .globl sun4v_devino_to_sysino 6ENTRY(sun4v_devino_to_sysino)
7 .type sun4v_devino_to_sysino,#function
8sun4v_devino_to_sysino:
9 mov HV_FAST_INTR_DEVINO2SYSINO, %o5 7 mov HV_FAST_INTR_DEVINO2SYSINO, %o5
10 ta HV_FAST_TRAP 8 ta HV_FAST_TRAP
11 retl 9 retl
12 mov %o1, %o0 10 mov %o1, %o0
13 .size sun4v_devino_to_sysino, .-sun4v_devino_to_sysino 11ENDPROC(sun4v_devino_to_sysino)
14 12
15 /* %o0: sysino 13 /* %o0: sysino
16 * 14 *
17 * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED}) 15 * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
18 */ 16 */
19 .globl sun4v_intr_getenabled 17ENTRY(sun4v_intr_getenabled)
20 .type sun4v_intr_getenabled,#function
21sun4v_intr_getenabled:
22 mov HV_FAST_INTR_GETENABLED, %o5 18 mov HV_FAST_INTR_GETENABLED, %o5
23 ta HV_FAST_TRAP 19 ta HV_FAST_TRAP
24 retl 20 retl
25 mov %o1, %o0 21 mov %o1, %o0
26 .size sun4v_intr_getenabled, .-sun4v_intr_getenabled 22ENDPROC(sun4v_intr_getenabled)
27 23
28 /* %o0: sysino 24 /* %o0: sysino
29 * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED}) 25 * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
30 */ 26 */
31 .globl sun4v_intr_setenabled 27ENTRY(sun4v_intr_setenabled)
32 .type sun4v_intr_setenabled,#function
33sun4v_intr_setenabled:
34 mov HV_FAST_INTR_SETENABLED, %o5 28 mov HV_FAST_INTR_SETENABLED, %o5
35 ta HV_FAST_TRAP 29 ta HV_FAST_TRAP
36 retl 30 retl
37 nop 31 nop
38 .size sun4v_intr_setenabled, .-sun4v_intr_setenabled 32ENDPROC(sun4v_intr_setenabled)
39 33
40 /* %o0: sysino 34 /* %o0: sysino
41 * 35 *
42 * returns %o0: intr_state (HV_INTR_STATE_*) 36 * returns %o0: intr_state (HV_INTR_STATE_*)
43 */ 37 */
44 .globl sun4v_intr_getstate 38ENTRY(sun4v_intr_getstate)
45 .type sun4v_intr_getstate,#function
46sun4v_intr_getstate:
47 mov HV_FAST_INTR_GETSTATE, %o5 39 mov HV_FAST_INTR_GETSTATE, %o5
48 ta HV_FAST_TRAP 40 ta HV_FAST_TRAP
49 retl 41 retl
50 mov %o1, %o0 42 mov %o1, %o0
51 .size sun4v_intr_getstate, .-sun4v_intr_getstate 43ENDPROC(sun4v_intr_getstate)
52 44
53 /* %o0: sysino 45 /* %o0: sysino
54 * %o1: intr_state (HV_INTR_STATE_*) 46 * %o1: intr_state (HV_INTR_STATE_*)
55 */ 47 */
56 .globl sun4v_intr_setstate 48ENTRY(sun4v_intr_setstate)
57 .type sun4v_intr_setstate,#function
58sun4v_intr_setstate:
59 mov HV_FAST_INTR_SETSTATE, %o5 49 mov HV_FAST_INTR_SETSTATE, %o5
60 ta HV_FAST_TRAP 50 ta HV_FAST_TRAP
61 retl 51 retl
62 nop 52 nop
63 .size sun4v_intr_setstate, .-sun4v_intr_setstate 53ENDPROC(sun4v_intr_setstate)
64 54
65 /* %o0: sysino 55 /* %o0: sysino
66 * 56 *
67 * returns %o0: cpuid 57 * returns %o0: cpuid
68 */ 58 */
69 .globl sun4v_intr_gettarget 59ENTRY(sun4v_intr_gettarget)
70 .type sun4v_intr_gettarget,#function
71sun4v_intr_gettarget:
72 mov HV_FAST_INTR_GETTARGET, %o5 60 mov HV_FAST_INTR_GETTARGET, %o5
73 ta HV_FAST_TRAP 61 ta HV_FAST_TRAP
74 retl 62 retl
75 mov %o1, %o0 63 mov %o1, %o0
76 .size sun4v_intr_gettarget, .-sun4v_intr_gettarget 64ENDPROC(sun4v_intr_gettarget)
77 65
78 /* %o0: sysino 66 /* %o0: sysino
79 * %o1: cpuid 67 * %o1: cpuid
80 */ 68 */
81 .globl sun4v_intr_settarget 69ENTRY(sun4v_intr_settarget)
82 .type sun4v_intr_settarget,#function
83sun4v_intr_settarget:
84 mov HV_FAST_INTR_SETTARGET, %o5 70 mov HV_FAST_INTR_SETTARGET, %o5
85 ta HV_FAST_TRAP 71 ta HV_FAST_TRAP
86 retl 72 retl
87 nop 73 nop
88 .size sun4v_intr_settarget, .-sun4v_intr_settarget 74ENDPROC(sun4v_intr_settarget)
89 75
90 /* %o0: cpuid 76 /* %o0: cpuid
91 * %o1: pc 77 * %o1: pc
@@ -94,37 +80,31 @@ sun4v_intr_settarget:
94 * 80 *
95 * returns %o0: status 81 * returns %o0: status
96 */ 82 */
97 .globl sun4v_cpu_start 83ENTRY(sun4v_cpu_start)
98 .type sun4v_cpu_start,#function
99sun4v_cpu_start:
100 mov HV_FAST_CPU_START, %o5 84 mov HV_FAST_CPU_START, %o5
101 ta HV_FAST_TRAP 85 ta HV_FAST_TRAP
102 retl 86 retl
103 nop 87 nop
104 .size sun4v_cpu_start, .-sun4v_cpu_start 88ENDPROC(sun4v_cpu_start)
105 89
106 /* %o0: cpuid 90 /* %o0: cpuid
107 * 91 *
108 * returns %o0: status 92 * returns %o0: status
109 */ 93 */
110 .globl sun4v_cpu_stop 94ENTRY(sun4v_cpu_stop)
111 .type sun4v_cpu_stop,#function
112sun4v_cpu_stop:
113 mov HV_FAST_CPU_STOP, %o5 95 mov HV_FAST_CPU_STOP, %o5
114 ta HV_FAST_TRAP 96 ta HV_FAST_TRAP
115 retl 97 retl
116 nop 98 nop
117 .size sun4v_cpu_stop, .-sun4v_cpu_stop 99ENDPROC(sun4v_cpu_stop)
118 100
119 /* returns %o0: status */ 101 /* returns %o0: status */
120 .globl sun4v_cpu_yield 102ENTRY(sun4v_cpu_yield)
121 .type sun4v_cpu_yield, #function
122sun4v_cpu_yield:
123 mov HV_FAST_CPU_YIELD, %o5 103 mov HV_FAST_CPU_YIELD, %o5
124 ta HV_FAST_TRAP 104 ta HV_FAST_TRAP
125 retl 105 retl
126 nop 106 nop
127 .size sun4v_cpu_yield, .-sun4v_cpu_yield 107ENDPROC(sun4v_cpu_yield)
128 108
129 /* %o0: type 109 /* %o0: type
130 * %o1: queue paddr 110 * %o1: queue paddr
@@ -132,14 +112,12 @@ sun4v_cpu_yield:
132 * 112 *
133 * returns %o0: status 113 * returns %o0: status
134 */ 114 */
135 .globl sun4v_cpu_qconf 115ENTRY(sun4v_cpu_qconf)
136 .type sun4v_cpu_qconf,#function
137sun4v_cpu_qconf:
138 mov HV_FAST_CPU_QCONF, %o5 116 mov HV_FAST_CPU_QCONF, %o5
139 ta HV_FAST_TRAP 117 ta HV_FAST_TRAP
140 retl 118 retl
141 nop 119 nop
142 .size sun4v_cpu_qconf, .-sun4v_cpu_qconf 120ENDPROC(sun4v_cpu_qconf)
143 121
144 /* %o0: num cpus in cpu list 122 /* %o0: num cpus in cpu list
145 * %o1: cpu list paddr 123 * %o1: cpu list paddr
@@ -147,23 +125,19 @@ sun4v_cpu_qconf:
147 * 125 *
148 * returns %o0: status 126 * returns %o0: status
149 */ 127 */
150 .globl sun4v_cpu_mondo_send 128ENTRY(sun4v_cpu_mondo_send)
151 .type sun4v_cpu_mondo_send,#function
152sun4v_cpu_mondo_send:
153 mov HV_FAST_CPU_MONDO_SEND, %o5 129 mov HV_FAST_CPU_MONDO_SEND, %o5
154 ta HV_FAST_TRAP 130 ta HV_FAST_TRAP
155 retl 131 retl
156 nop 132 nop
157 .size sun4v_cpu_mondo_send, .-sun4v_cpu_mondo_send 133ENDPROC(sun4v_cpu_mondo_send)
158 134
159 /* %o0: CPU ID 135 /* %o0: CPU ID
160 * 136 *
161 * returns %o0: -status if status non-zero, else 137 * returns %o0: -status if status non-zero, else
162 * %o0: cpu state as HV_CPU_STATE_* 138 * %o0: cpu state as HV_CPU_STATE_*
163 */ 139 */
164 .globl sun4v_cpu_state 140ENTRY(sun4v_cpu_state)
165 .type sun4v_cpu_state,#function
166sun4v_cpu_state:
167 mov HV_FAST_CPU_STATE, %o5 141 mov HV_FAST_CPU_STATE, %o5
168 ta HV_FAST_TRAP 142 ta HV_FAST_TRAP
169 brnz,pn %o0, 1f 143 brnz,pn %o0, 1f
@@ -171,7 +145,7 @@ sun4v_cpu_state:
171 mov %o1, %o0 145 mov %o1, %o0
1721: retl 1461: retl
173 nop 147 nop
174 .size sun4v_cpu_state, .-sun4v_cpu_state 148ENDPROC(sun4v_cpu_state)
175 149
176 /* %o0: virtual address 150 /* %o0: virtual address
177 * %o1: must be zero 151 * %o1: must be zero
@@ -180,28 +154,24 @@ sun4v_cpu_state:
180 * 154 *
181 * returns %o0: status 155 * returns %o0: status
182 */ 156 */
183 .globl sun4v_mmu_map_perm_addr 157ENTRY(sun4v_mmu_map_perm_addr)
184 .type sun4v_mmu_map_perm_addr,#function
185sun4v_mmu_map_perm_addr:
186 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 158 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
187 ta HV_FAST_TRAP 159 ta HV_FAST_TRAP
188 retl 160 retl
189 nop 161 nop
190 .size sun4v_mmu_map_perm_addr, .-sun4v_mmu_map_perm_addr 162ENDPROC(sun4v_mmu_map_perm_addr)
191 163
192 /* %o0: number of TSB descriptions 164 /* %o0: number of TSB descriptions
193 * %o1: TSB descriptions real address 165 * %o1: TSB descriptions real address
194 * 166 *
195 * returns %o0: status 167 * returns %o0: status
196 */ 168 */
197 .globl sun4v_mmu_tsb_ctx0 169ENTRY(sun4v_mmu_tsb_ctx0)
198 .type sun4v_mmu_tsb_ctx0,#function
199sun4v_mmu_tsb_ctx0:
200 mov HV_FAST_MMU_TSB_CTX0, %o5 170 mov HV_FAST_MMU_TSB_CTX0, %o5
201 ta HV_FAST_TRAP 171 ta HV_FAST_TRAP
202 retl 172 retl
203 nop 173 nop
204 .size sun4v_mmu_tsb_ctx0, .-sun4v_mmu_tsb_ctx0 174ENDPROC(sun4v_mmu_tsb_ctx0)
205 175
206 /* %o0: API group number 176 /* %o0: API group number
207 * %o1: pointer to unsigned long major number storage 177 * %o1: pointer to unsigned long major number storage
@@ -209,9 +179,7 @@ sun4v_mmu_tsb_ctx0:
209 * 179 *
210 * returns %o0: status 180 * returns %o0: status
211 */ 181 */
212 .globl sun4v_get_version 182ENTRY(sun4v_get_version)
213 .type sun4v_get_version,#function
214sun4v_get_version:
215 mov HV_CORE_GET_VER, %o5 183 mov HV_CORE_GET_VER, %o5
216 mov %o1, %o3 184 mov %o1, %o3
217 mov %o2, %o4 185 mov %o2, %o4
@@ -219,7 +187,7 @@ sun4v_get_version:
219 stx %o1, [%o3] 187 stx %o1, [%o3]
220 retl 188 retl
221 stx %o2, [%o4] 189 stx %o2, [%o4]
222 .size sun4v_get_version, .-sun4v_get_version 190ENDPROC(sun4v_get_version)
223 191
224 /* %o0: API group number 192 /* %o0: API group number
225 * %o1: desired major number 193 * %o1: desired major number
@@ -228,51 +196,43 @@ sun4v_get_version:
228 * 196 *
229 * returns %o0: status 197 * returns %o0: status
230 */ 198 */
231 .globl sun4v_set_version 199ENTRY(sun4v_set_version)
232 .type sun4v_set_version,#function
233sun4v_set_version:
234 mov HV_CORE_SET_VER, %o5 200 mov HV_CORE_SET_VER, %o5
235 mov %o3, %o4 201 mov %o3, %o4
236 ta HV_CORE_TRAP 202 ta HV_CORE_TRAP
237 retl 203 retl
238 stx %o1, [%o4] 204 stx %o1, [%o4]
239 .size sun4v_set_version, .-sun4v_set_version 205ENDPROC(sun4v_set_version)
240 206
241 /* %o0: pointer to unsigned long time 207 /* %o0: pointer to unsigned long time
242 * 208 *
243 * returns %o0: status 209 * returns %o0: status
244 */ 210 */
245 .globl sun4v_tod_get 211ENTRY(sun4v_tod_get)
246 .type sun4v_tod_get,#function
247sun4v_tod_get:
248 mov %o0, %o4 212 mov %o0, %o4
249 mov HV_FAST_TOD_GET, %o5 213 mov HV_FAST_TOD_GET, %o5
250 ta HV_FAST_TRAP 214 ta HV_FAST_TRAP
251 stx %o1, [%o4] 215 stx %o1, [%o4]
252 retl 216 retl
253 nop 217 nop
254 .size sun4v_tod_get, .-sun4v_tod_get 218ENDPROC(sun4v_tod_get)
255 219
256 /* %o0: time 220 /* %o0: time
257 * 221 *
258 * returns %o0: status 222 * returns %o0: status
259 */ 223 */
260 .globl sun4v_tod_set 224ENTRY(sun4v_tod_set)
261 .type sun4v_tod_set,#function
262sun4v_tod_set:
263 mov HV_FAST_TOD_SET, %o5 225 mov HV_FAST_TOD_SET, %o5
264 ta HV_FAST_TRAP 226 ta HV_FAST_TRAP
265 retl 227 retl
266 nop 228 nop
267 .size sun4v_tod_set, .-sun4v_tod_set 229ENDPROC(sun4v_tod_set)
268 230
269 /* %o0: pointer to unsigned long status 231 /* %o0: pointer to unsigned long status
270 * 232 *
271 * returns %o0: signed character 233 * returns %o0: signed character
272 */ 234 */
273 .globl sun4v_con_getchar 235ENTRY(sun4v_con_getchar)
274 .type sun4v_con_getchar,#function
275sun4v_con_getchar:
276 mov %o0, %o4 236 mov %o0, %o4
277 mov HV_FAST_CONS_GETCHAR, %o5 237 mov HV_FAST_CONS_GETCHAR, %o5
278 clr %o0 238 clr %o0
@@ -281,20 +241,18 @@ sun4v_con_getchar:
281 stx %o0, [%o4] 241 stx %o0, [%o4]
282 retl 242 retl
283 sra %o1, 0, %o0 243 sra %o1, 0, %o0
284 .size sun4v_con_getchar, .-sun4v_con_getchar 244ENDPROC(sun4v_con_getchar)
285 245
286 /* %o0: signed long character 246 /* %o0: signed long character
287 * 247 *
288 * returns %o0: status 248 * returns %o0: status
289 */ 249 */
290 .globl sun4v_con_putchar 250ENTRY(sun4v_con_putchar)
291 .type sun4v_con_putchar,#function
292sun4v_con_putchar:
293 mov HV_FAST_CONS_PUTCHAR, %o5 251 mov HV_FAST_CONS_PUTCHAR, %o5
294 ta HV_FAST_TRAP 252 ta HV_FAST_TRAP
295 retl 253 retl
296 sra %o0, 0, %o0 254 sra %o0, 0, %o0
297 .size sun4v_con_putchar, .-sun4v_con_putchar 255ENDPROC(sun4v_con_putchar)
298 256
299 /* %o0: buffer real address 257 /* %o0: buffer real address
300 * %o1: buffer size 258 * %o1: buffer size
@@ -302,9 +260,7 @@ sun4v_con_putchar:
302 * 260 *
303 * returns %o0: status 261 * returns %o0: status
304 */ 262 */
305 .globl sun4v_con_read 263ENTRY(sun4v_con_read)
306 .type sun4v_con_read,#function
307sun4v_con_read:
308 mov %o2, %o4 264 mov %o2, %o4
309 mov HV_FAST_CONS_READ, %o5 265 mov HV_FAST_CONS_READ, %o5
310 ta HV_FAST_TRAP 266 ta HV_FAST_TRAP
@@ -318,7 +274,7 @@ sun4v_con_read:
318 stx %o1, [%o4] 274 stx %o1, [%o4]
3191: retl 2751: retl
320 nop 276 nop
321 .size sun4v_con_read, .-sun4v_con_read 277ENDPROC(sun4v_con_read)
322 278
323 /* %o0: buffer real address 279 /* %o0: buffer real address
324 * %o1: buffer size 280 * %o1: buffer size
@@ -326,43 +282,37 @@ sun4v_con_read:
326 * 282 *
327 * returns %o0: status 283 * returns %o0: status
328 */ 284 */
329 .globl sun4v_con_write 285ENTRY(sun4v_con_write)
330 .type sun4v_con_write,#function
331sun4v_con_write:
332 mov %o2, %o4 286 mov %o2, %o4
333 mov HV_FAST_CONS_WRITE, %o5 287 mov HV_FAST_CONS_WRITE, %o5
334 ta HV_FAST_TRAP 288 ta HV_FAST_TRAP
335 stx %o1, [%o4] 289 stx %o1, [%o4]
336 retl 290 retl
337 nop 291 nop
338 .size sun4v_con_write, .-sun4v_con_write 292ENDPROC(sun4v_con_write)
339 293
340 /* %o0: soft state 294 /* %o0: soft state
341 * %o1: address of description string 295 * %o1: address of description string
342 * 296 *
343 * returns %o0: status 297 * returns %o0: status
344 */ 298 */
345 .globl sun4v_mach_set_soft_state 299ENTRY(sun4v_mach_set_soft_state)
346 .type sun4v_mach_set_soft_state,#function
347sun4v_mach_set_soft_state:
348 mov HV_FAST_MACH_SET_SOFT_STATE, %o5 300 mov HV_FAST_MACH_SET_SOFT_STATE, %o5
349 ta HV_FAST_TRAP 301 ta HV_FAST_TRAP
350 retl 302 retl
351 nop 303 nop
352 .size sun4v_mach_set_soft_state, .-sun4v_mach_set_soft_state 304ENDPROC(sun4v_mach_set_soft_state)
353 305
354 /* %o0: exit code 306 /* %o0: exit code
355 * 307 *
356 * Does not return. 308 * Does not return.
357 */ 309 */
358 .globl sun4v_mach_exit 310ENTRY(sun4v_mach_exit)
359 .type sun4v_mach_exit,#function
360sun4v_mach_exit:
361 mov HV_FAST_MACH_EXIT, %o5 311 mov HV_FAST_MACH_EXIT, %o5
362 ta HV_FAST_TRAP 312 ta HV_FAST_TRAP
363 retl 313 retl
364 nop 314 nop
365 .size sun4v_mach_exit, .-sun4v_mach_exit 315ENDPROC(sun4v_mach_exit)
366 316
367 /* %o0: buffer real address 317 /* %o0: buffer real address
368 * %o1: buffer length 318 * %o1: buffer length
@@ -370,44 +320,38 @@ sun4v_mach_exit:
370 * 320 *
371 * returns %o0: status 321 * returns %o0: status
372 */ 322 */
373 .globl sun4v_mach_desc 323ENTRY(sun4v_mach_desc)
374 .type sun4v_mach_desc,#function
375sun4v_mach_desc:
376 mov %o2, %o4 324 mov %o2, %o4
377 mov HV_FAST_MACH_DESC, %o5 325 mov HV_FAST_MACH_DESC, %o5
378 ta HV_FAST_TRAP 326 ta HV_FAST_TRAP
379 stx %o1, [%o4] 327 stx %o1, [%o4]
380 retl 328 retl
381 nop 329 nop
382 .size sun4v_mach_desc, .-sun4v_mach_desc 330ENDPROC(sun4v_mach_desc)
383 331
384 /* %o0: new timeout in milliseconds 332 /* %o0: new timeout in milliseconds
385 * %o1: pointer to unsigned long orig_timeout 333 * %o1: pointer to unsigned long orig_timeout
386 * 334 *
387 * returns %o0: status 335 * returns %o0: status
388 */ 336 */
389 .globl sun4v_mach_set_watchdog 337ENTRY(sun4v_mach_set_watchdog)
390 .type sun4v_mach_set_watchdog,#function
391sun4v_mach_set_watchdog:
392 mov %o1, %o4 338 mov %o1, %o4
393 mov HV_FAST_MACH_SET_WATCHDOG, %o5 339 mov HV_FAST_MACH_SET_WATCHDOG, %o5
394 ta HV_FAST_TRAP 340 ta HV_FAST_TRAP
395 stx %o1, [%o4] 341 stx %o1, [%o4]
396 retl 342 retl
397 nop 343 nop
398 .size sun4v_mach_set_watchdog, .-sun4v_mach_set_watchdog 344ENDPROC(sun4v_mach_set_watchdog)
399 345
400 /* No inputs and does not return. */ 346 /* No inputs and does not return. */
401 .globl sun4v_mach_sir 347ENTRY(sun4v_mach_sir)
402 .type sun4v_mach_sir,#function
403sun4v_mach_sir:
404 mov %o1, %o4 348 mov %o1, %o4
405 mov HV_FAST_MACH_SIR, %o5 349 mov HV_FAST_MACH_SIR, %o5
406 ta HV_FAST_TRAP 350 ta HV_FAST_TRAP
407 stx %o1, [%o4] 351 stx %o1, [%o4]
408 retl 352 retl
409 nop 353 nop
410 .size sun4v_mach_sir, .-sun4v_mach_sir 354ENDPROC(sun4v_mach_sir)
411 355
412 /* %o0: channel 356 /* %o0: channel
413 * %o1: ra 357 * %o1: ra
@@ -415,14 +359,12 @@ sun4v_mach_sir:
415 * 359 *
416 * returns %o0: status 360 * returns %o0: status
417 */ 361 */
418 .globl sun4v_ldc_tx_qconf 362ENTRY(sun4v_ldc_tx_qconf)
419 .type sun4v_ldc_tx_qconf,#function
420sun4v_ldc_tx_qconf:
421 mov HV_FAST_LDC_TX_QCONF, %o5 363 mov HV_FAST_LDC_TX_QCONF, %o5
422 ta HV_FAST_TRAP 364 ta HV_FAST_TRAP
423 retl 365 retl
424 nop 366 nop
425 .size sun4v_ldc_tx_qconf, .-sun4v_ldc_tx_qconf 367ENDPROC(sun4v_ldc_tx_qconf)
426 368
427 /* %o0: channel 369 /* %o0: channel
428 * %o1: pointer to unsigned long ra 370 * %o1: pointer to unsigned long ra
@@ -430,9 +372,7 @@ sun4v_ldc_tx_qconf:
430 * 372 *
431 * returns %o0: status 373 * returns %o0: status
432 */ 374 */
433 .globl sun4v_ldc_tx_qinfo 375ENTRY(sun4v_ldc_tx_qinfo)
434 .type sun4v_ldc_tx_qinfo,#function
435sun4v_ldc_tx_qinfo:
436 mov %o1, %g1 376 mov %o1, %g1
437 mov %o2, %g2 377 mov %o2, %g2
438 mov HV_FAST_LDC_TX_QINFO, %o5 378 mov HV_FAST_LDC_TX_QINFO, %o5
@@ -441,7 +381,7 @@ sun4v_ldc_tx_qinfo:
441 stx %o2, [%g2] 381 stx %o2, [%g2]
442 retl 382 retl
443 nop 383 nop
444 .size sun4v_ldc_tx_qinfo, .-sun4v_ldc_tx_qinfo 384ENDPROC(sun4v_ldc_tx_qinfo)
445 385
446 /* %o0: channel 386 /* %o0: channel
447 * %o1: pointer to unsigned long head_off 387 * %o1: pointer to unsigned long head_off
@@ -450,9 +390,7 @@ sun4v_ldc_tx_qinfo:
450 * 390 *
451 * returns %o0: status 391 * returns %o0: status
452 */ 392 */
453 .globl sun4v_ldc_tx_get_state 393ENTRY(sun4v_ldc_tx_get_state)
454 .type sun4v_ldc_tx_get_state,#function
455sun4v_ldc_tx_get_state:
456 mov %o1, %g1 394 mov %o1, %g1
457 mov %o2, %g2 395 mov %o2, %g2
458 mov %o3, %g3 396 mov %o3, %g3
@@ -463,21 +401,19 @@ sun4v_ldc_tx_get_state:
463 stx %o3, [%g3] 401 stx %o3, [%g3]
464 retl 402 retl
465 nop 403 nop
466 .size sun4v_ldc_tx_get_state, .-sun4v_ldc_tx_get_state 404ENDPROC(sun4v_ldc_tx_get_state)
467 405
468 /* %o0: channel 406 /* %o0: channel
469 * %o1: tail_off 407 * %o1: tail_off
470 * 408 *
471 * returns %o0: status 409 * returns %o0: status
472 */ 410 */
473 .globl sun4v_ldc_tx_set_qtail 411ENTRY(sun4v_ldc_tx_set_qtail)
474 .type sun4v_ldc_tx_set_qtail,#function
475sun4v_ldc_tx_set_qtail:
476 mov HV_FAST_LDC_TX_SET_QTAIL, %o5 412 mov HV_FAST_LDC_TX_SET_QTAIL, %o5
477 ta HV_FAST_TRAP 413 ta HV_FAST_TRAP
478 retl 414 retl
479 nop 415 nop
480 .size sun4v_ldc_tx_set_qtail, .-sun4v_ldc_tx_set_qtail 416ENDPROC(sun4v_ldc_tx_set_qtail)
481 417
482 /* %o0: channel 418 /* %o0: channel
483 * %o1: ra 419 * %o1: ra
@@ -485,14 +421,12 @@ sun4v_ldc_tx_set_qtail:
485 * 421 *
486 * returns %o0: status 422 * returns %o0: status
487 */ 423 */
488 .globl sun4v_ldc_rx_qconf 424ENTRY(sun4v_ldc_rx_qconf)
489 .type sun4v_ldc_rx_qconf,#function
490sun4v_ldc_rx_qconf:
491 mov HV_FAST_LDC_RX_QCONF, %o5 425 mov HV_FAST_LDC_RX_QCONF, %o5
492 ta HV_FAST_TRAP 426 ta HV_FAST_TRAP
493 retl 427 retl
494 nop 428 nop
495 .size sun4v_ldc_rx_qconf, .-sun4v_ldc_rx_qconf 429ENDPROC(sun4v_ldc_rx_qconf)
496 430
497 /* %o0: channel 431 /* %o0: channel
498 * %o1: pointer to unsigned long ra 432 * %o1: pointer to unsigned long ra
@@ -500,9 +434,7 @@ sun4v_ldc_rx_qconf:
500 * 434 *
501 * returns %o0: status 435 * returns %o0: status
502 */ 436 */
503 .globl sun4v_ldc_rx_qinfo 437ENTRY(sun4v_ldc_rx_qinfo)
504 .type sun4v_ldc_rx_qinfo,#function
505sun4v_ldc_rx_qinfo:
506 mov %o1, %g1 438 mov %o1, %g1
507 mov %o2, %g2 439 mov %o2, %g2
508 mov HV_FAST_LDC_RX_QINFO, %o5 440 mov HV_FAST_LDC_RX_QINFO, %o5
@@ -511,7 +443,7 @@ sun4v_ldc_rx_qinfo:
511 stx %o2, [%g2] 443 stx %o2, [%g2]
512 retl 444 retl
513 nop 445 nop
514 .size sun4v_ldc_rx_qinfo, .-sun4v_ldc_rx_qinfo 446ENDPROC(sun4v_ldc_rx_qinfo)
515 447
516 /* %o0: channel 448 /* %o0: channel
517 * %o1: pointer to unsigned long head_off 449 * %o1: pointer to unsigned long head_off
@@ -520,9 +452,7 @@ sun4v_ldc_rx_qinfo:
520 * 452 *
521 * returns %o0: status 453 * returns %o0: status
522 */ 454 */
523 .globl sun4v_ldc_rx_get_state 455ENTRY(sun4v_ldc_rx_get_state)
524 .type sun4v_ldc_rx_get_state,#function
525sun4v_ldc_rx_get_state:
526 mov %o1, %g1 456 mov %o1, %g1
527 mov %o2, %g2 457 mov %o2, %g2
528 mov %o3, %g3 458 mov %o3, %g3
@@ -533,21 +463,19 @@ sun4v_ldc_rx_get_state:
533 stx %o3, [%g3] 463 stx %o3, [%g3]
534 retl 464 retl
535 nop 465 nop
536 .size sun4v_ldc_rx_get_state, .-sun4v_ldc_rx_get_state 466ENDPROC(sun4v_ldc_rx_get_state)
537 467
538 /* %o0: channel 468 /* %o0: channel
539 * %o1: head_off 469 * %o1: head_off
540 * 470 *
541 * returns %o0: status 471 * returns %o0: status
542 */ 472 */
543 .globl sun4v_ldc_rx_set_qhead 473ENTRY(sun4v_ldc_rx_set_qhead)
544 .type sun4v_ldc_rx_set_qhead,#function
545sun4v_ldc_rx_set_qhead:
546 mov HV_FAST_LDC_RX_SET_QHEAD, %o5 474 mov HV_FAST_LDC_RX_SET_QHEAD, %o5
547 ta HV_FAST_TRAP 475 ta HV_FAST_TRAP
548 retl 476 retl
549 nop 477 nop
550 .size sun4v_ldc_rx_set_qhead, .-sun4v_ldc_rx_set_qhead 478ENDPROC(sun4v_ldc_rx_set_qhead)
551 479
552 /* %o0: channel 480 /* %o0: channel
553 * %o1: ra 481 * %o1: ra
@@ -555,14 +483,12 @@ sun4v_ldc_rx_set_qhead:
555 * 483 *
556 * returns %o0: status 484 * returns %o0: status
557 */ 485 */
558 .globl sun4v_ldc_set_map_table 486ENTRY(sun4v_ldc_set_map_table)
559 .type sun4v_ldc_set_map_table,#function
560sun4v_ldc_set_map_table:
561 mov HV_FAST_LDC_SET_MAP_TABLE, %o5 487 mov HV_FAST_LDC_SET_MAP_TABLE, %o5
562 ta HV_FAST_TRAP 488 ta HV_FAST_TRAP
563 retl 489 retl
564 nop 490 nop
565 .size sun4v_ldc_set_map_table, .-sun4v_ldc_set_map_table 491ENDPROC(sun4v_ldc_set_map_table)
566 492
567 /* %o0: channel 493 /* %o0: channel
568 * %o1: pointer to unsigned long ra 494 * %o1: pointer to unsigned long ra
@@ -570,9 +496,7 @@ sun4v_ldc_set_map_table:
570 * 496 *
571 * returns %o0: status 497 * returns %o0: status
572 */ 498 */
573 .globl sun4v_ldc_get_map_table 499ENTRY(sun4v_ldc_get_map_table)
574 .type sun4v_ldc_get_map_table,#function
575sun4v_ldc_get_map_table:
576 mov %o1, %g1 500 mov %o1, %g1
577 mov %o2, %g2 501 mov %o2, %g2
578 mov HV_FAST_LDC_GET_MAP_TABLE, %o5 502 mov HV_FAST_LDC_GET_MAP_TABLE, %o5
@@ -581,7 +505,7 @@ sun4v_ldc_get_map_table:
581 stx %o2, [%g2] 505 stx %o2, [%g2]
582 retl 506 retl
583 nop 507 nop
584 .size sun4v_ldc_get_map_table, .-sun4v_ldc_get_map_table 508ENDPROC(sun4v_ldc_get_map_table)
585 509
586 /* %o0: channel 510 /* %o0: channel
587 * %o1: dir_code 511 * %o1: dir_code
@@ -592,16 +516,14 @@ sun4v_ldc_get_map_table:
592 * 516 *
593 * returns %o0: status 517 * returns %o0: status
594 */ 518 */
595 .globl sun4v_ldc_copy 519ENTRY(sun4v_ldc_copy)
596 .type sun4v_ldc_copy,#function
597sun4v_ldc_copy:
598 mov %o5, %g1 520 mov %o5, %g1
599 mov HV_FAST_LDC_COPY, %o5 521 mov HV_FAST_LDC_COPY, %o5
600 ta HV_FAST_TRAP 522 ta HV_FAST_TRAP
601 stx %o1, [%g1] 523 stx %o1, [%g1]
602 retl 524 retl
603 nop 525 nop
604 .size sun4v_ldc_copy, .-sun4v_ldc_copy 526ENDPROC(sun4v_ldc_copy)
605 527
606 /* %o0: channel 528 /* %o0: channel
607 * %o1: cookie 529 * %o1: cookie
@@ -610,9 +532,7 @@ sun4v_ldc_copy:
610 * 532 *
611 * returns %o0: status 533 * returns %o0: status
612 */ 534 */
613 .globl sun4v_ldc_mapin 535ENTRY(sun4v_ldc_mapin)
614 .type sun4v_ldc_mapin,#function
615sun4v_ldc_mapin:
616 mov %o2, %g1 536 mov %o2, %g1
617 mov %o3, %g2 537 mov %o3, %g2
618 mov HV_FAST_LDC_MAPIN, %o5 538 mov HV_FAST_LDC_MAPIN, %o5
@@ -621,20 +541,18 @@ sun4v_ldc_mapin:
621 stx %o2, [%g2] 541 stx %o2, [%g2]
622 retl 542 retl
623 nop 543 nop
624 .size sun4v_ldc_mapin, .-sun4v_ldc_mapin 544ENDPROC(sun4v_ldc_mapin)
625 545
626 /* %o0: ra 546 /* %o0: ra
627 * 547 *
628 * returns %o0: status 548 * returns %o0: status
629 */ 549 */
630 .globl sun4v_ldc_unmap 550ENTRY(sun4v_ldc_unmap)
631 .type sun4v_ldc_unmap,#function
632sun4v_ldc_unmap:
633 mov HV_FAST_LDC_UNMAP, %o5 551 mov HV_FAST_LDC_UNMAP, %o5
634 ta HV_FAST_TRAP 552 ta HV_FAST_TRAP
635 retl 553 retl
636 nop 554 nop
637 .size sun4v_ldc_unmap, .-sun4v_ldc_unmap 555ENDPROC(sun4v_ldc_unmap)
638 556
639 /* %o0: channel 557 /* %o0: channel
640 * %o1: cookie 558 * %o1: cookie
@@ -642,14 +560,12 @@ sun4v_ldc_unmap:
642 * 560 *
643 * returns %o0: status 561 * returns %o0: status
644 */ 562 */
645 .globl sun4v_ldc_revoke 563ENTRY(sun4v_ldc_revoke)
646 .type sun4v_ldc_revoke,#function
647sun4v_ldc_revoke:
648 mov HV_FAST_LDC_REVOKE, %o5 564 mov HV_FAST_LDC_REVOKE, %o5
649 ta HV_FAST_TRAP 565 ta HV_FAST_TRAP
650 retl 566 retl
651 nop 567 nop
652 .size sun4v_ldc_revoke, .-sun4v_ldc_revoke 568ENDPROC(sun4v_ldc_revoke)
653 569
654 /* %o0: device handle 570 /* %o0: device handle
655 * %o1: device INO 571 * %o1: device INO
@@ -657,16 +573,14 @@ sun4v_ldc_revoke:
657 * 573 *
658 * returns %o0: status 574 * returns %o0: status
659 */ 575 */
660 .globl sun4v_vintr_get_cookie 576ENTRY(sun4v_vintr_get_cookie)
661 .type sun4v_vintr_get_cookie,#function
662sun4v_vintr_get_cookie:
663 mov %o2, %g1 577 mov %o2, %g1
664 mov HV_FAST_VINTR_GET_COOKIE, %o5 578 mov HV_FAST_VINTR_GET_COOKIE, %o5
665 ta HV_FAST_TRAP 579 ta HV_FAST_TRAP
666 stx %o1, [%g1] 580 stx %o1, [%g1]
667 retl 581 retl
668 nop 582 nop
669 .size sun4v_vintr_get_cookie, .-sun4v_vintr_get_cookie 583ENDPROC(sun4v_vintr_get_cookie)
670 584
671 /* %o0: device handle 585 /* %o0: device handle
672 * %o1: device INO 586 * %o1: device INO
@@ -674,14 +588,12 @@ sun4v_vintr_get_cookie:
674 * 588 *
675 * returns %o0: status 589 * returns %o0: status
676 */ 590 */
677 .globl sun4v_vintr_set_cookie 591ENTRY(sun4v_vintr_set_cookie)
678 .type sun4v_vintr_set_cookie,#function
679sun4v_vintr_set_cookie:
680 mov HV_FAST_VINTR_SET_COOKIE, %o5 592 mov HV_FAST_VINTR_SET_COOKIE, %o5
681 ta HV_FAST_TRAP 593 ta HV_FAST_TRAP
682 retl 594 retl
683 nop 595 nop
684 .size sun4v_vintr_set_cookie, .-sun4v_vintr_set_cookie 596ENDPROC(sun4v_vintr_set_cookie)
685 597
686 /* %o0: device handle 598 /* %o0: device handle
687 * %o1: device INO 599 * %o1: device INO
@@ -689,16 +601,14 @@ sun4v_vintr_set_cookie:
689 * 601 *
690 * returns %o0: status 602 * returns %o0: status
691 */ 603 */
692 .globl sun4v_vintr_get_valid 604ENTRY(sun4v_vintr_get_valid)
693 .type sun4v_vintr_get_valid,#function
694sun4v_vintr_get_valid:
695 mov %o2, %g1 605 mov %o2, %g1
696 mov HV_FAST_VINTR_GET_VALID, %o5 606 mov HV_FAST_VINTR_GET_VALID, %o5
697 ta HV_FAST_TRAP 607 ta HV_FAST_TRAP
698 stx %o1, [%g1] 608 stx %o1, [%g1]
699 retl 609 retl
700 nop 610 nop
701 .size sun4v_vintr_get_valid, .-sun4v_vintr_get_valid 611ENDPROC(sun4v_vintr_get_valid)
702 612
703 /* %o0: device handle 613 /* %o0: device handle
704 * %o1: device INO 614 * %o1: device INO
@@ -706,14 +616,12 @@ sun4v_vintr_get_valid:
706 * 616 *
707 * returns %o0: status 617 * returns %o0: status
708 */ 618 */
709 .globl sun4v_vintr_set_valid 619ENTRY(sun4v_vintr_set_valid)
710 .type sun4v_vintr_set_valid,#function
711sun4v_vintr_set_valid:
712 mov HV_FAST_VINTR_SET_VALID, %o5 620 mov HV_FAST_VINTR_SET_VALID, %o5
713 ta HV_FAST_TRAP 621 ta HV_FAST_TRAP
714 retl 622 retl
715 nop 623 nop
716 .size sun4v_vintr_set_valid, .-sun4v_vintr_set_valid 624ENDPROC(sun4v_vintr_set_valid)
717 625
718 /* %o0: device handle 626 /* %o0: device handle
719 * %o1: device INO 627 * %o1: device INO
@@ -721,16 +629,14 @@ sun4v_vintr_set_valid:
721 * 629 *
722 * returns %o0: status 630 * returns %o0: status
723 */ 631 */
724 .globl sun4v_vintr_get_state 632ENTRY(sun4v_vintr_get_state)
725 .type sun4v_vintr_get_state,#function
726sun4v_vintr_get_state:
727 mov %o2, %g1 633 mov %o2, %g1
728 mov HV_FAST_VINTR_GET_STATE, %o5 634 mov HV_FAST_VINTR_GET_STATE, %o5
729 ta HV_FAST_TRAP 635 ta HV_FAST_TRAP
730 stx %o1, [%g1] 636 stx %o1, [%g1]
731 retl 637 retl
732 nop 638 nop
733 .size sun4v_vintr_get_state, .-sun4v_vintr_get_state 639ENDPROC(sun4v_vintr_get_state)
734 640
735 /* %o0: device handle 641 /* %o0: device handle
736 * %o1: device INO 642 * %o1: device INO
@@ -738,14 +644,12 @@ sun4v_vintr_get_state:
738 * 644 *
739 * returns %o0: status 645 * returns %o0: status
740 */ 646 */
741 .globl sun4v_vintr_set_state 647ENTRY(sun4v_vintr_set_state)
742 .type sun4v_vintr_set_state,#function
743sun4v_vintr_set_state:
744 mov HV_FAST_VINTR_SET_STATE, %o5 648 mov HV_FAST_VINTR_SET_STATE, %o5
745 ta HV_FAST_TRAP 649 ta HV_FAST_TRAP
746 retl 650 retl
747 nop 651 nop
748 .size sun4v_vintr_set_state, .-sun4v_vintr_set_state 652ENDPROC(sun4v_vintr_set_state)
749 653
750 /* %o0: device handle 654 /* %o0: device handle
751 * %o1: device INO 655 * %o1: device INO
@@ -753,16 +657,14 @@ sun4v_vintr_set_state:
753 * 657 *
754 * returns %o0: status 658 * returns %o0: status
755 */ 659 */
756 .globl sun4v_vintr_get_target 660ENTRY(sun4v_vintr_get_target)
757 .type sun4v_vintr_get_target,#function
758sun4v_vintr_get_target:
759 mov %o2, %g1 661 mov %o2, %g1
760 mov HV_FAST_VINTR_GET_TARGET, %o5 662 mov HV_FAST_VINTR_GET_TARGET, %o5
761 ta HV_FAST_TRAP 663 ta HV_FAST_TRAP
762 stx %o1, [%g1] 664 stx %o1, [%g1]
763 retl 665 retl
764 nop 666 nop
765 .size sun4v_vintr_get_target, .-sun4v_vintr_get_target 667ENDPROC(sun4v_vintr_get_target)
766 668
767 /* %o0: device handle 669 /* %o0: device handle
768 * %o1: device INO 670 * %o1: device INO
@@ -770,14 +672,12 @@ sun4v_vintr_get_target:
770 * 672 *
771 * returns %o0: status 673 * returns %o0: status
772 */ 674 */
773 .globl sun4v_vintr_set_target 675ENTRY(sun4v_vintr_set_target)
774 .type sun4v_vintr_set_target,#function
775sun4v_vintr_set_target:
776 mov HV_FAST_VINTR_SET_TARGET, %o5 676 mov HV_FAST_VINTR_SET_TARGET, %o5
777 ta HV_FAST_TRAP 677 ta HV_FAST_TRAP
778 retl 678 retl
779 nop 679 nop
780 .size sun4v_vintr_set_target, .-sun4v_vintr_set_target 680ENDPROC(sun4v_vintr_set_target)
781 681
782 /* %o0: NCS sub-function 682 /* %o0: NCS sub-function
783 * %o1: sub-function arg real-address 683 * %o1: sub-function arg real-address
@@ -785,18 +685,14 @@ sun4v_vintr_set_target:
785 * 685 *
786 * returns %o0: status 686 * returns %o0: status
787 */ 687 */
788 .globl sun4v_ncs_request 688ENTRY(sun4v_ncs_request)
789 .type sun4v_ncs_request,#function
790sun4v_ncs_request:
791 mov HV_FAST_NCS_REQUEST, %o5 689 mov HV_FAST_NCS_REQUEST, %o5
792 ta HV_FAST_TRAP 690 ta HV_FAST_TRAP
793 retl 691 retl
794 nop 692 nop
795 .size sun4v_ncs_request, .-sun4v_ncs_request 693ENDPROC(sun4v_ncs_request)
796 694
797 .globl sun4v_svc_send 695ENTRY(sun4v_svc_send)
798 .type sun4v_svc_send,#function
799sun4v_svc_send:
800 save %sp, -192, %sp 696 save %sp, -192, %sp
801 mov %i0, %o0 697 mov %i0, %o0
802 mov %i1, %o1 698 mov %i1, %o1
@@ -806,11 +702,9 @@ sun4v_svc_send:
806 stx %o1, [%i3] 702 stx %o1, [%i3]
807 ret 703 ret
808 restore 704 restore
809 .size sun4v_svc_send, .-sun4v_svc_send 705ENDPROC(sun4v_svc_send)
810 706
811 .globl sun4v_svc_recv 707ENTRY(sun4v_svc_recv)
812 .type sun4v_svc_recv,#function
813sun4v_svc_recv:
814 save %sp, -192, %sp 708 save %sp, -192, %sp
815 mov %i0, %o0 709 mov %i0, %o0
816 mov %i1, %o1 710 mov %i1, %o1
@@ -820,62 +714,50 @@ sun4v_svc_recv:
820 stx %o1, [%i3] 714 stx %o1, [%i3]
821 ret 715 ret
822 restore 716 restore
823 .size sun4v_svc_recv, .-sun4v_svc_recv 717ENDPROC(sun4v_svc_recv)
824 718
825 .globl sun4v_svc_getstatus 719ENTRY(sun4v_svc_getstatus)
826 .type sun4v_svc_getstatus,#function
827sun4v_svc_getstatus:
828 mov HV_FAST_SVC_GETSTATUS, %o5 720 mov HV_FAST_SVC_GETSTATUS, %o5
829 mov %o1, %o4 721 mov %o1, %o4
830 ta HV_FAST_TRAP 722 ta HV_FAST_TRAP
831 stx %o1, [%o4] 723 stx %o1, [%o4]
832 retl 724 retl
833 nop 725 nop
834 .size sun4v_svc_getstatus, .-sun4v_svc_getstatus 726ENDPROC(sun4v_svc_getstatus)
835 727
836 .globl sun4v_svc_setstatus 728ENTRY(sun4v_svc_setstatus)
837 .type sun4v_svc_setstatus,#function
838sun4v_svc_setstatus:
839 mov HV_FAST_SVC_SETSTATUS, %o5 729 mov HV_FAST_SVC_SETSTATUS, %o5
840 ta HV_FAST_TRAP 730 ta HV_FAST_TRAP
841 retl 731 retl
842 nop 732 nop
843 .size sun4v_svc_setstatus, .-sun4v_svc_setstatus 733ENDPROC(sun4v_svc_setstatus)
844 734
845 .globl sun4v_svc_clrstatus 735ENTRY(sun4v_svc_clrstatus)
846 .type sun4v_svc_clrstatus,#function
847sun4v_svc_clrstatus:
848 mov HV_FAST_SVC_CLRSTATUS, %o5 736 mov HV_FAST_SVC_CLRSTATUS, %o5
849 ta HV_FAST_TRAP 737 ta HV_FAST_TRAP
850 retl 738 retl
851 nop 739 nop
852 .size sun4v_svc_clrstatus, .-sun4v_svc_clrstatus 740ENDPROC(sun4v_svc_clrstatus)
853 741
854 .globl sun4v_mmustat_conf 742ENTRY(sun4v_mmustat_conf)
855 .type sun4v_mmustat_conf,#function
856sun4v_mmustat_conf:
857 mov %o1, %o4 743 mov %o1, %o4
858 mov HV_FAST_MMUSTAT_CONF, %o5 744 mov HV_FAST_MMUSTAT_CONF, %o5
859 ta HV_FAST_TRAP 745 ta HV_FAST_TRAP
860 stx %o1, [%o4] 746 stx %o1, [%o4]
861 retl 747 retl
862 nop 748 nop
863 .size sun4v_mmustat_conf, .-sun4v_mmustat_conf 749ENDPROC(sun4v_mmustat_conf)
864 750
865 .globl sun4v_mmustat_info 751ENTRY(sun4v_mmustat_info)
866 .type sun4v_mmustat_info,#function
867sun4v_mmustat_info:
868 mov %o0, %o4 752 mov %o0, %o4
869 mov HV_FAST_MMUSTAT_INFO, %o5 753 mov HV_FAST_MMUSTAT_INFO, %o5
870 ta HV_FAST_TRAP 754 ta HV_FAST_TRAP
871 stx %o1, [%o4] 755 stx %o1, [%o4]
872 retl 756 retl
873 nop 757 nop
874 .size sun4v_mmustat_info, .-sun4v_mmustat_info 758ENDPROC(sun4v_mmustat_info)
875 759
876 .globl sun4v_mmu_demap_all 760ENTRY(sun4v_mmu_demap_all)
877 .type sun4v_mmu_demap_all,#function
878sun4v_mmu_demap_all:
879 clr %o0 761 clr %o0
880 clr %o1 762 clr %o1
881 mov HV_MMU_ALL, %o2 763 mov HV_MMU_ALL, %o2
@@ -883,4 +765,4 @@ sun4v_mmu_demap_all:
883 ta HV_FAST_TRAP 765 ta HV_FAST_TRAP
884 retl 766 retl
885 nop 767 nop
886 .size sun4v_mmu_demap_all, .-sun4v_mmu_demap_all 768ENDPROC(sun4v_mmu_demap_all)
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index 7495bc77468..52fc836f464 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -29,7 +29,6 @@
29#include <asm/system.h> 29#include <asm/system.h>
30#include <asm/irq.h> 30#include <asm/irq.h>
31#include <asm/io.h> 31#include <asm/io.h>
32#include <asm/sbus.h>
33#include <asm/iommu.h> 32#include <asm/iommu.h>
34#include <asm/upa.h> 33#include <asm/upa.h>
35#include <asm/oplib.h> 34#include <asm/oplib.h>
diff --git a/arch/sparc64/kernel/of_device.c b/arch/sparc64/kernel/of_device.c
index 100ebd52749..0f616ae3246 100644
--- a/arch/sparc64/kernel/of_device.c
+++ b/arch/sparc64/kernel/of_device.c
@@ -55,15 +55,38 @@ struct of_device *of_find_device_by_node(struct device_node *dp)
55} 55}
56EXPORT_SYMBOL(of_find_device_by_node); 56EXPORT_SYMBOL(of_find_device_by_node);
57 57
58#ifdef CONFIG_PCI 58unsigned int irq_of_parse_and_map(struct device_node *node, int index)
59struct bus_type ebus_bus_type; 59{
60EXPORT_SYMBOL(ebus_bus_type); 60 struct of_device *op = of_find_device_by_node(node);
61#endif 61
62 if (!op || index >= op->num_irqs)
63 return 0;
64
65 return op->irqs[index];
66}
67EXPORT_SYMBOL(irq_of_parse_and_map);
68
69/* Take the archdata values for IOMMU, STC, and HOSTDATA found in
70 * BUS and propagate to all child of_device objects.
71 */
72void of_propagate_archdata(struct of_device *bus)
73{
74 struct dev_archdata *bus_sd = &bus->dev.archdata;
75 struct device_node *bus_dp = bus->node;
76 struct device_node *dp;
62 77
63#ifdef CONFIG_SBUS 78 for (dp = bus_dp->child; dp; dp = dp->sibling) {
64struct bus_type sbus_bus_type; 79 struct of_device *op = of_find_device_by_node(dp);
65EXPORT_SYMBOL(sbus_bus_type); 80
66#endif 81 op->dev.archdata.iommu = bus_sd->iommu;
82 op->dev.archdata.stc = bus_sd->stc;
83 op->dev.archdata.host_controller = bus_sd->host_controller;
84 op->dev.archdata.numa_node = bus_sd->numa_node;
85
86 if (dp->child)
87 of_propagate_archdata(op);
88 }
89}
67 90
68struct bus_type of_platform_bus_type; 91struct bus_type of_platform_bus_type;
69EXPORT_SYMBOL(of_platform_bus_type); 92EXPORT_SYMBOL(of_platform_bus_type);
@@ -378,8 +401,7 @@ static int __init build_one_resource(struct device_node *parent,
378 int na, int ns, int pna) 401 int na, int ns, int pna)
379{ 402{
380 const u32 *ranges; 403 const u32 *ranges;
381 unsigned int rlen; 404 int rone, rlen;
382 int rone;
383 405
384 ranges = of_get_property(parent, "ranges", &rlen); 406 ranges = of_get_property(parent, "ranges", &rlen);
385 if (ranges == NULL || rlen == 0) { 407 if (ranges == NULL || rlen == 0) {
@@ -421,8 +443,17 @@ static int __init use_1to1_mapping(struct device_node *pp)
421 443
422 /* If the parent is the dma node of an ISA bus, pass 444 /* If the parent is the dma node of an ISA bus, pass
423 * the translation up to the root. 445 * the translation up to the root.
446 *
447 * Some SBUS devices use intermediate nodes to express
448 * hierarchy within the device itself. These aren't
449 * real bus nodes, and don't have a 'ranges' property.
450 * But, we should still pass the translation work up
451 * to the SBUS itself.
424 */ 452 */
425 if (!strcmp(pp->name, "dma")) 453 if (!strcmp(pp->name, "dma") ||
454 !strcmp(pp->name, "espdma") ||
455 !strcmp(pp->name, "ledma") ||
456 !strcmp(pp->name, "lebuffer"))
426 return 0; 457 return 0;
427 458
428 /* Similarly for all PCI bridges, if we get this far 459 /* Similarly for all PCI bridges, if we get this far
@@ -844,15 +875,6 @@ static int __init of_bus_driver_init(void)
844 int err; 875 int err;
845 876
846 err = of_bus_type_init(&of_platform_bus_type, "of"); 877 err = of_bus_type_init(&of_platform_bus_type, "of");
847#ifdef CONFIG_PCI
848 if (!err)
849 err = of_bus_type_init(&ebus_bus_type, "ebus");
850#endif
851#ifdef CONFIG_SBUS
852 if (!err)
853 err = of_bus_type_init(&sbus_bus_type, "sbus");
854#endif
855
856 if (!err) 878 if (!err)
857 scan_of_devices(); 879 scan_of_devices();
858 880
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index 80dad76f8b8..242ac1ccae7 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -18,32 +18,17 @@
18#include <linux/msi.h> 18#include <linux/msi.h>
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
21 23
22#include <asm/uaccess.h> 24#include <asm/uaccess.h>
23#include <asm/pgtable.h> 25#include <asm/pgtable.h>
24#include <asm/irq.h> 26#include <asm/irq.h>
25#include <asm/ebus.h>
26#include <asm/prom.h> 27#include <asm/prom.h>
27#include <asm/apb.h> 28#include <asm/apb.h>
28 29
29#include "pci_impl.h" 30#include "pci_impl.h"
30 31
31#ifndef CONFIG_PCI
32/* A "nop" PCI implementation. */
33asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
34 unsigned long off, unsigned long len,
35 unsigned char *buf)
36{
37 return 0;
38}
39asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
40 unsigned long off, unsigned long len,
41 unsigned char *buf)
42{
43 return 0;
44}
45#else
46
47/* List of all PCI controllers found in the system. */ 32/* List of all PCI controllers found in the system. */
48struct pci_pbm_info *pci_pbm_root = NULL; 33struct pci_pbm_info *pci_pbm_root = NULL;
49 34
@@ -179,97 +164,6 @@ void pci_config_write32(u32 *addr, u32 val)
179 spin_unlock_irqrestore(&pci_poke_lock, flags); 164 spin_unlock_irqrestore(&pci_poke_lock, flags);
180} 165}
181 166
182/* Probe for all PCI controllers in the system. */
183extern void sabre_init(struct device_node *, const char *);
184extern void psycho_init(struct device_node *, const char *);
185extern void schizo_init(struct device_node *, const char *);
186extern void schizo_plus_init(struct device_node *, const char *);
187extern void tomatillo_init(struct device_node *, const char *);
188extern void sun4v_pci_init(struct device_node *, const char *);
189extern void fire_pci_init(struct device_node *, const char *);
190
191static struct {
192 char *model_name;
193 void (*init)(struct device_node *, const char *);
194} pci_controller_table[] __initdata = {
195 { "SUNW,sabre", sabre_init },
196 { "pci108e,a000", sabre_init },
197 { "pci108e,a001", sabre_init },
198 { "SUNW,psycho", psycho_init },
199 { "pci108e,8000", psycho_init },
200 { "SUNW,schizo", schizo_init },
201 { "pci108e,8001", schizo_init },
202 { "SUNW,schizo+", schizo_plus_init },
203 { "pci108e,8002", schizo_plus_init },
204 { "SUNW,tomatillo", tomatillo_init },
205 { "pci108e,a801", tomatillo_init },
206 { "SUNW,sun4v-pci", sun4v_pci_init },
207 { "pciex108e,80f0", fire_pci_init },
208};
209#define PCI_NUM_CONTROLLER_TYPES ARRAY_SIZE(pci_controller_table)
210
211static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
212{
213 int i;
214
215 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
216 if (!strncmp(model_name,
217 pci_controller_table[i].model_name,
218 namelen)) {
219 pci_controller_table[i].init(dp, model_name);
220 return 1;
221 }
222 }
223
224 return 0;
225}
226
227static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
228{
229 struct device_node *dp;
230 int count = 0;
231
232 for_each_node_by_name(dp, "pci") {
233 struct property *prop;
234 int len;
235
236 prop = of_find_property(dp, "model", &len);
237 if (!prop)
238 prop = of_find_property(dp, "compatible", &len);
239
240 if (prop) {
241 const char *model = prop->value;
242 int item_len = 0;
243
244 /* Our value may be a multi-valued string in the
245 * case of some compatible properties. For sanity,
246 * only try the first one.
247 */
248 while (model[item_len] && len) {
249 len--;
250 item_len++;
251 }
252
253 if (handler(model, item_len, dp))
254 count++;
255 }
256 }
257
258 return count;
259}
260
261/* Find each controller in the system, attach and initialize
262 * software state structure for each and link into the
263 * pci_pbm_root. Setup the controller enough such
264 * that bus scanning can be done.
265 */
266static void __init pci_controller_probe(void)
267{
268 printk("PCI: Probing for controllers.\n");
269
270 pci_controller_scan(pci_controller_init);
271}
272
273static int ofpci_verbose; 167static int ofpci_verbose;
274 168
275static int __init ofpci_debug(char *str) 169static int __init ofpci_debug(char *str)
@@ -348,11 +242,12 @@ static void pci_parse_of_addrs(struct of_device *op,
348 } 242 }
349} 243}
350 244
351struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, 245static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
352 struct device_node *node, 246 struct device_node *node,
353 struct pci_bus *bus, int devfn) 247 struct pci_bus *bus, int devfn)
354{ 248{
355 struct dev_archdata *sd; 249 struct dev_archdata *sd;
250 struct of_device *op;
356 struct pci_dev *dev; 251 struct pci_dev *dev;
357 const char *type; 252 const char *type;
358 u32 class; 253 u32 class;
@@ -366,14 +261,17 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
366 sd->stc = &pbm->stc; 261 sd->stc = &pbm->stc;
367 sd->host_controller = pbm; 262 sd->host_controller = pbm;
368 sd->prom_node = node; 263 sd->prom_node = node;
369 sd->op = of_find_device_by_node(node); 264 sd->op = op = of_find_device_by_node(node);
370 sd->numa_node = pbm->numa_node; 265 sd->numa_node = pbm->numa_node;
371 266
372 sd = &sd->op->dev.archdata; 267 sd = &op->dev.archdata;
373 sd->iommu = pbm->iommu; 268 sd->iommu = pbm->iommu;
374 sd->stc = &pbm->stc; 269 sd->stc = &pbm->stc;
375 sd->numa_node = pbm->numa_node; 270 sd->numa_node = pbm->numa_node;
376 271
272 if (!strcmp(node->name, "ebus"))
273 of_propagate_archdata(op);
274
377 type = of_get_property(node, "device_type", NULL); 275 type = of_get_property(node, "device_type", NULL);
378 if (type == NULL) 276 if (type == NULL)
379 type = ""; 277 type = "";
@@ -775,15 +673,15 @@ static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
775 pci_bus_register_of_sysfs(child_bus); 673 pci_bus_register_of_sysfs(child_bus);
776} 674}
777 675
778struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm) 676struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
677 struct device *parent)
779{ 678{
780 struct device_node *node = pbm->prom_node; 679 struct device_node *node = pbm->op->node;
781 struct pci_bus *bus; 680 struct pci_bus *bus;
782 681
783 printk("PCI: Scanning PBM %s\n", node->full_name); 682 printk("PCI: Scanning PBM %s\n", node->full_name);
784 683
785 /* XXX parent device? XXX */ 684 bus = pci_create_bus(parent, pbm->pci_first_busno, pbm->pci_ops, pbm);
786 bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
787 if (!bus) { 685 if (!bus) {
788 printk(KERN_ERR "Failed to create bus for %s\n", 686 printk(KERN_ERR "Failed to create bus for %s\n",
789 node->full_name); 687 node->full_name);
@@ -802,32 +700,6 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
802 return bus; 700 return bus;
803} 701}
804 702
805static void __init pci_scan_each_controller_bus(void)
806{
807 struct pci_pbm_info *pbm;
808
809 for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
810 pbm->scan_bus(pbm);
811}
812
813extern void power_init(void);
814
815static int __init pcibios_init(void)
816{
817 pci_controller_probe();
818 if (pci_pbm_root == NULL)
819 return 0;
820
821 pci_scan_each_controller_bus();
822
823 ebus_init();
824 power_init();
825
826 return 0;
827}
828
829subsys_initcall(pcibios_init);
830
831void __devinit pcibios_fixup_bus(struct pci_bus *pbus) 703void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
832{ 704{
833 struct pci_pbm_info *pbm = pbus->sysdata; 705 struct pci_pbm_info *pbm = pbus->sysdata;
@@ -1105,14 +977,14 @@ int pcibus_to_node(struct pci_bus *pbus)
1105EXPORT_SYMBOL(pcibus_to_node); 977EXPORT_SYMBOL(pcibus_to_node);
1106#endif 978#endif
1107 979
1108/* Return the domain nuber for this pci bus */ 980/* Return the domain number for this pci bus */
1109 981
1110int pci_domain_nr(struct pci_bus *pbus) 982int pci_domain_nr(struct pci_bus *pbus)
1111{ 983{
1112 struct pci_pbm_info *pbm = pbus->sysdata; 984 struct pci_pbm_info *pbm = pbus->sysdata;
1113 int ret; 985 int ret;
1114 986
1115 if (pbm == NULL || pbm->parent == NULL) { 987 if (!pbm) {
1116 ret = -ENXIO; 988 ret = -ENXIO;
1117 } else { 989 } else {
1118 ret = pbm->index; 990 ret = pbm->index;
@@ -1126,7 +998,7 @@ EXPORT_SYMBOL(pci_domain_nr);
1126int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 998int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1127{ 999{
1128 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 1000 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1129 int virt_irq; 1001 unsigned int virt_irq;
1130 1002
1131 if (!pbm->setup_msi_irq) 1003 if (!pbm->setup_msi_irq)
1132 return -EINVAL; 1004 return -EINVAL;
@@ -1140,10 +1012,8 @@ void arch_teardown_msi_irq(unsigned int virt_irq)
1140 struct pci_dev *pdev = entry->dev; 1012 struct pci_dev *pdev = entry->dev;
1141 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 1013 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1142 1014
1143 if (!pbm->teardown_msi_irq) 1015 if (pbm->teardown_msi_irq)
1144 return; 1016 pbm->teardown_msi_irq(virt_irq, pdev);
1145
1146 return pbm->teardown_msi_irq(virt_irq, pdev);
1147} 1017}
1148#endif /* !(CONFIG_PCI_MSI) */ 1018#endif /* !(CONFIG_PCI_MSI) */
1149 1019
@@ -1215,5 +1085,3 @@ void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1215 *start = rp->start - offset; 1085 *start = rp->start - offset;
1216 *end = rp->end - offset; 1086 *end = rp->end - offset;
1217} 1087}
1218
1219#endif /* !(CONFIG_PCI) */
diff --git a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c
index 09a5ec200c6..23b88082d0b 100644
--- a/arch/sparc64/kernel/pci_common.c
+++ b/arch/sparc64/kernel/pci_common.c
@@ -314,12 +314,12 @@ struct pci_ops sun4v_pci_ops = {
314 314
315void pci_get_pbm_props(struct pci_pbm_info *pbm) 315void pci_get_pbm_props(struct pci_pbm_info *pbm)
316{ 316{
317 const u32 *val = of_get_property(pbm->prom_node, "bus-range", NULL); 317 const u32 *val = of_get_property(pbm->op->node, "bus-range", NULL);
318 318
319 pbm->pci_first_busno = val[0]; 319 pbm->pci_first_busno = val[0];
320 pbm->pci_last_busno = val[1]; 320 pbm->pci_last_busno = val[1];
321 321
322 val = of_get_property(pbm->prom_node, "ino-bitmap", NULL); 322 val = of_get_property(pbm->op->node, "ino-bitmap", NULL);
323 if (val) { 323 if (val) {
324 pbm->ino_bitmap = (((u64)val[1] << 32UL) | 324 pbm->ino_bitmap = (((u64)val[1] << 32UL) |
325 ((u64)val[0] << 0UL)); 325 ((u64)val[0] << 0UL));
@@ -365,7 +365,7 @@ static void pci_register_legacy_regions(struct resource *io_res,
365 365
366static void pci_register_iommu_region(struct pci_pbm_info *pbm) 366static void pci_register_iommu_region(struct pci_pbm_info *pbm)
367{ 367{
368 const u32 *vdma = of_get_property(pbm->prom_node, "virtual-dma", NULL); 368 const u32 *vdma = of_get_property(pbm->op->node, "virtual-dma", NULL);
369 369
370 if (vdma) { 370 if (vdma) {
371 struct resource *rp = kmalloc(sizeof(*rp), GFP_KERNEL); 371 struct resource *rp = kmalloc(sizeof(*rp), GFP_KERNEL);
@@ -389,7 +389,7 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
389 int num_pbm_ranges; 389 int num_pbm_ranges;
390 390
391 saw_mem = saw_io = 0; 391 saw_mem = saw_io = 0;
392 pbm_ranges = of_get_property(pbm->prom_node, "ranges", &i); 392 pbm_ranges = of_get_property(pbm->op->node, "ranges", &i);
393 if (!pbm_ranges) { 393 if (!pbm_ranges) {
394 prom_printf("PCI: Fatal error, missing PBM ranges property " 394 prom_printf("PCI: Fatal error, missing PBM ranges property "
395 " for %s\n", 395 " for %s\n",
diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c
index d23bb6f53cd..9462b68f489 100644
--- a/arch/sparc64/kernel/pci_fire.c
+++ b/arch/sparc64/kernel/pci_fire.c
@@ -8,34 +8,16 @@
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/msi.h> 9#include <linux/msi.h>
10#include <linux/irq.h> 10#include <linux/irq.h>
11#include <linux/of_device.h>
11 12
12#include <asm/oplib.h>
13#include <asm/prom.h> 13#include <asm/prom.h>
14#include <asm/irq.h> 14#include <asm/irq.h>
15#include <asm/upa.h>
15 16
16#include "pci_impl.h" 17#include "pci_impl.h"
17 18
18#define fire_read(__reg) \ 19#define DRIVER_NAME "fire"
19({ u64 __ret; \ 20#define PFX DRIVER_NAME ": "
20 __asm__ __volatile__("ldxa [%1] %2, %0" \
21 : "=r" (__ret) \
22 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
23 : "memory"); \
24 __ret; \
25})
26#define fire_write(__reg, __val) \
27 __asm__ __volatile__("stxa %0, [%1] %2" \
28 : /* no outputs */ \
29 : "r" (__val), "r" (__reg), \
30 "i" (ASI_PHYS_BYPASS_EC_E) \
31 : "memory")
32
33static void __init pci_fire_scan_bus(struct pci_pbm_info *pbm)
34{
35 pbm->pci_bus = pci_scan_one_pbm(pbm);
36
37 /* XXX register error interrupt handlers XXX */
38}
39 21
40#define FIRE_IOMMU_CONTROL 0x40000UL 22#define FIRE_IOMMU_CONTROL 0x40000UL
41#define FIRE_IOMMU_TSBBASE 0x40008UL 23#define FIRE_IOMMU_TSBBASE 0x40008UL
@@ -69,21 +51,21 @@ static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
69 /* 51 /*
70 * Invalidate TLB Entries. 52 * Invalidate TLB Entries.
71 */ 53 */
72 fire_write(iommu->iommu_flushinv, ~(u64)0); 54 upa_writeq(~(u64)0, iommu->iommu_flushinv);
73 55
74 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, 56 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
75 pbm->numa_node); 57 pbm->numa_node);
76 if (err) 58 if (err)
77 return err; 59 return err;
78 60
79 fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL); 61 upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);
80 62
81 control = fire_read(iommu->iommu_control); 63 control = upa_readq(iommu->iommu_control);
82 control |= (0x00000400 /* TSB cache snoop enable */ | 64 control |= (0x00000400 /* TSB cache snoop enable */ |
83 0x00000300 /* Cache mode */ | 65 0x00000300 /* Cache mode */ |
84 0x00000002 /* Bypass enable */ | 66 0x00000002 /* Bypass enable */ |
85 0x00000001 /* Translation enable */); 67 0x00000001 /* Translation enable */);
86 fire_write(iommu->iommu_control, control); 68 upa_writeq(control, iommu->iommu_control);
87 69
88 return 0; 70 return 0;
89} 71}
@@ -165,7 +147,7 @@ struct pci_msiq_entry {
165static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid, 147static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
166 unsigned long *head) 148 unsigned long *head)
167{ 149{
168 *head = fire_read(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid)); 150 *head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
169 return 0; 151 return 0;
170} 152}
171 153
@@ -191,8 +173,7 @@ static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
191 *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >> 173 *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
192 MSIQ_WORD0_DATA0_SHIFT); 174 MSIQ_WORD0_DATA0_SHIFT);
193 175
194 fire_write(pbm->pbm_regs + MSI_CLEAR(msi_num), 176 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));
195 MSI_CLEAR_EQWR_N);
196 177
197 /* Clear the entry. */ 178 /* Clear the entry. */
198 ep->word0 &= ~MSIQ_WORD0_FMT_TYPE; 179 ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
@@ -208,7 +189,7 @@ static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
208static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid, 189static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
209 unsigned long head) 190 unsigned long head)
210{ 191{
211 fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid), head); 192 upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
212 return 0; 193 return 0;
213} 194}
214 195
@@ -217,17 +198,16 @@ static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
217{ 198{
218 u64 val; 199 u64 val;
219 200
220 val = fire_read(pbm->pbm_regs + MSI_MAP(msi)); 201 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
221 val &= ~(MSI_MAP_EQNUM); 202 val &= ~(MSI_MAP_EQNUM);
222 val |= msiqid; 203 val |= msiqid;
223 fire_write(pbm->pbm_regs + MSI_MAP(msi), val); 204 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
224 205
225 fire_write(pbm->pbm_regs + MSI_CLEAR(msi), 206 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));
226 MSI_CLEAR_EQWR_N);
227 207
228 val = fire_read(pbm->pbm_regs + MSI_MAP(msi)); 208 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
229 val |= MSI_MAP_VALID; 209 val |= MSI_MAP_VALID;
230 fire_write(pbm->pbm_regs + MSI_MAP(msi), val); 210 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
231 211
232 return 0; 212 return 0;
233} 213}
@@ -237,12 +217,12 @@ static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
237 unsigned long msiqid; 217 unsigned long msiqid;
238 u64 val; 218 u64 val;
239 219
240 val = fire_read(pbm->pbm_regs + MSI_MAP(msi)); 220 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
241 msiqid = (val & MSI_MAP_EQNUM); 221 msiqid = (val & MSI_MAP_EQNUM);
242 222
243 val &= ~MSI_MAP_VALID; 223 val &= ~MSI_MAP_VALID;
244 224
245 fire_write(pbm->pbm_regs + MSI_MAP(msi), val); 225 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
246 226
247 return 0; 227 return 0;
248} 228}
@@ -261,22 +241,19 @@ static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
261 memset((char *)pages, 0, PAGE_SIZE << order); 241 memset((char *)pages, 0, PAGE_SIZE << order);
262 pbm->msi_queues = (void *) pages; 242 pbm->msi_queues = (void *) pages;
263 243
264 fire_write(pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG, 244 upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES |
265 (EVENT_QUEUE_BASE_ADDR_ALL_ONES | 245 __pa(pbm->msi_queues)),
266 __pa(pbm->msi_queues))); 246 pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);
267 247
268 fire_write(pbm->pbm_regs + IMONDO_DATA0, 248 upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);
269 pbm->portid << 6); 249 upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);
270 fire_write(pbm->pbm_regs + IMONDO_DATA1, 0);
271 250
272 fire_write(pbm->pbm_regs + MSI_32BIT_ADDR, 251 upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);
273 pbm->msi32_start); 252 upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);
274 fire_write(pbm->pbm_regs + MSI_64BIT_ADDR,
275 pbm->msi64_start);
276 253
277 for (i = 0; i < pbm->msiq_num; i++) { 254 for (i = 0; i < pbm->msiq_num; i++) {
278 fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(i), 0); 255 upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));
279 fire_write(pbm->pbm_regs + EVENT_QUEUE_TAIL(i), 0); 256 upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));
280 } 257 }
281 258
282 return 0; 259 return 0;
@@ -310,9 +287,9 @@ static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
310 /* XXX iterate amongst the 4 IRQ controllers XXX */ 287 /* XXX iterate amongst the 4 IRQ controllers XXX */
311 int_ctrlr = (1UL << 6); 288 int_ctrlr = (1UL << 6);
312 289
313 val = fire_read(imap_reg); 290 val = upa_readq(imap_reg);
314 val |= (1UL << 63) | int_ctrlr; 291 val |= (1UL << 63) | int_ctrlr;
315 fire_write(imap_reg, val); 292 upa_writeq(val, imap_reg);
316 293
317 fixup = ((pbm->portid << 6) | devino) - int_ctrlr; 294 fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
318 295
@@ -320,9 +297,8 @@ static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
320 if (!virt_irq) 297 if (!virt_irq)
321 return -ENOMEM; 298 return -ENOMEM;
322 299
323 fire_write(pbm->pbm_regs + 300 upa_writeq(EVENT_QUEUE_CONTROL_SET_EN,
324 EVENT_QUEUE_CONTROL_SET(msiqid), 301 pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));
325 EVENT_QUEUE_CONTROL_SET_EN);
326 302
327 return virt_irq; 303 return virt_irq;
328} 304}
@@ -390,77 +366,65 @@ static void pci_fire_hw_init(struct pci_pbm_info *pbm)
390{ 366{
391 u64 val; 367 u64 val;
392 368
393 fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL, 369 upa_writeq(FIRE_PARITY_ENAB,
394 FIRE_PARITY_ENAB); 370 pbm->controller_regs + FIRE_PARITY_CONTROL);
395 371
396 fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL, 372 upa_writeq((FIRE_FATAL_RESET_SPARE |
397 (FIRE_FATAL_RESET_SPARE |
398 FIRE_FATAL_RESET_MB | 373 FIRE_FATAL_RESET_MB |
399 FIRE_FATAL_RESET_CPE | 374 FIRE_FATAL_RESET_CPE |
400 FIRE_FATAL_RESET_APE | 375 FIRE_FATAL_RESET_APE |
401 FIRE_FATAL_RESET_PIO | 376 FIRE_FATAL_RESET_PIO |
402 FIRE_FATAL_RESET_JW | 377 FIRE_FATAL_RESET_JW |
403 FIRE_FATAL_RESET_JI | 378 FIRE_FATAL_RESET_JI |
404 FIRE_FATAL_RESET_JR)); 379 FIRE_FATAL_RESET_JR),
380 pbm->controller_regs + FIRE_FATAL_RESET_CTL);
405 381
406 fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0); 382 upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);
407 383
408 val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL); 384 val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);
409 val |= (FIRE_TLU_CTRL_TIM | 385 val |= (FIRE_TLU_CTRL_TIM |
410 FIRE_TLU_CTRL_QDET | 386 FIRE_TLU_CTRL_QDET |
411 FIRE_TLU_CTRL_CFG); 387 FIRE_TLU_CTRL_CFG);
412 fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val); 388 upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);
413 fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0); 389 upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);
414 fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL, 390 upa_writeq(FIRE_TLU_LINK_CTRL_CLK,
415 FIRE_TLU_LINK_CTRL_CLK); 391 pbm->pbm_regs + FIRE_TLU_LINK_CTRL);
416 392
417 fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0); 393 upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);
418 fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG, 394 upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);
419 FIRE_LPU_LLCFG_VC0); 395 upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P),
420 fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL, 396 pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);
421 (FIRE_LPU_FCTRL_UCTRL_N | 397 upa_writeq(((0xffff << 16) | (0x0000 << 0)),
422 FIRE_LPU_FCTRL_UCTRL_P)); 398 pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);
423 fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP, 399 upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);
424 ((0xffff << 16) | (0x0000 << 0))); 400 upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);
425 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000); 401 upa_writeq((2 << 16) | (140 << 8),
426 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000); 402 pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);
427 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4, 403 upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);
428 (2 << 16) | (140 << 8)); 404
429 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0); 405 upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);
430 406 upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);
431 fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0); 407 upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);
432 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0); 408
433 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0); 409 upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);
434
435 fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
436} 410}
437 411
438static int __init pci_fire_pbm_init(struct pci_controller_info *p, 412static int __init pci_fire_pbm_init(struct pci_pbm_info *pbm,
439 struct device_node *dp, u32 portid) 413 struct of_device *op, u32 portid)
440{ 414{
441 const struct linux_prom64_registers *regs; 415 const struct linux_prom64_registers *regs;
442 struct pci_pbm_info *pbm; 416 struct device_node *dp = op->node;
443 int err; 417 int err;
444 418
445 if ((portid & 1) == 0)
446 pbm = &p->pbm_A;
447 else
448 pbm = &p->pbm_B;
449
450 pbm->next = pci_pbm_root;
451 pci_pbm_root = pbm;
452
453 pbm->numa_node = -1; 419 pbm->numa_node = -1;
454 420
455 pbm->scan_bus = pci_fire_scan_bus;
456 pbm->pci_ops = &sun4u_pci_ops; 421 pbm->pci_ops = &sun4u_pci_ops;
457 pbm->config_space_reg_bits = 12; 422 pbm->config_space_reg_bits = 12;
458 423
459 pbm->index = pci_num_pbms++; 424 pbm->index = pci_num_pbms++;
460 425
461 pbm->portid = portid; 426 pbm->portid = portid;
462 pbm->parent = p; 427 pbm->op = op;
463 pbm->prom_node = dp;
464 pbm->name = dp->full_name; 428 pbm->name = dp->full_name;
465 429
466 regs = of_get_property(dp, "reg", NULL); 430 regs = of_get_property(dp, "reg", NULL);
@@ -481,53 +445,77 @@ static int __init pci_fire_pbm_init(struct pci_controller_info *p,
481 445
482 pci_fire_msi_init(pbm); 446 pci_fire_msi_init(pbm);
483 447
484 return 0; 448 pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);
485} 449
450 /* XXX register error interrupt handlers XXX */
451
452 pbm->next = pci_pbm_root;
453 pci_pbm_root = pbm;
486 454
487static inline int portid_compare(u32 x, u32 y)
488{
489 if (x == (y ^ 1))
490 return 1;
491 return 0; 455 return 0;
492} 456}
493 457
494void __init fire_pci_init(struct device_node *dp, const char *model_name) 458static int __devinit fire_probe(struct of_device *op,
459 const struct of_device_id *match)
495{ 460{
496 struct pci_controller_info *p; 461 struct device_node *dp = op->node;
497 u32 portid = of_getintprop_default(dp, "portid", 0xff);
498 struct iommu *iommu;
499 struct pci_pbm_info *pbm; 462 struct pci_pbm_info *pbm;
463 struct iommu *iommu;
464 u32 portid;
465 int err;
500 466
501 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 467 portid = of_getintprop_default(dp, "portid", 0xff);
502 if (portid_compare(pbm->portid, portid)) { 468
503 if (pci_fire_pbm_init(pbm->parent, dp, portid)) 469 err = -ENOMEM;
504 goto fatal_memory_error; 470 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
505 return; 471 if (!pbm) {
506 } 472 printk(KERN_ERR PFX "Cannot allocate pci_pbminfo.\n");
473 goto out_err;
507 } 474 }
508 475
509 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); 476 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
510 if (!p) 477 if (!iommu) {
511 goto fatal_memory_error; 478 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
479 goto out_free_controller;
480 }
512 481
513 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); 482 pbm->iommu = iommu;
514 if (!iommu)
515 goto fatal_memory_error;
516 483
517 p->pbm_A.iommu = iommu; 484 err = pci_fire_pbm_init(pbm, op, portid);
485 if (err)
486 goto out_free_iommu;
518 487
519 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); 488 dev_set_drvdata(&op->dev, pbm);
520 if (!iommu)
521 goto fatal_memory_error;
522 489
523 p->pbm_B.iommu = iommu; 490 return 0;
524 491
525 if (pci_fire_pbm_init(p, dp, portid)) 492out_free_iommu:
526 goto fatal_memory_error; 493 kfree(pbm->iommu);
494
495out_free_controller:
496 kfree(pbm);
527 497
528 return; 498out_err:
499 return err;
500}
501
502static struct of_device_id __initdata fire_match[] = {
503 {
504 .name = "pci",
505 .compatible = "pciex108e,80f0",
506 },
507 {},
508};
529 509
530fatal_memory_error: 510static struct of_platform_driver fire_driver = {
531 prom_printf("PCI_FIRE: Fatal memory allocation error.\n"); 511 .name = DRIVER_NAME,
532 prom_halt(); 512 .match_table = fire_match,
513 .probe = fire_probe,
514};
515
516static int __init fire_init(void)
517{
518 return of_register_driver(&fire_driver, &of_bus_type);
533} 519}
520
521subsys_initcall(fire_init);
diff --git a/arch/sparc64/kernel/pci_impl.h b/arch/sparc64/kernel/pci_impl.h
index c385d126be1..03186824327 100644
--- a/arch/sparc64/kernel/pci_impl.h
+++ b/arch/sparc64/kernel/pci_impl.h
@@ -10,6 +10,7 @@
10#include <linux/spinlock.h> 10#include <linux/spinlock.h>
11#include <linux/pci.h> 11#include <linux/pci.h>
12#include <linux/msi.h> 12#include <linux/msi.h>
13#include <linux/of_device.h>
13#include <asm/io.h> 14#include <asm/io.h>
14#include <asm/prom.h> 15#include <asm/prom.h>
15#include <asm/iommu.h> 16#include <asm/iommu.h>
@@ -56,15 +57,11 @@ struct sparc64_msiq_cookie {
56}; 57};
57#endif 58#endif
58 59
59struct pci_controller_info;
60
61struct pci_pbm_info { 60struct pci_pbm_info {
62 struct pci_pbm_info *next; 61 struct pci_pbm_info *next;
62 struct pci_pbm_info *sibling;
63 int index; 63 int index;
64 64
65 /* PCI controller we sit under. */
66 struct pci_controller_info *parent;
67
68 /* Physical address base of controller registers. */ 65 /* Physical address base of controller registers. */
69 unsigned long controller_regs; 66 unsigned long controller_regs;
70 67
@@ -94,7 +91,7 @@ struct pci_pbm_info {
94 char *name; 91 char *name;
95 92
96 /* OBP specific information. */ 93 /* OBP specific information. */
97 struct device_node *prom_node; 94 struct of_device *op;
98 u64 ino_bitmap; 95 u64 ino_bitmap;
99 96
100 /* PBM I/O and Memory space resources. */ 97 /* PBM I/O and Memory space resources. */
@@ -107,6 +104,10 @@ struct pci_pbm_info {
107 /* This will be 12 on PCI-E controllers, 8 elsewhere. */ 104 /* This will be 12 on PCI-E controllers, 8 elsewhere. */
108 unsigned long config_space_reg_bits; 105 unsigned long config_space_reg_bits;
109 106
107 unsigned long pci_afsr;
108 unsigned long pci_afar;
109 unsigned long pci_csr;
110
110 /* State of 66MHz capabilities on this PBM. */ 111 /* State of 66MHz capabilities on this PBM. */
111 int is_66mhz_capable; 112 int is_66mhz_capable;
112 int all_devs_66mhz; 113 int all_devs_66mhz;
@@ -146,25 +147,19 @@ struct pci_pbm_info {
146 unsigned int pci_first_busno; 147 unsigned int pci_first_busno;
147 unsigned int pci_last_busno; 148 unsigned int pci_last_busno;
148 struct pci_bus *pci_bus; 149 struct pci_bus *pci_bus;
149 void (*scan_bus)(struct pci_pbm_info *);
150 struct pci_ops *pci_ops; 150 struct pci_ops *pci_ops;
151 151
152 int numa_node; 152 int numa_node;
153}; 153};
154 154
155struct pci_controller_info {
156 /* The PCI bus modules controlled by us. */
157 struct pci_pbm_info pbm_A;
158 struct pci_pbm_info pbm_B;
159};
160
161extern struct pci_pbm_info *pci_pbm_root; 155extern struct pci_pbm_info *pci_pbm_root;
162 156
163extern int pci_num_pbms; 157extern int pci_num_pbms;
164 158
165/* PCI bus scanning and fixup support. */ 159/* PCI bus scanning and fixup support. */
166extern void pci_get_pbm_props(struct pci_pbm_info *pbm); 160extern void pci_get_pbm_props(struct pci_pbm_info *pbm);
167extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm); 161extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
162 struct device *parent);
168extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm); 163extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
169 164
170/* Error reporting support. */ 165/* Error reporting support. */
@@ -183,4 +178,8 @@ extern void pci_config_write32(u32 *addr, u32 val);
183extern struct pci_ops sun4u_pci_ops; 178extern struct pci_ops sun4u_pci_ops;
184extern struct pci_ops sun4v_pci_ops; 179extern struct pci_ops sun4v_pci_ops;
185 180
181extern volatile int pci_poke_in_progress;
182extern volatile int pci_poke_cpu;
183extern volatile int pci_poke_faulted;
184
186#endif /* !(PCI_IMPL_H) */ 185#endif /* !(PCI_IMPL_H) */
diff --git a/arch/sparc64/kernel/pci_msi.c b/arch/sparc64/kernel/pci_msi.c
index 60c71e35021..2e680f34f72 100644
--- a/arch/sparc64/kernel/pci_msi.c
+++ b/arch/sparc64/kernel/pci_msi.c
@@ -323,7 +323,7 @@ void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
323 const u32 *val; 323 const u32 *val;
324 int len; 324 int len;
325 325
326 val = of_get_property(pbm->prom_node, "#msi-eqs", &len); 326 val = of_get_property(pbm->op->node, "#msi-eqs", &len);
327 if (!val || len != 4) 327 if (!val || len != 4)
328 goto no_msi; 328 goto no_msi;
329 pbm->msiq_num = *val; 329 pbm->msiq_num = *val;
@@ -346,16 +346,16 @@ void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
346 u32 msi64_len; 346 u32 msi64_len;
347 } *arng; 347 } *arng;
348 348
349 val = of_get_property(pbm->prom_node, "msi-eq-size", &len); 349 val = of_get_property(pbm->op->node, "msi-eq-size", &len);
350 if (!val || len != 4) 350 if (!val || len != 4)
351 goto no_msi; 351 goto no_msi;
352 352
353 pbm->msiq_ent_count = *val; 353 pbm->msiq_ent_count = *val;
354 354
355 mqp = of_get_property(pbm->prom_node, 355 mqp = of_get_property(pbm->op->node,
356 "msi-eq-to-devino", &len); 356 "msi-eq-to-devino", &len);
357 if (!mqp) 357 if (!mqp)
358 mqp = of_get_property(pbm->prom_node, 358 mqp = of_get_property(pbm->op->node,
359 "msi-eq-devino", &len); 359 "msi-eq-devino", &len);
360 if (!mqp || len != sizeof(struct msiq_prop)) 360 if (!mqp || len != sizeof(struct msiq_prop))
361 goto no_msi; 361 goto no_msi;
@@ -363,27 +363,27 @@ void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
363 pbm->msiq_first = mqp->first_msiq; 363 pbm->msiq_first = mqp->first_msiq;
364 pbm->msiq_first_devino = mqp->first_devino; 364 pbm->msiq_first_devino = mqp->first_devino;
365 365
366 val = of_get_property(pbm->prom_node, "#msi", &len); 366 val = of_get_property(pbm->op->node, "#msi", &len);
367 if (!val || len != 4) 367 if (!val || len != 4)
368 goto no_msi; 368 goto no_msi;
369 pbm->msi_num = *val; 369 pbm->msi_num = *val;
370 370
371 mrng = of_get_property(pbm->prom_node, "msi-ranges", &len); 371 mrng = of_get_property(pbm->op->node, "msi-ranges", &len);
372 if (!mrng || len != sizeof(struct msi_range_prop)) 372 if (!mrng || len != sizeof(struct msi_range_prop))
373 goto no_msi; 373 goto no_msi;
374 pbm->msi_first = mrng->first_msi; 374 pbm->msi_first = mrng->first_msi;
375 375
376 val = of_get_property(pbm->prom_node, "msi-data-mask", &len); 376 val = of_get_property(pbm->op->node, "msi-data-mask", &len);
377 if (!val || len != 4) 377 if (!val || len != 4)
378 goto no_msi; 378 goto no_msi;
379 pbm->msi_data_mask = *val; 379 pbm->msi_data_mask = *val;
380 380
381 val = of_get_property(pbm->prom_node, "msix-data-width", &len); 381 val = of_get_property(pbm->op->node, "msix-data-width", &len);
382 if (!val || len != 4) 382 if (!val || len != 4)
383 goto no_msi; 383 goto no_msi;
384 pbm->msix_data_width = *val; 384 pbm->msix_data_width = *val;
385 385
386 arng = of_get_property(pbm->prom_node, "msi-address-ranges", 386 arng = of_get_property(pbm->op->node, "msi-address-ranges",
387 &len); 387 &len);
388 if (!arng || len != sizeof(struct addr_range_prop)) 388 if (!arng || len != sizeof(struct addr_range_prop))
389 goto no_msi; 389 goto no_msi;
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index f85b6bebb0b..dfb3ec89298 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -17,29 +17,14 @@
17#include <asm/irq.h> 17#include <asm/irq.h>
18#include <asm/starfire.h> 18#include <asm/starfire.h>
19#include <asm/prom.h> 19#include <asm/prom.h>
20#include <asm/oplib.h> 20#include <asm/upa.h>
21 21
22#include "pci_impl.h" 22#include "pci_impl.h"
23#include "iommu_common.h" 23#include "iommu_common.h"
24#include "psycho_common.h"
24 25
25/* All PSYCHO registers are 64-bits. The following accessor 26#define DRIVER_NAME "psycho"
26 * routines are how they are accessed. The REG parameter 27#define PFX DRIVER_NAME ": "
27 * is a physical address.
28 */
29#define psycho_read(__reg) \
30({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36})
37#define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43 28
44/* Misc. PSYCHO PCI controller register offsets and definitions. */ 29/* Misc. PSYCHO PCI controller register offsets and definitions. */
45#define PSYCHO_CONTROL 0x0010UL 30#define PSYCHO_CONTROL 0x0010UL
@@ -67,37 +52,7 @@
67#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ 52#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ 53#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
69 54
70/* U2P Programmer's Manual, page 13-55, configuration space
71 * address format:
72 *
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
77 */
78#define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80#define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
84
85static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
86 unsigned char bus,
87 unsigned int devfn,
88 int where)
89{
90 if (!pbm)
91 return NULL;
92 return (void *)
93 (PSYCHO_CONFIG_BASE(pbm) |
94 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
95}
96
97/* PSYCHO error handling support. */ 55/* PSYCHO error handling support. */
98enum psycho_error_type {
99 UE_ERR, CE_ERR, PCI_ERR
100};
101 56
102/* Helper function of IOMMU error checking, which checks out 57/* Helper function of IOMMU error checking, which checks out
103 * the state of the streaming buffers. The IOMMU lock is 58 * the state of the streaming buffers. The IOMMU lock is
@@ -122,129 +77,10 @@ enum psycho_error_type {
122#define PSYCHO_STC_DATA_B 0xc000UL 77#define PSYCHO_STC_DATA_B 0xc000UL
123#define PSYCHO_STC_ERR_A 0xb400UL 78#define PSYCHO_STC_ERR_A 0xb400UL
124#define PSYCHO_STC_ERR_B 0xc400UL 79#define PSYCHO_STC_ERR_B 0xc400UL
125#define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
126#define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
127#define PSYCHO_STC_TAG_A 0xb800UL 80#define PSYCHO_STC_TAG_A 0xb800UL
128#define PSYCHO_STC_TAG_B 0xc800UL 81#define PSYCHO_STC_TAG_B 0xc800UL
129#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
130#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
131#define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
132#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
133#define PSYCHO_STC_LINE_A 0xb900UL 82#define PSYCHO_STC_LINE_A 0xb900UL
134#define PSYCHO_STC_LINE_B 0xc900UL 83#define PSYCHO_STC_LINE_B 0xc900UL
135#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
136#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
137#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
138#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
139#define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
140#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
141
142static DEFINE_SPINLOCK(stc_buf_lock);
143static unsigned long stc_error_buf[128];
144static unsigned long stc_tag_buf[16];
145static unsigned long stc_line_buf[16];
146
147static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
148 int is_pbm_a)
149{
150 struct strbuf *strbuf = &pbm->stc;
151 unsigned long regbase = pbm->controller_regs;
152 unsigned long err_base, tag_base, line_base;
153 u64 control;
154 int i;
155
156 if (is_pbm_a) {
157 err_base = regbase + PSYCHO_STC_ERR_A;
158 tag_base = regbase + PSYCHO_STC_TAG_A;
159 line_base = regbase + PSYCHO_STC_LINE_A;
160 } else {
161 err_base = regbase + PSYCHO_STC_ERR_B;
162 tag_base = regbase + PSYCHO_STC_TAG_B;
163 line_base = regbase + PSYCHO_STC_LINE_B;
164 }
165
166 spin_lock(&stc_buf_lock);
167
168 /* This is __REALLY__ dangerous. When we put the
169 * streaming buffer into diagnostic mode to probe
170 * it's tags and error status, we _must_ clear all
171 * of the line tag valid bits before re-enabling
172 * the streaming buffer. If any dirty data lives
173 * in the STC when we do this, we will end up
174 * invalidating it before it has a chance to reach
175 * main memory.
176 */
177 control = psycho_read(strbuf->strbuf_control);
178 psycho_write(strbuf->strbuf_control,
179 (control | PSYCHO_STRBUF_CTRL_DENAB));
180 for (i = 0; i < 128; i++) {
181 unsigned long val;
182
183 val = psycho_read(err_base + (i * 8UL));
184 psycho_write(err_base + (i * 8UL), 0UL);
185 stc_error_buf[i] = val;
186 }
187 for (i = 0; i < 16; i++) {
188 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
189 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
190 psycho_write(tag_base + (i * 8UL), 0UL);
191 psycho_write(line_base + (i * 8UL), 0UL);
192 }
193
194 /* OK, state is logged, exit diagnostic mode. */
195 psycho_write(strbuf->strbuf_control, control);
196
197 for (i = 0; i < 16; i++) {
198 int j, saw_error, first, last;
199
200 saw_error = 0;
201 first = i * 8;
202 last = first + 8;
203 for (j = first; j < last; j++) {
204 unsigned long errval = stc_error_buf[j];
205 if (errval != 0) {
206 saw_error++;
207 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
208 pbm->name,
209 j,
210 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
211 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
212 }
213 }
214 if (saw_error != 0) {
215 unsigned long tagval = stc_tag_buf[i];
216 unsigned long lineval = stc_line_buf[i];
217 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
218 pbm->name,
219 i,
220 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
221 (tagval & PSYCHO_STCTAG_VPN),
222 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
223 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
224 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
225 "V(%d)FOFN(%d)]\n",
226 pbm->name,
227 i,
228 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
229 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
230 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
231 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
232 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
233 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
234 }
235 }
236
237 spin_unlock(&stc_buf_lock);
238}
239
240static void __psycho_check_stc_error(struct pci_pbm_info *pbm,
241 unsigned long afsr,
242 unsigned long afar,
243 enum psycho_error_type type)
244{
245 __psycho_check_one_stc(pbm,
246 (pbm == &pbm->parent->pbm_A));
247}
248 84
249/* When an Uncorrectable Error or a PCI Error happens, we 85/* When an Uncorrectable Error or a PCI Error happens, we
250 * interrogate the IOMMU state to see if it is the cause. 86 * interrogate the IOMMU state to see if it is the cause.
@@ -271,122 +107,7 @@ static void __psycho_check_stc_error(struct pci_pbm_info *pbm,
271#define PSYCHO_IOMMU_TSBBASE 0x0208UL 107#define PSYCHO_IOMMU_TSBBASE 0x0208UL
272#define PSYCHO_IOMMU_FLUSH 0x0210UL 108#define PSYCHO_IOMMU_FLUSH 0x0210UL
273#define PSYCHO_IOMMU_TAG 0xa580UL 109#define PSYCHO_IOMMU_TAG 0xa580UL
274#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
275#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
276#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
277#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
278#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
279#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
280#define PSYCHO_IOMMU_DATA 0xa600UL 110#define PSYCHO_IOMMU_DATA 0xa600UL
281#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
282#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
283#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
284static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
285 unsigned long afsr,
286 unsigned long afar,
287 enum psycho_error_type type)
288{
289 struct iommu *iommu = pbm->iommu;
290 unsigned long iommu_tag[16];
291 unsigned long iommu_data[16];
292 unsigned long flags;
293 u64 control;
294 int i;
295
296 spin_lock_irqsave(&iommu->lock, flags);
297 control = psycho_read(iommu->iommu_control);
298 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
299 char *type_string;
300
301 /* Clear the error encountered bit. */
302 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
303 psycho_write(iommu->iommu_control, control);
304
305 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
306 case 0:
307 type_string = "Protection Error";
308 break;
309 case 1:
310 type_string = "Invalid Error";
311 break;
312 case 2:
313 type_string = "TimeOut Error";
314 break;
315 case 3:
316 default:
317 type_string = "ECC Error";
318 break;
319 };
320 printk("%s: IOMMU Error, type[%s]\n",
321 pbm->name, type_string);
322
323 /* Put the IOMMU into diagnostic mode and probe
324 * it's TLB for entries with error status.
325 *
326 * It is very possible for another DVMA to occur
327 * while we do this probe, and corrupt the system
328 * further. But we are so screwed at this point
329 * that we are likely to crash hard anyways, so
330 * get as much diagnostic information to the
331 * console as we can.
332 */
333 psycho_write(iommu->iommu_control,
334 control | PSYCHO_IOMMU_CTRL_DENAB);
335 for (i = 0; i < 16; i++) {
336 unsigned long base = pbm->controller_regs;
337
338 iommu_tag[i] =
339 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
340 iommu_data[i] =
341 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
342
343 /* Now clear out the entry. */
344 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
345 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
346 }
347
348 /* Leave diagnostic mode. */
349 psycho_write(iommu->iommu_control, control);
350
351 for (i = 0; i < 16; i++) {
352 unsigned long tag, data;
353
354 tag = iommu_tag[i];
355 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
356 continue;
357
358 data = iommu_data[i];
359 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
360 case 0:
361 type_string = "Protection Error";
362 break;
363 case 1:
364 type_string = "Invalid Error";
365 break;
366 case 2:
367 type_string = "TimeOut Error";
368 break;
369 case 3:
370 default:
371 type_string = "ECC Error";
372 break;
373 };
374 printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
375 pbm->name, i, type_string,
376 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
377 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
378 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
379 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
380 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
381 pbm->name, i,
382 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
383 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
384 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
385 }
386 }
387 __psycho_check_stc_error(pbm, afsr, afar, type);
388 spin_unlock_irqrestore(&iommu->lock, flags);
389}
390 111
391/* Uncorrectable Errors. Cause of the error and the address are 112/* Uncorrectable Errors. Cause of the error and the address are
392 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors 113 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
@@ -410,15 +131,14 @@ static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
410static irqreturn_t psycho_ue_intr(int irq, void *dev_id) 131static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
411{ 132{
412 struct pci_pbm_info *pbm = dev_id; 133 struct pci_pbm_info *pbm = dev_id;
413 struct pci_controller_info *p = pbm->parent;
414 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR; 134 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
415 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR; 135 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
416 unsigned long afsr, afar, error_bits; 136 unsigned long afsr, afar, error_bits;
417 int reported; 137 int reported;
418 138
419 /* Latch uncorrectable error status. */ 139 /* Latch uncorrectable error status. */
420 afar = psycho_read(afar_reg); 140 afar = upa_readq(afar_reg);
421 afsr = psycho_read(afsr_reg); 141 afsr = upa_readq(afsr_reg);
422 142
423 /* Clear the primary/secondary error status bits. */ 143 /* Clear the primary/secondary error status bits. */
424 error_bits = afsr & 144 error_bits = afsr &
@@ -426,7 +146,7 @@ static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
426 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); 146 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
427 if (!error_bits) 147 if (!error_bits)
428 return IRQ_NONE; 148 return IRQ_NONE;
429 psycho_write(afsr_reg, error_bits); 149 upa_writeq(error_bits, afsr_reg);
430 150
431 /* Log the error. */ 151 /* Log the error. */
432 printk("%s: Uncorrectable Error, primary error type[%s]\n", 152 printk("%s: Uncorrectable Error, primary error type[%s]\n",
@@ -463,8 +183,9 @@ static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
463 printk("]\n"); 183 printk("]\n");
464 184
465 /* Interrogate both IOMMUs for error status. */ 185 /* Interrogate both IOMMUs for error status. */
466 psycho_check_iommu_error(&p->pbm_A, afsr, afar, UE_ERR); 186 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
467 psycho_check_iommu_error(&p->pbm_B, afsr, afar, UE_ERR); 187 if (pbm->sibling)
188 psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR);
468 189
469 return IRQ_HANDLED; 190 return IRQ_HANDLED;
470} 191}
@@ -495,8 +216,8 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
495 int reported; 216 int reported;
496 217
497 /* Latch error status. */ 218 /* Latch error status. */
498 afar = psycho_read(afar_reg); 219 afar = upa_readq(afar_reg);
499 afsr = psycho_read(afsr_reg); 220 afsr = upa_readq(afsr_reg);
500 221
501 /* Clear primary/secondary error status bits. */ 222 /* Clear primary/secondary error status bits. */
502 error_bits = afsr & 223 error_bits = afsr &
@@ -504,7 +225,7 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
504 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); 225 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
505 if (!error_bits) 226 if (!error_bits)
506 return IRQ_NONE; 227 return IRQ_NONE;
507 psycho_write(afsr_reg, error_bits); 228 upa_writeq(error_bits, afsr_reg);
508 229
509 /* Log the error. */ 230 /* Log the error. */
510 printk("%s: Correctable Error, primary error type[%s]\n", 231 printk("%s: Correctable Error, primary error type[%s]\n",
@@ -554,164 +275,9 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
554 */ 275 */
555#define PSYCHO_PCI_AFSR_A 0x2010UL 276#define PSYCHO_PCI_AFSR_A 0x2010UL
556#define PSYCHO_PCI_AFSR_B 0x4010UL 277#define PSYCHO_PCI_AFSR_B 0x4010UL
557#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
558#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
559#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
560#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
561#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
562#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
563#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
564#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
565#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
566#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
567#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
568#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
569#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
570#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
571#define PSYCHO_PCI_AFAR_A 0x2018UL 278#define PSYCHO_PCI_AFAR_A 0x2018UL
572#define PSYCHO_PCI_AFAR_B 0x4018UL 279#define PSYCHO_PCI_AFAR_B 0x4018UL
573 280
574static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
575{
576 unsigned long csr_reg, csr, csr_error_bits;
577 irqreturn_t ret = IRQ_NONE;
578 u16 stat, *addr;
579
580 if (is_pbm_a) {
581 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
582 } else {
583 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
584 }
585 csr = psycho_read(csr_reg);
586 csr_error_bits =
587 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
588 if (csr_error_bits) {
589 /* Clear the errors. */
590 psycho_write(csr_reg, csr);
591
592 /* Log 'em. */
593 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
594 printk("%s: PCI streaming byte hole error asserted.\n",
595 pbm->name);
596 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
597 printk("%s: PCI SERR signal asserted.\n", pbm->name);
598 ret = IRQ_HANDLED;
599 }
600 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
601 0, PCI_STATUS);
602 pci_config_read16(addr, &stat);
603 if (stat & (PCI_STATUS_PARITY |
604 PCI_STATUS_SIG_TARGET_ABORT |
605 PCI_STATUS_REC_TARGET_ABORT |
606 PCI_STATUS_REC_MASTER_ABORT |
607 PCI_STATUS_SIG_SYSTEM_ERROR)) {
608 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
609 pbm->name, stat);
610 pci_config_write16(addr, 0xffff);
611 ret = IRQ_HANDLED;
612 }
613 return ret;
614}
615
616static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
617{
618 struct pci_pbm_info *pbm = dev_id;
619 struct pci_controller_info *p = pbm->parent;
620 unsigned long afsr_reg, afar_reg;
621 unsigned long afsr, afar, error_bits;
622 int is_pbm_a, reported;
623
624 is_pbm_a = (pbm == &pbm->parent->pbm_A);
625 if (is_pbm_a) {
626 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
627 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
628 } else {
629 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
630 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
631 }
632
633 /* Latch error status. */
634 afar = psycho_read(afar_reg);
635 afsr = psycho_read(afsr_reg);
636
637 /* Clear primary/secondary error status bits. */
638 error_bits = afsr &
639 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
640 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
641 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
642 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
643 if (!error_bits)
644 return psycho_pcierr_intr_other(pbm, is_pbm_a);
645 psycho_write(afsr_reg, error_bits);
646
647 /* Log the error. */
648 printk("%s: PCI Error, primary error type[%s]\n",
649 pbm->name,
650 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
651 "Master Abort" :
652 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
653 "Target Abort" :
654 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
655 "Excessive Retries" :
656 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
657 "Parity Error" : "???"))))));
658 printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
659 pbm->name,
660 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
661 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
662 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
663 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
664 printk("%s: PCI Secondary errors [", pbm->name);
665 reported = 0;
666 if (afsr & PSYCHO_PCIAFSR_SMA) {
667 reported++;
668 printk("(Master Abort)");
669 }
670 if (afsr & PSYCHO_PCIAFSR_STA) {
671 reported++;
672 printk("(Target Abort)");
673 }
674 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
675 reported++;
676 printk("(Excessive Retries)");
677 }
678 if (afsr & PSYCHO_PCIAFSR_SPERR) {
679 reported++;
680 printk("(Parity Error)");
681 }
682 if (!reported)
683 printk("(none)");
684 printk("]\n");
685
686 /* For the error types shown, scan PBM's PCI bus for devices
687 * which have logged that error type.
688 */
689
690 /* If we see a Target Abort, this could be the result of an
691 * IOMMU translation error of some sort. It is extremely
692 * useful to log this information as usually it indicates
693 * a bug in the IOMMU support code or a PCI device driver.
694 */
695 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
696 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
697 pci_scan_for_target_abort(pbm, pbm->pci_bus);
698 }
699 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
700 pci_scan_for_master_abort(pbm, pbm->pci_bus);
701
702 /* For excessive retries, PSYCHO/PBM will abort the device
703 * and there is no way to specifically check for excessive
704 * retries in the config space status registers. So what
705 * we hope is that we'll catch it via the master/target
706 * abort events.
707 */
708
709 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
710 pci_scan_for_parity_error(pbm, pbm->pci_bus);
711
712 return IRQ_HANDLED;
713}
714
715/* XXX What about PowerFail/PowerManagement??? -DaveM */ 281/* XXX What about PowerFail/PowerManagement??? -DaveM */
716#define PSYCHO_ECC_CTRL 0x0020 282#define PSYCHO_ECC_CTRL 0x0020
717#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 283#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
@@ -719,7 +285,7 @@ static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
719#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 285#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
720static void psycho_register_error_handlers(struct pci_pbm_info *pbm) 286static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
721{ 287{
722 struct of_device *op = of_find_device_by_node(pbm->prom_node); 288 struct of_device *op = of_find_device_by_node(pbm->op->node);
723 unsigned long base = pbm->controller_regs; 289 unsigned long base = pbm->controller_regs;
724 u64 tmp; 290 u64 tmp;
725 int err; 291 int err;
@@ -762,27 +328,26 @@ static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
762 "err=%d\n", pbm->name, err); 328 "err=%d\n", pbm->name, err);
763 329
764 /* Enable UE and CE interrupts for controller. */ 330 /* Enable UE and CE interrupts for controller. */
765 psycho_write(base + PSYCHO_ECC_CTRL, 331 upa_writeq((PSYCHO_ECCCTRL_EE |
766 (PSYCHO_ECCCTRL_EE | 332 PSYCHO_ECCCTRL_UE |
767 PSYCHO_ECCCTRL_UE | 333 PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL);
768 PSYCHO_ECCCTRL_CE));
769 334
770 /* Enable PCI Error interrupts and clear error 335 /* Enable PCI Error interrupts and clear error
771 * bits for each PBM. 336 * bits for each PBM.
772 */ 337 */
773 tmp = psycho_read(base + PSYCHO_PCIA_CTRL); 338 tmp = upa_readq(base + PSYCHO_PCIA_CTRL);
774 tmp |= (PSYCHO_PCICTRL_SERR | 339 tmp |= (PSYCHO_PCICTRL_SERR |
775 PSYCHO_PCICTRL_SBH_ERR | 340 PSYCHO_PCICTRL_SBH_ERR |
776 PSYCHO_PCICTRL_EEN); 341 PSYCHO_PCICTRL_EEN);
777 tmp &= ~(PSYCHO_PCICTRL_SBH_INT); 342 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
778 psycho_write(base + PSYCHO_PCIA_CTRL, tmp); 343 upa_writeq(tmp, base + PSYCHO_PCIA_CTRL);
779 344
780 tmp = psycho_read(base + PSYCHO_PCIB_CTRL); 345 tmp = upa_readq(base + PSYCHO_PCIB_CTRL);
781 tmp |= (PSYCHO_PCICTRL_SERR | 346 tmp |= (PSYCHO_PCICTRL_SERR |
782 PSYCHO_PCICTRL_SBH_ERR | 347 PSYCHO_PCICTRL_SBH_ERR |
783 PSYCHO_PCICTRL_EEN); 348 PSYCHO_PCICTRL_EEN);
784 tmp &= ~(PSYCHO_PCICTRL_SBH_INT); 349 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
785 psycho_write(base + PSYCHO_PCIB_CTRL, tmp); 350 upa_writeq(tmp, base + PSYCHO_PCIB_CTRL);
786} 351}
787 352
788/* PSYCHO boot time probing and initialization. */ 353/* PSYCHO boot time probing and initialization. */
@@ -803,11 +368,12 @@ static void pbm_config_busmastering(struct pci_pbm_info *pbm)
803 pci_config_write8(addr, 64); 368 pci_config_write8(addr, 64);
804} 369}
805 370
806static void __init psycho_scan_bus(struct pci_pbm_info *pbm) 371static void __init psycho_scan_bus(struct pci_pbm_info *pbm,
372 struct device *parent)
807{ 373{
808 pbm_config_busmastering(pbm); 374 pbm_config_busmastering(pbm);
809 pbm->is_66mhz_capable = 0; 375 pbm->is_66mhz_capable = 0;
810 pbm->pci_bus = pci_scan_one_pbm(pbm); 376 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
811 377
812 /* After the PCI bus scan is complete, we can register 378 /* After the PCI bus scan is complete, we can register
813 * the error interrupt handlers. 379 * the error interrupt handlers.
@@ -815,61 +381,6 @@ static void __init psycho_scan_bus(struct pci_pbm_info *pbm)
815 psycho_register_error_handlers(pbm); 381 psycho_register_error_handlers(pbm);
816} 382}
817 383
818static int psycho_iommu_init(struct pci_pbm_info *pbm)
819{
820 struct iommu *iommu = pbm->iommu;
821 unsigned long i;
822 u64 control;
823 int err;
824
825 /* Register addresses. */
826 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
827 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
828 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
829 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
830
831 /* PSYCHO's IOMMU lacks ctx flushing. */
832 iommu->iommu_ctxflush = 0;
833
834 /* We use the main control register of PSYCHO as the write
835 * completion register.
836 */
837 iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL;
838
839 /*
840 * Invalidate TLB Entries.
841 */
842 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
843 control |= PSYCHO_IOMMU_CTRL_DENAB;
844 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
845 for(i = 0; i < 16; i++) {
846 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
847 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
848 }
849
850 /* Leave diag mode enabled for full-flushing done
851 * in pci_iommu.c
852 */
853 err = iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff,
854 pbm->numa_node);
855 if (err)
856 return err;
857
858 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE,
859 __pa(iommu->page_table));
860
861 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
862 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
863 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
864 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
865
866 /* If necessary, hook us up for starfire IRQ translations. */
867 if (this_is_starfire)
868 starfire_hookup(pbm->portid);
869
870 return 0;
871}
872
873#define PSYCHO_IRQ_RETRY 0x1a00UL 384#define PSYCHO_IRQ_RETRY 0x1a00UL
874#define PSYCHO_PCIA_DIAG 0x2020UL 385#define PSYCHO_PCIA_DIAG 0x2020UL
875#define PSYCHO_PCIB_DIAG 0x4020UL 386#define PSYCHO_PCIB_DIAG 0x4020UL
@@ -886,28 +397,28 @@ static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
886{ 397{
887 u64 tmp; 398 u64 tmp;
888 399
889 psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5); 400 upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY);
890 401
891 /* Enable arbiter for all PCI slots. */ 402 /* Enable arbiter for all PCI slots. */
892 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL); 403 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL);
893 tmp |= PSYCHO_PCICTRL_AEN; 404 tmp |= PSYCHO_PCICTRL_AEN;
894 psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp); 405 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL);
895 406
896 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL); 407 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL);
897 tmp |= PSYCHO_PCICTRL_AEN; 408 tmp |= PSYCHO_PCICTRL_AEN;
898 psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp); 409 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL);
899 410
900 /* Disable DMA write / PIO read synchronization on 411 /* Disable DMA write / PIO read synchronization on
901 * both PCI bus segments. 412 * both PCI bus segments.
902 * [ U2P Erratum 1243770, STP2223BGA data sheet ] 413 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
903 */ 414 */
904 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG); 415 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG);
905 tmp |= PSYCHO_PCIDIAG_DDWSYNC; 416 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
906 psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp); 417 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG);
907 418
908 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG); 419 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG);
909 tmp |= PSYCHO_PCIDIAG_DDWSYNC; 420 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
910 psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp); 421 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG);
911} 422}
912 423
913static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, 424static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
@@ -920,10 +431,16 @@ static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
920 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; 431 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
921 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; 432 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
922 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; 433 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
434 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A;
435 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A;
436 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A;
923 } else { 437 } else {
924 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; 438 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
925 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; 439 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
926 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; 440 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
441 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B;
442 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B;
443 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B;
927 } 444 }
928 /* PSYCHO's streaming buffer lacks ctx flushing. */ 445 /* PSYCHO's streaming buffer lacks ctx flushing. */
929 pbm->stc.strbuf_ctxflush = 0; 446 pbm->stc.strbuf_ctxflush = 0;
@@ -946,7 +463,7 @@ static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
946 */ 463 */
947#undef PSYCHO_STRBUF_RERUN_ENABLE 464#undef PSYCHO_STRBUF_RERUN_ENABLE
948#undef PSYCHO_STRBUF_RERUN_DISABLE 465#undef PSYCHO_STRBUF_RERUN_DISABLE
949 control = psycho_read(pbm->stc.strbuf_control); 466 control = upa_readq(pbm->stc.strbuf_control);
950 control |= PSYCHO_STRBUF_CTRL_ENAB; 467 control |= PSYCHO_STRBUF_CTRL_ENAB;
951 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); 468 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
952#ifdef PSYCHO_STRBUF_RERUN_ENABLE 469#ifdef PSYCHO_STRBUF_RERUN_ENABLE
@@ -956,7 +473,7 @@ static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
956 control |= PSYCHO_STRBUF_CTRL_RRDIS; 473 control |= PSYCHO_STRBUF_CTRL_RRDIS;
957#endif 474#endif
958#endif 475#endif
959 psycho_write(pbm->stc.strbuf_control, control); 476 upa_writeq(control, pbm->stc.strbuf_control);
960 477
961 pbm->stc.strbuf_enabled = 1; 478 pbm->stc.strbuf_enabled = 1;
962} 479}
@@ -968,111 +485,134 @@ static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
968#define PSYCHO_MEMSPACE_B 0x180000000UL 485#define PSYCHO_MEMSPACE_B 0x180000000UL
969#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL 486#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
970 487
971static void __init psycho_pbm_init(struct pci_controller_info *p, 488static void __init psycho_pbm_init(struct pci_pbm_info *pbm,
972 struct device_node *dp, int is_pbm_a) 489 struct of_device *op, int is_pbm_a)
973{ 490{
974 struct property *prop; 491 psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO);
975 struct pci_pbm_info *pbm; 492 psycho_pbm_strbuf_init(pbm, is_pbm_a);
976 493 psycho_scan_bus(pbm, &op->dev);
977 if (is_pbm_a) 494}
978 pbm = &p->pbm_A;
979 else
980 pbm = &p->pbm_B;
981
982 pbm->next = pci_pbm_root;
983 pci_pbm_root = pbm;
984
985 pbm->numa_node = -1;
986
987 pbm->scan_bus = psycho_scan_bus;
988 pbm->pci_ops = &sun4u_pci_ops;
989 pbm->config_space_reg_bits = 8;
990
991 pbm->index = pci_num_pbms++;
992
993 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
994 pbm->chip_version = 0;
995 prop = of_find_property(dp, "version#", NULL);
996 if (prop)
997 pbm->chip_version = *(int *) prop->value;
998 pbm->chip_revision = 0;
999 prop = of_find_property(dp, "module-revision#", NULL);
1000 if (prop)
1001 pbm->chip_revision = *(int *) prop->value;
1002
1003 pbm->parent = p;
1004 pbm->prom_node = dp;
1005 pbm->name = dp->full_name;
1006
1007 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1008 pbm->name,
1009 pbm->chip_version, pbm->chip_revision);
1010
1011 pci_determine_mem_io_space(pbm);
1012 495
1013 pci_get_pbm_props(pbm); 496static struct pci_pbm_info * __devinit psycho_find_sibling(u32 upa_portid)
497{
498 struct pci_pbm_info *pbm;
1014 499
1015 psycho_pbm_strbuf_init(pbm, is_pbm_a); 500 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
501 if (pbm->portid == upa_portid)
502 return pbm;
503 }
504 return NULL;
1016} 505}
1017 506
1018#define PSYCHO_CONFIGSPACE 0x001000000UL 507#define PSYCHO_CONFIGSPACE 0x001000000UL
1019 508
1020void __init psycho_init(struct device_node *dp, char *model_name) 509static int __devinit psycho_probe(struct of_device *op,
510 const struct of_device_id *match)
1021{ 511{
1022 struct linux_prom64_registers *pr_regs; 512 const struct linux_prom64_registers *pr_regs;
1023 struct pci_controller_info *p; 513 struct device_node *dp = op->node;
1024 struct pci_pbm_info *pbm; 514 struct pci_pbm_info *pbm;
1025 struct iommu *iommu; 515 struct iommu *iommu;
1026 struct property *prop; 516 int is_pbm_a, err;
1027 u32 upa_portid; 517 u32 upa_portid;
1028 int is_pbm_a;
1029 518
1030 upa_portid = 0xff; 519 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
1031 prop = of_find_property(dp, "upa-portid", NULL);
1032 if (prop)
1033 upa_portid = *(u32 *) prop->value;
1034 520
1035 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 521 err = -ENOMEM;
1036 struct pci_controller_info *p = pbm->parent; 522 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
523 if (!pbm) {
524 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
525 goto out_err;
526 }
1037 527
1038 if (p->pbm_A.portid == upa_portid) { 528 pbm->sibling = psycho_find_sibling(upa_portid);
1039 is_pbm_a = (p->pbm_A.prom_node == NULL); 529 if (pbm->sibling) {
1040 psycho_pbm_init(p, dp, is_pbm_a); 530 iommu = pbm->sibling->iommu;
1041 return; 531 } else {
532 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
533 if (!iommu) {
534 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
535 goto out_free_controller;
1042 } 536 }
1043 } 537 }
1044 538
1045 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); 539 pbm->iommu = iommu;
1046 if (!p) 540 pbm->portid = upa_portid;
1047 goto fatal_memory_error;
1048 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1049 if (!iommu)
1050 goto fatal_memory_error;
1051 541
1052 p->pbm_A.iommu = p->pbm_B.iommu = iommu; 542 pr_regs = of_get_property(dp, "reg", NULL);
543 err = -ENODEV;
544 if (!pr_regs) {
545 printk(KERN_ERR PFX "No reg property.\n");
546 goto out_free_iommu;
547 }
1053 548
1054 p->pbm_A.portid = upa_portid; 549 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1055 p->pbm_B.portid = upa_portid;
1056 550
1057 prop = of_find_property(dp, "reg", NULL); 551 pbm->controller_regs = pr_regs[2].phys_addr;
1058 pr_regs = prop->value; 552 pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1059 553
1060 p->pbm_A.controller_regs = pr_regs[2].phys_addr; 554 if (is_pbm_a) {
1061 p->pbm_B.controller_regs = pr_regs[2].phys_addr; 555 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A;
556 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A;
557 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL;
558 } else {
559 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B;
560 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B;
561 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL;
562 }
1062 563
1063 p->pbm_A.config_space = p->pbm_B.config_space = 564 psycho_controller_hwinit(pbm);
1064 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); 565 if (!pbm->sibling) {
566 err = psycho_iommu_init(pbm, 128, 0xc0000000,
567 0xffffffff, PSYCHO_CONTROL);
568 if (err)
569 goto out_free_iommu;
1065 570
1066 psycho_controller_hwinit(&p->pbm_A); 571 /* If necessary, hook us up for starfire IRQ translations. */
572 if (this_is_starfire)
573 starfire_hookup(pbm->portid);
574 }
1067 575
1068 if (psycho_iommu_init(&p->pbm_A)) 576 psycho_pbm_init(pbm, op, is_pbm_a);
1069 goto fatal_memory_error;
1070 577
1071 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); 578 pbm->next = pci_pbm_root;
1072 psycho_pbm_init(p, dp, is_pbm_a); 579 pci_pbm_root = pbm;
1073 return; 580
581 if (pbm->sibling)
582 pbm->sibling->sibling = pbm;
583
584 dev_set_drvdata(&op->dev, pbm);
585
586 return 0;
587
588out_free_iommu:
589 if (!pbm->sibling)
590 kfree(pbm->iommu);
1074 591
1075fatal_memory_error: 592out_free_controller:
1076 prom_printf("PSYCHO: Fatal memory allocation error.\n"); 593 kfree(pbm);
1077 prom_halt(); 594
595out_err:
596 return err;
1078} 597}
598
599static struct of_device_id __initdata psycho_match[] = {
600 {
601 .name = "pci",
602 .compatible = "pci108e,8000",
603 },
604 {},
605};
606
607static struct of_platform_driver psycho_driver = {
608 .name = DRIVER_NAME,
609 .match_table = psycho_match,
610 .probe = psycho_probe,
611};
612
613static int __init psycho_init(void)
614{
615 return of_register_driver(&psycho_driver, &of_bus_type);
616}
617
618subsys_initcall(psycho_init);
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index ade5184e75d..713257b6963 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -16,31 +16,15 @@
16#include <asm/apb.h> 16#include <asm/apb.h>
17#include <asm/iommu.h> 17#include <asm/iommu.h>
18#include <asm/irq.h> 18#include <asm/irq.h>
19#include <asm/smp.h>
20#include <asm/oplib.h>
21#include <asm/prom.h> 19#include <asm/prom.h>
20#include <asm/upa.h>
22 21
23#include "pci_impl.h" 22#include "pci_impl.h"
24#include "iommu_common.h" 23#include "iommu_common.h"
24#include "psycho_common.h"
25 25
26/* All SABRE registers are 64-bits. The following accessor 26#define DRIVER_NAME "sabre"
27 * routines are how they are accessed. The REG parameter 27#define PFX DRIVER_NAME ": "
28 * is a physical address.
29 */
30#define sabre_read(__reg) \
31({ u64 __ret; \
32 __asm__ __volatile__("ldxa [%1] %2, %0" \
33 : "=r" (__ret) \
34 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
35 : "memory"); \
36 __ret; \
37})
38#define sabre_write(__reg, __val) \
39 __asm__ __volatile__("stxa %0, [%1] %2" \
40 : /* no outputs */ \
41 : "r" (__val), "r" (__reg), \
42 "i" (ASI_PHYS_BYPASS_EC_E) \
43 : "memory")
44 28
45/* SABRE PCI controller register offsets and definitions. */ 29/* SABRE PCI controller register offsets and definitions. */
46#define SABRE_UE_AFSR 0x0030UL 30#define SABRE_UE_AFSR 0x0030UL
@@ -208,95 +192,6 @@
208static int hummingbird_p; 192static int hummingbird_p;
209static struct pci_bus *sabre_root_bus; 193static struct pci_bus *sabre_root_bus;
210 194
211/* SABRE error handling support. */
212static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
213 unsigned long afsr,
214 unsigned long afar)
215{
216 struct iommu *iommu = pbm->iommu;
217 unsigned long iommu_tag[16];
218 unsigned long iommu_data[16];
219 unsigned long flags;
220 u64 control;
221 int i;
222
223 spin_lock_irqsave(&iommu->lock, flags);
224 control = sabre_read(iommu->iommu_control);
225 if (control & SABRE_IOMMUCTRL_ERR) {
226 char *type_string;
227
228 /* Clear the error encountered bit.
229 * NOTE: On Sabre this is write 1 to clear,
230 * which is different from Psycho.
231 */
232 sabre_write(iommu->iommu_control, control);
233 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
234 case 1:
235 type_string = "Invalid Error";
236 break;
237 case 3:
238 type_string = "ECC Error";
239 break;
240 default:
241 type_string = "Unknown";
242 break;
243 };
244 printk("%s: IOMMU Error, type[%s]\n",
245 pbm->name, type_string);
246
247 /* Enter diagnostic mode and probe for error'd
248 * entries in the IOTLB.
249 */
250 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
251 sabre_write(iommu->iommu_control,
252 (control | SABRE_IOMMUCTRL_DENAB));
253 for (i = 0; i < 16; i++) {
254 unsigned long base = pbm->controller_regs;
255
256 iommu_tag[i] =
257 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
258 iommu_data[i] =
259 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
260 sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
261 sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
262 }
263 sabre_write(iommu->iommu_control, control);
264
265 for (i = 0; i < 16; i++) {
266 unsigned long tag, data;
267
268 tag = iommu_tag[i];
269 if (!(tag & SABRE_IOMMUTAG_ERR))
270 continue;
271
272 data = iommu_data[i];
273 switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
274 case 1:
275 type_string = "Invalid Error";
276 break;
277 case 3:
278 type_string = "ECC Error";
279 break;
280 default:
281 type_string = "Unknown";
282 break;
283 };
284 printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
285 pbm->name, i, tag, type_string,
286 ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
287 ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
288 ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
289 printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
290 pbm->name, i, data,
291 ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
292 ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
293 ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
294 ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
295 }
296 }
297 spin_unlock_irqrestore(&iommu->lock, flags);
298}
299
300static irqreturn_t sabre_ue_intr(int irq, void *dev_id) 195static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
301{ 196{
302 struct pci_pbm_info *pbm = dev_id; 197 struct pci_pbm_info *pbm = dev_id;
@@ -306,8 +201,8 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
306 int reported; 201 int reported;
307 202
308 /* Latch uncorrectable error status. */ 203 /* Latch uncorrectable error status. */
309 afar = sabre_read(afar_reg); 204 afar = upa_readq(afar_reg);
310 afsr = sabre_read(afsr_reg); 205 afsr = upa_readq(afsr_reg);
311 206
312 /* Clear the primary/secondary error status bits. */ 207 /* Clear the primary/secondary error status bits. */
313 error_bits = afsr & 208 error_bits = afsr &
@@ -316,7 +211,7 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
316 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE); 211 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
317 if (!error_bits) 212 if (!error_bits)
318 return IRQ_NONE; 213 return IRQ_NONE;
319 sabre_write(afsr_reg, error_bits); 214 upa_writeq(error_bits, afsr_reg);
320 215
321 /* Log the error. */ 216 /* Log the error. */
322 printk("%s: Uncorrectable Error, primary error type[%s%s]\n", 217 printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
@@ -352,7 +247,7 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
352 printk("]\n"); 247 printk("]\n");
353 248
354 /* Interrogate IOMMU for error status. */ 249 /* Interrogate IOMMU for error status. */
355 sabre_check_iommu_error(pbm, afsr, afar); 250 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
356 251
357 return IRQ_HANDLED; 252 return IRQ_HANDLED;
358} 253}
@@ -366,8 +261,8 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
366 int reported; 261 int reported;
367 262
368 /* Latch error status. */ 263 /* Latch error status. */
369 afar = sabre_read(afar_reg); 264 afar = upa_readq(afar_reg);
370 afsr = sabre_read(afsr_reg); 265 afsr = upa_readq(afsr_reg);
371 266
372 /* Clear primary/secondary error status bits. */ 267 /* Clear primary/secondary error status bits. */
373 error_bits = afsr & 268 error_bits = afsr &
@@ -375,7 +270,7 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
375 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR); 270 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
376 if (!error_bits) 271 if (!error_bits)
377 return IRQ_NONE; 272 return IRQ_NONE;
378 sabre_write(afsr_reg, error_bits); 273 upa_writeq(error_bits, afsr_reg);
379 274
380 /* Log the error. */ 275 /* Log the error. */
381 printk("%s: Correctable Error, primary error type[%s]\n", 276 printk("%s: Correctable Error, primary error type[%s]\n",
@@ -413,136 +308,9 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
413 return IRQ_HANDLED; 308 return IRQ_HANDLED;
414} 309}
415 310
416static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm)
417{
418 unsigned long csr_reg, csr, csr_error_bits;
419 irqreturn_t ret = IRQ_NONE;
420 u16 stat;
421
422 csr_reg = pbm->controller_regs + SABRE_PCICTRL;
423 csr = sabre_read(csr_reg);
424 csr_error_bits =
425 csr & SABRE_PCICTRL_SERR;
426 if (csr_error_bits) {
427 /* Clear the errors. */
428 sabre_write(csr_reg, csr);
429
430 /* Log 'em. */
431 if (csr_error_bits & SABRE_PCICTRL_SERR)
432 printk("%s: PCI SERR signal asserted.\n",
433 pbm->name);
434 ret = IRQ_HANDLED;
435 }
436 pci_bus_read_config_word(sabre_root_bus, 0,
437 PCI_STATUS, &stat);
438 if (stat & (PCI_STATUS_PARITY |
439 PCI_STATUS_SIG_TARGET_ABORT |
440 PCI_STATUS_REC_TARGET_ABORT |
441 PCI_STATUS_REC_MASTER_ABORT |
442 PCI_STATUS_SIG_SYSTEM_ERROR)) {
443 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
444 pbm->name, stat);
445 pci_bus_write_config_word(sabre_root_bus, 0,
446 PCI_STATUS, 0xffff);
447 ret = IRQ_HANDLED;
448 }
449 return ret;
450}
451
452static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
453{
454 struct pci_pbm_info *pbm = dev_id;
455 unsigned long afsr_reg, afar_reg;
456 unsigned long afsr, afar, error_bits;
457 int reported;
458
459 afsr_reg = pbm->controller_regs + SABRE_PIOAFSR;
460 afar_reg = pbm->controller_regs + SABRE_PIOAFAR;
461
462 /* Latch error status. */
463 afar = sabre_read(afar_reg);
464 afsr = sabre_read(afsr_reg);
465
466 /* Clear primary/secondary error status bits. */
467 error_bits = afsr &
468 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
469 SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
470 SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
471 SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
472 if (!error_bits)
473 return sabre_pcierr_intr_other(pbm);
474 sabre_write(afsr_reg, error_bits);
475
476 /* Log the error. */
477 printk("%s: PCI Error, primary error type[%s]\n",
478 pbm->name,
479 (((error_bits & SABRE_PIOAFSR_PMA) ?
480 "Master Abort" :
481 ((error_bits & SABRE_PIOAFSR_PTA) ?
482 "Target Abort" :
483 ((error_bits & SABRE_PIOAFSR_PRTRY) ?
484 "Excessive Retries" :
485 ((error_bits & SABRE_PIOAFSR_PPERR) ?
486 "Parity Error" : "???"))))));
487 printk("%s: bytemask[%04lx] was_block(%d)\n",
488 pbm->name,
489 (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
490 (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
491 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
492 printk("%s: PCI Secondary errors [", pbm->name);
493 reported = 0;
494 if (afsr & SABRE_PIOAFSR_SMA) {
495 reported++;
496 printk("(Master Abort)");
497 }
498 if (afsr & SABRE_PIOAFSR_STA) {
499 reported++;
500 printk("(Target Abort)");
501 }
502 if (afsr & SABRE_PIOAFSR_SRTRY) {
503 reported++;
504 printk("(Excessive Retries)");
505 }
506 if (afsr & SABRE_PIOAFSR_SPERR) {
507 reported++;
508 printk("(Parity Error)");
509 }
510 if (!reported)
511 printk("(none)");
512 printk("]\n");
513
514 /* For the error types shown, scan both PCI buses for devices
515 * which have logged that error type.
516 */
517
518 /* If we see a Target Abort, this could be the result of an
519 * IOMMU translation error of some sort. It is extremely
520 * useful to log this information as usually it indicates
521 * a bug in the IOMMU support code or a PCI device driver.
522 */
523 if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
524 sabre_check_iommu_error(pbm, afsr, afar);
525 pci_scan_for_target_abort(pbm, pbm->pci_bus);
526 }
527 if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
528 pci_scan_for_master_abort(pbm, pbm->pci_bus);
529
530 /* For excessive retries, SABRE/PBM will abort the device
531 * and there is no way to specifically check for excessive
532 * retries in the config space status registers. So what
533 * we hope is that we'll catch it via the master/target
534 * abort events.
535 */
536
537 if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
538 pci_scan_for_parity_error(pbm, pbm->pci_bus);
539
540 return IRQ_HANDLED;
541}
542
543static void sabre_register_error_handlers(struct pci_pbm_info *pbm) 311static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
544{ 312{
545 struct device_node *dp = pbm->prom_node; 313 struct device_node *dp = pbm->op->node;
546 struct of_device *op; 314 struct of_device *op;
547 unsigned long base = pbm->controller_regs; 315 unsigned long base = pbm->controller_regs;
548 u64 tmp; 316 u64 tmp;
@@ -568,33 +336,34 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
568 * registering the handler so that we don't get spurious 336 * registering the handler so that we don't get spurious
569 * interrupts. 337 * interrupts.
570 */ 338 */
571 sabre_write(base + SABRE_UE_AFSR, 339 upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
572 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | 340 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
573 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | 341 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE),
574 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE)); 342 base + SABRE_UE_AFSR);
575 343
576 err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm); 344 err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
577 if (err) 345 if (err)
578 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n", 346 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
579 pbm->name, err); 347 pbm->name, err);
580 348
581 sabre_write(base + SABRE_CE_AFSR, 349 upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
582 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | 350 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR),
583 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR)); 351 base + SABRE_CE_AFSR);
352
584 353
585 err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm); 354 err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
586 if (err) 355 if (err)
587 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n", 356 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
588 pbm->name, err); 357 pbm->name, err);
589 err = request_irq(op->irqs[0], sabre_pcierr_intr, 0, 358 err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
590 "SABRE_PCIERR", pbm); 359 "SABRE_PCIERR", pbm);
591 if (err) 360 if (err)
592 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n", 361 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
593 pbm->name, err); 362 pbm->name, err);
594 363
595 tmp = sabre_read(base + SABRE_PCICTRL); 364 tmp = upa_readq(base + SABRE_PCICTRL);
596 tmp |= SABRE_PCICTRL_ERREN; 365 tmp |= SABRE_PCICTRL_ERREN;
597 sabre_write(base + SABRE_PCICTRL, tmp); 366 upa_writeq(tmp, base + SABRE_PCICTRL);
598} 367}
599 368
600static void apb_init(struct pci_bus *sabre_bus) 369static void apb_init(struct pci_bus *sabre_bus)
@@ -633,7 +402,8 @@ static void apb_init(struct pci_bus *sabre_bus)
633 } 402 }
634} 403}
635 404
636static void __init sabre_scan_bus(struct pci_pbm_info *pbm) 405static void __init sabre_scan_bus(struct pci_pbm_info *pbm,
406 struct device *parent)
637{ 407{
638 static int once; 408 static int once;
639 409
@@ -656,12 +426,12 @@ static void __init sabre_scan_bus(struct pci_pbm_info *pbm)
656 * to live at bus 0. 426 * to live at bus 0.
657 */ 427 */
658 if (once != 0) { 428 if (once != 0) {
659 prom_printf("SABRE: Multiple controllers unsupported.\n"); 429 printk(KERN_ERR PFX "Multiple controllers unsupported.\n");
660 prom_halt(); 430 return;
661 } 431 }
662 once++; 432 once++;
663 433
664 pbm->pci_bus = pci_scan_one_pbm(pbm); 434 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
665 if (!pbm->pci_bus) 435 if (!pbm->pci_bus)
666 return; 436 return;
667 437
@@ -672,133 +442,58 @@ static void __init sabre_scan_bus(struct pci_pbm_info *pbm)
672 sabre_register_error_handlers(pbm); 442 sabre_register_error_handlers(pbm);
673} 443}
674 444
675static int sabre_iommu_init(struct pci_pbm_info *pbm, 445static void __init sabre_pbm_init(struct pci_pbm_info *pbm,
676 int tsbsize, unsigned long dvma_offset, 446 struct of_device *op)
677 u32 dma_mask)
678{
679 struct iommu *iommu = pbm->iommu;
680 unsigned long i;
681 u64 control;
682 int err;
683
684 /* Register addresses. */
685 iommu->iommu_control = pbm->controller_regs + SABRE_IOMMU_CONTROL;
686 iommu->iommu_tsbbase = pbm->controller_regs + SABRE_IOMMU_TSBBASE;
687 iommu->iommu_flush = pbm->controller_regs + SABRE_IOMMU_FLUSH;
688 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
689 iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC;
690 /* Sabre's IOMMU lacks ctx flushing. */
691 iommu->iommu_ctxflush = 0;
692
693 /* Invalidate TLB Entries. */
694 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
695 control |= SABRE_IOMMUCTRL_DENAB;
696 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
697
698 for(i = 0; i < 16; i++) {
699 sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
700 sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
701 }
702
703 /* Leave diag mode enabled for full-flushing done
704 * in pci_iommu.c
705 */
706 err = iommu_table_init(iommu, tsbsize * 1024 * 8,
707 dvma_offset, dma_mask, pbm->numa_node);
708 if (err)
709 return err;
710
711 sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE,
712 __pa(iommu->page_table));
713
714 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
715 control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
716 control |= SABRE_IOMMUCTRL_ENAB;
717 switch(tsbsize) {
718 case 64:
719 control |= SABRE_IOMMU_TSBSZ_64K;
720 break;
721 case 128:
722 control |= SABRE_IOMMU_TSBSZ_128K;
723 break;
724 default:
725 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
726 prom_halt();
727 break;
728 }
729 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
730
731 return 0;
732}
733
734static void __init sabre_pbm_init(struct pci_controller_info *p,
735 struct pci_pbm_info *pbm, struct device_node *dp)
736{ 447{
737 pbm->name = dp->full_name; 448 psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);
738 printk("%s: SABRE PCI Bus Module\n", pbm->name); 449 pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;
739 450 pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;
740 pbm->numa_node = -1; 451 pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;
741 452 sabre_scan_bus(pbm, &op->dev);
742 pbm->scan_bus = sabre_scan_bus;
743 pbm->pci_ops = &sun4u_pci_ops;
744 pbm->config_space_reg_bits = 8;
745
746 pbm->index = pci_num_pbms++;
747
748 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
749 pbm->parent = p;
750 pbm->prom_node = dp;
751 pci_get_pbm_props(pbm);
752
753 pci_determine_mem_io_space(pbm);
754} 453}
755 454
756void __init sabre_init(struct device_node *dp, char *model_name) 455static int __devinit sabre_probe(struct of_device *op,
456 const struct of_device_id *match)
757{ 457{
758 const struct linux_prom64_registers *pr_regs; 458 const struct linux_prom64_registers *pr_regs;
759 struct pci_controller_info *p; 459 struct device_node *dp = op->node;
760 struct pci_pbm_info *pbm; 460 struct pci_pbm_info *pbm;
461 u32 upa_portid, dma_mask;
761 struct iommu *iommu; 462 struct iommu *iommu;
762 int tsbsize; 463 int tsbsize, err;
763 const u32 *vdma; 464 const u32 *vdma;
764 u32 upa_portid, dma_mask;
765 u64 clear_irq; 465 u64 clear_irq;
766 466
767 hummingbird_p = 0; 467 hummingbird_p = (match->data != NULL);
768 if (!strcmp(model_name, "pci108e,a001")) 468 if (!hummingbird_p) {
769 hummingbird_p = 1; 469 struct device_node *cpu_dp;
770 else if (!strcmp(model_name, "SUNW,sabre")) { 470
771 const char *compat = of_get_property(dp, "compatible", NULL); 471 /* Of course, Sun has to encode things a thousand
772 if (compat && !strcmp(compat, "pci108e,a001")) 472 * different ways, inconsistently.
773 hummingbird_p = 1; 473 */
774 if (!hummingbird_p) { 474 for_each_node_by_type(cpu_dp, "cpu") {
775 struct device_node *dp; 475 if (!strcmp(cpu_dp->name, "SUNW,UltraSPARC-IIe"))
776 476 hummingbird_p = 1;
777 /* Of course, Sun has to encode things a thousand
778 * different ways, inconsistently.
779 */
780 for_each_node_by_type(dp, "cpu") {
781 if (!strcmp(dp->name, "SUNW,UltraSPARC-IIe"))
782 hummingbird_p = 1;
783 }
784 } 477 }
785 } 478 }
786 479
787 p = kzalloc(sizeof(*p), GFP_ATOMIC); 480 err = -ENOMEM;
788 if (!p) 481 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
789 goto fatal_memory_error; 482 if (!pbm) {
483 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
484 goto out_err;
485 }
486
487 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
488 if (!iommu) {
489 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
490 goto out_free_controller;
491 }
790 492
791 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
792 if (!iommu)
793 goto fatal_memory_error;
794 pbm = &p->pbm_A;
795 pbm->iommu = iommu; 493 pbm->iommu = iommu;
796 494
797 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); 495 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
798 496
799 pbm->next = pci_pbm_root;
800 pci_pbm_root = pbm;
801
802 pbm->portid = upa_portid; 497 pbm->portid = upa_portid;
803 498
804 /* 499 /*
@@ -806,6 +501,11 @@ void __init sabre_init(struct device_node *dp, char *model_name)
806 */ 501 */
807 502
808 pr_regs = of_get_property(dp, "reg", NULL); 503 pr_regs = of_get_property(dp, "reg", NULL);
504 err = -ENODEV;
505 if (!pr_regs) {
506 printk(KERN_ERR PFX "No reg property\n");
507 goto out_free_iommu;
508 }
809 509
810 /* 510 /*
811 * First REG in property is base of entire SABRE register space. 511 * First REG in property is base of entire SABRE register space.
@@ -816,22 +516,25 @@ void __init sabre_init(struct device_node *dp, char *model_name)
816 516
817 /* PCI first */ 517 /* PCI first */
818 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) 518 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
819 sabre_write(pbm->controller_regs + clear_irq, 0x0UL); 519 upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
820 520
821 /* Then OBIO */ 521 /* Then OBIO */
822 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) 522 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
823 sabre_write(pbm->controller_regs + clear_irq, 0x0UL); 523 upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
824 524
825 /* Error interrupts are enabled later after the bus scan. */ 525 /* Error interrupts are enabled later after the bus scan. */
826 sabre_write(pbm->controller_regs + SABRE_PCICTRL, 526 upa_writeq((SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
827 (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | 527 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN),
828 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN)); 528 pbm->controller_regs + SABRE_PCICTRL);
829 529
830 /* Now map in PCI config space for entire SABRE. */ 530 /* Now map in PCI config space for entire SABRE. */
831 pbm->config_space = 531 pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
832 (pbm->controller_regs + SABRE_CONFIGSPACE);
833 532
834 vdma = of_get_property(dp, "virtual-dma", NULL); 533 vdma = of_get_property(dp, "virtual-dma", NULL);
534 if (!vdma) {
535 printk(KERN_ERR PFX "No virtual-dma property\n");
536 goto out_free_iommu;
537 }
835 538
836 dma_mask = vdma[0]; 539 dma_mask = vdma[0];
837 switch(vdma[1]) { 540 switch(vdma[1]) {
@@ -849,20 +552,58 @@ void __init sabre_init(struct device_node *dp, char *model_name)
849 tsbsize = 128; 552 tsbsize = 128;
850 break; 553 break;
851 default: 554 default:
852 prom_printf("SABRE: strange virtual-dma size.\n"); 555 printk(KERN_ERR PFX "Strange virtual-dma size.\n");
853 prom_halt(); 556 goto out_free_iommu;
854 } 557 }
855 558
856 if (sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask)) 559 err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC);
857 goto fatal_memory_error; 560 if (err)
561 goto out_free_iommu;
858 562
859 /* 563 /*
860 * Look for APB underneath. 564 * Look for APB underneath.
861 */ 565 */
862 sabre_pbm_init(p, pbm, dp); 566 sabre_pbm_init(pbm, op);
863 return;
864 567
865fatal_memory_error: 568 pbm->next = pci_pbm_root;
866 prom_printf("SABRE: Fatal memory allocation error.\n"); 569 pci_pbm_root = pbm;
867 prom_halt(); 570
571 dev_set_drvdata(&op->dev, pbm);
572
573 return 0;
574
575out_free_iommu:
576 kfree(pbm->iommu);
577
578out_free_controller:
579 kfree(pbm);
580
581out_err:
582 return err;
583}
584
585static struct of_device_id __initdata sabre_match[] = {
586 {
587 .name = "pci",
588 .compatible = "pci108e,a001",
589 .data = (void *) 1,
590 },
591 {
592 .name = "pci",
593 .compatible = "pci108e,a000",
594 },
595 {},
596};
597
598static struct of_platform_driver sabre_driver = {
599 .name = DRIVER_NAME,
600 .match_table = sabre_match,
601 .probe = sabre_probe,
602};
603
604static int __init sabre_init(void)
605{
606 return of_register_driver(&sabre_driver, &of_bus_type);
868} 607}
608
609subsys_initcall(sabre_init);
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index 9248c6737f0..45d9dba1ba1 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -1,6 +1,6 @@
1/* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. 1/* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
2 * 2 *
3 * Copyright (C) 2001, 2002, 2003, 2007 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */ 4 */
5 5
6#include <linux/kernel.h> 6#include <linux/kernel.h>
@@ -13,32 +13,15 @@
13 13
14#include <asm/iommu.h> 14#include <asm/iommu.h>
15#include <asm/irq.h> 15#include <asm/irq.h>
16#include <asm/upa.h>
17#include <asm/pstate.h> 16#include <asm/pstate.h>
18#include <asm/prom.h> 17#include <asm/prom.h>
19#include <asm/oplib.h> 18#include <asm/upa.h>
20 19
21#include "pci_impl.h" 20#include "pci_impl.h"
22#include "iommu_common.h" 21#include "iommu_common.h"
23 22
24/* All SCHIZO registers are 64-bits. The following accessor 23#define DRIVER_NAME "schizo"
25 * routines are how they are accessed. The REG parameter 24#define PFX DRIVER_NAME ": "
26 * is a physical address.
27 */
28#define schizo_read(__reg) \
29({ u64 __ret; \
30 __asm__ __volatile__("ldxa [%1] %2, %0" \
31 : "=r" (__ret) \
32 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
33 : "memory"); \
34 __ret; \
35})
36#define schizo_write(__reg, __val) \
37 __asm__ __volatile__("stxa %0, [%1] %2" \
38 : /* no outputs */ \
39 : "r" (__val), "r" (__reg), \
40 "i" (ASI_PHYS_BYPASS_EC_E) \
41 : "memory")
42 25
43/* This is a convention that at least Excalibur and Merlin 26/* This is a convention that at least Excalibur and Merlin
44 * follow. I suppose the SCHIZO used in Starcat and friends 27 * follow. I suppose the SCHIZO used in Starcat and friends
@@ -163,25 +146,25 @@ static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
163 * invalidating it before it has a chance to reach 146 * invalidating it before it has a chance to reach
164 * main memory. 147 * main memory.
165 */ 148 */
166 control = schizo_read(strbuf->strbuf_control); 149 control = upa_readq(strbuf->strbuf_control);
167 schizo_write(strbuf->strbuf_control, 150 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB),
168 (control | SCHIZO_STRBUF_CTRL_DENAB)); 151 strbuf->strbuf_control);
169 for (i = 0; i < 128; i++) { 152 for (i = 0; i < 128; i++) {
170 unsigned long val; 153 unsigned long val;
171 154
172 val = schizo_read(err_base + (i * 8UL)); 155 val = upa_readq(err_base + (i * 8UL));
173 schizo_write(err_base + (i * 8UL), 0UL); 156 upa_writeq(0UL, err_base + (i * 8UL));
174 stc_error_buf[i] = val; 157 stc_error_buf[i] = val;
175 } 158 }
176 for (i = 0; i < 16; i++) { 159 for (i = 0; i < 16; i++) {
177 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL)); 160 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
178 stc_line_buf[i] = schizo_read(line_base + (i * 8UL)); 161 stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
179 schizo_write(tag_base + (i * 8UL), 0UL); 162 upa_writeq(0UL, tag_base + (i * 8UL));
180 schizo_write(line_base + (i * 8UL), 0UL); 163 upa_writeq(0UL, line_base + (i * 8UL));
181 } 164 }
182 165
183 /* OK, state is logged, exit diagnostic mode. */ 166 /* OK, state is logged, exit diagnostic mode. */
184 schizo_write(strbuf->strbuf_control, control); 167 upa_writeq(control, strbuf->strbuf_control);
185 168
186 for (i = 0; i < 16; i++) { 169 for (i = 0; i < 16; i++) {
187 int j, saw_error, first, last; 170 int j, saw_error, first, last;
@@ -258,14 +241,14 @@ static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
258 int i; 241 int i;
259 242
260 spin_lock_irqsave(&iommu->lock, flags); 243 spin_lock_irqsave(&iommu->lock, flags);
261 control = schizo_read(iommu->iommu_control); 244 control = upa_readq(iommu->iommu_control);
262 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { 245 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
263 unsigned long base; 246 unsigned long base;
264 char *type_string; 247 char *type_string;
265 248
266 /* Clear the error encountered bit. */ 249 /* Clear the error encountered bit. */
267 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; 250 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
268 schizo_write(iommu->iommu_control, control); 251 upa_writeq(control, iommu->iommu_control);
269 252
270 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { 253 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
271 case 0: 254 case 0:
@@ -295,24 +278,24 @@ static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
295 * get as much diagnostic information to the 278 * get as much diagnostic information to the
296 * console as we can. 279 * console as we can.
297 */ 280 */
298 schizo_write(iommu->iommu_control, 281 upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB,
299 control | SCHIZO_IOMMU_CTRL_DENAB); 282 iommu->iommu_control);
300 283
301 base = pbm->pbm_regs; 284 base = pbm->pbm_regs;
302 285
303 for (i = 0; i < 16; i++) { 286 for (i = 0; i < 16; i++) {
304 iommu_tag[i] = 287 iommu_tag[i] =
305 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL)); 288 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL));
306 iommu_data[i] = 289 iommu_data[i] =
307 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL)); 290 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL));
308 291
309 /* Now clear out the entry. */ 292 /* Now clear out the entry. */
310 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0); 293 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL));
311 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0); 294 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL));
312 } 295 }
313 296
314 /* Leave diagnostic mode. */ 297 /* Leave diagnostic mode. */
315 schizo_write(iommu->iommu_control, control); 298 upa_writeq(control, iommu->iommu_control);
316 299
317 for (i = 0; i < 16; i++) { 300 for (i = 0; i < 16; i++) {
318 unsigned long tag, data; 301 unsigned long tag, data;
@@ -357,11 +340,12 @@ static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
357 spin_unlock_irqrestore(&iommu->lock, flags); 340 spin_unlock_irqrestore(&iommu->lock, flags);
358} 341}
359 342
360static void schizo_check_iommu_error(struct pci_controller_info *p, 343static void schizo_check_iommu_error(struct pci_pbm_info *pbm,
361 enum schizo_error_type type) 344 enum schizo_error_type type)
362{ 345{
363 schizo_check_iommu_error_pbm(&p->pbm_A, type); 346 schizo_check_iommu_error_pbm(pbm, type);
364 schizo_check_iommu_error_pbm(&p->pbm_B, type); 347 if (pbm->sibling)
348 schizo_check_iommu_error_pbm(pbm->sibling, type);
365} 349}
366 350
367/* Uncorrectable ECC error status gathering. */ 351/* Uncorrectable ECC error status gathering. */
@@ -386,14 +370,13 @@ static void schizo_check_iommu_error(struct pci_controller_info *p,
386static irqreturn_t schizo_ue_intr(int irq, void *dev_id) 370static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
387{ 371{
388 struct pci_pbm_info *pbm = dev_id; 372 struct pci_pbm_info *pbm = dev_id;
389 struct pci_controller_info *p = pbm->parent;
390 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR; 373 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
391 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR; 374 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
392 unsigned long afsr, afar, error_bits; 375 unsigned long afsr, afar, error_bits;
393 int reported, limit; 376 int reported, limit;
394 377
395 /* Latch uncorrectable error status. */ 378 /* Latch uncorrectable error status. */
396 afar = schizo_read(afar_reg); 379 afar = upa_readq(afar_reg);
397 380
398 /* If either of the error pending bits are set in the 381 /* If either of the error pending bits are set in the
399 * AFSR, the error status is being actively updated by 382 * AFSR, the error status is being actively updated by
@@ -401,7 +384,7 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
401 */ 384 */
402 limit = 1000; 385 limit = 1000;
403 do { 386 do {
404 afsr = schizo_read(afsr_reg); 387 afsr = upa_readq(afsr_reg);
405 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 388 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
406 389
407 /* Clear the primary/secondary error status bits. */ 390 /* Clear the primary/secondary error status bits. */
@@ -410,7 +393,7 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
410 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); 393 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
411 if (!error_bits) 394 if (!error_bits)
412 return IRQ_NONE; 395 return IRQ_NONE;
413 schizo_write(afsr_reg, error_bits); 396 upa_writeq(error_bits, afsr_reg);
414 397
415 /* Log the error. */ 398 /* Log the error. */
416 printk("%s: Uncorrectable Error, primary error type[%s]\n", 399 printk("%s: Uncorrectable Error, primary error type[%s]\n",
@@ -449,7 +432,7 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
449 printk("]\n"); 432 printk("]\n");
450 433
451 /* Interrogate IOMMU for error status. */ 434 /* Interrogate IOMMU for error status. */
452 schizo_check_iommu_error(p, UE_ERR); 435 schizo_check_iommu_error(pbm, UE_ERR);
453 436
454 return IRQ_HANDLED; 437 return IRQ_HANDLED;
455} 438}
@@ -481,7 +464,7 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
481 int reported, limit; 464 int reported, limit;
482 465
483 /* Latch error status. */ 466 /* Latch error status. */
484 afar = schizo_read(afar_reg); 467 afar = upa_readq(afar_reg);
485 468
486 /* If either of the error pending bits are set in the 469 /* If either of the error pending bits are set in the
487 * AFSR, the error status is being actively updated by 470 * AFSR, the error status is being actively updated by
@@ -489,7 +472,7 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
489 */ 472 */
490 limit = 1000; 473 limit = 1000;
491 do { 474 do {
492 afsr = schizo_read(afsr_reg); 475 afsr = upa_readq(afsr_reg);
493 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 476 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
494 477
495 /* Clear primary/secondary error status bits. */ 478 /* Clear primary/secondary error status bits. */
@@ -498,7 +481,7 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
498 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); 481 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
499 if (!error_bits) 482 if (!error_bits)
500 return IRQ_NONE; 483 return IRQ_NONE;
501 schizo_write(afsr_reg, error_bits); 484 upa_writeq(error_bits, afsr_reg);
502 485
503 /* Log the error. */ 486 /* Log the error. */
504 printk("%s: Correctable Error, primary error type[%s]\n", 487 printk("%s: Correctable Error, primary error type[%s]\n",
@@ -600,7 +583,7 @@ static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
600 u16 stat; 583 u16 stat;
601 584
602 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; 585 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
603 csr = schizo_read(csr_reg); 586 csr = upa_readq(csr_reg);
604 csr_error_bits = 587 csr_error_bits =
605 csr & (SCHIZO_PCICTRL_BUS_UNUS | 588 csr & (SCHIZO_PCICTRL_BUS_UNUS |
606 SCHIZO_PCICTRL_TTO_ERR | 589 SCHIZO_PCICTRL_TTO_ERR |
@@ -610,7 +593,7 @@ static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
610 SCHIZO_PCICTRL_SERR); 593 SCHIZO_PCICTRL_SERR);
611 if (csr_error_bits) { 594 if (csr_error_bits) {
612 /* Clear the errors. */ 595 /* Clear the errors. */
613 schizo_write(csr_reg, csr); 596 upa_writeq(csr, csr_reg);
614 597
615 /* Log 'em. */ 598 /* Log 'em. */
616 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) 599 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
@@ -650,7 +633,6 @@ static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
650static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id) 633static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
651{ 634{
652 struct pci_pbm_info *pbm = dev_id; 635 struct pci_pbm_info *pbm = dev_id;
653 struct pci_controller_info *p = pbm->parent;
654 unsigned long afsr_reg, afar_reg, base; 636 unsigned long afsr_reg, afar_reg, base;
655 unsigned long afsr, afar, error_bits; 637 unsigned long afsr, afar, error_bits;
656 int reported; 638 int reported;
@@ -661,8 +643,8 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
661 afar_reg = base + SCHIZO_PCI_AFAR; 643 afar_reg = base + SCHIZO_PCI_AFAR;
662 644
663 /* Latch error status. */ 645 /* Latch error status. */
664 afar = schizo_read(afar_reg); 646 afar = upa_readq(afar_reg);
665 afsr = schizo_read(afsr_reg); 647 afsr = upa_readq(afsr_reg);
666 648
667 /* Clear primary/secondary error status bits. */ 649 /* Clear primary/secondary error status bits. */
668 error_bits = afsr & 650 error_bits = afsr &
@@ -674,7 +656,7 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
674 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); 656 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
675 if (!error_bits) 657 if (!error_bits)
676 return schizo_pcierr_intr_other(pbm); 658 return schizo_pcierr_intr_other(pbm);
677 schizo_write(afsr_reg, error_bits); 659 upa_writeq(error_bits, afsr_reg);
678 660
679 /* Log the error. */ 661 /* Log the error. */
680 printk("%s: PCI Error, primary error type[%s]\n", 662 printk("%s: PCI Error, primary error type[%s]\n",
@@ -744,7 +726,7 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
744 * a bug in the IOMMU support code or a PCI device driver. 726 * a bug in the IOMMU support code or a PCI device driver.
745 */ 727 */
746 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { 728 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
747 schizo_check_iommu_error(p, PCI_ERR); 729 schizo_check_iommu_error(pbm, PCI_ERR);
748 pci_scan_for_target_abort(pbm, pbm->pci_bus); 730 pci_scan_for_target_abort(pbm, pbm->pci_bus);
749 } 731 }
750 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) 732 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
@@ -805,12 +787,11 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
805static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id) 787static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
806{ 788{
807 struct pci_pbm_info *pbm = dev_id; 789 struct pci_pbm_info *pbm = dev_id;
808 struct pci_controller_info *p = pbm->parent;
809 u64 errlog; 790 u64 errlog;
810 791
811 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 792 errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
812 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG, 793 upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT),
813 errlog & ~(SAFARI_ERRLOG_ERROUT)); 794 pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
814 795
815 if (!(errlog & BUS_ERROR_UNMAP)) { 796 if (!(errlog & BUS_ERROR_UNMAP)) {
816 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n", 797 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
@@ -821,7 +802,7 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
821 802
822 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", 803 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
823 pbm->name); 804 pbm->name);
824 schizo_check_iommu_error(p, SAFARI_ERR); 805 schizo_check_iommu_error(pbm, SAFARI_ERR);
825 806
826 return IRQ_HANDLED; 807 return IRQ_HANDLED;
827} 808}
@@ -863,7 +844,7 @@ static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
863 */ 844 */
864static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm) 845static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
865{ 846{
866 struct of_device *op = of_find_device_by_node(pbm->prom_node); 847 struct of_device *op = of_find_device_by_node(pbm->op->node);
867 u64 tmp, err_mask, err_no_mask; 848 u64 tmp, err_mask, err_no_mask;
868 int err; 849 int err;
869 850
@@ -910,10 +891,9 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
910 } 891 }
911 892
912 /* Enable UE and CE interrupts for controller. */ 893 /* Enable UE and CE interrupts for controller. */
913 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL, 894 upa_writeq((SCHIZO_ECCCTRL_EE |
914 (SCHIZO_ECCCTRL_EE | 895 SCHIZO_ECCCTRL_UE |
915 SCHIZO_ECCCTRL_UE | 896 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
916 SCHIZO_ECCCTRL_CE));
917 897
918 /* Enable PCI Error interrupts and clear error 898 /* Enable PCI Error interrupts and clear error
919 * bits. 899 * bits.
@@ -926,10 +906,10 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
926 906
927 err_no_mask = SCHIZO_PCICTRL_DTO_ERR; 907 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
928 908
929 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); 909 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
930 tmp |= err_mask; 910 tmp |= err_mask;
931 tmp &= ~err_no_mask; 911 tmp &= ~err_no_mask;
932 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); 912 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
933 913
934 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 914 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
935 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 915 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
@@ -938,7 +918,7 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
938 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 918 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
939 SCHIZO_PCIAFSR_STTO); 919 SCHIZO_PCIAFSR_STTO);
940 920
941 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask); 921 upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR);
942 922
943 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | 923 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
944 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | 924 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
@@ -950,16 +930,16 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
950 BUS_ERROR_APERR | BUS_ERROR_UNMAP | 930 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
951 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); 931 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
952 932
953 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL, 933 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
954 (SCHIZO_SAFERRCTRL_EN | err_mask)); 934 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
955 935
956 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL, 936 upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)),
957 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); 937 pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL);
958} 938}
959 939
960static void schizo_register_error_handlers(struct pci_pbm_info *pbm) 940static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
961{ 941{
962 struct of_device *op = of_find_device_by_node(pbm->prom_node); 942 struct of_device *op = of_find_device_by_node(pbm->op->node);
963 u64 tmp, err_mask, err_no_mask; 943 u64 tmp, err_mask, err_no_mask;
964 int err; 944 int err;
965 945
@@ -1006,10 +986,9 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1006 } 986 }
1007 987
1008 /* Enable UE and CE interrupts for controller. */ 988 /* Enable UE and CE interrupts for controller. */
1009 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL, 989 upa_writeq((SCHIZO_ECCCTRL_EE |
1010 (SCHIZO_ECCCTRL_EE | 990 SCHIZO_ECCCTRL_UE |
1011 SCHIZO_ECCCTRL_UE | 991 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
1012 SCHIZO_ECCCTRL_CE));
1013 992
1014 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 993 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1015 SCHIZO_PCICTRL_ESLCK | 994 SCHIZO_PCICTRL_ESLCK |
@@ -1025,18 +1004,18 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1025 /* Enable PCI Error interrupts and clear error 1004 /* Enable PCI Error interrupts and clear error
1026 * bits for each PBM. 1005 * bits for each PBM.
1027 */ 1006 */
1028 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1007 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1029 tmp |= err_mask; 1008 tmp |= err_mask;
1030 tmp &= ~err_no_mask; 1009 tmp &= ~err_no_mask;
1031 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); 1010 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1032 1011
1033 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, 1012 upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1034 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1013 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1035 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1014 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1036 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 1015 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1037 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 1016 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1038 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 1017 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS),
1039 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS)); 1018 pbm->pbm_regs + SCHIZO_PCI_AFSR);
1040 1019
1041 /* Make all Safari error conditions fatal except unmapped 1020 /* Make all Safari error conditions fatal except unmapped
1042 * errors which we make generate interrupts. 1021 * errors which we make generate interrupts.
@@ -1063,8 +1042,8 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1063 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); 1042 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1064#endif 1043#endif
1065 1044
1066 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL, 1045 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
1067 (SCHIZO_SAFERRCTRL_EN | err_mask)); 1046 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
1068} 1047}
1069 1048
1070static void pbm_config_busmastering(struct pci_pbm_info *pbm) 1049static void pbm_config_busmastering(struct pci_pbm_info *pbm)
@@ -1084,14 +1063,15 @@ static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1084 pci_config_write8(addr, 64); 1063 pci_config_write8(addr, 64);
1085} 1064}
1086 1065
1087static void __init schizo_scan_bus(struct pci_pbm_info *pbm) 1066static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm,
1067 struct device *parent)
1088{ 1068{
1089 pbm_config_busmastering(pbm); 1069 pbm_config_busmastering(pbm);
1090 pbm->is_66mhz_capable = 1070 pbm->is_66mhz_capable =
1091 (of_find_property(pbm->prom_node, "66mhz-capable", NULL) 1071 (of_find_property(pbm->op->node, "66mhz-capable", NULL)
1092 != NULL); 1072 != NULL);
1093 1073
1094 pbm->pci_bus = pci_scan_one_pbm(pbm); 1074 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1095 1075
1096 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1076 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1097 tomatillo_register_error_handlers(pbm); 1077 tomatillo_register_error_handlers(pbm);
@@ -1133,12 +1113,12 @@ static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1133 * streaming buffer and leave the rerun-disable 1113 * streaming buffer and leave the rerun-disable
1134 * setting however OBP set it. 1114 * setting however OBP set it.
1135 */ 1115 */
1136 control = schizo_read(pbm->stc.strbuf_control); 1116 control = upa_readq(pbm->stc.strbuf_control);
1137 control &= ~(SCHIZO_STRBUF_CTRL_LPTR | 1117 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1138 SCHIZO_STRBUF_CTRL_LENAB | 1118 SCHIZO_STRBUF_CTRL_LENAB |
1139 SCHIZO_STRBUF_CTRL_DENAB); 1119 SCHIZO_STRBUF_CTRL_DENAB);
1140 control |= SCHIZO_STRBUF_CTRL_ENAB; 1120 control |= SCHIZO_STRBUF_CTRL_ENAB;
1141 schizo_write(pbm->stc.strbuf_control, control); 1121 upa_writeq(control, pbm->stc.strbuf_control);
1142 1122
1143 pbm->stc.strbuf_enabled = 1; 1123 pbm->stc.strbuf_enabled = 1;
1144} 1124}
@@ -1150,24 +1130,17 @@ static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1150 1130
1151static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm) 1131static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1152{ 1132{
1153 struct iommu *iommu = pbm->iommu; 1133 static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
1154 unsigned long i, tagbase, database; 1134 unsigned long i, tagbase, database;
1155 struct property *prop; 1135 struct iommu *iommu = pbm->iommu;
1156 u32 vdma[2], dma_mask;
1157 int tsbsize, err; 1136 int tsbsize, err;
1137 const u32 *vdma;
1138 u32 dma_mask;
1158 u64 control; 1139 u64 control;
1159 1140
1160 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL); 1141 vdma = of_get_property(pbm->op->node, "virtual-dma", NULL);
1161 if (prop) { 1142 if (!vdma)
1162 u32 *val = prop->value; 1143 vdma = vdma_default;
1163
1164 vdma[0] = val[0];
1165 vdma[1] = val[1];
1166 } else {
1167 /* No property, use default values. */
1168 vdma[0] = 0xc0000000;
1169 vdma[1] = 0x40000000;
1170 }
1171 1144
1172 dma_mask = vdma[0]; 1145 dma_mask = vdma[0];
1173 switch (vdma[1]) { 1146 switch (vdma[1]) {
@@ -1187,9 +1160,9 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1187 break; 1160 break;
1188 1161
1189 default: 1162 default:
1190 prom_printf("SCHIZO: strange virtual-dma size.\n"); 1163 printk(KERN_ERR PFX "Strange virtual-dma size.\n");
1191 prom_halt(); 1164 return -EINVAL;
1192 }; 1165 }
1193 1166
1194 /* Register addresses, SCHIZO has iommu ctx flushing. */ 1167 /* Register addresses, SCHIZO has iommu ctx flushing. */
1195 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; 1168 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
@@ -1206,15 +1179,15 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1206 /* 1179 /*
1207 * Invalidate TLB Entries. 1180 * Invalidate TLB Entries.
1208 */ 1181 */
1209 control = schizo_read(iommu->iommu_control); 1182 control = upa_readq(iommu->iommu_control);
1210 control |= SCHIZO_IOMMU_CTRL_DENAB; 1183 control |= SCHIZO_IOMMU_CTRL_DENAB;
1211 schizo_write(iommu->iommu_control, control); 1184 upa_writeq(control, iommu->iommu_control);
1212 1185
1213 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; 1186 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1214 1187
1215 for(i = 0; i < 16; i++) { 1188 for (i = 0; i < 16; i++) {
1216 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0); 1189 upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL));
1217 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0); 1190 upa_writeq(0, pbm->pbm_regs + database + (i * 8UL));
1218 } 1191 }
1219 1192
1220 /* Leave diag mode enabled for full-flushing done 1193 /* Leave diag mode enabled for full-flushing done
@@ -1222,12 +1195,14 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1222 */ 1195 */
1223 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, 1196 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1224 pbm->numa_node); 1197 pbm->numa_node);
1225 if (err) 1198 if (err) {
1199 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
1226 return err; 1200 return err;
1201 }
1227 1202
1228 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table)); 1203 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
1229 1204
1230 control = schizo_read(iommu->iommu_control); 1205 control = upa_readq(iommu->iommu_control);
1231 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); 1206 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1232 switch (tsbsize) { 1207 switch (tsbsize) {
1233 case 64: 1208 case 64:
@@ -1236,10 +1211,10 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1236 case 128: 1211 case 128:
1237 control |= SCHIZO_IOMMU_TSBSZ_128K; 1212 control |= SCHIZO_IOMMU_TSBSZ_128K;
1238 break; 1213 break;
1239 }; 1214 }
1240 1215
1241 control |= SCHIZO_IOMMU_CTRL_ENAB; 1216 control |= SCHIZO_IOMMU_CTRL_ENAB;
1242 schizo_write(iommu->iommu_control, control); 1217 upa_writeq(control, iommu->iommu_control);
1243 1218
1244 return 0; 1219 return 0;
1245} 1220}
@@ -1280,12 +1255,11 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1280 1255
1281static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) 1256static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1282{ 1257{
1283 struct property *prop;
1284 u64 tmp; 1258 u64 tmp;
1285 1259
1286 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5); 1260 upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY);
1287 1261
1288 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1262 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1289 1263
1290 /* Enable arbiter for all PCI slots. */ 1264 /* Enable arbiter for all PCI slots. */
1291 tmp |= 0xff; 1265 tmp |= 0xff;
@@ -1294,8 +1268,7 @@ static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1294 pbm->chip_version >= 0x2) 1268 pbm->chip_version >= 0x2)
1295 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; 1269 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1296 1270
1297 prop = of_find_property(pbm->prom_node, "no-bus-parking", NULL); 1271 if (!of_find_property(pbm->op->node, "no-bus-parking", NULL))
1298 if (!prop)
1299 tmp |= SCHIZO_PCICTRL_PARK; 1272 tmp |= SCHIZO_PCICTRL_PARK;
1300 else 1273 else
1301 tmp &= ~SCHIZO_PCICTRL_PARK; 1274 tmp &= ~SCHIZO_PCICTRL_PARK;
@@ -1311,13 +1284,13 @@ static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1311 SCHIZO_PCICTRL_RDO_PREF | 1284 SCHIZO_PCICTRL_RDO_PREF |
1312 SCHIZO_PCICTRL_RDL_PREF); 1285 SCHIZO_PCICTRL_RDL_PREF);
1313 1286
1314 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); 1287 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1315 1288
1316 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG); 1289 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1317 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | 1290 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1318 SCHIZO_PCIDIAG_D_RETRY | 1291 SCHIZO_PCIDIAG_D_RETRY |
1319 SCHIZO_PCIDIAG_D_INTSYNC); 1292 SCHIZO_PCIDIAG_D_INTSYNC);
1320 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp); 1293 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG);
1321 1294
1322 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1295 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1323 /* Clear prefetch lengths to workaround a bug in 1296 /* Clear prefetch lengths to workaround a bug in
@@ -1329,17 +1302,16 @@ static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1329 TOMATILLO_IOC_RDONE_CPENAB | 1302 TOMATILLO_IOC_RDONE_CPENAB |
1330 TOMATILLO_IOC_RDLINE_CPENAB); 1303 TOMATILLO_IOC_RDLINE_CPENAB);
1331 1304
1332 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR, 1305 upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR);
1333 tmp);
1334 } 1306 }
1335} 1307}
1336 1308
1337static int __init schizo_pbm_init(struct pci_controller_info *p, 1309static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm,
1338 struct device_node *dp, u32 portid, 1310 struct of_device *op, u32 portid,
1339 int chip_type) 1311 int chip_type)
1340{ 1312{
1341 const struct linux_prom64_registers *regs; 1313 const struct linux_prom64_registers *regs;
1342 struct pci_pbm_info *pbm; 1314 struct device_node *dp = op->node;
1343 const char *chipset_name; 1315 const char *chipset_name;
1344 int is_pbm_a, err; 1316 int is_pbm_a, err;
1345 1317
@@ -1372,25 +1344,19 @@ static int __init schizo_pbm_init(struct pci_controller_info *p,
1372 regs = of_get_property(dp, "reg", NULL); 1344 regs = of_get_property(dp, "reg", NULL);
1373 1345
1374 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000); 1346 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000);
1375 if (is_pbm_a)
1376 pbm = &p->pbm_A;
1377 else
1378 pbm = &p->pbm_B;
1379 1347
1380 pbm->next = pci_pbm_root; 1348 pbm->next = pci_pbm_root;
1381 pci_pbm_root = pbm; 1349 pci_pbm_root = pbm;
1382 1350
1383 pbm->numa_node = -1; 1351 pbm->numa_node = -1;
1384 1352
1385 pbm->scan_bus = schizo_scan_bus;
1386 pbm->pci_ops = &sun4u_pci_ops; 1353 pbm->pci_ops = &sun4u_pci_ops;
1387 pbm->config_space_reg_bits = 8; 1354 pbm->config_space_reg_bits = 8;
1388 1355
1389 pbm->index = pci_num_pbms++; 1356 pbm->index = pci_num_pbms++;
1390 1357
1391 pbm->portid = portid; 1358 pbm->portid = portid;
1392 pbm->parent = p; 1359 pbm->op = op;
1393 pbm->prom_node = dp;
1394 1360
1395 pbm->chip_type = chip_type; 1361 pbm->chip_type = chip_type;
1396 pbm->chip_version = of_getintprop_default(dp, "version#", 0); 1362 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
@@ -1420,6 +1386,8 @@ static int __init schizo_pbm_init(struct pci_controller_info *p,
1420 1386
1421 schizo_pbm_strbuf_init(pbm); 1387 schizo_pbm_strbuf_init(pbm);
1422 1388
1389 schizo_scan_bus(pbm, &op->dev);
1390
1423 return 0; 1391 return 0;
1424} 1392}
1425 1393
@@ -1433,62 +1401,104 @@ static inline int portid_compare(u32 x, u32 y, int chip_type)
1433 return (x == y); 1401 return (x == y);
1434} 1402}
1435 1403
1436static void __init __schizo_init(struct device_node *dp, char *model_name, 1404static struct pci_pbm_info * __devinit schizo_find_sibling(u32 portid,
1437 int chip_type) 1405 int chip_type)
1438{ 1406{
1439 struct pci_controller_info *p; 1407 struct pci_pbm_info *pbm;
1408
1409 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1410 if (portid_compare(pbm->portid, portid, chip_type))
1411 return pbm;
1412 }
1413 return NULL;
1414}
1415
1416static int __devinit __schizo_init(struct of_device *op, unsigned long chip_type)
1417{
1418 struct device_node *dp = op->node;
1440 struct pci_pbm_info *pbm; 1419 struct pci_pbm_info *pbm;
1441 struct iommu *iommu; 1420 struct iommu *iommu;
1442 u32 portid; 1421 u32 portid;
1422 int err;
1443 1423
1444 portid = of_getintprop_default(dp, "portid", 0xff); 1424 portid = of_getintprop_default(dp, "portid", 0xff);
1445 1425
1446 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 1426 err = -ENOMEM;
1447 if (portid_compare(pbm->portid, portid, chip_type)) { 1427 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1448 if (schizo_pbm_init(pbm->parent, dp, 1428 if (!pbm) {
1449 portid, chip_type)) 1429 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
1450 goto fatal_memory_error; 1430 goto out_err;
1451 return; 1431 }
1452 } 1432
1433 pbm->sibling = schizo_find_sibling(portid, chip_type);
1434
1435 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1436 if (!iommu) {
1437 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
1438 goto out_free_pbm;
1453 } 1439 }
1454 1440
1455 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); 1441 pbm->iommu = iommu;
1456 if (!p)
1457 goto fatal_memory_error;
1458 1442
1459 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); 1443 if (schizo_pbm_init(pbm, op, portid, chip_type))
1460 if (!iommu) 1444 goto out_free_iommu;
1461 goto fatal_memory_error;
1462 1445
1463 p->pbm_A.iommu = iommu; 1446 if (pbm->sibling)
1447 pbm->sibling->sibling = pbm;
1464 1448
1465 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); 1449 dev_set_drvdata(&op->dev, pbm);
1466 if (!iommu)
1467 goto fatal_memory_error;
1468 1450
1469 p->pbm_B.iommu = iommu; 1451 return 0;
1470 1452
1471 if (schizo_pbm_init(p, dp, portid, chip_type)) 1453out_free_iommu:
1472 goto fatal_memory_error; 1454 kfree(pbm->iommu);
1473 1455
1474 return; 1456out_free_pbm:
1457 kfree(pbm);
1475 1458
1476fatal_memory_error: 1459out_err:
1477 prom_printf("SCHIZO: Fatal memory allocation error.\n"); 1460 return err;
1478 prom_halt();
1479} 1461}
1480 1462
1481void __init schizo_init(struct device_node *dp, char *model_name) 1463static int __devinit schizo_probe(struct of_device *op,
1464 const struct of_device_id *match)
1482{ 1465{
1483 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO); 1466 return __schizo_init(op, (unsigned long) match->data);
1484} 1467}
1485 1468
1486void __init schizo_plus_init(struct device_node *dp, char *model_name) 1469/* The ordering of this table is very important. Some Tomatillo
1487{ 1470 * nodes announce that they are compatible with both pci108e,a801
1488 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS); 1471 * and pci108e,8001. So list the chips in reverse chronological
1489} 1472 * order.
1473 */
1474static struct of_device_id __initdata schizo_match[] = {
1475 {
1476 .name = "pci",
1477 .compatible = "pci108e,a801",
1478 .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
1479 },
1480 {
1481 .name = "pci",
1482 .compatible = "pci108e,8002",
1483 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
1484 },
1485 {
1486 .name = "pci",
1487 .compatible = "pci108e,8001",
1488 .data = (void *) PBM_CHIP_TYPE_SCHIZO,
1489 },
1490 {},
1491};
1490 1492
1491void __init tomatillo_init(struct device_node *dp, char *model_name) 1493static struct of_platform_driver schizo_driver = {
1494 .name = DRIVER_NAME,
1495 .match_table = schizo_match,
1496 .probe = schizo_probe,
1497};
1498
1499static int __init schizo_init(void)
1492{ 1500{
1493 __schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO); 1501 return of_register_driver(&schizo_driver, &of_bus_type);
1494} 1502}
1503
1504subsys_initcall(schizo_init);
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index a104c80d319..e86c73ec167 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -13,12 +13,10 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/msi.h> 14#include <linux/msi.h>
15#include <linux/log2.h> 15#include <linux/log2.h>
16#include <linux/of_device.h>
16 17
17#include <asm/iommu.h> 18#include <asm/iommu.h>
18#include <asm/irq.h> 19#include <asm/irq.h>
19#include <asm/upa.h>
20#include <asm/pstate.h>
21#include <asm/oplib.h>
22#include <asm/hypervisor.h> 20#include <asm/hypervisor.h>
23#include <asm/prom.h> 21#include <asm/prom.h>
24 22
@@ -27,6 +25,9 @@
27 25
28#include "pci_sun4v.h" 26#include "pci_sun4v.h"
29 27
28#define DRIVER_NAME "pci_sun4v"
29#define PFX DRIVER_NAME ": "
30
30static unsigned long vpci_major = 1; 31static unsigned long vpci_major = 1;
31static unsigned long vpci_minor = 1; 32static unsigned long vpci_minor = 1;
32 33
@@ -41,6 +42,7 @@ struct iommu_batch {
41}; 42};
42 43
43static DEFINE_PER_CPU(struct iommu_batch, iommu_batch); 44static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
45static int iommu_batch_initialized;
44 46
45/* Interrupts must be disabled. */ 47/* Interrupts must be disabled. */
46static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry) 48static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
@@ -542,15 +544,16 @@ static const struct dma_ops sun4v_dma_ops = {
542 .sync_sg_for_cpu = dma_4v_sync_sg_for_cpu, 544 .sync_sg_for_cpu = dma_4v_sync_sg_for_cpu,
543}; 545};
544 546
545static void __init pci_sun4v_scan_bus(struct pci_pbm_info *pbm) 547static void __init pci_sun4v_scan_bus(struct pci_pbm_info *pbm,
548 struct device *parent)
546{ 549{
547 struct property *prop; 550 struct property *prop;
548 struct device_node *dp; 551 struct device_node *dp;
549 552
550 dp = pbm->prom_node; 553 dp = pbm->op->node;
551 prop = of_find_property(dp, "66mhz-capable", NULL); 554 prop = of_find_property(dp, "66mhz-capable", NULL);
552 pbm->is_66mhz_capable = (prop != NULL); 555 pbm->is_66mhz_capable = (prop != NULL);
553 pbm->pci_bus = pci_scan_one_pbm(pbm); 556 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
554 557
555 /* XXX register error interrupt handlers XXX */ 558 /* XXX register error interrupt handlers XXX */
556} 559}
@@ -583,29 +586,22 @@ static unsigned long __init probe_existing_entries(struct pci_pbm_info *pbm,
583 return cnt; 586 return cnt;
584} 587}
585 588
586static void __init pci_sun4v_iommu_init(struct pci_pbm_info *pbm) 589static int __init pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
587{ 590{
591 static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
588 struct iommu *iommu = pbm->iommu; 592 struct iommu *iommu = pbm->iommu;
589 struct property *prop;
590 unsigned long num_tsb_entries, sz, tsbsize; 593 unsigned long num_tsb_entries, sz, tsbsize;
591 u32 vdma[2], dma_mask, dma_offset; 594 u32 dma_mask, dma_offset;
592 595 const u32 *vdma;
593 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL); 596
594 if (prop) { 597 vdma = of_get_property(pbm->op->node, "virtual-dma", NULL);
595 u32 *val = prop->value; 598 if (!vdma)
596 599 vdma = vdma_default;
597 vdma[0] = val[0];
598 vdma[1] = val[1];
599 } else {
600 /* No property, use default values. */
601 vdma[0] = 0x80000000;
602 vdma[1] = 0x80000000;
603 }
604 600
605 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) { 601 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
606 prom_printf("PCI-SUN4V: strange virtual-dma[%08x:%08x].\n", 602 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
607 vdma[0], vdma[1]); 603 vdma[0], vdma[1]);
608 prom_halt(); 604 return -EINVAL;
609 }; 605 };
610 606
611 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL); 607 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
@@ -625,8 +621,8 @@ static void __init pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
625 sz = (sz + 7UL) & ~7UL; 621 sz = (sz + 7UL) & ~7UL;
626 iommu->arena.map = kzalloc(sz, GFP_KERNEL); 622 iommu->arena.map = kzalloc(sz, GFP_KERNEL);
627 if (!iommu->arena.map) { 623 if (!iommu->arena.map) {
628 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n"); 624 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
629 prom_halt(); 625 return -ENOMEM;
630 } 626 }
631 iommu->arena.limit = num_tsb_entries; 627 iommu->arena.limit = num_tsb_entries;
632 628
@@ -634,6 +630,8 @@ static void __init pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
634 if (sz) 630 if (sz)
635 printk("%s: Imported %lu TSB entries from OBP\n", 631 printk("%s: Imported %lu TSB entries from OBP\n",
636 pbm->name, sz); 632 pbm->name, sz);
633
634 return 0;
637} 635}
638 636
639#ifdef CONFIG_PCI_MSI 637#ifdef CONFIG_PCI_MSI
@@ -890,29 +888,20 @@ static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
890} 888}
891#endif /* !(CONFIG_PCI_MSI) */ 889#endif /* !(CONFIG_PCI_MSI) */
892 890
893static void __init pci_sun4v_pbm_init(struct pci_controller_info *p, 891static int __init pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
894 struct device_node *dp, u32 devhandle) 892 struct of_device *op, u32 devhandle)
895{ 893{
896 struct pci_pbm_info *pbm; 894 struct device_node *dp = op->node;
897 895 int err;
898 if (devhandle & 0x40)
899 pbm = &p->pbm_B;
900 else
901 pbm = &p->pbm_A;
902
903 pbm->next = pci_pbm_root;
904 pci_pbm_root = pbm;
905 896
906 pbm->numa_node = of_node_to_nid(dp); 897 pbm->numa_node = of_node_to_nid(dp);
907 898
908 pbm->scan_bus = pci_sun4v_scan_bus;
909 pbm->pci_ops = &sun4v_pci_ops; 899 pbm->pci_ops = &sun4v_pci_ops;
910 pbm->config_space_reg_bits = 12; 900 pbm->config_space_reg_bits = 12;
911 901
912 pbm->index = pci_num_pbms++; 902 pbm->index = pci_num_pbms++;
913 903
914 pbm->parent = p; 904 pbm->op = op;
915 pbm->prom_node = dp;
916 905
917 pbm->devhandle = devhandle; 906 pbm->devhandle = devhandle;
918 907
@@ -924,82 +913,120 @@ static void __init pci_sun4v_pbm_init(struct pci_controller_info *p,
924 pci_determine_mem_io_space(pbm); 913 pci_determine_mem_io_space(pbm);
925 914
926 pci_get_pbm_props(pbm); 915 pci_get_pbm_props(pbm);
927 pci_sun4v_iommu_init(pbm); 916
917 err = pci_sun4v_iommu_init(pbm);
918 if (err)
919 return err;
920
928 pci_sun4v_msi_init(pbm); 921 pci_sun4v_msi_init(pbm);
922
923 pci_sun4v_scan_bus(pbm, &op->dev);
924
925 pbm->next = pci_pbm_root;
926 pci_pbm_root = pbm;
927
928 return 0;
929} 929}
930 930
931void __init sun4v_pci_init(struct device_node *dp, char *model_name) 931static int __devinit pci_sun4v_probe(struct of_device *op,
932 const struct of_device_id *match)
932{ 933{
934 const struct linux_prom64_registers *regs;
933 static int hvapi_negotiated = 0; 935 static int hvapi_negotiated = 0;
934 struct pci_controller_info *p;
935 struct pci_pbm_info *pbm; 936 struct pci_pbm_info *pbm;
937 struct device_node *dp;
936 struct iommu *iommu; 938 struct iommu *iommu;
937 struct property *prop;
938 struct linux_prom64_registers *regs;
939 u32 devhandle; 939 u32 devhandle;
940 int i; 940 int i, err;
941
942 dp = op->node;
941 943
942 if (!hvapi_negotiated++) { 944 if (!hvapi_negotiated++) {
943 int err = sun4v_hvapi_register(HV_GRP_PCI, 945 err = sun4v_hvapi_register(HV_GRP_PCI,
944 vpci_major, 946 vpci_major,
945 &vpci_minor); 947 &vpci_minor);
946 948
947 if (err) { 949 if (err) {
948 prom_printf("SUN4V_PCI: Could not register hvapi, " 950 printk(KERN_ERR PFX "Could not register hvapi, "
949 "err=%d\n", err); 951 "err=%d\n", err);
950 prom_halt(); 952 return err;
951 } 953 }
952 printk("SUN4V_PCI: Registered hvapi major[%lu] minor[%lu]\n", 954 printk(KERN_INFO PFX "Registered hvapi major[%lu] minor[%lu]\n",
953 vpci_major, vpci_minor); 955 vpci_major, vpci_minor);
954 956
955 dma_ops = &sun4v_dma_ops; 957 dma_ops = &sun4v_dma_ops;
956 } 958 }
957 959
958 prop = of_find_property(dp, "reg", NULL); 960 regs = of_get_property(dp, "reg", NULL);
959 if (!prop) { 961 err = -ENODEV;
960 prom_printf("SUN4V_PCI: Could not find config registers\n"); 962 if (!regs) {
961 prom_halt(); 963 printk(KERN_ERR PFX "Could not find config registers\n");
964 goto out_err;
962 } 965 }
963 regs = prop->value;
964
965 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff; 966 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
966 967
967 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 968 err = -ENOMEM;
968 if (pbm->devhandle == (devhandle ^ 0x40)) { 969 if (!iommu_batch_initialized) {
969 pci_sun4v_pbm_init(pbm->parent, dp, devhandle); 970 for_each_possible_cpu(i) {
970 return; 971 unsigned long page = get_zeroed_page(GFP_KERNEL);
972
973 if (!page)
974 goto out_err;
975
976 per_cpu(iommu_batch, i).pglist = (u64 *) page;
971 } 977 }
978 iommu_batch_initialized = 1;
972 } 979 }
973 980
974 for_each_possible_cpu(i) { 981 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
975 unsigned long page = get_zeroed_page(GFP_ATOMIC); 982 if (!pbm) {
976 983 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
977 if (!page) 984 goto out_err;
978 goto fatal_memory_error; 985 }
979 986
980 per_cpu(iommu_batch, i).pglist = (u64 *) page; 987 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
988 if (!iommu) {
989 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
990 goto out_free_controller;
981 } 991 }
982 992
983 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); 993 pbm->iommu = iommu;
984 if (!p)
985 goto fatal_memory_error;
986 994
987 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); 995 err = pci_sun4v_pbm_init(pbm, op, devhandle);
988 if (!iommu) 996 if (err)
989 goto fatal_memory_error; 997 goto out_free_iommu;
998
999 dev_set_drvdata(&op->dev, pbm);
1000
1001 return 0;
1002
1003out_free_iommu:
1004 kfree(pbm->iommu);
990 1005
991 p->pbm_A.iommu = iommu; 1006out_free_controller:
1007 kfree(pbm);
992 1008
993 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); 1009out_err:
994 if (!iommu) 1010 return err;
995 goto fatal_memory_error; 1011}
996 1012
997 p->pbm_B.iommu = iommu; 1013static struct of_device_id __initdata pci_sun4v_match[] = {
1014 {
1015 .name = "pci",
1016 .compatible = "SUNW,sun4v-pci",
1017 },
1018 {},
1019};
998 1020
999 pci_sun4v_pbm_init(p, dp, devhandle); 1021static struct of_platform_driver pci_sun4v_driver = {
1000 return; 1022 .name = DRIVER_NAME,
1023 .match_table = pci_sun4v_match,
1024 .probe = pci_sun4v_probe,
1025};
1001 1026
1002fatal_memory_error: 1027static int __init pci_sun4v_init(void)
1003 prom_printf("SUN4V_PCI: Fatal memory allocation error.\n"); 1028{
1004 prom_halt(); 1029 return of_register_driver(&pci_sun4v_driver, &of_bus_type);
1005} 1030}
1031
1032subsys_initcall(pci_sun4v_init);
diff --git a/arch/sparc64/kernel/pci_sun4v_asm.S b/arch/sparc64/kernel/pci_sun4v_asm.S
index ecb81f389b0..e606d46c681 100644
--- a/arch/sparc64/kernel/pci_sun4v_asm.S
+++ b/arch/sparc64/kernel/pci_sun4v_asm.S
@@ -1,8 +1,9 @@
1/* pci_sun4v_asm: Hypervisor calls for PCI support. 1/* pci_sun4v_asm: Hypervisor calls for PCI support.
2 * 2 *
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net> 3 * Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net>
4 */ 4 */
5 5
6#include <linux/linkage.h>
6#include <asm/hypervisor.h> 7#include <asm/hypervisor.h>
7 8
8 /* %o0: devhandle 9 /* %o0: devhandle
@@ -14,8 +15,7 @@
14 * returns %o0: -status if status was non-zero, else 15 * returns %o0: -status if status was non-zero, else
15 * %o0: num pages mapped 16 * %o0: num pages mapped
16 */ 17 */
17 .globl pci_sun4v_iommu_map 18ENTRY(pci_sun4v_iommu_map)
18pci_sun4v_iommu_map:
19 mov %o5, %g1 19 mov %o5, %g1
20 mov HV_FAST_PCI_IOMMU_MAP, %o5 20 mov HV_FAST_PCI_IOMMU_MAP, %o5
21 ta HV_FAST_TRAP 21 ta HV_FAST_TRAP
@@ -24,6 +24,7 @@ pci_sun4v_iommu_map:
24 mov %o1, %o0 24 mov %o1, %o0
251: retl 251: retl
26 nop 26 nop
27ENDPROC(pci_sun4v_iommu_map)
27 28
28 /* %o0: devhandle 29 /* %o0: devhandle
29 * %o1: tsbid 30 * %o1: tsbid
@@ -31,12 +32,12 @@ pci_sun4v_iommu_map:
31 * 32 *
32 * returns %o0: num ttes demapped 33 * returns %o0: num ttes demapped
33 */ 34 */
34 .globl pci_sun4v_iommu_demap 35ENTRY(pci_sun4v_iommu_demap)
35pci_sun4v_iommu_demap:
36 mov HV_FAST_PCI_IOMMU_DEMAP, %o5 36 mov HV_FAST_PCI_IOMMU_DEMAP, %o5
37 ta HV_FAST_TRAP 37 ta HV_FAST_TRAP
38 retl 38 retl
39 mov %o1, %o0 39 mov %o1, %o0
40ENDPROC(pci_sun4v_iommu_demap)
40 41
41 /* %o0: devhandle 42 /* %o0: devhandle
42 * %o1: tsbid 43 * %o1: tsbid
@@ -45,8 +46,7 @@ pci_sun4v_iommu_demap:
45 * 46 *
46 * returns %o0: status 47 * returns %o0: status
47 */ 48 */
48 .globl pci_sun4v_iommu_getmap 49ENTRY(pci_sun4v_iommu_getmap)
49pci_sun4v_iommu_getmap:
50 mov %o2, %o4 50 mov %o2, %o4
51 mov HV_FAST_PCI_IOMMU_GETMAP, %o5 51 mov HV_FAST_PCI_IOMMU_GETMAP, %o5
52 ta HV_FAST_TRAP 52 ta HV_FAST_TRAP
@@ -54,6 +54,7 @@ pci_sun4v_iommu_getmap:
54 stx %o2, [%o3] 54 stx %o2, [%o3]
55 retl 55 retl
56 mov %o0, %o0 56 mov %o0, %o0
57ENDPROC(pci_sun4v_iommu_getmap)
57 58
58 /* %o0: devhandle 59 /* %o0: devhandle
59 * %o1: pci_device 60 * %o1: pci_device
@@ -65,14 +66,14 @@ pci_sun4v_iommu_getmap:
65 * If there is an error, the data will be returned 66 * If there is an error, the data will be returned
66 * as all 1's. 67 * as all 1's.
67 */ 68 */
68 .globl pci_sun4v_config_get 69ENTRY(pci_sun4v_config_get)
69pci_sun4v_config_get:
70 mov HV_FAST_PCI_CONFIG_GET, %o5 70 mov HV_FAST_PCI_CONFIG_GET, %o5
71 ta HV_FAST_TRAP 71 ta HV_FAST_TRAP
72 brnz,a,pn %o1, 1f 72 brnz,a,pn %o1, 1f
73 mov -1, %o2 73 mov -1, %o2
741: retl 741: retl
75 mov %o2, %o0 75 mov %o2, %o0
76ENDPROC(pci_sun4v_config_get)
76 77
77 /* %o0: devhandle 78 /* %o0: devhandle
78 * %o1: pci_device 79 * %o1: pci_device
@@ -85,14 +86,14 @@ pci_sun4v_config_get:
85 * status will be zero if the operation completed 86 * status will be zero if the operation completed
86 * successfully, else -1 if not 87 * successfully, else -1 if not
87 */ 88 */
88 .globl pci_sun4v_config_put 89ENTRY(pci_sun4v_config_put)
89pci_sun4v_config_put:
90 mov HV_FAST_PCI_CONFIG_PUT, %o5 90 mov HV_FAST_PCI_CONFIG_PUT, %o5
91 ta HV_FAST_TRAP 91 ta HV_FAST_TRAP
92 brnz,a,pn %o1, 1f 92 brnz,a,pn %o1, 1f
93 mov -1, %o1 93 mov -1, %o1
941: retl 941: retl
95 mov %o1, %o0 95 mov %o1, %o0
96ENDPROC(pci_sun4v_config_put)
96 97
97 /* %o0: devhandle 98 /* %o0: devhandle
98 * %o1: msiqid 99 * %o1: msiqid
@@ -104,12 +105,12 @@ pci_sun4v_config_put:
104 * status will be zero if the operation completed 105 * status will be zero if the operation completed
105 * successfully, else -1 if not 106 * successfully, else -1 if not
106 */ 107 */
107 .globl pci_sun4v_msiq_conf 108ENTRY(pci_sun4v_msiq_conf)
108pci_sun4v_msiq_conf:
109 mov HV_FAST_PCI_MSIQ_CONF, %o5 109 mov HV_FAST_PCI_MSIQ_CONF, %o5
110 ta HV_FAST_TRAP 110 ta HV_FAST_TRAP
111 retl 111 retl
112 mov %o0, %o0 112 mov %o0, %o0
113ENDPROC(pci_sun4v_msiq_conf)
113 114
114 /* %o0: devhandle 115 /* %o0: devhandle
115 * %o1: msiqid 116 * %o1: msiqid
@@ -118,8 +119,7 @@ pci_sun4v_msiq_conf:
118 * 119 *
119 * returns %o0: status 120 * returns %o0: status
120 */ 121 */
121 .globl pci_sun4v_msiq_info 122ENTRY(pci_sun4v_msiq_info)
122pci_sun4v_msiq_info:
123 mov %o2, %o4 123 mov %o2, %o4
124 mov HV_FAST_PCI_MSIQ_INFO, %o5 124 mov HV_FAST_PCI_MSIQ_INFO, %o5
125 ta HV_FAST_TRAP 125 ta HV_FAST_TRAP
@@ -127,6 +127,7 @@ pci_sun4v_msiq_info:
127 stx %o2, [%o3] 127 stx %o2, [%o3]
128 retl 128 retl
129 mov %o0, %o0 129 mov %o0, %o0
130ENDPROC(pci_sun4v_msiq_info)
130 131
131 /* %o0: devhandle 132 /* %o0: devhandle
132 * %o1: msiqid 133 * %o1: msiqid
@@ -134,13 +135,13 @@ pci_sun4v_msiq_info:
134 * 135 *
135 * returns %o0: status 136 * returns %o0: status
136 */ 137 */
137 .globl pci_sun4v_msiq_getvalid 138ENTRY(pci_sun4v_msiq_getvalid)
138pci_sun4v_msiq_getvalid:
139 mov HV_FAST_PCI_MSIQ_GETVALID, %o5 139 mov HV_FAST_PCI_MSIQ_GETVALID, %o5
140 ta HV_FAST_TRAP 140 ta HV_FAST_TRAP
141 stx %o1, [%o2] 141 stx %o1, [%o2]
142 retl 142 retl
143 mov %o0, %o0 143 mov %o0, %o0
144ENDPROC(pci_sun4v_msiq_getvalid)
144 145
145 /* %o0: devhandle 146 /* %o0: devhandle
146 * %o1: msiqid 147 * %o1: msiqid
@@ -148,12 +149,12 @@ pci_sun4v_msiq_getvalid:
148 * 149 *
149 * returns %o0: status 150 * returns %o0: status
150 */ 151 */
151 .globl pci_sun4v_msiq_setvalid 152ENTRY(pci_sun4v_msiq_setvalid)
152pci_sun4v_msiq_setvalid:
153 mov HV_FAST_PCI_MSIQ_SETVALID, %o5 153 mov HV_FAST_PCI_MSIQ_SETVALID, %o5
154 ta HV_FAST_TRAP 154 ta HV_FAST_TRAP
155 retl 155 retl
156 mov %o0, %o0 156 mov %o0, %o0
157ENDPROC(pci_sun4v_msiq_setvalid)
157 158
158 /* %o0: devhandle 159 /* %o0: devhandle
159 * %o1: msiqid 160 * %o1: msiqid
@@ -161,13 +162,13 @@ pci_sun4v_msiq_setvalid:
161 * 162 *
162 * returns %o0: status 163 * returns %o0: status
163 */ 164 */
164 .globl pci_sun4v_msiq_getstate 165ENTRY(pci_sun4v_msiq_getstate)
165pci_sun4v_msiq_getstate:
166 mov HV_FAST_PCI_MSIQ_GETSTATE, %o5 166 mov HV_FAST_PCI_MSIQ_GETSTATE, %o5
167 ta HV_FAST_TRAP 167 ta HV_FAST_TRAP
168 stx %o1, [%o2] 168 stx %o1, [%o2]
169 retl 169 retl
170 mov %o0, %o0 170 mov %o0, %o0
171ENDPROC(pci_sun4v_msiq_getstate)
171 172
172 /* %o0: devhandle 173 /* %o0: devhandle
173 * %o1: msiqid 174 * %o1: msiqid
@@ -175,12 +176,12 @@ pci_sun4v_msiq_getstate:
175 * 176 *
176 * returns %o0: status 177 * returns %o0: status
177 */ 178 */
178 .globl pci_sun4v_msiq_setstate 179ENTRY(pci_sun4v_msiq_setstate)
179pci_sun4v_msiq_setstate:
180 mov HV_FAST_PCI_MSIQ_SETSTATE, %o5 180 mov HV_FAST_PCI_MSIQ_SETSTATE, %o5
181 ta HV_FAST_TRAP 181 ta HV_FAST_TRAP
182 retl 182 retl
183 mov %o0, %o0 183 mov %o0, %o0
184ENDPROC(pci_sun4v_msiq_setstate)
184 185
185 /* %o0: devhandle 186 /* %o0: devhandle
186 * %o1: msiqid 187 * %o1: msiqid
@@ -188,13 +189,13 @@ pci_sun4v_msiq_setstate:
188 * 189 *
189 * returns %o0: status 190 * returns %o0: status
190 */ 191 */
191 .globl pci_sun4v_msiq_gethead 192ENTRY(pci_sun4v_msiq_gethead)
192pci_sun4v_msiq_gethead:
193 mov HV_FAST_PCI_MSIQ_GETHEAD, %o5 193 mov HV_FAST_PCI_MSIQ_GETHEAD, %o5
194 ta HV_FAST_TRAP 194 ta HV_FAST_TRAP
195 stx %o1, [%o2] 195 stx %o1, [%o2]
196 retl 196 retl
197 mov %o0, %o0 197 mov %o0, %o0
198ENDPROC(pci_sun4v_msiq_gethead)
198 199
199 /* %o0: devhandle 200 /* %o0: devhandle
200 * %o1: msiqid 201 * %o1: msiqid
@@ -202,12 +203,12 @@ pci_sun4v_msiq_gethead:
202 * 203 *
203 * returns %o0: status 204 * returns %o0: status
204 */ 205 */
205 .globl pci_sun4v_msiq_sethead 206ENTRY(pci_sun4v_msiq_sethead)
206pci_sun4v_msiq_sethead:
207 mov HV_FAST_PCI_MSIQ_SETHEAD, %o5 207 mov HV_FAST_PCI_MSIQ_SETHEAD, %o5
208 ta HV_FAST_TRAP 208 ta HV_FAST_TRAP
209 retl 209 retl
210 mov %o0, %o0 210 mov %o0, %o0
211ENDPROC(pci_sun4v_msiq_sethead)
211 212
212 /* %o0: devhandle 213 /* %o0: devhandle
213 * %o1: msiqid 214 * %o1: msiqid
@@ -215,13 +216,13 @@ pci_sun4v_msiq_sethead:
215 * 216 *
216 * returns %o0: status 217 * returns %o0: status
217 */ 218 */
218 .globl pci_sun4v_msiq_gettail 219ENTRY(pci_sun4v_msiq_gettail)
219pci_sun4v_msiq_gettail:
220 mov HV_FAST_PCI_MSIQ_GETTAIL, %o5 220 mov HV_FAST_PCI_MSIQ_GETTAIL, %o5
221 ta HV_FAST_TRAP 221 ta HV_FAST_TRAP
222 stx %o1, [%o2] 222 stx %o1, [%o2]
223 retl 223 retl
224 mov %o0, %o0 224 mov %o0, %o0
225ENDPROC(pci_sun4v_msiq_gettail)
225 226
226 /* %o0: devhandle 227 /* %o0: devhandle
227 * %o1: msinum 228 * %o1: msinum
@@ -229,13 +230,13 @@ pci_sun4v_msiq_gettail:
229 * 230 *
230 * returns %o0: status 231 * returns %o0: status
231 */ 232 */
232 .globl pci_sun4v_msi_getvalid 233ENTRY(pci_sun4v_msi_getvalid)
233pci_sun4v_msi_getvalid:
234 mov HV_FAST_PCI_MSI_GETVALID, %o5 234 mov HV_FAST_PCI_MSI_GETVALID, %o5
235 ta HV_FAST_TRAP 235 ta HV_FAST_TRAP
236 stx %o1, [%o2] 236 stx %o1, [%o2]
237 retl 237 retl
238 mov %o0, %o0 238 mov %o0, %o0
239ENDPROC(pci_sun4v_msi_getvalid)
239 240
240 /* %o0: devhandle 241 /* %o0: devhandle
241 * %o1: msinum 242 * %o1: msinum
@@ -243,12 +244,12 @@ pci_sun4v_msi_getvalid:
243 * 244 *
244 * returns %o0: status 245 * returns %o0: status
245 */ 246 */
246 .globl pci_sun4v_msi_setvalid 247ENTRY(pci_sun4v_msi_setvalid)
247pci_sun4v_msi_setvalid:
248 mov HV_FAST_PCI_MSI_SETVALID, %o5 248 mov HV_FAST_PCI_MSI_SETVALID, %o5
249 ta HV_FAST_TRAP 249 ta HV_FAST_TRAP
250 retl 250 retl
251 mov %o0, %o0 251 mov %o0, %o0
252ENDPROC(pci_sun4v_msi_setvalid)
252 253
253 /* %o0: devhandle 254 /* %o0: devhandle
254 * %o1: msinum 255 * %o1: msinum
@@ -256,13 +257,13 @@ pci_sun4v_msi_setvalid:
256 * 257 *
257 * returns %o0: status 258 * returns %o0: status
258 */ 259 */
259 .globl pci_sun4v_msi_getmsiq 260ENTRY(pci_sun4v_msi_getmsiq)
260pci_sun4v_msi_getmsiq:
261 mov HV_FAST_PCI_MSI_GETMSIQ, %o5 261 mov HV_FAST_PCI_MSI_GETMSIQ, %o5
262 ta HV_FAST_TRAP 262 ta HV_FAST_TRAP
263 stx %o1, [%o2] 263 stx %o1, [%o2]
264 retl 264 retl
265 mov %o0, %o0 265 mov %o0, %o0
266ENDPROC(pci_sun4v_msi_getmsiq)
266 267
267 /* %o0: devhandle 268 /* %o0: devhandle
268 * %o1: msinum 269 * %o1: msinum
@@ -271,12 +272,12 @@ pci_sun4v_msi_getmsiq:
271 * 272 *
272 * returns %o0: status 273 * returns %o0: status
273 */ 274 */
274 .globl pci_sun4v_msi_setmsiq 275ENTRY(pci_sun4v_msi_setmsiq)
275pci_sun4v_msi_setmsiq:
276 mov HV_FAST_PCI_MSI_SETMSIQ, %o5 276 mov HV_FAST_PCI_MSI_SETMSIQ, %o5
277 ta HV_FAST_TRAP 277 ta HV_FAST_TRAP
278 retl 278 retl
279 mov %o0, %o0 279 mov %o0, %o0
280ENDPROC(pci_sun4v_msi_setmsiq)
280 281
281 /* %o0: devhandle 282 /* %o0: devhandle
282 * %o1: msinum 283 * %o1: msinum
@@ -284,13 +285,13 @@ pci_sun4v_msi_setmsiq:
284 * 285 *
285 * returns %o0: status 286 * returns %o0: status
286 */ 287 */
287 .globl pci_sun4v_msi_getstate 288ENTRY(pci_sun4v_msi_getstate)
288pci_sun4v_msi_getstate:
289 mov HV_FAST_PCI_MSI_GETSTATE, %o5 289 mov HV_FAST_PCI_MSI_GETSTATE, %o5
290 ta HV_FAST_TRAP 290 ta HV_FAST_TRAP
291 stx %o1, [%o2] 291 stx %o1, [%o2]
292 retl 292 retl
293 mov %o0, %o0 293 mov %o0, %o0
294ENDPROC(pci_sun4v_msi_getstate)
294 295
295 /* %o0: devhandle 296 /* %o0: devhandle
296 * %o1: msinum 297 * %o1: msinum
@@ -298,12 +299,12 @@ pci_sun4v_msi_getstate:
298 * 299 *
299 * returns %o0: status 300 * returns %o0: status
300 */ 301 */
301 .globl pci_sun4v_msi_setstate 302ENTRY(pci_sun4v_msi_setstate)
302pci_sun4v_msi_setstate:
303 mov HV_FAST_PCI_MSI_SETSTATE, %o5 303 mov HV_FAST_PCI_MSI_SETSTATE, %o5
304 ta HV_FAST_TRAP 304 ta HV_FAST_TRAP
305 retl 305 retl
306 mov %o0, %o0 306 mov %o0, %o0
307ENDPROC(pci_sun4v_msi_setstate)
307 308
308 /* %o0: devhandle 309 /* %o0: devhandle
309 * %o1: msinum 310 * %o1: msinum
@@ -311,13 +312,13 @@ pci_sun4v_msi_setstate:
311 * 312 *
312 * returns %o0: status 313 * returns %o0: status
313 */ 314 */
314 .globl pci_sun4v_msg_getmsiq 315ENTRY(pci_sun4v_msg_getmsiq)
315pci_sun4v_msg_getmsiq:
316 mov HV_FAST_PCI_MSG_GETMSIQ, %o5 316 mov HV_FAST_PCI_MSG_GETMSIQ, %o5
317 ta HV_FAST_TRAP 317 ta HV_FAST_TRAP
318 stx %o1, [%o2] 318 stx %o1, [%o2]
319 retl 319 retl
320 mov %o0, %o0 320 mov %o0, %o0
321ENDPROC(pci_sun4v_msg_getmsiq)
321 322
322 /* %o0: devhandle 323 /* %o0: devhandle
323 * %o1: msinum 324 * %o1: msinum
@@ -325,12 +326,12 @@ pci_sun4v_msg_getmsiq:
325 * 326 *
326 * returns %o0: status 327 * returns %o0: status
327 */ 328 */
328 .globl pci_sun4v_msg_setmsiq 329ENTRY(pci_sun4v_msg_setmsiq)
329pci_sun4v_msg_setmsiq:
330 mov HV_FAST_PCI_MSG_SETMSIQ, %o5 330 mov HV_FAST_PCI_MSG_SETMSIQ, %o5
331 ta HV_FAST_TRAP 331 ta HV_FAST_TRAP
332 retl 332 retl
333 mov %o0, %o0 333 mov %o0, %o0
334ENDPROC(pci_sun4v_msg_setmsiq)
334 335
335 /* %o0: devhandle 336 /* %o0: devhandle
336 * %o1: msinum 337 * %o1: msinum
@@ -338,13 +339,13 @@ pci_sun4v_msg_setmsiq:
338 * 339 *
339 * returns %o0: status 340 * returns %o0: status
340 */ 341 */
341 .globl pci_sun4v_msg_getvalid 342ENTRY(pci_sun4v_msg_getvalid)
342pci_sun4v_msg_getvalid:
343 mov HV_FAST_PCI_MSG_GETVALID, %o5 343 mov HV_FAST_PCI_MSG_GETVALID, %o5
344 ta HV_FAST_TRAP 344 ta HV_FAST_TRAP
345 stx %o1, [%o2] 345 stx %o1, [%o2]
346 retl 346 retl
347 mov %o0, %o0 347 mov %o0, %o0
348ENDPROC(pci_sun4v_msg_getvalid)
348 349
349 /* %o0: devhandle 350 /* %o0: devhandle
350 * %o1: msinum 351 * %o1: msinum
@@ -352,10 +353,10 @@ pci_sun4v_msg_getvalid:
352 * 353 *
353 * returns %o0: status 354 * returns %o0: status
354 */ 355 */
355 .globl pci_sun4v_msg_setvalid 356ENTRY(pci_sun4v_msg_setvalid)
356pci_sun4v_msg_setvalid:
357 mov HV_FAST_PCI_MSG_SETVALID, %o5 357 mov HV_FAST_PCI_MSG_SETVALID, %o5
358 ta HV_FAST_TRAP 358 ta HV_FAST_TRAP
359 retl 359 retl
360 mov %o0, %o0 360 mov %o0, %o0
361ENDPROC(pci_sun4v_msg_setvalid)
361 362
diff --git a/arch/sparc64/kernel/power.c b/arch/sparc64/kernel/power.c
index 3bb987a6d03..076cad7f975 100644
--- a/arch/sparc64/kernel/power.c
+++ b/arch/sparc64/kernel/power.c
@@ -1,34 +1,17 @@
1/* power.c: Power management driver. 1/* power.c: Power management driver.
2 * 2 *
3 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */ 4 */
5 5
6#include <linux/kernel.h> 6#include <linux/kernel.h>
7#include <linux/module.h> 7#include <linux/module.h>
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/sched.h>
10#include <linux/signal.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h> 9#include <linux/interrupt.h>
13#include <linux/pm.h>
14#include <linux/syscalls.h>
15#include <linux/reboot.h> 10#include <linux/reboot.h>
16#include <linux/of_device.h> 11#include <linux/of_device.h>
17 12
18#include <asm/system.h>
19#include <asm/auxio.h>
20#include <asm/prom.h> 13#include <asm/prom.h>
21#include <asm/io.h> 14#include <asm/io.h>
22#include <asm/sstate.h>
23#include <asm/reboot.h>
24
25#include <linux/unistd.h>
26
27/*
28 * sysctl - toggle power-off restriction for serial console
29 * systems in machine_power_off()
30 */
31int scons_pwroff = 1;
32 15
33static void __iomem *power_reg; 16static void __iomem *power_reg;
34 17
@@ -40,31 +23,6 @@ static irqreturn_t power_handler(int irq, void *dev_id)
40 return IRQ_HANDLED; 23 return IRQ_HANDLED;
41} 24}
42 25
43static void (*poweroff_method)(void) = machine_alt_power_off;
44
45void machine_power_off(void)
46{
47 sstate_poweroff();
48 if (strcmp(of_console_device->type, "serial") || scons_pwroff) {
49 if (power_reg) {
50 /* Both register bits seem to have the
51 * same effect, so until I figure out
52 * what the difference is...
53 */
54 writel(AUXIO_PCIO_CPWR_OFF | AUXIO_PCIO_SPWR_OFF, power_reg);
55 } else {
56 if (poweroff_method != NULL) {
57 poweroff_method();
58 /* not reached */
59 }
60 }
61 }
62 machine_halt();
63}
64
65void (*pm_power_off)(void) = machine_power_off;
66EXPORT_SYMBOL(pm_power_off);
67
68static int __init has_button_interrupt(unsigned int irq, struct device_node *dp) 26static int __init has_button_interrupt(unsigned int irq, struct device_node *dp)
69{ 27{
70 if (irq == 0xffffffff) 28 if (irq == 0xffffffff)
@@ -85,8 +43,6 @@ static int __devinit power_probe(struct of_device *op, const struct of_device_id
85 printk(KERN_INFO "%s: Control reg at %lx\n", 43 printk(KERN_INFO "%s: Control reg at %lx\n",
86 op->node->name, res->start); 44 op->node->name, res->start);
87 45
88 poweroff_method = machine_halt; /* able to use the standard halt */
89
90 if (has_button_interrupt(irq, op->node)) { 46 if (has_button_interrupt(irq, op->node)) {
91 if (request_irq(irq, 47 if (request_irq(irq,
92 power_handler, 0, "power", NULL) < 0) 48 power_handler, 0, "power", NULL) < 0)
@@ -96,7 +52,7 @@ static int __devinit power_probe(struct of_device *op, const struct of_device_id
96 return 0; 52 return 0;
97} 53}
98 54
99static struct of_device_id power_match[] = { 55static struct of_device_id __initdata power_match[] = {
100 { 56 {
101 .name = "power", 57 .name = "power",
102 }, 58 },
@@ -111,8 +67,9 @@ static struct of_platform_driver power_driver = {
111 }, 67 },
112}; 68};
113 69
114void __init power_init(void) 70static int __init power_init(void)
115{ 71{
116 of_register_driver(&power_driver, &of_platform_bus_type); 72 return of_register_driver(&power_driver, &of_platform_bus_type);
117 return;
118} 73}
74
75device_initcall(power_init);
diff --git a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
index 15f4178592e..d5e2acef987 100644
--- a/arch/sparc64/kernel/process.c
+++ b/arch/sparc64/kernel/process.c
@@ -22,7 +22,6 @@
22#include <linux/ptrace.h> 22#include <linux/ptrace.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include <linux/user.h> 24#include <linux/user.h>
25#include <linux/reboot.h>
26#include <linux/delay.h> 25#include <linux/delay.h>
27#include <linux/compat.h> 26#include <linux/compat.h>
28#include <linux/tick.h> 27#include <linux/tick.h>
@@ -31,7 +30,6 @@
31#include <linux/elfcore.h> 30#include <linux/elfcore.h>
32#include <linux/sysrq.h> 31#include <linux/sysrq.h>
33 32
34#include <asm/oplib.h>
35#include <asm/uaccess.h> 33#include <asm/uaccess.h>
36#include <asm/system.h> 34#include <asm/system.h>
37#include <asm/page.h> 35#include <asm/page.h>
@@ -46,8 +44,6 @@
46#include <asm/mmu_context.h> 44#include <asm/mmu_context.h>
47#include <asm/unistd.h> 45#include <asm/unistd.h>
48#include <asm/hypervisor.h> 46#include <asm/hypervisor.h>
49#include <asm/sstate.h>
50#include <asm/reboot.h>
51#include <asm/syscalls.h> 47#include <asm/syscalls.h>
52#include <asm/irq_regs.h> 48#include <asm/irq_regs.h>
53#include <asm/smp.h> 49#include <asm/smp.h>
@@ -115,35 +111,6 @@ void cpu_idle(void)
115 } 111 }
116} 112}
117 113
118void machine_halt(void)
119{
120 sstate_halt();
121 prom_halt();
122 panic("Halt failed!");
123}
124
125void machine_alt_power_off(void)
126{
127 sstate_poweroff();
128 prom_halt_power_off();
129 panic("Power-off failed!");
130}
131
132void machine_restart(char * cmd)
133{
134 char *p;
135
136 sstate_reboot();
137 p = strchr (reboot_command, '\n');
138 if (p) *p = 0;
139 if (cmd)
140 prom_reboot(cmd);
141 if (*reboot_command)
142 prom_reboot(reboot_command);
143 prom_reboot("");
144 panic("Reboot failed!");
145}
146
147#ifdef CONFIG_COMPAT 114#ifdef CONFIG_COMPAT
148static void show_regwindow32(struct pt_regs *regs) 115static void show_regwindow32(struct pt_regs *regs)
149{ 116{
@@ -248,7 +215,6 @@ static void __global_reg_self(struct thread_info *tp, struct pt_regs *regs,
248 global_reg_snapshot[this_cpu].o7 = regs->u_regs[UREG_I7]; 215 global_reg_snapshot[this_cpu].o7 = regs->u_regs[UREG_I7];
249 216
250 if (regs->tstate & TSTATE_PRIV) { 217 if (regs->tstate & TSTATE_PRIV) {
251 struct thread_info *tp = current_thread_info();
252 struct reg_window *rw; 218 struct reg_window *rw;
253 219
254 rw = (struct reg_window *) 220 rw = (struct reg_window *)
@@ -304,7 +270,6 @@ void __trigger_all_cpu_backtrace(void)
304 270
305 for_each_online_cpu(cpu) { 271 for_each_online_cpu(cpu) {
306 struct global_reg_snapshot *gp = &global_reg_snapshot[cpu]; 272 struct global_reg_snapshot *gp = &global_reg_snapshot[cpu];
307 struct thread_info *tp;
308 273
309 __global_reg_poll(gp); 274 __global_reg_poll(gp);
310 275
diff --git a/arch/sparc64/kernel/prom.c b/arch/sparc64/kernel/prom.c
index 7151513f156..dbba82f9b14 100644
--- a/arch/sparc64/kernel/prom.c
+++ b/arch/sparc64/kernel/prom.c
@@ -38,7 +38,7 @@ struct device_node *of_find_node_by_phandle(phandle handle)
38{ 38{
39 struct device_node *np; 39 struct device_node *np;
40 40
41 for (np = allnodes; np != 0; np = np->allnext) 41 for (np = allnodes; np; np = np->allnext)
42 if (np->node == handle) 42 if (np->node == handle)
43 break; 43 break;
44 44
@@ -59,6 +59,9 @@ int of_getintprop_default(struct device_node *np, const char *name, int def)
59} 59}
60EXPORT_SYMBOL(of_getintprop_default); 60EXPORT_SYMBOL(of_getintprop_default);
61 61
62DEFINE_MUTEX(of_set_property_mutex);
63EXPORT_SYMBOL(of_set_property_mutex);
64
62int of_set_property(struct device_node *dp, const char *name, void *val, int len) 65int of_set_property(struct device_node *dp, const char *name, void *val, int len)
63{ 66{
64 struct property **prevp; 67 struct property **prevp;
@@ -82,7 +85,10 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
82 void *old_val = prop->value; 85 void *old_val = prop->value;
83 int ret; 86 int ret;
84 87
88 mutex_lock(&of_set_property_mutex);
85 ret = prom_setprop(dp->node, name, val, len); 89 ret = prom_setprop(dp->node, name, val, len);
90 mutex_unlock(&of_set_property_mutex);
91
86 err = -EINVAL; 92 err = -EINVAL;
87 if (ret >= 0) { 93 if (ret >= 0) {
88 prop->value = new_val; 94 prop->value = new_val;
@@ -945,22 +951,30 @@ static void __init irq_trans_init(struct device_node *dp)
945 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) { 951 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
946 struct irq_trans *t = &pci_irq_trans_table[i]; 952 struct irq_trans *t = &pci_irq_trans_table[i];
947 953
948 if (!strcmp(model, t->name)) 954 if (!strcmp(model, t->name)) {
949 return t->init(dp); 955 t->init(dp);
956 return;
957 }
950 } 958 }
951 } 959 }
952#endif 960#endif
953#ifdef CONFIG_SBUS 961#ifdef CONFIG_SBUS
954 if (!strcmp(dp->name, "sbus") || 962 if (!strcmp(dp->name, "sbus") ||
955 !strcmp(dp->name, "sbi")) 963 !strcmp(dp->name, "sbi")) {
956 return sbus_irq_trans_init(dp); 964 sbus_irq_trans_init(dp);
965 return;
966 }
957#endif 967#endif
958 if (!strcmp(dp->name, "fhc") && 968 if (!strcmp(dp->name, "fhc") &&
959 !strcmp(dp->parent->name, "central")) 969 !strcmp(dp->parent->name, "central")) {
960 return central_irq_trans_init(dp); 970 central_irq_trans_init(dp);
971 return;
972 }
961 if (!strcmp(dp->name, "virtual-devices") || 973 if (!strcmp(dp->name, "virtual-devices") ||
962 !strcmp(dp->name, "niu")) 974 !strcmp(dp->name, "niu")) {
963 return sun4v_vdev_irq_trans_init(dp); 975 sun4v_vdev_irq_trans_init(dp);
976 return;
977 }
964} 978}
965 979
966static int is_root_node(const struct device_node *dp) 980static int is_root_node(const struct device_node *dp)
@@ -1231,32 +1245,49 @@ static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
1231 1245
1232 if (parent != NULL) { 1246 if (parent != NULL) {
1233 if (!strcmp(parent->type, "pci") || 1247 if (!strcmp(parent->type, "pci") ||
1234 !strcmp(parent->type, "pciex")) 1248 !strcmp(parent->type, "pciex")) {
1235 return pci_path_component(dp, tmp_buf); 1249 pci_path_component(dp, tmp_buf);
1236 if (!strcmp(parent->type, "sbus")) 1250 return;
1237 return sbus_path_component(dp, tmp_buf); 1251 }
1238 if (!strcmp(parent->type, "upa")) 1252 if (!strcmp(parent->type, "sbus")) {
1239 return upa_path_component(dp, tmp_buf); 1253 sbus_path_component(dp, tmp_buf);
1240 if (!strcmp(parent->type, "ebus")) 1254 return;
1241 return ebus_path_component(dp, tmp_buf); 1255 }
1256 if (!strcmp(parent->type, "upa")) {
1257 upa_path_component(dp, tmp_buf);
1258 return;
1259 }
1260 if (!strcmp(parent->type, "ebus")) {
1261 ebus_path_component(dp, tmp_buf);
1262 return;
1263 }
1242 if (!strcmp(parent->name, "usb") || 1264 if (!strcmp(parent->name, "usb") ||
1243 !strcmp(parent->name, "hub")) 1265 !strcmp(parent->name, "hub")) {
1244 return usb_path_component(dp, tmp_buf); 1266 usb_path_component(dp, tmp_buf);
1245 if (!strcmp(parent->type, "i2c")) 1267 return;
1246 return i2c_path_component(dp, tmp_buf); 1268 }
1247 if (!strcmp(parent->type, "firewire")) 1269 if (!strcmp(parent->type, "i2c")) {
1248 return ieee1394_path_component(dp, tmp_buf); 1270 i2c_path_component(dp, tmp_buf);
1249 if (!strcmp(parent->type, "virtual-devices")) 1271 return;
1250 return vdev_path_component(dp, tmp_buf); 1272 }
1251 1273 if (!strcmp(parent->type, "firewire")) {
1274 ieee1394_path_component(dp, tmp_buf);
1275 return;
1276 }
1277 if (!strcmp(parent->type, "virtual-devices")) {
1278 vdev_path_component(dp, tmp_buf);
1279 return;
1280 }
1252 /* "isa" is handled with platform naming */ 1281 /* "isa" is handled with platform naming */
1253 } 1282 }
1254 1283
1255 /* Use platform naming convention. */ 1284 /* Use platform naming convention. */
1256 if (tlb_type == hypervisor) 1285 if (tlb_type == hypervisor) {
1257 return sun4v_path_component(dp, tmp_buf); 1286 sun4v_path_component(dp, tmp_buf);
1258 else 1287 return;
1259 return sun4u_path_component(dp, tmp_buf); 1288 } else {
1289 sun4u_path_component(dp, tmp_buf);
1290 }
1260} 1291}
1261 1292
1262static char * __init build_path_component(struct device_node *dp) 1293static char * __init build_path_component(struct device_node *dp)
diff --git a/arch/sparc64/kernel/psycho_common.c b/arch/sparc64/kernel/psycho_common.c
new file mode 100644
index 00000000000..790996428c1
--- /dev/null
+++ b/arch/sparc64/kernel/psycho_common.c
@@ -0,0 +1,470 @@
1/* psycho_common.c: Code common to PSYCHO and derivative PCI controllers.
2 *
3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
4 */
5#include <linux/kernel.h>
6#include <linux/interrupt.h>
7
8#include <asm/upa.h>
9
10#include "pci_impl.h"
11#include "iommu_common.h"
12#include "psycho_common.h"
13
14#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL
15#define PSYCHO_STCERR_WRITE 0x0000000000000002UL
16#define PSYCHO_STCERR_READ 0x0000000000000001UL
17#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL
18#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL
19#define PSYCHO_STCTAG_VALID 0x0000000000000002UL
20#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL
21#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL
22#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL
23#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL
24#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL
25#define PSYCHO_STCLINE_VALID 0x0000000000000002UL
26#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL
27
28static DEFINE_SPINLOCK(stc_buf_lock);
29static unsigned long stc_error_buf[128];
30static unsigned long stc_tag_buf[16];
31static unsigned long stc_line_buf[16];
32
33static void psycho_check_stc_error(struct pci_pbm_info *pbm)
34{
35 unsigned long err_base, tag_base, line_base;
36 struct strbuf *strbuf = &pbm->stc;
37 u64 control;
38 int i;
39
40 if (!strbuf->strbuf_control)
41 return;
42
43 err_base = strbuf->strbuf_err_stat;
44 tag_base = strbuf->strbuf_tag_diag;
45 line_base = strbuf->strbuf_line_diag;
46
47 spin_lock(&stc_buf_lock);
48
49 /* This is __REALLY__ dangerous. When we put the streaming
50 * buffer into diagnostic mode to probe it's tags and error
51 * status, we _must_ clear all of the line tag valid bits
52 * before re-enabling the streaming buffer. If any dirty data
53 * lives in the STC when we do this, we will end up
54 * invalidating it before it has a chance to reach main
55 * memory.
56 */
57 control = upa_readq(strbuf->strbuf_control);
58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control);
59 for (i = 0; i < 128; i++) {
60 u64 val;
61
62 val = upa_readq(err_base + (i * 8UL));
63 upa_writeq(0UL, err_base + (i * 8UL));
64 stc_error_buf[i] = val;
65 }
66 for (i = 0; i < 16; i++) {
67 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
68 stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
69 upa_writeq(0UL, tag_base + (i * 8UL));
70 upa_writeq(0UL, line_base + (i * 8UL));
71 }
72
73 /* OK, state is logged, exit diagnostic mode. */
74 upa_writeq(control, strbuf->strbuf_control);
75
76 for (i = 0; i < 16; i++) {
77 int j, saw_error, first, last;
78
79 saw_error = 0;
80 first = i * 8;
81 last = first + 8;
82 for (j = first; j < last; j++) {
83 u64 errval = stc_error_buf[j];
84 if (errval != 0) {
85 saw_error++;
86 printk(KERN_ERR "%s: STC_ERR(%d)[wr(%d)"
87 "rd(%d)]\n",
88 pbm->name,
89 j,
90 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
91 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
92 }
93 }
94 if (saw_error != 0) {
95 u64 tagval = stc_tag_buf[i];
96 u64 lineval = stc_line_buf[i];
97 printk(KERN_ERR "%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)"
98 "V(%d)W(%d)]\n",
99 pbm->name,
100 i,
101 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
102 (tagval & PSYCHO_STCTAG_VPN),
103 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
104 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
105 printk(KERN_ERR "%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)"
106 "LADDR(%lx)EP(%lx)V(%d)FOFN(%d)]\n",
107 pbm->name,
108 i,
109 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
110 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
111 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
112 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
113 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
114 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
115 }
116 }
117
118 spin_unlock(&stc_buf_lock);
119}
120
121#define PSYCHO_IOMMU_TAG 0xa580UL
122#define PSYCHO_IOMMU_DATA 0xa600UL
123
124static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm,
125 u64 *tag, u64 *data)
126{
127 int i;
128
129 for (i = 0; i < 16; i++) {
130 unsigned long base = pbm->controller_regs;
131 unsigned long off = i * 8UL;
132
133 tag[i] = upa_readq(base + PSYCHO_IOMMU_TAG+off);
134 data[i] = upa_readq(base + PSYCHO_IOMMU_DATA+off);
135
136 /* Now clear out the entry. */
137 upa_writeq(0, base + PSYCHO_IOMMU_TAG + off);
138 upa_writeq(0, base + PSYCHO_IOMMU_DATA + off);
139 }
140}
141
142#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
143#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
144#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
145#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
146#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
147#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
148#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
149#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
150#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
151
152static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm,
153 u64 *tag, u64 *data)
154{
155 int i;
156
157 for (i = 0; i < 16; i++) {
158 u64 tag_val, data_val;
159 const char *type_str;
160 tag_val = tag[i];
161 if (!(tag_val & PSYCHO_IOMMU_TAG_ERR))
162 continue;
163
164 data_val = data[i];
165 switch((tag_val & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
166 case 0:
167 type_str = "Protection Error";
168 break;
169 case 1:
170 type_str = "Invalid Error";
171 break;
172 case 2:
173 type_str = "TimeOut Error";
174 break;
175 case 3:
176 default:
177 type_str = "ECC Error";
178 break;
179 }
180
181 printk(KERN_ERR "%s: IOMMU TAG(%d)[error(%s) wr(%d) "
182 "str(%d) sz(%dK) vpg(%08lx)]\n",
183 pbm->name, i, type_str,
184 ((tag_val & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
185 ((tag_val & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
186 ((tag_val & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
187 (tag_val & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
188 printk(KERN_ERR "%s: IOMMU DATA(%d)[valid(%d) cache(%d) "
189 "ppg(%016lx)]\n",
190 pbm->name, i,
191 ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
192 ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
193 (data_val & PSYCHO_IOMMU_DATA_PPAGE)<<IOMMU_PAGE_SHIFT);
194 }
195}
196
197#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL
198#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL
199
200void psycho_check_iommu_error(struct pci_pbm_info *pbm,
201 unsigned long afsr,
202 unsigned long afar,
203 enum psycho_error_type type)
204{
205 u64 control, iommu_tag[16], iommu_data[16];
206 struct iommu *iommu = pbm->iommu;
207 unsigned long flags;
208
209 spin_lock_irqsave(&iommu->lock, flags);
210 control = upa_readq(iommu->iommu_control);
211 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
212 const char *type_str;
213
214 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
215 upa_writeq(control, iommu->iommu_control);
216
217 switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
218 case 0:
219 type_str = "Protection Error";
220 break;
221 case 1:
222 type_str = "Invalid Error";
223 break;
224 case 2:
225 type_str = "TimeOut Error";
226 break;
227 case 3:
228 default:
229 type_str = "ECC Error";
230 break;
231 };
232 printk(KERN_ERR "%s: IOMMU Error, type[%s]\n",
233 pbm->name, type_str);
234
235 /* It is very possible for another DVMA to occur while
236 * we do this probe, and corrupt the system further.
237 * But we are so screwed at this point that we are
238 * likely to crash hard anyways, so get as much
239 * diagnostic information to the console as we can.
240 */
241 psycho_record_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
242 psycho_dump_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
243 }
244 psycho_check_stc_error(pbm);
245 spin_unlock_irqrestore(&iommu->lock, flags);
246}
247
248#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL
249#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL
250
251static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
252{
253 irqreturn_t ret = IRQ_NONE;
254 u64 csr, csr_error_bits;
255 u16 stat, *addr;
256
257 csr = upa_readq(pbm->pci_csr);
258 csr_error_bits = csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
259 if (csr_error_bits) {
260 /* Clear the errors. */
261 upa_writeq(csr, pbm->pci_csr);
262
263 /* Log 'em. */
264 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
265 printk(KERN_ERR "%s: PCI streaming byte hole "
266 "error asserted.\n", pbm->name);
267 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
268 printk(KERN_ERR "%s: PCI SERR signal asserted.\n",
269 pbm->name);
270 ret = IRQ_HANDLED;
271 }
272 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
273 0, PCI_STATUS);
274 pci_config_read16(addr, &stat);
275 if (stat & (PCI_STATUS_PARITY |
276 PCI_STATUS_SIG_TARGET_ABORT |
277 PCI_STATUS_REC_TARGET_ABORT |
278 PCI_STATUS_REC_MASTER_ABORT |
279 PCI_STATUS_SIG_SYSTEM_ERROR)) {
280 printk(KERN_ERR "%s: PCI bus error, PCI_STATUS[%04x]\n",
281 pbm->name, stat);
282 pci_config_write16(addr, 0xffff);
283 ret = IRQ_HANDLED;
284 }
285 return ret;
286}
287
288#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL
289#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL
290#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL
291#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL
292#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL
293#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL
294#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL
295#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL
296#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL
297#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL
298#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL
299#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL
300#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL
301#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL
302
303irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
304{
305 struct pci_pbm_info *pbm = dev_id;
306 u64 afsr, afar, error_bits;
307 int reported;
308
309 afsr = upa_readq(pbm->pci_afsr);
310 afar = upa_readq(pbm->pci_afar);
311 error_bits = afsr &
312 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
313 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
314 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
315 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
316 if (!error_bits)
317 return psycho_pcierr_intr_other(pbm);
318 upa_writeq(error_bits, pbm->pci_afsr);
319 printk(KERN_ERR "%s: PCI Error, primary error type[%s]\n",
320 pbm->name,
321 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
322 "Master Abort" :
323 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
324 "Target Abort" :
325 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
326 "Excessive Retries" :
327 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
328 "Parity Error" : "???"))))));
329 printk(KERN_ERR "%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
330 pbm->name,
331 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
332 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
333 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
334 printk(KERN_ERR "%s: PCI AFAR [%016lx]\n", pbm->name, afar);
335 printk(KERN_ERR "%s: PCI Secondary errors [", pbm->name);
336 reported = 0;
337 if (afsr & PSYCHO_PCIAFSR_SMA) {
338 reported++;
339 printk("(Master Abort)");
340 }
341 if (afsr & PSYCHO_PCIAFSR_STA) {
342 reported++;
343 printk("(Target Abort)");
344 }
345 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
346 reported++;
347 printk("(Excessive Retries)");
348 }
349 if (afsr & PSYCHO_PCIAFSR_SPERR) {
350 reported++;
351 printk("(Parity Error)");
352 }
353 if (!reported)
354 printk("(none)");
355 printk("]\n");
356
357 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
358 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
359 pci_scan_for_target_abort(pbm, pbm->pci_bus);
360 }
361 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
362 pci_scan_for_master_abort(pbm, pbm->pci_bus);
363
364 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
365 pci_scan_for_parity_error(pbm, pbm->pci_bus);
366
367 return IRQ_HANDLED;
368}
369
370static void psycho_iommu_flush(struct pci_pbm_info *pbm)
371{
372 int i;
373
374 for (i = 0; i < 16; i++) {
375 unsigned long off = i * 8;
376
377 upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_TAG + off);
378 upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_DATA + off);
379 }
380}
381
382#define PSYCHO_IOMMU_CONTROL 0x0200UL
383#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL
384#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL
385#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL
386#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL
387#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL
388#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL
389#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL
390#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL
391#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL
392#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL
393#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL
394#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL
395#define PSYCHO_IOMMU_FLUSH 0x0210UL
396#define PSYCHO_IOMMU_TSBBASE 0x0208UL
397
398int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize,
399 u32 dvma_offset, u32 dma_mask,
400 unsigned long write_complete_offset)
401{
402 struct iommu *iommu = pbm->iommu;
403 u64 control;
404 int err;
405
406 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
407 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
408 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
409 iommu->iommu_tags = pbm->controller_regs + PSYCHO_IOMMU_TAG;
410 iommu->write_complete_reg = (pbm->controller_regs +
411 write_complete_offset);
412
413 iommu->iommu_ctxflush = 0;
414
415 control = upa_readq(iommu->iommu_control);
416 control |= PSYCHO_IOMMU_CTRL_DENAB;
417 upa_writeq(control, iommu->iommu_control);
418
419 psycho_iommu_flush(pbm);
420
421 /* Leave diag mode enabled for full-flushing done in pci_iommu.c */
422 err = iommu_table_init(iommu, tsbsize * 1024 * 8,
423 dvma_offset, dma_mask, pbm->numa_node);
424 if (err)
425 return err;
426
427 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
428
429 control = upa_readq(iommu->iommu_control);
430 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
431 control |= PSYCHO_IOMMU_CTRL_ENAB;
432
433 switch (tsbsize) {
434 case 64:
435 control |= PSYCHO_IOMMU_TSBSZ_64K;
436 break;
437 case 128:
438 control |= PSYCHO_IOMMU_TSBSZ_128K;
439 break;
440 default:
441 return -EINVAL;
442 }
443
444 upa_writeq(control, iommu->iommu_control);
445
446 return 0;
447
448}
449
450void psycho_pbm_init_common(struct pci_pbm_info *pbm, struct of_device *op,
451 const char *chip_name, int chip_type)
452{
453 struct device_node *dp = op->node;
454
455 pbm->name = dp->full_name;
456 pbm->numa_node = -1;
457 pbm->chip_type = chip_type;
458 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
459 pbm->chip_revision = of_getintprop_default(dp, "module-revision#", 0);
460 pbm->op = op;
461 pbm->pci_ops = &sun4u_pci_ops;
462 pbm->config_space_reg_bits = 8;
463 pbm->index = pci_num_pbms++;
464 pci_get_pbm_props(pbm);
465 pci_determine_mem_io_space(pbm);
466
467 printk(KERN_INFO "%s: %s PCI Bus Module ver[%x:%x]\n",
468 pbm->name, chip_name,
469 pbm->chip_version, pbm->chip_revision);
470}
diff --git a/arch/sparc64/kernel/psycho_common.h b/arch/sparc64/kernel/psycho_common.h
new file mode 100644
index 00000000000..092c278ef28
--- /dev/null
+++ b/arch/sparc64/kernel/psycho_common.h
@@ -0,0 +1,48 @@
1#ifndef _PSYCHO_COMMON_H
2#define _PSYCHO_COMMON_H
3
4/* U2P Programmer's Manual, page 13-55, configuration space
5 * address format:
6 *
7 * 32 24 23 16 15 11 10 8 7 2 1 0
8 * ---------------------------------------------------------
9 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
10 * ---------------------------------------------------------
11 */
12#define PSYCHO_CONFIG_BASE(PBM) \
13 ((PBM)->config_space | (1UL << 24))
14#define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
15 (((unsigned long)(BUS) << 16) | \
16 ((unsigned long)(DEVFN) << 8) | \
17 ((unsigned long)(REG)))
18
19static inline void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
20 unsigned char bus,
21 unsigned int devfn,
22 int where)
23{
24 return (void *)
25 (PSYCHO_CONFIG_BASE(pbm) |
26 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
27}
28
29enum psycho_error_type {
30 UE_ERR, CE_ERR, PCI_ERR
31};
32
33extern void psycho_check_iommu_error(struct pci_pbm_info *pbm,
34 unsigned long afsr,
35 unsigned long afar,
36 enum psycho_error_type type);
37
38extern irqreturn_t psycho_pcierr_intr(int irq, void *dev_id);
39
40extern int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize,
41 u32 dvma_offset, u32 dma_mask,
42 unsigned long write_complete_offset);
43
44extern void psycho_pbm_init_common(struct pci_pbm_info *pbm,
45 struct of_device *op,
46 const char *chip_name, int chip_type);
47
48#endif /* _PSYCHO_COMMON_H */
diff --git a/arch/sparc64/kernel/ptrace.c b/arch/sparc64/kernel/ptrace.c
index 10306e476e3..f43adbc773c 100644
--- a/arch/sparc64/kernel/ptrace.c
+++ b/arch/sparc64/kernel/ptrace.c
@@ -1050,31 +1050,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
1050 return ret; 1050 return ret;
1051} 1051}
1052 1052
1053asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p) 1053asmlinkage int syscall_trace_enter(struct pt_regs *regs)
1054{ 1054{
1055 int ret = 0; 1055 int ret = 0;
1056 1056
1057 /* do the secure computing check first */ 1057 /* do the secure computing check first */
1058 secure_computing(regs->u_regs[UREG_G1]); 1058 secure_computing(regs->u_regs[UREG_G1]);
1059 1059
1060 if (unlikely(current->audit_context) && syscall_exit_p) { 1060 if (test_thread_flag(TIF_SYSCALL_TRACE))
1061 unsigned long tstate = regs->tstate; 1061 ret = tracehook_report_syscall_entry(regs);
1062 int result = AUDITSC_SUCCESS;
1063
1064 if (unlikely(tstate & (TSTATE_XCARRY | TSTATE_ICARRY)))
1065 result = AUDITSC_FAILURE;
1066
1067 audit_syscall_exit(result, regs->u_regs[UREG_I0]);
1068 }
1069
1070 if (test_thread_flag(TIF_SYSCALL_TRACE)) {
1071 if (syscall_exit_p)
1072 tracehook_report_syscall_exit(regs, 0);
1073 else
1074 ret = tracehook_report_syscall_entry(regs);
1075 }
1076 1062
1077 if (unlikely(current->audit_context) && !syscall_exit_p && !ret) 1063 if (unlikely(current->audit_context) && !ret)
1078 audit_syscall_entry((test_thread_flag(TIF_32BIT) ? 1064 audit_syscall_entry((test_thread_flag(TIF_32BIT) ?
1079 AUDIT_ARCH_SPARC : 1065 AUDIT_ARCH_SPARC :
1080 AUDIT_ARCH_SPARC64), 1066 AUDIT_ARCH_SPARC64),
@@ -1086,3 +1072,19 @@ asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p)
1086 1072
1087 return ret; 1073 return ret;
1088} 1074}
1075
1076asmlinkage void syscall_trace_leave(struct pt_regs *regs)
1077{
1078 if (unlikely(current->audit_context)) {
1079 unsigned long tstate = regs->tstate;
1080 int result = AUDITSC_SUCCESS;
1081
1082 if (unlikely(tstate & (TSTATE_XCARRY | TSTATE_ICARRY)))
1083 result = AUDITSC_FAILURE;
1084
1085 audit_syscall_exit(result, regs->u_regs[UREG_I0]);
1086 }
1087
1088 if (test_thread_flag(TIF_SYSCALL_TRACE))
1089 tracehook_report_syscall_exit(regs, 0);
1090}
diff --git a/arch/sparc64/kernel/reboot.c b/arch/sparc64/kernel/reboot.c
new file mode 100644
index 00000000000..ef89d3d6974
--- /dev/null
+++ b/arch/sparc64/kernel/reboot.c
@@ -0,0 +1,53 @@
1/* reboot.c: reboot/shutdown/halt/poweroff handling
2 *
3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
4 */
5#include <linux/kernel.h>
6#include <linux/reboot.h>
7#include <linux/module.h>
8#include <linux/pm.h>
9
10#include <asm/system.h>
11#include <asm/oplib.h>
12#include <asm/prom.h>
13
14/* sysctl - toggle power-off restriction for serial console
15 * systems in machine_power_off()
16 */
17int scons_pwroff = 1;
18
19/* This isn't actually used, it exists merely to satisfy the
20 * reference in kernel/sys.c
21 */
22void (*pm_power_off)(void) = machine_power_off;
23EXPORT_SYMBOL(pm_power_off);
24
25void machine_power_off(void)
26{
27 if (strcmp(of_console_device->type, "serial") || scons_pwroff)
28 prom_halt_power_off();
29
30 prom_halt();
31}
32
33void machine_halt(void)
34{
35 prom_halt();
36 panic("Halt failed!");
37}
38
39void machine_restart(char *cmd)
40{
41 char *p;
42
43 p = strchr(reboot_command, '\n');
44 if (p)
45 *p = 0;
46 if (cmd)
47 prom_reboot(cmd);
48 if (*reboot_command)
49 prom_reboot(reboot_command);
50 prom_reboot("");
51 panic("Reboot failed!");
52}
53
diff --git a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c
index e33a8a660e9..2ead310066d 100644
--- a/arch/sparc64/kernel/sbus.c
+++ b/arch/sparc64/kernel/sbus.c
@@ -11,15 +11,17 @@
11#include <linux/slab.h> 11#include <linux/slab.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
14 16
15#include <asm/page.h> 17#include <asm/page.h>
16#include <asm/sbus.h>
17#include <asm/io.h> 18#include <asm/io.h>
18#include <asm/upa.h> 19#include <asm/upa.h>
19#include <asm/cache.h> 20#include <asm/cache.h>
20#include <asm/dma.h> 21#include <asm/dma.h>
21#include <asm/irq.h> 22#include <asm/irq.h>
22#include <asm/prom.h> 23#include <asm/prom.h>
24#include <asm/oplib.h>
23#include <asm/starfire.h> 25#include <asm/starfire.h>
24 26
25#include "iommu_common.h" 27#include "iommu_common.h"
@@ -52,13 +54,23 @@
52#define STRBUF_TAG_VALID 0x02UL 54#define STRBUF_TAG_VALID 0x02UL
53 55
54/* Enable 64-bit DVMA mode for the given device. */ 56/* Enable 64-bit DVMA mode for the given device. */
55void sbus_set_sbus64(struct sbus_dev *sdev, int bursts) 57void sbus_set_sbus64(struct device *dev, int bursts)
56{ 58{
57 struct iommu *iommu = sdev->ofdev.dev.archdata.iommu; 59 struct iommu *iommu = dev->archdata.iommu;
58 int slot = sdev->slot; 60 struct of_device *op = to_of_device(dev);
61 const struct linux_prom_registers *regs;
59 unsigned long cfg_reg; 62 unsigned long cfg_reg;
63 int slot;
60 u64 val; 64 u64 val;
61 65
66 regs = of_get_property(op->node, "reg", NULL);
67 if (!regs) {
68 printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %s\n",
69 op->node->full_name);
70 return;
71 }
72 slot = regs->which_io;
73
62 cfg_reg = iommu->write_complete_reg; 74 cfg_reg = iommu->write_complete_reg;
63 switch (slot) { 75 switch (slot) {
64 case 0: 76 case 0:
@@ -191,10 +203,9 @@ static unsigned long sysio_imap_to_iclr(unsigned long imap)
191 return imap + diff; 203 return imap + diff;
192} 204}
193 205
194unsigned int sbus_build_irq(void *buscookie, unsigned int ino) 206static unsigned int sbus_build_irq(struct of_device *op, unsigned int ino)
195{ 207{
196 struct sbus_bus *sbus = (struct sbus_bus *)buscookie; 208 struct iommu *iommu = op->dev.archdata.iommu;
197 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
198 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 209 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
199 unsigned long imap, iclr; 210 unsigned long imap, iclr;
200 int sbus_level = 0; 211 int sbus_level = 0;
@@ -255,12 +266,12 @@ unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
255#define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ 266#define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
256static irqreturn_t sysio_ue_handler(int irq, void *dev_id) 267static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
257{ 268{
258 struct sbus_bus *sbus = dev_id; 269 struct of_device *op = dev_id;
259 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu; 270 struct iommu *iommu = op->dev.archdata.iommu;
260 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 271 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
261 unsigned long afsr_reg, afar_reg; 272 unsigned long afsr_reg, afar_reg;
262 unsigned long afsr, afar, error_bits; 273 unsigned long afsr, afar, error_bits;
263 int reported; 274 int reported, portid;
264 275
265 afsr_reg = reg_base + SYSIO_UE_AFSR; 276 afsr_reg = reg_base + SYSIO_UE_AFSR;
266 afar_reg = reg_base + SYSIO_UE_AFAR; 277 afar_reg = reg_base + SYSIO_UE_AFAR;
@@ -275,9 +286,11 @@ static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
275 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR); 286 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
276 upa_writeq(error_bits, afsr_reg); 287 upa_writeq(error_bits, afsr_reg);
277 288
289 portid = of_getintprop_default(op->node, "portid", -1);
290
278 /* Log the error. */ 291 /* Log the error. */
279 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n", 292 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
280 sbus->portid, 293 portid,
281 (((error_bits & SYSIO_UEAFSR_PPIO) ? 294 (((error_bits & SYSIO_UEAFSR_PPIO) ?
282 "PIO" : 295 "PIO" :
283 ((error_bits & SYSIO_UEAFSR_PDRD) ? 296 ((error_bits & SYSIO_UEAFSR_PDRD) ?
@@ -285,12 +298,12 @@ static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
285 ((error_bits & SYSIO_UEAFSR_PDWR) ? 298 ((error_bits & SYSIO_UEAFSR_PDWR) ?
286 "DVMA Write" : "???"))))); 299 "DVMA Write" : "???")))));
287 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n", 300 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
288 sbus->portid, 301 portid,
289 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL, 302 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
290 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL, 303 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
291 (afsr & SYSIO_UEAFSR_MID) >> 37UL); 304 (afsr & SYSIO_UEAFSR_MID) >> 37UL);
292 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar); 305 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
293 printk("SYSIO[%x]: Secondary UE errors [", sbus->portid); 306 printk("SYSIO[%x]: Secondary UE errors [", portid);
294 reported = 0; 307 reported = 0;
295 if (afsr & SYSIO_UEAFSR_SPIO) { 308 if (afsr & SYSIO_UEAFSR_SPIO) {
296 reported++; 309 reported++;
@@ -327,12 +340,12 @@ static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
327#define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ 340#define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
328static irqreturn_t sysio_ce_handler(int irq, void *dev_id) 341static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
329{ 342{
330 struct sbus_bus *sbus = dev_id; 343 struct of_device *op = dev_id;
331 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu; 344 struct iommu *iommu = op->dev.archdata.iommu;
332 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 345 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
333 unsigned long afsr_reg, afar_reg; 346 unsigned long afsr_reg, afar_reg;
334 unsigned long afsr, afar, error_bits; 347 unsigned long afsr, afar, error_bits;
335 int reported; 348 int reported, portid;
336 349
337 afsr_reg = reg_base + SYSIO_CE_AFSR; 350 afsr_reg = reg_base + SYSIO_CE_AFSR;
338 afar_reg = reg_base + SYSIO_CE_AFAR; 351 afar_reg = reg_base + SYSIO_CE_AFAR;
@@ -347,8 +360,10 @@ static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
347 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR); 360 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
348 upa_writeq(error_bits, afsr_reg); 361 upa_writeq(error_bits, afsr_reg);
349 362
363 portid = of_getintprop_default(op->node, "portid", -1);
364
350 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n", 365 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
351 sbus->portid, 366 portid,
352 (((error_bits & SYSIO_CEAFSR_PPIO) ? 367 (((error_bits & SYSIO_CEAFSR_PPIO) ?
353 "PIO" : 368 "PIO" :
354 ((error_bits & SYSIO_CEAFSR_PDRD) ? 369 ((error_bits & SYSIO_CEAFSR_PDRD) ?
@@ -360,14 +375,14 @@ static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
360 * XXX UDB CE trap handler does... -DaveM 375 * XXX UDB CE trap handler does... -DaveM
361 */ 376 */
362 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n", 377 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
363 sbus->portid, 378 portid,
364 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL, 379 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
365 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL, 380 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
366 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL, 381 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
367 (afsr & SYSIO_CEAFSR_MID) >> 37UL); 382 (afsr & SYSIO_CEAFSR_MID) >> 37UL);
368 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar); 383 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
369 384
370 printk("SYSIO[%x]: Secondary CE errors [", sbus->portid); 385 printk("SYSIO[%x]: Secondary CE errors [", portid);
371 reported = 0; 386 reported = 0;
372 if (afsr & SYSIO_CEAFSR_SPIO) { 387 if (afsr & SYSIO_CEAFSR_SPIO) {
373 reported++; 388 reported++;
@@ -404,11 +419,11 @@ static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
404#define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */ 419#define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
405static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id) 420static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
406{ 421{
407 struct sbus_bus *sbus = dev_id; 422 struct of_device *op = dev_id;
408 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu; 423 struct iommu *iommu = op->dev.archdata.iommu;
409 unsigned long afsr_reg, afar_reg, reg_base; 424 unsigned long afsr_reg, afar_reg, reg_base;
410 unsigned long afsr, afar, error_bits; 425 unsigned long afsr, afar, error_bits;
411 int reported; 426 int reported, portid;
412 427
413 reg_base = iommu->write_complete_reg - 0x2000UL; 428 reg_base = iommu->write_complete_reg - 0x2000UL;
414 afsr_reg = reg_base + SYSIO_SBUS_AFSR; 429 afsr_reg = reg_base + SYSIO_SBUS_AFSR;
@@ -423,9 +438,11 @@ static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
423 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR); 438 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
424 upa_writeq(error_bits, afsr_reg); 439 upa_writeq(error_bits, afsr_reg);
425 440
441 portid = of_getintprop_default(op->node, "portid", -1);
442
426 /* Log the error. */ 443 /* Log the error. */
427 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n", 444 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
428 sbus->portid, 445 portid,
429 (((error_bits & SYSIO_SBAFSR_PLE) ? 446 (((error_bits & SYSIO_SBAFSR_PLE) ?
430 "Late PIO Error" : 447 "Late PIO Error" :
431 ((error_bits & SYSIO_SBAFSR_PTO) ? 448 ((error_bits & SYSIO_SBAFSR_PTO) ?
@@ -434,11 +451,11 @@ static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
434 "Error Ack" : "???")))), 451 "Error Ack" : "???")))),
435 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0); 452 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
436 printk("SYSIO[%x]: size[%lx] MID[%lx]\n", 453 printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
437 sbus->portid, 454 portid,
438 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL, 455 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
439 (afsr & SYSIO_SBAFSR_MID) >> 37UL); 456 (afsr & SYSIO_SBAFSR_MID) >> 37UL);
440 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar); 457 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
441 printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid); 458 printk("SYSIO[%x]: Secondary SBUS errors [", portid);
442 reported = 0; 459 reported = 0;
443 if (afsr & SYSIO_SBAFSR_SLE) { 460 if (afsr & SYSIO_SBAFSR_SLE) {
444 reported++; 461 reported++;
@@ -470,34 +487,37 @@ static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
470#define SYSIO_CE_INO 0x35 487#define SYSIO_CE_INO 0x35
471#define SYSIO_SBUSERR_INO 0x36 488#define SYSIO_SBUSERR_INO 0x36
472 489
473static void __init sysio_register_error_handlers(struct sbus_bus *sbus) 490static void __init sysio_register_error_handlers(struct of_device *op)
474{ 491{
475 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu; 492 struct iommu *iommu = op->dev.archdata.iommu;
476 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 493 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
477 unsigned int irq; 494 unsigned int irq;
478 u64 control; 495 u64 control;
496 int portid;
497
498 portid = of_getintprop_default(op->node, "portid", -1);
479 499
480 irq = sbus_build_irq(sbus, SYSIO_UE_INO); 500 irq = sbus_build_irq(op, SYSIO_UE_INO);
481 if (request_irq(irq, sysio_ue_handler, 0, 501 if (request_irq(irq, sysio_ue_handler, 0,
482 "SYSIO_UE", sbus) < 0) { 502 "SYSIO_UE", op) < 0) {
483 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n", 503 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
484 sbus->portid); 504 portid);
485 prom_halt(); 505 prom_halt();
486 } 506 }
487 507
488 irq = sbus_build_irq(sbus, SYSIO_CE_INO); 508 irq = sbus_build_irq(op, SYSIO_CE_INO);
489 if (request_irq(irq, sysio_ce_handler, 0, 509 if (request_irq(irq, sysio_ce_handler, 0,
490 "SYSIO_CE", sbus) < 0) { 510 "SYSIO_CE", op) < 0) {
491 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n", 511 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
492 sbus->portid); 512 portid);
493 prom_halt(); 513 prom_halt();
494 } 514 }
495 515
496 irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO); 516 irq = sbus_build_irq(op, SYSIO_SBUSERR_INO);
497 if (request_irq(irq, sysio_sbus_error_handler, 0, 517 if (request_irq(irq, sysio_sbus_error_handler, 0,
498 "SYSIO_SBERR", sbus) < 0) { 518 "SYSIO_SBERR", op) < 0) {
499 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n", 519 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
500 sbus->portid); 520 portid);
501 prom_halt(); 521 prom_halt();
502 } 522 }
503 523
@@ -513,19 +533,15 @@ static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
513} 533}
514 534
515/* Boot time initialization. */ 535/* Boot time initialization. */
516static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus) 536static void __init sbus_iommu_init(struct of_device *op)
517{ 537{
518 const struct linux_prom64_registers *pr; 538 const struct linux_prom64_registers *pr;
519 struct device_node *dp; 539 struct device_node *dp = op->node;
520 struct iommu *iommu; 540 struct iommu *iommu;
521 struct strbuf *strbuf; 541 struct strbuf *strbuf;
522 unsigned long regs, reg_base; 542 unsigned long regs, reg_base;
543 int i, portid;
523 u64 control; 544 u64 control;
524 int i;
525
526 dp = of_find_node_by_phandle(__node);
527
528 sbus->portid = of_getintprop_default(dp, "upa-portid", -1);
529 545
530 pr = of_get_property(dp, "reg", NULL); 546 pr = of_get_property(dp, "reg", NULL);
531 if (!pr) { 547 if (!pr) {
@@ -542,9 +558,9 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
542 if (!strbuf) 558 if (!strbuf)
543 goto fatal_memory_error; 559 goto fatal_memory_error;
544 560
545 sbus->ofdev.dev.archdata.iommu = iommu; 561 op->dev.archdata.iommu = iommu;
546 sbus->ofdev.dev.archdata.stc = strbuf; 562 op->dev.archdata.stc = strbuf;
547 sbus->ofdev.dev.archdata.numa_node = -1; 563 op->dev.archdata.numa_node = -1;
548 564
549 reg_base = regs + SYSIO_IOMMUREG_BASE; 565 reg_base = regs + SYSIO_IOMMUREG_BASE;
550 iommu->iommu_control = reg_base + IOMMU_CONTROL; 566 iommu->iommu_control = reg_base + IOMMU_CONTROL;
@@ -572,8 +588,9 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
572 */ 588 */
573 iommu->write_complete_reg = regs + 0x2000UL; 589 iommu->write_complete_reg = regs + 0x2000UL;
574 590
575 printk("SYSIO: UPA portID %x, at %016lx\n", 591 portid = of_getintprop_default(op->node, "portid", -1);
576 sbus->portid, regs); 592 printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n",
593 portid, regs);
577 594
578 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */ 595 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
579 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1)) 596 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
@@ -631,56 +648,27 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
631 648
632 /* Now some Xfire specific grot... */ 649 /* Now some Xfire specific grot... */
633 if (this_is_starfire) 650 if (this_is_starfire)
634 starfire_hookup(sbus->portid); 651 starfire_hookup(portid);
635 652
636 sysio_register_error_handlers(sbus); 653 sysio_register_error_handlers(op);
637 return; 654 return;
638 655
639fatal_memory_error: 656fatal_memory_error:
640 prom_printf("sbus_iommu_init: Fatal memory allocation error.\n"); 657 prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
641} 658}
642 659
643void sbus_fill_device_irq(struct sbus_dev *sdev) 660static int __init sbus_init(void)
644{ 661{
645 struct device_node *dp = of_find_node_by_phandle(sdev->prom_node); 662 struct device_node *dp;
646 const struct linux_prom_irqs *irqs;
647
648 irqs = of_get_property(dp, "interrupts", NULL);
649 if (!irqs) {
650 sdev->irqs[0] = 0;
651 sdev->num_irqs = 0;
652 } else {
653 unsigned int pri = irqs[0].pri;
654 663
655 sdev->num_irqs = 1; 664 for_each_node_by_name(dp, "sbus") {
656 if (pri < 0x20) 665 struct of_device *op = of_find_device_by_node(dp);
657 pri += sdev->slot * 8;
658 666
659 sdev->irqs[0] = sbus_build_irq(sdev->bus, pri); 667 sbus_iommu_init(op);
668 of_propagate_archdata(op);
660 } 669 }
661}
662 670
663void __init sbus_arch_bus_ranges_init(struct device_node *pn, struct sbus_bus *sbus)
664{
665}
666
667void __init sbus_setup_iommu(struct sbus_bus *sbus, struct device_node *dp)
668{
669 sbus_iommu_init(dp->node, sbus);
670}
671
672void __init sbus_setup_arch_props(struct sbus_bus *sbus, struct device_node *dp)
673{
674}
675
676int __init sbus_arch_preinit(void)
677{
678 return 0; 671 return 0;
679} 672}
680 673
681void __init sbus_arch_postinit(void) 674subsys_initcall(sbus_init);
682{
683 extern void firetruck_init(void);
684
685 firetruck_init();
686}
diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
index 0804f71df6c..30bba8b0a3b 100644
--- a/arch/sparc64/kernel/sparc64_ksyms.c
+++ b/arch/sparc64/kernel/sparc64_ksyms.c
@@ -36,7 +36,6 @@
36#include <asm/elf.h> 36#include <asm/elf.h>
37#include <asm/head.h> 37#include <asm/head.h>
38#include <asm/smp.h> 38#include <asm/smp.h>
39#include <asm/mostek.h>
40#include <asm/ptrace.h> 39#include <asm/ptrace.h>
41#include <asm/uaccess.h> 40#include <asm/uaccess.h>
42#include <asm/checksum.h> 41#include <asm/checksum.h>
@@ -44,12 +43,8 @@
44#include <asm/pgalloc.h> 43#include <asm/pgalloc.h>
45#include <asm/cacheflush.h> 44#include <asm/cacheflush.h>
46#ifdef CONFIG_SBUS 45#ifdef CONFIG_SBUS
47#include <asm/sbus.h>
48#include <asm/dma.h> 46#include <asm/dma.h>
49#endif 47#endif
50#ifdef CONFIG_PCI
51#include <asm/ebus.h>
52#endif
53#include <asm/ns87303.h> 48#include <asm/ns87303.h>
54#include <asm/timer.h> 49#include <asm/timer.h>
55#include <asm/cpudata.h> 50#include <asm/cpudata.h>
@@ -68,7 +63,6 @@ extern void *__memscan_zero(void *, size_t);
68extern void *__memscan_generic(void *, int, size_t); 63extern void *__memscan_generic(void *, int, size_t);
69extern int __memcmp(const void *, const void *, __kernel_size_t); 64extern int __memcmp(const void *, const void *, __kernel_size_t);
70extern __kernel_size_t strlen(const char *); 65extern __kernel_size_t strlen(const char *);
71extern void syscall_trace(struct pt_regs *, int);
72extern void sys_sigsuspend(void); 66extern void sys_sigsuspend(void);
73extern int compat_sys_ioctl(unsigned int fd, unsigned int cmd, u32 arg); 67extern int compat_sys_ioctl(unsigned int fd, unsigned int cmd, u32 arg);
74extern int (*handle_mathemu)(struct pt_regs *, struct fpustate *); 68extern int (*handle_mathemu)(struct pt_regs *, struct fpustate *);
@@ -154,26 +148,12 @@ EXPORT_SYMBOL(flush_dcache_page);
154EXPORT_SYMBOL(__flush_dcache_range); 148EXPORT_SYMBOL(__flush_dcache_range);
155#endif 149#endif
156 150
157EXPORT_SYMBOL(mostek_lock);
158EXPORT_SYMBOL(mstk48t02_regs);
159#ifdef CONFIG_SUN_AUXIO 151#ifdef CONFIG_SUN_AUXIO
160EXPORT_SYMBOL(auxio_set_led); 152EXPORT_SYMBOL(auxio_set_led);
161EXPORT_SYMBOL(auxio_set_lte); 153EXPORT_SYMBOL(auxio_set_lte);
162#endif 154#endif
163#ifdef CONFIG_SBUS 155#ifdef CONFIG_SBUS
164EXPORT_SYMBOL(sbus_root);
165EXPORT_SYMBOL(dma_chain);
166EXPORT_SYMBOL(sbus_set_sbus64); 156EXPORT_SYMBOL(sbus_set_sbus64);
167EXPORT_SYMBOL(sbus_alloc_consistent);
168EXPORT_SYMBOL(sbus_free_consistent);
169EXPORT_SYMBOL(sbus_map_single);
170EXPORT_SYMBOL(sbus_unmap_single);
171EXPORT_SYMBOL(sbus_map_sg);
172EXPORT_SYMBOL(sbus_unmap_sg);
173EXPORT_SYMBOL(sbus_dma_sync_single_for_cpu);
174EXPORT_SYMBOL(sbus_dma_sync_single_for_device);
175EXPORT_SYMBOL(sbus_dma_sync_sg_for_cpu);
176EXPORT_SYMBOL(sbus_dma_sync_sg_for_device);
177#endif 157#endif
178EXPORT_SYMBOL(outsb); 158EXPORT_SYMBOL(outsb);
179EXPORT_SYMBOL(outsw); 159EXPORT_SYMBOL(outsw);
@@ -182,7 +162,6 @@ EXPORT_SYMBOL(insb);
182EXPORT_SYMBOL(insw); 162EXPORT_SYMBOL(insw);
183EXPORT_SYMBOL(insl); 163EXPORT_SYMBOL(insl);
184#ifdef CONFIG_PCI 164#ifdef CONFIG_PCI
185EXPORT_SYMBOL(ebus_chain);
186EXPORT_SYMBOL(pci_alloc_consistent); 165EXPORT_SYMBOL(pci_alloc_consistent);
187EXPORT_SYMBOL(pci_free_consistent); 166EXPORT_SYMBOL(pci_free_consistent);
188EXPORT_SYMBOL(pci_map_single); 167EXPORT_SYMBOL(pci_map_single);
@@ -300,3 +279,5 @@ EXPORT_SYMBOL(xor_niagara_2);
300EXPORT_SYMBOL(xor_niagara_3); 279EXPORT_SYMBOL(xor_niagara_3);
301EXPORT_SYMBOL(xor_niagara_4); 280EXPORT_SYMBOL(xor_niagara_4);
302EXPORT_SYMBOL(xor_niagara_5); 281EXPORT_SYMBOL(xor_niagara_5);
282
283EXPORT_SYMBOL_GPL(real_hard_smp_processor_id);
diff --git a/arch/sparc64/kernel/sstate.c b/arch/sparc64/kernel/sstate.c
index 5b6e75b7f05..8cdbe5946b4 100644
--- a/arch/sparc64/kernel/sstate.c
+++ b/arch/sparc64/kernel/sstate.c
@@ -1,14 +1,15 @@
1/* sstate.c: System soft state support. 1/* sstate.c: System soft state support.
2 * 2 *
3 * Copyright (C) 2007 David S. Miller <davem@davemloft.net> 3 * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net>
4 */ 4 */
5 5
6#include <linux/kernel.h> 6#include <linux/kernel.h>
7#include <linux/notifier.h> 7#include <linux/notifier.h>
8#include <linux/reboot.h>
8#include <linux/init.h> 9#include <linux/init.h>
9 10
10#include <asm/hypervisor.h> 11#include <asm/hypervisor.h>
11#include <asm/sstate.h> 12#include <asm/spitfire.h>
12#include <asm/oplib.h> 13#include <asm/oplib.h>
13#include <asm/head.h> 14#include <asm/head.h>
14#include <asm/io.h> 15#include <asm/io.h>
@@ -50,31 +51,34 @@ static const char rebooting_msg[32] __attribute__((aligned(32))) =
50static const char panicing_msg[32] __attribute__((aligned(32))) = 51static const char panicing_msg[32] __attribute__((aligned(32))) =
51 "Linux panicing"; 52 "Linux panicing";
52 53
53void sstate_booting(void) 54static int sstate_reboot_call(struct notifier_block *np, unsigned long type, void *_unused)
54{ 55{
55 do_set_sstate(HV_SOFT_STATE_TRANSITION, booting_msg); 56 const char *msg;
56}
57 57
58void sstate_running(void) 58 switch (type) {
59{ 59 case SYS_DOWN:
60 do_set_sstate(HV_SOFT_STATE_NORMAL, running_msg); 60 default:
61} 61 msg = rebooting_msg;
62 break;
62 63
63void sstate_halt(void) 64 case SYS_HALT:
64{ 65 msg = halting_msg;
65 do_set_sstate(HV_SOFT_STATE_TRANSITION, halting_msg); 66 break;
66}
67 67
68void sstate_poweroff(void) 68 case SYS_POWER_OFF:
69{ 69 msg = poweroff_msg;
70 do_set_sstate(HV_SOFT_STATE_TRANSITION, poweroff_msg); 70 break;
71} 71 }
72 72
73void sstate_reboot(void) 73 do_set_sstate(HV_SOFT_STATE_TRANSITION, msg);
74{ 74
75 do_set_sstate(HV_SOFT_STATE_TRANSITION, rebooting_msg); 75 return NOTIFY_OK;
76} 76}
77 77
78static struct notifier_block sstate_reboot_notifier = {
79 .notifier_call = sstate_reboot_call,
80};
81
78static int sstate_panic_event(struct notifier_block *n, unsigned long event, void *ptr) 82static int sstate_panic_event(struct notifier_block *n, unsigned long event, void *ptr)
79{ 83{
80 do_set_sstate(HV_SOFT_STATE_TRANSITION, panicing_msg); 84 do_set_sstate(HV_SOFT_STATE_TRANSITION, panicing_msg);
@@ -87,18 +91,37 @@ static struct notifier_block sstate_panic_block = {
87 .priority = INT_MAX, 91 .priority = INT_MAX,
88}; 92};
89 93
90void __init sun4v_sstate_init(void) 94static int __init sstate_init(void)
91{ 95{
92 unsigned long major, minor; 96 unsigned long major, minor;
93 97
98 if (tlb_type != hypervisor)
99 return 0;
100
94 major = 1; 101 major = 1;
95 minor = 0; 102 minor = 0;
96 if (sun4v_hvapi_register(HV_GRP_SOFT_STATE, major, &minor)) 103 if (sun4v_hvapi_register(HV_GRP_SOFT_STATE, major, &minor))
97 return; 104 return 0;
98 105
99 hv_supports_soft_state = 1; 106 hv_supports_soft_state = 1;
100 107
101 prom_sun4v_guest_soft_state(); 108 prom_sun4v_guest_soft_state();
109
110 do_set_sstate(HV_SOFT_STATE_TRANSITION, booting_msg);
111
102 atomic_notifier_chain_register(&panic_notifier_list, 112 atomic_notifier_chain_register(&panic_notifier_list,
103 &sstate_panic_block); 113 &sstate_panic_block);
114 register_reboot_notifier(&sstate_reboot_notifier);
115
116 return 0;
104} 117}
118
119core_initcall(sstate_init);
120
121static int __init sstate_running(void)
122{
123 do_set_sstate(HV_SOFT_STATE_NORMAL, running_msg);
124 return 0;
125}
126
127late_initcall(sstate_running);
diff --git a/arch/sparc64/kernel/starfire.c b/arch/sparc64/kernel/starfire.c
index 7461581b3bb..060d0f3a615 100644
--- a/arch/sparc64/kernel/starfire.c
+++ b/arch/sparc64/kernel/starfire.c
@@ -28,11 +28,6 @@ void check_if_starfire(void)
28 this_is_starfire = 1; 28 this_is_starfire = 1;
29} 29}
30 30
31void starfire_cpu_setup(void)
32{
33 /* Currently, nothing to do. */
34}
35
36int starfire_hard_smp_processor_id(void) 31int starfire_hard_smp_processor_id(void)
37{ 32{
38 return upa_readl(0x1fff40000d0UL); 33 return upa_readl(0x1fff40000d0UL);
diff --git a/arch/sparc64/kernel/sys_sparc32.c b/arch/sparc64/kernel/sys_sparc32.c
index 3d118531baf..3320c9d0075 100644
--- a/arch/sparc64/kernel/sys_sparc32.c
+++ b/arch/sparc64/kernel/sys_sparc32.c
@@ -575,14 +575,6 @@ asmlinkage long sys32_settimeofday(struct compat_timeval __user *tv,
575 return do_sys_settimeofday(tv ? &kts : NULL, tz ? &ktz : NULL); 575 return do_sys_settimeofday(tv ? &kts : NULL, tz ? &ktz : NULL);
576} 576}
577 577
578/* These are here just in case some old sparc32 binary calls it. */
579asmlinkage long sys32_pause(void)
580{
581 current->state = TASK_INTERRUPTIBLE;
582 schedule();
583 return -ERESTARTNOHAND;
584}
585
586asmlinkage compat_ssize_t sys32_pread64(unsigned int fd, 578asmlinkage compat_ssize_t sys32_pread64(unsigned int fd,
587 char __user *ubuf, 579 char __user *ubuf,
588 compat_size_t count, 580 compat_size_t count,
diff --git a/arch/sparc64/kernel/syscalls.S b/arch/sparc64/kernel/syscalls.S
index a2f24270ed8..7a6786a7136 100644
--- a/arch/sparc64/kernel/syscalls.S
+++ b/arch/sparc64/kernel/syscalls.S
@@ -65,9 +65,8 @@ sys32_rt_sigreturn:
65 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0 65 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
66 be,pt %icc, rtrap 66 be,pt %icc, rtrap
67 nop 67 nop
68 add %sp, PTREGS_OFF, %o0 68 call syscall_trace_leave
69 call syscall_trace 69 add %sp, PTREGS_OFF, %o0
70 mov 1, %o1
71 ba,pt %xcc, rtrap 70 ba,pt %xcc, rtrap
72 nop 71 nop
73 72
@@ -159,9 +158,8 @@ linux_sparc_ni_syscall:
159 or %l7, %lo(sys_ni_syscall), %l7 158 or %l7, %lo(sys_ni_syscall), %l7
160 159
161linux_syscall_trace32: 160linux_syscall_trace32:
162 add %sp, PTREGS_OFF, %o0 161 call syscall_trace_enter
163 call syscall_trace 162 add %sp, PTREGS_OFF, %o0
164 clr %o1
165 brnz,pn %o0, 3f 163 brnz,pn %o0, 3f
166 mov -ENOSYS, %o0 164 mov -ENOSYS, %o0
167 srl %i0, 0, %o0 165 srl %i0, 0, %o0
@@ -172,9 +170,8 @@ linux_syscall_trace32:
172 srl %i3, 0, %o3 170 srl %i3, 0, %o3
173 171
174linux_syscall_trace: 172linux_syscall_trace:
175 add %sp, PTREGS_OFF, %o0 173 call syscall_trace_enter
176 call syscall_trace 174 add %sp, PTREGS_OFF, %o0
177 clr %o1
178 brnz,pn %o0, 3f 175 brnz,pn %o0, 3f
179 mov -ENOSYS, %o0 176 mov -ENOSYS, %o0
180 mov %i0, %o0 177 mov %i0, %o0
@@ -275,9 +272,8 @@ ret_sys_call:
275 b,pt %xcc, rtrap 272 b,pt %xcc, rtrap
276 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] 273 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
277linux_syscall_trace2: 274linux_syscall_trace2:
278 add %sp, PTREGS_OFF, %o0 275 call syscall_trace_leave
279 call syscall_trace 276 add %sp, PTREGS_OFF, %o0
280 mov 1, %o1
281 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] 277 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
282 ba,pt %xcc, rtrap 278 ba,pt %xcc, rtrap
283 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] 279 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
diff --git a/arch/sparc64/kernel/systbls.S b/arch/sparc64/kernel/systbls.S
index 0fdbf3ba956..5daee4b04dd 100644
--- a/arch/sparc64/kernel/systbls.S
+++ b/arch/sparc64/kernel/systbls.S
@@ -23,7 +23,7 @@ sys_call_table32:
23/*10*/ .word sys_unlink, sunos_execv, sys_chdir, sys_chown16, sys32_mknod 23/*10*/ .word sys_unlink, sunos_execv, sys_chdir, sys_chown16, sys32_mknod
24/*15*/ .word sys_chmod, sys_lchown16, sparc_brk, sys32_perfctr, sys32_lseek 24/*15*/ .word sys_chmod, sys_lchown16, sparc_brk, sys32_perfctr, sys32_lseek
25/*20*/ .word sys_getpid, sys_capget, sys_capset, sys_setuid16, sys_getuid16 25/*20*/ .word sys_getpid, sys_capget, sys_capset, sys_setuid16, sys_getuid16
26/*25*/ .word sys32_vmsplice, compat_sys_ptrace, sys_alarm, sys32_sigaltstack, sys32_pause 26/*25*/ .word sys32_vmsplice, compat_sys_ptrace, sys_alarm, sys32_sigaltstack, sys_pause
27/*30*/ .word compat_sys_utime, sys_lchown, sys_fchown, sys32_access, sys32_nice 27/*30*/ .word compat_sys_utime, sys_lchown, sys_fchown, sys32_access, sys32_nice
28 .word sys_chown, sys_sync, sys32_kill, compat_sys_newstat, sys32_sendfile 28 .word sys_chown, sys_sync, sys32_kill, compat_sys_newstat, sys32_sendfile
29/*40*/ .word compat_sys_newlstat, sys_dup, sys_pipe, compat_sys_times, sys_getuid 29/*40*/ .word compat_sys_newlstat, sys_dup, sys_pipe, compat_sys_times, sys_getuid
diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c
index cc16fdcf98a..80d71a5ce1e 100644
--- a/arch/sparc64/kernel/time.c
+++ b/arch/sparc64/kernel/time.c
@@ -30,13 +30,14 @@
30#include <linux/percpu.h> 30#include <linux/percpu.h>
31#include <linux/miscdevice.h> 31#include <linux/miscdevice.h>
32#include <linux/rtc.h> 32#include <linux/rtc.h>
33#include <linux/rtc/m48t59.h>
33#include <linux/kernel_stat.h> 34#include <linux/kernel_stat.h>
34#include <linux/clockchips.h> 35#include <linux/clockchips.h>
35#include <linux/clocksource.h> 36#include <linux/clocksource.h>
36#include <linux/of_device.h> 37#include <linux/of_device.h>
38#include <linux/platform_device.h>
37 39
38#include <asm/oplib.h> 40#include <asm/oplib.h>
39#include <asm/mostek.h>
40#include <asm/timer.h> 41#include <asm/timer.h>
41#include <asm/irq.h> 42#include <asm/irq.h>
42#include <asm/io.h> 43#include <asm/io.h>
@@ -50,18 +51,7 @@
50 51
51#include "entry.h" 52#include "entry.h"
52 53
53DEFINE_SPINLOCK(mostek_lock);
54DEFINE_SPINLOCK(rtc_lock); 54DEFINE_SPINLOCK(rtc_lock);
55void __iomem *mstk48t02_regs = NULL;
56#ifdef CONFIG_PCI
57unsigned long ds1287_regs = 0UL;
58static void __iomem *bq4802_regs;
59#endif
60
61static void __iomem *mstk48t08_regs;
62static void __iomem *mstk48t59_regs;
63
64static int set_rtc_mmss(unsigned long);
65 55
66#define TICK_PRIV_BIT (1UL << 63) 56#define TICK_PRIV_BIT (1UL << 63)
67#define TICKCMP_IRQ_BIT (1UL << 63) 57#define TICKCMP_IRQ_BIT (1UL << 63)
@@ -405,313 +395,167 @@ static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
405 395
406int update_persistent_clock(struct timespec now) 396int update_persistent_clock(struct timespec now)
407{ 397{
408 return set_rtc_mmss(now.tv_sec); 398 struct rtc_device *rtc = rtc_class_open("rtc0");
409} 399 int err = -1;
410 400
411/* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */ 401 if (rtc) {
412static void __init kick_start_clock(void) 402 err = rtc_set_mmss(rtc, now.tv_sec);
413{ 403 rtc_class_close(rtc);
414 void __iomem *regs = mstk48t02_regs;
415 u8 sec, tmp;
416 int i, count;
417
418 prom_printf("CLOCK: Clock was stopped. Kick start ");
419
420 spin_lock_irq(&mostek_lock);
421
422 /* Turn on the kick start bit to start the oscillator. */
423 tmp = mostek_read(regs + MOSTEK_CREG);
424 tmp |= MSTK_CREG_WRITE;
425 mostek_write(regs + MOSTEK_CREG, tmp);
426 tmp = mostek_read(regs + MOSTEK_SEC);
427 tmp &= ~MSTK_STOP;
428 mostek_write(regs + MOSTEK_SEC, tmp);
429 tmp = mostek_read(regs + MOSTEK_HOUR);
430 tmp |= MSTK_KICK_START;
431 mostek_write(regs + MOSTEK_HOUR, tmp);
432 tmp = mostek_read(regs + MOSTEK_CREG);
433 tmp &= ~MSTK_CREG_WRITE;
434 mostek_write(regs + MOSTEK_CREG, tmp);
435
436 spin_unlock_irq(&mostek_lock);
437
438 /* Delay to allow the clock oscillator to start. */
439 sec = MSTK_REG_SEC(regs);
440 for (i = 0; i < 3; i++) {
441 while (sec == MSTK_REG_SEC(regs))
442 for (count = 0; count < 100000; count++)
443 /* nothing */ ;
444 prom_printf(".");
445 sec = MSTK_REG_SEC(regs);
446 }
447 prom_printf("\n");
448
449 spin_lock_irq(&mostek_lock);
450
451 /* Turn off kick start and set a "valid" time and date. */
452 tmp = mostek_read(regs + MOSTEK_CREG);
453 tmp |= MSTK_CREG_WRITE;
454 mostek_write(regs + MOSTEK_CREG, tmp);
455 tmp = mostek_read(regs + MOSTEK_HOUR);
456 tmp &= ~MSTK_KICK_START;
457 mostek_write(regs + MOSTEK_HOUR, tmp);
458 MSTK_SET_REG_SEC(regs,0);
459 MSTK_SET_REG_MIN(regs,0);
460 MSTK_SET_REG_HOUR(regs,0);
461 MSTK_SET_REG_DOW(regs,5);
462 MSTK_SET_REG_DOM(regs,1);
463 MSTK_SET_REG_MONTH(regs,8);
464 MSTK_SET_REG_YEAR(regs,1996 - MSTK_YEAR_ZERO);
465 tmp = mostek_read(regs + MOSTEK_CREG);
466 tmp &= ~MSTK_CREG_WRITE;
467 mostek_write(regs + MOSTEK_CREG, tmp);
468
469 spin_unlock_irq(&mostek_lock);
470
471 /* Ensure the kick start bit is off. If it isn't, turn it off. */
472 while (mostek_read(regs + MOSTEK_HOUR) & MSTK_KICK_START) {
473 prom_printf("CLOCK: Kick start still on!\n");
474
475 spin_lock_irq(&mostek_lock);
476
477 tmp = mostek_read(regs + MOSTEK_CREG);
478 tmp |= MSTK_CREG_WRITE;
479 mostek_write(regs + MOSTEK_CREG, tmp);
480
481 tmp = mostek_read(regs + MOSTEK_HOUR);
482 tmp &= ~MSTK_KICK_START;
483 mostek_write(regs + MOSTEK_HOUR, tmp);
484
485 tmp = mostek_read(regs + MOSTEK_CREG);
486 tmp &= ~MSTK_CREG_WRITE;
487 mostek_write(regs + MOSTEK_CREG, tmp);
488
489 spin_unlock_irq(&mostek_lock);
490 } 404 }
491 405
492 prom_printf("CLOCK: Kick start procedure successful.\n"); 406 return err;
493} 407}
494 408
495/* Return nonzero if the clock chip battery is low. */ 409unsigned long cmos_regs;
496static int __init has_low_battery(void) 410EXPORT_SYMBOL(cmos_regs);
497{
498 void __iomem *regs = mstk48t02_regs;
499 u8 data1, data2;
500
501 spin_lock_irq(&mostek_lock);
502 411
503 data1 = mostek_read(regs + MOSTEK_EEPROM); /* Read some data. */ 412static struct resource rtc_cmos_resource;
504 mostek_write(regs + MOSTEK_EEPROM, ~data1); /* Write back the complement. */
505 data2 = mostek_read(regs + MOSTEK_EEPROM); /* Read back the complement. */
506 mostek_write(regs + MOSTEK_EEPROM, data1); /* Restore original value. */
507 413
508 spin_unlock_irq(&mostek_lock); 414static struct platform_device rtc_cmos_device = {
509 415 .name = "rtc_cmos",
510 return (data1 == data2); /* Was the write blocked? */ 416 .id = -1,
511} 417 .resource = &rtc_cmos_resource,
418 .num_resources = 1,
419};
512 420
513static void __init mostek_set_system_time(void __iomem *mregs) 421static int __devinit rtc_probe(struct of_device *op, const struct of_device_id *match)
514{ 422{
515 unsigned int year, mon, day, hour, min, sec; 423 struct resource *r;
516 u8 tmp;
517
518 spin_lock_irq(&mostek_lock);
519 424
520 /* Traditional Mostek chip. */ 425 printk(KERN_INFO "%s: RTC regs at 0x%lx\n",
521 tmp = mostek_read(mregs + MOSTEK_CREG); 426 op->node->full_name, op->resource[0].start);
522 tmp |= MSTK_CREG_READ;
523 mostek_write(mregs + MOSTEK_CREG, tmp);
524 427
525 sec = MSTK_REG_SEC(mregs); 428 /* The CMOS RTC driver only accepts IORESOURCE_IO, so cons
526 min = MSTK_REG_MIN(mregs); 429 * up a fake resource so that the probe works for all cases.
527 hour = MSTK_REG_HOUR(mregs); 430 * When the RTC is behind an ISA bus it will have IORESOURCE_IO
528 day = MSTK_REG_DOM(mregs); 431 * already, whereas when it's behind EBUS is will be IORESOURCE_MEM.
529 mon = MSTK_REG_MONTH(mregs); 432 */
530 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
531
532 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
533 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
534 set_normalized_timespec(&wall_to_monotonic,
535 -xtime.tv_sec, -xtime.tv_nsec);
536 433
537 tmp = mostek_read(mregs + MOSTEK_CREG); 434 r = &rtc_cmos_resource;
538 tmp &= ~MSTK_CREG_READ; 435 r->flags = IORESOURCE_IO;
539 mostek_write(mregs + MOSTEK_CREG, tmp); 436 r->name = op->resource[0].name;
437 r->start = op->resource[0].start;
438 r->end = op->resource[0].end;
540 439
541 spin_unlock_irq(&mostek_lock); 440 cmos_regs = op->resource[0].start;
441 return platform_device_register(&rtc_cmos_device);
542} 442}
543 443
544/* Probe for the real time clock chip. */ 444static struct of_device_id __initdata rtc_match[] = {
545static void __init set_system_time(void) 445 {
546{ 446 .name = "rtc",
547 unsigned int year, mon, day, hour, min, sec; 447 .compatible = "m5819",
548 void __iomem *mregs = mstk48t02_regs; 448 },
549#ifdef CONFIG_PCI 449 {
550 unsigned long dregs = ds1287_regs; 450 .name = "rtc",
551 void __iomem *bregs = bq4802_regs; 451 .compatible = "isa-m5819p",
552#else 452 },
553 unsigned long dregs = 0UL; 453 {
554 void __iomem *bregs = 0UL; 454 .name = "rtc",
555#endif 455 .compatible = "isa-m5823p",
556 456 },
557 if (!mregs && !dregs && !bregs) { 457 {
558 prom_printf("Something wrong, clock regs not mapped yet.\n"); 458 .name = "rtc",
559 prom_halt(); 459 .compatible = "ds1287",
560 } 460 },
561 461 {},
562 if (mregs) { 462};
563 mostek_set_system_time(mregs);
564 return;
565 }
566
567 if (bregs) {
568 unsigned char val = readb(bregs + 0x0e);
569 unsigned int century;
570 463
571 /* BQ4802 RTC chip. */ 464static struct of_platform_driver rtc_driver = {
465 .match_table = rtc_match,
466 .probe = rtc_probe,
467 .driver = {
468 .name = "rtc",
469 },
470};
572 471
573 writeb(val | 0x08, bregs + 0x0e); 472static struct platform_device rtc_bq4802_device = {
473 .name = "rtc-bq4802",
474 .id = -1,
475 .num_resources = 1,
476};
574 477
575 sec = readb(bregs + 0x00); 478static int __devinit bq4802_probe(struct of_device *op, const struct of_device_id *match)
576 min = readb(bregs + 0x02); 479{
577 hour = readb(bregs + 0x04);
578 day = readb(bregs + 0x06);
579 mon = readb(bregs + 0x09);
580 year = readb(bregs + 0x0a);
581 century = readb(bregs + 0x0f);
582 480
583 writeb(val, bregs + 0x0e); 481 printk(KERN_INFO "%s: BQ4802 regs at 0x%lx\n",
482 op->node->full_name, op->resource[0].start);
584 483
585 BCD_TO_BIN(sec); 484 rtc_bq4802_device.resource = &op->resource[0];
586 BCD_TO_BIN(min); 485 return platform_device_register(&rtc_bq4802_device);
587 BCD_TO_BIN(hour); 486}
588 BCD_TO_BIN(day);
589 BCD_TO_BIN(mon);
590 BCD_TO_BIN(year);
591 BCD_TO_BIN(century);
592 487
593 year += (century * 100); 488static struct of_device_id __initdata bq4802_match[] = {
594 } else { 489 {
595 /* Dallas 12887 RTC chip. */ 490 .name = "rtc",
596 491 .compatible = "bq4802",
597 do { 492 },
598 sec = CMOS_READ(RTC_SECONDS); 493};
599 min = CMOS_READ(RTC_MINUTES);
600 hour = CMOS_READ(RTC_HOURS);
601 day = CMOS_READ(RTC_DAY_OF_MONTH);
602 mon = CMOS_READ(RTC_MONTH);
603 year = CMOS_READ(RTC_YEAR);
604 } while (sec != CMOS_READ(RTC_SECONDS));
605
606 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
607 BCD_TO_BIN(sec);
608 BCD_TO_BIN(min);
609 BCD_TO_BIN(hour);
610 BCD_TO_BIN(day);
611 BCD_TO_BIN(mon);
612 BCD_TO_BIN(year);
613 }
614 if ((year += 1900) < 1970)
615 year += 100;
616 }
617 494
618 xtime.tv_sec = mktime(year, mon, day, hour, min, sec); 495static struct of_platform_driver bq4802_driver = {
619 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); 496 .match_table = bq4802_match,
620 set_normalized_timespec(&wall_to_monotonic, 497 .probe = bq4802_probe,
621 -xtime.tv_sec, -xtime.tv_nsec); 498 .driver = {
622} 499 .name = "bq4802",
500 },
501};
623 502
624/* davem suggests we keep this within the 4M locked kernel image */ 503static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
625static u32 starfire_get_time(void)
626{ 504{
627 static char obp_gettod[32]; 505 struct platform_device *pdev = to_platform_device(dev);
628 static u32 unix_tod; 506 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
507 void __iomem *regs;
508 unsigned char val;
629 509
630 sprintf(obp_gettod, "h# %08x unix-gettod", 510 regs = (void __iomem *) pdev->resource[0].start;
631 (unsigned int) (long) &unix_tod); 511 val = readb(regs + ofs);
632 prom_feval(obp_gettod);
633 512
634 return unix_tod; 513 /* the year 0 is 1968 */
514 if (ofs == pdata->offset + M48T59_YEAR) {
515 val += 0x68;
516 if ((val & 0xf) > 9)
517 val += 6;
518 }
519 return val;
635} 520}
636 521
637static int starfire_set_time(u32 val) 522static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
638{ 523{
639 /* Do nothing, time is set using the service processor 524 struct platform_device *pdev = to_platform_device(dev);
640 * console on this platform. 525 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
641 */ 526 void __iomem *regs;
642 return 0;
643}
644 527
645static u32 hypervisor_get_time(void) 528 regs = (void __iomem *) pdev->resource[0].start;
646{ 529 if (ofs == pdata->offset + M48T59_YEAR) {
647 unsigned long ret, time; 530 if (val < 0x68)
648 int retries = 10000; 531 val += 0x32;
649 532 else
650retry: 533 val -= 0x68;
651 ret = sun4v_tod_get(&time); 534 if ((val & 0xf) > 9)
652 if (ret == HV_EOK) 535 val += 6;
653 return time; 536 if ((val & 0xf0) > 0x9A)
654 if (ret == HV_EWOULDBLOCK) { 537 val += 0x60;
655 if (--retries > 0) {
656 udelay(100);
657 goto retry;
658 }
659 printk(KERN_WARNING "SUN4V: tod_get() timed out.\n");
660 return 0;
661 } 538 }
662 printk(KERN_WARNING "SUN4V: tod_get() not supported.\n"); 539 writeb(val, regs + ofs);
663 return 0;
664} 540}
665 541
666static int hypervisor_set_time(u32 secs) 542static struct m48t59_plat_data m48t59_data = {
667{ 543 .read_byte = mostek_read_byte,
668 unsigned long ret; 544 .write_byte = mostek_write_byte,
669 int retries = 10000; 545};
670
671retry:
672 ret = sun4v_tod_set(secs);
673 if (ret == HV_EOK)
674 return 0;
675 if (ret == HV_EWOULDBLOCK) {
676 if (--retries > 0) {
677 udelay(100);
678 goto retry;
679 }
680 printk(KERN_WARNING "SUN4V: tod_set() timed out.\n");
681 return -EAGAIN;
682 }
683 printk(KERN_WARNING "SUN4V: tod_set() not supported.\n");
684 return -EOPNOTSUPP;
685}
686 546
687static int __init clock_model_matches(const char *model) 547static struct platform_device m48t59_rtc = {
688{ 548 .name = "rtc-m48t59",
689 if (strcmp(model, "mk48t02") && 549 .id = 0,
690 strcmp(model, "mk48t08") && 550 .num_resources = 1,
691 strcmp(model, "mk48t59") && 551 .dev = {
692 strcmp(model, "m5819") && 552 .platform_data = &m48t59_data,
693 strcmp(model, "m5819p") && 553 },
694 strcmp(model, "m5823") && 554};
695 strcmp(model, "ds1287") &&
696 strcmp(model, "bq4802"))
697 return 0;
698
699 return 1;
700}
701 555
702static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match) 556static int __devinit mostek_probe(struct of_device *op, const struct of_device_id *match)
703{ 557{
704 struct device_node *dp = op->node; 558 struct device_node *dp = op->node;
705 const char *model = of_get_property(dp, "model", NULL);
706 const char *compat = of_get_property(dp, "compatible", NULL);
707 unsigned long size, flags;
708 void __iomem *regs;
709
710 if (!model)
711 model = compat;
712
713 if (!model || !clock_model_matches(model))
714 return -ENODEV;
715 559
716 /* On an Enterprise system there can be multiple mostek clocks. 560 /* On an Enterprise system there can be multiple mostek clocks.
717 * We should only match the one that is on the central FHC bus. 561 * We should only match the one that is on the central FHC bus.
@@ -720,88 +564,51 @@ static int __devinit clock_probe(struct of_device *op, const struct of_device_id
720 strcmp(dp->parent->parent->name, "central") != 0) 564 strcmp(dp->parent->parent->name, "central") != 0)
721 return -ENODEV; 565 return -ENODEV;
722 566
723 size = (op->resource[0].end - op->resource[0].start) + 1; 567 printk(KERN_INFO "%s: Mostek regs at 0x%lx\n",
724 regs = of_ioremap(&op->resource[0], 0, size, "clock"); 568 dp->full_name, op->resource[0].start);
725 if (!regs)
726 return -ENOMEM;
727
728#ifdef CONFIG_PCI
729 if (!strcmp(model, "ds1287") ||
730 !strcmp(model, "m5819") ||
731 !strcmp(model, "m5819p") ||
732 !strcmp(model, "m5823")) {
733 ds1287_regs = (unsigned long) regs;
734 } else if (!strcmp(model, "bq4802")) {
735 bq4802_regs = regs;
736 } else
737#endif
738 if (model[5] == '0' && model[6] == '2') {
739 mstk48t02_regs = regs;
740 } else if(model[5] == '0' && model[6] == '8') {
741 mstk48t08_regs = regs;
742 mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
743 } else {
744 mstk48t59_regs = regs;
745 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
746 }
747
748 printk(KERN_INFO "%s: Clock regs at %p\n", dp->full_name, regs);
749
750 local_irq_save(flags);
751
752 if (mstk48t02_regs != NULL) {
753 /* Report a low battery voltage condition. */
754 if (has_low_battery())
755 prom_printf("NVRAM: Low battery voltage!\n");
756
757 /* Kick start the clock if it is completely stopped. */
758 if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
759 kick_start_clock();
760 }
761
762 set_system_time();
763
764 local_irq_restore(flags);
765 569
766 return 0; 570 m48t59_rtc.resource = &op->resource[0];
571 return platform_device_register(&m48t59_rtc);
767} 572}
768 573
769static struct of_device_id clock_match[] = { 574static struct of_device_id __initdata mostek_match[] = {
770 { 575 {
771 .name = "eeprom", 576 .name = "eeprom",
772 }, 577 },
773 {
774 .name = "rtc",
775 },
776 {}, 578 {},
777}; 579};
778 580
779static struct of_platform_driver clock_driver = { 581static struct of_platform_driver mostek_driver = {
780 .match_table = clock_match, 582 .match_table = mostek_match,
781 .probe = clock_probe, 583 .probe = mostek_probe,
782 .driver = { 584 .driver = {
783 .name = "clock", 585 .name = "mostek",
784 }, 586 },
785}; 587};
786 588
589static struct platform_device rtc_sun4v_device = {
590 .name = "rtc-sun4v",
591 .id = -1,
592};
593
594static struct platform_device rtc_starfire_device = {
595 .name = "rtc-starfire",
596 .id = -1,
597};
598
787static int __init clock_init(void) 599static int __init clock_init(void)
788{ 600{
789 if (this_is_starfire) { 601 if (this_is_starfire)
790 xtime.tv_sec = starfire_get_time(); 602 return platform_device_register(&rtc_starfire_device);
791 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); 603
792 set_normalized_timespec(&wall_to_monotonic, 604 if (tlb_type == hypervisor)
793 -xtime.tv_sec, -xtime.tv_nsec); 605 return platform_device_register(&rtc_sun4v_device);
794 return 0; 606
795 } 607 (void) of_register_driver(&rtc_driver, &of_platform_bus_type);
796 if (tlb_type == hypervisor) { 608 (void) of_register_driver(&mostek_driver, &of_platform_bus_type);
797 xtime.tv_sec = hypervisor_get_time(); 609 (void) of_register_driver(&bq4802_driver, &of_platform_bus_type);
798 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
799 set_normalized_timespec(&wall_to_monotonic,
800 -xtime.tv_sec, -xtime.tv_nsec);
801 return 0;
802 }
803 610
804 return of_register_driver(&clock_driver, &of_platform_bus_type); 611 return 0;
805} 612}
806 613
807/* Must be after subsys_initcall() so that busses are probed. Must 614/* Must be after subsys_initcall() so that busses are probed. Must
@@ -814,7 +621,7 @@ fs_initcall(clock_init);
814static unsigned long sparc64_init_timers(void) 621static unsigned long sparc64_init_timers(void)
815{ 622{
816 struct device_node *dp; 623 struct device_node *dp;
817 unsigned long clock; 624 unsigned long freq;
818 625
819 dp = of_find_node_by_path("/"); 626 dp = of_find_node_by_path("/");
820 if (tlb_type == spitfire) { 627 if (tlb_type == spitfire) {
@@ -827,17 +634,17 @@ static unsigned long sparc64_init_timers(void)
827 if (manuf == 0x17 && impl == 0x13) { 634 if (manuf == 0x17 && impl == 0x13) {
828 /* Hummingbird, aka Ultra-IIe */ 635 /* Hummingbird, aka Ultra-IIe */
829 tick_ops = &hbtick_operations; 636 tick_ops = &hbtick_operations;
830 clock = of_getintprop_default(dp, "stick-frequency", 0); 637 freq = of_getintprop_default(dp, "stick-frequency", 0);
831 } else { 638 } else {
832 tick_ops = &tick_operations; 639 tick_ops = &tick_operations;
833 clock = local_cpu_data().clock_tick; 640 freq = local_cpu_data().clock_tick;
834 } 641 }
835 } else { 642 } else {
836 tick_ops = &stick_operations; 643 tick_ops = &stick_operations;
837 clock = of_getintprop_default(dp, "stick-frequency", 0); 644 freq = of_getintprop_default(dp, "stick-frequency", 0);
838 } 645 }
839 646
840 return clock; 647 return freq;
841} 648}
842 649
843struct freq_table { 650struct freq_table {
@@ -1029,16 +836,16 @@ EXPORT_SYMBOL(udelay);
1029 836
1030void __init time_init(void) 837void __init time_init(void)
1031{ 838{
1032 unsigned long clock = sparc64_init_timers(); 839 unsigned long freq = sparc64_init_timers();
1033 840
1034 tb_ticks_per_usec = clock / USEC_PER_SEC; 841 tb_ticks_per_usec = freq / USEC_PER_SEC;
1035 842
1036 timer_ticks_per_nsec_quotient = 843 timer_ticks_per_nsec_quotient =
1037 clocksource_hz2mult(clock, SPARC64_NSEC_PER_CYC_SHIFT); 844 clocksource_hz2mult(freq, SPARC64_NSEC_PER_CYC_SHIFT);
1038 845
1039 clocksource_tick.name = tick_ops->name; 846 clocksource_tick.name = tick_ops->name;
1040 clocksource_tick.mult = 847 clocksource_tick.mult =
1041 clocksource_hz2mult(clock, 848 clocksource_hz2mult(freq,
1042 clocksource_tick.shift); 849 clocksource_tick.shift);
1043 clocksource_tick.read = tick_ops->get_tick; 850 clocksource_tick.read = tick_ops->get_tick;
1044 851
@@ -1049,7 +856,7 @@ void __init time_init(void)
1049 856
1050 sparc64_clockevent.name = tick_ops->name; 857 sparc64_clockevent.name = tick_ops->name;
1051 858
1052 setup_clockevent_multiplier(clock); 859 setup_clockevent_multiplier(freq);
1053 860
1054 sparc64_clockevent.max_delta_ns = 861 sparc64_clockevent.max_delta_ns =
1055 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent); 862 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent);
@@ -1070,672 +877,8 @@ unsigned long long sched_clock(void)
1070 >> SPARC64_NSEC_PER_CYC_SHIFT; 877 >> SPARC64_NSEC_PER_CYC_SHIFT;
1071} 878}
1072 879
1073static int set_rtc_mmss(unsigned long nowtime)
1074{
1075 int real_seconds, real_minutes, chip_minutes;
1076 void __iomem *mregs = mstk48t02_regs;
1077#ifdef CONFIG_PCI
1078 unsigned long dregs = ds1287_regs;
1079 void __iomem *bregs = bq4802_regs;
1080#else
1081 unsigned long dregs = 0UL;
1082 void __iomem *bregs = 0UL;
1083#endif
1084 unsigned long flags;
1085 u8 tmp;
1086
1087 /*
1088 * Not having a register set can lead to trouble.
1089 * Also starfire doesn't have a tod clock.
1090 */
1091 if (!mregs && !dregs && !bregs)
1092 return -1;
1093
1094 if (mregs) {
1095 spin_lock_irqsave(&mostek_lock, flags);
1096
1097 /* Read the current RTC minutes. */
1098 tmp = mostek_read(mregs + MOSTEK_CREG);
1099 tmp |= MSTK_CREG_READ;
1100 mostek_write(mregs + MOSTEK_CREG, tmp);
1101
1102 chip_minutes = MSTK_REG_MIN(mregs);
1103
1104 tmp = mostek_read(mregs + MOSTEK_CREG);
1105 tmp &= ~MSTK_CREG_READ;
1106 mostek_write(mregs + MOSTEK_CREG, tmp);
1107
1108 /*
1109 * since we're only adjusting minutes and seconds,
1110 * don't interfere with hour overflow. This avoids
1111 * messing with unknown time zones but requires your
1112 * RTC not to be off by more than 15 minutes
1113 */
1114 real_seconds = nowtime % 60;
1115 real_minutes = nowtime / 60;
1116 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1117 real_minutes += 30; /* correct for half hour time zone */
1118 real_minutes %= 60;
1119
1120 if (abs(real_minutes - chip_minutes) < 30) {
1121 tmp = mostek_read(mregs + MOSTEK_CREG);
1122 tmp |= MSTK_CREG_WRITE;
1123 mostek_write(mregs + MOSTEK_CREG, tmp);
1124
1125 MSTK_SET_REG_SEC(mregs,real_seconds);
1126 MSTK_SET_REG_MIN(mregs,real_minutes);
1127
1128 tmp = mostek_read(mregs + MOSTEK_CREG);
1129 tmp &= ~MSTK_CREG_WRITE;
1130 mostek_write(mregs + MOSTEK_CREG, tmp);
1131
1132 spin_unlock_irqrestore(&mostek_lock, flags);
1133
1134 return 0;
1135 } else {
1136 spin_unlock_irqrestore(&mostek_lock, flags);
1137
1138 return -1;
1139 }
1140 } else if (bregs) {
1141 int retval = 0;
1142 unsigned char val = readb(bregs + 0x0e);
1143
1144 /* BQ4802 RTC chip. */
1145
1146 writeb(val | 0x08, bregs + 0x0e);
1147
1148 chip_minutes = readb(bregs + 0x02);
1149 BCD_TO_BIN(chip_minutes);
1150 real_seconds = nowtime % 60;
1151 real_minutes = nowtime / 60;
1152 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1153 real_minutes += 30;
1154 real_minutes %= 60;
1155
1156 if (abs(real_minutes - chip_minutes) < 30) {
1157 BIN_TO_BCD(real_seconds);
1158 BIN_TO_BCD(real_minutes);
1159 writeb(real_seconds, bregs + 0x00);
1160 writeb(real_minutes, bregs + 0x02);
1161 } else {
1162 printk(KERN_WARNING
1163 "set_rtc_mmss: can't update from %d to %d\n",
1164 chip_minutes, real_minutes);
1165 retval = -1;
1166 }
1167
1168 writeb(val, bregs + 0x0e);
1169
1170 return retval;
1171 } else {
1172 int retval = 0;
1173 unsigned char save_control, save_freq_select;
1174
1175 /* Stolen from arch/i386/kernel/time.c, see there for
1176 * credits and descriptive comments.
1177 */
1178 spin_lock_irqsave(&rtc_lock, flags);
1179 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
1180 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1181
1182 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
1183 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1184
1185 chip_minutes = CMOS_READ(RTC_MINUTES);
1186 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
1187 BCD_TO_BIN(chip_minutes);
1188 real_seconds = nowtime % 60;
1189 real_minutes = nowtime / 60;
1190 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1191 real_minutes += 30;
1192 real_minutes %= 60;
1193
1194 if (abs(real_minutes - chip_minutes) < 30) {
1195 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1196 BIN_TO_BCD(real_seconds);
1197 BIN_TO_BCD(real_minutes);
1198 }
1199 CMOS_WRITE(real_seconds,RTC_SECONDS);
1200 CMOS_WRITE(real_minutes,RTC_MINUTES);
1201 } else {
1202 printk(KERN_WARNING
1203 "set_rtc_mmss: can't update from %d to %d\n",
1204 chip_minutes, real_minutes);
1205 retval = -1;
1206 }
1207
1208 CMOS_WRITE(save_control, RTC_CONTROL);
1209 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1210 spin_unlock_irqrestore(&rtc_lock, flags);
1211
1212 return retval;
1213 }
1214}
1215
1216#define RTC_IS_OPEN 0x01 /* means /dev/rtc is in use */
1217static unsigned char mini_rtc_status; /* bitmapped status byte. */
1218
1219#define FEBRUARY 2
1220#define STARTOFTIME 1970
1221#define SECDAY 86400L
1222#define SECYR (SECDAY * 365)
1223#define leapyear(year) ((year) % 4 == 0 && \
1224 ((year) % 100 != 0 || (year) % 400 == 0))
1225#define days_in_year(a) (leapyear(a) ? 366 : 365)
1226#define days_in_month(a) (month_days[(a) - 1])
1227
1228static int month_days[12] = {
1229 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
1230};
1231
1232/*
1233 * This only works for the Gregorian calendar - i.e. after 1752 (in the UK)
1234 */
1235static void GregorianDay(struct rtc_time * tm)
1236{
1237 int leapsToDate;
1238 int lastYear;
1239 int day;
1240 int MonthOffset[] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 };
1241
1242 lastYear = tm->tm_year - 1;
1243
1244 /*
1245 * Number of leap corrections to apply up to end of last year
1246 */
1247 leapsToDate = lastYear / 4 - lastYear / 100 + lastYear / 400;
1248
1249 /*
1250 * This year is a leap year if it is divisible by 4 except when it is
1251 * divisible by 100 unless it is divisible by 400
1252 *
1253 * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 was
1254 */
1255 day = tm->tm_mon > 2 && leapyear(tm->tm_year);
1256
1257 day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] +
1258 tm->tm_mday;
1259
1260 tm->tm_wday = day % 7;
1261}
1262
1263static void to_tm(int tim, struct rtc_time *tm)
1264{
1265 register int i;
1266 register long hms, day;
1267
1268 day = tim / SECDAY;
1269 hms = tim % SECDAY;
1270
1271 /* Hours, minutes, seconds are easy */
1272 tm->tm_hour = hms / 3600;
1273 tm->tm_min = (hms % 3600) / 60;
1274 tm->tm_sec = (hms % 3600) % 60;
1275
1276 /* Number of years in days */
1277 for (i = STARTOFTIME; day >= days_in_year(i); i++)
1278 day -= days_in_year(i);
1279 tm->tm_year = i;
1280
1281 /* Number of months in days left */
1282 if (leapyear(tm->tm_year))
1283 days_in_month(FEBRUARY) = 29;
1284 for (i = 1; day >= days_in_month(i); i++)
1285 day -= days_in_month(i);
1286 days_in_month(FEBRUARY) = 28;
1287 tm->tm_mon = i;
1288
1289 /* Days are what is left over (+1) from all that. */
1290 tm->tm_mday = day + 1;
1291
1292 /*
1293 * Determine the day of week
1294 */
1295 GregorianDay(tm);
1296}
1297
1298/* Both Starfire and SUN4V give us seconds since Jan 1st, 1970,
1299 * aka Unix time. So we have to convert to/from rtc_time.
1300 */
1301static void starfire_get_rtc_time(struct rtc_time *time)
1302{
1303 u32 seconds = starfire_get_time();
1304
1305 to_tm(seconds, time);
1306 time->tm_year -= 1900;
1307 time->tm_mon -= 1;
1308}
1309
1310static int starfire_set_rtc_time(struct rtc_time *time)
1311{
1312 u32 seconds = mktime(time->tm_year + 1900, time->tm_mon + 1,
1313 time->tm_mday, time->tm_hour,
1314 time->tm_min, time->tm_sec);
1315
1316 return starfire_set_time(seconds);
1317}
1318
1319static void hypervisor_get_rtc_time(struct rtc_time *time)
1320{
1321 u32 seconds = hypervisor_get_time();
1322
1323 to_tm(seconds, time);
1324 time->tm_year -= 1900;
1325 time->tm_mon -= 1;
1326}
1327
1328static int hypervisor_set_rtc_time(struct rtc_time *time)
1329{
1330 u32 seconds = mktime(time->tm_year + 1900, time->tm_mon + 1,
1331 time->tm_mday, time->tm_hour,
1332 time->tm_min, time->tm_sec);
1333
1334 return hypervisor_set_time(seconds);
1335}
1336
1337#ifdef CONFIG_PCI
1338static void bq4802_get_rtc_time(struct rtc_time *time)
1339{
1340 unsigned char val = readb(bq4802_regs + 0x0e);
1341 unsigned int century;
1342
1343 writeb(val | 0x08, bq4802_regs + 0x0e);
1344
1345 time->tm_sec = readb(bq4802_regs + 0x00);
1346 time->tm_min = readb(bq4802_regs + 0x02);
1347 time->tm_hour = readb(bq4802_regs + 0x04);
1348 time->tm_mday = readb(bq4802_regs + 0x06);
1349 time->tm_mon = readb(bq4802_regs + 0x09);
1350 time->tm_year = readb(bq4802_regs + 0x0a);
1351 time->tm_wday = readb(bq4802_regs + 0x08);
1352 century = readb(bq4802_regs + 0x0f);
1353
1354 writeb(val, bq4802_regs + 0x0e);
1355
1356 BCD_TO_BIN(time->tm_sec);
1357 BCD_TO_BIN(time->tm_min);
1358 BCD_TO_BIN(time->tm_hour);
1359 BCD_TO_BIN(time->tm_mday);
1360 BCD_TO_BIN(time->tm_mon);
1361 BCD_TO_BIN(time->tm_year);
1362 BCD_TO_BIN(time->tm_wday);
1363 BCD_TO_BIN(century);
1364
1365 time->tm_year += (century * 100);
1366 time->tm_year -= 1900;
1367
1368 time->tm_mon--;
1369}
1370
1371static int bq4802_set_rtc_time(struct rtc_time *time)
1372{
1373 unsigned char val = readb(bq4802_regs + 0x0e);
1374 unsigned char sec, min, hrs, day, mon, yrs, century;
1375 unsigned int year;
1376
1377 year = time->tm_year + 1900;
1378 century = year / 100;
1379 yrs = year % 100;
1380
1381 mon = time->tm_mon + 1; /* tm_mon starts at zero */
1382 day = time->tm_mday;
1383 hrs = time->tm_hour;
1384 min = time->tm_min;
1385 sec = time->tm_sec;
1386
1387 BIN_TO_BCD(sec);
1388 BIN_TO_BCD(min);
1389 BIN_TO_BCD(hrs);
1390 BIN_TO_BCD(day);
1391 BIN_TO_BCD(mon);
1392 BIN_TO_BCD(yrs);
1393 BIN_TO_BCD(century);
1394
1395 writeb(val | 0x08, bq4802_regs + 0x0e);
1396
1397 writeb(sec, bq4802_regs + 0x00);
1398 writeb(min, bq4802_regs + 0x02);
1399 writeb(hrs, bq4802_regs + 0x04);
1400 writeb(day, bq4802_regs + 0x06);
1401 writeb(mon, bq4802_regs + 0x09);
1402 writeb(yrs, bq4802_regs + 0x0a);
1403 writeb(century, bq4802_regs + 0x0f);
1404
1405 writeb(val, bq4802_regs + 0x0e);
1406
1407 return 0;
1408}
1409
1410static void cmos_get_rtc_time(struct rtc_time *rtc_tm)
1411{
1412 unsigned char ctrl;
1413
1414 rtc_tm->tm_sec = CMOS_READ(RTC_SECONDS);
1415 rtc_tm->tm_min = CMOS_READ(RTC_MINUTES);
1416 rtc_tm->tm_hour = CMOS_READ(RTC_HOURS);
1417 rtc_tm->tm_mday = CMOS_READ(RTC_DAY_OF_MONTH);
1418 rtc_tm->tm_mon = CMOS_READ(RTC_MONTH);
1419 rtc_tm->tm_year = CMOS_READ(RTC_YEAR);
1420 rtc_tm->tm_wday = CMOS_READ(RTC_DAY_OF_WEEK);
1421
1422 ctrl = CMOS_READ(RTC_CONTROL);
1423 if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1424 BCD_TO_BIN(rtc_tm->tm_sec);
1425 BCD_TO_BIN(rtc_tm->tm_min);
1426 BCD_TO_BIN(rtc_tm->tm_hour);
1427 BCD_TO_BIN(rtc_tm->tm_mday);
1428 BCD_TO_BIN(rtc_tm->tm_mon);
1429 BCD_TO_BIN(rtc_tm->tm_year);
1430 BCD_TO_BIN(rtc_tm->tm_wday);
1431 }
1432
1433 if (rtc_tm->tm_year <= 69)
1434 rtc_tm->tm_year += 100;
1435
1436 rtc_tm->tm_mon--;
1437}
1438
1439static int cmos_set_rtc_time(struct rtc_time *rtc_tm)
1440{
1441 unsigned char mon, day, hrs, min, sec;
1442 unsigned char save_control, save_freq_select;
1443 unsigned int yrs;
1444
1445 yrs = rtc_tm->tm_year;
1446 mon = rtc_tm->tm_mon + 1;
1447 day = rtc_tm->tm_mday;
1448 hrs = rtc_tm->tm_hour;
1449 min = rtc_tm->tm_min;
1450 sec = rtc_tm->tm_sec;
1451
1452 if (yrs >= 100)
1453 yrs -= 100;
1454
1455 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1456 BIN_TO_BCD(sec);
1457 BIN_TO_BCD(min);
1458 BIN_TO_BCD(hrs);
1459 BIN_TO_BCD(day);
1460 BIN_TO_BCD(mon);
1461 BIN_TO_BCD(yrs);
1462 }
1463
1464 save_control = CMOS_READ(RTC_CONTROL);
1465 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1466 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1467 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1468
1469 CMOS_WRITE(yrs, RTC_YEAR);
1470 CMOS_WRITE(mon, RTC_MONTH);
1471 CMOS_WRITE(day, RTC_DAY_OF_MONTH);
1472 CMOS_WRITE(hrs, RTC_HOURS);
1473 CMOS_WRITE(min, RTC_MINUTES);
1474 CMOS_WRITE(sec, RTC_SECONDS);
1475
1476 CMOS_WRITE(save_control, RTC_CONTROL);
1477 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1478
1479 return 0;
1480}
1481#endif /* CONFIG_PCI */
1482
1483static void mostek_get_rtc_time(struct rtc_time *rtc_tm)
1484{
1485 void __iomem *regs = mstk48t02_regs;
1486 u8 tmp;
1487
1488 spin_lock_irq(&mostek_lock);
1489
1490 tmp = mostek_read(regs + MOSTEK_CREG);
1491 tmp |= MSTK_CREG_READ;
1492 mostek_write(regs + MOSTEK_CREG, tmp);
1493
1494 rtc_tm->tm_sec = MSTK_REG_SEC(regs);
1495 rtc_tm->tm_min = MSTK_REG_MIN(regs);
1496 rtc_tm->tm_hour = MSTK_REG_HOUR(regs);
1497 rtc_tm->tm_mday = MSTK_REG_DOM(regs);
1498 rtc_tm->tm_mon = MSTK_REG_MONTH(regs);
1499 rtc_tm->tm_year = MSTK_CVT_YEAR( MSTK_REG_YEAR(regs) );
1500 rtc_tm->tm_wday = MSTK_REG_DOW(regs);
1501
1502 tmp = mostek_read(regs + MOSTEK_CREG);
1503 tmp &= ~MSTK_CREG_READ;
1504 mostek_write(regs + MOSTEK_CREG, tmp);
1505
1506 spin_unlock_irq(&mostek_lock);
1507
1508 rtc_tm->tm_mon--;
1509 rtc_tm->tm_wday--;
1510 rtc_tm->tm_year -= 1900;
1511}
1512
1513static int mostek_set_rtc_time(struct rtc_time *rtc_tm)
1514{
1515 unsigned char mon, day, hrs, min, sec, wday;
1516 void __iomem *regs = mstk48t02_regs;
1517 unsigned int yrs;
1518 u8 tmp;
1519
1520 yrs = rtc_tm->tm_year + 1900;
1521 mon = rtc_tm->tm_mon + 1;
1522 day = rtc_tm->tm_mday;
1523 wday = rtc_tm->tm_wday + 1;
1524 hrs = rtc_tm->tm_hour;
1525 min = rtc_tm->tm_min;
1526 sec = rtc_tm->tm_sec;
1527
1528 spin_lock_irq(&mostek_lock);
1529
1530 tmp = mostek_read(regs + MOSTEK_CREG);
1531 tmp |= MSTK_CREG_WRITE;
1532 mostek_write(regs + MOSTEK_CREG, tmp);
1533
1534 MSTK_SET_REG_SEC(regs, sec);
1535 MSTK_SET_REG_MIN(regs, min);
1536 MSTK_SET_REG_HOUR(regs, hrs);
1537 MSTK_SET_REG_DOW(regs, wday);
1538 MSTK_SET_REG_DOM(regs, day);
1539 MSTK_SET_REG_MONTH(regs, mon);
1540 MSTK_SET_REG_YEAR(regs, yrs - MSTK_YEAR_ZERO);
1541
1542 tmp = mostek_read(regs + MOSTEK_CREG);
1543 tmp &= ~MSTK_CREG_WRITE;
1544 mostek_write(regs + MOSTEK_CREG, tmp);
1545
1546 spin_unlock_irq(&mostek_lock);
1547
1548 return 0;
1549}
1550
1551struct mini_rtc_ops {
1552 void (*get_rtc_time)(struct rtc_time *);
1553 int (*set_rtc_time)(struct rtc_time *);
1554};
1555
1556static struct mini_rtc_ops starfire_rtc_ops = {
1557 .get_rtc_time = starfire_get_rtc_time,
1558 .set_rtc_time = starfire_set_rtc_time,
1559};
1560
1561static struct mini_rtc_ops hypervisor_rtc_ops = {
1562 .get_rtc_time = hypervisor_get_rtc_time,
1563 .set_rtc_time = hypervisor_set_rtc_time,
1564};
1565
1566#ifdef CONFIG_PCI
1567static struct mini_rtc_ops bq4802_rtc_ops = {
1568 .get_rtc_time = bq4802_get_rtc_time,
1569 .set_rtc_time = bq4802_set_rtc_time,
1570};
1571
1572static struct mini_rtc_ops cmos_rtc_ops = {
1573 .get_rtc_time = cmos_get_rtc_time,
1574 .set_rtc_time = cmos_set_rtc_time,
1575};
1576#endif /* CONFIG_PCI */
1577
1578static struct mini_rtc_ops mostek_rtc_ops = {
1579 .get_rtc_time = mostek_get_rtc_time,
1580 .set_rtc_time = mostek_set_rtc_time,
1581};
1582
1583static struct mini_rtc_ops *mini_rtc_ops;
1584
1585static inline void mini_get_rtc_time(struct rtc_time *time)
1586{
1587 unsigned long flags;
1588
1589 spin_lock_irqsave(&rtc_lock, flags);
1590 mini_rtc_ops->get_rtc_time(time);
1591 spin_unlock_irqrestore(&rtc_lock, flags);
1592}
1593
1594static inline int mini_set_rtc_time(struct rtc_time *time)
1595{
1596 unsigned long flags;
1597 int err;
1598
1599 spin_lock_irqsave(&rtc_lock, flags);
1600 err = mini_rtc_ops->set_rtc_time(time);
1601 spin_unlock_irqrestore(&rtc_lock, flags);
1602
1603 return err;
1604}
1605
1606static int mini_rtc_ioctl(struct inode *inode, struct file *file,
1607 unsigned int cmd, unsigned long arg)
1608{
1609 struct rtc_time wtime;
1610 void __user *argp = (void __user *)arg;
1611
1612 switch (cmd) {
1613
1614 case RTC_PLL_GET:
1615 return -EINVAL;
1616
1617 case RTC_PLL_SET:
1618 return -EINVAL;
1619
1620 case RTC_UIE_OFF: /* disable ints from RTC updates. */
1621 return 0;
1622
1623 case RTC_UIE_ON: /* enable ints for RTC updates. */
1624 return -EINVAL;
1625
1626 case RTC_RD_TIME: /* Read the time/date from RTC */
1627 /* this doesn't get week-day, who cares */
1628 memset(&wtime, 0, sizeof(wtime));
1629 mini_get_rtc_time(&wtime);
1630
1631 return copy_to_user(argp, &wtime, sizeof(wtime)) ? -EFAULT : 0;
1632
1633 case RTC_SET_TIME: /* Set the RTC */
1634 {
1635 int year, days;
1636
1637 if (!capable(CAP_SYS_TIME))
1638 return -EACCES;
1639
1640 if (copy_from_user(&wtime, argp, sizeof(wtime)))
1641 return -EFAULT;
1642
1643 year = wtime.tm_year + 1900;
1644 days = month_days[wtime.tm_mon] +
1645 ((wtime.tm_mon == 1) && leapyear(year));
1646
1647 if ((wtime.tm_mon < 0 || wtime.tm_mon > 11) ||
1648 (wtime.tm_mday < 1))
1649 return -EINVAL;
1650
1651 if (wtime.tm_mday < 0 || wtime.tm_mday > days)
1652 return -EINVAL;
1653
1654 if (wtime.tm_hour < 0 || wtime.tm_hour >= 24 ||
1655 wtime.tm_min < 0 || wtime.tm_min >= 60 ||
1656 wtime.tm_sec < 0 || wtime.tm_sec >= 60)
1657 return -EINVAL;
1658
1659 return mini_set_rtc_time(&wtime);
1660 }
1661 }
1662
1663 return -EINVAL;
1664}
1665
1666static int mini_rtc_open(struct inode *inode, struct file *file)
1667{
1668 lock_kernel();
1669 if (mini_rtc_status & RTC_IS_OPEN) {
1670 unlock_kernel();
1671 return -EBUSY;
1672 }
1673
1674 mini_rtc_status |= RTC_IS_OPEN;
1675 unlock_kernel();
1676
1677 return 0;
1678}
1679
1680static int mini_rtc_release(struct inode *inode, struct file *file)
1681{
1682 mini_rtc_status &= ~RTC_IS_OPEN;
1683 return 0;
1684}
1685
1686
1687static const struct file_operations mini_rtc_fops = {
1688 .owner = THIS_MODULE,
1689 .ioctl = mini_rtc_ioctl,
1690 .open = mini_rtc_open,
1691 .release = mini_rtc_release,
1692};
1693
1694static struct miscdevice rtc_mini_dev =
1695{
1696 .minor = RTC_MINOR,
1697 .name = "rtc",
1698 .fops = &mini_rtc_fops,
1699};
1700
1701static int __init rtc_mini_init(void)
1702{
1703 int retval;
1704
1705 if (tlb_type == hypervisor)
1706 mini_rtc_ops = &hypervisor_rtc_ops;
1707 else if (this_is_starfire)
1708 mini_rtc_ops = &starfire_rtc_ops;
1709#ifdef CONFIG_PCI
1710 else if (bq4802_regs)
1711 mini_rtc_ops = &bq4802_rtc_ops;
1712 else if (ds1287_regs)
1713 mini_rtc_ops = &cmos_rtc_ops;
1714#endif /* CONFIG_PCI */
1715 else if (mstk48t02_regs)
1716 mini_rtc_ops = &mostek_rtc_ops;
1717 else
1718 return -ENODEV;
1719
1720 printk(KERN_INFO "Mini RTC Driver\n");
1721
1722 retval = misc_register(&rtc_mini_dev);
1723 if (retval < 0)
1724 return retval;
1725
1726 return 0;
1727}
1728
1729static void __exit rtc_mini_exit(void)
1730{
1731 misc_deregister(&rtc_mini_dev);
1732}
1733
1734int __devinit read_current_timer(unsigned long *timer_val) 880int __devinit read_current_timer(unsigned long *timer_val)
1735{ 881{
1736 *timer_val = tick_ops->get_tick(); 882 *timer_val = tick_ops->get_tick();
1737 return 0; 883 return 0;
1738} 884}
1739
1740module_init(rtc_mini_init);
1741module_exit(rtc_mini_exit);
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index c824df13f58..81ccd22e78d 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -38,6 +38,7 @@
38#include <asm/timer.h> 38#include <asm/timer.h>
39#include <asm/head.h> 39#include <asm/head.h>
40#include <asm/prom.h> 40#include <asm/prom.h>
41#include <asm/memctrl.h>
41 42
42#include "entry.h" 43#include "entry.h"
43#include "kstack.h" 44#include "kstack.h"
@@ -129,6 +130,56 @@ void do_BUG(const char *file, int line)
129} 130}
130#endif 131#endif
131 132
133static DEFINE_SPINLOCK(dimm_handler_lock);
134static dimm_printer_t dimm_handler;
135
136static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
137{
138 unsigned long flags;
139 int ret = -ENODEV;
140
141 spin_lock_irqsave(&dimm_handler_lock, flags);
142 if (dimm_handler) {
143 ret = dimm_handler(synd_code, paddr, buf, buflen);
144 } else if (tlb_type == spitfire) {
145 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
146 ret = -EINVAL;
147 else
148 ret = 0;
149 } else
150 ret = -ENODEV;
151 spin_unlock_irqrestore(&dimm_handler_lock, flags);
152
153 return ret;
154}
155
156int register_dimm_printer(dimm_printer_t func)
157{
158 unsigned long flags;
159 int ret = 0;
160
161 spin_lock_irqsave(&dimm_handler_lock, flags);
162 if (!dimm_handler)
163 dimm_handler = func;
164 else
165 ret = -EEXIST;
166 spin_unlock_irqrestore(&dimm_handler_lock, flags);
167
168 return ret;
169}
170EXPORT_SYMBOL_GPL(register_dimm_printer);
171
172void unregister_dimm_printer(dimm_printer_t func)
173{
174 unsigned long flags;
175
176 spin_lock_irqsave(&dimm_handler_lock, flags);
177 if (dimm_handler == func)
178 dimm_handler = NULL;
179 spin_unlock_irqrestore(&dimm_handler_lock, flags);
180}
181EXPORT_SYMBOL_GPL(unregister_dimm_printer);
182
132void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar) 183void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
133{ 184{
134 siginfo_t info; 185 siginfo_t info;
@@ -291,10 +342,7 @@ void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, u
291} 342}
292 343
293#ifdef CONFIG_PCI 344#ifdef CONFIG_PCI
294/* This is really pathetic... */ 345#include "pci_impl.h"
295extern volatile int pci_poke_in_progress;
296extern volatile int pci_poke_cpu;
297extern volatile int pci_poke_faulted;
298#endif 346#endif
299 347
300/* When access exceptions happen, we must do this. */ 348/* When access exceptions happen, we must do this. */
@@ -376,8 +424,7 @@ static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, un
376 424
377 if (udbl & bit) { 425 if (udbl & bit) {
378 scode = ecc_syndrome_table[udbl & 0xff]; 426 scode = ecc_syndrome_table[udbl & 0xff];
379 if (prom_getunumber(scode, afar, 427 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
380 memmod_str, sizeof(memmod_str)) == -1)
381 p = syndrome_unknown; 428 p = syndrome_unknown;
382 else 429 else
383 p = memmod_str; 430 p = memmod_str;
@@ -388,8 +435,7 @@ static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, un
388 435
389 if (udbh & bit) { 436 if (udbh & bit) {
390 scode = ecc_syndrome_table[udbh & 0xff]; 437 scode = ecc_syndrome_table[udbh & 0xff];
391 if (prom_getunumber(scode, afar, 438 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
392 memmod_str, sizeof(memmod_str)) == -1)
393 p = syndrome_unknown; 439 p = syndrome_unknown;
394 else 440 else
395 p = memmod_str; 441 p = memmod_str;
@@ -1062,8 +1108,6 @@ static const char *cheetah_get_string(unsigned long bit)
1062 return "???"; 1108 return "???";
1063} 1109}
1064 1110
1065extern int chmc_getunumber(int, unsigned long, char *, int);
1066
1067static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info, 1111static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1068 unsigned long afsr, unsigned long afar, int recoverable) 1112 unsigned long afsr, unsigned long afar, int recoverable)
1069{ 1113{
@@ -1105,7 +1149,7 @@ static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *in
1105 1149
1106 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT; 1150 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1107 syndrome = cheetah_ecc_syntab[syndrome]; 1151 syndrome = cheetah_ecc_syntab[syndrome];
1108 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum)); 1152 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1109 if (ret != -1) 1153 if (ret != -1)
1110 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n", 1154 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1111 (recoverable ? KERN_WARNING : KERN_CRIT), 1155 (recoverable ? KERN_WARNING : KERN_CRIT),
@@ -1116,7 +1160,7 @@ static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *in
1116 1160
1117 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT; 1161 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1118 syndrome = cheetah_mtag_syntab[syndrome]; 1162 syndrome = cheetah_mtag_syntab[syndrome];
1119 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum)); 1163 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1120 if (ret != -1) 1164 if (ret != -1)
1121 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n", 1165 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1122 (recoverable ? KERN_WARNING : KERN_CRIT), 1166 (recoverable ? KERN_WARNING : KERN_CRIT),
@@ -2224,7 +2268,6 @@ void die_if_kernel(char *str, struct pt_regs *regs)
2224 2268
2225extern int handle_popc(u32 insn, struct pt_regs *regs); 2269extern int handle_popc(u32 insn, struct pt_regs *regs);
2226extern int handle_ldf_stq(u32 insn, struct pt_regs *regs); 2270extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2227extern int vis_emul(struct pt_regs *, unsigned int);
2228 2271
2229void do_illegal_instruction(struct pt_regs *regs) 2272void do_illegal_instruction(struct pt_regs *regs)
2230{ 2273{
diff --git a/arch/sparc64/kernel/vio.c b/arch/sparc64/kernel/vio.c
index a490077891a..92b1f8ec01d 100644
--- a/arch/sparc64/kernel/vio.c
+++ b/arch/sparc64/kernel/vio.c
@@ -152,7 +152,7 @@ show_pciobppath_attr(struct device *dev, struct device_attribute *attr,
152static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, 152static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH,
153 show_pciobppath_attr, NULL); 153 show_pciobppath_attr, NULL);
154 154
155struct device_node *cdev_node; 155static struct device_node *cdev_node;
156 156
157static struct vio_dev *root_vdev; 157static struct vio_dev *root_vdev;
158static u64 cdev_cfg_handle; 158static u64 cdev_cfg_handle;
@@ -371,9 +371,9 @@ static struct mdesc_notifier_client vio_ds_notifier = {
371 .node_name = "domain-services-port", 371 .node_name = "domain-services-port",
372}; 372};
373 373
374const char *channel_devices_node = "channel-devices"; 374static const char *channel_devices_node = "channel-devices";
375const char *channel_devices_compat = "SUNW,sun4v-channel-devices"; 375static const char *channel_devices_compat = "SUNW,sun4v-channel-devices";
376const char *cfg_handle_prop = "cfg-handle"; 376static const char *cfg_handle_prop = "cfg-handle";
377 377
378static int __init vio_init(void) 378static int __init vio_init(void)
379{ 379{
diff --git a/arch/sparc64/kernel/visemul.c b/arch/sparc64/kernel/visemul.c
index c3fd64706b5..9e05cb5cb85 100644
--- a/arch/sparc64/kernel/visemul.c
+++ b/arch/sparc64/kernel/visemul.c
@@ -243,7 +243,7 @@ static inline unsigned int *fps_regaddr(struct fpustate *f,
243struct edge_tab { 243struct edge_tab {
244 u16 left, right; 244 u16 left, right;
245}; 245};
246struct edge_tab edge8_tab[8] = { 246static struct edge_tab edge8_tab[8] = {
247 { 0xff, 0x80 }, 247 { 0xff, 0x80 },
248 { 0x7f, 0xc0 }, 248 { 0x7f, 0xc0 },
249 { 0x3f, 0xe0 }, 249 { 0x3f, 0xe0 },
@@ -253,7 +253,7 @@ struct edge_tab edge8_tab[8] = {
253 { 0x03, 0xfe }, 253 { 0x03, 0xfe },
254 { 0x01, 0xff }, 254 { 0x01, 0xff },
255}; 255};
256struct edge_tab edge8_tab_l[8] = { 256static struct edge_tab edge8_tab_l[8] = {
257 { 0xff, 0x01 }, 257 { 0xff, 0x01 },
258 { 0xfe, 0x03 }, 258 { 0xfe, 0x03 },
259 { 0xfc, 0x07 }, 259 { 0xfc, 0x07 },
@@ -263,23 +263,23 @@ struct edge_tab edge8_tab_l[8] = {
263 { 0xc0, 0x7f }, 263 { 0xc0, 0x7f },
264 { 0x80, 0xff }, 264 { 0x80, 0xff },
265}; 265};
266struct edge_tab edge16_tab[4] = { 266static struct edge_tab edge16_tab[4] = {
267 { 0xf, 0x8 }, 267 { 0xf, 0x8 },
268 { 0x7, 0xc }, 268 { 0x7, 0xc },
269 { 0x3, 0xe }, 269 { 0x3, 0xe },
270 { 0x1, 0xf }, 270 { 0x1, 0xf },
271}; 271};
272struct edge_tab edge16_tab_l[4] = { 272static struct edge_tab edge16_tab_l[4] = {
273 { 0xf, 0x1 }, 273 { 0xf, 0x1 },
274 { 0xe, 0x3 }, 274 { 0xe, 0x3 },
275 { 0xc, 0x7 }, 275 { 0xc, 0x7 },
276 { 0x8, 0xf }, 276 { 0x8, 0xf },
277}; 277};
278struct edge_tab edge32_tab[2] = { 278static struct edge_tab edge32_tab[2] = {
279 { 0x3, 0x2 }, 279 { 0x3, 0x2 },
280 { 0x1, 0x3 }, 280 { 0x1, 0x3 },
281}; 281};
282struct edge_tab edge32_tab_l[2] = { 282static struct edge_tab edge32_tab_l[2] = {
283 { 0x3, 0x1 }, 283 { 0x3, 0x1 },
284 { 0x2, 0x3 }, 284 { 0x2, 0x3 },
285}; 285};
diff --git a/arch/sparc64/mm/fault.c b/arch/sparc64/mm/fault.c
index ea7d7ae76bc..a9e474bf638 100644
--- a/arch/sparc64/mm/fault.c
+++ b/arch/sparc64/mm/fault.c
@@ -51,43 +51,6 @@ static inline int notify_page_fault(struct pt_regs *regs)
51} 51}
52#endif 52#endif
53 53
54/*
55 * To debug kernel to catch accesses to certain virtual/physical addresses.
56 * Mode = 0 selects physical watchpoints, mode = 1 selects virtual watchpoints.
57 * flags = VM_READ watches memread accesses, flags = VM_WRITE watches memwrite accesses.
58 * Caller passes in a 64bit aligned addr, with mask set to the bytes that need to be
59 * watched. This is only useful on a single cpu machine for now. After the watchpoint
60 * is detected, the process causing it will be killed, thus preventing an infinite loop.
61 */
62void set_brkpt(unsigned long addr, unsigned char mask, int flags, int mode)
63{
64 unsigned long lsubits;
65
66 __asm__ __volatile__("ldxa [%%g0] %1, %0"
67 : "=r" (lsubits)
68 : "i" (ASI_LSU_CONTROL));
69 lsubits &= ~(LSU_CONTROL_PM | LSU_CONTROL_VM |
70 LSU_CONTROL_PR | LSU_CONTROL_VR |
71 LSU_CONTROL_PW | LSU_CONTROL_VW);
72
73 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
74 "membar #Sync"
75 : /* no outputs */
76 : "r" (addr), "r" (mode ? VIRT_WATCHPOINT : PHYS_WATCHPOINT),
77 "i" (ASI_DMMU));
78
79 lsubits |= ((unsigned long)mask << (mode ? 25 : 33));
80 if (flags & VM_READ)
81 lsubits |= (mode ? LSU_CONTROL_VR : LSU_CONTROL_PR);
82 if (flags & VM_WRITE)
83 lsubits |= (mode ? LSU_CONTROL_VW : LSU_CONTROL_PW);
84 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
85 "membar #Sync"
86 : /* no outputs */
87 : "r" (lsubits), "i" (ASI_LSU_CONTROL)
88 : "memory");
89}
90
91static void __kprobes unhandled_fault(unsigned long address, 54static void __kprobes unhandled_fault(unsigned long address,
92 struct task_struct *tsk, 55 struct task_struct *tsk,
93 struct pt_regs *regs) 56 struct pt_regs *regs)
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index a41df7bef03..3c10daf8fc0 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -46,15 +46,11 @@
46#include <asm/tsb.h> 46#include <asm/tsb.h>
47#include <asm/hypervisor.h> 47#include <asm/hypervisor.h>
48#include <asm/prom.h> 48#include <asm/prom.h>
49#include <asm/sstate.h>
50#include <asm/mdesc.h> 49#include <asm/mdesc.h>
51#include <asm/cpudata.h> 50#include <asm/cpudata.h>
52#include <asm/irq.h> 51#include <asm/irq.h>
53 52
54#define MAX_PHYS_ADDRESS (1UL << 42UL) 53#include "init.h"
55#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
56#define KPTE_BITMAP_BYTES \
57 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
58 54
59unsigned long kern_linear_pte_xor[2] __read_mostly; 55unsigned long kern_linear_pte_xor[2] __read_mostly;
60 56
@@ -416,17 +412,9 @@ void mmu_info(struct seq_file *m)
416#endif /* CONFIG_DEBUG_DCFLUSH */ 412#endif /* CONFIG_DEBUG_DCFLUSH */
417} 413}
418 414
419struct linux_prom_translation {
420 unsigned long virt;
421 unsigned long size;
422 unsigned long data;
423};
424
425/* Exported for kernel TLB miss handling in ktlb.S */
426struct linux_prom_translation prom_trans[512] __read_mostly; 415struct linux_prom_translation prom_trans[512] __read_mostly;
427unsigned int prom_trans_ents __read_mostly; 416unsigned int prom_trans_ents __read_mostly;
428 417
429/* Exported for SMP bootup purposes. */
430unsigned long kern_locked_tte_data; 418unsigned long kern_locked_tte_data;
431 419
432/* The obp translations are saved based on 8k pagesize, since obp can 420/* The obp translations are saved based on 8k pagesize, since obp can
@@ -938,6 +926,10 @@ int of_node_to_nid(struct device_node *dp)
938 int count, nid; 926 int count, nid;
939 u64 grp; 927 u64 grp;
940 928
929 /* This is the right thing to do on currently supported
930 * SUN4U NUMA platforms as well, as the PCI controller does
931 * not sit behind any particular memory controller.
932 */
941 if (!mlgroups) 933 if (!mlgroups)
942 return -1; 934 return -1;
943 935
@@ -1206,8 +1198,44 @@ out:
1206 return err; 1198 return err;
1207} 1199}
1208 1200
1201static int __init numa_parse_jbus(void)
1202{
1203 unsigned long cpu, index;
1204
1205 /* NUMA node id is encoded in bits 36 and higher, and there is
1206 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1207 */
1208 index = 0;
1209 for_each_present_cpu(cpu) {
1210 numa_cpu_lookup_table[cpu] = index;
1211 numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu);
1212 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1213 node_masks[index].val = cpu << 36UL;
1214
1215 index++;
1216 }
1217 num_node_masks = index;
1218
1219 add_node_ranges();
1220
1221 for (index = 0; index < num_node_masks; index++) {
1222 allocate_node_data(index);
1223 node_set_online(index);
1224 }
1225
1226 return 0;
1227}
1228
1209static int __init numa_parse_sun4u(void) 1229static int __init numa_parse_sun4u(void)
1210{ 1230{
1231 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1232 unsigned long ver;
1233
1234 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1235 if ((ver >> 32UL) == __JALAPENO_ID ||
1236 (ver >> 32UL) == __SERRANO_ID)
1237 return numa_parse_jbus();
1238 }
1211 return -1; 1239 return -1;
1212} 1240}
1213 1241
@@ -1633,8 +1661,6 @@ void __cpuinit sun4v_ktsb_register(void)
1633 1661
1634/* paging_init() sets up the page tables */ 1662/* paging_init() sets up the page tables */
1635 1663
1636extern void central_probe(void);
1637
1638static unsigned long last_valid_pfn; 1664static unsigned long last_valid_pfn;
1639pgd_t swapper_pg_dir[2048]; 1665pgd_t swapper_pg_dir[2048];
1640 1666
@@ -1679,8 +1705,6 @@ void __init paging_init(void)
1679 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL; 1705 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1680 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 1706 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1681 1707
1682 sstate_booting();
1683
1684 /* Invalidate both kernel TSBs. */ 1708 /* Invalidate both kernel TSBs. */
1685 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 1709 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1686#ifndef CONFIG_DEBUG_PAGEALLOC 1710#ifndef CONFIG_DEBUG_PAGEALLOC
@@ -1803,9 +1827,6 @@ void __init paging_init(void)
1803 } 1827 }
1804 1828
1805 printk("Booting Linux...\n"); 1829 printk("Booting Linux...\n");
1806
1807 central_probe();
1808 cpu_probe();
1809} 1830}
1810 1831
1811int __init page_in_phys_avail(unsigned long paddr) 1832int __init page_in_phys_avail(unsigned long paddr)
@@ -2032,7 +2053,6 @@ pgprot_t PAGE_COPY __read_mostly;
2032pgprot_t PAGE_SHARED __read_mostly; 2053pgprot_t PAGE_SHARED __read_mostly;
2033EXPORT_SYMBOL(PAGE_SHARED); 2054EXPORT_SYMBOL(PAGE_SHARED);
2034 2055
2035pgprot_t PAGE_EXEC __read_mostly;
2036unsigned long pg_iobits __read_mostly; 2056unsigned long pg_iobits __read_mostly;
2037 2057
2038unsigned long _PAGE_IE __read_mostly; 2058unsigned long _PAGE_IE __read_mostly;
@@ -2045,14 +2065,6 @@ unsigned long _PAGE_CACHE __read_mostly;
2045EXPORT_SYMBOL(_PAGE_CACHE); 2065EXPORT_SYMBOL(_PAGE_CACHE);
2046 2066
2047#ifdef CONFIG_SPARSEMEM_VMEMMAP 2067#ifdef CONFIG_SPARSEMEM_VMEMMAP
2048
2049#define VMEMMAP_CHUNK_SHIFT 22
2050#define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
2051#define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
2052#define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
2053
2054#define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
2055 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
2056unsigned long vmemmap_table[VMEMMAP_SIZE]; 2068unsigned long vmemmap_table[VMEMMAP_SIZE];
2057 2069
2058int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node) 2070int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
@@ -2136,7 +2148,6 @@ static void __init sun4u_pgprot_init(void)
2136 _PAGE_CACHE_4U | _PAGE_P_4U | 2148 _PAGE_CACHE_4U | _PAGE_P_4U |
2137 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2149 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2138 _PAGE_EXEC_4U | _PAGE_L_4U); 2150 _PAGE_EXEC_4U | _PAGE_L_4U);
2139 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
2140 2151
2141 _PAGE_IE = _PAGE_IE_4U; 2152 _PAGE_IE = _PAGE_IE_4U;
2142 _PAGE_E = _PAGE_E_4U; 2153 _PAGE_E = _PAGE_E_4U;
@@ -2147,10 +2158,10 @@ static void __init sun4u_pgprot_init(void)
2147 2158
2148#ifdef CONFIG_DEBUG_PAGEALLOC 2159#ifdef CONFIG_DEBUG_PAGEALLOC
2149 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^ 2160 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2150 0xfffff80000000000; 2161 0xfffff80000000000UL;
2151#else 2162#else
2152 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2163 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2153 0xfffff80000000000; 2164 0xfffff80000000000UL;
2154#endif 2165#endif
2155 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2166 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2156 _PAGE_P_4U | _PAGE_W_4U); 2167 _PAGE_P_4U | _PAGE_W_4U);
@@ -2188,7 +2199,6 @@ static void __init sun4v_pgprot_init(void)
2188 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2199 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2189 _PAGE_EXEC_4V); 2200 _PAGE_EXEC_4V);
2190 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2201 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2191 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
2192 2202
2193 _PAGE_IE = _PAGE_IE_4V; 2203 _PAGE_IE = _PAGE_IE_4V;
2194 _PAGE_E = _PAGE_E_4V; 2204 _PAGE_E = _PAGE_E_4V;
@@ -2196,20 +2206,20 @@ static void __init sun4v_pgprot_init(void)
2196 2206
2197#ifdef CONFIG_DEBUG_PAGEALLOC 2207#ifdef CONFIG_DEBUG_PAGEALLOC
2198 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ 2208 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2199 0xfffff80000000000; 2209 0xfffff80000000000UL;
2200#else 2210#else
2201 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2211 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2202 0xfffff80000000000; 2212 0xfffff80000000000UL;
2203#endif 2213#endif
2204 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V | 2214 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2205 _PAGE_P_4V | _PAGE_W_4V); 2215 _PAGE_P_4V | _PAGE_W_4V);
2206 2216
2207#ifdef CONFIG_DEBUG_PAGEALLOC 2217#ifdef CONFIG_DEBUG_PAGEALLOC
2208 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ 2218 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2209 0xfffff80000000000; 2219 0xfffff80000000000UL;
2210#else 2220#else
2211 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2221 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2212 0xfffff80000000000; 2222 0xfffff80000000000UL;
2213#endif 2223#endif
2214 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V | 2224 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2215 _PAGE_P_4V | _PAGE_W_4V); 2225 _PAGE_P_4V | _PAGE_W_4V);
diff --git a/arch/sparc64/mm/init.h b/arch/sparc64/mm/init.h
new file mode 100644
index 00000000000..16063870a48
--- /dev/null
+++ b/arch/sparc64/mm/init.h
@@ -0,0 +1,49 @@
1#ifndef _SPARC64_MM_INIT_H
2#define _SPARC64_MM_INIT_H
3
4/* Most of the symbols in this file are defined in init.c and
5 * marked non-static so that assembler code can get at them.
6 */
7
8#define MAX_PHYS_ADDRESS (1UL << 42UL)
9#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
10#define KPTE_BITMAP_BYTES \
11 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
12
13extern unsigned long kern_linear_pte_xor[2];
14extern unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
15extern unsigned int sparc64_highest_unlocked_tlb_ent;
16extern unsigned long sparc64_kern_pri_context;
17extern unsigned long sparc64_kern_pri_nuc_bits;
18extern unsigned long sparc64_kern_sec_context;
19extern void mmu_info(struct seq_file *m);
20
21struct linux_prom_translation {
22 unsigned long virt;
23 unsigned long size;
24 unsigned long data;
25};
26
27/* Exported for kernel TLB miss handling in ktlb.S */
28extern struct linux_prom_translation prom_trans[512];
29extern unsigned int prom_trans_ents;
30
31/* Exported for SMP bootup purposes. */
32extern unsigned long kern_locked_tte_data;
33
34extern void prom_world(int enter);
35
36extern void free_initmem(void);
37
38#ifdef CONFIG_SPARSEMEM_VMEMMAP
39#define VMEMMAP_CHUNK_SHIFT 22
40#define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
41#define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
42#define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
43
44#define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
45 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
46extern unsigned long vmemmap_table[VMEMMAP_SIZE];
47#endif
48
49#endif /* _SPARC64_MM_INIT_H */
diff --git a/arch/sparc64/mm/tlb.c b/arch/sparc64/mm/tlb.c
index ae24919cba7..d8f21e24a82 100644
--- a/arch/sparc64/mm/tlb.c
+++ b/arch/sparc64/mm/tlb.c
@@ -19,7 +19,7 @@
19 19
20/* Heavily inspired by the ppc64 code. */ 20/* Heavily inspired by the ppc64 code. */
21 21
22DEFINE_PER_CPU(struct mmu_gather, mmu_gathers) = { 0, }; 22DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
23 23
24void flush_tlb_pending(void) 24void flush_tlb_pending(void)
25{ 25{