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-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig16
-rw-r--r--arch/blackfin/configs/BF526-EZBRD_defconfig16
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig16
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig16
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig6
-rw-r--r--arch/blackfin/configs/CM-BF527_defconfig16
-rw-r--r--arch/blackfin/configs/CM-BF537E_defconfig16
-rw-r--r--arch/blackfin/configs/CM-BF537U_defconfig16
-rw-r--r--arch/blackfin/configs/PNAV-10_defconfig16
-rw-r--r--arch/blackfin/configs/SRV1_defconfig16
-rw-r--r--arch/blackfin/configs/TCM-BF537_defconfig16
-rw-r--r--arch/blackfin/include/asm/atomic.h32
-rw-r--r--arch/blackfin/include/asm/bitops.h24
-rw-r--r--arch/blackfin/include/asm/entry.h9
-rw-r--r--arch/blackfin/include/asm/ipipe.h278
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h80
-rw-r--r--arch/blackfin/include/asm/irq.h223
-rw-r--r--arch/blackfin/include/asm/system.h4
-rw-r--r--arch/blackfin/kernel/Makefile2
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c100
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c8
-rw-r--r--arch/blackfin/kernel/entry.S4
-rw-r--r--arch/blackfin/kernel/ipipe.c428
-rw-r--r--arch/blackfin/kernel/irqchip.c5
-rw-r--r--arch/blackfin/kernel/mcount.S70
-rw-r--r--arch/blackfin/kernel/process.c7
-rw-r--r--arch/blackfin/kernel/time.c15
-rw-r--r--arch/blackfin/kernel/traps.c13
-rw-r--r--arch/blackfin/lib/ins.S163
-rw-r--r--arch/blackfin/mach-bf518/Kconfig34
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h8
-rw-r--r--arch/blackfin/mach-bf518/include/mach/irq.h32
-rw-r--r--arch/blackfin/mach-bf518/ints-priority.c16
-rw-r--r--arch/blackfin/mach-bf527/Kconfig34
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h8
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h32
-rw-r--r--arch/blackfin/mach-bf527/ints-priority.c16
-rw-r--r--arch/blackfin/mach-bf533/Kconfig2
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h16
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h6
-rw-r--r--arch/blackfin/mach-bf537/Kconfig34
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h8
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h32
-rw-r--r--arch/blackfin/mach-bf537/ints-priority.c16
-rw-r--r--arch/blackfin/mach-bf538/Kconfig14
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF538.h8
-rw-r--r--arch/blackfin/mach-bf538/include/mach/irq.h12
-rw-r--r--arch/blackfin/mach-bf538/ints-priority.c6
-rw-r--r--arch/blackfin/mach-bf548/Kconfig2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h8
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf561/Kconfig2
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h8
-rw-r--r--arch/blackfin/mach-common/cpufreq.c4
-rw-r--r--arch/blackfin/mach-common/interrupt.S60
-rw-r--r--arch/blackfin/mach-common/ints-priority.c235
-rw-r--r--arch/blackfin/mach-common/pm.c10
-rw-r--r--arch/blackfin/mach-common/smp.c4
58 files changed, 1881 insertions, 419 deletions
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index 98cf7c3cfef..699781c4a4c 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -204,14 +204,14 @@ CONFIG_IRQ_MAC_RX=11
204CONFIG_IRQ_PORTH_INTA=11 204CONFIG_IRQ_PORTH_INTA=11
205CONFIG_IRQ_MAC_TX=11 205CONFIG_IRQ_MAC_TX=11
206CONFIG_IRQ_PORTH_INTB=11 206CONFIG_IRQ_PORTH_INTB=11
207CONFIG_IRQ_TMR0=12 207CONFIG_IRQ_TIMER0=12
208CONFIG_IRQ_TMR1=12 208CONFIG_IRQ_TIMER1=12
209CONFIG_IRQ_TMR2=12 209CONFIG_IRQ_TIMER2=12
210CONFIG_IRQ_TMR3=12 210CONFIG_IRQ_TIMER3=12
211CONFIG_IRQ_TMR4=12 211CONFIG_IRQ_TIMER4=12
212CONFIG_IRQ_TMR5=12 212CONFIG_IRQ_TIMER5=12
213CONFIG_IRQ_TMR6=12 213CONFIG_IRQ_TIMER6=12
214CONFIG_IRQ_TMR7=12 214CONFIG_IRQ_TIMER7=12
215CONFIG_IRQ_PORTG_INTA=12 215CONFIG_IRQ_PORTG_INTA=12
216CONFIG_IRQ_PORTG_INTB=12 216CONFIG_IRQ_PORTG_INTB=12
217CONFIG_IRQ_MEM_DMA0=13 217CONFIG_IRQ_MEM_DMA0=13
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index 667af6bb0c4..6dfcd270513 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -199,14 +199,14 @@ CONFIG_IRQ_MAC_RX=11
199CONFIG_IRQ_PORTH_INTA=11 199CONFIG_IRQ_PORTH_INTA=11
200CONFIG_IRQ_MAC_TX=11 200CONFIG_IRQ_MAC_TX=11
201CONFIG_IRQ_PORTH_INTB=11 201CONFIG_IRQ_PORTH_INTB=11
202CONFIG_IRQ_TMR0=12 202CONFIG_IRQ_TIMER0=12
203CONFIG_IRQ_TMR1=12 203CONFIG_IRQ_TIMER1=12
204CONFIG_IRQ_TMR2=12 204CONFIG_IRQ_TIMER2=12
205CONFIG_IRQ_TMR3=12 205CONFIG_IRQ_TIMER3=12
206CONFIG_IRQ_TMR4=12 206CONFIG_IRQ_TIMER4=12
207CONFIG_IRQ_TMR5=12 207CONFIG_IRQ_TIMER5=12
208CONFIG_IRQ_TMR6=12 208CONFIG_IRQ_TIMER6=12
209CONFIG_IRQ_TMR7=12 209CONFIG_IRQ_TIMER7=12
210CONFIG_IRQ_PORTG_INTA=12 210CONFIG_IRQ_PORTG_INTA=12
211CONFIG_IRQ_PORTG_INTB=12 211CONFIG_IRQ_PORTG_INTB=12
212CONFIG_IRQ_MEM_DMA0=13 212CONFIG_IRQ_MEM_DMA0=13
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 70b50d01047..2947dcba5ff 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -188,14 +188,14 @@ CONFIG_IRQ_MAC_RX=11
188CONFIG_IRQ_PORTH_INTA=11 188CONFIG_IRQ_PORTH_INTA=11
189CONFIG_IRQ_MAC_TX=11 189CONFIG_IRQ_MAC_TX=11
190CONFIG_IRQ_PORTH_INTB=11 190CONFIG_IRQ_PORTH_INTB=11
191CONFIG_IRQ_TMR0=12 191CONFIG_IRQ_TIMER0=8
192CONFIG_IRQ_TMR1=12 192CONFIG_IRQ_TIMER1=12
193CONFIG_IRQ_TMR2=12 193CONFIG_IRQ_TIMER2=12
194CONFIG_IRQ_TMR3=12 194CONFIG_IRQ_TIMER3=12
195CONFIG_IRQ_TMR4=12 195CONFIG_IRQ_TIMER4=12
196CONFIG_IRQ_TMR5=12 196CONFIG_IRQ_TIMER5=12
197CONFIG_IRQ_TMR6=12 197CONFIG_IRQ_TIMER6=12
198CONFIG_IRQ_TMR7=12 198CONFIG_IRQ_TIMER7=12
199CONFIG_IRQ_PORTG_INTA=12 199CONFIG_IRQ_PORTG_INTA=12
200CONFIG_IRQ_PORTG_INTB=12 200CONFIG_IRQ_PORTG_INTB=12
201CONFIG_IRQ_MEM_DMA0=13 201CONFIG_IRQ_MEM_DMA0=13
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index ed84c620d03..4aa66872303 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -148,14 +148,14 @@ CONFIG_IRQ_UART1_RX=10
148CONFIG_IRQ_UART1_TX=10 148CONFIG_IRQ_UART1_TX=10
149CONFIG_IRQ_MAC_RX=11 149CONFIG_IRQ_MAC_RX=11
150CONFIG_IRQ_MAC_TX=11 150CONFIG_IRQ_MAC_TX=11
151CONFIG_IRQ_TMR0=12 151CONFIG_IRQ_TIMER0=8
152CONFIG_IRQ_TMR1=12 152CONFIG_IRQ_TIMER1=12
153CONFIG_IRQ_TMR2=12 153CONFIG_IRQ_TIMER2=12
154CONFIG_IRQ_TMR3=12 154CONFIG_IRQ_TIMER3=12
155CONFIG_IRQ_TMR4=12 155CONFIG_IRQ_TIMER4=12
156CONFIG_IRQ_TMR5=12 156CONFIG_IRQ_TIMER5=12
157CONFIG_IRQ_TMR6=12 157CONFIG_IRQ_TIMER6=12
158CONFIG_IRQ_TMR7=12 158CONFIG_IRQ_TIMER7=12
159CONFIG_IRQ_PORTG_INTB=12 159CONFIG_IRQ_PORTG_INTB=12
160CONFIG_IRQ_MEM_DMA0=13 160CONFIG_IRQ_MEM_DMA0=13
161CONFIG_IRQ_MEM_DMA1=13 161CONFIG_IRQ_MEM_DMA1=13
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index f1d2b366994..baf33e66209 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -163,9 +163,9 @@ CONFIG_IRQ_UART0_RX=10
163CONFIG_IRQ_UART0_TX=10 163CONFIG_IRQ_UART0_TX=10
164CONFIG_IRQ_UART1_RX=10 164CONFIG_IRQ_UART1_RX=10
165CONFIG_IRQ_UART1_TX=10 165CONFIG_IRQ_UART1_TX=10
166CONFIG_IRQ_TMR0=12 166CONFIG_IRQ_TIMER0=12
167CONFIG_IRQ_TMR1=12 167CONFIG_IRQ_TIMER1=12
168CONFIG_IRQ_TMR2=12 168CONFIG_IRQ_TIMER2=12
169CONFIG_IRQ_WATCH=13 169CONFIG_IRQ_WATCH=13
170CONFIG_IRQ_PORTF_INTA=12 170CONFIG_IRQ_PORTF_INTA=12
171CONFIG_IRQ_PORTF_INTB=12 171CONFIG_IRQ_PORTF_INTB=12
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index 0043da5f493..719538571a5 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -190,14 +190,14 @@ CONFIG_IRQ_MAC_RX=11
190CONFIG_IRQ_PORTH_INTA=11 190CONFIG_IRQ_PORTH_INTA=11
191CONFIG_IRQ_MAC_TX=11 191CONFIG_IRQ_MAC_TX=11
192CONFIG_IRQ_PORTH_INTB=11 192CONFIG_IRQ_PORTH_INTB=11
193CONFIG_IRQ_TMR0=12 193CONFIG_IRQ_TIMER0=12
194CONFIG_IRQ_TMR1=12 194CONFIG_IRQ_TIMER1=12
195CONFIG_IRQ_TMR2=12 195CONFIG_IRQ_TIMER2=12
196CONFIG_IRQ_TMR3=12 196CONFIG_IRQ_TIMER3=12
197CONFIG_IRQ_TMR4=12 197CONFIG_IRQ_TIMER4=12
198CONFIG_IRQ_TMR5=12 198CONFIG_IRQ_TIMER5=12
199CONFIG_IRQ_TMR6=12 199CONFIG_IRQ_TIMER6=12
200CONFIG_IRQ_TMR7=12 200CONFIG_IRQ_TIMER7=12
201CONFIG_IRQ_PORTG_INTA=12 201CONFIG_IRQ_PORTG_INTA=12
202CONFIG_IRQ_PORTG_INTB=12 202CONFIG_IRQ_PORTG_INTB=12
203CONFIG_IRQ_MEM_DMA0=13 203CONFIG_IRQ_MEM_DMA0=13
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
index 1b50d382f6e..cbf4803b448 100644
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ b/arch/blackfin/configs/CM-BF537E_defconfig
@@ -157,14 +157,14 @@ CONFIG_IRQ_UART1_RX=10
157CONFIG_IRQ_UART1_TX=10 157CONFIG_IRQ_UART1_TX=10
158CONFIG_IRQ_MAC_RX=11 158CONFIG_IRQ_MAC_RX=11
159CONFIG_IRQ_MAC_TX=11 159CONFIG_IRQ_MAC_TX=11
160CONFIG_IRQ_TMR0=12 160CONFIG_IRQ_TIMER0=12
161CONFIG_IRQ_TMR1=12 161CONFIG_IRQ_TIMER1=12
162CONFIG_IRQ_TMR2=12 162CONFIG_IRQ_TIMER2=12
163CONFIG_IRQ_TMR3=12 163CONFIG_IRQ_TIMER3=12
164CONFIG_IRQ_TMR4=12 164CONFIG_IRQ_TIMER4=12
165CONFIG_IRQ_TMR5=12 165CONFIG_IRQ_TIMER5=12
166CONFIG_IRQ_TMR6=12 166CONFIG_IRQ_TIMER6=12
167CONFIG_IRQ_TMR7=12 167CONFIG_IRQ_TIMER7=12
168CONFIG_IRQ_PORTG_INTB=12 168CONFIG_IRQ_PORTG_INTB=12
169CONFIG_IRQ_MEM_DMA0=13 169CONFIG_IRQ_MEM_DMA0=13
170CONFIG_IRQ_MEM_DMA1=13 170CONFIG_IRQ_MEM_DMA1=13
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
index 2ca768d15b5..f2ac0cc37bf 100644
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ b/arch/blackfin/configs/CM-BF537U_defconfig
@@ -157,14 +157,14 @@ CONFIG_IRQ_UART1_RX=10
157CONFIG_IRQ_UART1_TX=10 157CONFIG_IRQ_UART1_TX=10
158CONFIG_IRQ_MAC_RX=11 158CONFIG_IRQ_MAC_RX=11
159CONFIG_IRQ_MAC_TX=11 159CONFIG_IRQ_MAC_TX=11
160CONFIG_IRQ_TMR0=12 160CONFIG_IRQ_TIMER0=12
161CONFIG_IRQ_TMR1=12 161CONFIG_IRQ_TIMER1=12
162CONFIG_IRQ_TMR2=12 162CONFIG_IRQ_TIMER2=12
163CONFIG_IRQ_TMR3=12 163CONFIG_IRQ_TIMER3=12
164CONFIG_IRQ_TMR4=12 164CONFIG_IRQ_TIMER4=12
165CONFIG_IRQ_TMR5=12 165CONFIG_IRQ_TIMER5=12
166CONFIG_IRQ_TMR6=12 166CONFIG_IRQ_TIMER6=12
167CONFIG_IRQ_TMR7=12 167CONFIG_IRQ_TIMER7=12
168CONFIG_IRQ_PORTG_INTB=12 168CONFIG_IRQ_PORTG_INTB=12
169CONFIG_IRQ_MEM_DMA0=13 169CONFIG_IRQ_MEM_DMA0=13
170CONFIG_IRQ_MEM_DMA1=13 170CONFIG_IRQ_MEM_DMA1=13
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index 648edd99a94..834fb8c9eef 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -153,14 +153,14 @@ CONFIG_IRQ_UART1_RX=10
153CONFIG_IRQ_UART1_TX=10 153CONFIG_IRQ_UART1_TX=10
154CONFIG_IRQ_MAC_RX=11 154CONFIG_IRQ_MAC_RX=11
155CONFIG_IRQ_MAC_TX=11 155CONFIG_IRQ_MAC_TX=11
156CONFIG_IRQ_TMR0=12 156CONFIG_IRQ_TIMER0=12
157CONFIG_IRQ_TMR1=12 157CONFIG_IRQ_TIMER1=12
158CONFIG_IRQ_TMR2=12 158CONFIG_IRQ_TIMER2=12
159CONFIG_IRQ_TMR3=12 159CONFIG_IRQ_TIMER3=12
160CONFIG_IRQ_TMR4=12 160CONFIG_IRQ_TIMER4=12
161CONFIG_IRQ_TMR5=12 161CONFIG_IRQ_TIMER5=12
162CONFIG_IRQ_TMR6=12 162CONFIG_IRQ_TIMER6=12
163CONFIG_IRQ_TMR7=12 163CONFIG_IRQ_TIMER7=12
164CONFIG_IRQ_PORTG_INTB=12 164CONFIG_IRQ_PORTG_INTB=12
165CONFIG_IRQ_MEM_DMA0=13 165CONFIG_IRQ_MEM_DMA0=13
166CONFIG_IRQ_MEM_DMA1=13 166CONFIG_IRQ_MEM_DMA1=13
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index ffa2396e612..010f0aa7e4c 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -172,14 +172,14 @@ CONFIG_IRQ_UART1_RX=10
172CONFIG_IRQ_UART1_TX=10 172CONFIG_IRQ_UART1_TX=10
173CONFIG_IRQ_MAC_RX=11 173CONFIG_IRQ_MAC_RX=11
174CONFIG_IRQ_MAC_TX=11 174CONFIG_IRQ_MAC_TX=11
175CONFIG_IRQ_TMR0=12 175CONFIG_IRQ_TIMER0=12
176CONFIG_IRQ_TMR1=12 176CONFIG_IRQ_TIMER1=12
177CONFIG_IRQ_TMR2=12 177CONFIG_IRQ_TIMER2=12
178CONFIG_IRQ_TMR3=12 178CONFIG_IRQ_TIMER3=12
179CONFIG_IRQ_TMR4=12 179CONFIG_IRQ_TIMER4=12
180CONFIG_IRQ_TMR5=12 180CONFIG_IRQ_TIMER5=12
181CONFIG_IRQ_TMR6=12 181CONFIG_IRQ_TIMER6=12
182CONFIG_IRQ_TMR7=12 182CONFIG_IRQ_TIMER7=12
183CONFIG_IRQ_PORTG_INTB=12 183CONFIG_IRQ_PORTG_INTB=12
184CONFIG_IRQ_MEM_DMA0=13 184CONFIG_IRQ_MEM_DMA0=13
185CONFIG_IRQ_MEM_DMA1=13 185CONFIG_IRQ_MEM_DMA1=13
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
index 6431192073c..0ba4aa89213 100644
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ b/arch/blackfin/configs/TCM-BF537_defconfig
@@ -144,14 +144,14 @@ CONFIG_IRQ_UART1_RX=10
144CONFIG_IRQ_UART1_TX=10 144CONFIG_IRQ_UART1_TX=10
145CONFIG_IRQ_MAC_RX=11 145CONFIG_IRQ_MAC_RX=11
146CONFIG_IRQ_MAC_TX=11 146CONFIG_IRQ_MAC_TX=11
147CONFIG_IRQ_TMR0=12 147CONFIG_IRQ_TIMER0=12
148CONFIG_IRQ_TMR1=12 148CONFIG_IRQ_TIMER1=12
149CONFIG_IRQ_TMR2=12 149CONFIG_IRQ_TIMER2=12
150CONFIG_IRQ_TMR3=12 150CONFIG_IRQ_TIMER3=12
151CONFIG_IRQ_TMR4=12 151CONFIG_IRQ_TIMER4=12
152CONFIG_IRQ_TMR5=12 152CONFIG_IRQ_TIMER5=12
153CONFIG_IRQ_TMR6=12 153CONFIG_IRQ_TIMER6=12
154CONFIG_IRQ_TMR7=12 154CONFIG_IRQ_TIMER7=12
155CONFIG_IRQ_PORTG_INTB=12 155CONFIG_IRQ_PORTG_INTB=12
156CONFIG_IRQ_MEM_DMA0=13 156CONFIG_IRQ_MEM_DMA0=13
157CONFIG_IRQ_MEM_DMA1=13 157CONFIG_IRQ_MEM_DMA1=13
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index d76275e5638..94b2a9b1945 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -92,18 +92,18 @@ static inline void atomic_add(int i, atomic_t *v)
92{ 92{
93 long flags; 93 long flags;
94 94
95 local_irq_save(flags); 95 local_irq_save_hw(flags);
96 v->counter += i; 96 v->counter += i;
97 local_irq_restore(flags); 97 local_irq_restore_hw(flags);
98} 98}
99 99
100static inline void atomic_sub(int i, atomic_t *v) 100static inline void atomic_sub(int i, atomic_t *v)
101{ 101{
102 long flags; 102 long flags;
103 103
104 local_irq_save(flags); 104 local_irq_save_hw(flags);
105 v->counter -= i; 105 v->counter -= i;
106 local_irq_restore(flags); 106 local_irq_restore_hw(flags);
107 107
108} 108}
109 109
@@ -112,10 +112,10 @@ static inline int atomic_add_return(int i, atomic_t *v)
112 int __temp = 0; 112 int __temp = 0;
113 long flags; 113 long flags;
114 114
115 local_irq_save(flags); 115 local_irq_save_hw(flags);
116 v->counter += i; 116 v->counter += i;
117 __temp = v->counter; 117 __temp = v->counter;
118 local_irq_restore(flags); 118 local_irq_restore_hw(flags);
119 119
120 120
121 return __temp; 121 return __temp;
@@ -126,10 +126,10 @@ static inline int atomic_sub_return(int i, atomic_t *v)
126 int __temp = 0; 126 int __temp = 0;
127 long flags; 127 long flags;
128 128
129 local_irq_save(flags); 129 local_irq_save_hw(flags);
130 v->counter -= i; 130 v->counter -= i;
131 __temp = v->counter; 131 __temp = v->counter;
132 local_irq_restore(flags); 132 local_irq_restore_hw(flags);
133 133
134 return __temp; 134 return __temp;
135} 135}
@@ -138,36 +138,36 @@ static inline void atomic_inc(volatile atomic_t *v)
138{ 138{
139 long flags; 139 long flags;
140 140
141 local_irq_save(flags); 141 local_irq_save_hw(flags);
142 v->counter++; 142 v->counter++;
143 local_irq_restore(flags); 143 local_irq_restore_hw(flags);
144} 144}
145 145
146static inline void atomic_dec(volatile atomic_t *v) 146static inline void atomic_dec(volatile atomic_t *v)
147{ 147{
148 long flags; 148 long flags;
149 149
150 local_irq_save(flags); 150 local_irq_save_hw(flags);
151 v->counter--; 151 v->counter--;
152 local_irq_restore(flags); 152 local_irq_restore_hw(flags);
153} 153}
154 154
155static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) 155static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
156{ 156{
157 long flags; 157 long flags;
158 158
159 local_irq_save(flags); 159 local_irq_save_hw(flags);
160 v->counter &= ~mask; 160 v->counter &= ~mask;
161 local_irq_restore(flags); 161 local_irq_restore_hw(flags);
162} 162}
163 163
164static inline void atomic_set_mask(unsigned int mask, atomic_t *v) 164static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
165{ 165{
166 long flags; 166 long flags;
167 167
168 local_irq_save(flags); 168 local_irq_save_hw(flags);
169 v->counter |= mask; 169 v->counter |= mask;
170 local_irq_restore(flags); 170 local_irq_restore_hw(flags);
171} 171}
172 172
173/* Atomic operations are already serializing */ 173/* Atomic operations are already serializing */
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 9964e17232e..21b036eadab 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -90,9 +90,9 @@ static inline void set_bit(int nr, volatile unsigned long *addr)
90 unsigned long flags; 90 unsigned long flags;
91 a += nr >> 5; 91 a += nr >> 5;
92 mask = 1 << (nr & 0x1f); 92 mask = 1 << (nr & 0x1f);
93 local_irq_save(flags); 93 local_irq_save_hw(flags);
94 *a |= mask; 94 *a |= mask;
95 local_irq_restore(flags); 95 local_irq_restore_hw(flags);
96} 96}
97 97
98static inline void clear_bit(int nr, volatile unsigned long *addr) 98static inline void clear_bit(int nr, volatile unsigned long *addr)
@@ -102,9 +102,9 @@ static inline void clear_bit(int nr, volatile unsigned long *addr)
102 unsigned long flags; 102 unsigned long flags;
103 a += nr >> 5; 103 a += nr >> 5;
104 mask = 1 << (nr & 0x1f); 104 mask = 1 << (nr & 0x1f);
105 local_irq_save(flags); 105 local_irq_save_hw(flags);
106 *a &= ~mask; 106 *a &= ~mask;
107 local_irq_restore(flags); 107 local_irq_restore_hw(flags);
108} 108}
109 109
110static inline void change_bit(int nr, volatile unsigned long *addr) 110static inline void change_bit(int nr, volatile unsigned long *addr)
@@ -114,9 +114,9 @@ static inline void change_bit(int nr, volatile unsigned long *addr)
114 114
115 ADDR += nr >> 5; 115 ADDR += nr >> 5;
116 mask = 1 << (nr & 31); 116 mask = 1 << (nr & 31);
117 local_irq_save(flags); 117 local_irq_save_hw(flags);
118 *ADDR ^= mask; 118 *ADDR ^= mask;
119 local_irq_restore(flags); 119 local_irq_restore_hw(flags);
120} 120}
121 121
122static inline int test_and_set_bit(int nr, volatile unsigned long *addr) 122static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
@@ -127,10 +127,10 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
127 127
128 a += nr >> 5; 128 a += nr >> 5;
129 mask = 1 << (nr & 0x1f); 129 mask = 1 << (nr & 0x1f);
130 local_irq_save(flags); 130 local_irq_save_hw(flags);
131 retval = (mask & *a) != 0; 131 retval = (mask & *a) != 0;
132 *a |= mask; 132 *a |= mask;
133 local_irq_restore(flags); 133 local_irq_restore_hw(flags);
134 134
135 return retval; 135 return retval;
136} 136}
@@ -143,10 +143,10 @@ static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
143 143
144 a += nr >> 5; 144 a += nr >> 5;
145 mask = 1 << (nr & 0x1f); 145 mask = 1 << (nr & 0x1f);
146 local_irq_save(flags); 146 local_irq_save_hw(flags);
147 retval = (mask & *a) != 0; 147 retval = (mask & *a) != 0;
148 *a &= ~mask; 148 *a &= ~mask;
149 local_irq_restore(flags); 149 local_irq_restore_hw(flags);
150 150
151 return retval; 151 return retval;
152} 152}
@@ -159,10 +159,10 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
159 159
160 a += nr >> 5; 160 a += nr >> 5;
161 mask = 1 << (nr & 0x1f); 161 mask = 1 << (nr & 0x1f);
162 local_irq_save(flags); 162 local_irq_save_hw(flags);
163 retval = (mask & *a) != 0; 163 retval = (mask & *a) != 0;
164 *a ^= mask; 164 *a ^= mask;
165 local_irq_restore(flags); 165 local_irq_restore_hw(flags);
166 return retval; 166 return retval;
167} 167}
168 168
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
index d94e4f5139d..b30a2968e27 100644
--- a/arch/blackfin/include/asm/entry.h
+++ b/arch/blackfin/include/asm/entry.h
@@ -27,6 +27,14 @@
27#define SAVE_ALL_SYS save_context_no_interrupts 27#define SAVE_ALL_SYS save_context_no_interrupts
28/* This is used for all normal interrupts. It saves a minimum of registers 28/* This is used for all normal interrupts. It saves a minimum of registers
29 to the stack, loads the IRQ number, and jumps to common code. */ 29 to the stack, loads the IRQ number, and jumps to common code. */
30#ifdef CONFIG_IPIPE
31# define LOAD_IPIPE_IPEND \
32 P0.l = lo(IPEND); \
33 P0.h = hi(IPEND); \
34 R1 = [P0];
35#else
36# define LOAD_IPIPE_IPEND
37#endif
30#define INTERRUPT_ENTRY(N) \ 38#define INTERRUPT_ENTRY(N) \
31 [--sp] = SYSCFG; \ 39 [--sp] = SYSCFG; \
32 \ 40 \
@@ -34,6 +42,7 @@
34 [--sp] = R0; /*orig_r0*/ \ 42 [--sp] = R0; /*orig_r0*/ \
35 [--sp] = (R7:0,P5:0); \ 43 [--sp] = (R7:0,P5:0); \
36 R0 = (N); \ 44 R0 = (N); \
45 LOAD_IPIPE_IPEND \
37 jump __common_int_entry; 46 jump __common_int_entry;
38 47
39/* For timer interrupts, we need to save IPEND, since the user_mode 48/* For timer interrupts, we need to save IPEND, since the user_mode
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
new file mode 100644
index 00000000000..76f53d8b9a0
--- /dev/null
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -0,0 +1,278 @@
1/* -*- linux-c -*-
2 * include/asm-blackfin/ipipe.h
3 *
4 * Copyright (C) 2002-2007 Philippe Gerum.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
9 * USA; either version 2 of the License, or (at your option) any later
10 * version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __ASM_BLACKFIN_IPIPE_H
23#define __ASM_BLACKFIN_IPIPE_H
24
25#ifdef CONFIG_IPIPE
26
27#include <linux/cpumask.h>
28#include <linux/list.h>
29#include <linux/threads.h>
30#include <linux/irq.h>
31#include <linux/ipipe_percpu.h>
32#include <asm/ptrace.h>
33#include <asm/irq.h>
34#include <asm/bitops.h>
35#include <asm/atomic.h>
36#include <asm/traps.h>
37
38#define IPIPE_ARCH_STRING "1.8-00"
39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 8
41#define IPIPE_PATCH_NUMBER 0
42
43#ifdef CONFIG_SMP
44#error "I-pipe/blackfin: SMP not implemented"
45#else /* !CONFIG_SMP */
46#define ipipe_processor_id() 0
47#endif /* CONFIG_SMP */
48
49#define prepare_arch_switch(next) \
50do { \
51 ipipe_schedule_notify(current, next); \
52 local_irq_disable_hw(); \
53} while (0)
54
55#define task_hijacked(p) \
56 ({ \
57 int __x__ = ipipe_current_domain != ipipe_root_domain; \
58 /* We would need to clear the SYNC flag for the root domain */ \
59 /* over the current processor in SMP mode. */ \
60 local_irq_enable_hw(); __x__; \
61 })
62
63struct ipipe_domain;
64
65struct ipipe_sysinfo {
66
67 int ncpus; /* Number of CPUs on board */
68 u64 cpufreq; /* CPU frequency (in Hz) */
69
70 /* Arch-dependent block */
71
72 struct {
73 unsigned tmirq; /* Timer tick IRQ */
74 u64 tmfreq; /* Timer frequency */
75 } archdep;
76};
77
78#define ipipe_read_tsc(t) \
79 ({ \
80 unsigned long __cy2; \
81 __asm__ __volatile__ ("1: %0 = CYCLES2\n" \
82 "%1 = CYCLES\n" \
83 "%2 = CYCLES2\n" \
84 "CC = %2 == %0\n" \
85 "if ! CC jump 1b\n" \
86 : "=r" (((unsigned long *)&t)[1]), \
87 "=r" (((unsigned long *)&t)[0]), \
88 "=r" (__cy2) \
89 : /*no input*/ : "CC"); \
90 t; \
91 })
92
93#define ipipe_cpu_freq() __ipipe_core_clock
94#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale)
95#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1)
96
97/* Private interface -- Internal use only */
98
99#define __ipipe_check_platform() do { } while (0)
100
101#define __ipipe_init_platform() do { } while (0)
102
103extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
104
105extern unsigned long __ipipe_irq_lvmask;
106
107extern struct ipipe_domain ipipe_root;
108
109/* enable/disable_irqdesc _must_ be used in pairs. */
110
111void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
112 unsigned irq);
113
114void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
115 unsigned irq);
116
117#define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq))
118
119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq))
120
121#define __ipipe_lock_root() \
122 set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
123
124#define __ipipe_unlock_root() \
125 clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
126
127void __ipipe_enable_pipeline(void);
128
129#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
130
131#define __ipipe_sync_pipeline(syncmask) \
132 do { \
133 struct ipipe_domain *ipd = ipipe_current_domain; \
134 if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \
135 __ipipe_sync_stage(syncmask); \
136 } while (0)
137
138void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
139
140int __ipipe_get_irq_priority(unsigned irq);
141
142int __ipipe_get_irqthread_priority(unsigned irq);
143
144void __ipipe_stall_root_raw(void);
145
146void __ipipe_unstall_root_raw(void);
147
148void __ipipe_serial_debug(const char *fmt, ...);
149
150DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
151
152extern unsigned long __ipipe_core_clock;
153
154extern unsigned long __ipipe_freq_scale;
155
156extern unsigned long __ipipe_irq_tail_hook;
157
158static inline unsigned long __ipipe_ffnz(unsigned long ul)
159{
160 return ffs(ul) - 1;
161}
162
163#define __ipipe_run_irqtail() /* Must be a macro */ \
164 do { \
165 asmlinkage void __ipipe_call_irqtail(void); \
166 unsigned long __pending; \
167 CSYNC(); \
168 __pending = bfin_read_IPEND(); \
169 if (__pending & 0x8000) { \
170 __pending &= ~0x8010; \
171 if (__pending && (__pending & (__pending - 1)) == 0) \
172 __ipipe_call_irqtail(); \
173 } \
174 } while (0)
175
176#define __ipipe_run_isr(ipd, irq) \
177 do { \
178 if (ipd == ipipe_root_domain) { \
179 /* \
180 * Note: the I-pipe implements a threaded interrupt model on \
181 * this arch for Linux external IRQs. The interrupt handler we \
182 * call here only wakes up the associated IRQ thread. \
183 */ \
184 if (ipipe_virtual_irq_p(irq)) { \
185 /* No irqtail here; virtual interrupts have no effect \
186 on IPEND so there is no need for processing \
187 deferral. */ \
188 local_irq_enable_nohead(ipd); \
189 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
190 local_irq_disable_nohead(ipd); \
191 } else \
192 /* \
193 * No need to run the irqtail here either; \
194 * we can't be preempted by hw IRQs, so \
195 * non-Linux IRQs cannot stack over the short \
196 * thread wakeup code. Which in turn means \
197 * that no irqtail condition could be pending \
198 * for domains above Linux in the pipeline. \
199 */ \
200 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
201 } else { \
202 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
203 local_irq_enable_nohead(ipd); \
204 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
205 /* Attempt to exit the outer interrupt level before \
206 * starting the deferred IRQ processing. */ \
207 local_irq_disable_nohead(ipd); \
208 __ipipe_run_irqtail(); \
209 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
210 } \
211 } while (0)
212
213#define __ipipe_syscall_watched_p(p, sc) \
214 (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls)
215
216void ipipe_init_irq_threads(void);
217
218int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
219
220#define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS)
221#define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS)
222
223#define IRQ_SYSTMR IRQ_TIMER0
224#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
225
226#if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533)
227#define PRIO_GPIODEMUX(irq) CONFIG_PFA
228#elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
229#define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA
230#elif defined(CONFIG_BF52x)
231#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \
232 (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \
233 (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \
234 -1)
235#elif defined(CONFIG_BF561)
236#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \
237 (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \
238 (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \
239 -1)
240#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
241#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
242#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
243#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
244#elif defined(CONFIG_BF54x)
245#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \
246 (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \
247 (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \
248 (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \
249 -1)
250#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
251#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
252#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
253#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
254#else
255# error "no PRIO_GPIODEMUX() for this part"
256#endif
257
258#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
259
260#else /* !CONFIG_IPIPE */
261
262#define task_hijacked(p) 0
263#define ipipe_trap_notify(t, r) 0
264
265#define __ipipe_stall_root_raw() do { } while (0)
266#define __ipipe_unstall_root_raw() do { } while (0)
267
268#define ipipe_init_irq_threads() do { } while (0)
269#define ipipe_start_irq_thread(irq, desc) 0
270
271#define IRQ_SYSTMR IRQ_CORETMR
272#define IRQ_PRIOTMR IRQ_CORETMR
273
274#define __ipipe_root_tick_p(regs) 1
275
276#endif /* !CONFIG_IPIPE */
277
278#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
new file mode 100644
index 00000000000..cb1025aeabc
--- /dev/null
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -0,0 +1,80 @@
1/* -*- linux-c -*-
2 * include/asm-blackfin/_baseipipe.h
3 *
4 * Copyright (C) 2007 Philippe Gerum.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
9 * USA; either version 2 of the License, or (at your option) any later
10 * version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __ASM_BLACKFIN_IPIPE_BASE_H
23#define __ASM_BLACKFIN_IPIPE_BASE_H
24
25#ifdef CONFIG_IPIPE
26
27#define IPIPE_NR_XIRQS NR_IRQS
28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
29
30/* Blackfin-specific, global domain flags */
31#define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */
32
33 /* Blackfin traps -- i.e. exception vector numbers */
34#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
35/* Pseudo-vectors used for kernel events */
36#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS
37#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT)
38#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1)
39#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2)
40#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3)
41#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
42#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
43#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
44#define IPIPE_LAST_EVENT IPIPE_EVENT_CLEANUP
45#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
46
47#define IPIPE_TIMER_IRQ IRQ_CORETMR
48
49#ifndef __ASSEMBLY__
50
51#include <linux/bitops.h>
52
53extern int test_bit(int nr, const void *addr);
54
55
56extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
57
58static inline void __ipipe_stall_root(void)
59{
60 volatile unsigned long *p = &__ipipe_root_status;
61 set_bit(0, p);
62}
63
64static inline unsigned long __ipipe_test_and_stall_root(void)
65{
66 volatile unsigned long *p = &__ipipe_root_status;
67 return test_and_set_bit(0, p);
68}
69
70static inline unsigned long __ipipe_test_root(void)
71{
72 const unsigned long *p = &__ipipe_root_status;
73 return test_bit(0, p);
74}
75
76#endif /* !__ASSEMBLY__ */
77
78#endif /* CONFIG_IPIPE */
79
80#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 21e25f778a6..3d977909ce7 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -22,11 +22,176 @@
22#include <asm/pda.h> 22#include <asm/pda.h>
23#include <asm/processor.h> 23#include <asm/processor.h>
24 24
25static __inline__ int irq_canonicalize(int irq) 25#ifdef CONFIG_SMP
26/* Forward decl needed due to cdef inter dependencies */
27static inline uint32_t __pure bfin_dspid(void);
28# define blackfin_core_id() (bfin_dspid() & 0xff)
29# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
30#else
31extern unsigned long bfin_irq_flags;
32#endif
33
34#ifdef CONFIG_IPIPE
35
36#include <linux/ipipe_trace.h>
37
38void __ipipe_unstall_root(void);
39
40void __ipipe_restore_root(unsigned long flags);
41
42#ifdef CONFIG_DEBUG_HWERR
43# define __all_masked_irq_flags 0x3f
44# define __save_and_cli_hw(x) \
45 __asm__ __volatile__( \
46 "cli %0;" \
47 "sti %1;" \
48 : "=&d"(x) \
49 : "d" (0x3F) \
50 )
51#else
52# define __all_masked_irq_flags 0x1f
53# define __save_and_cli_hw(x) \
54 __asm__ __volatile__( \
55 "cli %0;" \
56 : "=&d"(x) \
57 )
58#endif
59
60#define irqs_enabled_from_flags_hw(x) ((x) != __all_masked_irq_flags)
61#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags))
62#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x)
63
64#define local_save_flags(x) \
65 do { \
66 (x) = __ipipe_test_root() ? \
67 __all_masked_irq_flags : bfin_irq_flags; \
68 } while (0)
69
70#define local_irq_save(x) \
71 do { \
72 (x) = __ipipe_test_and_stall_root(); \
73 } while (0)
74
75#define local_irq_restore(x) __ipipe_restore_root(x)
76#define local_irq_disable() __ipipe_stall_root()
77#define local_irq_enable() __ipipe_unstall_root()
78#define irqs_disabled() __ipipe_test_root()
79
80#define local_save_flags_hw(x) \
81 __asm__ __volatile__( \
82 "cli %0;" \
83 "sti %0;" \
84 : "=d"(x) \
85 )
86
87#define irqs_disabled_hw() \
88 ({ \
89 unsigned long flags; \
90 local_save_flags_hw(flags); \
91 !irqs_enabled_from_flags_hw(flags); \
92 })
93
94static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
26{ 95{
27 return irq; 96 /* Merge virtual and real interrupt mask bits into a single
97 32bit word. */
98 return (real & ~(1 << 31)) | ((virt != 0) << 31);
28} 99}
29 100
101static inline int raw_demangle_irq_bits(unsigned long *x)
102{
103 int virt = (*x & (1 << 31)) != 0;
104 *x &= ~(1L << 31);
105 return virt;
106}
107
108#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
109
110#define local_irq_disable_hw() \
111 do { \
112 int _tmp_dummy; \
113 if (!irqs_disabled_hw()) \
114 ipipe_trace_begin(0x80000000); \
115 __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : ); \
116 } while (0)
117
118#define local_irq_enable_hw() \
119 do { \
120 if (irqs_disabled_hw()) \
121 ipipe_trace_end(0x80000000); \
122 __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags)); \
123 } while (0)
124
125#define local_irq_save_hw(x) \
126 do { \
127 __save_and_cli_hw(x); \
128 if (local_test_iflag_hw(x)) \
129 ipipe_trace_begin(0x80000001); \
130 } while (0)
131
132#define local_irq_restore_hw(x) \
133 do { \
134 if (local_test_iflag_hw(x)) { \
135 ipipe_trace_end(0x80000001); \
136 local_irq_enable_hw_notrace(); \
137 } \
138 } while (0)
139
140#define local_irq_disable_hw_notrace() \
141 do { \
142 int _tmp_dummy; \
143 __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : ); \
144 } while (0)
145
146#define local_irq_enable_hw_notrace() \
147 __asm__ __volatile__( \
148 "sti %0;" \
149 : \
150 : "d"(bfin_irq_flags) \
151 )
152
153#define local_irq_save_hw_notrace(x) __save_and_cli_hw(x)
154
155#define local_irq_restore_hw_notrace(x) \
156 do { \
157 if (local_test_iflag_hw(x)) \
158 local_irq_enable_hw_notrace(); \
159 } while (0)
160
161#else /* CONFIG_IPIPE_TRACE_IRQSOFF */
162
163#define local_irq_enable_hw() \
164 __asm__ __volatile__( \
165 "sti %0;" \
166 : \
167 : "d"(bfin_irq_flags) \
168 )
169
170#define local_irq_disable_hw() \
171 do { \
172 int _tmp_dummy; \
173 __asm__ __volatile__ ( \
174 "cli %0;" \
175 : "=d" (_tmp_dummy)); \
176 } while (0)
177
178#define local_irq_restore_hw(x) \
179 do { \
180 if (irqs_enabled_from_flags_hw(x)) \
181 local_irq_enable_hw(); \
182 } while (0)
183
184#define local_irq_save_hw(x) __save_and_cli_hw(x)
185
186#define local_irq_disable_hw_notrace() local_irq_disable_hw()
187#define local_irq_enable_hw_notrace() local_irq_enable_hw()
188#define local_irq_save_hw_notrace(x) local_irq_save_hw(x)
189#define local_irq_restore_hw_notrace(x) local_irq_restore_hw(x)
190
191#endif /* CONFIG_IPIPE_TRACE_IRQSOFF */
192
193#else /* !CONFIG_IPIPE */
194
30/* 195/*
31 * Interrupt configuring macros. 196 * Interrupt configuring macros.
32 */ 197 */
@@ -39,21 +204,6 @@ static __inline__ int irq_canonicalize(int irq)
39 ); \ 204 ); \
40 } while (0) 205 } while (0)
41 206
42#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
43# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
44#else
45# define NOP_PAD_ANOMALY_05000244
46#endif
47
48#ifdef CONFIG_SMP
49/* Forward decl needed due to cdef inter dependencies */
50static inline uint32_t __pure bfin_dspid(void);
51# define blackfin_core_id() (bfin_dspid() & 0xff)
52# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
53#else
54extern unsigned long bfin_irq_flags;
55#endif
56
57#define local_irq_enable() \ 207#define local_irq_enable() \
58 __asm__ __volatile__( \ 208 __asm__ __volatile__( \
59 "sti %0;" \ 209 "sti %0;" \
@@ -61,16 +211,6 @@ extern unsigned long bfin_irq_flags;
61 : "d" (bfin_irq_flags) \ 211 : "d" (bfin_irq_flags) \
62 ) 212 )
63 213
64#define idle_with_irq_disabled() \
65 __asm__ __volatile__( \
66 NOP_PAD_ANOMALY_05000244 \
67 ".align 8;" \
68 "sti %0;" \
69 "idle;" \
70 : \
71 : "d" (bfin_irq_flags) \
72 )
73
74#ifdef CONFIG_DEBUG_HWERR 214#ifdef CONFIG_DEBUG_HWERR
75# define __save_and_cli(x) \ 215# define __save_and_cli(x) \
76 __asm__ __volatile__( \ 216 __asm__ __volatile__( \
@@ -116,4 +256,33 @@ extern unsigned long bfin_irq_flags;
116 !irqs_enabled_from_flags(flags); \ 256 !irqs_enabled_from_flags(flags); \
117}) 257})
118 258
259#define local_irq_save_hw(x) local_irq_save(x)
260#define local_irq_restore_hw(x) local_irq_restore(x)
261#define local_irq_enable_hw() local_irq_enable()
262#define local_irq_disable_hw() local_irq_disable()
263#define irqs_disabled_hw() irqs_disabled()
264
265#endif /* !CONFIG_IPIPE */
266
267#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
268# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
269#else
270# define NOP_PAD_ANOMALY_05000244
271#endif
272
273#define idle_with_irq_disabled() \
274 __asm__ __volatile__( \
275 NOP_PAD_ANOMALY_05000244 \
276 ".align 8;" \
277 "sti %0;" \
278 "idle;" \
279 : \
280 : "d" (bfin_irq_flags) \
281 )
282
283static inline int irq_canonicalize(int irq)
284{
285 return irq;
286}
287
119#endif /* _BFIN_IRQ_H_ */ 288#endif /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index 812e6e6e2ce..a4c8254bec5 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -141,7 +141,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
141 unsigned long tmp = 0; 141 unsigned long tmp = 0;
142 unsigned long flags = 0; 142 unsigned long flags = 0;
143 143
144 local_irq_save(flags); 144 local_irq_save_hw(flags);
145 145
146 switch (size) { 146 switch (size) {
147 case 1: 147 case 1:
@@ -163,7 +163,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
163 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); 163 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
164 break; 164 break;
165 } 165 }
166 local_irq_restore(flags); 166 local_irq_restore_hw(flags);
167 return tmp; 167 return tmp;
168} 168}
169 169
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index f0902c120dc..38a233374f0 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -15,6 +15,8 @@ else
15 obj-y += time.o 15 obj-y += time.o
16endif 16endif
17 17
18obj-$(CONFIG_IPIPE) += ipipe.o
19obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o
18obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o 20obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
19obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 21obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
20obj-$(CONFIG_MODULES) += module.o 22obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 2c72b15b71b..4c14331978f 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -422,13 +422,13 @@ arch_initcall(bfin_gpio_init);
422void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ 422void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
423{ \ 423{ \
424 unsigned long flags; \ 424 unsigned long flags; \
425 local_irq_save(flags); \ 425 local_irq_save_hw(flags); \
426 if (arg) \ 426 if (arg) \
427 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ 427 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
428 else \ 428 else \
429 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \ 429 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
430 AWA_DUMMY_READ(name); \ 430 AWA_DUMMY_READ(name); \
431 local_irq_restore(flags); \ 431 local_irq_restore_hw(flags); \
432} \ 432} \
433EXPORT_SYMBOL(set_gpio_ ## name); 433EXPORT_SYMBOL(set_gpio_ ## name);
434 434
@@ -444,13 +444,13 @@ SET_GPIO(both)
444void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ 444void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
445{ \ 445{ \
446 unsigned long flags; \ 446 unsigned long flags; \
447 local_irq_save(flags); \ 447 local_irq_save_hw(flags); \
448 if (arg) \ 448 if (arg) \
449 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ 449 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
450 else \ 450 else \
451 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \ 451 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
452 AWA_DUMMY_READ(name); \ 452 AWA_DUMMY_READ(name); \
453 local_irq_restore(flags); \ 453 local_irq_restore_hw(flags); \
454} \ 454} \
455EXPORT_SYMBOL(set_gpio_ ## name); 455EXPORT_SYMBOL(set_gpio_ ## name);
456#else 456#else
@@ -473,10 +473,10 @@ SET_GPIO_SC(data)
473void set_gpio_toggle(unsigned gpio) 473void set_gpio_toggle(unsigned gpio)
474{ 474{
475 unsigned long flags; 475 unsigned long flags;
476 local_irq_save(flags); 476 local_irq_save_hw(flags);
477 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio); 477 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
478 AWA_DUMMY_READ(toggle); 478 AWA_DUMMY_READ(toggle);
479 local_irq_restore(flags); 479 local_irq_restore_hw(flags);
480} 480}
481#else 481#else
482void set_gpio_toggle(unsigned gpio) 482void set_gpio_toggle(unsigned gpio)
@@ -494,10 +494,10 @@ EXPORT_SYMBOL(set_gpio_toggle);
494void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ 494void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
495{ \ 495{ \
496 unsigned long flags; \ 496 unsigned long flags; \
497 local_irq_save(flags); \ 497 local_irq_save_hw(flags); \
498 gpio_bankb[gpio_bank(gpio)]->name = arg; \ 498 gpio_bankb[gpio_bank(gpio)]->name = arg; \
499 AWA_DUMMY_READ(name); \ 499 AWA_DUMMY_READ(name); \
500 local_irq_restore(flags); \ 500 local_irq_restore_hw(flags); \
501} \ 501} \
502EXPORT_SYMBOL(set_gpiop_ ## name); 502EXPORT_SYMBOL(set_gpiop_ ## name);
503#else 503#else
@@ -525,10 +525,10 @@ unsigned short get_gpio_ ## name(unsigned gpio) \
525{ \ 525{ \
526 unsigned long flags; \ 526 unsigned long flags; \
527 unsigned short ret; \ 527 unsigned short ret; \
528 local_irq_save(flags); \ 528 local_irq_save_hw(flags); \
529 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \ 529 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
530 AWA_DUMMY_READ(name); \ 530 AWA_DUMMY_READ(name); \
531 local_irq_restore(flags); \ 531 local_irq_restore_hw(flags); \
532 return ret; \ 532 return ret; \
533} \ 533} \
534EXPORT_SYMBOL(get_gpio_ ## name); 534EXPORT_SYMBOL(get_gpio_ ## name);
@@ -558,10 +558,10 @@ unsigned short get_gpiop_ ## name(unsigned gpio) \
558{ \ 558{ \
559 unsigned long flags; \ 559 unsigned long flags; \
560 unsigned short ret; \ 560 unsigned short ret; \
561 local_irq_save(flags); \ 561 local_irq_save_hw(flags); \
562 ret = (gpio_bankb[gpio_bank(gpio)]->name); \ 562 ret = (gpio_bankb[gpio_bank(gpio)]->name); \
563 AWA_DUMMY_READ(name); \ 563 AWA_DUMMY_READ(name); \
564 local_irq_restore(flags); \ 564 local_irq_restore_hw(flags); \
565 return ret; \ 565 return ret; \
566} \ 566} \
567EXPORT_SYMBOL(get_gpiop_ ## name); 567EXPORT_SYMBOL(get_gpiop_ ## name);
@@ -611,10 +611,10 @@ int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
611 if ((check_gpio(gpio) < 0) || !type) 611 if ((check_gpio(gpio) < 0) || !type)
612 return -EINVAL; 612 return -EINVAL;
613 613
614 local_irq_save(flags); 614 local_irq_save_hw(flags);
615 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); 615 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
616 wakeup_flags_map[gpio] = type; 616 wakeup_flags_map[gpio] = type;
617 local_irq_restore(flags); 617 local_irq_restore_hw(flags);
618 618
619 return 0; 619 return 0;
620} 620}
@@ -627,11 +627,11 @@ void gpio_pm_wakeup_free(unsigned gpio)
627 if (check_gpio(gpio) < 0) 627 if (check_gpio(gpio) < 0)
628 return; 628 return;
629 629
630 local_irq_save(flags); 630 local_irq_save_hw(flags);
631 631
632 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); 632 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
633 633
634 local_irq_restore(flags); 634 local_irq_restore_hw(flags);
635} 635}
636EXPORT_SYMBOL(gpio_pm_wakeup_free); 636EXPORT_SYMBOL(gpio_pm_wakeup_free);
637 637
@@ -882,7 +882,7 @@ int peripheral_request(unsigned short per, const char *label)
882 if (!(per & P_DEFINED)) 882 if (!(per & P_DEFINED))
883 return -ENODEV; 883 return -ENODEV;
884 884
885 local_irq_save(flags); 885 local_irq_save_hw(flags);
886 886
887 /* If a pin can be muxed as either GPIO or peripheral, make 887 /* If a pin can be muxed as either GPIO or peripheral, make
888 * sure it is not already a GPIO pin when we request it. 888 * sure it is not already a GPIO pin when we request it.
@@ -893,7 +893,7 @@ int peripheral_request(unsigned short per, const char *label)
893 printk(KERN_ERR 893 printk(KERN_ERR
894 "%s: Peripheral %d is already reserved as GPIO by %s !\n", 894 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
895 __func__, ident, get_label(ident)); 895 __func__, ident, get_label(ident));
896 local_irq_restore(flags); 896 local_irq_restore_hw(flags);
897 return -EBUSY; 897 return -EBUSY;
898 } 898 }
899 899
@@ -923,7 +923,7 @@ int peripheral_request(unsigned short per, const char *label)
923 printk(KERN_ERR 923 printk(KERN_ERR
924 "%s: Peripheral %d function %d is already reserved by %s !\n", 924 "%s: Peripheral %d function %d is already reserved by %s !\n",
925 __func__, ident, P_FUNCT2MUX(per), get_label(ident)); 925 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
926 local_irq_restore(flags); 926 local_irq_restore_hw(flags);
927 return -EBUSY; 927 return -EBUSY;
928 } 928 }
929 } 929 }
@@ -938,7 +938,7 @@ int peripheral_request(unsigned short per, const char *label)
938#endif 938#endif
939 port_setup(ident, PERIPHERAL_USAGE); 939 port_setup(ident, PERIPHERAL_USAGE);
940 940
941 local_irq_restore(flags); 941 local_irq_restore_hw(flags);
942 set_label(ident, label); 942 set_label(ident, label);
943 943
944 return 0; 944 return 0;
@@ -980,10 +980,10 @@ void peripheral_free(unsigned short per)
980 if (check_gpio(ident) < 0) 980 if (check_gpio(ident) < 0)
981 return; 981 return;
982 982
983 local_irq_save(flags); 983 local_irq_save_hw(flags);
984 984
985 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) { 985 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
986 local_irq_restore(flags); 986 local_irq_restore_hw(flags);
987 return; 987 return;
988 } 988 }
989 989
@@ -994,7 +994,7 @@ void peripheral_free(unsigned short per)
994 994
995 set_label(ident, "free"); 995 set_label(ident, "free");
996 996
997 local_irq_restore(flags); 997 local_irq_restore_hw(flags);
998} 998}
999EXPORT_SYMBOL(peripheral_free); 999EXPORT_SYMBOL(peripheral_free);
1000 1000
@@ -1028,7 +1028,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
1028 if (check_gpio(gpio) < 0) 1028 if (check_gpio(gpio) < 0)
1029 return -EINVAL; 1029 return -EINVAL;
1030 1030
1031 local_irq_save(flags); 1031 local_irq_save_hw(flags);
1032 1032
1033 /* 1033 /*
1034 * Allow that the identical GPIO can 1034 * Allow that the identical GPIO can
@@ -1037,7 +1037,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
1037 */ 1037 */
1038 1038
1039 if (cmp_label(gpio, label) == 0) { 1039 if (cmp_label(gpio, label) == 0) {
1040 local_irq_restore(flags); 1040 local_irq_restore_hw(flags);
1041 return 0; 1041 return 0;
1042 } 1042 }
1043 1043
@@ -1045,7 +1045,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
1045 dump_stack(); 1045 dump_stack();
1046 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", 1046 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
1047 gpio, get_label(gpio)); 1047 gpio, get_label(gpio));
1048 local_irq_restore(flags); 1048 local_irq_restore_hw(flags);
1049 return -EBUSY; 1049 return -EBUSY;
1050 } 1050 }
1051 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 1051 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
@@ -1053,7 +1053,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
1053 printk(KERN_ERR 1053 printk(KERN_ERR
1054 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", 1054 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1055 gpio, get_label(gpio)); 1055 gpio, get_label(gpio));
1056 local_irq_restore(flags); 1056 local_irq_restore_hw(flags);
1057 return -EBUSY; 1057 return -EBUSY;
1058 } 1058 }
1059 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) 1059 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))
@@ -1063,7 +1063,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
1063 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); 1063 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1064 set_label(gpio, label); 1064 set_label(gpio, label);
1065 1065
1066 local_irq_restore(flags); 1066 local_irq_restore_hw(flags);
1067 1067
1068 port_setup(gpio, GPIO_USAGE); 1068 port_setup(gpio, GPIO_USAGE);
1069 1069
@@ -1078,12 +1078,12 @@ void bfin_gpio_free(unsigned gpio)
1078 if (check_gpio(gpio) < 0) 1078 if (check_gpio(gpio) < 0)
1079 return; 1079 return;
1080 1080
1081 local_irq_save(flags); 1081 local_irq_save_hw(flags);
1082 1082
1083 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { 1083 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1084 dump_stack(); 1084 dump_stack();
1085 gpio_error(gpio); 1085 gpio_error(gpio);
1086 local_irq_restore(flags); 1086 local_irq_restore_hw(flags);
1087 return; 1087 return;
1088 } 1088 }
1089 1089
@@ -1091,7 +1091,7 @@ void bfin_gpio_free(unsigned gpio)
1091 1091
1092 set_label(gpio, "free"); 1092 set_label(gpio, "free");
1093 1093
1094 local_irq_restore(flags); 1094 local_irq_restore_hw(flags);
1095} 1095}
1096EXPORT_SYMBOL(bfin_gpio_free); 1096EXPORT_SYMBOL(bfin_gpio_free);
1097 1097
@@ -1102,14 +1102,14 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
1102 if (check_gpio(gpio) < 0) 1102 if (check_gpio(gpio) < 0)
1103 return -EINVAL; 1103 return -EINVAL;
1104 1104
1105 local_irq_save(flags); 1105 local_irq_save_hw(flags);
1106 1106
1107 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 1107 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1108 dump_stack(); 1108 dump_stack();
1109 printk(KERN_ERR 1109 printk(KERN_ERR
1110 "bfin-gpio: GPIO %d is already reserved as gpio-irq !\n", 1110 "bfin-gpio: GPIO %d is already reserved as gpio-irq !\n",
1111 gpio); 1111 gpio);
1112 local_irq_restore(flags); 1112 local_irq_restore_hw(flags);
1113 return -EBUSY; 1113 return -EBUSY;
1114 } 1114 }
1115 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 1115 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
@@ -1117,7 +1117,7 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
1117 printk(KERN_ERR 1117 printk(KERN_ERR
1118 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", 1118 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1119 gpio, get_label(gpio)); 1119 gpio, get_label(gpio));
1120 local_irq_restore(flags); 1120 local_irq_restore_hw(flags);
1121 return -EBUSY; 1121 return -EBUSY;
1122 } 1122 }
1123 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) 1123 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))
@@ -1128,7 +1128,7 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
1128 reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio); 1128 reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1129 set_label(gpio, label); 1129 set_label(gpio, label);
1130 1130
1131 local_irq_restore(flags); 1131 local_irq_restore_hw(flags);
1132 1132
1133 port_setup(gpio, GPIO_USAGE); 1133 port_setup(gpio, GPIO_USAGE);
1134 1134
@@ -1142,12 +1142,12 @@ void bfin_gpio_irq_free(unsigned gpio)
1142 if (check_gpio(gpio) < 0) 1142 if (check_gpio(gpio) < 0)
1143 return; 1143 return;
1144 1144
1145 local_irq_save(flags); 1145 local_irq_save_hw(flags);
1146 1146
1147 if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { 1147 if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1148 dump_stack(); 1148 dump_stack();
1149 gpio_error(gpio); 1149 gpio_error(gpio);
1150 local_irq_restore(flags); 1150 local_irq_restore_hw(flags);
1151 return; 1151 return;
1152 } 1152 }
1153 1153
@@ -1155,7 +1155,7 @@ void bfin_gpio_irq_free(unsigned gpio)
1155 1155
1156 set_label(gpio, "free"); 1156 set_label(gpio, "free");
1157 1157
1158 local_irq_restore(flags); 1158 local_irq_restore_hw(flags);
1159} 1159}
1160 1160
1161 1161
@@ -1169,10 +1169,10 @@ int bfin_gpio_direction_input(unsigned gpio)
1169 return -EINVAL; 1169 return -EINVAL;
1170 } 1170 }
1171 1171
1172 local_irq_save(flags); 1172 local_irq_save_hw(flags);
1173 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); 1173 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1174 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); 1174 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1175 local_irq_restore(flags); 1175 local_irq_restore_hw(flags);
1176 1176
1177 return 0; 1177 return 0;
1178} 1178}
@@ -1187,11 +1187,11 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1187 return -EINVAL; 1187 return -EINVAL;
1188 } 1188 }
1189 1189
1190 local_irq_save(flags); 1190 local_irq_save_hw(flags);
1191 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio); 1191 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
1192 gpio_set_value(gpio, value); 1192 gpio_set_value(gpio, value);
1193 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio); 1193 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
1194 local_irq_restore(flags); 1194 local_irq_restore_hw(flags);
1195 1195
1196 return 0; 1196 return 0;
1197} 1197}
@@ -1218,10 +1218,10 @@ void bfin_gpio_irq_prepare(unsigned gpio)
1218 1218
1219 port_setup(gpio, GPIO_USAGE); 1219 port_setup(gpio, GPIO_USAGE);
1220 1220
1221 local_irq_save(flags); 1221 local_irq_save_hw(flags);
1222 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); 1222 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1223 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); 1223 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1224 local_irq_restore(flags); 1224 local_irq_restore_hw(flags);
1225} 1225}
1226 1226
1227#else 1227#else
@@ -1232,11 +1232,11 @@ int bfin_gpio_get_value(unsigned gpio)
1232 int ret; 1232 int ret;
1233 1233
1234 if (unlikely(get_gpio_edge(gpio))) { 1234 if (unlikely(get_gpio_edge(gpio))) {
1235 local_irq_save(flags); 1235 local_irq_save_hw(flags);
1236 set_gpio_edge(gpio, 0); 1236 set_gpio_edge(gpio, 0);
1237 ret = get_gpio_data(gpio); 1237 ret = get_gpio_data(gpio);
1238 set_gpio_edge(gpio, 1); 1238 set_gpio_edge(gpio, 1);
1239 local_irq_restore(flags); 1239 local_irq_restore_hw(flags);
1240 1240
1241 return ret; 1241 return ret;
1242 } else 1242 } else
@@ -1254,11 +1254,11 @@ int bfin_gpio_direction_input(unsigned gpio)
1254 return -EINVAL; 1254 return -EINVAL;
1255 } 1255 }
1256 1256
1257 local_irq_save(flags); 1257 local_irq_save_hw(flags);
1258 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); 1258 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1259 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio); 1259 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1260 AWA_DUMMY_READ(inen); 1260 AWA_DUMMY_READ(inen);
1261 local_irq_restore(flags); 1261 local_irq_restore_hw(flags);
1262 1262
1263 return 0; 1263 return 0;
1264} 1264}
@@ -1273,7 +1273,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1273 return -EINVAL; 1273 return -EINVAL;
1274 } 1274 }
1275 1275
1276 local_irq_save(flags); 1276 local_irq_save_hw(flags);
1277 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); 1277 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1278 1278
1279 if (value) 1279 if (value)
@@ -1283,7 +1283,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1283 1283
1284 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio); 1284 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1285 AWA_DUMMY_READ(dir); 1285 AWA_DUMMY_READ(dir);
1286 local_irq_restore(flags); 1286 local_irq_restore_hw(flags);
1287 1287
1288 return 0; 1288 return 0;
1289} 1289}
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 5ef5d1a787f..87463ce87f5 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -332,7 +332,7 @@ void flush_switched_cplbs(unsigned int cpu)
332 332
333 nr_cplb_flush[cpu]++; 333 nr_cplb_flush[cpu]++;
334 334
335 local_irq_save(flags); 335 local_irq_save_hw(flags);
336 disable_icplb(); 336 disable_icplb();
337 for (i = first_switched_icplb; i < MAX_CPLBS; i++) { 337 for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
338 icplb_tbl[cpu][i].data = 0; 338 icplb_tbl[cpu][i].data = 0;
@@ -346,7 +346,7 @@ void flush_switched_cplbs(unsigned int cpu)
346 bfin_write32(DCPLB_DATA0 + i * 4, 0); 346 bfin_write32(DCPLB_DATA0 + i * 4, 0);
347 } 347 }
348 enable_dcplb(); 348 enable_dcplb();
349 local_irq_restore(flags); 349 local_irq_restore_hw(flags);
350 350
351} 351}
352 352
@@ -362,7 +362,7 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
362 return; 362 return;
363 } 363 }
364 364
365 local_irq_save(flags); 365 local_irq_save_hw(flags);
366 current_rwx_mask[cpu] = masks; 366 current_rwx_mask[cpu] = masks;
367 367
368 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; 368 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
@@ -382,5 +382,5 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
382 addr += PAGE_SIZE; 382 addr += PAGE_SIZE;
383 } 383 }
384 enable_dcplb(); 384 enable_dcplb();
385 local_irq_restore(flags); 385 local_irq_restore_hw(flags);
386} 386}
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S
index c0c3fe81122..a9cfba9946b 100644
--- a/arch/blackfin/kernel/entry.S
+++ b/arch/blackfin/kernel/entry.S
@@ -42,6 +42,10 @@
42#endif 42#endif
43 43
44ENTRY(_ret_from_fork) 44ENTRY(_ret_from_fork)
45#ifdef CONFIG_IPIPE
46 [--sp] = reti; /* IRQs on. */
47 SP += 4;
48#endif /* CONFIG_IPIPE */
45 SP += -12; 49 SP += -12;
46 call _schedule_tail; 50 call _schedule_tail;
47 SP += 12; 51 SP += 12;
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
new file mode 100644
index 00000000000..339be5a3ae6
--- /dev/null
+++ b/arch/blackfin/kernel/ipipe.c
@@ -0,0 +1,428 @@
1/* -*- linux-c -*-
2 * linux/arch/blackfin/kernel/ipipe.c
3 *
4 * Copyright (C) 2005-2007 Philippe Gerum.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
9 * USA; either version 2 of the License, or (at your option) any later
10 * version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 * Architecture-dependent I-pipe support for the Blackfin.
22 */
23
24#include <linux/kernel.h>
25#include <linux/sched.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/percpu.h>
29#include <linux/bitops.h>
30#include <linux/slab.h>
31#include <linux/errno.h>
32#include <linux/kthread.h>
33#include <asm/unistd.h>
34#include <asm/system.h>
35#include <asm/atomic.h>
36#include <asm/io.h>
37
38static int create_irq_threads;
39
40DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
41
42static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask);
43
44static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count);
45
46asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
47
48static void __ipipe_no_irqtail(void);
49
50unsigned long __ipipe_irq_tail_hook = (unsigned long)&__ipipe_no_irqtail;
51EXPORT_SYMBOL(__ipipe_irq_tail_hook);
52
53unsigned long __ipipe_core_clock;
54EXPORT_SYMBOL(__ipipe_core_clock);
55
56unsigned long __ipipe_freq_scale;
57EXPORT_SYMBOL(__ipipe_freq_scale);
58
59atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
60
61unsigned long __ipipe_irq_lvmask = __all_masked_irq_flags;
62EXPORT_SYMBOL(__ipipe_irq_lvmask);
63
64static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc)
65{
66 desc->ipipe_ack(irq, desc);
67}
68
69/*
70 * __ipipe_enable_pipeline() -- We are running on the boot CPU, hw
71 * interrupts are off, and secondary CPUs are still lost in space.
72 */
73void __ipipe_enable_pipeline(void)
74{
75 unsigned irq;
76
77 __ipipe_core_clock = get_cclk(); /* Fetch this once. */
78 __ipipe_freq_scale = 1000000000UL / __ipipe_core_clock;
79
80 for (irq = 0; irq < NR_IRQS; ++irq)
81 ipipe_virtualize_irq(ipipe_root_domain,
82 irq,
83 (ipipe_irq_handler_t)&asm_do_IRQ,
84 NULL,
85 &__ipipe_ack_irq,
86 IPIPE_HANDLE_MASK | IPIPE_PASS_MASK);
87}
88
89/*
90 * __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic
91 * interrupt protection log is maintained here for each domain. Hw
92 * interrupts are masked on entry.
93 */
94void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
95{
96 struct ipipe_domain *this_domain, *next_domain;
97 struct list_head *head, *pos;
98 int m_ack, s = -1;
99
100 /*
101 * Software-triggered IRQs do not need any ack. The contents
102 * of the register frame should only be used when processing
103 * the timer interrupt, but not for handling any other
104 * interrupt.
105 */
106 m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
107
108 this_domain = ipipe_current_domain;
109
110 if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control)))
111 head = &this_domain->p_link;
112 else {
113 head = __ipipe_pipeline.next;
114 next_domain = list_entry(head, struct ipipe_domain, p_link);
115 if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) {
116 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL)
117 next_domain->irqs[irq].acknowledge(irq, irq_desc + irq);
118 if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags))
119 s = __test_and_set_bit(IPIPE_STALL_FLAG,
120 &ipipe_root_cpudom_var(status));
121 __ipipe_dispatch_wired(next_domain, irq);
122 goto finalize;
123 return;
124 }
125 }
126
127 /* Ack the interrupt. */
128
129 pos = head;
130
131 while (pos != &__ipipe_pipeline) {
132 next_domain = list_entry(pos, struct ipipe_domain, p_link);
133 /*
134 * For each domain handling the incoming IRQ, mark it
135 * as pending in its log.
136 */
137 if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) {
138 /*
139 * Domains that handle this IRQ are polled for
140 * acknowledging it by decreasing priority
141 * order. The interrupt must be made pending
142 * _first_ in the domain's status flags before
143 * the PIC is unlocked.
144 */
145 __ipipe_set_irq_pending(next_domain, irq);
146
147 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) {
148 next_domain->irqs[irq].acknowledge(irq, irq_desc + irq);
149 m_ack = 1;
150 }
151 }
152
153 /*
154 * If the domain does not want the IRQ to be passed
155 * down the interrupt pipe, exit the loop now.
156 */
157 if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control))
158 break;
159
160 pos = next_domain->p_link.next;
161 }
162
163 /*
164 * Now walk the pipeline, yielding control to the highest
165 * priority domain that has pending interrupt(s) or
166 * immediately to the current domain if the interrupt has been
167 * marked as 'sticky'. This search does not go beyond the
168 * current domain in the pipeline. We also enforce the
169 * additional root stage lock (blackfin-specific). */
170
171 if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags))
172 s = __test_and_set_bit(IPIPE_STALL_FLAG,
173 &ipipe_root_cpudom_var(status));
174finalize:
175
176 __ipipe_walk_pipeline(head);
177
178 if (!s)
179 __clear_bit(IPIPE_STALL_FLAG,
180 &ipipe_root_cpudom_var(status));
181}
182
183int __ipipe_check_root(void)
184{
185 return ipipe_root_domain_p;
186}
187
188void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
189{
190 struct irq_desc *desc = irq_desc + irq;
191 int prio = desc->ic_prio;
192
193 desc->depth = 0;
194 if (ipd != &ipipe_root &&
195 atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1)
196 __set_bit(prio, &__ipipe_irq_lvmask);
197}
198EXPORT_SYMBOL(__ipipe_enable_irqdesc);
199
200void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
201{
202 struct irq_desc *desc = irq_desc + irq;
203 int prio = desc->ic_prio;
204
205 if (ipd != &ipipe_root &&
206 atomic_dec_and_test(&__ipipe_irq_lvdepth[prio]))
207 __clear_bit(prio, &__ipipe_irq_lvmask);
208}
209EXPORT_SYMBOL(__ipipe_disable_irqdesc);
210
211void __ipipe_stall_root_raw(void)
212{
213 /*
214 * This code is called by the ins{bwl} routines (see
215 * arch/blackfin/lib/ins.S), which are heavily used by the
216 * network stack. It masks all interrupts but those handled by
217 * non-root domains, so that we keep decent network transfer
218 * rates for Linux without inducing pathological jitter for
219 * the real-time domain.
220 */
221 __asm__ __volatile__ ("sti %0;" : : "d"(__ipipe_irq_lvmask));
222
223 __set_bit(IPIPE_STALL_FLAG,
224 &ipipe_root_cpudom_var(status));
225}
226
227void __ipipe_unstall_root_raw(void)
228{
229 __clear_bit(IPIPE_STALL_FLAG,
230 &ipipe_root_cpudom_var(status));
231
232 __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags));
233}
234
235int __ipipe_syscall_root(struct pt_regs *regs)
236{
237 unsigned long flags;
238
239 /* We need to run the IRQ tail hook whenever we don't
240 * propagate a syscall to higher domains, because we know that
241 * important operations might be pending there (e.g. Xenomai
242 * deferred rescheduling). */
243
244 if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) {
245 void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
246 hook();
247 return 0;
248 }
249
250 /*
251 * This routine either returns:
252 * 0 -- if the syscall is to be passed to Linux;
253 * 1 -- if the syscall should not be passed to Linux, and no
254 * tail work should be performed;
255 * -1 -- if the syscall should not be passed to Linux but the
256 * tail work has to be performed (for handling signals etc).
257 */
258
259 if (__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL) &&
260 __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs) > 0) {
261 if (ipipe_root_domain_p && !in_atomic()) {
262 /*
263 * Sync pending VIRQs before _TIF_NEED_RESCHED
264 * is tested.
265 */
266 local_irq_save_hw(flags);
267 if ((ipipe_root_cpudom_var(irqpend_himask) & IPIPE_IRQMASK_VIRT) != 0)
268 __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT);
269 local_irq_restore_hw(flags);
270 return -1;
271 }
272 return 1;
273 }
274
275 return 0;
276}
277
278unsigned long ipipe_critical_enter(void (*syncfn) (void))
279{
280 unsigned long flags;
281
282 local_irq_save_hw(flags);
283
284 return flags;
285}
286
287void ipipe_critical_exit(unsigned long flags)
288{
289 local_irq_restore_hw(flags);
290}
291
292static void __ipipe_no_irqtail(void)
293{
294}
295
296int ipipe_get_sysinfo(struct ipipe_sysinfo *info)
297{
298 info->ncpus = num_online_cpus();
299 info->cpufreq = ipipe_cpu_freq();
300 info->archdep.tmirq = IPIPE_TIMER_IRQ;
301 info->archdep.tmfreq = info->cpufreq;
302
303 return 0;
304}
305
306/*
307 * ipipe_trigger_irq() -- Push the interrupt at front of the pipeline
308 * just like if it has been actually received from a hw source. Also
309 * works for virtual interrupts.
310 */
311int ipipe_trigger_irq(unsigned irq)
312{
313 unsigned long flags;
314
315 if (irq >= IPIPE_NR_IRQS ||
316 (ipipe_virtual_irq_p(irq)
317 && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
318 return -EINVAL;
319
320 local_irq_save_hw(flags);
321
322 __ipipe_handle_irq(irq, NULL);
323
324 local_irq_restore_hw(flags);
325
326 return 1;
327}
328
329/* Move Linux IRQ to threads. */
330
331static int do_irqd(void *__desc)
332{
333 struct irq_desc *desc = __desc;
334 unsigned irq = desc - irq_desc;
335 int thrprio = desc->thr_prio;
336 int thrmask = 1 << thrprio;
337 int cpu = smp_processor_id();
338 cpumask_t cpumask;
339
340 sigfillset(&current->blocked);
341 current->flags |= PF_NOFREEZE;
342 cpumask = cpumask_of_cpu(cpu);
343 set_cpus_allowed(current, cpumask);
344 ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio);
345
346 while (!kthread_should_stop()) {
347 local_irq_disable();
348 if (!(desc->status & IRQ_SCHEDULED)) {
349 set_current_state(TASK_INTERRUPTIBLE);
350resched:
351 local_irq_enable();
352 schedule();
353 local_irq_disable();
354 }
355 __set_current_state(TASK_RUNNING);
356 /*
357 * If higher priority interrupt servers are ready to
358 * run, reschedule immediately. We need this for the
359 * GPIO demux IRQ handler to unmask the interrupt line
360 * _last_, after all GPIO IRQs have run.
361 */
362 if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1)))
363 goto resched;
364 if (--per_cpu(pending_irq_count[thrprio], cpu) == 0)
365 per_cpu(pending_irqthread_mask, cpu) &= ~thrmask;
366 desc->status &= ~IRQ_SCHEDULED;
367 desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs));
368 local_irq_enable();
369 }
370 __set_current_state(TASK_RUNNING);
371 return 0;
372}
373
374static void kick_irqd(unsigned irq, void *cookie)
375{
376 struct irq_desc *desc = irq_desc + irq;
377 int thrprio = desc->thr_prio;
378 int thrmask = 1 << thrprio;
379 int cpu = smp_processor_id();
380
381 if (!(desc->status & IRQ_SCHEDULED)) {
382 desc->status |= IRQ_SCHEDULED;
383 per_cpu(pending_irqthread_mask, cpu) |= thrmask;
384 ++per_cpu(pending_irq_count[thrprio], cpu);
385 wake_up_process(desc->thread);
386 }
387}
388
389int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc)
390{
391 if (desc->thread || !create_irq_threads)
392 return 0;
393
394 desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq);
395 if (desc->thread == NULL) {
396 printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq);
397 return -ENOMEM;
398 }
399
400 wake_up_process(desc->thread);
401
402 desc->thr_handler = ipipe_root_domain->irqs[irq].handler;
403 ipipe_root_domain->irqs[irq].handler = &kick_irqd;
404
405 return 0;
406}
407
408void __init ipipe_init_irq_threads(void)
409{
410 unsigned irq;
411 struct irq_desc *desc;
412
413 create_irq_threads = 1;
414
415 for (irq = 0; irq < NR_IRQS; irq++) {
416 desc = irq_desc + irq;
417 if (desc->action != NULL ||
418 (desc->status & IRQ_NOREQUEST) != 0)
419 ipipe_start_irq_thread(irq, desc);
420 }
421}
422
423EXPORT_SYMBOL(show_stack);
424
425#ifdef CONFIG_IPIPE_TRACE_MCOUNT
426void notrace _mcount(void);
427EXPORT_SYMBOL(_mcount);
428#endif /* CONFIG_IPIPE_TRACE_MCOUNT */
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 1624e112968..ab8209cbbad 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -108,8 +108,9 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
108{ 108{
109 struct pt_regs *old_regs; 109 struct pt_regs *old_regs;
110 struct irq_desc *desc = irq_desc + irq; 110 struct irq_desc *desc = irq_desc + irq;
111#ifndef CONFIG_IPIPE
111 unsigned short pending, other_ints; 112 unsigned short pending, other_ints;
112 113#endif
113 old_regs = set_irq_regs(regs); 114 old_regs = set_irq_regs(regs);
114 115
115 /* 116 /*
@@ -137,6 +138,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
137#endif 138#endif
138 generic_handle_irq(irq); 139 generic_handle_irq(irq);
139 140
141#ifndef CONFIG_IPIPE /* Useless and bugous over the I-pipe: IRQs are threaded. */
140 /* If we're the only interrupt running (ignoring IRQ15 which is for 142 /* If we're the only interrupt running (ignoring IRQ15 which is for
141 syscalls), lower our priority to IRQ14 so that softirqs run at 143 syscalls), lower our priority to IRQ14 so that softirqs run at
142 that level. If there's another, lower-level interrupt, irq_exit 144 that level. If there's another, lower-level interrupt, irq_exit
@@ -146,6 +148,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
146 other_ints = pending & (pending - 1); 148 other_ints = pending & (pending - 1);
147 if (other_ints == 0) 149 if (other_ints == 0)
148 lower_to_irq14(); 150 lower_to_irq14();
151#endif /* !CONFIG_IPIPE */
149 irq_exit(); 152 irq_exit();
150 153
151 set_irq_regs(old_regs); 154 set_irq_regs(old_regs);
diff --git a/arch/blackfin/kernel/mcount.S b/arch/blackfin/kernel/mcount.S
new file mode 100644
index 00000000000..edcfb3865f4
--- /dev/null
+++ b/arch/blackfin/kernel/mcount.S
@@ -0,0 +1,70 @@
1/*
2 * linux/arch/blackfin/mcount.S
3 *
4 * Copyright (C) 2006 Analog Devices Inc.
5 *
6 * 2007/04/12 Save index, length, modify and base registers. --rpm
7 */
8
9#include <linux/linkage.h>
10#include <asm/blackfin.h>
11
12.text
13
14.align 4 /* just in case */
15
16ENTRY(__mcount)
17 [--sp] = i0;
18 [--sp] = i1;
19 [--sp] = i2;
20 [--sp] = i3;
21 [--sp] = l0;
22 [--sp] = l1;
23 [--sp] = l2;
24 [--sp] = l3;
25 [--sp] = m0;
26 [--sp] = m1;
27 [--sp] = m2;
28 [--sp] = m3;
29 [--sp] = b0;
30 [--sp] = b1;
31 [--sp] = b2;
32 [--sp] = b3;
33 [--sp] = ( r7:0, p5:0 );
34 [--sp] = ASTAT;
35
36 p1.L = _ipipe_trace_enable;
37 p1.H = _ipipe_trace_enable;
38 r7 = [p1];
39 CC = r7 == 0;
40 if CC jump out;
41 link 0x10;
42 r0 = 0x0;
43 [sp + 0xc] = r0; /* v */
44 r0 = 0x0; /* type: IPIPE_TRACE_FN */
45 r1 = rets;
46 p0 = [fp]; /* p0: Prior FP */
47 r2 = [p0 + 4]; /* r2: Prior RETS */
48 call ___ipipe_trace;
49 unlink;
50out:
51 ASTAT = [sp++];
52 ( r7:0, p5:0 ) = [sp++];
53 b3 = [sp++];
54 b2 = [sp++];
55 b1 = [sp++];
56 b0 = [sp++];
57 m3 = [sp++];
58 m2 = [sp++];
59 m1 = [sp++];
60 m0 = [sp++];
61 l3 = [sp++];
62 l2 = [sp++];
63 l1 = [sp++];
64 l0 = [sp++];
65 i3 = [sp++];
66 i2 = [sp++];
67 i1 = [sp++];
68 i0 = [sp++];
69 rts;
70ENDPROC(__mcount)
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 1ec0faa8c68..33e2e8993f7 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -82,11 +82,14 @@ void cpu_idle(void)__attribute__((l1_text));
82 */ 82 */
83static void default_idle(void) 83static void default_idle(void)
84{ 84{
85 local_irq_disable(); 85#ifdef CONFIG_IPIPE
86 ipipe_suspend_domain();
87#endif
88 local_irq_disable_hw();
86 if (!need_resched()) 89 if (!need_resched())
87 idle_with_irq_disabled(); 90 idle_with_irq_disabled();
88 91
89 local_irq_enable(); 92 local_irq_enable_hw();
90} 93}
91 94
92/* 95/*
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index ec4dfa38eb0..172b4c58846 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -31,7 +31,7 @@ static struct irqaction bfin_timer_irq = {
31#endif 31#endif
32}; 32};
33 33
34#ifdef CONFIG_TICK_SOURCE_SYSTMR0 34#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
35void __init setup_system_timer0(void) 35void __init setup_system_timer0(void)
36{ 36{
37 /* Power down the core timer, just to play safe. */ 37 /* Power down the core timer, just to play safe. */
@@ -74,7 +74,7 @@ void __init setup_core_timer(void)
74static void __init 74static void __init
75time_sched_init(irqreturn_t(*timer_routine) (int, void *)) 75time_sched_init(irqreturn_t(*timer_routine) (int, void *))
76{ 76{
77#ifdef CONFIG_TICK_SOURCE_SYSTMR0 77#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
78 setup_system_timer0(); 78 setup_system_timer0();
79 bfin_timer_irq.handler = timer_routine; 79 bfin_timer_irq.handler = timer_routine;
80 setup_irq(IRQ_TIMER0, &bfin_timer_irq); 80 setup_irq(IRQ_TIMER0, &bfin_timer_irq);
@@ -94,7 +94,7 @@ static unsigned long gettimeoffset(void)
94 unsigned long offset; 94 unsigned long offset;
95 unsigned long clocks_per_jiffy; 95 unsigned long clocks_per_jiffy;
96 96
97#ifdef CONFIG_TICK_SOURCE_SYSTMR0 97#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
98 clocks_per_jiffy = bfin_read_TIMER0_PERIOD(); 98 clocks_per_jiffy = bfin_read_TIMER0_PERIOD();
99 offset = bfin_read_TIMER0_COUNTER() / \ 99 offset = bfin_read_TIMER0_COUNTER() / \
100 (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC); 100 (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
@@ -133,7 +133,8 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
133 static long last_rtc_update; 133 static long last_rtc_update;
134 134
135 write_seqlock(&xtime_lock); 135 write_seqlock(&xtime_lock);
136#ifdef CONFIG_TICK_SOURCE_SYSTMR0 136#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
137/* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */
137 if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { 138 if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) {
138#endif 139#endif
139 do_timer(1); 140 do_timer(1);
@@ -155,13 +156,17 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
155 /* Do it again in 60s. */ 156 /* Do it again in 60s. */
156 last_rtc_update = xtime.tv_sec - 600; 157 last_rtc_update = xtime.tv_sec - 600;
157 } 158 }
158#ifdef CONFIG_TICK_SOURCE_SYSTMR0 159#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
159 set_gptimer_status(0, TIMER_STATUS_TIMIL0); 160 set_gptimer_status(0, TIMER_STATUS_TIMIL0);
160 } 161 }
161#endif 162#endif
162 write_sequnlock(&xtime_lock); 163 write_sequnlock(&xtime_lock);
163 164
165#ifdef CONFIG_IPIPE
166 update_root_process_times(get_irq_regs());
167#else
164 update_process_times(user_mode(get_irq_regs())); 168 update_process_times(user_mode(get_irq_regs()));
169#endif
165 profile_tick(CPU_PROFILING); 170 profile_tick(CPU_PROFILING);
166 171
167 return IRQ_HANDLED; 172 return IRQ_HANDLED;
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 950cc822fb7..956aefb8468 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -577,10 +577,15 @@ asmlinkage void trap_c(struct pt_regs *fp)
577 } 577 }
578 } 578 }
579 579
580 info.si_signo = sig; 580#ifdef CONFIG_IPIPE
581 info.si_errno = 0; 581 if (!ipipe_trap_notify(fp->seqstat & 0x3f, fp))
582 info.si_addr = (void __user *)fp->pc; 582#endif
583 force_sig_info(sig, &info, current); 583 {
584 info.si_signo = sig;
585 info.si_errno = 0;
586 info.si_addr = (void __user *)fp->pc;
587 force_sig_info(sig, &info, current);
588 }
584 589
585 trace_buffer_restore(j); 590 trace_buffer_restore(j);
586 return; 591 return;
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
index d60554dce87..1b84b21ca7d 100644
--- a/arch/blackfin/lib/ins.S
+++ b/arch/blackfin/lib/ins.S
@@ -56,7 +56,16 @@
56ENTRY(_insl) 56ENTRY(_insl)
57#ifdef CONFIG_BFIN_INS_LOWOVERHEAD 57#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
58 P0 = R0; /* P0 = port */ 58 P0 = R0; /* P0 = port */
59#ifdef CONFIG_IPIPE
60 [--sp] = rets
61 [--sp] = (P5:0);
62 sp += -12
63 call ___ipipe_stall_root_raw
64 sp += 12
65 (P5:0) = [sp++];
66#else
59 cli R3; 67 cli R3;
68#endif
60 P1 = R1; /* P1 = address */ 69 P1 = R1; /* P1 = address */
61 P2 = R2; /* P2 = count */ 70 P2 = R2; /* P2 = count */
62 SSYNC; 71 SSYNC;
@@ -65,7 +74,14 @@ ENTRY(_insl)
65 [P1++] = R0; 74 [P1++] = R0;
66 NOP; 75 NOP;
67.Llong_loop_e: NOP; 76.Llong_loop_e: NOP;
77#ifdef CONFIG_IPIPE
78 sp += -12
79 call ___ipipe_unstall_root_raw
80 sp += 12
81 rets = [sp++]
82#else
68 sti R3; 83 sti R3;
84#endif
69 RTS; 85 RTS;
70#else 86#else
71 P0 = R0; /* P0 = port */ 87 P0 = R0; /* P0 = port */
@@ -74,13 +90,28 @@ ENTRY(_insl)
74 SSYNC; 90 SSYNC;
75 LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2; 91 LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
76.Llong_loop_s: 92.Llong_loop_s:
93#ifdef CONFIG_IPIPE
94 [--sp] = rets
95 [--sp] = (P5:0);
96 sp += -12
97 call ___ipipe_stall_root_raw
98 sp += 12
99 (P5:0) = [sp++];
100#else
77 CLI R3; 101 CLI R3;
102#endif
78 NOP; NOP; NOP; 103 NOP; NOP; NOP;
79 R0 = [P0]; 104 R0 = [P0];
80 [P1++] = R0; 105 [P1++] = R0;
81.Llong_loop_e: 106.Llong_loop_e:
107#ifdef CONFIG_IPIPE
108 sp += -12
109 call ___ipipe_unstall_root_raw
110 sp += 12
111 rets = [sp++]
112#else
82 STI R3; 113 STI R3;
83 114#endif
84 RTS; 115 RTS;
85#endif 116#endif
86ENDPROC(_insl) 117ENDPROC(_insl)
@@ -88,7 +119,16 @@ ENDPROC(_insl)
88ENTRY(_insw) 119ENTRY(_insw)
89#ifdef CONFIG_BFIN_INS_LOWOVERHEAD 120#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
90 P0 = R0; /* P0 = port */ 121 P0 = R0; /* P0 = port */
122#ifdef CONFIG_IPIPE
123 [--sp] = rets
124 [--sp] = (P5:0);
125 sp += -12
126 call ___ipipe_stall_root_raw
127 sp += 12
128 (P5:0) = [sp++];
129#else
91 cli R3; 130 cli R3;
131#endif
92 P1 = R1; /* P1 = address */ 132 P1 = R1; /* P1 = address */
93 P2 = R2; /* P2 = count */ 133 P2 = R2; /* P2 = count */
94 SSYNC; 134 SSYNC;
@@ -97,7 +137,14 @@ ENTRY(_insw)
97 W[P1++] = R0; 137 W[P1++] = R0;
98 NOP; 138 NOP;
99.Lword_loop_e: NOP; 139.Lword_loop_e: NOP;
140#ifdef CONFIG_IPIPE
141 sp += -12
142 call ___ipipe_unstall_root_raw
143 sp += 12
144 rets = [sp++]
145#else
100 sti R3; 146 sti R3;
147#endif
101 RTS; 148 RTS;
102#else 149#else
103 P0 = R0; /* P0 = port */ 150 P0 = R0; /* P0 = port */
@@ -106,12 +153,28 @@ ENTRY(_insw)
106 SSYNC; 153 SSYNC;
107 LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2; 154 LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
108.Lword_loop_s: 155.Lword_loop_s:
156#ifdef CONFIG_IPIPE
157 [--sp] = rets
158 [--sp] = (P5:0);
159 sp += -12
160 call ___ipipe_stall_root_raw
161 sp += 12
162 (P5:0) = [sp++];
163#else
109 CLI R3; 164 CLI R3;
165#endif
110 NOP; NOP; NOP; 166 NOP; NOP; NOP;
111 R0 = W[P0]; 167 R0 = W[P0];
112 W[P1++] = R0; 168 W[P1++] = R0;
113.Lword_loop_e: 169.Lword_loop_e:
170#ifdef CONFIG_IPIPE
171 sp += -12
172 call ___ipipe_unstall_root_raw
173 sp += 12
174 rets = [sp++]
175#else
114 STI R3; 176 STI R3;
177#endif
115 RTS; 178 RTS;
116 179
117#endif 180#endif
@@ -120,7 +183,16 @@ ENDPROC(_insw)
120ENTRY(_insw_8) 183ENTRY(_insw_8)
121#ifdef CONFIG_BFIN_INS_LOWOVERHEAD 184#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
122 P0 = R0; /* P0 = port */ 185 P0 = R0; /* P0 = port */
186#ifdef CONFIG_IPIPE
187 [--sp] = rets
188 [--sp] = (P5:0);
189 sp += -12
190 call ___ipipe_stall_root_raw
191 sp += 12
192 (P5:0) = [sp++];
193#else
123 cli R3; 194 cli R3;
195#endif
124 P1 = R1; /* P1 = address */ 196 P1 = R1; /* P1 = address */
125 P2 = R2; /* P2 = count */ 197 P2 = R2; /* P2 = count */
126 SSYNC; 198 SSYNC;
@@ -131,7 +203,14 @@ ENTRY(_insw_8)
131 B[P1++] = R0; 203 B[P1++] = R0;
132 NOP; 204 NOP;
133.Lword8_loop_e: NOP; 205.Lword8_loop_e: NOP;
206#ifdef CONFIG_IPIPE
207 sp += -12
208 call ___ipipe_unstall_root_raw
209 sp += 12
210 rets = [sp++]
211#else
134 sti R3; 212 sti R3;
213#endif
135 RTS; 214 RTS;
136#else 215#else
137 P0 = R0; /* P0 = port */ 216 P0 = R0; /* P0 = port */
@@ -140,7 +219,16 @@ ENTRY(_insw_8)
140 SSYNC; 219 SSYNC;
141 LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; 220 LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
142.Lword8_loop_s: 221.Lword8_loop_s:
222#ifdef CONFIG_IPIPE
223 [--sp] = rets
224 [--sp] = (P5:0);
225 sp += -12
226 call ___ipipe_stall_root_raw
227 sp += 12
228 (P5:0) = [sp++];
229#else
143 CLI R3; 230 CLI R3;
231#endif
144 NOP; NOP; NOP; 232 NOP; NOP; NOP;
145 R0 = W[P0]; 233 R0 = W[P0];
146 B[P1++] = R0; 234 B[P1++] = R0;
@@ -148,8 +236,14 @@ ENTRY(_insw_8)
148 B[P1++] = R0; 236 B[P1++] = R0;
149 NOP; 237 NOP;
150.Lword8_loop_e: 238.Lword8_loop_e:
239#ifdef CONFIG_IPIPE
240 sp += -12
241 call ___ipipe_unstall_root_raw
242 sp += 12
243 rets = [sp++]
244#else
151 STI R3; 245 STI R3;
152 246#endif
153 RTS; 247 RTS;
154#endif 248#endif
155ENDPROC(_insw_8) 249ENDPROC(_insw_8)
@@ -157,7 +251,16 @@ ENDPROC(_insw_8)
157ENTRY(_insb) 251ENTRY(_insb)
158#ifdef CONFIG_BFIN_INS_LOWOVERHEAD 252#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
159 P0 = R0; /* P0 = port */ 253 P0 = R0; /* P0 = port */
254#ifdef CONFIG_IPIPE
255 [--sp] = rets
256 [--sp] = (P5:0);
257 sp += -12
258 call ___ipipe_stall_root_raw
259 sp += 12
260 (P5:0) = [sp++];
261#else
160 cli R3; 262 cli R3;
263#endif
161 P1 = R1; /* P1 = address */ 264 P1 = R1; /* P1 = address */
162 P2 = R2; /* P2 = count */ 265 P2 = R2; /* P2 = count */
163 SSYNC; 266 SSYNC;
@@ -166,7 +269,14 @@ ENTRY(_insb)
166 B[P1++] = R0; 269 B[P1++] = R0;
167 NOP; 270 NOP;
168.Lbyte_loop_e: NOP; 271.Lbyte_loop_e: NOP;
272#ifdef CONFIG_IPIPE
273 sp += -12
274 call ___ipipe_unstall_root_raw
275 sp += 12
276 rets = [sp++]
277#else
169 sti R3; 278 sti R3;
279#endif
170 RTS; 280 RTS;
171#else 281#else
172 P0 = R0; /* P0 = port */ 282 P0 = R0; /* P0 = port */
@@ -175,13 +285,28 @@ ENTRY(_insb)
175 SSYNC; 285 SSYNC;
176 LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2; 286 LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
177.Lbyte_loop_s: 287.Lbyte_loop_s:
288#ifdef CONFIG_IPIPE
289 [--sp] = rets
290 [--sp] = (P5:0);
291 sp += -12
292 call ___ipipe_stall_root_raw
293 sp += 12
294 (P5:0) = [sp++];
295#else
178 CLI R3; 296 CLI R3;
297#endif
179 NOP; NOP; NOP; 298 NOP; NOP; NOP;
180 R0 = B[P0]; 299 R0 = B[P0];
181 B[P1++] = R0; 300 B[P1++] = R0;
182.Lbyte_loop_e: 301.Lbyte_loop_e:
302#ifdef CONFIG_IPIPE
303 sp += -12
304 call ___ipipe_unstall_root_raw
305 sp += 12
306 rets = [sp++]
307#else
183 STI R3; 308 STI R3;
184 309#endif
185 RTS; 310 RTS;
186#endif 311#endif
187ENDPROC(_insb) 312ENDPROC(_insb)
@@ -189,7 +314,16 @@ ENDPROC(_insb)
189ENTRY(_insl_16) 314ENTRY(_insl_16)
190#ifdef CONFIG_BFIN_INS_LOWOVERHEAD 315#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
191 P0 = R0; /* P0 = port */ 316 P0 = R0; /* P0 = port */
317#ifdef CONFIG_IPIPE
318 [--sp] = rets
319 [--sp] = (P5:0);
320 sp += -12
321 call ___ipipe_stall_root_raw
322 sp += 12
323 (P5:0) = [sp++];
324#else
192 cli R3; 325 cli R3;
326#endif
193 P1 = R1; /* P1 = address */ 327 P1 = R1; /* P1 = address */
194 P2 = R2; /* P2 = count */ 328 P2 = R2; /* P2 = count */
195 SSYNC; 329 SSYNC;
@@ -200,7 +334,14 @@ ENTRY(_insl_16)
200 W[P1++] = R0; 334 W[P1++] = R0;
201 NOP; 335 NOP;
202.Llong16_loop_e: NOP; 336.Llong16_loop_e: NOP;
337#ifdef CONFIG_IPIPE
338 sp += -12
339 call ___ipipe_unstall_root_raw
340 sp += 12
341 rets = [sp++]
342#else
203 sti R3; 343 sti R3;
344#endif
204 RTS; 345 RTS;
205#else 346#else
206 P0 = R0; /* P0 = port */ 347 P0 = R0; /* P0 = port */
@@ -209,14 +350,30 @@ ENTRY(_insl_16)
209 SSYNC; 350 SSYNC;
210 LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2; 351 LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2;
211.Llong16_loop_s: 352.Llong16_loop_s:
353#ifdef CONFIG_IPIPE
354 [--sp] = rets
355 [--sp] = (P5:0);
356 sp += -12
357 call ___ipipe_stall_root_raw
358 sp += 12
359 (P5:0) = [sp++];
360#else
212 CLI R3; 361 CLI R3;
362#endif
213 NOP; NOP; NOP; 363 NOP; NOP; NOP;
214 R0 = [P0]; 364 R0 = [P0];
215 W[P1++] = R0; 365 W[P1++] = R0;
216 R0 = R0 >> 16; 366 R0 = R0 >> 16;
217 W[P1++] = R0; 367 W[P1++] = R0;
218.Llong16_loop_e: 368.Llong16_loop_e:
369#ifdef CONFIG_IPIPE
370 sp += -12
371 call ___ipipe_unstall_root_raw
372 sp += 12
373 rets = [sp++]
374#else
219 STI R3; 375 STI R3;
376#endif
220 RTS; 377 RTS;
221#endif 378#endif
222ENDPROC(_insl_16) 379ENDPROC(_insl_16)
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 00f2d370063..f397ede006b 100644
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -154,29 +154,29 @@ config IRQ_MAC_TX
154config IRQ_PORTH_INTB 154config IRQ_PORTH_INTB
155 int "IRQ_PORTH_INTB" 155 int "IRQ_PORTH_INTB"
156 default 11 156 default 11
157config IRQ_TMR0 157config IRQ_TIMER0
158 int "IRQ_TMR0" 158 int "IRQ_TIMER0"
159 default 12 159 default 8
160config IRQ_TMR1 160config IRQ_TIMER1
161 int "IRQ_TMR1" 161 int "IRQ_TIMER1"
162 default 12 162 default 12
163config IRQ_TMR2 163config IRQ_TIMER2
164 int "IRQ_TMR2" 164 int "IRQ_TIMER2"
165 default 12 165 default 12
166config IRQ_TMR3 166config IRQ_TIMER3
167 int "IRQ_TMR3" 167 int "IRQ_TIMER3"
168 default 12 168 default 12
169config IRQ_TMR4 169config IRQ_TIMER4
170 int "IRQ_TMR4" 170 int "IRQ_TIMER4"
171 default 12 171 default 12
172config IRQ_TMR5 172config IRQ_TIMER5
173 int "IRQ_TMR5" 173 int "IRQ_TIMER5"
174 default 12 174 default 12
175config IRQ_TMR6 175config IRQ_TIMER6
176 int "IRQ_TMR6" 176 int "IRQ_TIMER6"
177 default 12 177 default 12
178config IRQ_TMR7 178config IRQ_TIMER7
179 int "IRQ_TMR7" 179 int "IRQ_TIMER7"
180 default 12 180 default 12
181config IRQ_PORTG_INTA 181config IRQ_PORTG_INTA
182 int "IRQ_PORTG_INTA" 182 int "IRQ_PORTG_INTA"
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index 9fbcd222198..ee3d4733369 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -1163,7 +1163,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1163 if (val == bfin_read_PLL_CTL()) 1163 if (val == bfin_read_PLL_CTL())
1164 return; 1164 return;
1165 1165
1166 local_irq_save(flags); 1166 local_irq_save_hw(flags);
1167 /* Enable the PLL Wakeup bit in SIC IWR */ 1167 /* Enable the PLL Wakeup bit in SIC IWR */
1168 iwr0 = bfin_read32(SIC_IWR0); 1168 iwr0 = bfin_read32(SIC_IWR0);
1169 iwr1 = bfin_read32(SIC_IWR1); 1169 iwr1 = bfin_read32(SIC_IWR1);
@@ -1177,7 +1177,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1177 1177
1178 bfin_write32(SIC_IWR0, iwr0); 1178 bfin_write32(SIC_IWR0, iwr0);
1179 bfin_write32(SIC_IWR1, iwr1); 1179 bfin_write32(SIC_IWR1, iwr1);
1180 local_irq_restore(flags); 1180 local_irq_restore_hw(flags);
1181} 1181}
1182 1182
1183/* Writing to VR_CTL initiates a PLL relock sequence. */ 1183/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -1188,7 +1188,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1188 if (val == bfin_read_VR_CTL()) 1188 if (val == bfin_read_VR_CTL())
1189 return; 1189 return;
1190 1190
1191 local_irq_save(flags); 1191 local_irq_save_hw(flags);
1192 /* Enable the PLL Wakeup bit in SIC IWR */ 1192 /* Enable the PLL Wakeup bit in SIC IWR */
1193 iwr0 = bfin_read32(SIC_IWR0); 1193 iwr0 = bfin_read32(SIC_IWR0);
1194 iwr1 = bfin_read32(SIC_IWR1); 1194 iwr1 = bfin_read32(SIC_IWR1);
@@ -1202,7 +1202,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1202 1202
1203 bfin_write32(SIC_IWR0, iwr0); 1203 bfin_write32(SIC_IWR0, iwr0);
1204 bfin_write32(SIC_IWR1, iwr1); 1204 bfin_write32(SIC_IWR1, iwr1);
1205 local_irq_restore(flags); 1205 local_irq_restore_hw(flags);
1206} 1206}
1207 1207
1208#endif /* _CDEF_BF52X_H */ 1208#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index e5062f107ae..3ff0f093313 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -98,14 +98,14 @@
98#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 98#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
99#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */ 99#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
100#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 100#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
101#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */ 101#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
102#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */ 102#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
103#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */ 103#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
104#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */ 104#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
105#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */ 105#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
106#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */ 106#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
107#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */ 107#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
108#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */ 108#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
109#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ 109#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
110#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ 110#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
111#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ 111#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
@@ -230,14 +230,14 @@
230#define IRQ_PORTH_INTB_POS 28 230#define IRQ_PORTH_INTB_POS 28
231 231
232/* IAR4 BIT FIELDS */ 232/* IAR4 BIT FIELDS */
233#define IRQ_TMR0_POS 0 233#define IRQ_TIMER0_POS 0
234#define IRQ_TMR1_POS 4 234#define IRQ_TIMER1_POS 4
235#define IRQ_TMR2_POS 8 235#define IRQ_TIMER2_POS 8
236#define IRQ_TMR3_POS 12 236#define IRQ_TIMER3_POS 12
237#define IRQ_TMR4_POS 16 237#define IRQ_TIMER4_POS 16
238#define IRQ_TMR5_POS 20 238#define IRQ_TIMER5_POS 20
239#define IRQ_TMR6_POS 24 239#define IRQ_TIMER6_POS 24
240#define IRQ_TMR7_POS 28 240#define IRQ_TIMER7_POS 28
241 241
242/* IAR5 BIT FIELDS */ 242/* IAR5 BIT FIELDS */
243#define IRQ_PORTG_INTA_POS 0 243#define IRQ_PORTG_INTA_POS 0
diff --git a/arch/blackfin/mach-bf518/ints-priority.c b/arch/blackfin/mach-bf518/ints-priority.c
index c490c79194c..3151fd5501c 100644
--- a/arch/blackfin/mach-bf518/ints-priority.c
+++ b/arch/blackfin/mach-bf518/ints-priority.c
@@ -70,14 +70,14 @@ void __init program_IAR(void)
70 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | 70 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
71 ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); 71 ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
72 72
73 bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | 73 bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
74 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | 74 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
75 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | 75 ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
76 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) | 76 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
77 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) | 77 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
78 ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) | 78 ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
79 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) | 79 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
80 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS)); 80 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
81 81
82 bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | 82 bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
83 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | 83 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 3cde4beeb21..8438ec6d667 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -168,29 +168,29 @@ config IRQ_MAC_TX
168config IRQ_PORTH_INTB 168config IRQ_PORTH_INTB
169 int "IRQ_PORTH_INTB" 169 int "IRQ_PORTH_INTB"
170 default 11 170 default 11
171config IRQ_TMR0 171config IRQ_TIMER0
172 int "IRQ_TMR0" 172 int "IRQ_TIMER0"
173 default 12 173 default 8
174config IRQ_TMR1 174config IRQ_TIMER1
175 int "IRQ_TMR1" 175 int "IRQ_TIMER1"
176 default 12 176 default 12
177config IRQ_TMR2 177config IRQ_TIMER2
178 int "IRQ_TMR2" 178 int "IRQ_TIMER2"
179 default 12 179 default 12
180config IRQ_TMR3 180config IRQ_TIMER3
181 int "IRQ_TMR3" 181 int "IRQ_TIMER3"
182 default 12 182 default 12
183config IRQ_TMR4 183config IRQ_TIMER4
184 int "IRQ_TMR4" 184 int "IRQ_TIMER4"
185 default 12 185 default 12
186config IRQ_TMR5 186config IRQ_TIMER5
187 int "IRQ_TMR5" 187 int "IRQ_TIMER5"
188 default 12 188 default 12
189config IRQ_TMR6 189config IRQ_TIMER6
190 int "IRQ_TMR6" 190 int "IRQ_TIMER6"
191 default 12 191 default 12
192config IRQ_TMR7 192config IRQ_TIMER7
193 int "IRQ_TMR7" 193 int "IRQ_TIMER7"
194 default 12 194 default 12
195config IRQ_PORTG_INTA 195config IRQ_PORTG_INTA
196 int "IRQ_PORTG_INTA" 196 int "IRQ_PORTG_INTA"
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 8a374c358ed..1fe76d8e040 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -1163,7 +1163,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1163 if (val == bfin_read_PLL_CTL()) 1163 if (val == bfin_read_PLL_CTL())
1164 return; 1164 return;
1165 1165
1166 local_irq_save(flags); 1166 local_irq_save_hw(flags);
1167 /* Enable the PLL Wakeup bit in SIC IWR */ 1167 /* Enable the PLL Wakeup bit in SIC IWR */
1168 iwr0 = bfin_read32(SIC_IWR0); 1168 iwr0 = bfin_read32(SIC_IWR0);
1169 iwr1 = bfin_read32(SIC_IWR1); 1169 iwr1 = bfin_read32(SIC_IWR1);
@@ -1177,7 +1177,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1177 1177
1178 bfin_write32(SIC_IWR0, iwr0); 1178 bfin_write32(SIC_IWR0, iwr0);
1179 bfin_write32(SIC_IWR1, iwr1); 1179 bfin_write32(SIC_IWR1, iwr1);
1180 local_irq_restore(flags); 1180 local_irq_restore_hw(flags);
1181} 1181}
1182 1182
1183/* Writing to VR_CTL initiates a PLL relock sequence. */ 1183/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -1188,7 +1188,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1188 if (val == bfin_read_VR_CTL()) 1188 if (val == bfin_read_VR_CTL())
1189 return; 1189 return;
1190 1190
1191 local_irq_save(flags); 1191 local_irq_save_hw(flags);
1192 /* Enable the PLL Wakeup bit in SIC IWR */ 1192 /* Enable the PLL Wakeup bit in SIC IWR */
1193 iwr0 = bfin_read32(SIC_IWR0); 1193 iwr0 = bfin_read32(SIC_IWR0);
1194 iwr1 = bfin_read32(SIC_IWR1); 1194 iwr1 = bfin_read32(SIC_IWR1);
@@ -1202,7 +1202,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1202 1202
1203 bfin_write32(SIC_IWR0, iwr0); 1203 bfin_write32(SIC_IWR0, iwr0);
1204 bfin_write32(SIC_IWR1, iwr1); 1204 bfin_write32(SIC_IWR1, iwr1);
1205 local_irq_restore(flags); 1205 local_irq_restore_hw(flags);
1206} 1206}
1207 1207
1208#endif /* _CDEF_BF52X_H */ 1208#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 4e2b3f2020e..8ea660d8151 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -96,14 +96,14 @@
96#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 96#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
97#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 97#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
98#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 98#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
99#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */ 99#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
100#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */ 100#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
101#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */ 101#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
102#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */ 102#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
103#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */ 103#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
104#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */ 104#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
105#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */ 105#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
106#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */ 106#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
107#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ 107#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
108#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ 108#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
109#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ 109#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
@@ -227,14 +227,14 @@
227#define IRQ_PORTH_INTB_POS 28 227#define IRQ_PORTH_INTB_POS 28
228 228
229/* IAR4 BIT FIELDS */ 229/* IAR4 BIT FIELDS */
230#define IRQ_TMR0_POS 0 230#define IRQ_TIMER0_POS 0
231#define IRQ_TMR1_POS 4 231#define IRQ_TIMER1_POS 4
232#define IRQ_TMR2_POS 8 232#define IRQ_TIMER2_POS 8
233#define IRQ_TMR3_POS 12 233#define IRQ_TIMER3_POS 12
234#define IRQ_TMR4_POS 16 234#define IRQ_TIMER4_POS 16
235#define IRQ_TMR5_POS 20 235#define IRQ_TIMER5_POS 20
236#define IRQ_TMR6_POS 24 236#define IRQ_TIMER6_POS 24
237#define IRQ_TMR7_POS 28 237#define IRQ_TIMER7_POS 28
238 238
239/* IAR5 BIT FIELDS */ 239/* IAR5 BIT FIELDS */
240#define IRQ_PORTG_INTA_POS 0 240#define IRQ_PORTG_INTA_POS 0
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c
index 8a2367403d2..f8c8acd73e3 100644
--- a/arch/blackfin/mach-bf527/ints-priority.c
+++ b/arch/blackfin/mach-bf527/ints-priority.c
@@ -69,14 +69,14 @@ void __init program_IAR(void)
69 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | 69 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
70 ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); 70 ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
71 71
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | 72 bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
73 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | 73 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
74 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | 74 ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
75 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) | 75 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
76 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) | 76 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
77 ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) | 77 ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
78 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) | 78 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
79 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS)); 79 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
80 80
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | 81 bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
82 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | 82 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig
index 76beb75f12d..14427de7d77 100644
--- a/arch/blackfin/mach-bf533/Kconfig
+++ b/arch/blackfin/mach-bf533/Kconfig
@@ -59,7 +59,7 @@ config DMA7_UARTTX
59 default 10 59 default 10
60config TIMER0 60config TIMER0
61 int "TIMER0" 61 int "TIMER0"
62 default 11 62 default 8
63config TIMER1 63config TIMER1
64 int "TIMER1" 64 int "TIMER1"
65 default 11 65 default 11
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index d7b08f638ea..bbc3c8386d4 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -684,10 +684,10 @@
684static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ 684static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
685{ \ 685{ \
686 unsigned long flags; \ 686 unsigned long flags; \
687 local_irq_save(flags); \ 687 local_irq_save_hw(flags); \
688 bfin_write16(FIO_FLAG_##name, val); \ 688 bfin_write16(FIO_FLAG_##name, val); \
689 bfin_read_CHIPID(); \ 689 bfin_read_CHIPID(); \
690 local_irq_restore(flags); \ 690 local_irq_restore_hw(flags); \
691} 691}
692BFIN_WRITE_FIO_FLAG(D) 692BFIN_WRITE_FIO_FLAG(D)
693BFIN_WRITE_FIO_FLAG(C) 693BFIN_WRITE_FIO_FLAG(C)
@@ -699,10 +699,10 @@ static inline u16 bfin_read_FIO_FLAG_##name(void) \
699{ \ 699{ \
700 unsigned long flags; \ 700 unsigned long flags; \
701 u16 ret; \ 701 u16 ret; \
702 local_irq_save(flags); \ 702 local_irq_save_hw(flags); \
703 ret = bfin_read16(FIO_FLAG_##name); \ 703 ret = bfin_read16(FIO_FLAG_##name); \
704 bfin_read_CHIPID(); \ 704 bfin_read_CHIPID(); \
705 local_irq_restore(flags); \ 705 local_irq_restore_hw(flags); \
706 return ret; \ 706 return ret; \
707} 707}
708BFIN_READ_FIO_FLAG(D) 708BFIN_READ_FIO_FLAG(D)
@@ -729,7 +729,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
729 if (val == bfin_read_PLL_CTL()) 729 if (val == bfin_read_PLL_CTL())
730 return; 730 return;
731 731
732 local_irq_save(flags); 732 local_irq_save_hw(flags);
733 /* Enable the PLL Wakeup bit in SIC IWR */ 733 /* Enable the PLL Wakeup bit in SIC IWR */
734 iwr = bfin_read32(SIC_IWR); 734 iwr = bfin_read32(SIC_IWR);
735 /* Only allow PPL Wakeup) */ 735 /* Only allow PPL Wakeup) */
@@ -740,7 +740,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
740 asm("IDLE;"); 740 asm("IDLE;");
741 741
742 bfin_write32(SIC_IWR, iwr); 742 bfin_write32(SIC_IWR, iwr);
743 local_irq_restore(flags); 743 local_irq_restore_hw(flags);
744} 744}
745 745
746/* Writing to VR_CTL initiates a PLL relock sequence. */ 746/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -751,7 +751,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
751 if (val == bfin_read_VR_CTL()) 751 if (val == bfin_read_VR_CTL())
752 return; 752 return;
753 753
754 local_irq_save(flags); 754 local_irq_save_hw(flags);
755 /* Enable the PLL Wakeup bit in SIC IWR */ 755 /* Enable the PLL Wakeup bit in SIC IWR */
756 iwr = bfin_read32(SIC_IWR); 756 iwr = bfin_read32(SIC_IWR);
757 /* Only allow PPL Wakeup) */ 757 /* Only allow PPL Wakeup) */
@@ -762,7 +762,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
762 asm("IDLE;"); 762 asm("IDLE;");
763 763
764 bfin_write32(SIC_IWR, iwr); 764 bfin_write32(SIC_IWR, iwr);
765 local_irq_restore(flags); 765 local_irq_restore_hw(flags);
766} 766}
767 767
768#endif /* _CDEF_BF532_H */ 768#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index e7dd315159d..db1e346cd1a 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -100,9 +100,9 @@ Core Emulation **
100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ 100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
101#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */ 101#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
102#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */ 102#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
103#define IRQ_TMR0 23 /*Timer 0 */ 103#define IRQ_TIMER0 23 /*Timer 0 */
104#define IRQ_TMR1 24 /*Timer 1 */ 104#define IRQ_TIMER1 24 /*Timer 1 */
105#define IRQ_TMR2 25 /*Timer 2 */ 105#define IRQ_TIMER2 25 /*Timer 2 */
106#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ 106#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
107#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ 107#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
108#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ 108#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
index 8255374c04a..bbc08fd4f12 100644
--- a/arch/blackfin/mach-bf537/Kconfig
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -64,29 +64,29 @@ config IRQ_MAC_RX
64config IRQ_MAC_TX 64config IRQ_MAC_TX
65 int "IRQ_MAC_TX" 65 int "IRQ_MAC_TX"
66 default 11 66 default 11
67config IRQ_TMR0 67config IRQ_TIMER0
68 int "IRQ_TMR0" 68 int "IRQ_TIMER0"
69 default 12 69 default 8
70config IRQ_TMR1 70config IRQ_TIMER1
71 int "IRQ_TMR1" 71 int "IRQ_TIMER1"
72 default 12 72 default 12
73config IRQ_TMR2 73config IRQ_TIMER2
74 int "IRQ_TMR2" 74 int "IRQ_TIMER2"
75 default 12 75 default 12
76config IRQ_TMR3 76config IRQ_TIMER3
77 int "IRQ_TMR3" 77 int "IRQ_TIMER3"
78 default 12 78 default 12
79config IRQ_TMR4 79config IRQ_TIMER4
80 int "IRQ_TMR4" 80 int "IRQ_TIMER4"
81 default 12 81 default 12
82config IRQ_TMR5 82config IRQ_TIMER5
83 int "IRQ_TMR5" 83 int "IRQ_TIMER5"
84 default 12 84 default 12
85config IRQ_TMR6 85config IRQ_TIMER6
86 int "IRQ_TMR6" 86 int "IRQ_TIMER6"
87 default 12 87 default 12
88config IRQ_TMR7 88config IRQ_TIMER7
89 int "IRQ_TMR7" 89 int "IRQ_TIMER7"
90 default 12 90 default 12
91config IRQ_PROG_INTA 91config IRQ_PROG_INTA
92 int "IRQ_PROG_INTA" 92 int "IRQ_PROG_INTA"
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index f3416923be6..5f8b5f845be 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1783,7 +1783,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1783 if (val == bfin_read_PLL_CTL()) 1783 if (val == bfin_read_PLL_CTL())
1784 return; 1784 return;
1785 1785
1786 local_irq_save(flags); 1786 local_irq_save_hw(flags);
1787 /* Enable the PLL Wakeup bit in SIC IWR */ 1787 /* Enable the PLL Wakeup bit in SIC IWR */
1788 iwr = bfin_read32(SIC_IWR); 1788 iwr = bfin_read32(SIC_IWR);
1789 /* Only allow PPL Wakeup) */ 1789 /* Only allow PPL Wakeup) */
@@ -1794,7 +1794,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1794 asm("IDLE;"); 1794 asm("IDLE;");
1795 1795
1796 bfin_write32(SIC_IWR, iwr); 1796 bfin_write32(SIC_IWR, iwr);
1797 local_irq_restore(flags); 1797 local_irq_restore_hw(flags);
1798} 1798}
1799 1799
1800/* Writing to VR_CTL initiates a PLL relock sequence. */ 1800/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -1805,7 +1805,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1805 if (val == bfin_read_VR_CTL()) 1805 if (val == bfin_read_VR_CTL())
1806 return; 1806 return;
1807 1807
1808 local_irq_save(flags); 1808 local_irq_save_hw(flags);
1809 /* Enable the PLL Wakeup bit in SIC IWR */ 1809 /* Enable the PLL Wakeup bit in SIC IWR */
1810 iwr = bfin_read32(SIC_IWR); 1810 iwr = bfin_read32(SIC_IWR);
1811 /* Only allow PPL Wakeup) */ 1811 /* Only allow PPL Wakeup) */
@@ -1816,7 +1816,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1816 asm("IDLE;"); 1816 asm("IDLE;");
1817 1817
1818 bfin_write32(SIC_IWR, iwr); 1818 bfin_write32(SIC_IWR, iwr);
1819 local_irq_restore(flags); 1819 local_irq_restore_hw(flags);
1820} 1820}
1821 1821
1822#endif /* _CDEF_BF534_H */ 1822#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 2e68a8a1e73..b2a71d5d4e5 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -82,14 +82,14 @@
82#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ 82#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
83#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ 83#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
84#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ 84#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
85#define IRQ_TMR0 26 /*Timer 0 */ 85#define IRQ_TIMER0 26 /*Timer 0 */
86#define IRQ_TMR1 27 /*Timer 1 */ 86#define IRQ_TIMER1 27 /*Timer 1 */
87#define IRQ_TMR2 28 /*Timer 2 */ 87#define IRQ_TIMER2 28 /*Timer 2 */
88#define IRQ_TMR3 29 /*Timer 3 */ 88#define IRQ_TIMER3 29 /*Timer 3 */
89#define IRQ_TMR4 30 /*Timer 4 */ 89#define IRQ_TIMER4 30 /*Timer 4 */
90#define IRQ_TMR5 31 /*Timer 5 */ 90#define IRQ_TIMER5 31 /*Timer 5 */
91#define IRQ_TMR6 32 /*Timer 6 */ 91#define IRQ_TIMER6 32 /*Timer 6 */
92#define IRQ_TMR7 33 /*Timer 7 */ 92#define IRQ_TIMER7 33 /*Timer 7 */
93#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ 93#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
94#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 94#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
95#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 95#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
@@ -195,16 +195,16 @@
195#define IRQ_CAN_TX_POS 0 195#define IRQ_CAN_TX_POS 0
196#define IRQ_MAC_RX_POS 4 196#define IRQ_MAC_RX_POS 4
197#define IRQ_MAC_TX_POS 8 197#define IRQ_MAC_TX_POS 8
198#define IRQ_TMR0_POS 12 198#define IRQ_TIMER0_POS 12
199#define IRQ_TMR1_POS 16 199#define IRQ_TIMER1_POS 16
200#define IRQ_TMR2_POS 20 200#define IRQ_TIMER2_POS 20
201#define IRQ_TMR3_POS 24 201#define IRQ_TIMER3_POS 24
202#define IRQ_TMR4_POS 28 202#define IRQ_TIMER4_POS 28
203 203
204/* IAR3 BIT FIELDS*/ 204/* IAR3 BIT FIELDS*/
205#define IRQ_TMR5_POS 0 205#define IRQ_TIMER5_POS 0
206#define IRQ_TMR6_POS 4 206#define IRQ_TIMER6_POS 4
207#define IRQ_TMR7_POS 8 207#define IRQ_TIMER7_POS 8
208#define IRQ_PROG_INTA_POS 12 208#define IRQ_PROG_INTA_POS 12
209#define IRQ_PORTG_INTB_POS 16 209#define IRQ_PORTG_INTB_POS 16
210#define IRQ_MEM_DMA0_POS 20 210#define IRQ_MEM_DMA0_POS 20
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index b1300b3f181..51c48087e03 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -55,15 +55,15 @@ void __init program_IAR(void)
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) | 55 bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
56 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) | 56 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
57 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | 57 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
58 ((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | 58 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
59 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | 59 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
60 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | 60 ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
61 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) | 61 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
62 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS)); 62 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
63 63
64 bfin_write_SIC_IAR3(((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) | 64 bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
65 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) | 65 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
66 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS) | 66 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
67 ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) | 67 ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
68 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | 68 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
69 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) | 69 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig
index a6f3307758c..f068c3523cd 100644
--- a/arch/blackfin/mach-bf538/Kconfig
+++ b/arch/blackfin/mach-bf538/Kconfig
@@ -55,14 +55,14 @@ config IRQ_UART0_RX
55config IRQ_UART0_TX 55config IRQ_UART0_TX
56 int "IRQ_UART0_TX" 56 int "IRQ_UART0_TX"
57 default 10 57 default 10
58config IRQ_TMR0 58config IRQ_TIMER0
59 int "IRQ_TMR0" 59 int "IRQ_TIMER0"
60 default 11 60 default 8
61config IRQ_TMR1 61config IRQ_TIMER1
62 int "IRQ_TMR1" 62 int "IRQ_TIMER1"
63 default 11 63 default 11
64config IRQ_TMR2 64config IRQ_TIMER2
65 int "IRQ_TMR2" 65 int "IRQ_TIMER2"
66 default 11 66 default 11
67config IRQ_PORTF_INTA 67config IRQ_PORTF_INTA
68 int "IRQ_PORTF_INTA" 68 int "IRQ_PORTF_INTA"
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 7e469b8d939..241725bc698 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -2063,7 +2063,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2063 if (val == bfin_read_PLL_CTL()) 2063 if (val == bfin_read_PLL_CTL())
2064 return; 2064 return;
2065 2065
2066 local_irq_save(flags); 2066 local_irq_save_hw(flags);
2067 /* Enable the PLL Wakeup bit in SIC IWR */ 2067 /* Enable the PLL Wakeup bit in SIC IWR */
2068 iwr0 = bfin_read32(SIC_IWR0); 2068 iwr0 = bfin_read32(SIC_IWR0);
2069 iwr1 = bfin_read32(SIC_IWR1); 2069 iwr1 = bfin_read32(SIC_IWR1);
@@ -2077,7 +2077,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2077 2077
2078 bfin_write32(SIC_IWR0, iwr0); 2078 bfin_write32(SIC_IWR0, iwr0);
2079 bfin_write32(SIC_IWR1, iwr1); 2079 bfin_write32(SIC_IWR1, iwr1);
2080 local_irq_restore(flags); 2080 local_irq_restore_hw(flags);
2081} 2081}
2082 2082
2083/* Writing to VR_CTL initiates a PLL relock sequence. */ 2083/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -2088,7 +2088,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2088 if (val == bfin_read_VR_CTL()) 2088 if (val == bfin_read_VR_CTL())
2089 return; 2089 return;
2090 2090
2091 local_irq_save(flags); 2091 local_irq_save_hw(flags);
2092 /* Enable the PLL Wakeup bit in SIC IWR */ 2092 /* Enable the PLL Wakeup bit in SIC IWR */
2093 iwr0 = bfin_read32(SIC_IWR0); 2093 iwr0 = bfin_read32(SIC_IWR0);
2094 iwr1 = bfin_read32(SIC_IWR1); 2094 iwr1 = bfin_read32(SIC_IWR1);
@@ -2102,7 +2102,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2102 2102
2103 bfin_write32(SIC_IWR0, iwr0); 2103 bfin_write32(SIC_IWR0, iwr0);
2104 bfin_write32(SIC_IWR1, iwr1); 2104 bfin_write32(SIC_IWR1, iwr1);
2105 local_irq_restore(flags); 2105 local_irq_restore_hw(flags);
2106} 2106}
2107 2107
2108#endif 2108#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 60bdac4cb6a..fdc87fe2c17 100644
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -81,9 +81,9 @@
81#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */ 81#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
82#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */ 82#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
83#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */ 83#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
84#define IRQ_TMR0 BFIN_IRQ(16) /* Timer 0 */ 84#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
85#define IRQ_TMR1 BFIN_IRQ(17) /* Timer 1 */ 85#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
86#define IRQ_TMR2 BFIN_IRQ(18) /* Timer 2 */ 86#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
87#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */ 87#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
88#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */ 88#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
89#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */ 89#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
@@ -168,9 +168,9 @@
168#define IRQ_UART0_TX_POS 28 168#define IRQ_UART0_TX_POS 28
169 169
170/* IAR2 BIT FIELDS */ 170/* IAR2 BIT FIELDS */
171#define IRQ_TMR0_POS 0 171#define IRQ_TIMER0_POS 0
172#define IRQ_TMR1_POS 4 172#define IRQ_TIMER1_POS 4
173#define IRQ_TMR2_POS 8 173#define IRQ_TIMER2_POS 8
174#define IRQ_PORTF_INTA_POS 12 174#define IRQ_PORTF_INTA_POS 12
175#define IRQ_PORTF_INTB_POS 16 175#define IRQ_PORTF_INTB_POS 16
176#define IRQ_MEM0_DMA0_POS 20 176#define IRQ_MEM0_DMA0_POS 20
diff --git a/arch/blackfin/mach-bf538/ints-priority.c b/arch/blackfin/mach-bf538/ints-priority.c
index f81f2ac9184..70d17e550e0 100644
--- a/arch/blackfin/mach-bf538/ints-priority.c
+++ b/arch/blackfin/mach-bf538/ints-priority.c
@@ -53,9 +53,9 @@ void __init program_IAR(void)
53 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | 53 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
54 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); 54 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
55 55
56 bfin_write_SIC_IAR2(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | 56 bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
57 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | 57 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
58 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | 58 ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
59 ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) | 59 ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
60 ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) | 60 ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
61 ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) | 61 ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index 1bfcd8f646a..dcf65715905 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -250,7 +250,7 @@ config IRQ_OTPSEC
250 default 11 250 default 11
251config IRQ_TIMER0 251config IRQ_TIMER0
252 int "IRQ_TIMER0" 252 int "IRQ_TIMER0"
253 default 11 253 default 8
254config IRQ_TIMER1 254config IRQ_TIMER1
255 int "IRQ_TIMER1" 255 int "IRQ_TIMER1"
256 default 11 256 default 11
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index 0a3b210daad..6e636c418cb 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -2702,7 +2702,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2702 if (val == bfin_read_PLL_CTL()) 2702 if (val == bfin_read_PLL_CTL())
2703 return; 2703 return;
2704 2704
2705 local_irq_save(flags); 2705 local_irq_save_hw(flags);
2706 /* Enable the PLL Wakeup bit in SIC IWR */ 2706 /* Enable the PLL Wakeup bit in SIC IWR */
2707 iwr0 = bfin_read32(SIC_IWR0); 2707 iwr0 = bfin_read32(SIC_IWR0);
2708 iwr1 = bfin_read32(SIC_IWR1); 2708 iwr1 = bfin_read32(SIC_IWR1);
@@ -2719,7 +2719,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2719 bfin_write32(SIC_IWR0, iwr0); 2719 bfin_write32(SIC_IWR0, iwr0);
2720 bfin_write32(SIC_IWR1, iwr1); 2720 bfin_write32(SIC_IWR1, iwr1);
2721 bfin_write32(SIC_IWR2, iwr2); 2721 bfin_write32(SIC_IWR2, iwr2);
2722 local_irq_restore(flags); 2722 local_irq_restore_hw(flags);
2723} 2723}
2724 2724
2725/* Writing to VR_CTL initiates a PLL relock sequence. */ 2725/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -2730,7 +2730,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2730 if (val == bfin_read_VR_CTL()) 2730 if (val == bfin_read_VR_CTL())
2731 return; 2731 return;
2732 2732
2733 local_irq_save(flags); 2733 local_irq_save_hw(flags);
2734 /* Enable the PLL Wakeup bit in SIC IWR */ 2734 /* Enable the PLL Wakeup bit in SIC IWR */
2735 iwr0 = bfin_read32(SIC_IWR0); 2735 iwr0 = bfin_read32(SIC_IWR0);
2736 iwr1 = bfin_read32(SIC_IWR1); 2736 iwr1 = bfin_read32(SIC_IWR1);
@@ -2747,7 +2747,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2747 bfin_write32(SIC_IWR0, iwr0); 2747 bfin_write32(SIC_IWR0, iwr0);
2748 bfin_write32(SIC_IWR1, iwr1); 2748 bfin_write32(SIC_IWR1, iwr1);
2749 bfin_write32(SIC_IWR2, iwr2); 2749 bfin_write32(SIC_IWR2, iwr2);
2750 local_irq_restore(flags); 2750 local_irq_restore_hw(flags);
2751} 2751}
2752 2752
2753#endif /* _CDEF_BF54X_H */ 2753#endif /* _CDEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index ad380d1f587..60299a71e09 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -158,7 +158,7 @@ Events (highest priority) EMU 0
158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ 158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ 159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
160 160
161#define SYS_IRQS IRQ_PINT3 161#define SYS_IRQS IRQ_PINT3
162 162
163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) 163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
164#define IRQ_PA0 BFIN_PA_IRQ(0) 164#define IRQ_PA0 BFIN_PA_IRQ(0)
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
index 5d56438cad2..638ec38ca47 100644
--- a/arch/blackfin/mach-bf561/Kconfig
+++ b/arch/blackfin/mach-bf561/Kconfig
@@ -138,7 +138,7 @@ config IRQ_DMA2_11
138 default 9 138 default 9
139config IRQ_TIMER0 139config IRQ_TIMER0
140 int "TIMER 0 Interrupt" 140 int "TIMER 0 Interrupt"
141 default 10 141 default 8
142config IRQ_TIMER1 142config IRQ_TIMER1
143 int "TIMER 1 Interrupt" 143 int "TIMER 1 Interrupt"
144 default 10 144 default 10
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index b16875d735b..95d609f11c9 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -1537,7 +1537,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1537 if (val == bfin_read_PLL_CTL()) 1537 if (val == bfin_read_PLL_CTL())
1538 return; 1538 return;
1539 1539
1540 local_irq_save(flags); 1540 local_irq_save_hw(flags);
1541 /* Enable the PLL Wakeup bit in SIC IWR */ 1541 /* Enable the PLL Wakeup bit in SIC IWR */
1542 iwr0 = bfin_read32(SICA_IWR0); 1542 iwr0 = bfin_read32(SICA_IWR0);
1543 iwr1 = bfin_read32(SICA_IWR1); 1543 iwr1 = bfin_read32(SICA_IWR1);
@@ -1551,7 +1551,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1551 1551
1552 bfin_write32(SICA_IWR0, iwr0); 1552 bfin_write32(SICA_IWR0, iwr0);
1553 bfin_write32(SICA_IWR1, iwr1); 1553 bfin_write32(SICA_IWR1, iwr1);
1554 local_irq_restore(flags); 1554 local_irq_restore_hw(flags);
1555} 1555}
1556 1556
1557/* Writing to VR_CTL initiates a PLL relock sequence. */ 1557/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -1562,7 +1562,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1562 if (val == bfin_read_VR_CTL()) 1562 if (val == bfin_read_VR_CTL())
1563 return; 1563 return;
1564 1564
1565 local_irq_save(flags); 1565 local_irq_save_hw(flags);
1566 /* Enable the PLL Wakeup bit in SIC IWR */ 1566 /* Enable the PLL Wakeup bit in SIC IWR */
1567 iwr0 = bfin_read32(SICA_IWR0); 1567 iwr0 = bfin_read32(SICA_IWR0);
1568 iwr1 = bfin_read32(SICA_IWR1); 1568 iwr1 = bfin_read32(SICA_IWR1);
@@ -1576,7 +1576,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1576 1576
1577 bfin_write32(SICA_IWR0, iwr0); 1577 bfin_write32(SICA_IWR0, iwr0);
1578 bfin_write32(SICA_IWR1, iwr1); 1578 bfin_write32(SICA_IWR1, iwr1);
1579 local_irq_restore(flags); 1579 local_irq_restore_hw(flags);
1580} 1580}
1581 1581
1582#endif /* _CDEF_BF561_H */ 1582#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 56f68d879b3..72e16605ca0 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -104,7 +104,7 @@ static int bfin_target(struct cpufreq_policy *policy,
104 cclk_hz, target_freq, freqs.old); 104 cclk_hz, target_freq, freqs.old);
105 105
106 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 106 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
107 local_irq_save(flags); 107 local_irq_save_hw(flags);
108 plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel; 108 plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
109 tscale = dpm_state_table[index].tscale; 109 tscale = dpm_state_table[index].tscale;
110 bfin_write_PLL_DIV(plldiv); 110 bfin_write_PLL_DIV(plldiv);
@@ -115,7 +115,7 @@ static int bfin_target(struct cpufreq_policy *policy,
115 cycles += 10; /* ~10 cycles we lose after get_cycles() */ 115 cycles += 10; /* ~10 cycles we lose after get_cycles() */
116 __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index); 116 __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index);
117 __bfin_cycles_mod = index; 117 __bfin_cycles_mod = index;
118 local_irq_restore(flags); 118 local_irq_restore_hw(flags);
119 /* TODO: just test case for cycles clock source, remove later */ 119 /* TODO: just test case for cycles clock source, remove later */
120 pr_debug("cpufreq: done\n"); 120 pr_debug("cpufreq: done\n");
121 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 121 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 2604b532897..c1bdd1edc8e 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -129,8 +129,15 @@ __common_int_entry:
129#endif 129#endif
130 r1 = sp; 130 r1 = sp;
131 SP += -12; 131 SP += -12;
132#ifdef CONFIG_IPIPE
133 call ___ipipe_grab_irq
134 SP += 12;
135 cc = r0 == 0;
136 if cc jump .Lcommon_restore_context;
137#else /* CONFIG_IPIPE */
132 call _do_irq; 138 call _do_irq;
133 SP += 12; 139 SP += 12;
140#endif /* CONFIG_IPIPE */
134 call _return_from_int; 141 call _return_from_int;
135.Lcommon_restore_context: 142.Lcommon_restore_context:
136 RESTORE_CONTEXT 143 RESTORE_CONTEXT
@@ -247,3 +254,56 @@ ENTRY(_evt_system_call)
247 call _system_call; 254 call _system_call;
248 jump .Lcommon_restore_context; 255 jump .Lcommon_restore_context;
249ENDPROC(_evt_system_call) 256ENDPROC(_evt_system_call)
257
258#ifdef CONFIG_IPIPE
259ENTRY(___ipipe_call_irqtail)
260 r0.l = 1f;
261 r0.h = 1f;
262 reti = r0;
263 rti;
2641:
265 [--sp] = rets;
266 [--sp] = ( r7:4, p5:3 );
267 p0.l = ___ipipe_irq_tail_hook;
268 p0.h = ___ipipe_irq_tail_hook;
269 p0 = [p0];
270 sp += -12;
271 call (p0);
272 sp += 12;
273 ( r7:4, p5:3 ) = [sp++];
274 rets = [sp++];
275
276 [--sp] = reti;
277 reti = [sp++]; /* IRQs are off. */
278 r0.h = 3f;
279 r0.l = 3f;
280 p0.l = lo(EVT14);
281 p0.h = hi(EVT14);
282 [p0] = r0;
283 csync;
284 r0 = 0x401f;
285 sti r0;
286 raise 14;
287 [--sp] = reti; /* IRQs on. */
2882:
289 jump 2b; /* Likely paranoid. */
2903:
291 sp += 4; /* Discard saved RETI */
292 r0.h = _evt14_softirq;
293 r0.l = _evt14_softirq;
294 p0.l = lo(EVT14);
295 p0.h = hi(EVT14);
296 [p0] = r0;
297 csync;
298 p0.l = _bfin_irq_flags;
299 p0.h = _bfin_irq_flags;
300 r0 = [p0];
301 sti r0;
302#if 0 /* FIXME: this actually raises scheduling latencies */
303 /* Reenable interrupts */
304 [--sp] = reti;
305 r0 = [sp++];
306#endif
307 rts;
308ENDPROC(___ipipe_call_irqtail)
309#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 7c1db775751..1bba6030dce 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -34,6 +34,9 @@
34#include <linux/kernel_stat.h> 34#include <linux/kernel_stat.h>
35#include <linux/seq_file.h> 35#include <linux/seq_file.h>
36#include <linux/irq.h> 36#include <linux/irq.h>
37#ifdef CONFIG_IPIPE
38#include <linux/ipipe.h>
39#endif
37#ifdef CONFIG_KGDB 40#ifdef CONFIG_KGDB
38#include <linux/kgdb.h> 41#include <linux/kgdb.h>
39#endif 42#endif
@@ -135,8 +138,8 @@ static void bfin_ack_noop(unsigned int irq)
135static void bfin_core_mask_irq(unsigned int irq) 138static void bfin_core_mask_irq(unsigned int irq)
136{ 139{
137 bfin_irq_flags &= ~(1 << irq); 140 bfin_irq_flags &= ~(1 << irq);
138 if (!irqs_disabled()) 141 if (!irqs_disabled_hw())
139 local_irq_enable(); 142 local_irq_enable_hw();
140} 143}
141 144
142static void bfin_core_unmask_irq(unsigned int irq) 145static void bfin_core_unmask_irq(unsigned int irq)
@@ -151,8 +154,8 @@ static void bfin_core_unmask_irq(unsigned int irq)
151 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly 154 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
152 * what we need. 155 * what we need.
153 */ 156 */
154 if (!irqs_disabled()) 157 if (!irqs_disabled_hw())
155 local_irq_enable(); 158 local_irq_enable_hw();
156 return; 159 return;
157} 160}
158 161
@@ -235,7 +238,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
235 break; 238 break;
236 } 239 }
237 240
238 local_irq_save(flags); 241 local_irq_save_hw(flags);
239 242
240 if (state) { 243 if (state) {
241 bfin_sic_iwr[bank] |= (1 << bit); 244 bfin_sic_iwr[bank] |= (1 << bit);
@@ -246,7 +249,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
246 vr_wakeup &= ~wakeup; 249 vr_wakeup &= ~wakeup;
247 } 250 }
248 251
249 local_irq_restore(flags); 252 local_irq_restore_hw(flags);
250 253
251 return 0; 254 return 0;
252} 255}
@@ -272,6 +275,19 @@ static struct irq_chip bfin_internal_irqchip = {
272#endif 275#endif
273}; 276};
274 277
278static void bfin_handle_irq(unsigned irq)
279{
280#ifdef CONFIG_IPIPE
281 struct pt_regs regs; /* Contents not used. */
282 ipipe_trace_irq_entry(irq);
283 __ipipe_handle_irq(irq, &regs);
284 ipipe_trace_irq_exit(irq);
285#else /* !CONFIG_IPIPE */
286 struct irq_desc *desc = irq_desc + irq;
287 desc->handle_irq(irq, desc);
288#endif /* !CONFIG_IPIPE */
289}
290
275#ifdef BF537_GENERIC_ERROR_INT_DEMUX 291#ifdef BF537_GENERIC_ERROR_INT_DEMUX
276static int error_int_mask; 292static int error_int_mask;
277 293
@@ -325,10 +341,9 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
325 irq = IRQ_UART1_ERROR; 341 irq = IRQ_UART1_ERROR;
326 342
327 if (irq) { 343 if (irq) {
328 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) { 344 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
329 struct irq_desc *desc = irq_desc + irq; 345 bfin_handle_irq(irq);
330 desc->handle_irq(irq, desc); 346 else {
331 } else {
332 347
333 switch (irq) { 348 switch (irq) {
334 case IRQ_PPI_ERROR: 349 case IRQ_PPI_ERROR:
@@ -374,10 +389,14 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
374 389
375static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) 390static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
376{ 391{
392#ifdef CONFIG_IPIPE
393 _set_irq_handler(irq, handle_edge_irq);
394#else
377 struct irq_desc *desc = irq_desc + irq; 395 struct irq_desc *desc = irq_desc + irq;
378 /* May not call generic set_irq_handler() due to spinlock 396 /* May not call generic set_irq_handler() due to spinlock
379 recursion. */ 397 recursion. */
380 desc->handle_irq = handle; 398 desc->handle_irq = handle;
399#endif
381} 400}
382 401
383static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); 402static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
@@ -563,10 +582,8 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
563 mask = get_gpiop_data(i) & get_gpiop_maska(i); 582 mask = get_gpiop_data(i) & get_gpiop_maska(i);
564 583
565 while (mask) { 584 while (mask) {
566 if (mask & 1) { 585 if (mask & 1)
567 desc = irq_desc + irq; 586 bfin_handle_irq(irq);
568 desc->handle_irq(irq, desc);
569 }
570 irq++; 587 irq++;
571 mask >>= 1; 588 mask >>= 1;
572 } 589 }
@@ -576,10 +593,8 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
576 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); 593 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
577 594
578 do { 595 do {
579 if (mask & 1) { 596 if (mask & 1)
580 desc = irq_desc + irq; 597 bfin_handle_irq(irq);
581 desc->handle_irq(irq, desc);
582 }
583 irq++; 598 irq++;
584 mask >>= 1; 599 mask >>= 1;
585 } while (mask); 600 } while (mask);
@@ -900,8 +915,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
900 while (request) { 915 while (request) {
901 if (request & 1) { 916 if (request & 1) {
902 irq = pint2irq_lut[pint_val] + SYS_IRQS; 917 irq = pint2irq_lut[pint_val] + SYS_IRQS;
903 desc = irq_desc + irq; 918 bfin_handle_irq(irq);
904 desc->handle_irq(irq, desc);
905 } 919 }
906 pint_val++; 920 pint_val++;
907 request >>= 1; 921 request >>= 1;
@@ -1025,11 +1039,10 @@ int __init init_arch_irq(void)
1025 break; 1039 break;
1026#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1040#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1027 case IRQ_GENERIC_ERROR: 1041 case IRQ_GENERIC_ERROR:
1028 set_irq_handler(irq, bfin_demux_error_irq); 1042 set_irq_chained_handler(irq, bfin_demux_error_irq);
1029
1030 break; 1043 break;
1031#endif 1044#endif
1032#ifdef CONFIG_TICK_SOURCE_SYSTMR0 1045#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
1033 case IRQ_TIMER0: 1046 case IRQ_TIMER0:
1034 set_irq_handler(irq, handle_percpu_irq); 1047 set_irq_handler(irq, handle_percpu_irq);
1035 break; 1048 break;
@@ -1041,7 +1054,17 @@ int __init init_arch_irq(void)
1041 break; 1054 break;
1042#endif 1055#endif
1043 default: 1056 default:
1057#ifdef CONFIG_IPIPE
1058 /*
1059 * We want internal interrupt sources to be masked, because
1060 * ISRs may trigger interrupts recursively (e.g. DMA), but
1061 * interrupts are _not_ masked at CPU level. So let's handle
1062 * them as level interrupts.
1063 */
1064 set_irq_handler(irq, handle_level_irq);
1065#else /* !CONFIG_IPIPE */
1044 set_irq_handler(irq, handle_simple_irq); 1066 set_irq_handler(irq, handle_simple_irq);
1067#endif /* !CONFIG_IPIPE */
1045 break; 1068 break;
1046 } 1069 }
1047 } 1070 }
@@ -1101,6 +1124,14 @@ int __init init_arch_irq(void)
1101 bfin_write_SIC_IWR(IWR_DISABLE_ALL); 1124 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1102#endif 1125#endif
1103 1126
1127#ifdef CONFIG_IPIPE
1128 for (irq = 0; irq < NR_IRQS; irq++) {
1129 struct irq_desc *desc = irq_desc + irq;
1130 desc->ic_prio = __ipipe_get_irq_priority(irq);
1131 desc->thr_prio = __ipipe_get_irqthread_priority(irq);
1132 }
1133#endif /* CONFIG_IPIPE */
1134
1104 return 0; 1135 return 0;
1105} 1136}
1106 1137
@@ -1156,3 +1187,161 @@ void do_irq(int vec, struct pt_regs *fp)
1156 } 1187 }
1157 asm_do_IRQ(vec, fp); 1188 asm_do_IRQ(vec, fp);
1158} 1189}
1190
1191#ifdef CONFIG_IPIPE
1192
1193int __ipipe_get_irq_priority(unsigned irq)
1194{
1195 int ient, prio;
1196
1197 if (irq <= IRQ_CORETMR)
1198 return irq;
1199
1200 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1201 struct ivgx *ivg = ivg_table + ient;
1202 if (ivg->irqno == irq) {
1203 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1204 if (ivg7_13[prio].ifirst <= ivg &&
1205 ivg7_13[prio].istop > ivg)
1206 return IVG7 + prio;
1207 }
1208 }
1209 }
1210
1211 return IVG15;
1212}
1213
1214int __ipipe_get_irqthread_priority(unsigned irq)
1215{
1216 int ient, prio;
1217 int demux_irq;
1218
1219 /* The returned priority value is rescaled to [0..IVG13+1]
1220 * with 0 being the lowest effective priority level. */
1221
1222 if (irq <= IRQ_CORETMR)
1223 return IVG13 - irq + 1;
1224
1225 /* GPIO IRQs are given the priority of the demux
1226 * interrupt. */
1227 if (IS_GPIOIRQ(irq)) {
1228#if defined(CONFIG_BF54x)
1229 u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]);
1230 demux_irq = (bank == 0 ? IRQ_PINT0 :
1231 bank == 1 ? IRQ_PINT1 :
1232 bank == 2 ? IRQ_PINT2 :
1233 IRQ_PINT3);
1234#elif defined(CONFIG_BF561)
1235 demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA :
1236 irq >= IRQ_PF16 ? IRQ_PROG1_INTA :
1237 IRQ_PROG0_INTA);
1238#elif defined(CONFIG_BF52x)
1239 demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA :
1240 irq >= IRQ_PG0 ? IRQ_PORTG_INTA :
1241 IRQ_PORTF_INTA);
1242#else
1243 demux_irq = irq;
1244#endif
1245 return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1;
1246 }
1247
1248 /* The GPIO demux interrupt is given a lower priority
1249 * than the GPIO IRQs, so that its threaded handler
1250 * unmasks the interrupt line after the decoded IRQs
1251 * have been processed. */
1252 prio = PRIO_GPIODEMUX(irq);
1253 /* demux irq? */
1254 if (prio != -1)
1255 return IVG13 - prio;
1256
1257 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1258 struct ivgx *ivg = ivg_table + ient;
1259 if (ivg->irqno == irq) {
1260 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1261 if (ivg7_13[prio].ifirst <= ivg &&
1262 ivg7_13[prio].istop > ivg)
1263 return IVG7 - prio;
1264 }
1265 }
1266 }
1267
1268 return 0;
1269}
1270
1271/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1272#ifdef CONFIG_DO_IRQ_L1
1273__attribute__((l1_text))
1274#endif
1275asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1276{
1277 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1278 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1279 int irq;
1280
1281 if (likely(vec == EVT_IVTMR_P)) {
1282 irq = IRQ_CORETMR;
1283 goto handle_irq;
1284 }
1285
1286 SSYNC();
1287
1288#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1289 {
1290 unsigned long sic_status[3];
1291
1292 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1293 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1294#ifdef CONFIG_BF54x
1295 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1296#endif
1297 for (;; ivg++) {
1298 if (ivg >= ivg_stop) {
1299 atomic_inc(&num_spurious);
1300 return 0;
1301 }
1302 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1303 break;
1304 }
1305 }
1306#else
1307 {
1308 unsigned long sic_status;
1309
1310 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1311
1312 for (;; ivg++) {
1313 if (ivg >= ivg_stop) {
1314 atomic_inc(&num_spurious);
1315 return 0;
1316 } else if (sic_status & ivg->isrflag)
1317 break;
1318 }
1319 }
1320#endif
1321
1322 irq = ivg->irqno;
1323
1324 if (irq == IRQ_SYSTMR) {
1325 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1326 /* This is basically what we need from the register frame. */
1327 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1328 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1329 if (!ipipe_root_domain_p)
1330 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1331 else
1332 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1333 }
1334
1335handle_irq:
1336
1337 ipipe_trace_irq_entry(irq);
1338 __ipipe_handle_irq(irq, regs);
1339 ipipe_trace_irq_exit(irq);
1340
1341 if (ipipe_root_domain_p)
1342 return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
1343
1344 return 0;
1345}
1346
1347#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 96600b8cb6a..d3d70fd67c1 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -71,7 +71,7 @@ void bfin_pm_suspend_standby_enter(void)
71 gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE); 71 gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
72#endif 72#endif
73 73
74 local_irq_save(flags); 74 local_irq_save_hw(flags);
75 bfin_pm_standby_setup(); 75 bfin_pm_standby_setup();
76 76
77#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER 77#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
@@ -105,7 +105,7 @@ void bfin_pm_suspend_standby_enter(void)
105 bfin_write_SIC_IWR(IWR_DISABLE_ALL); 105 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
106#endif 106#endif
107 107
108 local_irq_restore(flags); 108 local_irq_restore_hw(flags);
109} 109}
110 110
111int bf53x_suspend_l1_mem(unsigned char *memptr) 111int bf53x_suspend_l1_mem(unsigned char *memptr)
@@ -249,12 +249,12 @@ int bfin_pm_suspend_mem_enter(void)
249 wakeup |= GPWE; 249 wakeup |= GPWE;
250#endif 250#endif
251 251
252 local_irq_save(flags); 252 local_irq_save_hw(flags);
253 253
254 ret = blackfin_dma_suspend(); 254 ret = blackfin_dma_suspend();
255 255
256 if (ret) { 256 if (ret) {
257 local_irq_restore(flags); 257 local_irq_restore_hw(flags);
258 kfree(memptr); 258 kfree(memptr);
259 return ret; 259 return ret;
260 } 260 }
@@ -275,7 +275,7 @@ int bfin_pm_suspend_mem_enter(void)
275 bfin_gpio_pm_hibernate_restore(); 275 bfin_gpio_pm_hibernate_restore();
276 blackfin_dma_resume(); 276 blackfin_dma_resume();
277 277
278 local_irq_restore(flags); 278 local_irq_restore_hw(flags);
279 kfree(memptr); 279 kfree(memptr);
280 280
281 return 0; 281 return 0;
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 66c47a702da..77c99284709 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -348,7 +348,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
348 348
349static void __cpuinit setup_secondary(unsigned int cpu) 349static void __cpuinit setup_secondary(unsigned int cpu)
350{ 350{
351#ifndef CONFIG_TICK_SOURCE_SYSTMR0 351#if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE))
352 struct irq_desc *timer_desc; 352 struct irq_desc *timer_desc;
353#endif 353#endif
354 unsigned long ilat; 354 unsigned long ilat;
@@ -369,7 +369,7 @@ static void __cpuinit setup_secondary(unsigned int cpu)
369 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 369 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
370 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 370 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
371 371
372#ifdef CONFIG_TICK_SOURCE_SYSTMR0 372#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
373 /* Power down the core timer, just to play safe. */ 373 /* Power down the core timer, just to play safe. */
374 bfin_write_TCNTL(0); 374 bfin_write_TCNTL(0);
375 375
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 06:33:33 -0500