12 files changed, 32 insertions, 34 deletions

diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index e48640cfac0..6882a735d9c 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -7,7 +7,7 @@
 #include <asm/pat.h>
 #include <asm/processor.h>
 
-#include <asm/genapic.h>
+#include <asm/apic.h>
 
 struct cpuid_bit {
         u16 feature;
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index ff4d7b9e32e..25423a5b80e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -12,8 +12,6 @@
 # include <asm/cacheflush.h>
 #endif
 
-#include <asm/genapic.h>
-
 #include "cpu.h"
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 4db150ed446..826d5c87627 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -23,11 +23,9 @@
 #include <asm/smp.h>
 #include <asm/cpu.h>
 #include <asm/cpumask.h>
-#ifdef CONFIG_X86_LOCAL_APIC
-#include <asm/mpspec.h>
 #include <asm/apic.h>
-#include <asm/genapic.h>
-#include <asm/genapic.h>
+
+#ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/uv/uv.h>
 #endif
 
@@ -1051,7 +1049,7 @@ void __cpuinit cpu_init(void)
         barrier();
 
         check_efer();
-        if (cpu != 0 && x2apic)
+        if (cpu != 0)
                 enable_x2apic();
 
         /*
diff --git a/arch/x86/kernel/cpu/cpufreq/e_powersaver.c b/arch/x86/kernel/cpu/cpufreq/e_powersaver.c
index c2f930d8664..41ab3f064cb 100644
--- a/arch/x86/kernel/cpu/cpufreq/e_powersaver.c
+++ b/arch/x86/kernel/cpu/cpufreq/e_powersaver.c
@@ -204,12 +204,12 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
         }
         /* Enable Enhanced PowerSaver */
         rdmsrl(MSR_IA32_MISC_ENABLE, val);
-        if (!(val & 1 << 16)) {
-                val |= 1 << 16;
+        if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
+                val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
                 wrmsrl(MSR_IA32_MISC_ENABLE, val);
                 /* Can be locked at 0 */
                 rdmsrl(MSR_IA32_MISC_ENABLE, val);
-                if (!(val & 1 << 16)) {
+                if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
                         printk(KERN_INFO "eps: Can't enable Enhanced PowerSaver\n");
                         return -ENODEV;
                 }
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index fb039cd345d..6428aa17b40 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1157,8 +1157,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
         data->cpu = pol->cpu;
         data->currpstate = HW_PSTATE_INVALID;
 
-        rc = powernow_k8_cpu_init_acpi(data);
-        if (rc) {
+        if (powernow_k8_cpu_init_acpi(data)) {
                 /*
                  * Use the PSB BIOS structure. This is only availabe on
                  * an UP version, and is deprecated by AMD.
@@ -1176,17 +1175,20 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
                                "ACPI maintainers and complain to your BIOS "
                                "vendor.\n");
 #endif
-                        goto err_out;
+                        kfree(data);
+                        return -ENODEV;
                 }
                 if (pol->cpu != 0) {
                         printk(KERN_ERR FW_BUG PFX "No ACPI _PSS objects for "
                                "CPU other than CPU0. Complain to your BIOS "
                                "vendor.\n");
-                        goto err_out;
+                        kfree(data);
+                        return -ENODEV;
                 }
                 rc = find_psb_table(data);
                 if (rc) {
-                        goto err_out;
+                        kfree(data);
+                        return -ENODEV;
                 }
                 /* Take a crude guess here.
                  * That guess was in microseconds, so multiply with 1000 */
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
index f08998278a3..c9f1fdc0283 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -390,14 +390,14 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
            enable it if not. */
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 
-        if (!(l & (1<<16))) {
-                l |= (1<<16);
+        if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
+                l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
 
                 /* check to see if it stuck */
                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-                if (!(l & (1<<16))) {
+                if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
                         printk(KERN_INFO PFX
                                 "couldn't enable Enhanced SpeedStep\n");
                         return -ENODEV;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1f137a87d4b..25c559ba8d5 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -24,7 +24,6 @@
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/mpspec.h>
 #include <asm/apic.h>
-#include <asm/genapic.h>
 #endif
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
@@ -147,10 +146,10 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
          */
         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
-                if ((lo & (1<<9)) == 0) {
+                if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
-                        lo |= (1<<9);   /* Disable hw prefetching */
+                        lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
                 }
         }
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c
index 1c838032fd3..fe79985ce0f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -295,11 +295,11 @@ void do_machine_check(struct pt_regs * regs, long error_code)
                  * If we know that the error was in user space, send a
                  * SIGBUS.  Otherwise, panic if tolerance is low.
                  *
-                 * do_exit() takes an awful lot of locks and has a slight
+                 * force_sig() takes an awful lot of locks and has a slight
                  * risk of deadlocking.
                  */
                 if (user_space) {
-                        do_exit(SIGBUS);
+                        force_sig(SIGBUS, current);
                 } else if (panic_on_oops || tolerant < 2) {
                         mce_panic("Uncorrected machine check",
                                 &panicm, mcestart);
@@ -490,7 +490,7 @@ static void __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
 
 }
 
-static void __cpuinit mce_cpu_features(struct cpuinfo_x86 *c)
+static void mce_cpu_features(struct cpuinfo_x86 *c)
 {
         switch (c->x86_vendor) {
         case X86_VENDOR_INTEL:
@@ -734,6 +734,7 @@ __setup("mce=", mcheck_enable);
 static int mce_resume(struct sys_device *dev)
 {
         mce_init(NULL);
+        mce_cpu_features(&current_cpu_data);
         return 0;
 }
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
index 4772e91e824..9817506dd46 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
@@ -121,7 +121,7 @@ static long threshold_restart_bank(void *_tr)
 }
 
 /* cpu init entry point, called from mce.c with preempt off */
-void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
+void mce_amd_feature_init(struct cpuinfo_x86 *c)
 {
         unsigned int bank, block;
         unsigned int cpu = smp_processor_id();
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
index 5e8c79e748a..aa5e287c98e 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
@@ -31,7 +31,7 @@ asmlinkage void smp_thermal_interrupt(void)
         irq_exit();
 }
 
-static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
+static void intel_init_thermal(struct cpuinfo_x86 *c)
 {
         u32 l, h;
         int tm2 = 0;
@@ -49,13 +49,13 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
          */
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         h = apic_read(APIC_LVTTHMR);
-        if ((l & (1 << 3)) && (h & APIC_DM_SMI)) {
+        if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
                 printk(KERN_DEBUG
                        "CPU%d: Thermal monitoring handled by SMI\n", cpu);
                 return;
         }
 
-        if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13)))
+        if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
                 tm2 = 1;
 
         if (h & APIC_VECTOR_MASK) {
@@ -73,7 +73,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
         wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
 
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-        wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
+        wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
 
         l = apic_read(APIC_LVTTHMR);
         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
@@ -85,7 +85,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
         return;
 }
 
-void __cpuinit mce_intel_feature_init(struct cpuinfo_x86 *c)
+void mce_intel_feature_init(struct cpuinfo_x86 *c)
 {
         intel_init_thermal(c);
 }
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c
index 9b60fce09f7..f53bdcbaf38 100644
--- a/arch/x86/kernel/cpu/mcheck/p4.c
+++ b/arch/x86/kernel/cpu/mcheck/p4.c
@@ -85,7 +85,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
          */
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         h = apic_read(APIC_LVTTHMR);
-        if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
+        if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
                 printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
                                 cpu);
                 return; /* -EBUSY */
@@ -111,7 +111,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
         vendor_thermal_interrupt = intel_thermal_interrupt;
 
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-        wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
+        wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
 
         l = apic_read(APIC_LVTTHMR);
         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 9abd48b2267..f6c70a164e3 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -19,7 +19,7 @@
 #include <linux/nmi.h>
 #include <linux/kprobes.h>
 
-#include <asm/apic.h>
+#include <asm/genapic.h>
 #include <asm/intel_arch_perfmon.h>
 
 struct nmi_watchdog_ctlblk {