diff options
Diffstat (limited to 'arch/sparc/include/asm/dma-mapping_64.h')
-rw-r--r-- | arch/sparc/include/asm/dma-mapping_64.h | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/arch/sparc/include/asm/dma-mapping_64.h b/arch/sparc/include/asm/dma-mapping_64.h index bfa64f9702d..017ae706ac6 100644 --- a/arch/sparc/include/asm/dma-mapping_64.h +++ b/arch/sparc/include/asm/dma-mapping_64.h | |||
@@ -4,8 +4,6 @@ | |||
4 | #include <linux/scatterlist.h> | 4 | #include <linux/scatterlist.h> |
5 | #include <linux/mm.h> | 5 | #include <linux/mm.h> |
6 | 6 | ||
7 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) | ||
8 | |||
9 | struct dma_ops { | 7 | struct dma_ops { |
10 | void *(*alloc_coherent)(struct device *dev, size_t size, | 8 | void *(*alloc_coherent)(struct device *dev, size_t size, |
11 | dma_addr_t *dma_handle, gfp_t flag); | 9 | dma_addr_t *dma_handle, gfp_t flag); |
@@ -31,9 +29,6 @@ struct dma_ops { | |||
31 | }; | 29 | }; |
32 | extern const struct dma_ops *dma_ops; | 30 | extern const struct dma_ops *dma_ops; |
33 | 31 | ||
34 | extern int dma_supported(struct device *dev, u64 mask); | ||
35 | extern int dma_set_mask(struct device *dev, u64 dma_mask); | ||
36 | |||
37 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | 32 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, |
38 | dma_addr_t *dma_handle, gfp_t flag) | 33 | dma_addr_t *dma_handle, gfp_t flag) |
39 | { | 34 | { |
@@ -102,25 +97,6 @@ static inline void dma_sync_single_for_device(struct device *dev, | |||
102 | /* No flushing needed to sync cpu writes to the device. */ | 97 | /* No flushing needed to sync cpu writes to the device. */ |
103 | } | 98 | } |
104 | 99 | ||
105 | static inline void dma_sync_single_range_for_cpu(struct device *dev, | ||
106 | dma_addr_t dma_handle, | ||
107 | unsigned long offset, | ||
108 | size_t size, | ||
109 | enum dma_data_direction direction) | ||
110 | { | ||
111 | dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction); | ||
112 | } | ||
113 | |||
114 | static inline void dma_sync_single_range_for_device(struct device *dev, | ||
115 | dma_addr_t dma_handle, | ||
116 | unsigned long offset, | ||
117 | size_t size, | ||
118 | enum dma_data_direction direction) | ||
119 | { | ||
120 | /* No flushing needed to sync cpu writes to the device. */ | ||
121 | } | ||
122 | |||
123 | |||
124 | static inline void dma_sync_sg_for_cpu(struct device *dev, | 100 | static inline void dma_sync_sg_for_cpu(struct device *dev, |
125 | struct scatterlist *sg, int nelems, | 101 | struct scatterlist *sg, int nelems, |
126 | enum dma_data_direction direction) | 102 | enum dma_data_direction direction) |
@@ -135,20 +111,4 @@ static inline void dma_sync_sg_for_device(struct device *dev, | |||
135 | /* No flushing needed to sync cpu writes to the device. */ | 111 | /* No flushing needed to sync cpu writes to the device. */ |
136 | } | 112 | } |
137 | 113 | ||
138 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | ||
139 | { | ||
140 | return (dma_addr == DMA_ERROR_CODE); | ||
141 | } | ||
142 | |||
143 | static inline int dma_get_cache_alignment(void) | ||
144 | { | ||
145 | /* no easy way to get cache size on all processors, so return | ||
146 | * the maximum possible, to be safe */ | ||
147 | return (1 << INTERNODE_CACHE_SHIFT); | ||
148 | } | ||
149 | |||
150 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) | ||
151 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | ||
152 | #define dma_is_consistent(d, h) (1) | ||
153 | |||
154 | #endif /* _ASM_SPARC64_DMA_MAPPING_H */ | 114 | #endif /* _ASM_SPARC64_DMA_MAPPING_H */ |