diff options
Diffstat (limited to 'arch/sh')
-rw-r--r-- | arch/sh/Kconfig | 6 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/clock.c | 13 |
2 files changed, 1 insertions, 18 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 01bc7d589af..504d56f8ca7 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig | |||
@@ -396,14 +396,8 @@ source "arch/sh/boards/renesas/hs7751rvoip/Kconfig" | |||
396 | 396 | ||
397 | source "arch/sh/boards/renesas/rts7751r2d/Kconfig" | 397 | source "arch/sh/boards/renesas/rts7751r2d/Kconfig" |
398 | 398 | ||
399 | config SH_PCLK_FREQ_BOOL | ||
400 | bool "Set default pclk frequency" | ||
401 | default y if !SH_RTC | ||
402 | default n | ||
403 | |||
404 | config SH_PCLK_FREQ | 399 | config SH_PCLK_FREQ |
405 | int "Peripheral clock frequency (in Hz)" | 400 | int "Peripheral clock frequency (in Hz)" |
406 | depends on SH_PCLK_FREQ_BOOL | ||
407 | default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780 | 401 | default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780 |
408 | default "60000000" if CPU_SUBTYPE_SH7751 | 402 | default "60000000" if CPU_SUBTYPE_SH7751 |
409 | default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7760 | 403 | default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7760 |
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c index 989e7fdd524..97fa37f42b8 100644 --- a/arch/sh/kernel/cpu/clock.c +++ b/arch/sh/kernel/cpu/clock.c | |||
@@ -38,9 +38,7 @@ static DECLARE_MUTEX(clock_list_sem); | |||
38 | static struct clk master_clk = { | 38 | static struct clk master_clk = { |
39 | .name = "master_clk", | 39 | .name = "master_clk", |
40 | .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES, | 40 | .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES, |
41 | #ifdef CONFIG_SH_PCLK_FREQ_BOOL | ||
42 | .rate = CONFIG_SH_PCLK_FREQ, | 41 | .rate = CONFIG_SH_PCLK_FREQ, |
43 | #endif | ||
44 | }; | 42 | }; |
45 | 43 | ||
46 | static struct clk module_clk = { | 44 | static struct clk module_clk = { |
@@ -227,16 +225,7 @@ int __init clk_init(void) | |||
227 | { | 225 | { |
228 | int i, ret = 0; | 226 | int i, ret = 0; |
229 | 227 | ||
230 | if (unlikely(!master_clk.rate)) | 228 | BUG_ON(unlikely(!master_clk.rate)); |
231 | /* | ||
232 | * NOTE: This will break if the default divisor has been | ||
233 | * changed. | ||
234 | * | ||
235 | * No one should be changing the default on us however, | ||
236 | * expect that a sane value for CONFIG_SH_PCLK_FREQ will | ||
237 | * be defined in the event of a different divisor. | ||
238 | */ | ||
239 | master_clk.rate = get_timer_frequency() * 4; | ||
240 | 229 | ||
241 | for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) { | 230 | for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) { |
242 | struct clk *clk = onchip_clocks[i]; | 231 | struct clk *clk = onchip_clocks[i]; |