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-rw-r--r--arch/powerpc/boot/dts/amigaone.dts173
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts28
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts49
-rw-r--r--arch/powerpc/boot/dts/digsy_mtc.dts254
-rw-r--r--arch/powerpc/boot/dts/gef_ppc9a.dts364
-rw-r--r--arch/powerpc/boot/dts/gef_sbc310.dts364
-rw-r--r--arch/powerpc/boot/dts/gef_sbc610.dts2
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts52
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts63
-rw-r--r--arch/powerpc/boot/dts/media5200.dts318
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts42
-rw-r--r--arch/powerpc/boot/dts/mpc8315erdb.dts64
-rw-r--r--arch/powerpc/boot/dts/mpc8377_mds.dts71
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts102
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts71
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts102
-rw-r--r--arch/powerpc/boot/dts/mpc8379_mds.dts7
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts38
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts10
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_36b.dts787
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts10
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts6
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts2
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts182
-rw-r--r--arch/powerpc/boot/dts/pcm032.dts392
-rw-r--r--arch/powerpc/boot/dts/redwood.dts244
-rw-r--r--arch/powerpc/boot/dts/tqm5200.dts32
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts5
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts5
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts5
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts9
-rw-r--r--arch/powerpc/boot/dts/virtex440-ml507.dts124
34 files changed, 3641 insertions, 354 deletions
diff --git a/arch/powerpc/boot/dts/amigaone.dts b/arch/powerpc/boot/dts/amigaone.dts
new file mode 100644
index 00000000000..26549fca2ed
--- /dev/null
+++ b/arch/powerpc/boot/dts/amigaone.dts
@@ -0,0 +1,173 @@
1/*
2 * AmigaOne Device Tree Source
3 *
4 * Copyright 2008 Gerhard Pircher (gerhard_pircher@gmx.net)
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "AmigaOne";
16 compatible = "eyetech,amigaone";
17 coherency-off;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 cpus {
22 #cpus = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>; // 32 bytes
30 i-cache-line-size = <32>; // 32 bytes
31 d-cache-size = <32768>; // L1, 32K
32 i-cache-size = <32768>; // L1, 32K
33 timebase-frequency = <0>; // 33.3 MHz, from U-boot
34 clock-frequency = <0>; // From U-boot
35 bus-frequency = <0>; // From U-boot
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0 0>; // From U-boot
42 };
43
44 pci@80000000 {
45 device_type = "pci";
46 compatible = "mai-logic,articia-s";
47 bus-frequency = <33333333>;
48 bus-range = <0 0xff>;
49 ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
50 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
51 0x02000000 0 0x00000000 0xfd000000 0 0x01000000>; // PCI alias memory (ISA)
52 // Configuration address and data register.
53 reg = <0xfec00cf8 4
54 0xfee00cfc 4>;
55 8259-interrupt-acknowledge = <0xfef00000>;
56 // Do not define a interrupt-parent here, if there is no
57 // interrupt-map property.
58 #address-cells = <3>;
59 #size-cells = <2>;
60
61 isa@7 {
62 device_type = "isa";
63 compatible = "pciclass,0601";
64 vendor-id = <0x00001106>;
65 device-id = <0x00000686>;
66 revision-id = <0x00000010>;
67 class-code = <0x00060100>;
68 subsystem-id = <0>;
69 subsystem-vendor-id = <0>;
70 devsel-speed = <0x00000001>;
71 min-grant = <0>;
72 max-latency = <0>;
73 /* First 64k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */
74 ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00010000>;
75 interrupt-parent = <&i8259>;
76 #interrupt-cells = <2>;
77 #address-cells = <2>;
78 #size-cells = <1>;
79
80 dma-controller@0 {
81 compatible = "pnpPNP,200";
82 reg = <1 0x00000000 0x00000020
83 1 0x00000080 0x00000010
84 1 0x000000c0 0x00000020>;
85 };
86
87 i8259: interrupt-controller@20 {
88 device_type = "interrupt-controller";
89 compatible = "pnpPNP,000";
90 interrupt-controller;
91 reg = <1 0x00000020 0x00000002
92 1 0x000000a0 0x00000002
93 1 0x000004d0 0x00000002>;
94 reserved-interrupts = <2>;
95 #interrupt-cells = <2>;
96 };
97
98 timer@40 {
99 // Also adds pcspkr to platform devices.
100 compatible = "pnpPNP,100";
101 reg = <1 0x00000040 0x00000020>;
102 };
103
104 8042@60 {
105 device_type = "8042";
106 reg = <1 0x00000060 0x00000001
107 1 0x00000064 0x00000001>;
108 interrupts = <1 3 12 3>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111
112 keyboard@0 {
113 compatible = "pnpPNP,303";
114 reg = <0>;
115 };
116
117 mouse@1 {
118 compatible = "pnpPNP,f03";
119 reg = <1>;
120 };
121 };
122
123 rtc@70 {
124 compatible = "pnpPNP,b00";
125 reg = <1 0x00000070 0x00000002>;
126 interrupts = <8 3>;
127 };
128
129 serial@3f8 {
130 device_type = "serial";
131 compatible = "pnpPNP,501","pnpPNP,500";
132 reg = <1 0x000003f8 0x00000008>;
133 interrupts = <4 3>;
134 clock-frequency = <1843200>;
135 current-speed = <115200>;
136 };
137
138 serial@2f8 {
139 device_type = "serial";
140 compatible = "pnpPNP,501","pnpPNP,500";
141 reg = <1 0x000002f8 0x00000008>;
142 interrupts = <3 3>;
143 clock-frequency = <1843200>;
144 current-speed = <115200>;
145 };
146
147 parallel@378 {
148 device_type = "parallel";
149 // No ECP support for now, otherwise add "pnpPNP,401".
150 compatible = "pnpPNP,400";
151 reg = <1 0x00000378 0x00000003
152 1 0x00000778 0x00000003>;
153 };
154
155 fdc@3f0 {
156 device_type = "fdc";
157 compatible = "pnpPNP,700";
158 reg = <1 0x000003f0 0x00000008>;
159 interrupts = <6 3>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 disk@0 {
164 reg = <0>;
165 };
166 };
167 };
168 };
169
170 chosen {
171 linux,stdout-path = "/pci@80000000/isa@7/serial@3f8";
172 };
173};
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 8b5ba8261a3..540ec3241f7 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -142,6 +142,20 @@
142 /*RXDE*/ 0x5 0x4>; 142 /*RXDE*/ 0x5 0x4>;
143 }; 143 };
144 144
145 USB0: ehci@bffd0400 {
146 compatible = "ibm,usb-ehci-460ex", "usb-ehci";
147 interrupt-parent = <&UIC2>;
148 interrupts = <0x1d 4>;
149 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
150 };
151
152 USB1: usb@bffd0000 {
153 compatible = "ohci-le";
154 reg = <4 0xbffd0000 0x60>;
155 interrupt-parent = <&UIC2>;
156 interrupts = <0x1e 4>;
157 };
158
145 POB0: opb { 159 POB0: opb {
146 compatible = "ibm,opb-460ex", "ibm,opb"; 160 compatible = "ibm,opb-460ex", "ibm,opb";
147 #address-cells = <1>; 161 #address-cells = <1>;
@@ -245,6 +259,20 @@
245 reg = <0xef600700 0x00000014>; 259 reg = <0xef600700 0x00000014>;
246 interrupt-parent = <&UIC0>; 260 interrupt-parent = <&UIC0>;
247 interrupts = <0x2 0x4>; 261 interrupts = <0x2 0x4>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264 rtc@68 {
265 compatible = "stm,m41t80";
266 reg = <0x68>;
267 interrupt-parent = <&UIC2>;
268 interrupts = <0x19 0x8>;
269 };
270 sttm@48 {
271 compatible = "ad,ad7414";
272 reg = <0x48>;
273 interrupt-parent = <&UIC1>;
274 interrupts = <0x14 0x8>;
275 };
248 }; 276 };
249 277
250 IIC1: i2c@ef600800 { 278 IIC1: i2c@ef600800 {
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 2f74cc4e093..cee8080aa24 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -17,6 +17,7 @@
17 compatible = "schindler,cm5200"; 17 compatible = "schindler,cm5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
@@ -74,84 +74,76 @@
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 }; 77 };
79 78
80 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
83 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
84 interrupt-parent = <&mpc5200_pic>;
85 }; 83 };
86 84
87 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
90 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
91 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
97 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 95 };
100 96
101 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
104 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
105 interrupt-parent = <&mpc5200_pic>;
106 }; 101 };
107 102
108 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
109 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
110 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
111 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 107 };
114 108
115 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
118 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 }; 113 };
121 114
122 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
123 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
124 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
125 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
126 interrupt-parent = <&mpc5200_pic>;
127 }; 119 };
128 120
129 gpio@b00 { 121 gpio_simple: gpio@b00 {
130 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 122 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
131 reg = <0xb00 0x40>; 123 reg = <0xb00 0x40>;
132 interrupts = <1 7 0>; 124 interrupts = <1 7 0>;
133 interrupt-parent = <&mpc5200_pic>; 125 gpio-controller;
126 #gpio-cells = <2>;
134 }; 127 };
135 128
136 gpio@c00 { 129 gpio_wkup: gpio@c00 {
137 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 130 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
138 reg = <0xc00 0x40>; 131 reg = <0xc00 0x40>;
139 interrupts = <1 8 0 0 3 0>; 132 interrupts = <1 8 0 0 3 0>;
140 interrupt-parent = <&mpc5200_pic>; 133 gpio-controller;
134 #gpio-cells = <2>;
141 }; 135 };
142 136
143 spi@f00 { 137 spi@f00 {
144 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 138 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
145 reg = <0xf00 0x20>; 139 reg = <0xf00 0x20>;
146 interrupts = <2 13 0 2 14 0>; 140 interrupts = <2 13 0 2 14 0>;
147 interrupt-parent = <&mpc5200_pic>;
148 }; 141 };
149 142
150 usb@1000 { 143 usb@1000 {
151 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 144 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
152 reg = <0x1000 0xff>; 145 reg = <0x1000 0xff>;
153 interrupts = <2 6 0>; 146 interrupts = <2 6 0>;
154 interrupt-parent = <&mpc5200_pic>;
155 }; 147 };
156 148
157 dma-controller@1200 { 149 dma-controller@1200 {
@@ -161,7 +153,6 @@
161 3 4 0 3 5 0 3 6 0 3 7 0 153 3 4 0 3 5 0 3 6 0 3 7 0
162 3 8 0 3 9 0 3 10 0 3 11 0 154 3 8 0 3 9 0 3 10 0 3 11 0
163 3 12 0 3 13 0 3 14 0 3 15 0>; 155 3 12 0 3 13 0 3 14 0 3 15 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 }; 156 };
166 157
167 xlb@1f00 { 158 xlb@1f00 {
@@ -170,48 +161,34 @@
170 }; 161 };
171 162
172 serial@2000 { // PSC1 163 serial@2000 { // PSC1
173 device_type = "serial";
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 164 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 port-number = <0>; // Logical port assignment
176 reg = <0x2000 0x100>; 165 reg = <0x2000 0x100>;
177 interrupts = <2 1 0>; 166 interrupts = <2 1 0>;
178 interrupt-parent = <&mpc5200_pic>;
179 }; 167 };
180 168
181 serial@2200 { // PSC2 169 serial@2200 { // PSC2
182 device_type = "serial"; 170 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
183 compatible = "fsl,mpc5200-psc-uart";
184 port-number = <1>; // Logical port assignment
185 reg = <0x2200 0x100>; 171 reg = <0x2200 0x100>;
186 interrupts = <2 2 0>; 172 interrupts = <2 2 0>;
187 interrupt-parent = <&mpc5200_pic>;
188 }; 173 };
189 174
190 serial@2400 { // PSC3 175 serial@2400 { // PSC3
191 device_type = "serial"; 176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
192 compatible = "fsl,mpc5200-psc-uart";
193 port-number = <2>; // Logical port assignment
194 reg = <0x2400 0x100>; 177 reg = <0x2400 0x100>;
195 interrupts = <2 3 0>; 178 interrupts = <2 3 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 179 };
198 180
199 serial@2c00 { // PSC6 181 serial@2c00 { // PSC6
200 device_type = "serial";
201 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 182 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
202 port-number = <5>; // Logical port assignment
203 reg = <0x2c00 0x100>; 183 reg = <0x2c00 0x100>;
204 interrupts = <2 4 0>; 184 interrupts = <2 4 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 185 };
207 186
208 ethernet@3000 { 187 ethernet@3000 {
209 device_type = "network";
210 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 188 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
211 reg = <0x3000 0x400>; 189 reg = <0x3000 0x400>;
212 local-mac-address = [ 00 00 00 00 00 00 ]; 190 local-mac-address = [ 00 00 00 00 00 00 ];
213 interrupts = <2 5 0>; 191 interrupts = <2 5 0>;
214 interrupt-parent = <&mpc5200_pic>;
215 phy-handle = <&phy0>; 192 phy-handle = <&phy0>;
216 }; 193 };
217 194
@@ -221,10 +198,8 @@
221 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 198 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
222 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 199 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
223 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 200 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
224 interrupt-parent = <&mpc5200_pic>;
225 201
226 phy0: ethernet-phy@0 { 202 phy0: ethernet-phy@0 {
227 device_type = "ethernet-phy";
228 reg = <0>; 203 reg = <0>;
229 }; 204 };
230 }; 205 };
@@ -235,7 +210,6 @@
235 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 210 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
236 reg = <0x3d40 0x40>; 211 reg = <0x3d40 0x40>;
237 interrupts = <2 16 0>; 212 interrupts = <2 16 0>;
238 interrupt-parent = <&mpc5200_pic>;
239 fsl5200-clocking; 213 fsl5200-clocking;
240 }; 214 };
241 215
@@ -245,9 +219,8 @@
245 }; 219 };
246 }; 220 };
247 221
248 lpb { 222 localbus {
249 model = "fsl,lpb"; 223 compatible = "fsl,mpc5200b-lpb","simple-bus";
250 compatible = "fsl,lpb";
251 #address-cells = <2>; 224 #address-cells = <2>;
252 #size-cells = <1>; 225 #size-cells = <1>;
253 ranges = <0 0 0xfc000000 0x2000000>; 226 ranges = <0 0 0xfc000000 0x2000000>;
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
new file mode 100644
index 00000000000..4c36186ef94
--- /dev/null
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -0,0 +1,254 @@
1/*
2 * Digsy MTC board Device Tree Source
3 *
4 * Copyright (C) 2009 Semihalf
5 *
6 * Based on the CM5200 by M. Balakowicz
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "intercontrol,digsy-mtc";
18 compatible = "intercontrol,digsy-mtc";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x02000000>; // 32MB
43 };
44
45 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt;
72 };
73
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 };
85
86 timer@630 { // General Purpose Timer
87 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
88 reg = <0x630 0x10>;
89 interrupts = <1 12 0>;
90 };
91
92 timer@640 { // General Purpose Timer
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 reg = <0x640 0x10>;
95 interrupts = <1 13 0>;
96 };
97
98 timer@650 { // General Purpose Timer
99 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
100 reg = <0x650 0x10>;
101 interrupts = <1 14 0>;
102 };
103
104 timer@660 { // General Purpose Timer
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
106 reg = <0x660 0x10>;
107 interrupts = <1 15 0>;
108 };
109
110 timer@670 { // General Purpose Timer
111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
112 reg = <0x670 0x10>;
113 interrupts = <1 16 0>;
114 };
115
116 gpio_simple: gpio@b00 {
117 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
118 reg = <0xb00 0x40>;
119 interrupts = <1 7 0>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 };
123
124 gpio_wkup: gpio@c00 {
125 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
126 reg = <0xc00 0x40>;
127 interrupts = <1 8 0 0 3 0>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 };
131
132 spi@f00 {
133 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
134 reg = <0xf00 0x20>;
135 interrupts = <2 13 0 2 14 0>;
136 };
137
138 usb@1000 {
139 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
140 reg = <0x1000 0xff>;
141 interrupts = <2 6 0>;
142 };
143
144 dma-controller@1200 {
145 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
146 reg = <0x1200 0x80>;
147 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
148 3 4 0 3 5 0 3 6 0 3 7 0
149 3 8 0 3 9 0 3 10 0 3 11 0
150 3 12 0 3 13 0 3 14 0 3 15 0>;
151 };
152
153 xlb@1f00 {
154 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
155 reg = <0x1f00 0x100>;
156 };
157
158 serial@2600 { // PSC4
159 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
160 reg = <0x2600 0x100>;
161 interrupts = <2 11 0>;
162 };
163
164 serial@2800 { // PSC5
165 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
166 reg = <0x2800 0x100>;
167 interrupts = <2 12 0>;
168 };
169
170 ethernet@3000 {
171 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
172 reg = <0x3000 0x400>;
173 local-mac-address = [ 00 00 00 00 00 00 ];
174 interrupts = <2 5 0>;
175 phy-handle = <&phy0>;
176 };
177
178 mdio@3000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
182 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
183 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
184
185 phy0: ethernet-phy@0 {
186 reg = <0>;
187 };
188 };
189
190 ata@3a00 {
191 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
192 reg = <0x3a00 0x100>;
193 interrupts = <2 7 0>;
194 };
195
196 i2c@3d00 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
200 reg = <0x3d00 0x40>;
201 interrupts = <2 15 0>;
202 fsl5200-clocking;
203
204 rtc@50 {
205 compatible = "at,24c08";
206 reg = <0x50>;
207 };
208
209 rtc@68 {
210 compatible = "dallas,ds1339";
211 reg = <0x68>;
212 };
213 };
214
215 sram@8000 {
216 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
217 reg = <0x8000 0x4000>;
218 };
219 };
220
221 lpb {
222 compatible = "fsl,mpc5200b-lpb","simple-bus";
223 #address-cells = <2>;
224 #size-cells = <1>;
225 ranges = <0 0 0xff000000 0x1000000>;
226
227 // 16-bit flash device at LocalPlus Bus CS0
228 flash@0,0 {
229 compatible = "cfi-flash";
230 reg = <0 0 0x1000000>;
231 bank-width = <2>;
232 device-width = <2>;
233 #size-cells = <1>;
234 #address-cells = <1>;
235
236 partition@0 {
237 label = "kernel";
238 reg = <0x0 0x00200000>;
239 };
240 partition@200000 {
241 label = "root";
242 reg = <0x00200000 0x00300000>;
243 };
244 partition@500000 {
245 label = "user";
246 reg = <0x00500000 0x00a00000>;
247 };
248 partition@f00000 {
249 label = "u-boot";
250 reg = <0x00f00000 0x100000>;
251 };
252 };
253 };
254};
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
new file mode 100644
index 00000000000..0ddfdfc7ab5
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -0,0 +1,364 @@
1/*
2 * GE Fanuc PPC9A Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17/*
18 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
19 */
20
21/dts-v1/;
22
23/ {
24 model = "GEF_PPC9A";
25 compatible = "gef,ppc9a";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
64
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
69
70 localbus@fef05000 {
71 #address-cells = <2>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>;
77
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe8000000 0x08000000 // Paged Flash 0
80 2 0 0xe0000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00008000 // FPGA
83 5 0 0xfc008000 0x00008000 // AFIX FPGA
84 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
85 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
86
87 /* flash@0,0 is a mirror of part of the memory in flash@1,0
88 flash@0,0 {
89 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
90 reg = <0x0 0x0 0x1000000>;
91 bank-width = <4>;
92 device-width = <2>;
93 #address-cells = <1>;
94 #size-cells = <1>;
95 partition@0 {
96 label = "firmware";
97 reg = <0x0 0x1000000>;
98 read-only;
99 };
100 };
101 */
102
103 flash@1,0 {
104 compatible = "gef,ppc9a-paged-flash", "cfi-flash";
105 reg = <0x1 0x0 0x8000000>;
106 bank-width = <4>;
107 device-width = <2>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 partition@0 {
111 label = "user";
112 reg = <0x0 0x7800000>;
113 };
114 partition@7800000 {
115 label = "firmware";
116 reg = <0x7800000 0x800000>;
117 read-only;
118 };
119 };
120
121 fpga@4,0 {
122 compatible = "gef,ppc9a-fpga-regs";
123 reg = <0x4 0x0 0x40>;
124 };
125
126 wdt@4,2000 {
127 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
128 "gef,fpga-wdt";
129 reg = <0x4 0x2000 0x8>;
130 interrupts = <0x1a 0x4>;
131 interrupt-parent = <&gef_pic>;
132 };
133 /* Second watchdog available, driver currently supports one.
134 wdt@4,2010 {
135 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
136 "gef,fpga-wdt";
137 reg = <0x4 0x2010 0x8>;
138 interrupts = <0x1b 0x4>;
139 interrupt-parent = <&gef_pic>;
140 };
141 */
142 gef_pic: pic@4,4000 {
143 #interrupt-cells = <1>;
144 interrupt-controller;
145 compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
146 reg = <0x4 0x4000 0x20>;
147 interrupts = <0x8
148 0x9>;
149 interrupt-parent = <&mpic>;
150
151 };
152 gef_gpio: gpio@7,14000 {
153 #gpio-cells = <2>;
154 compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
155 reg = <0x7 0x14000 0x24>;
156 gpio-controller;
157 };
158 };
159
160 soc@fef00000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 #interrupt-cells = <2>;
164 compatible = "fsl,mpc8641-soc", "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>;
166 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
167 bus-frequency = <33333333>;
168
169 i2c1: i2c@3000 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl-i2c";
173 reg = <0x3000 0x100>;
174 interrupts = <0x2b 0x2>;
175 interrupt-parent = <&mpic>;
176 dfsrr;
177
178 hwmon@48 {
179 compatible = "national,lm92";
180 reg = <0x48>;
181 };
182
183 hwmon@4c {
184 compatible = "adi,adt7461";
185 reg = <0x4c>;
186 };
187
188 rtc@51 {
189 compatible = "epson,rx8581";
190 reg = <0x00000051>;
191 };
192
193 eti@6b {
194 compatible = "dallas,ds1682";
195 reg = <0x6b>;
196 };
197 };
198
199 i2c2: i2c@3100 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "fsl-i2c";
203 reg = <0x3100 0x100>;
204 interrupts = <0x2b 0x2>;
205 interrupt-parent = <&mpic>;
206 dfsrr;
207 };
208
209 dma@21300 {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
213 reg = <0x21300 0x4>;
214 ranges = <0x0 0x21100 0x200>;
215 cell-index = <0>;
216 dma-channel@0 {
217 compatible = "fsl,mpc8641-dma-channel",
218 "fsl,eloplus-dma-channel";
219 reg = <0x0 0x80>;
220 cell-index = <0>;
221 interrupt-parent = <&mpic>;
222 interrupts = <20 2>;
223 };
224 dma-channel@80 {
225 compatible = "fsl,mpc8641-dma-channel",
226 "fsl,eloplus-dma-channel";
227 reg = <0x80 0x80>;
228 cell-index = <1>;
229 interrupt-parent = <&mpic>;
230 interrupts = <21 2>;
231 };
232 dma-channel@100 {
233 compatible = "fsl,mpc8641-dma-channel",
234 "fsl,eloplus-dma-channel";
235 reg = <0x100 0x80>;
236 cell-index = <2>;
237 interrupt-parent = <&mpic>;
238 interrupts = <22 2>;
239 };
240 dma-channel@180 {
241 compatible = "fsl,mpc8641-dma-channel",
242 "fsl,eloplus-dma-channel";
243 reg = <0x180 0x80>;
244 cell-index = <3>;
245 interrupt-parent = <&mpic>;
246 interrupts = <23 2>;
247 };
248 };
249
250 mdio@24520 {
251 #address-cells = <1>;
252 #size-cells = <0>;
253 compatible = "fsl,gianfar-mdio";
254 reg = <0x24520 0x20>;
255
256 phy0: ethernet-phy@0 {
257 interrupt-parent = <&gef_pic>;
258 interrupts = <0x9 0x4>;
259 reg = <1>;
260 };
261 phy2: ethernet-phy@2 {
262 interrupt-parent = <&gef_pic>;
263 interrupts = <0x8 0x4>;
264 reg = <3>;
265 };
266 };
267
268 enet0: ethernet@24000 {
269 device_type = "network";
270 model = "eTSEC";
271 compatible = "gianfar";
272 reg = <0x24000 0x1000>;
273 local-mac-address = [ 00 00 00 00 00 00 ];
274 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
275 interrupt-parent = <&mpic>;
276 phy-handle = <&phy0>;
277 phy-connection-type = "gmii";
278 };
279
280 enet1: ethernet@26000 {
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
287 interrupt-parent = <&mpic>;
288 phy-handle = <&phy2>;
289 phy-connection-type = "gmii";
290 };
291
292 serial0: serial@4500 {
293 cell-index = <0>;
294 device_type = "serial";
295 compatible = "ns16550";
296 reg = <0x4500 0x100>;
297 clock-frequency = <0>;
298 interrupts = <0x2a 0x2>;
299 interrupt-parent = <&mpic>;
300 };
301
302 serial1: serial@4600 {
303 cell-index = <1>;
304 device_type = "serial";
305 compatible = "ns16550";
306 reg = <0x4600 0x100>;
307 clock-frequency = <0>;
308 interrupts = <0x1c 0x2>;
309 interrupt-parent = <&mpic>;
310 };
311
312 mpic: pic@40000 {
313 clock-frequency = <0>;
314 interrupt-controller;
315 #address-cells = <0>;
316 #interrupt-cells = <2>;
317 reg = <0x40000 0x40000>;
318 compatible = "chrp,open-pic";
319 device_type = "open-pic";
320 };
321
322 global-utilities@e0000 {
323 compatible = "fsl,mpc8641-guts";
324 reg = <0xe0000 0x1000>;
325 fsl,has-rstcr;
326 };
327 };
328
329 pci0: pcie@fef08000 {
330 compatible = "fsl,mpc8641-pcie";
331 device_type = "pci";
332 #interrupt-cells = <1>;
333 #size-cells = <2>;
334 #address-cells = <3>;
335 reg = <0xfef08000 0x1000>;
336 bus-range = <0x0 0xff>;
337 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
338 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
339 clock-frequency = <33333333>;
340 interrupt-parent = <&mpic>;
341 interrupts = <0x18 0x2>;
342 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
343 interrupt-map = <
344 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
345 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
346 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
347 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
348 >;
349
350 pcie@0 {
351 reg = <0 0 0 0 0>;
352 #size-cells = <2>;
353 #address-cells = <3>;
354 device_type = "pci";
355 ranges = <0x02000000 0x0 0x80000000
356 0x02000000 0x0 0x80000000
357 0x0 0x40000000
358
359 0x01000000 0x0 0x00000000
360 0x01000000 0x0 0x00000000
361 0x0 0x00400000>;
362 };
363 };
364};
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
new file mode 100644
index 00000000000..09eeb438216
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -0,0 +1,364 @@
1/*
2 * GE Fanuc SBC310 Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17/*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
19 */
20
21/dts-v1/;
22
23/ {
24 model = "GEF_SBC310";
25 compatible = "gef,sbc310";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
64
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
69
70 localbus@fef05000 {
71 #address-cells = <2>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>;
77
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe0000000 0x08000000 // Paged Flash 0
80 2 0 0xe8000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00010000>; // FPGA
83
84 /* flash@0,0 is a mirror of part of the memory in flash@1,0
85 flash@0,0 {
86 compatible = "cfi-flash";
87 reg = <0 0 0x01000000>;
88 bank-width = <2>;
89 device-width = <2>;
90 #address-cells = <1>;
91 #size-cells = <1>;
92 partition@0 {
93 label = "firmware";
94 reg = <0x00000000 0x01000000>;
95 read-only;
96 };
97 };
98 */
99
100 flash@1,0 {
101 compatible = "cfi-flash";
102 reg = <1 0 0x8000000>;
103 bank-width = <2>;
104 device-width = <2>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 partition@0 {
108 label = "user";
109 reg = <0x00000000 0x07800000>;
110 };
111 partition@7800000 {
112 label = "firmware";
113 reg = <0x07800000 0x00800000>;
114 read-only;
115 };
116 };
117
118 fpga@4,0 {
119 compatible = "gef,fpga-regs";
120 reg = <0x4 0x0 0x40>;
121 };
122
123 wdt@4,2000 {
124 #interrupt-cells = <2>;
125 device_type = "watchdog";
126 compatible = "gef,fpga-wdt";
127 reg = <0x4 0x2000 0x8>;
128 interrupts = <0x1a 0x4>;
129 interrupt-parent = <&gef_pic>;
130 };
131/*
132 wdt@4,2010 {
133 #interrupt-cells = <2>;
134 device_type = "watchdog";
135 compatible = "gef,fpga-wdt";
136 reg = <0x4 0x2010 0x8>;
137 interrupts = <0x1b 0x4>;
138 interrupt-parent = <&gef_pic>;
139 };
140*/
141 gef_pic: pic@4,4000 {
142 #interrupt-cells = <1>;
143 interrupt-controller;
144 compatible = "gef,fpga-pic";
145 reg = <0x4 0x4000 0x20>;
146 interrupts = <0x8
147 0x9>;
148 interrupt-parent = <&mpic>;
149
150 };
151 gef_gpio: gpio@4,8000 {
152 #gpio-cells = <2>;
153 compatible = "gef,sbc310-gpio";
154 reg = <0x4 0x8000 0x24>;
155 gpio-controller;
156 };
157 };
158
159 soc@fef00000 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 #interrupt-cells = <2>;
163 device_type = "soc";
164 compatible = "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>;
166 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
167 bus-frequency = <33333333>;
168
169 i2c1: i2c@3000 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl-i2c";
173 reg = <0x3000 0x100>;
174 interrupts = <0x2b 0x2>;
175 interrupt-parent = <&mpic>;
176 dfsrr;
177
178 rtc@51 {
179 compatible = "epson,rx8581";
180 reg = <0x00000051>;
181 };
182 };
183
184 i2c2: i2c@3100 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "fsl-i2c";
188 reg = <0x3100 0x100>;
189 interrupts = <0x2b 0x2>;
190 interrupt-parent = <&mpic>;
191 dfsrr;
192
193 hwmon@48 {
194 compatible = "national,lm92";
195 reg = <0x48>;
196 };
197
198 hwmon@4c {
199 compatible = "adi,adt7461";
200 reg = <0x4c>;
201 };
202
203 eti@6b {
204 compatible = "dallas,ds1682";
205 reg = <0x6b>;
206 };
207 };
208
209 dma@21300 {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
213 reg = <0x21300 0x4>;
214 ranges = <0x0 0x21100 0x200>;
215 cell-index = <0>;
216 dma-channel@0 {
217 compatible = "fsl,mpc8641-dma-channel",
218 "fsl,eloplus-dma-channel";
219 reg = <0x0 0x80>;
220 cell-index = <0>;
221 interrupt-parent = <&mpic>;
222 interrupts = <20 2>;
223 };
224 dma-channel@80 {
225 compatible = "fsl,mpc8641-dma-channel",
226 "fsl,eloplus-dma-channel";
227 reg = <0x80 0x80>;
228 cell-index = <1>;
229 interrupt-parent = <&mpic>;
230 interrupts = <21 2>;
231 };
232 dma-channel@100 {
233 compatible = "fsl,mpc8641-dma-channel",
234 "fsl,eloplus-dma-channel";
235 reg = <0x100 0x80>;
236 cell-index = <2>;
237 interrupt-parent = <&mpic>;
238 interrupts = <22 2>;
239 };
240 dma-channel@180 {
241 compatible = "fsl,mpc8641-dma-channel",
242 "fsl,eloplus-dma-channel";
243 reg = <0x180 0x80>;
244 cell-index = <3>;
245 interrupt-parent = <&mpic>;
246 interrupts = <23 2>;
247 };
248 };
249
250 mdio@24520 {
251 #address-cells = <1>;
252 #size-cells = <0>;
253 compatible = "fsl,gianfar-mdio";
254 reg = <0x24520 0x20>;
255
256 phy0: ethernet-phy@0 {
257 interrupt-parent = <&gef_pic>;
258 interrupts = <0x9 0x4>;
259 reg = <1>;
260 };
261 phy2: ethernet-phy@2 {
262 interrupt-parent = <&gef_pic>;
263 interrupts = <0x8 0x4>;
264 reg = <3>;
265 };
266 };
267
268 enet0: ethernet@24000 {
269 device_type = "network";
270 model = "eTSEC";
271 compatible = "gianfar";
272 reg = <0x24000 0x1000>;
273 local-mac-address = [ 00 00 00 00 00 00 ];
274 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
275 interrupt-parent = <&mpic>;
276 phy-handle = <&phy0>;
277 phy-connection-type = "gmii";
278 };
279
280 enet1: ethernet@26000 {
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
287 interrupt-parent = <&mpic>;
288 phy-handle = <&phy2>;
289 phy-connection-type = "gmii";
290 };
291
292 serial0: serial@4500 {
293 cell-index = <0>;
294 device_type = "serial";
295 compatible = "ns16550";
296 reg = <0x4500 0x100>;
297 clock-frequency = <0>;
298 interrupts = <0x2a 0x2>;
299 interrupt-parent = <&mpic>;
300 };
301
302 serial1: serial@4600 {
303 cell-index = <1>;
304 device_type = "serial";
305 compatible = "ns16550";
306 reg = <0x4600 0x100>;
307 clock-frequency = <0>;
308 interrupts = <0x1c 0x2>;
309 interrupt-parent = <&mpic>;
310 };
311
312 mpic: pic@40000 {
313 clock-frequency = <0>;
314 interrupt-controller;
315 #address-cells = <0>;
316 #interrupt-cells = <2>;
317 reg = <0x40000 0x40000>;
318 compatible = "chrp,open-pic";
319 device_type = "open-pic";
320 };
321
322 global-utilities@e0000 {
323 compatible = "fsl,mpc8641-guts";
324 reg = <0xe0000 0x1000>;
325 fsl,has-rstcr;
326 };
327 };
328
329 pci0: pcie@fef08000 {
330 compatible = "fsl,mpc8641-pcie";
331 device_type = "pci";
332 #interrupt-cells = <1>;
333 #size-cells = <2>;
334 #address-cells = <3>;
335 reg = <0xfef08000 0x1000>;
336 bus-range = <0x0 0xff>;
337 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
338 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
339 clock-frequency = <33333333>;
340 interrupt-parent = <&mpic>;
341 interrupts = <0x18 0x2>;
342 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
343 interrupt-map = <
344 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
345 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
346 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
347 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
348 >;
349
350 pcie@0 {
351 reg = <0 0 0 0 0>;
352 #size-cells = <2>;
353 #address-cells = <3>;
354 device_type = "pci";
355 ranges = <0x02000000 0x0 0x80000000
356 0x02000000 0x0 0x80000000
357 0x0 0x40000000
358
359 0x01000000 0x0 0x00000000
360 0x01000000 0x0 0x00000000
361 0x0 0x00400000>;
362 };
363 };
364};
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index e78c355c7ba..714175ccb2a 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -71,7 +71,7 @@
71 #address-cells = <2>; 71 #address-cells = <2>;
72 #size-cells = <1>; 72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus"; 73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xf8005000 0x1000>; 74 reg = <0xfef05000 0x1000>;
75 interrupts = <19 2>; 75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 77
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 3f7a5dce8de..de30b3f9eb2 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,lite5200"; 17 compatible = "fsl,lite5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -58,96 +59,74 @@
58 // 5200 interrupts are encoded into two levels; 59 // 5200 interrupts are encoded into two levels;
59 interrupt-controller; 60 interrupt-controller;
60 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
61 device_type = "interrupt-controller";
62 compatible = "fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200-pic";
63 reg = <0x500 0x80>; 63 reg = <0x500 0x80>;
64 }; 64 };
65 65
66 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
68 cell-index = <0>;
69 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
71 interrupt-parent = <&mpc5200_pic>;
72 fsl,has-wdt; 70 fsl,has-wdt;
73 }; 71 };
74 72
75 timer@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
76 compatible = "fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200-gpt";
77 cell-index = <1>;
78 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
79 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
80 interrupt-parent = <&mpc5200_pic>;
81 }; 77 };
82 78
83 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
84 compatible = "fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200-gpt";
85 cell-index = <2>;
86 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
87 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 }; 83 };
90 84
91 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200-gpt";
93 cell-index = <3>;
94 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
95 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
96 interrupt-parent = <&mpc5200_pic>;
97 }; 89 };
98 90
99 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200-gpt";
101 cell-index = <4>;
102 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
103 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
104 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200-gpt";
109 cell-index = <5>;
110 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
111 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 101 };
114 102
115 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200-gpt";
117 cell-index = <6>;
118 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
119 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
120 interrupt-parent = <&mpc5200_pic>;
121 }; 107 };
122 108
123 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
124 compatible = "fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200-gpt";
125 cell-index = <7>;
126 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
127 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
128 interrupt-parent = <&mpc5200_pic>;
129 }; 113 };
130 114
131 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
132 compatible = "fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200-rtc";
133 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
134 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 }; 119 };
137 120
138 can@900 { 121 can@900 {
139 compatible = "fsl,mpc5200-mscan"; 122 compatible = "fsl,mpc5200-mscan";
140 cell-index = <0>;
141 interrupts = <2 17 0>; 123 interrupts = <2 17 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 reg = <0x900 0x80>; 124 reg = <0x900 0x80>;
144 }; 125 };
145 126
146 can@980 { 127 can@980 {
147 compatible = "fsl,mpc5200-mscan"; 128 compatible = "fsl,mpc5200-mscan";
148 cell-index = <1>;
149 interrupts = <2 18 0>; 129 interrupts = <2 18 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <0x980 0x80>; 130 reg = <0x980 0x80>;
152 }; 131 };
153 132
@@ -155,39 +134,33 @@
155 compatible = "fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200-gpio";
156 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
157 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
158 interrupt-parent = <&mpc5200_pic>;
159 }; 137 };
160 138
161 gpio@c00 { 139 gpio@c00 {
162 compatible = "fsl,mpc5200-gpio-wkup"; 140 compatible = "fsl,mpc5200-gpio-wkup";
163 reg = <0xc00 0x40>; 141 reg = <0xc00 0x40>;
164 interrupts = <1 8 0 0 3 0>; 142 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <&mpc5200_pic>;
166 }; 143 };
167 144
168 spi@f00 { 145 spi@f00 {
169 compatible = "fsl,mpc5200-spi"; 146 compatible = "fsl,mpc5200-spi";
170 reg = <0xf00 0x20>; 147 reg = <0xf00 0x20>;
171 interrupts = <2 13 0 2 14 0>; 148 interrupts = <2 13 0 2 14 0>;
172 interrupt-parent = <&mpc5200_pic>;
173 }; 149 };
174 150
175 usb@1000 { 151 usb@1000 {
176 compatible = "fsl,mpc5200-ohci","ohci-be"; 152 compatible = "fsl,mpc5200-ohci","ohci-be";
177 reg = <0x1000 0xff>; 153 reg = <0x1000 0xff>;
178 interrupts = <2 6 0>; 154 interrupts = <2 6 0>;
179 interrupt-parent = <&mpc5200_pic>;
180 }; 155 };
181 156
182 dma-controller@1200 { 157 dma-controller@1200 {
183 device_type = "dma-controller";
184 compatible = "fsl,mpc5200-bestcomm"; 158 compatible = "fsl,mpc5200-bestcomm";
185 reg = <0x1200 0x80>; 159 reg = <0x1200 0x80>;
186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 160 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
187 3 4 0 3 5 0 3 6 0 3 7 0 161 3 4 0 3 5 0 3 6 0 3 7 0
188 3 8 0 3 9 0 3 10 0 3 11 0 162 3 8 0 3 9 0 3 10 0 3 11 0
189 3 12 0 3 13 0 3 14 0 3 15 0>; 163 3 12 0 3 13 0 3 14 0 3 15 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 }; 164 };
192 165
193 xlb@1f00 { 166 xlb@1f00 {
@@ -196,13 +169,10 @@
196 }; 169 };
197 170
198 serial@2000 { // PSC1 171 serial@2000 { // PSC1
199 device_type = "serial";
200 compatible = "fsl,mpc5200-psc-uart"; 172 compatible = "fsl,mpc5200-psc-uart";
201 port-number = <0>; // Logical port assignment
202 cell-index = <0>; 173 cell-index = <0>;
203 reg = <0x2000 0x100>; 174 reg = <0x2000 0x100>;
204 interrupts = <2 1 0>; 175 interrupts = <2 1 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 176 };
207 177
208 // PSC2 in ac97 mode example 178 // PSC2 in ac97 mode example
@@ -211,7 +181,6 @@
211 // cell-index = <1>; 181 // cell-index = <1>;
212 // reg = <0x2200 0x100>; 182 // reg = <0x2200 0x100>;
213 // interrupts = <2 2 0>; 183 // interrupts = <2 2 0>;
214 // interrupt-parent = <&mpc5200_pic>;
215 //}; 184 //};
216 185
217 // PSC3 in CODEC mode example 186 // PSC3 in CODEC mode example
@@ -220,27 +189,22 @@
220 // cell-index = <2>; 189 // cell-index = <2>;
221 // reg = <0x2400 0x100>; 190 // reg = <0x2400 0x100>;
222 // interrupts = <2 3 0>; 191 // interrupts = <2 3 0>;
223 // interrupt-parent = <&mpc5200_pic>;
224 //}; 192 //};
225 193
226 // PSC4 in uart mode example 194 // PSC4 in uart mode example
227 //serial@2600 { // PSC4 195 //serial@2600 { // PSC4
228 // device_type = "serial";
229 // compatible = "fsl,mpc5200-psc-uart"; 196 // compatible = "fsl,mpc5200-psc-uart";
230 // cell-index = <3>; 197 // cell-index = <3>;
231 // reg = <0x2600 0x100>; 198 // reg = <0x2600 0x100>;
232 // interrupts = <2 11 0>; 199 // interrupts = <2 11 0>;
233 // interrupt-parent = <&mpc5200_pic>;
234 //}; 200 //};
235 201
236 // PSC5 in uart mode example 202 // PSC5 in uart mode example
237 //serial@2800 { // PSC5 203 //serial@2800 { // PSC5
238 // device_type = "serial";
239 // compatible = "fsl,mpc5200-psc-uart"; 204 // compatible = "fsl,mpc5200-psc-uart";
240 // cell-index = <4>; 205 // cell-index = <4>;
241 // reg = <0x2800 0x100>; 206 // reg = <0x2800 0x100>;
242 // interrupts = <2 12 0>; 207 // interrupts = <2 12 0>;
243 // interrupt-parent = <&mpc5200_pic>;
244 //}; 208 //};
245 209
246 // PSC6 in spi mode example 210 // PSC6 in spi mode example
@@ -249,16 +213,13 @@
249 // cell-index = <5>; 213 // cell-index = <5>;
250 // reg = <0x2c00 0x100>; 214 // reg = <0x2c00 0x100>;
251 // interrupts = <2 4 0>; 215 // interrupts = <2 4 0>;
252 // interrupt-parent = <&mpc5200_pic>;
253 //}; 216 //};
254 217
255 ethernet@3000 { 218 ethernet@3000 {
256 device_type = "network";
257 compatible = "fsl,mpc5200-fec"; 219 compatible = "fsl,mpc5200-fec";
258 reg = <0x3000 0x400>; 220 reg = <0x3000 0x400>;
259 local-mac-address = [ 00 00 00 00 00 00 ]; 221 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupts = <2 5 0>; 222 interrupts = <2 5 0>;
261 interrupt-parent = <&mpc5200_pic>;
262 phy-handle = <&phy0>; 223 phy-handle = <&phy0>;
263 }; 224 };
264 225
@@ -268,30 +229,24 @@
268 compatible = "fsl,mpc5200-mdio"; 229 compatible = "fsl,mpc5200-mdio";
269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 230 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 231 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
271 interrupt-parent = <&mpc5200_pic>;
272 232
273 phy0: ethernet-phy@1 { 233 phy0: ethernet-phy@1 {
274 device_type = "ethernet-phy";
275 reg = <1>; 234 reg = <1>;
276 }; 235 };
277 }; 236 };
278 237
279 ata@3a00 { 238 ata@3a00 {
280 device_type = "ata";
281 compatible = "fsl,mpc5200-ata"; 239 compatible = "fsl,mpc5200-ata";
282 reg = <0x3a00 0x100>; 240 reg = <0x3a00 0x100>;
283 interrupts = <2 7 0>; 241 interrupts = <2 7 0>;
284 interrupt-parent = <&mpc5200_pic>;
285 }; 242 };
286 243
287 i2c@3d00 { 244 i2c@3d00 {
288 #address-cells = <1>; 245 #address-cells = <1>;
289 #size-cells = <0>; 246 #size-cells = <0>;
290 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 247 compatible = "fsl,mpc5200-i2c","fsl-i2c";
291 cell-index = <0>;
292 reg = <0x3d00 0x40>; 248 reg = <0x3d00 0x40>;
293 interrupts = <2 15 0>; 249 interrupts = <2 15 0>;
294 interrupt-parent = <&mpc5200_pic>;
295 fsl5200-clocking; 250 fsl5200-clocking;
296 }; 251 };
297 252
@@ -299,14 +254,12 @@
299 #address-cells = <1>; 254 #address-cells = <1>;
300 #size-cells = <0>; 255 #size-cells = <0>;
301 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 256 compatible = "fsl,mpc5200-i2c","fsl-i2c";
302 cell-index = <1>;
303 reg = <0x3d40 0x40>; 257 reg = <0x3d40 0x40>;
304 interrupts = <2 16 0>; 258 interrupts = <2 16 0>;
305 interrupt-parent = <&mpc5200_pic>;
306 fsl5200-clocking; 259 fsl5200-clocking;
307 }; 260 };
308 sram@8000 { 261 sram@8000 {
309 compatible = "fsl,mpc5200-sram","sram"; 262 compatible = "fsl,mpc5200-sram";
310 reg = <0x8000 0x4000>; 263 reg = <0x8000 0x4000>;
311 }; 264 };
312 }; 265 };
@@ -325,7 +278,6 @@
325 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 278 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
326 clock-frequency = <0>; // From boot loader 279 clock-frequency = <0>; // From boot loader
327 interrupts = <2 8 0 2 9 0 2 10 0>; 280 interrupts = <2 8 0 2 9 0 2 10 0>;
328 interrupt-parent = <&mpc5200_pic>;
329 bus-range = <0 0>; 281 bus-range = <0 0>;
330 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 282 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
331 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 283 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 63e3bb48e84..c63e3566479 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,lite5200b"; 17 compatible = "fsl,lite5200b";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -58,136 +59,112 @@
58 // 5200 interrupts are encoded into two levels; 59 // 5200 interrupts are encoded into two levels;
59 interrupt-controller; 60 interrupt-controller;
60 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
61 device_type = "interrupt-controller";
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>; 63 reg = <0x500 0x80>;
64 }; 64 };
65 65
66 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 cell-index = <0>;
69 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
71 interrupt-parent = <&mpc5200_pic>;
72 fsl,has-wdt; 70 fsl,has-wdt;
73 }; 71 };
74 72
75 timer@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 cell-index = <1>;
78 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
79 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
80 interrupt-parent = <&mpc5200_pic>;
81 }; 77 };
82 78
83 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 cell-index = <2>;
86 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
87 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 }; 83 };
90 84
91 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 cell-index = <3>;
94 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
95 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
96 interrupt-parent = <&mpc5200_pic>;
97 }; 89 };
98 90
99 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 cell-index = <4>;
102 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
103 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
104 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 cell-index = <5>;
110 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
111 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 101 };
114 102
115 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 cell-index = <6>;
118 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
119 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
120 interrupt-parent = <&mpc5200_pic>;
121 }; 107 };
122 108
123 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 cell-index = <7>;
126 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
127 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
128 interrupt-parent = <&mpc5200_pic>;
129 }; 113 };
130 114
131 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
132 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
133 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
134 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 }; 119 };
137 120
138 can@900 { 121 can@900 {
139 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
140 cell-index = <0>;
141 interrupts = <2 17 0>; 123 interrupts = <2 17 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 reg = <0x900 0x80>; 124 reg = <0x900 0x80>;
144 }; 125 };
145 126
146 can@980 { 127 can@980 {
147 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
148 cell-index = <1>;
149 interrupts = <2 18 0>; 129 interrupts = <2 18 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <0x980 0x80>; 130 reg = <0x980 0x80>;
152 }; 131 };
153 132
154 gpio@b00 { 133 gpio_simple: gpio@b00 {
155 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
156 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
157 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
158 interrupt-parent = <&mpc5200_pic>; 137 gpio-controller;
138 #gpio-cells = <2>;
159 }; 139 };
160 140
161 gpio@c00 { 141 gpio_wkup: gpio@c00 {
162 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
163 reg = <0xc00 0x40>; 143 reg = <0xc00 0x40>;
164 interrupts = <1 8 0 0 3 0>; 144 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <&mpc5200_pic>; 145 gpio-controller;
146 #gpio-cells = <2>;
166 }; 147 };
167 148
168 spi@f00 { 149 spi@f00 {
169 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
170 reg = <0xf00 0x20>; 151 reg = <0xf00 0x20>;
171 interrupts = <2 13 0 2 14 0>; 152 interrupts = <2 13 0 2 14 0>;
172 interrupt-parent = <&mpc5200_pic>;
173 }; 153 };
174 154
175 usb@1000 { 155 usb@1000 {
176 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
177 reg = <0x1000 0xff>; 157 reg = <0x1000 0xff>;
178 interrupts = <2 6 0>; 158 interrupts = <2 6 0>;
179 interrupt-parent = <&mpc5200_pic>;
180 }; 159 };
181 160
182 dma-controller@1200 { 161 dma-controller@1200 {
183 device_type = "dma-controller";
184 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
185 reg = <0x1200 0x80>; 163 reg = <0x1200 0x80>;
186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
187 3 4 0 3 5 0 3 6 0 3 7 0 165 3 4 0 3 5 0 3 6 0 3 7 0
188 3 8 0 3 9 0 3 10 0 3 11 0 166 3 8 0 3 9 0 3 10 0 3 11 0
189 3 12 0 3 13 0 3 14 0 3 15 0>; 167 3 12 0 3 13 0 3 14 0 3 15 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 }; 168 };
192 169
193 xlb@1f00 { 170 xlb@1f00 {
@@ -196,13 +173,10 @@
196 }; 173 };
197 174
198 serial@2000 { // PSC1 175 serial@2000 { // PSC1
199 device_type = "serial";
200 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
201 port-number = <0>; // Logical port assignment
202 cell-index = <0>; 177 cell-index = <0>;
203 reg = <0x2000 0x100>; 178 reg = <0x2000 0x100>;
204 interrupts = <2 1 0>; 179 interrupts = <2 1 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 180 };
207 181
208 // PSC2 in ac97 mode example 182 // PSC2 in ac97 mode example
@@ -211,7 +185,6 @@
211 // cell-index = <1>; 185 // cell-index = <1>;
212 // reg = <0x2200 0x100>; 186 // reg = <0x2200 0x100>;
213 // interrupts = <2 2 0>; 187 // interrupts = <2 2 0>;
214 // interrupt-parent = <&mpc5200_pic>;
215 //}; 188 //};
216 189
217 // PSC3 in CODEC mode example 190 // PSC3 in CODEC mode example
@@ -220,27 +193,22 @@
220 // cell-index = <2>; 193 // cell-index = <2>;
221 // reg = <0x2400 0x100>; 194 // reg = <0x2400 0x100>;
222 // interrupts = <2 3 0>; 195 // interrupts = <2 3 0>;
223 // interrupt-parent = <&mpc5200_pic>;
224 //}; 196 //};
225 197
226 // PSC4 in uart mode example 198 // PSC4 in uart mode example
227 //serial@2600 { // PSC4 199 //serial@2600 { // PSC4
228 // device_type = "serial";
229 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 200 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
230 // cell-index = <3>; 201 // cell-index = <3>;
231 // reg = <0x2600 0x100>; 202 // reg = <0x2600 0x100>;
232 // interrupts = <2 11 0>; 203 // interrupts = <2 11 0>;
233 // interrupt-parent = <&mpc5200_pic>;
234 //}; 204 //};
235 205
236 // PSC5 in uart mode example 206 // PSC5 in uart mode example
237 //serial@2800 { // PSC5 207 //serial@2800 { // PSC5
238 // device_type = "serial";
239 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 208 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
240 // cell-index = <4>; 209 // cell-index = <4>;
241 // reg = <0x2800 0x100>; 210 // reg = <0x2800 0x100>;
242 // interrupts = <2 12 0>; 211 // interrupts = <2 12 0>;
243 // interrupt-parent = <&mpc5200_pic>;
244 //}; 212 //};
245 213
246 // PSC6 in spi mode example 214 // PSC6 in spi mode example
@@ -249,49 +217,40 @@
249 // cell-index = <5>; 217 // cell-index = <5>;
250 // reg = <0x2c00 0x100>; 218 // reg = <0x2c00 0x100>;
251 // interrupts = <2 4 0>; 219 // interrupts = <2 4 0>;
252 // interrupt-parent = <&mpc5200_pic>;
253 //}; 220 //};
254 221
255 ethernet@3000 { 222 ethernet@3000 {
256 device_type = "network";
257 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 223 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
258 reg = <0x3000 0x400>; 224 reg = <0x3000 0x400>;
259 local-mac-address = [ 00 00 00 00 00 00 ]; 225 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupts = <2 5 0>; 226 interrupts = <2 5 0>;
261 interrupt-parent = <&mpc5200_pic>;
262 phy-handle = <&phy0>; 227 phy-handle = <&phy0>;
263 }; 228 };
264 229
265 mdio@3000 { 230 mdio@3000 {
266 #address-cells = <1>; 231 #address-cells = <1>;
267 #size-cells = <0>; 232 #size-cells = <0>;
268 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 233 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 234 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 235 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
271 interrupt-parent = <&mpc5200_pic>;
272 236
273 phy0: ethernet-phy@0 { 237 phy0: ethernet-phy@0 {
274 device_type = "ethernet-phy";
275 reg = <0>; 238 reg = <0>;
276 }; 239 };
277 }; 240 };
278 241
279 ata@3a00 { 242 ata@3a00 {
280 device_type = "ata";
281 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 243 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
282 reg = <0x3a00 0x100>; 244 reg = <0x3a00 0x100>;
283 interrupts = <2 7 0>; 245 interrupts = <2 7 0>;
284 interrupt-parent = <&mpc5200_pic>;
285 }; 246 };
286 247
287 i2c@3d00 { 248 i2c@3d00 {
288 #address-cells = <1>; 249 #address-cells = <1>;
289 #size-cells = <0>; 250 #size-cells = <0>;
290 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 251 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
291 cell-index = <0>;
292 reg = <0x3d00 0x40>; 252 reg = <0x3d00 0x40>;
293 interrupts = <2 15 0>; 253 interrupts = <2 15 0>;
294 interrupt-parent = <&mpc5200_pic>;
295 fsl5200-clocking; 254 fsl5200-clocking;
296 }; 255 };
297 256
@@ -299,14 +258,13 @@
299 #address-cells = <1>; 258 #address-cells = <1>;
300 #size-cells = <0>; 259 #size-cells = <0>;
301 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 260 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
302 cell-index = <1>;
303 reg = <0x3d40 0x40>; 261 reg = <0x3d40 0x40>;
304 interrupts = <2 16 0>; 262 interrupts = <2 16 0>;
305 interrupt-parent = <&mpc5200_pic>;
306 fsl5200-clocking; 263 fsl5200-clocking;
307 }; 264 };
265
308 sram@8000 { 266 sram@8000 {
309 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 267 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
310 reg = <0x8000 0x4000>; 268 reg = <0x8000 0x4000>;
311 }; 269 };
312 }; 270 };
@@ -330,7 +288,6 @@
330 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 288 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
331 clock-frequency = <0>; // From boot loader 289 clock-frequency = <0>; // From boot loader
332 interrupts = <2 8 0 2 9 0 2 10 0>; 290 interrupts = <2 8 0 2 9 0 2 10 0>;
333 interrupt-parent = <&mpc5200_pic>;
334 bus-range = <0 0>; 291 bus-range = <0 0>;
335 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 292 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
336 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 293 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
new file mode 100644
index 00000000000..e297d8b4187
--- /dev/null
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -0,0 +1,318 @@
1/*
2 * Freescale Media5200 board Device Tree Source
3 *
4 * Copyright 2009 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 * Steven Cavanagh <scavanagh@secretlab.ca>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "fsl,media5200";
18 compatible = "fsl,media5200";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 aliases {
24 console = &console;
25 ethernet0 = &eth0;
26 };
27
28 chosen {
29 linux,stdout-path = &console;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,5200@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <0x4000>; // L1, 16K
42 i-cache-size = <0x4000>; // L1, 16K
43 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
44 bus-frequency = <132000000>; // 132 MHz
45 clock-frequency = <396000000>; // 396 MHz
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x08000000>; // 128MB RAM
52 };
53
54 soc@f0000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "fsl,mpc5200b-immr";
58 ranges = <0 0xf0000000 0x0000c000>;
59 reg = <0xf0000000 0x00000100>;
60 bus-frequency = <132000000>;// 132 MHz
61 system-frequency = <0>; // from bootloader
62
63 cdm@200 {
64 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
65 reg = <0x200 0x38>;
66 };
67
68 mpc5200_pic: interrupt-controller@500 {
69 // 5200 interrupts are encoded into two levels;
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
73 reg = <0x500 0x80>;
74 };
75
76 timer@600 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 reg = <0x600 0x10>;
79 interrupts = <1 9 0>;
80 fsl,has-wdt;
81 };
82
83 timer@610 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x610 0x10>;
86 interrupts = <1 10 0>;
87 };
88
89 timer@620 { // General Purpose Timer
90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 reg = <0x620 0x10>;
92 interrupts = <1 11 0>;
93 };
94
95 timer@630 { // General Purpose Timer
96 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
97 reg = <0x630 0x10>;
98 interrupts = <1 12 0>;
99 };
100
101 timer@640 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x640 0x10>;
104 interrupts = <1 13 0>;
105 };
106
107 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 };
112
113 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 reg = <0x660 0x10>;
116 interrupts = <1 15 0>;
117 };
118
119 timer@670 { // General Purpose Timer
120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121 reg = <0x670 0x10>;
122 interrupts = <1 16 0>;
123 };
124
125 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>;
129 };
130
131 can@900 {
132 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
133 interrupts = <2 17 0>;
134 reg = <0x900 0x80>;
135 };
136
137 can@980 {
138 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
139 interrupts = <2 18 0>;
140 reg = <0x980 0x80>;
141 };
142
143 gpio_simple: gpio@b00 {
144 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
145 reg = <0xb00 0x40>;
146 interrupts = <1 7 0>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 };
150
151 gpio_wkup: gpio@c00 {
152 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
153 reg = <0xc00 0x40>;
154 interrupts = <1 8 0 0 3 0>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 };
158
159 spi@f00 {
160 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
161 reg = <0xf00 0x20>;
162 interrupts = <2 13 0 2 14 0>;
163 };
164
165 usb@1000 {
166 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
167 reg = <0x1000 0x100>;
168 interrupts = <2 6 0>;
169 };
170
171 dma-controller@1200 {
172 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
173 reg = <0x1200 0x80>;
174 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
175 3 4 0 3 5 0 3 6 0 3 7 0
176 3 8 0 3 9 0 3 10 0 3 11 0
177 3 12 0 3 13 0 3 14 0 3 15 0>;
178 };
179
180 xlb@1f00 {
181 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
182 reg = <0x1f00 0x100>;
183 };
184
185 // PSC6 in uart mode
186 console: serial@2c00 { // PSC6
187 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
188 cell-index = <5>;
189 port-number = <0>; // Logical port assignment
190 reg = <0x2c00 0x100>;
191 interrupts = <2 4 0>;
192 };
193
194 eth0: ethernet@3000 {
195 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
196 reg = <0x3000 0x400>;
197 local-mac-address = [ 00 00 00 00 00 00 ];
198 interrupts = <2 5 0>;
199 phy-handle = <&phy0>;
200 };
201
202 mdio@3000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
206 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
207 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
208
209 phy0: ethernet-phy@0 {
210 reg = <0>;
211 };
212 };
213
214 ata@3a00 {
215 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
216 reg = <0x3a00 0x100>;
217 interrupts = <2 7 0>;
218 };
219
220 i2c@3d00 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
224 reg = <0x3d00 0x40>;
225 interrupts = <2 15 0>;
226 fsl5200-clocking;
227 };
228
229 i2c@3d40 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
233 reg = <0x3d40 0x40>;
234 interrupts = <2 16 0>;
235 fsl5200-clocking;
236 };
237
238 sram@8000 {
239 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
240 reg = <0x8000 0x4000>;
241 };
242 };
243
244 pci@f0000d00 {
245 #interrupt-cells = <1>;
246 #size-cells = <2>;
247 #address-cells = <3>;
248 device_type = "pci";
249 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
250 reg = <0xf0000d00 0x100>;
251 interrupt-map-mask = <0xf800 0 0 7>;
252 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
253 0xc000 0 0 2 &media5200_fpga 0 3
254 0xc000 0 0 3 &media5200_fpga 0 4
255 0xc000 0 0 4 &media5200_fpga 0 5
256
257 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
258 0xc800 0 0 2 &media5200_fpga 0 4
259 0xc800 0 0 3 &media5200_fpga 0 5
260 0xc800 0 0 4 &media5200_fpga 0 2
261
262 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
263 0xd000 0 0 2 &media5200_fpga 0 5
264
265 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
266 >;
267 clock-frequency = <0>; // From boot loader
268 interrupts = <2 8 0 2 9 0 2 10 0>;
269 interrupt-parent = <&mpc5200_pic>;
270 bus-range = <0 0>;
271 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
272 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
273 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
274 };
275
276 localbus {
277 compatible = "fsl,mpc5200b-lpb","simple-bus";
278 #address-cells = <2>;
279 #size-cells = <1>;
280
281 ranges = < 0 0 0xfc000000 0x02000000
282 1 0 0xfe000000 0x02000000
283 2 0 0xf0010000 0x00010000
284 3 0 0xf0020000 0x00010000 >;
285
286 flash@0,0 {
287 compatible = "amd,am29lv28ml", "cfi-flash";
288 reg = <0 0x0 0x2000000>; // 32 MB
289 bank-width = <4>; // Width in bytes of the flash bank
290 device-width = <2>; // Two devices on each bank
291 };
292
293 flash@1,0 {
294 compatible = "amd,am29lv28ml", "cfi-flash";
295 reg = <1 0 0x2000000>; // 32 MB
296 bank-width = <4>; // Width in bytes of the flash bank
297 device-width = <2>; // Two devices on each bank
298 };
299
300 media5200_fpga: fpga@2,0 {
301 compatible = "fsl,media5200-fpga";
302 interrupt-controller;
303 #interrupt-cells = <2>; // 0:bank 1:id; no type field
304 reg = <2 0 0x10000>;
305
306 interrupt-parent = <&mpc5200_pic>;
307 interrupts = <0 0 3 // IRQ bank 0
308 1 1 3>; // IRQ bank 1
309 };
310
311 uart@3,0 {
312 compatible = "ti,tl16c752bpt";
313 reg = <3 0 0x10000>;
314 interrupt-parent = <&media5200_fpga>;
315 interrupts = <0 0 0 1>; // 2 irqs
316 };
317 };
318};
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 52ba6f98b27..7be8ca03867 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -17,6 +17,7 @@
17 compatible = "promess,motionpro"; 17 compatible = "promess,motionpro";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
@@ -74,35 +74,30 @@
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 }; 77 };
79 78
80 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
83 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
84 interrupt-parent = <&mpc5200_pic>;
85 }; 83 };
86 84
87 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
90 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
91 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
97 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 95 };
100 96
101 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
104 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
105 interrupt-parent = <&mpc5200_pic>;
106 }; 101 };
107 102
108 motionpro-led@660 { // Motion-PRO status LED 103 motionpro-led@660 { // Motion-PRO status LED
@@ -110,7 +105,6 @@
110 label = "motionpro-statusled"; 105 label = "motionpro-statusled";
111 reg = <0x660 0x10>; 106 reg = <0x660 0x10>;
112 interrupts = <1 15 0>; 107 interrupts = <1 15 0>;
113 interrupt-parent = <&mpc5200_pic>;
114 blink-delay = <100>; // 100 msec 108 blink-delay = <100>; // 100 msec
115 }; 109 };
116 110
@@ -119,49 +113,46 @@
119 label = "motionpro-readyled"; 113 label = "motionpro-readyled";
120 reg = <0x670 0x10>; 114 reg = <0x670 0x10>;
121 interrupts = <1 16 0>; 115 interrupts = <1 16 0>;
122 interrupt-parent = <&mpc5200_pic>;
123 }; 116 };
124 117
125 rtc@800 { // Real time clock 118 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 119 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>; 120 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>; 121 interrupts = <1 5 0 1 6 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 }; 122 };
131 123
132 can@980 { 124 can@980 {
133 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 125 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
134 interrupts = <2 18 0>; 126 interrupts = <2 18 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 reg = <0x980 0x80>; 127 reg = <0x980 0x80>;
137 }; 128 };
138 129
139 gpio@b00 { 130 gpio_simple: gpio@b00 {
140 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 131 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
141 reg = <0xb00 0x40>; 132 reg = <0xb00 0x40>;
142 interrupts = <1 7 0>; 133 interrupts = <1 7 0>;
143 interrupt-parent = <&mpc5200_pic>; 134 gpio-controller;
135 #gpio-cells = <2>;
144 }; 136 };
145 137
146 gpio@c00 { 138 gpio_wkup: gpio@c00 {
147 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 139 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
148 reg = <0xc00 0x40>; 140 reg = <0xc00 0x40>;
149 interrupts = <1 8 0 0 3 0>; 141 interrupts = <1 8 0 0 3 0>;
150 interrupt-parent = <&mpc5200_pic>; 142 gpio-controller;
143 #gpio-cells = <2>;
151 }; 144 };
152 145
153 spi@f00 { 146 spi@f00 {
154 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 147 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
155 reg = <0xf00 0x20>; 148 reg = <0xf00 0x20>;
156 interrupts = <2 13 0 2 14 0>; 149 interrupts = <2 13 0 2 14 0>;
157 interrupt-parent = <&mpc5200_pic>;
158 }; 150 };
159 151
160 usb@1000 { 152 usb@1000 {
161 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 153 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
162 reg = <0x1000 0xff>; 154 reg = <0x1000 0xff>;
163 interrupts = <2 6 0>; 155 interrupts = <2 6 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 }; 156 };
166 157
167 dma-controller@1200 { 158 dma-controller@1200 {
@@ -171,7 +162,6 @@
171 3 4 0 3 5 0 3 6 0 3 7 0 162 3 4 0 3 5 0 3 6 0 3 7 0
172 3 8 0 3 9 0 3 10 0 3 11 0 163 3 8 0 3 9 0 3 10 0 3 11 0
173 3 12 0 3 13 0 3 14 0 3 15 0>; 164 3 12 0 3 13 0 3 14 0 3 15 0>;
174 interrupt-parent = <&mpc5200_pic>;
175 }; 165 };
176 166
177 xlb@1f00 { 167 xlb@1f00 {
@@ -180,12 +170,9 @@
180 }; 170 };
181 171
182 serial@2000 { // PSC1 172 serial@2000 { // PSC1
183 device_type = "serial";
184 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 173 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
185 port-number = <0>; // Logical port assignment
186 reg = <0x2000 0x100>; 174 reg = <0x2000 0x100>;
187 interrupts = <2 1 0>; 175 interrupts = <2 1 0>;
188 interrupt-parent = <&mpc5200_pic>;
189 }; 176 };
190 177
191 // PSC2 in spi master mode 178 // PSC2 in spi master mode
@@ -194,26 +181,20 @@
194 cell-index = <1>; 181 cell-index = <1>;
195 reg = <0x2200 0x100>; 182 reg = <0x2200 0x100>;
196 interrupts = <2 2 0>; 183 interrupts = <2 2 0>;
197 interrupt-parent = <&mpc5200_pic>;
198 }; 184 };
199 185
200 // PSC5 in uart mode 186 // PSC5 in uart mode
201 serial@2800 { // PSC5 187 serial@2800 { // PSC5
202 device_type = "serial";
203 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 188 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
204 port-number = <4>; // Logical port assignment
205 reg = <0x2800 0x100>; 189 reg = <0x2800 0x100>;
206 interrupts = <2 12 0>; 190 interrupts = <2 12 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 191 };
209 192
210 ethernet@3000 { 193 ethernet@3000 {
211 device_type = "network";
212 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 194 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
213 reg = <0x3000 0x400>; 195 reg = <0x3000 0x400>;
214 local-mac-address = [ 00 00 00 00 00 00 ]; 196 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <2 5 0>; 197 interrupts = <2 5 0>;
216 interrupt-parent = <&mpc5200_pic>;
217 phy-handle = <&phy0>; 198 phy-handle = <&phy0>;
218 }; 199 };
219 200
@@ -223,10 +204,8 @@
223 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 204 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
224 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 205 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
225 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 206 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
226 interrupt-parent = <&mpc5200_pic>;
227 207
228 phy0: ethernet-phy@2 { 208 phy0: ethernet-phy@2 {
229 device_type = "ethernet-phy";
230 reg = <2>; 209 reg = <2>;
231 }; 210 };
232 }; 211 };
@@ -235,7 +214,6 @@
235 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 214 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
236 reg = <0x3a00 0x100>; 215 reg = <0x3a00 0x100>;
237 interrupts = <2 7 0>; 216 interrupts = <2 7 0>;
238 interrupt-parent = <&mpc5200_pic>;
239 }; 217 };
240 218
241 i2c@3d40 { 219 i2c@3d40 {
@@ -244,7 +222,6 @@
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d40 0x40>; 223 reg = <0x3d40 0x40>;
246 interrupts = <2 16 0>; 224 interrupts = <2 16 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 fsl5200-clocking; 225 fsl5200-clocking;
249 226
250 rtc@68 { 227 rtc@68 {
@@ -259,8 +236,8 @@
259 }; 236 };
260 }; 237 };
261 238
262 lpb { 239 localbus {
263 compatible = "fsl,lpb"; 240 compatible = "fsl,mpc5200b-lpb","simple-bus";
264 #address-cells = <2>; 241 #address-cells = <2>;
265 #size-cells = <1>; 242 #size-cells = <1>;
266 ranges = <0 0 0xff000000 0x01000000 243 ranges = <0 0 0xff000000 0x01000000
@@ -273,7 +250,6 @@
273 compatible = "promess,motionpro-kollmorgen"; 250 compatible = "promess,motionpro-kollmorgen";
274 reg = <1 0 0x10000>; 251 reg = <1 0 0x10000>;
275 interrupts = <1 1 0>; 252 interrupts = <1 1 0>;
276 interrupt-parent = <&mpc5200_pic>;
277 }; 253 };
278 254
279 // 8-bit board CPLD on LocalPlus Bus CS2 255 // 8-bit board CPLD on LocalPlus Bus CS2
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 71784165b77..88d691cccb3 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -22,6 +22,8 @@
22 serial0 = &serial0; 22 serial0 = &serial0;
23 serial1 = &serial1; 23 serial1 = &serial1;
24 pci0 = &pci0; 24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
25 }; 27 };
26 28
27 cpus { 29 cpus {
@@ -349,4 +351,66 @@
349 compatible = "fsl,mpc8349-pci"; 351 compatible = "fsl,mpc8349-pci";
350 device_type = "pci"; 352 device_type = "pci";
351 }; 353 };
354
355 pci1: pcie@e0009000 {
356 #address-cells = <3>;
357 #size-cells = <2>;
358 #interrupt-cells = <1>;
359 device_type = "pci";
360 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
361 reg = <0xe0009000 0x00001000>;
362 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
363 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
364 bus-range = <0 255>;
365 interrupt-map-mask = <0xf800 0 0 7>;
366 interrupt-map = <0 0 0 1 &ipic 1 8
367 0 0 0 2 &ipic 1 8
368 0 0 0 3 &ipic 1 8
369 0 0 0 4 &ipic 1 8>;
370 clock-frequency = <0>;
371
372 pcie@0 {
373 #address-cells = <3>;
374 #size-cells = <2>;
375 device_type = "pci";
376 reg = <0 0 0 0 0>;
377 ranges = <0x02000000 0 0xa0000000
378 0x02000000 0 0xa0000000
379 0 0x10000000
380 0x01000000 0 0x00000000
381 0x01000000 0 0x00000000
382 0 0x00800000>;
383 };
384 };
385
386 pci2: pcie@e000a000 {
387 #address-cells = <3>;
388 #size-cells = <2>;
389 #interrupt-cells = <1>;
390 device_type = "pci";
391 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
392 reg = <0xe000a000 0x00001000>;
393 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
394 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
395 bus-range = <0 255>;
396 interrupt-map-mask = <0xf800 0 0 7>;
397 interrupt-map = <0 0 0 1 &ipic 2 8
398 0 0 0 2 &ipic 2 8
399 0 0 0 3 &ipic 2 8
400 0 0 0 4 &ipic 2 8>;
401 clock-frequency = <0>;
402
403 pcie@0 {
404 #address-cells = <3>;
405 #size-cells = <2>;
406 device_type = "pci";
407 reg = <0 0 0 0 0>;
408 ranges = <0x02000000 0 0xc0000000
409 0x02000000 0 0xc0000000
410 0 0x10000000
411 0x01000000 0 0x00000000
412 0x01000000 0 0x00000000
413 0 0x00800000>;
414 };
415 };
352}; 416};
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 1d14d7052e6..3e3ec8fdef4 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -23,6 +23,8 @@
23 serial0 = &serial0; 23 serial0 = &serial0;
24 serial1 = &serial1; 24 serial1 = &serial1;
25 pci0 = &pci0; 25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
26 }; 28 };
27 29
28 cpus { 30 cpus {
@@ -311,12 +313,13 @@
311 fsl,descriptor-types-mask = <0x3ab0ebf>; 313 fsl,descriptor-types-mask = <0x3ab0ebf>;
312 }; 314 };
313 315
314 sdhc@2e000 { 316 sdhci@2e000 {
315 model = "eSDHC"; 317 compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
316 compatible = "fsl,esdhc";
317 reg = <0x2e000 0x1000>; 318 reg = <0x2e000 0x1000>;
318 interrupts = <42 0x8>; 319 interrupts = <42 0x8>;
319 interrupt-parent = <&ipic>; 320 interrupt-parent = <&ipic>;
321 /* Filled in by U-Boot */
322 clock-frequency = <0>;
320 }; 323 };
321 324
322 sata@18000 { 325 sata@18000 {
@@ -409,4 +412,66 @@
409 compatible = "fsl,mpc8349-pci"; 412 compatible = "fsl,mpc8349-pci";
410 device_type = "pci"; 413 device_type = "pci";
411 }; 414 };
415
416 pci1: pcie@e0009000 {
417 #address-cells = <3>;
418 #size-cells = <2>;
419 #interrupt-cells = <1>;
420 device_type = "pci";
421 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
422 reg = <0xe0009000 0x00001000>;
423 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
424 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
425 bus-range = <0 255>;
426 interrupt-map-mask = <0xf800 0 0 7>;
427 interrupt-map = <0 0 0 1 &ipic 1 8
428 0 0 0 2 &ipic 1 8
429 0 0 0 3 &ipic 1 8
430 0 0 0 4 &ipic 1 8>;
431 clock-frequency = <0>;
432
433 pcie@0 {
434 #address-cells = <3>;
435 #size-cells = <2>;
436 device_type = "pci";
437 reg = <0 0 0 0 0>;
438 ranges = <0x02000000 0 0xa8000000
439 0x02000000 0 0xa8000000
440 0 0x10000000
441 0x01000000 0 0x00000000
442 0x01000000 0 0x00000000
443 0 0x00800000>;
444 };
445 };
446
447 pci2: pcie@e000a000 {
448 #address-cells = <3>;
449 #size-cells = <2>;
450 #interrupt-cells = <1>;
451 device_type = "pci";
452 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
453 reg = <0xe000a000 0x00001000>;
454 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
455 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
456 bus-range = <0 255>;
457 interrupt-map-mask = <0xf800 0 0 7>;
458 interrupt-map = <0 0 0 1 &ipic 2 8
459 0 0 0 2 &ipic 2 8
460 0 0 0 3 &ipic 2 8
461 0 0 0 4 &ipic 2 8>;
462 clock-frequency = <0>;
463
464 pcie@0 {
465 #address-cells = <3>;
466 #size-cells = <2>;
467 device_type = "pci";
468 reg = <0 0 0 0 0>;
469 ranges = <0x02000000 0 0xc8000000
470 0x02000000 0 0xc8000000
471 0 0x10000000
472 0x01000000 0 0x00000000
473 0x01000000 0 0x00000000
474 0 0x00800000>;
475 };
476 };
412}; 477};
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 9413af3b992..fb1d884348e 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -22,6 +22,8 @@
22 serial0 = &serial0; 22 serial0 = &serial0;
23 serial1 = &serial1; 23 serial1 = &serial1;
24 pci0 = &pci0; 24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
25 }; 27 };
26 28
27 cpus { 29 cpus {
@@ -107,6 +109,24 @@
107 reg = <0x200 0x100>; 109 reg = <0x200 0x100>;
108 }; 110 };
109 111
112 gpio1: gpio-controller@c00 {
113 #gpio-cells = <2>;
114 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
115 reg = <0xc00 0x100>;
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
118 gpio-controller;
119 };
120
121 gpio2: gpio-controller@d00 {
122 #gpio-cells = <2>;
123 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
124 reg = <0xd00 0x100>;
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
127 gpio-controller;
128 };
129
110 i2c@3000 { 130 i2c@3000 {
111 #address-cells = <1>; 131 #address-cells = <1>;
112 #size-cells = <0>; 132 #size-cells = <0>;
@@ -116,6 +136,17 @@
116 interrupts = <14 0x8>; 136 interrupts = <14 0x8>;
117 interrupt-parent = <&ipic>; 137 interrupt-parent = <&ipic>;
118 dfsrr; 138 dfsrr;
139
140 dtt@48 {
141 compatible = "national,lm75";
142 reg = <0x48>;
143 };
144
145 at24@50 {
146 compatible = "at24,24c256";
147 reg = <0x50>;
148 };
149
119 rtc@68 { 150 rtc@68 {
120 compatible = "dallas,ds1339"; 151 compatible = "dallas,ds1339";
121 reg = <0x68>; 152 reg = <0x68>;
@@ -289,6 +320,15 @@
289 fsl,descriptor-types-mask = <0x3ab0ebf>; 320 fsl,descriptor-types-mask = <0x3ab0ebf>;
290 }; 321 };
291 322
323 sdhci@2e000 {
324 compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
325 reg = <0x2e000 0x1000>;
326 interrupts = <42 0x8>;
327 interrupt-parent = <&ipic>;
328 /* Filled in by U-Boot */
329 clock-frequency = <0>;
330 };
331
292 sata@18000 { 332 sata@18000 {
293 compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; 333 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
294 reg = <0x18000 0x1000>; 334 reg = <0x18000 0x1000>;
@@ -350,4 +390,66 @@
350 compatible = "fsl,mpc8349-pci"; 390 compatible = "fsl,mpc8349-pci";
351 device_type = "pci"; 391 device_type = "pci";
352 }; 392 };
393
394 pci1: pcie@e0009000 {
395 #address-cells = <3>;
396 #size-cells = <2>;
397 #interrupt-cells = <1>;
398 device_type = "pci";
399 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
400 reg = <0xe0009000 0x00001000>;
401 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
402 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
403 bus-range = <0 255>;
404 interrupt-map-mask = <0xf800 0 0 7>;
405 interrupt-map = <0 0 0 1 &ipic 1 8
406 0 0 0 2 &ipic 1 8
407 0 0 0 3 &ipic 1 8
408 0 0 0 4 &ipic 1 8>;
409 clock-frequency = <0>;
410
411 pcie@0 {
412 #address-cells = <3>;
413 #size-cells = <2>;
414 device_type = "pci";
415 reg = <0 0 0 0 0>;
416 ranges = <0x02000000 0 0xa8000000
417 0x02000000 0 0xa8000000
418 0 0x10000000
419 0x01000000 0 0x00000000
420 0x01000000 0 0x00000000
421 0 0x00800000>;
422 };
423 };
424
425 pci2: pcie@e000a000 {
426 #address-cells = <3>;
427 #size-cells = <2>;
428 #interrupt-cells = <1>;
429 device_type = "pci";
430 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
431 reg = <0xe000a000 0x00001000>;
432 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
433 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
434 bus-range = <0 255>;
435 interrupt-map-mask = <0xf800 0 0 7>;
436 interrupt-map = <0 0 0 1 &ipic 2 8
437 0 0 0 2 &ipic 2 8
438 0 0 0 3 &ipic 2 8
439 0 0 0 4 &ipic 2 8>;
440 clock-frequency = <0>;
441
442 pcie@0 {
443 #address-cells = <3>;
444 #size-cells = <2>;
445 device_type = "pci";
446 reg = <0 0 0 0 0>;
447 ranges = <0x02000000 0 0xc8000000
448 0x02000000 0 0xc8000000
449 0 0x10000000
450 0x01000000 0 0x00000000
451 0x01000000 0 0x00000000
452 0 0x00800000>;
453 };
454 };
353}; 455};
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index b85fc02682d..c3b212cf902 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -23,6 +23,8 @@
23 serial0 = &serial0; 23 serial0 = &serial0;
24 serial1 = &serial1; 24 serial1 = &serial1;
25 pci0 = &pci0; 25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
26 }; 28 };
27 29
28 cpus { 30 cpus {
@@ -311,12 +313,13 @@
311 fsl,descriptor-types-mask = <0x3ab0ebf>; 313 fsl,descriptor-types-mask = <0x3ab0ebf>;
312 }; 314 };
313 315
314 sdhc@2e000 { 316 sdhci@2e000 {
315 model = "eSDHC"; 317 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
316 compatible = "fsl,esdhc";
317 reg = <0x2e000 0x1000>; 318 reg = <0x2e000 0x1000>;
318 interrupts = <42 0x8>; 319 interrupts = <42 0x8>;
319 interrupt-parent = <&ipic>; 320 interrupt-parent = <&ipic>;
321 /* Filled in by U-Boot */
322 clock-frequency = <0>;
320 }; 323 };
321 324
322 /* IPIC 325 /* IPIC
@@ -395,4 +398,66 @@
395 compatible = "fsl,mpc8349-pci"; 398 compatible = "fsl,mpc8349-pci";
396 device_type = "pci"; 399 device_type = "pci";
397 }; 400 };
401
402 pci1: pcie@e0009000 {
403 #address-cells = <3>;
404 #size-cells = <2>;
405 #interrupt-cells = <1>;
406 device_type = "pci";
407 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
408 reg = <0xe0009000 0x00001000>;
409 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
410 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
411 bus-range = <0 255>;
412 interrupt-map-mask = <0xf800 0 0 7>;
413 interrupt-map = <0 0 0 1 &ipic 1 8
414 0 0 0 2 &ipic 1 8
415 0 0 0 3 &ipic 1 8
416 0 0 0 4 &ipic 1 8>;
417 clock-frequency = <0>;
418
419 pcie@0 {
420 #address-cells = <3>;
421 #size-cells = <2>;
422 device_type = "pci";
423 reg = <0 0 0 0 0>;
424 ranges = <0x02000000 0 0xa8000000
425 0x02000000 0 0xa8000000
426 0 0x10000000
427 0x01000000 0 0x00000000
428 0x01000000 0 0x00000000
429 0 0x00800000>;
430 };
431 };
432
433 pci2: pcie@e000a000 {
434 #address-cells = <3>;
435 #size-cells = <2>;
436 #interrupt-cells = <1>;
437 device_type = "pci";
438 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
439 reg = <0xe000a000 0x00001000>;
440 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
441 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
442 bus-range = <0 255>;
443 interrupt-map-mask = <0xf800 0 0 7>;
444 interrupt-map = <0 0 0 1 &ipic 2 8
445 0 0 0 2 &ipic 2 8
446 0 0 0 3 &ipic 2 8
447 0 0 0 4 &ipic 2 8>;
448 clock-frequency = <0>;
449
450 pcie@0 {
451 #address-cells = <3>;
452 #size-cells = <2>;
453 device_type = "pci";
454 reg = <0 0 0 0 0>;
455 ranges = <0x02000000 0 0xc8000000
456 0x02000000 0 0xc8000000
457 0 0x10000000
458 0x01000000 0 0x00000000
459 0x01000000 0 0x00000000
460 0 0x00800000>;
461 };
462 };
398}; 463};
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 23c10ce22c2..37c8555cc8d 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -22,6 +22,8 @@
22 serial0 = &serial0; 22 serial0 = &serial0;
23 serial1 = &serial1; 23 serial1 = &serial1;
24 pci0 = &pci0; 24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
25 }; 27 };
26 28
27 cpus { 29 cpus {
@@ -107,6 +109,24 @@
107 reg = <0x200 0x100>; 109 reg = <0x200 0x100>;
108 }; 110 };
109 111
112 gpio1: gpio-controller@c00 {
113 #gpio-cells = <2>;
114 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
115 reg = <0xc00 0x100>;
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
118 gpio-controller;
119 };
120
121 gpio2: gpio-controller@d00 {
122 #gpio-cells = <2>;
123 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
124 reg = <0xd00 0x100>;
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
127 gpio-controller;
128 };
129
110 i2c@3000 { 130 i2c@3000 {
111 #address-cells = <1>; 131 #address-cells = <1>;
112 #size-cells = <0>; 132 #size-cells = <0>;
@@ -116,6 +136,17 @@
116 interrupts = <14 0x8>; 136 interrupts = <14 0x8>;
117 interrupt-parent = <&ipic>; 137 interrupt-parent = <&ipic>;
118 dfsrr; 138 dfsrr;
139
140 dtt@48 {
141 compatible = "national,lm75";
142 reg = <0x48>;
143 };
144
145 at24@50 {
146 compatible = "at24,24c256";
147 reg = <0x50>;
148 };
149
119 rtc@68 { 150 rtc@68 {
120 compatible = "dallas,ds1339"; 151 compatible = "dallas,ds1339";
121 reg = <0x68>; 152 reg = <0x68>;
@@ -287,6 +318,15 @@
287 fsl,descriptor-types-mask = <0x3ab0ebf>; 318 fsl,descriptor-types-mask = <0x3ab0ebf>;
288 }; 319 };
289 320
321 sdhci@2e000 {
322 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
323 reg = <0x2e000 0x1000>;
324 interrupts = <42 0x8>;
325 interrupt-parent = <&ipic>;
326 /* Filled in by U-Boot */
327 clock-frequency = <0>;
328 };
329
290 /* IPIC 330 /* IPIC
291 * interrupts cell = <intr #, sense> 331 * interrupts cell = <intr #, sense>
292 * sense values match linux IORESOURCE_IRQ_* defines: 332 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -334,4 +374,66 @@
334 compatible = "fsl,mpc8349-pci"; 374 compatible = "fsl,mpc8349-pci";
335 device_type = "pci"; 375 device_type = "pci";
336 }; 376 };
377
378 pci1: pcie@e0009000 {
379 #address-cells = <3>;
380 #size-cells = <2>;
381 #interrupt-cells = <1>;
382 device_type = "pci";
383 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
384 reg = <0xe0009000 0x00001000>;
385 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
386 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
387 bus-range = <0 255>;
388 interrupt-map-mask = <0xf800 0 0 7>;
389 interrupt-map = <0 0 0 1 &ipic 1 8
390 0 0 0 2 &ipic 1 8
391 0 0 0 3 &ipic 1 8
392 0 0 0 4 &ipic 1 8>;
393 clock-frequency = <0>;
394
395 pcie@0 {
396 #address-cells = <3>;
397 #size-cells = <2>;
398 device_type = "pci";
399 reg = <0 0 0 0 0>;
400 ranges = <0x02000000 0 0xa8000000
401 0x02000000 0 0xa8000000
402 0 0x10000000
403 0x01000000 0 0x00000000
404 0x01000000 0 0x00000000
405 0 0x00800000>;
406 };
407 };
408
409 pci2: pcie@e000a000 {
410 #address-cells = <3>;
411 #size-cells = <2>;
412 #interrupt-cells = <1>;
413 device_type = "pci";
414 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
415 reg = <0xe000a000 0x00001000>;
416 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
417 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
418 bus-range = <0 255>;
419 interrupt-map-mask = <0xf800 0 0 7>;
420 interrupt-map = <0 0 0 1 &ipic 2 8
421 0 0 0 2 &ipic 2 8
422 0 0 0 3 &ipic 2 8
423 0 0 0 4 &ipic 2 8>;
424 clock-frequency = <0>;
425
426 pcie@0 {
427 #address-cells = <3>;
428 #size-cells = <2>;
429 device_type = "pci";
430 reg = <0 0 0 0 0>;
431 ranges = <0x02000000 0 0xc8000000
432 0x02000000 0 0xc8000000
433 0 0x10000000
434 0x01000000 0 0x00000000
435 0x01000000 0 0x00000000
436 0 0x00800000>;
437 };
438 };
337}; 439};
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index acf06c438db..1b61cda1eb4 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -310,12 +310,13 @@
310 fsl,descriptor-types-mask = <0x3ab0ebf>; 310 fsl,descriptor-types-mask = <0x3ab0ebf>;
311 }; 311 };
312 312
313 sdhc@2e000 { 313 sdhci@2e000 {
314 model = "eSDHC"; 314 compatible = "fsl,mpc8379-esdhc";
315 compatible = "fsl,esdhc";
316 reg = <0x2e000 0x1000>; 315 reg = <0x2e000 0x1000>;
317 interrupts = <42 0x8>; 316 interrupts = <42 0x8>;
318 interrupt-parent = <&ipic>; 317 interrupt-parent = <&ipic>;
318 /* Filled in by U-Boot */
319 clock-frequency = <0>;
319 }; 320 };
320 321
321 sata@18000 { 322 sata@18000 {
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 72cdc3c4c7e..e2f98e6a51a 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -107,6 +107,24 @@
107 reg = <0x200 0x100>; 107 reg = <0x200 0x100>;
108 }; 108 };
109 109
110 gpio1: gpio-controller@c00 {
111 #gpio-cells = <2>;
112 compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
113 reg = <0xc00 0x100>;
114 interrupts = <74 0x8>;
115 interrupt-parent = <&ipic>;
116 gpio-controller;
117 };
118
119 gpio2: gpio-controller@d00 {
120 #gpio-cells = <2>;
121 compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
122 reg = <0xd00 0x100>;
123 interrupts = <75 0x8>;
124 interrupt-parent = <&ipic>;
125 gpio-controller;
126 };
127
110 i2c@3000 { 128 i2c@3000 {
111 #address-cells = <1>; 129 #address-cells = <1>;
112 #size-cells = <0>; 130 #size-cells = <0>;
@@ -116,6 +134,17 @@
116 interrupts = <14 0x8>; 134 interrupts = <14 0x8>;
117 interrupt-parent = <&ipic>; 135 interrupt-parent = <&ipic>;
118 dfsrr; 136 dfsrr;
137
138 dtt@48 {
139 compatible = "national,lm75";
140 reg = <0x48>;
141 };
142
143 at24@50 {
144 compatible = "at24,24c256";
145 reg = <0x50>;
146 };
147
119 rtc@68 { 148 rtc@68 {
120 compatible = "dallas,ds1339"; 149 compatible = "dallas,ds1339";
121 reg = <0x68>; 150 reg = <0x68>;
@@ -288,6 +317,15 @@
288 fsl,descriptor-types-mask = <0x3ab0ebf>; 317 fsl,descriptor-types-mask = <0x3ab0ebf>;
289 }; 318 };
290 319
320 sdhci@2e000 {
321 compatible = "fsl,mpc8379-esdhc";
322 reg = <0x2e000 0x1000>;
323 interrupts = <42 0x8>;
324 interrupt-parent = <&ipic>;
325 /* Filled in by U-Boot */
326 clock-frequency = <0>;
327 };
328
291 sata@18000 { 329 sata@18000 {
292 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 330 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
293 reg = <0x18000 0x1000>; 331 reg = <0x18000 0x1000>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 359c3b72742..6c9354b2d7b 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8572 DS Device Tree Source 2 * MPC8572 DS Device Tree Source
3 * 3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -643,7 +643,7 @@
643 643
644 0x1000000 0x0 0x0 644 0x1000000 0x0 0x0
645 0x1000000 0x0 0x0 645 0x1000000 0x0 0x0
646 0x0 0x100000>; 646 0x0 0x10000>;
647 uli1575@0 { 647 uli1575@0 {
648 reg = <0x0 0x0 0x0 0x0 0x0>; 648 reg = <0x0 0x0 0x0 0x0 0x0>;
649 #size-cells = <2>; 649 #size-cells = <2>;
@@ -654,7 +654,7 @@
654 654
655 0x1000000 0x0 0x0 655 0x1000000 0x0 0x0
656 0x1000000 0x0 0x0 656 0x1000000 0x0 0x0
657 0x0 0x100000>; 657 0x0 0x10000>;
658 isa@1e { 658 isa@1e {
659 device_type = "isa"; 659 device_type = "isa";
660 #interrupt-cells = <2>; 660 #interrupt-cells = <2>;
@@ -744,7 +744,7 @@
744 744
745 0x1000000 0x0 0x0 745 0x1000000 0x0 0x0
746 0x1000000 0x0 0x0 746 0x1000000 0x0 0x0
747 0x0 0x100000>; 747 0x0 0x10000>;
748 }; 748 };
749 }; 749 };
750 750
@@ -781,7 +781,7 @@
781 781
782 0x1000000 0x0 0x0 782 0x1000000 0x0 0x0
783 0x1000000 0x0 0x0 783 0x1000000 0x0 0x0
784 0x0 0x100000>; 784 0x0 0x10000>;
785 }; 785 };
786 }; 786 };
787}; 787};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
new file mode 100644
index 00000000000..fc7dbf49f4c
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
@@ -0,0 +1,787 @@
1/*
2 * MPC8572 DS Device Tree Source
3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47
48 PowerPC,8572@1 {
49 device_type = "cpu";
50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
59 };
60 };
61
62 memory {
63 device_type = "memory";
64 };
65
66 localbus@fffe05000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0xf 0xffe05000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
73
74 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
75 0x1 0x0 0xf 0xe0000000 0x08000000
76 0x2 0x0 0xf 0xffa00000 0x00040000
77 0x3 0x0 0xf 0xffdf0000 0x00008000
78 0x4 0x0 0xf 0xffa40000 0x00040000
79 0x5 0x0 0xf 0xffa80000 0x00040000
80 0x6 0x0 0xf 0xffac0000 0x00040000>;
81
82 nor@0,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
87 bank-width = <2>;
88 device-width = <1>;
89
90 ramdisk@0 {
91 reg = <0x0 0x03000000>;
92 read-only;
93 };
94
95 diagnostic@3000000 {
96 reg = <0x03000000 0x00e00000>;
97 read-only;
98 };
99
100 dink@3e00000 {
101 reg = <0x03e00000 0x00200000>;
102 read-only;
103 };
104
105 kernel@4000000 {
106 reg = <0x04000000 0x00400000>;
107 read-only;
108 };
109
110 jffs2@4400000 {
111 reg = <0x04400000 0x03b00000>;
112 };
113
114 dtb@7f00000 {
115 reg = <0x07f00000 0x00080000>;
116 read-only;
117 };
118
119 u-boot@7f80000 {
120 reg = <0x07f80000 0x00080000>;
121 read-only;
122 };
123 };
124
125 nand@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
129 "fsl,elbc-fcm-nand";
130 reg = <0x2 0x0 0x40000>;
131
132 u-boot@0 {
133 reg = <0x0 0x02000000>;
134 read-only;
135 };
136
137 jffs2@2000000 {
138 reg = <0x02000000 0x10000000>;
139 };
140
141 ramdisk@12000000 {
142 reg = <0x12000000 0x08000000>;
143 read-only;
144 };
145
146 kernel@1a000000 {
147 reg = <0x1a000000 0x04000000>;
148 };
149
150 dtb@1e000000 {
151 reg = <0x1e000000 0x01000000>;
152 read-only;
153 };
154
155 empty@1f000000 {
156 reg = <0x1f000000 0x21000000>;
157 };
158 };
159
160 nand@4,0 {
161 compatible = "fsl,mpc8572-fcm-nand",
162 "fsl,elbc-fcm-nand";
163 reg = <0x4 0x0 0x40000>;
164 };
165
166 nand@5,0 {
167 compatible = "fsl,mpc8572-fcm-nand",
168 "fsl,elbc-fcm-nand";
169 reg = <0x5 0x0 0x40000>;
170 };
171
172 nand@6,0 {
173 compatible = "fsl,mpc8572-fcm-nand",
174 "fsl,elbc-fcm-nand";
175 reg = <0x6 0x0 0x40000>;
176 };
177 };
178
179 soc8572@fffe00000 {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "soc";
183 compatible = "simple-bus";
184 ranges = <0x0 0xf 0xffe00000 0x100000>;
185 reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
186 bus-frequency = <0>; // Filled out by uboot.
187
188 memory-controller@2000 {
189 compatible = "fsl,mpc8572-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <18 2>;
193 };
194
195 memory-controller@6000 {
196 compatible = "fsl,mpc8572-memory-controller";
197 reg = <0x6000 0x1000>;
198 interrupt-parent = <&mpic>;
199 interrupts = <18 2>;
200 };
201
202 L2: l2-cache-controller@20000 {
203 compatible = "fsl,mpc8572-l2-cache-controller";
204 reg = <0x20000 0x1000>;
205 cache-line-size = <32>; // 32 bytes
206 cache-size = <0x100000>; // L2, 1M
207 interrupt-parent = <&mpic>;
208 interrupts = <16 2>;
209 };
210
211 i2c@3000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 cell-index = <0>;
215 compatible = "fsl-i2c";
216 reg = <0x3000 0x100>;
217 interrupts = <43 2>;
218 interrupt-parent = <&mpic>;
219 dfsrr;
220 };
221
222 i2c@3100 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 cell-index = <1>;
226 compatible = "fsl-i2c";
227 reg = <0x3100 0x100>;
228 interrupts = <43 2>;
229 interrupt-parent = <&mpic>;
230 dfsrr;
231 };
232
233 dma@c300 {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
237 reg = <0xc300 0x4>;
238 ranges = <0x0 0xc100 0x200>;
239 cell-index = <1>;
240 dma-channel@0 {
241 compatible = "fsl,mpc8572-dma-channel",
242 "fsl,eloplus-dma-channel";
243 reg = <0x0 0x80>;
244 cell-index = <0>;
245 interrupt-parent = <&mpic>;
246 interrupts = <76 2>;
247 };
248 dma-channel@80 {
249 compatible = "fsl,mpc8572-dma-channel",
250 "fsl,eloplus-dma-channel";
251 reg = <0x80 0x80>;
252 cell-index = <1>;
253 interrupt-parent = <&mpic>;
254 interrupts = <77 2>;
255 };
256 dma-channel@100 {
257 compatible = "fsl,mpc8572-dma-channel",
258 "fsl,eloplus-dma-channel";
259 reg = <0x100 0x80>;
260 cell-index = <2>;
261 interrupt-parent = <&mpic>;
262 interrupts = <78 2>;
263 };
264 dma-channel@180 {
265 compatible = "fsl,mpc8572-dma-channel",
266 "fsl,eloplus-dma-channel";
267 reg = <0x180 0x80>;
268 cell-index = <3>;
269 interrupt-parent = <&mpic>;
270 interrupts = <79 2>;
271 };
272 };
273
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,mpc8572-dma-channel",
283 "fsl,eloplus-dma-channel";
284 reg = <0x0 0x80>;
285 cell-index = <0>;
286 interrupt-parent = <&mpic>;
287 interrupts = <20 2>;
288 };
289 dma-channel@80 {
290 compatible = "fsl,mpc8572-dma-channel",
291 "fsl,eloplus-dma-channel";
292 reg = <0x80 0x80>;
293 cell-index = <1>;
294 interrupt-parent = <&mpic>;
295 interrupts = <21 2>;
296 };
297 dma-channel@100 {
298 compatible = "fsl,mpc8572-dma-channel",
299 "fsl,eloplus-dma-channel";
300 reg = <0x100 0x80>;
301 cell-index = <2>;
302 interrupt-parent = <&mpic>;
303 interrupts = <22 2>;
304 };
305 dma-channel@180 {
306 compatible = "fsl,mpc8572-dma-channel",
307 "fsl,eloplus-dma-channel";
308 reg = <0x180 0x80>;
309 cell-index = <3>;
310 interrupt-parent = <&mpic>;
311 interrupts = <23 2>;
312 };
313 };
314
315 mdio@24520 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "fsl,gianfar-mdio";
319 reg = <0x24520 0x20>;
320
321 phy0: ethernet-phy@0 {
322 interrupt-parent = <&mpic>;
323 interrupts = <10 1>;
324 reg = <0x0>;
325 };
326 phy1: ethernet-phy@1 {
327 interrupt-parent = <&mpic>;
328 interrupts = <10 1>;
329 reg = <0x1>;
330 };
331 phy2: ethernet-phy@2 {
332 interrupt-parent = <&mpic>;
333 interrupts = <10 1>;
334 reg = <0x2>;
335 };
336 phy3: ethernet-phy@3 {
337 interrupt-parent = <&mpic>;
338 interrupts = <10 1>;
339 reg = <0x3>;
340 };
341
342 tbi0: tbi-phy@11 {
343 reg = <0x11>;
344 device_type = "tbi-phy";
345 };
346 };
347
348 mdio@25520 {
349 #address-cells = <1>;
350 #size-cells = <0>;
351 compatible = "fsl,gianfar-tbi";
352 reg = <0x25520 0x20>;
353
354 tbi1: tbi-phy@11 {
355 reg = <0x11>;
356 device_type = "tbi-phy";
357 };
358 };
359
360 mdio@26520 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 compatible = "fsl,gianfar-tbi";
364 reg = <0x26520 0x20>;
365
366 tbi2: tbi-phy@11 {
367 reg = <0x11>;
368 device_type = "tbi-phy";
369 };
370 };
371
372 mdio@27520 {
373 #address-cells = <1>;
374 #size-cells = <0>;
375 compatible = "fsl,gianfar-tbi";
376 reg = <0x27520 0x20>;
377
378 tbi3: tbi-phy@11 {
379 reg = <0x11>;
380 device_type = "tbi-phy";
381 };
382 };
383
384 enet0: ethernet@24000 {
385 cell-index = <0>;
386 device_type = "network";
387 model = "eTSEC";
388 compatible = "gianfar";
389 reg = <0x24000 0x1000>;
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 interrupts = <29 2 30 2 34 2>;
392 interrupt-parent = <&mpic>;
393 tbi-handle = <&tbi0>;
394 phy-handle = <&phy0>;
395 phy-connection-type = "rgmii-id";
396 };
397
398 enet1: ethernet@25000 {
399 cell-index = <1>;
400 device_type = "network";
401 model = "eTSEC";
402 compatible = "gianfar";
403 reg = <0x25000 0x1000>;
404 local-mac-address = [ 00 00 00 00 00 00 ];
405 interrupts = <35 2 36 2 40 2>;
406 interrupt-parent = <&mpic>;
407 tbi-handle = <&tbi1>;
408 phy-handle = <&phy1>;
409 phy-connection-type = "rgmii-id";
410 };
411
412 enet2: ethernet@26000 {
413 cell-index = <2>;
414 device_type = "network";
415 model = "eTSEC";
416 compatible = "gianfar";
417 reg = <0x26000 0x1000>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupts = <31 2 32 2 33 2>;
420 interrupt-parent = <&mpic>;
421 tbi-handle = <&tbi2>;
422 phy-handle = <&phy2>;
423 phy-connection-type = "rgmii-id";
424 };
425
426 enet3: ethernet@27000 {
427 cell-index = <3>;
428 device_type = "network";
429 model = "eTSEC";
430 compatible = "gianfar";
431 reg = <0x27000 0x1000>;
432 local-mac-address = [ 00 00 00 00 00 00 ];
433 interrupts = <37 2 38 2 39 2>;
434 interrupt-parent = <&mpic>;
435 tbi-handle = <&tbi3>;
436 phy-handle = <&phy3>;
437 phy-connection-type = "rgmii-id";
438 };
439
440 serial0: serial@4500 {
441 cell-index = <0>;
442 device_type = "serial";
443 compatible = "ns16550";
444 reg = <0x4500 0x100>;
445 clock-frequency = <0>;
446 interrupts = <42 2>;
447 interrupt-parent = <&mpic>;
448 };
449
450 serial1: serial@4600 {
451 cell-index = <1>;
452 device_type = "serial";
453 compatible = "ns16550";
454 reg = <0x4600 0x100>;
455 clock-frequency = <0>;
456 interrupts = <42 2>;
457 interrupt-parent = <&mpic>;
458 };
459
460 global-utilities@e0000 { //global utilities block
461 compatible = "fsl,mpc8572-guts";
462 reg = <0xe0000 0x1000>;
463 fsl,has-rstcr;
464 };
465
466 msi@41600 {
467 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
468 reg = <0x41600 0x80>;
469 msi-available-ranges = <0 0x100>;
470 interrupts = <
471 0xe0 0
472 0xe1 0
473 0xe2 0
474 0xe3 0
475 0xe4 0
476 0xe5 0
477 0xe6 0
478 0xe7 0>;
479 interrupt-parent = <&mpic>;
480 };
481
482 crypto@30000 {
483 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
484 "fsl,sec2.1", "fsl,sec2.0";
485 reg = <0x30000 0x10000>;
486 interrupts = <45 2 58 2>;
487 interrupt-parent = <&mpic>;
488 fsl,num-channels = <4>;
489 fsl,channel-fifo-len = <24>;
490 fsl,exec-units-mask = <0x9fe>;
491 fsl,descriptor-types-mask = <0x3ab0ebf>;
492 };
493
494 mpic: pic@40000 {
495 interrupt-controller;
496 #address-cells = <0>;
497 #interrupt-cells = <2>;
498 reg = <0x40000 0x40000>;
499 compatible = "chrp,open-pic";
500 device_type = "open-pic";
501 };
502 };
503
504 pci0: pcie@fffe08000 {
505 cell-index = <0>;
506 compatible = "fsl,mpc8548-pcie";
507 device_type = "pci";
508 #interrupt-cells = <1>;
509 #size-cells = <2>;
510 #address-cells = <3>;
511 reg = <0xf 0xffe08000 0 0x1000>;
512 bus-range = <0 255>;
513 ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000
514 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
515 clock-frequency = <33333333>;
516 interrupt-parent = <&mpic>;
517 interrupts = <24 2>;
518 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
519 interrupt-map = <
520 /* IDSEL 0x11 func 0 - PCI slot 1 */
521 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
522 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
523 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
524 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
525
526 /* IDSEL 0x11 func 1 - PCI slot 1 */
527 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
528 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
529 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
530 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
531
532 /* IDSEL 0x11 func 2 - PCI slot 1 */
533 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
534 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
535 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
536 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
537
538 /* IDSEL 0x11 func 3 - PCI slot 1 */
539 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
540 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
541 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
542 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
543
544 /* IDSEL 0x11 func 4 - PCI slot 1 */
545 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
546 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
547 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
548 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
549
550 /* IDSEL 0x11 func 5 - PCI slot 1 */
551 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
552 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
553 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
554 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
555
556 /* IDSEL 0x11 func 6 - PCI slot 1 */
557 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
558 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
559 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
560 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
561
562 /* IDSEL 0x11 func 7 - PCI slot 1 */
563 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
564 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
565 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
566 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
567
568 /* IDSEL 0x12 func 0 - PCI slot 2 */
569 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
570 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
571 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
572 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
573
574 /* IDSEL 0x12 func 1 - PCI slot 2 */
575 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
576 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
577 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
578 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
579
580 /* IDSEL 0x12 func 2 - PCI slot 2 */
581 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
582 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
583 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
584 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
585
586 /* IDSEL 0x12 func 3 - PCI slot 2 */
587 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
588 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
589 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
590 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
591
592 /* IDSEL 0x12 func 4 - PCI slot 2 */
593 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
594 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
595 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
596 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
597
598 /* IDSEL 0x12 func 5 - PCI slot 2 */
599 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
600 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
601 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
602 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
603
604 /* IDSEL 0x12 func 6 - PCI slot 2 */
605 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
606 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
607 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
608 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
609
610 /* IDSEL 0x12 func 7 - PCI slot 2 */
611 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
612 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
613 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
614 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
615
616 // IDSEL 0x1c USB
617 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
618 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
619 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
620 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
621
622 // IDSEL 0x1d Audio
623 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
624
625 // IDSEL 0x1e Legacy
626 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
627 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
628
629 // IDSEL 0x1f IDE/SATA
630 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
631 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
632
633 >;
634
635 pcie@0 {
636 reg = <0x0 0x0 0x0 0x0 0x0>;
637 #size-cells = <2>;
638 #address-cells = <3>;
639 device_type = "pci";
640 ranges = <0x2000000 0x0 0xc0000000
641 0x2000000 0x0 0xc0000000
642 0x0 0x20000000
643
644 0x1000000 0x0 0x0
645 0x1000000 0x0 0x0
646 0x0 0x10000>;
647 uli1575@0 {
648 reg = <0x0 0x0 0x0 0x0 0x0>;
649 #size-cells = <2>;
650 #address-cells = <3>;
651 ranges = <0x2000000 0x0 0xc0000000
652 0x2000000 0x0 0xc0000000
653 0x0 0x20000000
654
655 0x1000000 0x0 0x0
656 0x1000000 0x0 0x0
657 0x0 0x10000>;
658 isa@1e {
659 device_type = "isa";
660 #interrupt-cells = <2>;
661 #size-cells = <1>;
662 #address-cells = <2>;
663 reg = <0xf000 0x0 0x0 0x0 0x0>;
664 ranges = <0x1 0x0 0x1000000 0x0 0x0
665 0x1000>;
666 interrupt-parent = <&i8259>;
667
668 i8259: interrupt-controller@20 {
669 reg = <0x1 0x20 0x2
670 0x1 0xa0 0x2
671 0x1 0x4d0 0x2>;
672 interrupt-controller;
673 device_type = "interrupt-controller";
674 #address-cells = <0>;
675 #interrupt-cells = <2>;
676 compatible = "chrp,iic";
677 interrupts = <9 2>;
678 interrupt-parent = <&mpic>;
679 };
680
681 i8042@60 {
682 #size-cells = <0>;
683 #address-cells = <1>;
684 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
685 interrupts = <1 3 12 3>;
686 interrupt-parent =
687 <&i8259>;
688
689 keyboard@0 {
690 reg = <0x0>;
691 compatible = "pnpPNP,303";
692 };
693
694 mouse@1 {
695 reg = <0x1>;
696 compatible = "pnpPNP,f03";
697 };
698 };
699
700 rtc@70 {
701 compatible = "pnpPNP,b00";
702 reg = <0x1 0x70 0x2>;
703 };
704
705 gpio@400 {
706 reg = <0x1 0x400 0x80>;
707 };
708 };
709 };
710 };
711
712 };
713
714 pci1: pcie@fffe09000 {
715 cell-index = <1>;
716 compatible = "fsl,mpc8548-pcie";
717 device_type = "pci";
718 #interrupt-cells = <1>;
719 #size-cells = <2>;
720 #address-cells = <3>;
721 reg = <0xf 0xffe09000 0 0x1000>;
722 bus-range = <0 255>;
723 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
724 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
725 clock-frequency = <33333333>;
726 interrupt-parent = <&mpic>;
727 interrupts = <25 2>;
728 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
729 interrupt-map = <
730 /* IDSEL 0x0 */
731 0000 0x0 0x0 0x1 &mpic 0x4 0x1
732 0000 0x0 0x0 0x2 &mpic 0x5 0x1
733 0000 0x0 0x0 0x3 &mpic 0x6 0x1
734 0000 0x0 0x0 0x4 &mpic 0x7 0x1
735 >;
736 pcie@0 {
737 reg = <0x0 0x0 0x0 0x0 0x0>;
738 #size-cells = <2>;
739 #address-cells = <3>;
740 device_type = "pci";
741 ranges = <0x2000000 0x0 0xc0000000
742 0x2000000 0x0 0xc0000000
743 0x0 0x20000000
744
745 0x1000000 0x0 0x0
746 0x1000000 0x0 0x0
747 0x0 0x10000>;
748 };
749 };
750
751 pci2: pcie@fffe0a000 {
752 cell-index = <2>;
753 compatible = "fsl,mpc8548-pcie";
754 device_type = "pci";
755 #interrupt-cells = <1>;
756 #size-cells = <2>;
757 #address-cells = <3>;
758 reg = <0xf 0xffe0a000 0 0x1000>;
759 bus-range = <0 255>;
760 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
761 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
762 clock-frequency = <33333333>;
763 interrupt-parent = <&mpic>;
764 interrupts = <26 2>;
765 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
766 interrupt-map = <
767 /* IDSEL 0x0 */
768 0000 0x0 0x0 0x1 &mpic 0x0 0x1
769 0000 0x0 0x0 0x2 &mpic 0x1 0x1
770 0000 0x0 0x0 0x3 &mpic 0x2 0x1
771 0000 0x0 0x0 0x4 &mpic 0x3 0x1
772 >;
773 pcie@0 {
774 reg = <0x0 0x0 0x0 0x0 0x0>;
775 #size-cells = <2>;
776 #address-cells = <3>;
777 device_type = "pci";
778 ranges = <0x2000000 0x0 0xc0000000
779 0x2000000 0x0 0xc0000000
780 0x0 0x20000000
781
782 0x1000000 0x0 0x0
783 0x1000000 0x0 0x0
784 0x0 0x10000>;
785 };
786 };
787};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index fd462efa9e6..32178bfa77d 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -6,7 +6,7 @@
6 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0, 6 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
7 * eth1, crypto, pci0, pci1. 7 * eth1, crypto, pci0, pci1.
8 * 8 *
9 * Copyright 2007, 2008 Freescale Semiconductor Inc. 9 * Copyright 2007-2009 Freescale Semiconductor Inc.
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify it 11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the 12 * under the terms of the GNU General Public License as published by the
@@ -227,7 +227,7 @@
227 device_type = "open-pic"; 227 device_type = "open-pic";
228 protected-sources = < 228 protected-sources = <
229 31 32 33 37 38 39 /* enet2 enet3 */ 229 31 32 33 37 38 39 /* enet2 enet3 */
230 76 77 78 79 27 42 /* dma2 pci2 serial*/ 230 76 77 78 79 26 42 /* dma2 pci2 serial*/
231 0xe0 0xe1 0xe2 0xe3 /* msi */ 231 0xe0 0xe1 0xe2 0xe3 /* msi */
232 0xe4 0xe5 0xe6 0xe7 232 0xe4 0xe5 0xe6 0xe7
233 >; 233 >;
@@ -376,7 +376,7 @@
376 376
377 0x1000000 0x0 0x0 377 0x1000000 0x0 0x0
378 0x1000000 0x0 0x0 378 0x1000000 0x0 0x0
379 0x0 0x100000>; 379 0x0 0x10000>;
380 uli1575@0 { 380 uli1575@0 {
381 reg = <0x0 0x0 0x0 0x0 0x0>; 381 reg = <0x0 0x0 0x0 0x0 0x0>;
382 #size-cells = <2>; 382 #size-cells = <2>;
@@ -387,7 +387,7 @@
387 387
388 0x1000000 0x0 0x0 388 0x1000000 0x0 0x0
389 0x1000000 0x0 0x0 389 0x1000000 0x0 0x0
390 0x0 0x100000>; 390 0x0 0x10000>;
391 isa@1e { 391 isa@1e {
392 device_type = "isa"; 392 device_type = "isa";
393 #interrupt-cells = <2>; 393 #interrupt-cells = <2>;
@@ -477,7 +477,7 @@
477 477
478 0x1000000 0x0 0x0 478 0x1000000 0x0 0x0
479 0x1000000 0x0 0x0 479 0x1000000 0x0 0x0
480 0x0 0x100000>; 480 0x0 0x10000>;
481 }; 481 };
482 }; 482 };
483}; 483};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index e35230f2ac9..159cb3a875f 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -7,7 +7,7 @@
7 * 7 *
8 * Please note to add "-b 1" for core1's dts compiling. 8 * Please note to add "-b 1" for core1's dts compiling.
9 * 9 *
10 * Copyright 2007, 2008 Freescale Semiconductor Inc. 10 * Copyright 2007-2009 Freescale Semiconductor Inc.
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
@@ -186,7 +186,7 @@
186 protected-sources = < 186 protected-sources = <
187 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */ 187 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
188 29 30 34 35 36 40 /* enet0 enet1 */ 188 29 30 34 35 36 40 /* enet0 enet1 */
189 24 26 20 21 22 23 /* pcie0 pcie1 dma1 */ 189 24 25 20 21 22 23 /* pci0 pci1 dma1 */
190 43 /* i2c */ 190 43 /* i2c */
191 0x1 0x2 0x3 0x4 /* pci slot */ 191 0x1 0x2 0x3 0x4 /* pci slot */
192 0x9 0xa 0xb 0xc /* usb */ 192 0x9 0xa 0xb 0xc /* usb */
@@ -228,7 +228,7 @@
228 228
229 0x1000000 0x0 0x0 229 0x1000000 0x0 0x0
230 0x1000000 0x0 0x0 230 0x1000000 0x0 0x0
231 0x0 0x100000>; 231 0x0 0x10000>;
232 }; 232 };
233 }; 233 };
234}; 234};
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index f724d72c7b9..1bd3ebe1143 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -217,6 +217,7 @@
217 codec-handle = <&cs4270>; 217 codec-handle = <&cs4270>;
218 fsl,playback-dma = <&dma00>; 218 fsl,playback-dma = <&dma00>;
219 fsl,capture-dma = <&dma01>; 219 fsl,capture-dma = <&dma01>;
220 fsl,fifo-depth = <8>;
220 }; 221 };
221 222
222 ssi@16100 { 223 ssi@16100 {
@@ -225,6 +226,7 @@
225 reg = <0x16100 0x100>; 226 reg = <0x16100 0x100>;
226 interrupt-parent = <&mpic>; 227 interrupt-parent = <&mpic>;
227 interrupts = <63 2>; 228 interrupts = <63 2>;
229 fsl,fifo-depth = <8>;
228 }; 230 };
229 231
230 dma@21300 { 232 dma@21300 {
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index be2c11ca059..89583471389 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -19,6 +19,7 @@
19 compatible = "phytec,pcm030"; 19 compatible = "phytec,pcm030";
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
22 23
23 cpus { 24 cpus {
24 #address-cells = <1>; 25 #address-cells = <1>;
@@ -29,26 +30,26 @@
29 reg = <0>; 30 reg = <0>;
30 d-cache-line-size = <32>; 31 d-cache-line-size = <32>;
31 i-cache-line-size = <32>; 32 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; /* L1, 16K */ 33 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; /* L1, 16K */ 34 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; /* From Bootloader */ 35 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; /* From Bootloader */ 36 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; /* From Bootloader */ 37 clock-frequency = <0>; // from bootloader
37 }; 38 };
38 }; 39 };
39 40
40 memory { 41 memory {
41 device_type = "memory"; 42 device_type = "memory";
42 reg = <0x00000000 0x04000000>; /* 64MB */ 43 reg = <0x00000000 0x04000000>; // 64MB
43 }; 44 };
44 45
45 soc5200@f0000000 { 46 soc5200@f0000000 {
46 #address-cells = <1>; 47 #address-cells = <1>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr"; 49 compatible = "fsl,mpc5200b-immr";
49 ranges = <0x0 0xf0000000 0x0000c000>; 50 ranges = <0 0xf0000000 0x0000c000>;
50 bus-frequency = <0>; /* From bootloader */ 51 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; /* From bootloader */ 52 system-frequency = <0>; // from bootloader
52 53
53 cdm@200 { 54 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
@@ -56,87 +57,70 @@
56 }; 57 };
57 58
58 mpc5200_pic: interrupt-controller@500 { 59 mpc5200_pic: interrupt-controller@500 {
59 /* 5200 interrupts are encoded into two levels; */ 60 // 5200 interrupts are encoded into two levels;
60 interrupt-controller; 61 interrupt-controller;
61 #interrupt-cells = <3>; 62 #interrupt-cells = <3>;
62 device_type = "interrupt-controller";
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>; 64 reg = <0x500 0x80>;
65 }; 65 };
66 66
67 timer@600 { /* General Purpose Timer */ 67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 cell-index = <0>;
70 reg = <0x600 0x10>; 69 reg = <0x600 0x10>;
71 interrupts = <0x1 0x9 0x0>; 70 interrupts = <1 9 0>;
72 interrupt-parent = <&mpc5200_pic>;
73 fsl,has-wdt; 71 fsl,has-wdt;
74 }; 72 };
75 73
76 timer@610 { /* General Purpose Timer */ 74 timer@610 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 cell-index = <1>;
79 reg = <0x610 0x10>; 76 reg = <0x610 0x10>;
80 interrupts = <0x1 0xa 0x0>; 77 interrupts = <1 10 0>;
81 interrupt-parent = <&mpc5200_pic>;
82 }; 78 };
83 79
84 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */ 80 gpt2: timer@620 { // General Purpose Timer in GPIO mode
85 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 81 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
86 cell-index = <2>;
87 reg = <0x620 0x10>; 82 reg = <0x620 0x10>;
88 interrupts = <0x1 0xb 0x0>; 83 interrupts = <1 11 0>;
89 interrupt-parent = <&mpc5200_pic>;
90 gpio-controller; 84 gpio-controller;
91 #gpio-cells = <2>; 85 #gpio-cells = <2>;
92 }; 86 };
93 87
94 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */ 88 gpt3: timer@630 { // General Purpose Timer in GPIO mode
95 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 89 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
96 cell-index = <3>;
97 reg = <0x630 0x10>; 90 reg = <0x630 0x10>;
98 interrupts = <0x1 0xc 0x0>; 91 interrupts = <1 12 0>;
99 interrupt-parent = <&mpc5200_pic>;
100 gpio-controller; 92 gpio-controller;
101 #gpio-cells = <2>; 93 #gpio-cells = <2>;
102 }; 94 };
103 95
104 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */ 96 gpt4: timer@640 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 97 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106 cell-index = <4>;
107 reg = <0x640 0x10>; 98 reg = <0x640 0x10>;
108 interrupts = <0x1 0xd 0x0>; 99 interrupts = <1 13 0>;
109 interrupt-parent = <&mpc5200_pic>;
110 gpio-controller; 100 gpio-controller;
111 #gpio-cells = <2>; 101 #gpio-cells = <2>;
112 }; 102 };
113 103
114 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */ 104 gpt5: timer@650 { // General Purpose Timer in GPIO mode
115 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
116 cell-index = <5>;
117 reg = <0x650 0x10>; 106 reg = <0x650 0x10>;
118 interrupts = <0x1 0xe 0x0>; 107 interrupts = <1 14 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 gpio-controller; 108 gpio-controller;
121 #gpio-cells = <2>; 109 #gpio-cells = <2>;
122 }; 110 };
123 111
124 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */ 112 gpt6: timer@660 { // General Purpose Timer in GPIO mode
125 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 113 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
126 cell-index = <6>;
127 reg = <0x660 0x10>; 114 reg = <0x660 0x10>;
128 interrupts = <0x1 0xf 0x0>; 115 interrupts = <1 15 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 gpio-controller; 116 gpio-controller;
131 #gpio-cells = <2>; 117 #gpio-cells = <2>;
132 }; 118 };
133 119
134 gpt7: timer@670 { /* General Purpose Timer in GPIO mode */ 120 gpt7: timer@670 { // General Purpose Timer in GPIO mode
135 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 121 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
136 cell-index = <7>;
137 reg = <0x670 0x10>; 122 reg = <0x670 0x10>;
138 interrupts = <0x1 0x10 0x0>; 123 interrupts = <1 16 0>;
139 interrupt-parent = <&mpc5200_pic>;
140 gpio-controller; 124 gpio-controller;
141 #gpio-cells = <2>; 125 #gpio-cells = <2>;
142 }; 126 };
@@ -144,40 +128,33 @@
144 rtc@800 { // Real time clock 128 rtc@800 { // Real time clock
145 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
146 reg = <0x800 0x100>; 130 reg = <0x800 0x100>;
147 interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>; 131 interrupts = <1 5 0 1 6 0>;
148 interrupt-parent = <&mpc5200_pic>;
149 }; 132 };
150 133
151 can@900 { 134 can@900 {
152 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
153 cell-index = <0>; 136 interrupts = <2 17 0>;
154 interrupts = <0x2 0x11 0x0>;
155 interrupt-parent = <&mpc5200_pic>;
156 reg = <0x900 0x80>; 137 reg = <0x900 0x80>;
157 }; 138 };
158 139
159 can@980 { 140 can@980 {
160 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
161 cell-index = <1>; 142 interrupts = <2 18 0>;
162 interrupts = <0x2 0x12 0x0>;
163 interrupt-parent = <&mpc5200_pic>;
164 reg = <0x980 0x80>; 143 reg = <0x980 0x80>;
165 }; 144 };
166 145
167 gpio_simple: gpio@b00 { 146 gpio_simple: gpio@b00 {
168 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
169 reg = <0xb00 0x40>; 148 reg = <0xb00 0x40>;
170 interrupts = <0x1 0x7 0x0>; 149 interrupts = <1 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 gpio-controller; 150 gpio-controller;
173 #gpio-cells = <2>; 151 #gpio-cells = <2>;
174 }; 152 };
175 153
176 gpio_wkup: gpio-wkup@c00 { 154 gpio_wkup: gpio@c00 {
177 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
178 reg = <0xc00 0x40>; 156 reg = <0xc00 0x40>;
179 interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>; 157 interrupts = <1 8 0 0 3 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 gpio-controller; 158 gpio-controller;
182 #gpio-cells = <2>; 159 #gpio-cells = <2>;
183 }; 160 };
@@ -185,26 +162,22 @@
185 spi@f00 { 162 spi@f00 {
186 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
187 reg = <0xf00 0x20>; 164 reg = <0xf00 0x20>;
188 interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>; 165 interrupts = <2 13 0 2 14 0>;
189 interrupt-parent = <&mpc5200_pic>;
190 }; 166 };
191 167
192 usb@1000 { 168 usb@1000 {
193 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
194 reg = <0x1000 0xff>; 170 reg = <0x1000 0xff>;
195 interrupts = <0x2 0x6 0x0>; 171 interrupts = <2 6 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 172 };
198 173
199 dma-controller@1200 { 174 dma-controller@1200 {
200 device_type = "dma-controller";
201 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
202 reg = <0x1200 0x80>; 176 reg = <0x1200 0x80>;
203 interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0 177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
204 0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0 178 3 4 0 3 5 0 3 6 0 3 7 0
205 0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0 179 3 8 0 3 9 0 3 10 0 3 11 0
206 0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>; 180 3 12 0 3 13 0 3 14 0 3 15 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 181 };
209 182
210 xlb@1f00 { 183 xlb@1f00 {
@@ -213,24 +186,19 @@
213 }; 186 };
214 187
215 ac97@2000 { /* PSC1 in ac97 mode */ 188 ac97@2000 { /* PSC1 in ac97 mode */
216 device_type = "sound";
217 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 189 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
218 cell-index = <0>; 190 cell-index = <0>;
219 reg = <0x2000 0x100>; 191 reg = <0x2000 0x100>;
220 interrupts = <0x2 0x2 0x0>; 192 interrupts = <2 1 0>;
221 interrupt-parent = <&mpc5200_pic>;
222 }; 193 };
223 194
224 /* PSC2 port is used by CAN1/2 */ 195 /* PSC2 port is used by CAN1/2 */
225 196
226 serial@2400 { /* PSC3 in UART mode */ 197 serial@2400 { /* PSC3 in UART mode */
227 device_type = "serial";
228 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
229 port-number = <0>;
230 cell-index = <2>; 199 cell-index = <2>;
231 reg = <0x2400 0x100>; 200 reg = <0x2400 0x100>;
232 interrupts = <0x2 0x3 0x0>; 201 interrupts = <2 3 0>;
233 interrupt-parent = <&mpc5200_pic>;
234 }; 202 };
235 203
236 /* PSC4 is ??? */ 204 /* PSC4 is ??? */
@@ -238,55 +206,44 @@
238 /* PSC5 is ??? */ 206 /* PSC5 is ??? */
239 207
240 serial@2c00 { /* PSC6 in UART mode */ 208 serial@2c00 { /* PSC6 in UART mode */
241 device_type = "serial";
242 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
243 port-number = <1>;
244 cell-index = <5>; 210 cell-index = <5>;
245 reg = <0x2c00 0x100>; 211 reg = <0x2c00 0x100>;
246 interrupts = <0x2 0x4 0x0>; 212 interrupts = <2 4 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 }; 213 };
249 214
250 ethernet@3000 { 215 ethernet@3000 {
251 device_type = "network";
252 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
253 reg = <0x3000 0x400>; 217 reg = <0x3000 0x400>;
254 local-mac-address = [00 00 00 00 00 00]; 218 local-mac-address = [ 00 00 00 00 00 00 ];
255 interrupts = <0x2 0x5 0x0>; 219 interrupts = <2 5 0>;
256 interrupt-parent = <&mpc5200_pic>;
257 phy-handle = <&phy0>; 220 phy-handle = <&phy0>;
258 }; 221 };
259 222
260 mdio@3000 { 223 mdio@3000 {
261 #address-cells = <1>; 224 #address-cells = <1>;
262 #size-cells = <0>; 225 #size-cells = <0>;
263 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
264 reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */ 227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
265 interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */ 228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
266 interrupt-parent = <&mpc5200_pic>; 229
267 230 phy0: ethernet-phy@0 {
268 phy0:ethernet-phy@0 { 231 reg = <0>;
269 device_type = "ethernet-phy";
270 reg = <0x0>;
271 }; 232 };
272 }; 233 };
273 234
274 ata@3a00 { 235 ata@3a00 {
275 device_type = "ata";
276 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
277 reg = <0x3a00 0x100>; 237 reg = <0x3a00 0x100>;
278 interrupts = <0x2 0x7 0x0>; 238 interrupts = <2 7 0>;
279 interrupt-parent = <&mpc5200_pic>;
280 }; 239 };
281 240
282 i2c@3d00 { 241 i2c@3d00 {
283 #address-cells = <1>; 242 #address-cells = <1>;
284 #size-cells = <0>; 243 #size-cells = <0>;
285 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
286 cell-index = <0>;
287 reg = <0x3d00 0x40>; 245 reg = <0x3d00 0x40>;
288 interrupts = <0x2 0xf 0x0>; 246 interrupts = <2 15 0>;
289 interrupt-parent = <&mpc5200_pic>;
290 fsl5200-clocking; 247 fsl5200-clocking;
291 }; 248 };
292 249
@@ -294,10 +251,8 @@
294 #address-cells = <1>; 251 #address-cells = <1>;
295 #size-cells = <0>; 252 #size-cells = <0>;
296 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
297 cell-index = <1>;
298 reg = <0x3d40 0x40>; 254 reg = <0x3d40 0x40>;
299 interrupts = <0x2 0x10 0x0>; 255 interrupts = <2 16 0>;
300 interrupt-parent = <&mpc5200_pic>;
301 fsl5200-clocking; 256 fsl5200-clocking;
302 rtc@51 { 257 rtc@51 {
303 compatible = "nxp,pcf8563"; 258 compatible = "nxp,pcf8563";
@@ -307,7 +262,7 @@
307 }; 262 };
308 263
309 sram@8000 { 264 sram@8000 {
310 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 265 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
311 reg = <0x8000 0x4000>; 266 reg = <0x8000 0x4000>;
312 }; 267 };
313 268
@@ -340,22 +295,21 @@
340 device_type = "pci"; 295 device_type = "pci";
341 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 296 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
342 reg = <0xf0000d00 0x100>; 297 reg = <0xf0000d00 0x100>;
343 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 298 interrupt-map-mask = <0xf800 0 0 7>;
344 interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */ 299 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
345 0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3 300 0xc000 0 0 2 &mpc5200_pic 1 1 3
346 0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3 301 0xc000 0 0 3 &mpc5200_pic 1 2 3
347 0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3 302 0xc000 0 0 4 &mpc5200_pic 1 3 3
348 303
349 0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */ 304 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
350 0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3 305 0xc800 0 0 2 &mpc5200_pic 1 2 3
351 0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3 306 0xc800 0 0 3 &mpc5200_pic 1 3 3
352 0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>; 307 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
353 clock-frequency = <0>; // From boot loader 308 clock-frequency = <0>; // From boot loader
354 interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>; 309 interrupts = <2 8 0 2 9 0 2 10 0>;
355 interrupt-parent = <&mpc5200_pic>;
356 bus-range = <0 0>; 310 bus-range = <0 0>;
357 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 311 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
358 0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 312 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
359 0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>; 313 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
360 }; 314 };
361}; 315};
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
new file mode 100644
index 00000000000..03004267839
--- /dev/null
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -0,0 +1,392 @@
1/*
2 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
3 *
4 * Copyright (C) 2006-2009 Pengutronix
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Juergen Beisert <j.beisert@pengutronix.de>
7 * Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/dts-v1/;
16
17/ {
18 model = "phytec,pcm032";
19 compatible = "phytec,pcm032";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5200@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <0x4000>; // L1, 16K
34 i-cache-size = <0x4000>; // L1, 16K
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x08000000>; // 128MB
44 };
45
46 soc5200@f0000000 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "fsl,mpc5200b-immr";
50 ranges = <0 0xf0000000 0x0000c000>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt;
72 };
73
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 gpt2: timer@620 { // General Purpose Timer in GPIO mode
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 gpio-controller;
85 #gpio-cells = <2>;
86 };
87
88 gpt3: timer@630 { // General Purpose Timer in GPIO mode
89 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
90 reg = <0x630 0x10>;
91 interrupts = <1 12 0>;
92 gpio-controller;
93 #gpio-cells = <2>;
94 };
95
96 gpt4: timer@640 { // General Purpose Timer in GPIO mode
97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
98 reg = <0x640 0x10>;
99 interrupts = <1 13 0>;
100 gpio-controller;
101 #gpio-cells = <2>;
102 };
103
104 gpt5: timer@650 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
106 reg = <0x650 0x10>;
107 interrupts = <1 14 0>;
108 gpio-controller;
109 #gpio-cells = <2>;
110 };
111
112 gpt6: timer@660 { // General Purpose Timer in GPIO mode
113 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
114 reg = <0x660 0x10>;
115 interrupts = <1 15 0>;
116 gpio-controller;
117 #gpio-cells = <2>;
118 };
119
120 gpt7: timer@670 { // General Purpose Timer in GPIO mode
121 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
122 reg = <0x670 0x10>;
123 interrupts = <1 16 0>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 };
127
128 rtc@800 { // Real time clock
129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
130 reg = <0x800 0x100>;
131 interrupts = <1 5 0 1 6 0>;
132 };
133
134 can@900 {
135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
136 interrupts = <2 17 0>;
137 reg = <0x900 0x80>;
138 };
139
140 can@980 {
141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
142 interrupts = <2 18 0>;
143 reg = <0x980 0x80>;
144 };
145
146 gpio_simple: gpio@b00 {
147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
148 reg = <0xb00 0x40>;
149 interrupts = <1 7 0>;
150 gpio-controller;
151 #gpio-cells = <2>;
152 };
153
154 gpio_wkup: gpio@c00 {
155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
156 reg = <0xc00 0x40>;
157 interrupts = <1 8 0 0 3 0>;
158 gpio-controller;
159 #gpio-cells = <2>;
160 };
161
162 spi@f00 {
163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
164 reg = <0xf00 0x20>;
165 interrupts = <2 13 0 2 14 0>;
166 };
167
168 usb@1000 {
169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
170 reg = <0x1000 0xff>;
171 interrupts = <2 6 0>;
172 };
173
174 dma-controller@1200 {
175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
176 reg = <0x1200 0x80>;
177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
178 3 4 0 3 5 0 3 6 0 3 7 0
179 3 8 0 3 9 0 3 10 0 3 11 0
180 3 12 0 3 13 0 3 14 0 3 15 0>;
181 };
182
183 xlb@1f00 {
184 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
185 reg = <0x1f00 0x100>;
186 };
187
188 ac97@2000 { /* PSC1 is ac97 */
189 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
190 cell-index = <0>;
191 reg = <0x2000 0x100>;
192 interrupts = <2 1 0>;
193 };
194
195 /* PSC2 port is used by CAN1/2 */
196
197 serial@2400 { /* PSC3 in UART mode */
198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
199 cell-index = <2>;
200 reg = <0x2400 0x100>;
201 interrupts = <2 3 0>;
202 };
203
204 /* PSC4 is ??? */
205
206 /* PSC5 is ??? */
207
208 serial@2c00 { /* PSC6 in UART mode */
209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
210 cell-index = <5>;
211 reg = <0x2c00 0x100>;
212 interrupts = <2 4 0>;
213 };
214
215 ethernet@3000 {
216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
217 reg = <0x3000 0x400>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 interrupts = <2 5 0>;
220 phy-handle = <&phy0>;
221 };
222
223 mdio@3000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
229
230 phy0: ethernet-phy@0 {
231 reg = <0>;
232 };
233 };
234
235 ata@3a00 {
236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
237 reg = <0x3a00 0x100>;
238 interrupts = <2 7 0>;
239 };
240
241 i2c@3d00 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d00 0x40>;
246 interrupts = <2 15 0>;
247 fsl5200-clocking;
248 };
249
250 i2c@3d40 {
251 #address-cells = <1>;
252 #size-cells = <0>;
253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
254 reg = <0x3d40 0x40>;
255 interrupts = <2 16 0>;
256 fsl5200-clocking;
257 rtc@51 {
258 compatible = "nxp,pcf8563";
259 reg = <0x51>;
260 };
261 eeprom@52 {
262 compatible = "at24,24c32";
263 reg = <0x52>;
264 };
265 };
266
267 sram@8000 {
268 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
269 reg = <0x8000 0x4000>;
270 };
271 };
272
273 pci@f0000d00 {
274 #interrupt-cells = <1>;
275 #size-cells = <2>;
276 #address-cells = <3>;
277 device_type = "pci";
278 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
279 reg = <0xf0000d00 0x100>;
280 interrupt-map-mask = <0xf800 0 0 7>;
281 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
282 0xc000 0 0 2 &mpc5200_pic 1 1 3
283 0xc000 0 0 3 &mpc5200_pic 1 2 3
284 0xc000 0 0 4 &mpc5200_pic 1 3 3
285
286 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
287 0xc800 0 0 2 &mpc5200_pic 1 2 3
288 0xc800 0 0 3 &mpc5200_pic 1 3 3
289 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
290 clock-frequency = <0>; // From boot loader
291 interrupts = <2 8 0 2 9 0 2 10 0>;
292 bus-range = <0 0>;
293 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
294 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
295 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
296 };
297
298 localbus {
299 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
300
301 #address-cells = <2>;
302 #size-cells = <1>;
303
304 ranges = <0 0 0xfe000000 0x02000000
305 1 0 0xfc000000 0x02000000
306 2 0 0xfbe00000 0x00200000
307 3 0 0xf9e00000 0x02000000
308 4 0 0xf7e00000 0x02000000
309 5 0 0xe6000000 0x02000000
310 6 0 0xe8000000 0x02000000
311 7 0 0xea000000 0x02000000>;
312
313 flash@0,0 {
314 compatible = "cfi-flash";
315 reg = <0 0 0x02000000>;
316 bank-width = <4>;
317 #size-cells = <1>;
318 #address-cells = <1>;
319
320 partition@0 {
321 label = "ubootl";
322 reg = <0x00000000 0x00040000>;
323 };
324 partition@40000 {
325 label = "kernel";
326 reg = <0x00040000 0x001c0000>;
327 };
328 partition@200000 {
329 label = "jffs2";
330 reg = <0x00200000 0x01d00000>;
331 };
332 partition@1f00000 {
333 label = "uboot";
334 reg = <0x01f00000 0x00040000>;
335 };
336 partition@1f40000 {
337 label = "env";
338 reg = <0x01f40000 0x00040000>;
339 };
340 partition@1f80000 {
341 label = "oftree";
342 reg = <0x01f80000 0x00040000>;
343 };
344 partition@1fc0000 {
345 label = "space";
346 reg = <0x01fc0000 0x00040000>;
347 };
348 };
349
350 sram@2,0 {
351 compatible = "mtd-ram";
352 reg = <2 0 0x00200000>;
353 bank-width = <2>;
354 };
355
356 /*
357 * example snippets for FPGA
358 *
359 * fpga@3,0 {
360 * compatible = "fpga_driver";
361 * reg = <3 0 0x02000000>;
362 * bank-width = <4>;
363 * };
364 *
365 * fpga@4,0 {
366 * compatible = "fpga_driver";
367 * reg = <4 0 0x02000000>;
368 * bank-width = <4>;
369 * };
370 */
371
372 /*
373 * example snippets for free chipselects
374 *
375 * device@5,0 {
376 * compatible = "custom_driver";
377 * reg = <5 0 0x02000000>;
378 * };
379 *
380 * device@6,0 {
381 * compatible = "custom_driver";
382 * reg = <6 0 0x02000000>;
383 * };
384 *
385 * device@7,0 {
386 * compatible = "custom_driver";
387 * reg = <7 0 0x02000000>;
388 * };
389 */
390 };
391};
392
diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
new file mode 100644
index 00000000000..ad402c48874
--- /dev/null
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -0,0 +1,244 @@
1/*
2 * Device Tree Source for AMCC Redwood(460SX)
3 *
4 * Copyright 2008 AMCC <tmarri@amcc.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,redwood";
17 compatible = "amcc,redwood";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 serial0 = &UART0;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 model = "PowerPC,460SX";
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <32>;
36 d-cache-line-size = <32>;
37 i-cache-size = <32768>;
38 d-cache-size = <32768>;
39 dcr-controller;
40 dcr-access-method = "native";
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
47 };
48
49 UIC0: interrupt-controller0 {
50 compatible = "ibm,uic-460sx","ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
58
59 UIC1: interrupt-controller1 {
60 compatible = "ibm,uic-460sx","ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
63 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
67 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
68 interrupt-parent = <&UIC0>;
69 };
70
71 UIC2: interrupt-controller2 {
72 compatible = "ibm,uic-460sx","ibm,uic";
73 interrupt-controller;
74 cell-index = <2>;
75 dcr-reg = <0x0e0 0x009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
78 #interrupt-cells = <2>;
79 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
80 interrupt-parent = <&UIC0>;
81 };
82
83 UIC3: interrupt-controller3 {
84 compatible = "ibm,uic-460sx","ibm,uic";
85 interrupt-controller;
86 cell-index = <3>;
87 dcr-reg = <0x0f0 0x009>;
88 #address-cells = <0>;
89 #size-cells = <0>;
90 #interrupt-cells = <2>;
91 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
92 interrupt-parent = <&UIC0>;
93 };
94
95 SDR0: sdr {
96 compatible = "ibm,sdr-460sx";
97 dcr-reg = <0x00e 0x002>;
98 };
99
100 CPR0: cpr {
101 compatible = "ibm,cpr-460sx";
102 dcr-reg = <0x00c 0x002>;
103 };
104
105 plb {
106 compatible = "ibm,plb-460sx", "ibm,plb4";
107 #address-cells = <2>;
108 #size-cells = <1>;
109 ranges;
110 clock-frequency = <0>; /* Filled in by U-Boot */
111
112 SDRAM0: sdram {
113 compatible = "ibm,sdram-460sx", "ibm,sdram-405gp";
114 dcr-reg = <0x010 0x002>;
115 };
116
117 MAL0: mcmal {
118 compatible = "ibm,mcmal-460sx", "ibm,mcmal2";
119 dcr-reg = <0x180 0x62>;
120 num-tx-chans = <4>;
121 num-rx-chans = <32>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 interrupt-parent = <&UIC1>;
125 interrupts = < /*TXEOB*/ 0x6 0x4
126 /*RXEOB*/ 0x7 0x4
127 /*SERR*/ 0x1 0x4
128 /*TXDE*/ 0x2 0x4
129 /*RXDE*/ 0x3 0x4
130 /*COAL TX0*/ 0x18 0x2
131 /*COAL TX1*/ 0x19 0x2
132 /*COAL TX2*/ 0x1a 0x2
133 /*COAL TX3*/ 0x1b 0x2
134 /*COAL RX0*/ 0x1c 0x2
135 /*COAL RX1*/ 0x1d 0x2
136 /*COAL RX2*/ 0x1e 0x2
137 /*COAL RX3*/ 0x1f 0x2>;
138 };
139
140 POB0: opb {
141 compatible = "ibm,opb-460sx", "ibm,opb";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
145 clock-frequency = <0>; /* Filled in by U-Boot */
146
147 EBC0: ebc {
148 compatible = "ibm,ebc-460sx", "ibm,ebc";
149 dcr-reg = <0x012 0x002>;
150 #address-cells = <2>;
151 #size-cells = <1>;
152 clock-frequency = <0>; /* Filled in by U-Boot */
153 /* ranges property is supplied by U-Boot */
154 interrupts = <0x6 0x4>;
155 interrupt-parent = <&UIC1>;
156
157 nor_flash@0,0 {
158 compatible = "amd,s29gl512n", "cfi-flash";
159 bank-width = <2>;
160 reg = <0x0000000 0x00000000 0x04000000>;
161 #address-cells = <1>;
162 #size-cells = <1>;
163 partition@0 {
164 label = "kernel";
165 reg = <0x00000000 0x001e0000>;
166 };
167 partition@1e0000 {
168 label = "dtb";
169 reg = <0x001e0000 0x00020000>;
170 };
171 partition@200000 {
172 label = "ramdisk";
173 reg = <0x00200000 0x01400000>;
174 };
175 partition@1600000 {
176 label = "jffs2";
177 reg = <0x01600000 0x00400000>;
178 };
179 partition@1a00000 {
180 label = "user";
181 reg = <0x01a00000 0x02560000>;
182 };
183 partition@3f60000 {
184 label = "env";
185 reg = <0x03f60000 0x00040000>;
186 };
187 partition@3fa0000 {
188 label = "u-boot";
189 reg = <0x03fa0000 0x00060000>;
190 };
191 };
192 };
193
194 UART0: serial@ef600200 {
195 device_type = "serial";
196 compatible = "ns16550";
197 reg = <0xef600200 0x00000008>;
198 virtual-reg = <0xef600200>;
199 clock-frequency = <0>; /* Filled in by U-Boot */
200 current-speed = <0>; /* Filled in by U-Boot */
201 interrupt-parent = <&UIC0>;
202 interrupts = <0x0 0x4>;
203 };
204
205 RGMII0: emac-rgmii@ef600900 {
206 compatible = "ibm,rgmii-460sx", "ibm,rgmii";
207 reg = <0xef600900 0x00000008>;
208 };
209
210 EMAC0: ethernet@ef600a00 {
211 device_type = "network";
212 compatible = "ibm,emac-460sx", "ibm,emac4";
213 interrupt-parent = <&EMAC0>;
214 interrupts = <0x0 0x1>;
215 #interrupt-cells = <1>;
216 #address-cells = <0>;
217 #size-cells = <0>;
218 interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
219 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
220 reg = <0xef600a00 0x00000070>;
221 local-mac-address = [000000000000]; /* Filled in by U-Boot */
222 mal-device = <&MAL0>;
223 mal-tx-channel = <0>;
224 mal-rx-channel = <0>;
225 cell-index = <0>;
226 max-frame-size = <9000>;
227 rx-fifo-size = <4096>;
228 tx-fifo-size = <2048>;
229 phy-mode = "rgmii";
230 phy-map = <0x00000000>;
231 rgmii-device = <&RGMII0>;
232 rgmii-channel = <0>;
233 has-inverted-stacr-oc;
234 has-new-stacr-staopc;
235 };
236
237 };
238
239 };
240 chosen {
241 linux,stdout-path = "/plb/opb/serial@ef600200";
242 };
243
244};
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index 906302e26a6..c9590b58b7b 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -17,6 +17,7 @@
17 compatible = "tqc,tqm5200"; 17 compatible = "tqc,tqm5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,36 +67,33 @@
66 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
73 can@900 { 73 can@900 {
74 compatible = "fsl,mpc5200-mscan"; 74 compatible = "fsl,mpc5200-mscan";
75 interrupts = <2 17 0>; 75 interrupts = <2 17 0>;
76 interrupt-parent = <&mpc5200_pic>;
77 reg = <0x900 0x80>; 76 reg = <0x900 0x80>;
78 }; 77 };
79 78
80 can@980 { 79 can@980 {
81 compatible = "fsl,mpc5200-mscan"; 80 compatible = "fsl,mpc5200-mscan";
82 interrupts = <2 18 0>; 81 interrupts = <2 18 0>;
83 interrupt-parent = <&mpc5200_pic>;
84 reg = <0x980 0x80>; 82 reg = <0x980 0x80>;
85 }; 83 };
86 84
87 gpio@b00 { 85 gpio_simple: gpio@b00 {
88 compatible = "fsl,mpc5200-gpio"; 86 compatible = "fsl,mpc5200-gpio";
89 reg = <0xb00 0x40>; 87 reg = <0xb00 0x40>;
90 interrupts = <1 7 0>; 88 interrupts = <1 7 0>;
91 interrupt-parent = <&mpc5200_pic>; 89 gpio-controller;
90 #gpio-cells = <2>;
92 }; 91 };
93 92
94 usb@1000 { 93 usb@1000 {
95 compatible = "fsl,mpc5200-ohci","ohci-be"; 94 compatible = "fsl,mpc5200-ohci","ohci-be";
96 reg = <0x1000 0xff>; 95 reg = <0x1000 0xff>;
97 interrupts = <2 6 0>; 96 interrupts = <2 6 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 97 };
100 98
101 dma-controller@1200 { 99 dma-controller@1200 {
@@ -105,7 +103,6 @@
105 3 4 0 3 5 0 3 6 0 3 7 0 103 3 4 0 3 5 0 3 6 0 3 7 0
106 3 8 0 3 9 0 3 10 0 3 11 0 104 3 8 0 3 9 0 3 10 0 3 11 0
107 3 12 0 3 13 0 3 14 0 3 15 0>; 105 3 12 0 3 13 0 3 14 0 3 15 0>;
108 interrupt-parent = <&mpc5200_pic>;
109 }; 106 };
110 107
111 xlb@1f00 { 108 xlb@1f00 {
@@ -114,39 +111,28 @@
114 }; 111 };
115 112
116 serial@2000 { // PSC1 113 serial@2000 { // PSC1
117 device_type = "serial";
118 compatible = "fsl,mpc5200-psc-uart"; 114 compatible = "fsl,mpc5200-psc-uart";
119 port-number = <0>; // Logical port assignment
120 reg = <0x2000 0x100>; 115 reg = <0x2000 0x100>;
121 interrupts = <2 1 0>; 116 interrupts = <2 1 0>;
122 interrupt-parent = <&mpc5200_pic>;
123 }; 117 };
124 118
125 serial@2200 { // PSC2 119 serial@2200 { // PSC2
126 device_type = "serial";
127 compatible = "fsl,mpc5200-psc-uart"; 120 compatible = "fsl,mpc5200-psc-uart";
128 port-number = <1>; // Logical port assignment
129 reg = <0x2200 0x100>; 121 reg = <0x2200 0x100>;
130 interrupts = <2 2 0>; 122 interrupts = <2 2 0>;
131 interrupt-parent = <&mpc5200_pic>;
132 }; 123 };
133 124
134 serial@2400 { // PSC3 125 serial@2400 { // PSC3
135 device_type = "serial";
136 compatible = "fsl,mpc5200-psc-uart"; 126 compatible = "fsl,mpc5200-psc-uart";
137 port-number = <2>; // Logical port assignment
138 reg = <0x2400 0x100>; 127 reg = <0x2400 0x100>;
139 interrupts = <2 3 0>; 128 interrupts = <2 3 0>;
140 interrupt-parent = <&mpc5200_pic>;
141 }; 129 };
142 130
143 ethernet@3000 { 131 ethernet@3000 {
144 device_type = "network";
145 compatible = "fsl,mpc5200-fec"; 132 compatible = "fsl,mpc5200-fec";
146 reg = <0x3000 0x400>; 133 reg = <0x3000 0x400>;
147 local-mac-address = [ 00 00 00 00 00 00 ]; 134 local-mac-address = [ 00 00 00 00 00 00 ];
148 interrupts = <2 5 0>; 135 interrupts = <2 5 0>;
149 interrupt-parent = <&mpc5200_pic>;
150 phy-handle = <&phy0>; 136 phy-handle = <&phy0>;
151 }; 137 };
152 138
@@ -156,10 +142,8 @@
156 compatible = "fsl,mpc5200-mdio"; 142 compatible = "fsl,mpc5200-mdio";
157 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 143 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
158 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 144 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
159 interrupt-parent = <&mpc5200_pic>;
160 145
161 phy0: ethernet-phy@0 { 146 phy0: ethernet-phy@0 {
162 device_type = "ethernet-phy";
163 reg = <0>; 147 reg = <0>;
164 }; 148 };
165 }; 149 };
@@ -168,7 +152,6 @@
168 compatible = "fsl,mpc5200-ata"; 152 compatible = "fsl,mpc5200-ata";
169 reg = <0x3a00 0x100>; 153 reg = <0x3a00 0x100>;
170 interrupts = <2 7 0>; 154 interrupts = <2 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 }; 155 };
173 156
174 i2c@3d40 { 157 i2c@3d40 {
@@ -177,7 +160,6 @@
177 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 160 compatible = "fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>; 161 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>; 162 interrupts = <2 16 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 fsl5200-clocking; 163 fsl5200-clocking;
182 164
183 rtc@68 { 165 rtc@68 {
@@ -192,9 +174,8 @@
192 }; 174 };
193 }; 175 };
194 176
195 lpb { 177 localbus {
196 model = "fsl,lpb"; 178 compatible = "fsl,mpc5200-lpb","simple-bus";
197 compatible = "fsl,lpb";
198 #address-cells = <2>; 179 #address-cells = <2>;
199 #size-cells = <1>; 180 #size-cells = <1>;
200 ranges = <0 0 0xfc000000 0x02000000>; 181 ranges = <0 0 0xfc000000 0x02000000>;
@@ -223,7 +204,6 @@
223 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 204 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
224 clock-frequency = <0>; // From boot loader 205 clock-frequency = <0>; // From boot loader
225 interrupts = <2 8 0 2 9 0 2 10 0>; 206 interrupts = <2 8 0 2 9 0 2 10 0>;
226 interrupt-parent = <&mpc5200_pic>;
227 bus-range = <0 0>; 207 bus-range = <0 0>;
228 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 208 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
229 0x02000000 0 0x90000000 0x90000000 0 0x10000000 209 0x02000000 0 0x90000000 0x90000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index a693f01c21a..39e55ab82b8 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -84,6 +84,11 @@
84 interrupt-parent = <&mpic>; 84 interrupt-parent = <&mpic>;
85 dfsrr; 85 dfsrr;
86 86
87 dtt@50 {
88 compatible = "national,lm75";
89 reg = <0x50>;
90 };
91
87 rtc@68 { 92 rtc@68 {
88 compatible = "dallas,ds1337"; 93 compatible = "dallas,ds1337";
89 reg = <0x68>; 94 reg = <0x68>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index 9e3f5f0dde2..58ae8bc5881 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -83,6 +83,11 @@
83 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
84 dfsrr; 84 dfsrr;
85 85
86 dtt@50 {
87 compatible = "national,lm75";
88 reg = <0x50>;
89 };
90
86 rtc@68 { 91 rtc@68 {
87 compatible = "dallas,ds1337"; 92 compatible = "dallas,ds1337";
88 reg = <0x68>; 93 reg = <0x68>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 15086eb65c5..bff380a25aa 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -85,6 +85,11 @@
85 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
86 dfsrr; 86 dfsrr;
87 87
88 dtt@50 {
89 compatible = "national,lm75";
90 reg = <0x50>;
91 };
92
88 rtc@68 { 93 rtc@68 {
89 compatible = "dallas,ds1337"; 94 compatible = "dallas,ds1337";
90 reg = <0x68>; 95 reg = <0x68>;
@@ -365,14 +370,14 @@
365 can0@2,0 { 370 can0@2,0 {
366 compatible = "intel,82527"; // Bosch CC770 371 compatible = "intel,82527"; // Bosch CC770
367 reg = <2 0x0 0x100>; 372 reg = <2 0x0 0x100>;
368 interrupts = <4 0>; 373 interrupts = <4 1>;
369 interrupt-parent = <&mpic>; 374 interrupt-parent = <&mpic>;
370 }; 375 };
371 376
372 can1@2,100 { 377 can1@2,100 {
373 compatible = "intel,82527"; // Bosch CC770 378 compatible = "intel,82527"; // Bosch CC770
374 reg = <2 0x100 0x100>; 379 reg = <2 0x100 0x100>;
375 interrupts = <4 0>; 380 interrupts = <4 1>;
376 interrupt-parent = <&mpic>; 381 interrupt-parent = <&mpic>;
377 }; 382 };
378 383
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index b7b65f5e79b..112ac90f2ea 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -85,6 +85,11 @@
85 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
86 dfsrr; 86 dfsrr;
87 87
88 dtt@50 {
89 compatible = "national,lm75";
90 reg = <0x50>;
91 };
92
88 rtc@68 { 93 rtc@68 {
89 compatible = "dallas,ds1337"; 94 compatible = "dallas,ds1337";
90 reg = <0x68>; 95 reg = <0x68>;
@@ -365,14 +370,14 @@
365 can0@2,0 { 370 can0@2,0 {
366 compatible = "intel,82527"; // Bosch CC770 371 compatible = "intel,82527"; // Bosch CC770
367 reg = <2 0x0 0x100>; 372 reg = <2 0x0 0x100>;
368 interrupts = <4 0>; 373 interrupts = <4 1>;
369 interrupt-parent = <&mpic>; 374 interrupt-parent = <&mpic>;
370 }; 375 };
371 376
372 can1@2,100 { 377 can1@2,100 {
373 compatible = "intel,82527"; // Bosch CC770 378 compatible = "intel,82527"; // Bosch CC770
374 reg = <2 0x100 0x100>; 379 reg = <2 0x100 0x100>;
375 interrupts = <4 0>; 380 interrupts = <4 1>;
376 interrupt-parent = <&mpic>; 381 interrupt-parent = <&mpic>;
377 }; 382 };
378 383
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index cf92b4e7945..4b7da890c03 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -83,6 +83,11 @@
83 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
84 dfsrr; 84 dfsrr;
85 85
86 dtt@50 {
87 compatible = "national,lm75";
88 reg = <0x50>;
89 };
90
86 rtc@68 { 91 rtc@68 {
87 compatible = "dallas,ds1337"; 92 compatible = "dallas,ds1337";
88 reg = <0x68>; 93 reg = <0x68>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 9e1ab2d2f66..3fa552f31ed 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -85,6 +85,11 @@
85 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
86 dfsrr; 86 dfsrr;
87 87
88 dtt@50 {
89 compatible = "national,lm75";
90 reg = <0x50>;
91 };
92
88 rtc@68 { 93 rtc@68 {
89 compatible = "dallas,ds1337"; 94 compatible = "dallas,ds1337";
90 reg = <0x68>; 95 reg = <0x68>;
@@ -335,14 +340,14 @@
335 can0@2,0 { 340 can0@2,0 {
336 compatible = "intel,82527"; // Bosch CC770 341 compatible = "intel,82527"; // Bosch CC770
337 reg = <2 0x0 0x100>; 342 reg = <2 0x0 0x100>;
338 interrupts = <4 0>; 343 interrupts = <4 1>;
339 interrupt-parent = <&mpic>; 344 interrupt-parent = <&mpic>;
340 }; 345 };
341 346
342 can1@2,100 { 347 can1@2,100 {
343 compatible = "intel,82527"; // Bosch CC770 348 compatible = "intel,82527"; // Bosch CC770
344 reg = <2 0x100 0x100>; 349 reg = <2 0x100 0x100>;
345 interrupts = <4 0>; 350 interrupts = <4 1>;
346 interrupt-parent = <&mpic>; 351 interrupt-parent = <&mpic>;
347 }; 352 };
348 }; 353 };
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
index dc8e78e2dce..52d8c1ad26a 100644
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ b/arch/powerpc/boot/dts/virtex440-ml507.dts
@@ -7,6 +7,15 @@
7 * This file is licensed under the terms of the GNU General Public License 7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any 8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 *
11 * ---
12 *
13 * Device Tree Generator version: 1.1
14 *
15 * CAUTION: This file is automatically generated by libgen.
16 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
17 *
18 * XPS project directory: ml507_ppc440_emb_ref
10 */ 19 */
11 20
12/dts-v1/; 21/dts-v1/;
@@ -22,8 +31,8 @@
22 reg = < 0 0x10000000 >; 31 reg = < 0 0x10000000 >;
23 } ; 32 } ;
24 chosen { 33 chosen {
25 bootargs = "console=ttyS0 ip=on root=/dev/ram"; 34 bootargs = "console=ttyS0 root=/dev/ram";
26 linux,stdout-path = "/plb@0/serial@83e00000"; 35 linux,stdout-path = &RS232_Uart_1;
27 } ; 36 } ;
28 cpus { 37 cpus {
29 #address-cells = <1>; 38 #address-cells = <1>;
@@ -136,19 +145,19 @@
136 compatible = "xlnx,ll-dma-1.00.a"; 145 compatible = "xlnx,ll-dma-1.00.a";
137 dcr-reg = < 0x80 0x11 >; 146 dcr-reg = < 0x80 0x11 >;
138 interrupt-parent = <&xps_intc_0>; 147 interrupt-parent = <&xps_intc_0>;
139 interrupts = < 9 2 0xa 2 >; 148 interrupts = < 10 2 11 2 >;
140 } ; 149 } ;
141 } ; 150 } ;
142 } ; 151 } ;
143 plb_v46_0: plb@0 { 152 plb_v46_0: plb@0 {
144 #address-cells = <1>; 153 #address-cells = <1>;
145 #size-cells = <1>; 154 #size-cells = <1>;
146 compatible = "xlnx,plb-v46-1.02.a", "simple-bus"; 155 compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
147 ranges ; 156 ranges ;
148 DIP_Switches_8Bit: gpio@81460000 { 157 DIP_Switches_8Bit: gpio@81460000 {
149 compatible = "xlnx,xps-gpio-1.00.a"; 158 compatible = "xlnx,xps-gpio-1.00.a";
150 interrupt-parent = <&xps_intc_0>; 159 interrupt-parent = <&xps_intc_0>;
151 interrupts = < 6 2 >; 160 interrupts = < 7 2 >;
152 reg = < 0x81460000 0x10000 >; 161 reg = < 0x81460000 0x10000 >;
153 xlnx,all-inputs = <1>; 162 xlnx,all-inputs = <1>;
154 xlnx,all-inputs-2 = <0>; 163 xlnx,all-inputs-2 = <0>;
@@ -163,6 +172,86 @@
163 xlnx,tri-default = <0xffffffff>; 172 xlnx,tri-default = <0xffffffff>;
164 xlnx,tri-default-2 = <0xffffffff>; 173 xlnx,tri-default-2 = <0xffffffff>;
165 } ; 174 } ;
175 FLASH: flash@fc000000 {
176 bank-width = <2>;
177 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
178 reg = < 0xfc000000 0x2000000 >;
179 xlnx,family = "virtex5";
180 xlnx,include-datawidth-matching-0 = <0x1>;
181 xlnx,include-datawidth-matching-1 = <0x0>;
182 xlnx,include-datawidth-matching-2 = <0x0>;
183 xlnx,include-datawidth-matching-3 = <0x0>;
184 xlnx,include-negedge-ioregs = <0x0>;
185 xlnx,include-plb-ipif = <0x1>;
186 xlnx,include-wrbuf = <0x1>;
187 xlnx,max-mem-width = <0x10>;
188 xlnx,mch-native-dwidth = <0x20>;
189 xlnx,mch-plb-clk-period-ps = <0x2710>;
190 xlnx,mch-splb-awidth = <0x20>;
191 xlnx,mch0-accessbuf-depth = <0x10>;
192 xlnx,mch0-protocol = <0x0>;
193 xlnx,mch0-rddatabuf-depth = <0x10>;
194 xlnx,mch1-accessbuf-depth = <0x10>;
195 xlnx,mch1-protocol = <0x0>;
196 xlnx,mch1-rddatabuf-depth = <0x10>;
197 xlnx,mch2-accessbuf-depth = <0x10>;
198 xlnx,mch2-protocol = <0x0>;
199 xlnx,mch2-rddatabuf-depth = <0x10>;
200 xlnx,mch3-accessbuf-depth = <0x10>;
201 xlnx,mch3-protocol = <0x0>;
202 xlnx,mch3-rddatabuf-depth = <0x10>;
203 xlnx,mem0-width = <0x10>;
204 xlnx,mem1-width = <0x20>;
205 xlnx,mem2-width = <0x20>;
206 xlnx,mem3-width = <0x20>;
207 xlnx,num-banks-mem = <0x1>;
208 xlnx,num-channels = <0x2>;
209 xlnx,priority-mode = <0x0>;
210 xlnx,synch-mem-0 = <0x0>;
211 xlnx,synch-mem-1 = <0x0>;
212 xlnx,synch-mem-2 = <0x0>;
213 xlnx,synch-mem-3 = <0x0>;
214 xlnx,synch-pipedelay-0 = <0x2>;
215 xlnx,synch-pipedelay-1 = <0x2>;
216 xlnx,synch-pipedelay-2 = <0x2>;
217 xlnx,synch-pipedelay-3 = <0x2>;
218 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
219 xlnx,tavdv-ps-mem-1 = <0x3a98>;
220 xlnx,tavdv-ps-mem-2 = <0x3a98>;
221 xlnx,tavdv-ps-mem-3 = <0x3a98>;
222 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
223 xlnx,tcedv-ps-mem-1 = <0x3a98>;
224 xlnx,tcedv-ps-mem-2 = <0x3a98>;
225 xlnx,tcedv-ps-mem-3 = <0x3a98>;
226 xlnx,thzce-ps-mem-0 = <0x88b8>;
227 xlnx,thzce-ps-mem-1 = <0x1b58>;
228 xlnx,thzce-ps-mem-2 = <0x1b58>;
229 xlnx,thzce-ps-mem-3 = <0x1b58>;
230 xlnx,thzoe-ps-mem-0 = <0x1b58>;
231 xlnx,thzoe-ps-mem-1 = <0x1b58>;
232 xlnx,thzoe-ps-mem-2 = <0x1b58>;
233 xlnx,thzoe-ps-mem-3 = <0x1b58>;
234 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
235 xlnx,tlzwe-ps-mem-1 = <0x0>;
236 xlnx,tlzwe-ps-mem-2 = <0x0>;
237 xlnx,tlzwe-ps-mem-3 = <0x0>;
238 xlnx,twc-ps-mem-0 = <0x2af8>;
239 xlnx,twc-ps-mem-1 = <0x3a98>;
240 xlnx,twc-ps-mem-2 = <0x3a98>;
241 xlnx,twc-ps-mem-3 = <0x3a98>;
242 xlnx,twp-ps-mem-0 = <0x11170>;
243 xlnx,twp-ps-mem-1 = <0x2ee0>;
244 xlnx,twp-ps-mem-2 = <0x2ee0>;
245 xlnx,twp-ps-mem-3 = <0x2ee0>;
246 xlnx,xcl0-linesize = <0x4>;
247 xlnx,xcl0-writexfer = <0x1>;
248 xlnx,xcl1-linesize = <0x4>;
249 xlnx,xcl1-writexfer = <0x1>;
250 xlnx,xcl2-linesize = <0x4>;
251 xlnx,xcl2-writexfer = <0x1>;
252 xlnx,xcl3-linesize = <0x4>;
253 xlnx,xcl3-writexfer = <0x1>;
254 } ;
166 Hard_Ethernet_MAC: xps-ll-temac@81c00000 { 255 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
167 #address-cells = <1>; 256 #address-cells = <1>;
168 #size-cells = <1>; 257 #size-cells = <1>;
@@ -185,6 +274,19 @@
185 xlnx,txfifo = <0x1000>; 274 xlnx,txfifo = <0x1000>;
186 } ; 275 } ;
187 } ; 276 } ;
277 IIC_EEPROM: i2c@81600000 {
278 compatible = "xlnx,xps-iic-2.00.a";
279 interrupt-parent = <&xps_intc_0>;
280 interrupts = < 6 2 >;
281 reg = < 0x81600000 0x10000 >;
282 xlnx,clk-freq = <0x5f5e100>;
283 xlnx,family = "virtex5";
284 xlnx,gpo-width = <0x1>;
285 xlnx,iic-freq = <0x186a0>;
286 xlnx,scl-inertial-delay = <0x0>;
287 xlnx,sda-inertial-delay = <0x0>;
288 xlnx,ten-bit-adr = <0x0>;
289 } ;
188 LEDs_8Bit: gpio@81400000 { 290 LEDs_8Bit: gpio@81400000 {
189 compatible = "xlnx,xps-gpio-1.00.a"; 291 compatible = "xlnx,xps-gpio-1.00.a";
190 reg = < 0x81400000 0x10000 >; 292 reg = < 0x81400000 0x10000 >;
@@ -220,7 +322,7 @@
220 Push_Buttons_5Bit: gpio@81440000 { 322 Push_Buttons_5Bit: gpio@81440000 {
221 compatible = "xlnx,xps-gpio-1.00.a"; 323 compatible = "xlnx,xps-gpio-1.00.a";
222 interrupt-parent = <&xps_intc_0>; 324 interrupt-parent = <&xps_intc_0>;
223 interrupts = < 7 2 >; 325 interrupts = < 8 2 >;
224 reg = < 0x81440000 0x10000 >; 326 reg = < 0x81440000 0x10000 >;
225 xlnx,all-inputs = <1>; 327 xlnx,all-inputs = <1>;
226 xlnx,all-inputs-2 = <0>; 328 xlnx,all-inputs-2 = <0>;
@@ -237,13 +339,13 @@
237 } ; 339 } ;
238 RS232_Uart_1: serial@83e00000 { 340 RS232_Uart_1: serial@83e00000 {
239 clock-frequency = <100000000>; 341 clock-frequency = <100000000>;
240 compatible = "xlnx,xps-uart16550-2.00.a", "ns16550"; 342 compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
241 current-speed = <0x2580>; 343 current-speed = <9600>;
242 device_type = "serial"; 344 device_type = "serial";
243 interrupt-parent = <&xps_intc_0>; 345 interrupt-parent = <&xps_intc_0>;
244 interrupts = < 8 2 >; 346 interrupts = < 9 2 >;
245 reg = < 0x83e00000 0x10000 >; 347 reg = < 0x83e00000 0x10000 >;
246 reg-offset = <3>; 348 reg-offset = <0x1003>;
247 reg-shift = <2>; 349 reg-shift = <2>;
248 xlnx,family = "virtex5"; 350 xlnx,family = "virtex5";
249 xlnx,has-external-rclk = <0>; 351 xlnx,has-external-rclk = <0>;
@@ -268,7 +370,7 @@
268 compatible = "xlnx,xps-intc-1.00.a"; 370 compatible = "xlnx,xps-intc-1.00.a";
269 interrupt-controller ; 371 interrupt-controller ;
270 reg = < 0x81800000 0x10000 >; 372 reg = < 0x81800000 0x10000 >;
271 xlnx,num-intr-inputs = <0xb>; 373 xlnx,num-intr-inputs = <0xc>;
272 } ; 374 } ;
273 xps_timebase_wdt_1: xps-timebase-wdt@83a00000 { 375 xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
274 compatible = "xlnx,xps-timebase-wdt-1.00.b"; 376 compatible = "xlnx,xps-timebase-wdt-1.00.b";
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 01:02:04 -0500