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-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts432
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diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
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1/*
2 * MPC8536 DS Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30
31 cpus {
32 #cpus = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8536@0 {
37 device_type = "cpu";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <00000000 00000000>; // Filled by U-Boot
46 };
47
48 soc@ffe00000 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 device_type = "soc";
52 ranges = <0x0 0xffe00000 0x100000>;
53 reg = <0xffe00000 0x1000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 memory-controller@2000 {
57 compatible = "fsl,mpc8536-memory-controller";
58 reg = <0x2000 0x1000>;
59 interrupt-parent = <&mpic>;
60 interrupts = <18 0x2>;
61 };
62
63 L2: l2-cache-controller@20000 {
64 compatible = "fsl,mpc8536-l2-cache-controller";
65 reg = <0x20000 0x1000>;
66 interrupt-parent = <&mpic>;
67 interrupts = <16 0x2>;
68 };
69
70 i2c@3000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 cell-index = <0>;
74 compatible = "fsl-i2c";
75 reg = <0x3000 0x100>;
76 interrupts = <43 0x2>;
77 interrupt-parent = <&mpic>;
78 dfsrr;
79 };
80
81 i2c@3100 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <1>;
85 compatible = "fsl-i2c";
86 reg = <0x3100 0x100>;
87 interrupts = <43 0x2>;
88 interrupt-parent = <&mpic>;
89 dfsrr;
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 };
94 };
95
96 dma@21300 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
100 reg = <0x21300 4>;
101 ranges = <0 0x21100 0x200>;
102 cell-index = <0>;
103 dma-channel@0 {
104 compatible = "fsl,mpc8536-dma-channel",
105 "fsl,eloplus-dma-channel";
106 reg = <0x0 0x80>;
107 cell-index = <0>;
108 interrupt-parent = <&mpic>;
109 interrupts = <14 0x2>;
110 };
111 dma-channel@80 {
112 compatible = "fsl,mpc8536-dma-channel",
113 "fsl,eloplus-dma-channel";
114 reg = <0x80 0x80>;
115 cell-index = <1>;
116 interrupt-parent = <&mpic>;
117 interrupts = <15 0x2>;
118 };
119 dma-channel@100 {
120 compatible = "fsl,mpc8536-dma-channel",
121 "fsl,eloplus-dma-channel";
122 reg = <0x100 0x80>;
123 cell-index = <2>;
124 interrupt-parent = <&mpic>;
125 interrupts = <16 0x2>;
126 };
127 dma-channel@180 {
128 compatible = "fsl,mpc8536-dma-channel",
129 "fsl,eloplus-dma-channel";
130 reg = <0x180 0x80>;
131 cell-index = <3>;
132 interrupt-parent = <&mpic>;
133 interrupts = <17 0x2>;
134 };
135 };
136
137 mdio@24520 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 compatible = "fsl,gianfar-mdio";
141 reg = <0x24520 0x20>;
142
143 phy0: ethernet-phy@0 {
144 interrupt-parent = <&mpic>;
145 interrupts = <10 0x1>;
146 reg = <0>;
147 device_type = "ethernet-phy";
148 };
149 phy1: ethernet-phy@1 {
150 interrupt-parent = <&mpic>;
151 interrupts = <10 0x1>;
152 reg = <1>;
153 device_type = "ethernet-phy";
154 };
155 };
156
157 usb@22000 {
158 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
159 reg = <0x22000 0x1000>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupt-parent = <&mpic>;
163 interrupts = <28 0x2>;
164 phy_type = "ulpi";
165 };
166
167 usb@23000 {
168 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
169 reg = <0x23000 0x1000>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 interrupt-parent = <&mpic>;
173 interrupts = <46 0x2>;
174 phy_type = "ulpi";
175 };
176
177 enet0: ethernet@24000 {
178 cell-index = <0>;
179 device_type = "network";
180 model = "TSEC";
181 compatible = "gianfar";
182 reg = <0x24000 0x1000>;
183 local-mac-address = [ 00 00 00 00 00 00 ];
184 interrupts = <29 2 30 2 34 2>;
185 interrupt-parent = <&mpic>;
186 phy-handle = <&phy1>;
187 phy-connection-type = "rgmii-id";
188 };
189
190 enet1: ethernet@26000 {
191 cell-index = <1>;
192 device_type = "network";
193 model = "TSEC";
194 compatible = "gianfar";
195 reg = <0x26000 0x1000>;
196 local-mac-address = [ 00 00 00 00 00 00 ];
197 interrupts = <31 2 32 2 33 2>;
198 interrupt-parent = <&mpic>;
199 phy-handle = <&phy0>;
200 phy-connection-type = "rgmii-id";
201 };
202
203 usb@2b000 {
204 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
205 reg = <0x2b000 0x1000>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 interrupt-parent = <&mpic>;
209 interrupts = <60 0x2>;
210 dr_mode = "peripheral";
211 phy_type = "ulpi";
212 };
213
214 serial0: serial@4500 {
215 cell-index = <0>;
216 device_type = "serial";
217 compatible = "ns16550";
218 reg = <0x4500 0x100>;
219 clock-frequency = <0>;
220 interrupts = <42 0x2>;
221 interrupt-parent = <&mpic>;
222 };
223
224 serial1: serial@4600 {
225 cell-index = <1>;
226 device_type = "serial";
227 compatible = "ns16550";
228 reg = <0x4600 0x100>;
229 clock-frequency = <0>;
230 interrupts = <42 0x2>;
231 interrupt-parent = <&mpic>;
232 };
233
234 crypto@30000 {
235 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
236 "fsl,sec2.1", "fsl,sec2.0";
237 reg = <0x30000 0x10000>;
238 interrupts = <45 2 58 2>;
239 interrupt-parent = <&mpic>;
240 fsl,num-channels = <4>;
241 fsl,channel-fifo-len = <24>;
242 fsl,exec-units-mask = <0x9fe>;
243 fsl,descriptor-types-mask = <0x3ab0ebf>;
244 };
245
246 sata@18000 {
247 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
248 reg = <0x18000 0x1000>;
249 cell-index = <1>;
250 interrupts = <74 0x2>;
251 interrupt-parent = <&mpic>;
252 };
253
254 sata@19000 {
255 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
256 reg = <0x19000 0x1000>;
257 cell-index = <2>;
258 interrupts = <41 0x2>;
259 interrupt-parent = <&mpic>;
260 };
261
262 global-utilities@e0000 { //global utilities block
263 compatible = "fsl,mpc8548-guts";
264 reg = <0xe0000 0x1000>;
265 fsl,has-rstcr;
266 };
267
268 mpic: pic@40000 {
269 clock-frequency = <0>;
270 interrupt-controller;
271 #address-cells = <0>;
272 #interrupt-cells = <2>;
273 reg = <0x40000 0x40000>;
274 compatible = "chrp,open-pic";
275 device_type = "open-pic";
276 big-endian;
277 };
278
279 msi@41600 {
280 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
281 reg = <0x41600 0x80>;
282 msi-available-ranges = <0 0x100>;
283 interrupts = <
284 0xe0 0
285 0xe1 0
286 0xe2 0
287 0xe3 0
288 0xe4 0
289 0xe5 0
290 0xe6 0
291 0xe7 0>;
292 interrupt-parent = <&mpic>;
293 };
294 };
295
296 pci0: pci@ffe08000 {
297 cell-index = <0>;
298 compatible = "fsl,mpc8540-pci";
299 device_type = "pci";
300 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
301 interrupt-map = <
302
303 /* IDSEL 0x11 J17 Slot 1 */
304 0x8800 0 0 1 &mpic 1 1
305 0x8800 0 0 2 &mpic 2 1
306 0x8800 0 0 3 &mpic 3 1
307 0x8800 0 0 4 &mpic 4 1>;
308
309 interrupt-parent = <&mpic>;
310 interrupts = <24 0x2>;
311 bus-range = <0 0xff>;
312 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
313 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
314 clock-frequency = <66666666>;
315 #interrupt-cells = <1>;
316 #size-cells = <2>;
317 #address-cells = <3>;
318 reg = <0xffe08000 0x1000>;
319 };
320
321 pci1: pcie@ffe09000 {
322 cell-index = <1>;
323 compatible = "fsl,mpc8548-pcie";
324 device_type = "pci";
325 #interrupt-cells = <1>;
326 #size-cells = <2>;
327 #address-cells = <3>;
328 reg = <0xffe09000 0x1000>;
329 bus-range = <0 0xff>;
330 ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
331 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
332 clock-frequency = <33333333>;
333 interrupt-parent = <&mpic>;
334 interrupts = <25 0x2>;
335 interrupt-map-mask = <0xf800 0 0 7>;
336 interrupt-map = <
337 /* IDSEL 0x0 */
338 0000 0 0 1 &mpic 4 1
339 0000 0 0 2 &mpic 5 1
340 0000 0 0 3 &mpic 6 1
341 0000 0 0 4 &mpic 7 1
342 >;
343 pcie@0 {
344 reg = <0 0 0 0 0>;
345 #size-cells = <2>;
346 #address-cells = <3>;
347 device_type = "pci";
348 ranges = <0x02000000 0 0x98000000
349 0x02000000 0 0x98000000
350 0 0x08000000
351
352 0x01000000 0 0x00000000
353 0x01000000 0 0x00000000
354 0 0x00010000>;
355 };
356 };
357
358 pci2: pcie@ffe0a000 {
359 cell-index = <2>;
360 compatible = "fsl,mpc8548-pcie";
361 device_type = "pci";
362 #interrupt-cells = <1>;
363 #size-cells = <2>;
364 #address-cells = <3>;
365 reg = <0xffe0a000 0x1000>;
366 bus-range = <0 0xff>;
367 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
368 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
369 clock-frequency = <33333333>;
370 interrupt-parent = <&mpic>;
371 interrupts = <26 0x2>;
372 interrupt-map-mask = <0xf800 0 0 7>;
373 interrupt-map = <
374 /* IDSEL 0x0 */
375 0000 0 0 1 &mpic 0 1
376 0000 0 0 2 &mpic 1 1
377 0000 0 0 3 &mpic 2 1
378 0000 0 0 4 &mpic 3 1
379 >;
380 pcie@0 {
381 reg = <0 0 0 0 0>;
382 #size-cells = <2>;
383 #address-cells = <3>;
384 device_type = "pci";
385 ranges = <0x02000000 0 0x90000000
386 0x02000000 0 0x90000000
387 0 0x08000000
388
389 0x01000000 0 0x00000000
390 0x01000000 0 0x00000000
391 0 0x00010000>;
392 };
393 };
394
395 pci3: pcie@ffe0b000 {
396 cell-index = <3>;
397 compatible = "fsl,mpc8548-pcie";
398 device_type = "pci";
399 #interrupt-cells = <1>;
400 #size-cells = <2>;
401 #address-cells = <3>;
402 reg = <0xffe0b000 0x1000>;
403 bus-range = <0 0xff>;
404 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
405 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
406 clock-frequency = <33333333>;
407 interrupt-parent = <&mpic>;
408 interrupts = <27 0x2>;
409 interrupt-map-mask = <0xf800 0 0 7>;
410 interrupt-map = <
411 /* IDSEL 0x0 */
412 0000 0 0 1 &mpic 8 1
413 0000 0 0 2 &mpic 9 1
414 0000 0 0 3 &mpic 10 1
415 0000 0 0 4 &mpic 11 1
416 >;
417
418 pcie@0 {
419 reg = <0 0 0 0 0>;
420 #size-cells = <2>;
421 #address-cells = <3>;
422 device_type = "pci";
423 ranges = <0x02000000 0 0xa0000000
424 0x02000000 0 0xa0000000
425 0 0x20000000
426
427 0x01000000 0 0x00000000
428 0x01000000 0 0x00000000
429 0 0x00100000>;
430 };
431 };
432};