85 files changed, 4052 insertions, 1056 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5f149b030c0..f4af967a6b3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -238,21 +238,8 @@ config MIPS_SIM
           This option enables support for MIPS Technologies MIPSsim software
           emulator.
 
-config MARKEINS
-        bool "NEC EMMA2RH Mark-eins"
-        select CEVT_R4K
-        select CSRC_R4K
-        select DMA_NONCOHERENT
-        select HW_HAS_PCI
-        select IRQ_CPU
-        select SWAP_IO_SPACE
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_HAS_CPU_R5000
-        help
-          This enables support for the R5432-based NEC Mark-eins
-          boards with R5500 CPU.
+config MACH_EMMA
+        bool "NEC EMMA series based machines"
 
 config MACH_VR41XX
         bool "NEC VR4100 series based machines"
@@ -261,6 +248,19 @@ config MACH_VR41XX
         select SYS_HAS_CPU_VR41XX
         select GENERIC_HARDIRQS_NO__DO_IRQ
 
+config NXP_STB220
+        bool "NXP STB220 board"
+        select SOC_PNX833X
+        help
+         Support for NXP Semiconductors STB220 Development Board.
+
+config NXP_STB225
+        bool "NXP 225 board"
+        select SOC_PNX833X
+        select SOC_PNX8335
+        help
+         Support for NXP Semiconductors STB225 Development Board.
+
 config PNX8550_JBS
         bool "NXP PNX8550 based JBS board"
         select PNX8550
@@ -327,7 +327,6 @@ config SGI_IP22
         select IP22_CPU_SCACHE
         select IRQ_CPU
         select GENERIC_ISA_DMA_SUPPORT_BROKEN
-        select SGI_HAS_DS1286
         select SGI_HAS_I8042
         select SGI_HAS_INDYDOG
         select SGI_HAS_HAL2
@@ -382,7 +381,6 @@ config SGI_IP28
         select HW_HAS_EISA
         select I8253
         select I8259
-        select SGI_HAS_DS1286
         select SGI_HAS_I8042
         select SGI_HAS_INDYDOG
         select SGI_HAS_HAL2
@@ -601,6 +599,7 @@ endchoice
 
 source "arch/mips/alchemy/Kconfig"
 source "arch/mips/basler/excite/Kconfig"
+source "arch/mips/emma/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/lasat/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
@@ -849,6 +848,24 @@ config MIPS_RM9122
         bool
         select SERIAL_RM9000
 
+config SOC_PNX833X
+        bool
+        select CEVT_R4K
+        select CSRC_R4K
+        select IRQ_CPU
+        select DMA_NONCOHERENT
+        select SYS_HAS_CPU_MIPS32_R2
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select GENERIC_HARDIRQS_NO__DO_IRQ
+        select GENERIC_GPIO
+        select CPU_MIPSR2_IRQ_VI
+
+config SOC_PNX8335
+        bool
+        select SOC_PNX833X
+
 config PNX8550
         bool
         select SOC_PNX8550
@@ -874,9 +891,6 @@ config EMMA2RH
 config SERIAL_RM9000
         bool
 
-config SGI_HAS_DS1286
-        bool
-
 config SGI_HAS_INDYDOG
         bool
 
@@ -1092,6 +1106,16 @@ config CPU_R5432
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
 
+config CPU_R5500
+        bool "R5500"
+        depends on SYS_HAS_CPU_R5500
+        select CPU_HAS_LLSC
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_SUPPORTS_64BIT_KERNEL
+        help
+          NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
+          instruction set.
+
 config CPU_R6000
         bool "R6000"
         depends on EXPERIMENTAL
@@ -1202,6 +1226,9 @@ config SYS_HAS_CPU_R5000
 config SYS_HAS_CPU_R5432
         bool
 
+config SYS_HAS_CPU_R5500
+        bool
+
 config SYS_HAS_CPU_R6000
         bool
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 7f39fd8a91f..28c55f60891 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -131,6 +131,8 @@ cflags-$(CONFIG_CPU_MIPS64_R2)	+= $(call cc-option,-march=mips64r2,-mips64r2 -U_
 cflags-$(CONFIG_CPU_R5000)      += -march=r5000 -Wa,--trap
 cflags-$(CONFIG_CPU_R5432)      += $(call cc-option,-march=r5400,-march=r5000) \
                         -Wa,--trap
+cflags-$(CONFIG_CPU_R5500)      += $(call cc-option,-march=r5500,-march=r5000) \
+                        -Wa,--trap
 cflags-$(CONFIG_CPU_NEVADA)     += $(call cc-option,-march=rm5200,-march=r5000) \
                         -Wa,--trap
 cflags-$(CONFIG_CPU_RM7000)     += $(call cc-option,-march=rm7000,-march=r5000) \
@@ -381,6 +383,14 @@ load-$(CONFIG_CASIO_E55)	+= 0xffffffff80004000
 #
 load-$(CONFIG_TANBAC_TB022X)    += 0xffffffff80000000
 
+# NXP STB225
+core-$(CONFIG_SOC_PNX833X)              += arch/mips/nxp/pnx833x/common/
+cflags-$(CONFIG_SOC_PNX833X)    += -Iarch/mips/include/asm/mach-pnx833x
+libs-$(CONFIG_NXP_STB220)               += arch/mips/nxp/pnx833x/stb22x/
+load-$(CONFIG_NXP_STB220)               += 0xffffffff80001000
+libs-$(CONFIG_NXP_STB225)               += arch/mips/nxp/pnx833x/stb22x/
+load-$(CONFIG_NXP_STB225)               += 0xffffffff80001000
+
 #
 # Common NXP PNX8550
 #
@@ -399,14 +409,17 @@ load-$(CONFIG_PNX8550_JBS)	+= 0xffffffff80060000
 libs-$(CONFIG_PNX8550_STB810)   += arch/mips/nxp/pnx8550/stb810/
 load-$(CONFIG_PNX8550_STB810)   += 0xffffffff80060000
 
-# NEC EMMA2RH boards
 #
-core-$(CONFIG_EMMA2RH)          += arch/mips/emma2rh/common/
-cflags-$(CONFIG_EMMA2RH)        += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
+# Common NEC EMMAXXX
+#
+core-$(CONFIG_SOC_EMMA)         += arch/mips/emma/common/
+cflags-$(CONFIG_SOC_EMMA2RH)    += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
 
+#
 # NEC EMMA2RH Mark-eins
-core-$(CONFIG_MARKEINS)         += arch/mips/emma2rh/markeins/
-load-$(CONFIG_MARKEINS)         += 0xffffffff88100000
+#
+core-$(CONFIG_NEC_MARKEINS)     += arch/mips/emma/markeins/
+load-$(CONFIG_NEC_MARKEINS)     += 0xffffffff88100000
 
 #
 # SGI IP22 (Indy/Indigo2)
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index dc8a67efac2..5c76c6448e0 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -17,6 +17,8 @@
 #include <linux/init.h>
 
 #include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/mach-au1x00/au1100_mmc.h>
 
 #define PORT(_base, _irq)                               \
         {                                               \
@@ -163,24 +165,6 @@ static struct resource au1xxx_usb_gdt_resources[] = {
         },
 };
 
-static struct resource au1xxx_mmc_resources[] = {
-        [0] = {
-                .start          = SD0_PHYS_ADDR,
-                .end            = SD0_PHYS_ADDR + 0x7ffff,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = SD1_PHYS_ADDR,
-                .end            = SD1_PHYS_ADDR + 0x7ffff,
-                .flags          = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start          = AU1200_SD_INT,
-                .end            = AU1200_SD_INT,
-                .flags          = IORESOURCE_IRQ,
-        }
-};
-
 static u64 udc_dmamask = DMA_32BIT_MASK;
 
 static struct platform_device au1xxx_usb_gdt_device = {
@@ -249,16 +233,79 @@ static struct platform_device au1200_lcd_device = {
 
 static u64 au1xxx_mmc_dmamask =  DMA_32BIT_MASK;
 
-static struct platform_device au1xxx_mmc_device = {
+extern struct au1xmmc_platform_data au1xmmc_platdata[2];
+
+static struct resource au1200_mmc0_resources[] = {
+        [0] = {
+                .start          = SD0_PHYS_ADDR,
+                .end            = SD0_PHYS_ADDR + 0x7ffff,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = AU1200_SD_INT,
+                .end            = AU1200_SD_INT,
+                .flags          = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start          = DSCR_CMD0_SDMS_TX0,
+                .end            = DSCR_CMD0_SDMS_TX0,
+                .flags          = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start          = DSCR_CMD0_SDMS_RX0,
+                .end            = DSCR_CMD0_SDMS_RX0,
+                .flags          = IORESOURCE_DMA,
+        }
+};
+
+static struct platform_device au1200_mmc0_device = {
         .name = "au1xxx-mmc",
         .id = 0,
         .dev = {
-                .dma_mask               = &au1xxx_mmc_dmamask,
-                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .dma_mask               = &au1xxx_mmc_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .platform_data          = &au1xmmc_platdata[0],
         },
-        .num_resources  = ARRAY_SIZE(au1xxx_mmc_resources),
-        .resource       = au1xxx_mmc_resources,
+        .num_resources  = ARRAY_SIZE(au1200_mmc0_resources),
+        .resource       = au1200_mmc0_resources,
 };
+
+#ifndef CONFIG_MIPS_DB1200
+static struct resource au1200_mmc1_resources[] = {
+        [0] = {
+                .start          = SD1_PHYS_ADDR,
+                .end            = SD1_PHYS_ADDR + 0x7ffff,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = AU1200_SD_INT,
+                .end            = AU1200_SD_INT,
+                .flags          = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start          = DSCR_CMD0_SDMS_TX1,
+                .end            = DSCR_CMD0_SDMS_TX1,
+                .flags          = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start          = DSCR_CMD0_SDMS_RX1,
+                .end            = DSCR_CMD0_SDMS_RX1,
+                .flags          = IORESOURCE_DMA,
+        }
+};
+
+static struct platform_device au1200_mmc1_device = {
+        .name = "au1xxx-mmc",
+        .id = 1,
+        .dev = {
+                .dma_mask               = &au1xxx_mmc_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .platform_data          = &au1xmmc_platdata[1],
+        },
+        .num_resources  = ARRAY_SIZE(au1200_mmc1_resources),
+        .resource       = au1200_mmc1_resources,
+};
+#endif /* #ifndef CONFIG_MIPS_DB1200 */
 #endif /* #ifdef CONFIG_SOC_AU1200 */
 
 static struct platform_device au1x00_pcmcia_device = {
@@ -296,7 +343,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
         &au1xxx_usb_gdt_device,
         &au1xxx_usb_otg_device,
         &au1200_lcd_device,
-        &au1xxx_mmc_device,
+        &au1200_mmc0_device,
+#ifndef CONFIG_MIPS_DB1200
+        &au1200_mmc1_device,
+#endif
 #endif
 #ifdef SMBUS_PSC_BASE
         &pbdb_smbus_device,
diff --git a/arch/mips/alchemy/pb1200/platform.c b/arch/mips/alchemy/pb1200/platform.c
index f8fb0aeac57..95303297c53 100644
--- a/arch/mips/alchemy/pb1200/platform.c
+++ b/arch/mips/alchemy/pb1200/platform.c
@@ -20,9 +20,90 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
+#include <linux/leds.h>
 #include <linux/platform_device.h>
 
 #include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1100_mmc.h>
+
+static int mmc_activity;
+
+static void pb1200mmc0_set_power(void *mmc_host, int state)
+{
+        if (state)
+                bcsr->board |= BCSR_BOARD_SD0PWR;
+        else
+                bcsr->board &= ~BCSR_BOARD_SD0PWR;
+
+        au_sync_delay(1);
+}
+
+static int pb1200mmc0_card_readonly(void *mmc_host)
+{
+        return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0;
+}
+
+static int pb1200mmc0_card_inserted(void *mmc_host)
+{
+        return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0;
+}
+
+static void pb1200_mmcled_set(struct led_classdev *led,
+                        enum led_brightness brightness)
+{
+        if (brightness != LED_OFF) {
+                if (++mmc_activity == 1)
+                        bcsr->disk_leds &= ~(1 << 8);
+        } else {
+                if (--mmc_activity == 0)
+                        bcsr->disk_leds |= (1 << 8);
+        }
+}
+
+static struct led_classdev pb1200mmc_led = {
+        .brightness_set = pb1200_mmcled_set,
+};
+
+#ifndef CONFIG_MIPS_DB1200
+static void pb1200mmc1_set_power(void *mmc_host, int state)
+{
+        if (state)
+                bcsr->board |= BCSR_BOARD_SD1PWR;
+        else
+                bcsr->board &= ~BCSR_BOARD_SD1PWR;
+
+        au_sync_delay(1);
+}
+
+static int pb1200mmc1_card_readonly(void *mmc_host)
+{
+        return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0;
+}
+
+static int pb1200mmc1_card_inserted(void *mmc_host)
+{
+        return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0;
+}
+#endif
+
+const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
+        [0] = {
+                .set_power      = pb1200mmc0_set_power,
+                .card_inserted  = pb1200mmc0_card_inserted,
+                .card_readonly  = pb1200mmc0_card_readonly,
+                .cd_setup       = NULL,         /* use poll-timer in driver */
+                .led            = &pb1200mmc_led,
+        },
+#ifndef CONFIG_MIPS_DB1200
+        [1] = {
+                .set_power      = pb1200mmc1_set_power,
+                .card_inserted  = pb1200mmc1_card_inserted,
+                .card_readonly  = pb1200mmc1_card_readonly,
+                .cd_setup       = NULL,         /* use poll-timer in driver */
+                .led            = &pb1200mmc_led,
+        },
+#endif
+};
 
 static struct resource ide_resources[] = {
         [0] = {
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index cc8e6bf2b24..f719bf5e01a 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -771,7 +771,6 @@ CONFIG_WATCHDOG=y
 CONFIG_INDYDOG=m
 # CONFIG_HW_RANDOM is not set
 # CONFIG_RTC is not set
-CONFIG_SGI_DS1286=m
 # CONFIG_R3964 is not set
 CONFIG_RAW_DRIVER=m
 CONFIG_MAX_RAW_DEVS=256
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 831d3e5a1ea..34ea319be94 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -701,7 +701,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=m
 # CONFIG_RTC is not set
-CONFIG_SGI_IP27_RTC=y
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_DRM is not set
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 822b01f643e..70a744e9a8c 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -70,7 +70,6 @@ CONFIG_CPU_BIG_ENDIAN=y
 CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
 CONFIG_IRQ_CPU=y
 CONFIG_SWAP_IO_SPACE=y
-CONFIG_SGI_HAS_DS1286=y
 CONFIG_SGI_HAS_INDYDOG=y
 CONFIG_SGI_HAS_SEEQ=y
 CONFIG_SGI_HAS_WD93=y
@@ -585,7 +584,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_RTC is not set
-CONFIG_SGI_DS1286=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig
new file mode 100644
index 00000000000..d9536522cff
--- /dev/null
+++ b/arch/mips/configs/pnx8335-stb225_defconfig
@@ -0,0 +1,1149 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26
+# Sat Jul 26 09:02:59 2008
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+CONFIG_NXP_STB225=y
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_HOTPLUG_CPU is not set
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SOC_PNX833X=y
+CONFIG_SOC_PNX8335=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2 is not set
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_128=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=128
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+# CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=y
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_LE_BYTE_SWAP=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x18000000
+CONFIG_MTD_PHYSMAP_LEN=0x04000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PNX8XXX=y
+CONFIG_SERIAL_PNX8XXX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+CONFIG_DVB_CORE=y
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# DVB-S (satellite) frontends
+#
+# CONFIG_DVB_CX24110 is not set
+# CONFIG_DVB_CX24123 is not set
+# CONFIG_DVB_MT312 is not set
+# CONFIG_DVB_S5H1420 is not set
+# CONFIG_DVB_STV0299 is not set
+# CONFIG_DVB_TDA8083 is not set
+# CONFIG_DVB_TDA10086 is not set
+# CONFIG_DVB_VES1X93 is not set
+# CONFIG_DVB_TUNER_ITD1000 is not set
+# CONFIG_DVB_TDA826X is not set
+# CONFIG_DVB_TUA6100 is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+# CONFIG_DVB_SP8870 is not set
+# CONFIG_DVB_SP887X is not set
+# CONFIG_DVB_CX22700 is not set
+# CONFIG_DVB_CX22702 is not set
+# CONFIG_DVB_DRX397XD is not set
+# CONFIG_DVB_L64781 is not set
+CONFIG_DVB_TDA1004X=y
+# CONFIG_DVB_NXT6000 is not set
+# CONFIG_DVB_MT352 is not set
+# CONFIG_DVB_ZL10353 is not set
+# CONFIG_DVB_DIB3000MB is not set
+# CONFIG_DVB_DIB3000MC is not set
+# CONFIG_DVB_DIB7000M is not set
+# CONFIG_DVB_DIB7000P is not set
+# CONFIG_DVB_TDA10048 is not set
+
+#
+# DVB-C (cable) frontends
+#
+# CONFIG_DVB_VES1820 is not set
+# CONFIG_DVB_TDA10021 is not set
+# CONFIG_DVB_TDA10023 is not set
+# CONFIG_DVB_STV0297 is not set
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+# CONFIG_DVB_NXT200X is not set
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+# CONFIG_DVB_BCM3510 is not set
+# CONFIG_DVB_LGDT330X is not set
+# CONFIG_DVB_S5H1409 is not set
+# CONFIG_DVB_AU8522 is not set
+# CONFIG_DVB_S5H1411 is not set
+
+#
+# Digital terrestrial only tuners/PLL
+#
+# CONFIG_DVB_PLL is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+
+#
+# SEC control devices for DVB-S
+#
+# CONFIG_DVB_LNBP21 is not set
+# CONFIG_DVB_ISL6405 is not set
+# CONFIG_DVB_ISL6421 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_MIPS=y
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=m
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_CODEPAGE_932=m
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_KERNEL_TESTS is not set
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_PRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/mips/emma/Kconfig b/arch/mips/emma/Kconfig
new file mode 100644
index 00000000000..9669c72123c
--- /dev/null
+++ b/arch/mips/emma/Kconfig
@@ -0,0 +1,29 @@
+choice
+        prompt "Machine type"
+        depends on MACH_EMMA
+        default NEC_MARKEINS
+
+config NEC_MARKEINS
+        bool "NEC EMMA2RH Mark-eins board"
+        select SOC_EMMA2RH
+        select HW_HAS_PCI
+        help
+          This enables support for the NEC Electronics Mark-eins boards.
+
+endchoice
+
+config SOC_EMMA2RH
+        bool
+        select SOC_EMMA
+        select SYS_HAS_CPU_R5500
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_64BIT_KERNEL
+
+config SOC_EMMA
+        bool
+        select CEVT_R4K
+        select CSRC_R4K
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/emma2rh/common/Makefile b/arch/mips/emma/common/Makefile
index 859121b3867..c392d28c1ef 100644
--- a/arch/mips/emma2rh/common/Makefile
+++ b/arch/mips/emma/common/Makefile
@@ -10,4 +10,4 @@
 #  (at your option) any later version.
 #
 
-obj-$(CONFIG_MARKEINS)  += irq.o irq_emma2rh.o prom.o
+obj-$(CONFIG_NEC_MARKEINS)      += prom.o
diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma/common/prom.c
index e14a2e3d884..120f53fbdb4 100644
--- a/arch/mips/emma2rh/common/prom.c
+++ b/arch/mips/emma/common/prom.c
@@ -29,11 +29,11 @@
 
 #include <asm/addrspace.h>
 #include <asm/bootinfo.h>
-#include <asm/emma2rh/emma2rh.h>
+#include <asm/emma/emma2rh.h>
 
 const char *get_system_type(void)
 {
-#if defined(CONFIG_MARKEINS)
+#ifdef CONFIG_NEC_MARKEINS
         return "NEC EMMA2RH Mark-eins";
 #else
 #error  Unknown NEC board
@@ -60,7 +60,7 @@ void __init prom_init(void)
                 strcat(arcs_cmdline, " ");
         }
 
-#if defined(CONFIG_MARKEINS)
+#ifdef CONFIG_NEC_MARKEINS
         add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
 #else
 #error  Unknown NEC board
diff --git a/arch/mips/emma2rh/markeins/Makefile b/arch/mips/emma/markeins/Makefile
index 14fc268b175..16e0017ba91 100644
--- a/arch/mips/emma2rh/markeins/Makefile
+++ b/arch/mips/emma/markeins/Makefile
@@ -10,4 +10,4 @@
 #  (at your option) any later version.
 #
 
-obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o
+obj-$(CONFIG_NEC_MARKEINS) += irq.o setup.o led.o platform.o
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
new file mode 100644
index 00000000000..c2583ecc93c
--- /dev/null
+++ b/arch/mips/emma/markeins/irq.c
@@ -0,0 +1,331 @@
+/*
+ *  arch/mips/emma2rh/markeins/irq.c
+ *      This file defines the irq handler for EMMA2RH.
+ *
+ *  Copyright (C) NEC Electronics Corporation 2004-2006
+ *
+ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
+ *
+ *      Copyright 2001 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/delay.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/system.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+
+#include <asm/emma/emma2rh.h>
+
+static void emma2rh_irq_enable(unsigned int irq)
+{
+        u32 reg_value;
+        u32 reg_bitmask;
+        u32 reg_index;
+
+        irq -= EMMA2RH_IRQ_BASE;
+
+        reg_index = EMMA2RH_BHIF_INT_EN_0 +
+                    (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
+        reg_value = emma2rh_in32(reg_index);
+        reg_bitmask = 0x1 << (irq % 32);
+        emma2rh_out32(reg_index, reg_value | reg_bitmask);
+}
+
+static void emma2rh_irq_disable(unsigned int irq)
+{
+        u32 reg_value;
+        u32 reg_bitmask;
+        u32 reg_index;
+
+        irq -= EMMA2RH_IRQ_BASE;
+
+        reg_index = EMMA2RH_BHIF_INT_EN_0 +
+                    (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
+        reg_value = emma2rh_in32(reg_index);
+        reg_bitmask = 0x1 << (irq % 32);
+        emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
+}
+
+struct irq_chip emma2rh_irq_controller = {
+        .name = "emma2rh_irq",
+        .ack = emma2rh_irq_disable,
+        .mask = emma2rh_irq_disable,
+        .mask_ack = emma2rh_irq_disable,
+        .unmask = emma2rh_irq_enable,
+};
+
+void emma2rh_irq_init(void)
+{
+        u32 i;
+
+        for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
+                set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
+                                         &emma2rh_irq_controller,
+                                         handle_level_irq);
+}
+
+static void emma2rh_sw_irq_enable(unsigned int irq)
+{
+        u32 reg;
+
+        irq -= EMMA2RH_SW_IRQ_BASE;
+
+        reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
+        reg |= 1 << irq;
+        emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
+}
+
+static void emma2rh_sw_irq_disable(unsigned int irq)
+{
+        u32 reg;
+
+        irq -= EMMA2RH_SW_IRQ_BASE;
+
+        reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
+        reg &= ~(1 << irq);
+        emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
+}
+
+struct irq_chip emma2rh_sw_irq_controller = {
+        .name = "emma2rh_sw_irq",
+        .ack = emma2rh_sw_irq_disable,
+        .mask = emma2rh_sw_irq_disable,
+        .mask_ack = emma2rh_sw_irq_disable,
+        .unmask = emma2rh_sw_irq_enable,
+};
+
+void emma2rh_sw_irq_init(void)
+{
+        u32 i;
+
+        for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
+                set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
+                                         &emma2rh_sw_irq_controller,
+                                         handle_level_irq);
+}
+
+static void emma2rh_gpio_irq_enable(unsigned int irq)
+{
+        u32 reg;
+
+        irq -= EMMA2RH_GPIO_IRQ_BASE;
+
+        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+        reg |= 1 << irq;
+        emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
+}
+
+static void emma2rh_gpio_irq_disable(unsigned int irq)
+{
+        u32 reg;
+
+        irq -= EMMA2RH_GPIO_IRQ_BASE;
+
+        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+        reg &= ~(1 << irq);
+        emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
+}
+
+static void emma2rh_gpio_irq_ack(unsigned int irq)
+{
+        u32 reg;
+
+        irq -= EMMA2RH_GPIO_IRQ_BASE;
+        emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
+
+        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+        reg &= ~(1 << irq);
+        emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
+}
+
+static void emma2rh_gpio_irq_end(unsigned int irq)
+{
+        u32 reg;
+
+        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+
+                irq -= EMMA2RH_GPIO_IRQ_BASE;
+
+                reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+                reg |= 1 << irq;
+                emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
+        }
+}
+
+struct irq_chip emma2rh_gpio_irq_controller = {
+        .name = "emma2rh_gpio_irq",
+        .ack = emma2rh_gpio_irq_ack,
+        .mask = emma2rh_gpio_irq_disable,
+        .mask_ack = emma2rh_gpio_irq_ack,
+        .unmask = emma2rh_gpio_irq_enable,
+        .end = emma2rh_gpio_irq_end,
+};
+
+void emma2rh_gpio_irq_init(void)
+{
+        u32 i;
+
+        for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
+                set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
+                             &emma2rh_gpio_irq_controller);
+}
+
+static struct irqaction irq_cascade = {
+           .handler = no_action,
+           .flags = 0,
+           .mask = CPU_MASK_NONE,
+           .name = "cascade",
+           .dev_id = NULL,
+           .next = NULL,
+};
+
+/*
+ * the first level int-handler will jump here if it is a emma2rh irq
+ */
+void emma2rh_irq_dispatch(void)
+{
+        u32 intStatus;
+        u32 bitmask;
+        u32 i;
+
+        intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) &
+                    emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
+
+#ifdef EMMA2RH_SW_CASCADE
+        if (intStatus &
+            (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
+                u32 swIntStatus;
+                swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
+                    & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
+                for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
+                        if (swIntStatus & bitmask) {
+                                do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
+                                return;
+                        }
+                }
+        }
+#endif
+
+        for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
+                if (intStatus & bitmask) {
+                        do_IRQ(EMMA2RH_IRQ_BASE + i);
+                        return;
+                }
+        }
+
+        intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) &
+                    emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
+
+#ifdef EMMA2RH_GPIO_CASCADE
+        if (intStatus &
+            (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
+                u32 gpioIntStatus;
+                gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
+                    & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+                for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
+                        if (gpioIntStatus & bitmask) {
+                                do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
+                                return;
+                        }
+                }
+        }
+#endif
+
+        for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
+                if (intStatus & bitmask) {
+                        do_IRQ(EMMA2RH_IRQ_BASE + i);
+                        return;
+                }
+        }
+
+        intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) &
+                    emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
+
+        for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
+                if (intStatus & bitmask) {
+                        do_IRQ(EMMA2RH_IRQ_BASE + i);
+                        return;
+                }
+        }
+}
+
+void __init arch_init_irq(void)
+{
+        u32 reg;
+
+        /* by default, interrupts are disabled. */
+        emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
+        emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
+        emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
+        emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
+        emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
+        emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
+        emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
+
+        clear_c0_status(0xff00);
+        set_c0_status(0x0400);
+
+#define GPIO_PCI (0xf<<15)
+        /* setup GPIO interrupt for PCI interface */
+        /* direction input */
+        reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
+        emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
+        /* disable interrupt */
+        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+        emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
+        /* level triggerd */
+        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
+        emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
+        reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
+        emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
+        /* interrupt clear */
+        emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
+
+        /* init all controllers */
+        emma2rh_irq_init();
+        emma2rh_sw_irq_init();
+        emma2rh_gpio_irq_init();
+        mips_cpu_irq_init();
+
+        /* setup cascade interrupts */
+        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
+        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
+        setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
+        if (pending & STATUSF_IP7)
+                do_IRQ(CPU_IRQ_BASE + 7);
+        else if (pending & STATUSF_IP2)
+                emma2rh_irq_dispatch();
+        else if (pending & STATUSF_IP1)
+                do_IRQ(CPU_IRQ_BASE + 1);
+        else if (pending & STATUSF_IP0)
+                do_IRQ(CPU_IRQ_BASE + 0);
+        else
+                spurious_interrupt();
+}
diff --git a/arch/mips/emma2rh/markeins/led.c b/arch/mips/emma/markeins/led.c
index b65254c1bfe..377a181b656 100644
--- a/arch/mips/emma2rh/markeins/led.c
+++ b/arch/mips/emma/markeins/led.c
@@ -21,7 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/string.h>
-#include <asm/emma2rh/emma2rh.h>
+#include <asm/emma/emma2rh.h>
 
 const unsigned long clear = 0x20202020;
 
diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma/markeins/platform.c
index fb9cda253ab..88e87f6b344 100644
--- a/arch/mips/emma2rh/markeins/platform.c
+++ b/arch/mips/emma/markeins/platform.c
@@ -36,7 +36,7 @@
 #include <asm/reboot.h>
 #include <asm/traps.h>
 
-#include <asm/emma2rh/emma2rh.h>
+#include <asm/emma/emma2rh.h>
 
 
 #define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma/markeins/setup.c
index b6a23ad539f..67f45650008 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma/markeins/setup.c
@@ -29,7 +29,7 @@
 #include <asm/time.h>
 #include <asm/reboot.h>
 
-#include <asm/emma2rh/emma2rh.h>
+#include <asm/emma/emma2rh.h>
 
 #define USE_CPU_COUNTER_TIMER   /* whether we use cpu counter */
 
diff --git a/arch/mips/emma2rh/common/irq.c b/arch/mips/emma2rh/common/irq.c
deleted file mode 100644
index 91cbd959ab6..00000000000
--- a/arch/mips/emma2rh/common/irq.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- *  arch/mips/emma2rh/common/irq.c
- *      This file is common irq dispatcher.
- *
- *  Copyright (C) NEC Electronics Corporation 2005-2006
- *
- *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
- *
- *      Copyright 2001 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-
-#include <asm/system.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-
-#include <asm/emma2rh/emma2rh.h>
-
-/*
- * the first level int-handler will jump here if it is a emma2rh irq
- */
-void emma2rh_irq_dispatch(void)
-{
-        u32 intStatus;
-        u32 bitmask;
-        u32 i;
-
-        intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
-            & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
-
-#ifdef EMMA2RH_SW_CASCADE
-        if (intStatus &
-            (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
-                u32 swIntStatus;
-                swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
-                    & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
-                for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
-                        if (swIntStatus & bitmask) {
-                                do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
-                                return;
-                        }
-                }
-        }
-#endif
-
-        for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
-                if (intStatus & bitmask) {
-                        do_IRQ(EMMA2RH_IRQ_BASE + i);
-                        return;
-                }
-        }
-
-        intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
-            & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
-
-#ifdef EMMA2RH_GPIO_CASCADE
-        if (intStatus &
-            (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
-                u32 gpioIntStatus;
-                gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
-                    & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-                for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
-                        if (gpioIntStatus & bitmask) {
-                                do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
-                                return;
-                        }
-                }
-        }
-#endif
-
-        for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
-                if (intStatus & bitmask) {
-                        do_IRQ(EMMA2RH_IRQ_BASE + i);
-                        return;
-                }
-        }
-
-        intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
-            & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
-
-        for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
-                if (intStatus & bitmask) {
-                        do_IRQ(EMMA2RH_IRQ_BASE + i);
-                        return;
-                }
-        }
-}
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
deleted file mode 100644
index 96df37b7775..00000000000
--- a/arch/mips/emma2rh/common/irq_emma2rh.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- *  arch/mips/emma2rh/common/irq_emma2rh.c
- *      This file defines the irq handler for EMMA2RH.
- *
- *  Copyright (C) NEC Electronics Corporation 2005-2006
- *
- *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
- *
- *      Copyright 2001 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * EMMA2RH defines 64 IRQs.
- *
- * This file exports one function:
- *      emma2rh_irq_init(u32 irq_base);
- */
-
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-
-#include <asm/debug.h>
-
-#include <asm/emma2rh/emma2rh.h>
-
-/* number of total irqs supported by EMMA2RH */
-#define NUM_EMMA2RH_IRQ         96
-
-static int emma2rh_irq_base = -1;
-
-void ll_emma2rh_irq_enable(int);
-void ll_emma2rh_irq_disable(int);
-
-static void emma2rh_irq_enable(unsigned int irq)
-{
-        ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
-}
-
-static void emma2rh_irq_disable(unsigned int irq)
-{
-        ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
-}
-
-struct irq_chip emma2rh_irq_controller = {
-        .name = "emma2rh_irq",
-        .ack = emma2rh_irq_disable,
-        .mask = emma2rh_irq_disable,
-        .mask_ack = emma2rh_irq_disable,
-        .unmask = emma2rh_irq_enable,
-};
-
-void emma2rh_irq_init(u32 irq_base)
-{
-        u32 i;
-
-        for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
-                set_irq_chip_and_handler(i, &emma2rh_irq_controller,
-                                         handle_level_irq);
-
-        emma2rh_irq_base = irq_base;
-}
-
-void ll_emma2rh_irq_enable(int emma2rh_irq)
-{
-        u32 reg_value;
-        u32 reg_bitmask;
-        u32 reg_index;
-
-        reg_index = EMMA2RH_BHIF_INT_EN_0
-            + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
-            * (emma2rh_irq / 32);
-        reg_value = emma2rh_in32(reg_index);
-        reg_bitmask = 0x1 << (emma2rh_irq % 32);
-        db_assert((reg_value & reg_bitmask) == 0);
-        emma2rh_out32(reg_index, reg_value | reg_bitmask);
-}
-
-void ll_emma2rh_irq_disable(int emma2rh_irq)
-{
-        u32 reg_value;
-        u32 reg_bitmask;
-        u32 reg_index;
-
-        reg_index = EMMA2RH_BHIF_INT_EN_0
-            + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
-            * (emma2rh_irq / 32);
-        reg_value = emma2rh_in32(reg_index);
-        reg_bitmask = 0x1 << (emma2rh_irq % 32);
-        db_assert((reg_value & reg_bitmask) != 0);
-        emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
-}
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
deleted file mode 100644
index 6bcf6a06367..00000000000
--- a/arch/mips/emma2rh/markeins/irq.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  arch/mips/emma2rh/markeins/irq.c
- *      This file defines the irq handler for EMMA2RH.
- *
- *  Copyright (C) NEC Electronics Corporation 2004-2006
- *
- *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
- *
- *      Copyright 2001 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/delay.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/system.h>
-#include <asm/mipsregs.h>
-#include <asm/debug.h>
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-
-#include <asm/emma2rh/emma2rh.h>
-
-/*
- * IRQ mapping
- *
- *  0-7: 8 CPU interrupts
- *      0 -     software interrupt 0
- *      1 -     software interrupt 1
- *      2 -     most Vrc5477 interrupts are routed to this pin
- *      3 -     (optional) some other interrupts routed to this pin for debugg
- *      4 -     not used
- *      5 -     not used
- *      6 -     not used
- *      7 -     cpu timer (used by default)
- *
- */
-
-extern void emma2rh_sw_irq_init(u32 base);
-extern void emma2rh_gpio_irq_init(u32 base);
-extern void emma2rh_irq_init(u32 base);
-extern void emma2rh_irq_dispatch(void);
-
-static struct irqaction irq_cascade = {
-           .handler = no_action,
-           .flags = 0,
-           .mask = CPU_MASK_NONE,
-           .name = "cascade",
-           .dev_id = NULL,
-           .next = NULL,
-};
-
-void __init arch_init_irq(void)
-{
-        u32 reg;
-
-        db_run(printk("markeins_irq_setup invoked.\n"));
-
-        /* by default, interrupts are disabled. */
-        emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
-        emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
-        emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
-        emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
-        emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
-        emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
-        emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
-
-        clear_c0_status(0xff00);
-        set_c0_status(0x0400);
-
-#define GPIO_PCI (0xf<<15)
-        /* setup GPIO interrupt for PCI interface */
-        /* direction input */
-        reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
-        emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
-        /* disable interrupt */
-        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-        emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
-        /* level triggerd */
-        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
-        emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
-        reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
-        emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
-        /* interrupt clear */
-        emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
-
-        /* init all controllers */
-        emma2rh_irq_init(EMMA2RH_IRQ_BASE);
-        emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
-        emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
-        mips_cpu_irq_init();
-
-        /* setup cascade interrupts */
-        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
-        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
-        setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
-        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
-
-        if (pending & STATUSF_IP7)
-                do_IRQ(CPU_IRQ_BASE + 7);
-        else if (pending & STATUSF_IP2)
-                emma2rh_irq_dispatch();
-        else if (pending & STATUSF_IP1)
-                do_IRQ(CPU_IRQ_BASE + 1);
-        else if (pending & STATUSF_IP0)
-                do_IRQ(CPU_IRQ_BASE + 0);
-        else
-                spurious_interrupt();
-}
-
-
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
deleted file mode 100644
index fba5c156f47..00000000000
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- *  arch/mips/emma2rh/markeins/irq_markeins.c
- *      This file defines the irq handler for Mark-eins.
- *
- *  Copyright (C) NEC Electronics Corporation 2004-2006
- *
- *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
- *
- *      Copyright 2001 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-
-#include <asm/debug.h>
-#include <asm/emma2rh/emma2rh.h>
-
-static int emma2rh_sw_irq_base = -1;
-static int emma2rh_gpio_irq_base = -1;
-
-void ll_emma2rh_sw_irq_enable(int reg);
-void ll_emma2rh_sw_irq_disable(int reg);
-void ll_emma2rh_gpio_irq_enable(int reg);
-void ll_emma2rh_gpio_irq_disable(int reg);
-
-static void emma2rh_sw_irq_enable(unsigned int irq)
-{
-        ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
-}
-
-static void emma2rh_sw_irq_disable(unsigned int irq)
-{
-        ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
-}
-
-struct irq_chip emma2rh_sw_irq_controller = {
-        .name = "emma2rh_sw_irq",
-        .ack = emma2rh_sw_irq_disable,
-        .mask = emma2rh_sw_irq_disable,
-        .mask_ack = emma2rh_sw_irq_disable,
-        .unmask = emma2rh_sw_irq_enable,
-};
-
-void emma2rh_sw_irq_init(u32 irq_base)
-{
-        u32 i;
-
-        for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
-                set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
-                                         handle_level_irq);
-
-        emma2rh_sw_irq_base = irq_base;
-}
-
-void ll_emma2rh_sw_irq_enable(int irq)
-{
-        u32 reg;
-
-        db_assert(irq >= 0);
-        db_assert(irq < NUM_EMMA2RH_IRQ_SW);
-
-        reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
-        reg |= 1 << irq;
-        emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
-}
-
-void ll_emma2rh_sw_irq_disable(int irq)
-{
-        u32 reg;
-
-        db_assert(irq >= 0);
-        db_assert(irq < 32);
-
-        reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
-        reg &= ~(1 << irq);
-        emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
-}
-
-static void emma2rh_gpio_irq_enable(unsigned int irq)
-{
-        ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
-}
-
-static void emma2rh_gpio_irq_disable(unsigned int irq)
-{
-        ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
-}
-
-static void emma2rh_gpio_irq_ack(unsigned int irq)
-{
-        irq -= emma2rh_gpio_irq_base;
-        emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
-        ll_emma2rh_gpio_irq_disable(irq);
-}
-
-static void emma2rh_gpio_irq_end(unsigned int irq)
-{
-        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-                ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
-}
-
-struct irq_chip emma2rh_gpio_irq_controller = {
-        .name = "emma2rh_gpio_irq",
-        .ack = emma2rh_gpio_irq_ack,
-        .mask = emma2rh_gpio_irq_disable,
-        .mask_ack = emma2rh_gpio_irq_ack,
-        .unmask = emma2rh_gpio_irq_enable,
-        .end = emma2rh_gpio_irq_end,
-};
-
-void emma2rh_gpio_irq_init(u32 irq_base)
-{
-        u32 i;
-
-        for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
-                set_irq_chip(i, &emma2rh_gpio_irq_controller);
-
-        emma2rh_gpio_irq_base = irq_base;
-}
-
-void ll_emma2rh_gpio_irq_enable(int irq)
-{
-        u32 reg;
-
-        db_assert(irq >= 0);
-        db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
-
-        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-        reg |= 1 << irq;
-        emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
-}
-
-void ll_emma2rh_gpio_irq_disable(int irq)
-{
-        u32 reg;
-
-        db_assert(irq >= 0);
-        db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
-
-        reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-        reg &= ~(1 << irq);
-        emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
-}
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 49df8c4c9d2..bac4a960b24 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -558,39 +558,67 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
         __clear_bit(nr, addr);
 }
 
-#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
-
 /*
  * Return the bit position (0..63) of the most significant 1 bit in a word
  * Returns -1 if no 1 bit exists
  */
-static inline unsigned long __fls(unsigned long x)
+static inline unsigned long __fls(unsigned long word)
 {
-        int lz;
+        int num;
 
-        if (sizeof(x) == 4) {
+        if (BITS_PER_LONG == 32 &&
+            __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
                 __asm__(
                 "       .set    push                                    \n"
                 "       .set    mips32                                  \n"
                 "       clz     %0, %1                                  \n"
                 "       .set    pop                                     \n"
-                : "=r" (lz)
-                : "r" (x));
+                : "=r" (num)
+                : "r" (word));
 
-                return 31 - lz;
+                return 31 - num;
         }
 
-        BUG_ON(sizeof(x) != 8);
+        if (BITS_PER_LONG == 64 &&
+            __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
+                __asm__(
+                "       .set    push                                    \n"
+                "       .set    mips64                                  \n"
+                "       dclz    %0, %1                                  \n"
+                "       .set    pop                                     \n"
+                : "=r" (num)
+                : "r" (word));
 
-        __asm__(
-        "       .set    push                                            \n"
-        "       .set    mips64                                          \n"
-        "       dclz    %0, %1                                          \n"
-        "       .set    pop                                             \n"
-        : "=r" (lz)
-        : "r" (x));
+                return 63 - num;
+        }
+
+        num = BITS_PER_LONG - 1;
 
-        return 63 - lz;
+#if BITS_PER_LONG == 64
+        if (!(word & (~0ul << 32))) {
+                num -= 32;
+                word <<= 32;
+        }
+#endif
+        if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
+                num -= 16;
+                word <<= 16;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
+                num -= 8;
+                word <<= 8;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
+                num -= 4;
+                word <<= 4;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
+                num -= 2;
+                word <<= 2;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-1))))
+                num -= 1;
+        return num;
 }
 
 /*
@@ -612,23 +640,43 @@ static inline unsigned long __ffs(unsigned long word)
  * This is defined the same way as ffs.
  * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
  */
-static inline int fls(int word)
+static inline int fls(int x)
 {
-        __asm__("clz %0, %1" : "=r" (word) : "r" (word));
+        int r;
 
-        return 32 - word;
-}
+        if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
+                __asm__("clz %0, %1" : "=r" (x) : "r" (x));
 
-#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
-static inline int fls64(__u64 word)
-{
-        __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
+                return 32 - x;
+        }
 
-        return 64 - word;
+        r = 32;
+        if (!x)
+                return 0;
+        if (!(x & 0xffff0000u)) {
+                x <<= 16;
+                r -= 16;
+        }
+        if (!(x & 0xff000000u)) {
+                x <<= 8;
+                r -= 8;
+        }
+        if (!(x & 0xf0000000u)) {
+                x <<= 4;
+                r -= 4;
+        }
+        if (!(x & 0xc0000000u)) {
+                x <<= 2;
+                r -= 2;
+        }
+        if (!(x & 0x80000000u)) {
+                x <<= 1;
+                r -= 1;
+        }
+        return r;
 }
-#else
+
 #include <asm-generic/bitops/fls64.h>
-#endif
 
 /*
  * ffs - find first bit set.
@@ -646,16 +694,6 @@ static inline int ffs(int word)
         return fls(word & -word);
 }
 
-#else
-
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
-
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/find.h>
 
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 25b980c91e7..44437ed765e 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -29,6 +29,7 @@
 #define _BRK_THREADBP   11      /* For threads, user bp (used by debuggers) */
 #define BRK_BUG         512     /* Used by BUG() */
 #define BRK_KDB         513     /* Used in KDB_ENTER() */
+#define BRK_MEMU        514     /* Used by FPU emulator */
 #define BRK_MULOVF      1023    /* Multiply overflow */
 
 #endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index fe7dc2d59b6..2988d29a086 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -11,11 +11,19 @@
 #include <linux/compiler.h>
 #include <asm/types.h>
 
-#ifdef __GNUC__
+#if defined(__MIPSEB__)
+# define __BIG_ENDIAN
+#elif defined(__MIPSEL__)
+# define __LITTLE_ENDIAN
+#else
+# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#define __SWAB_64_THRU_32__
 
 #ifdef CONFIG_CPU_MIPSR2
 
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
 {
         __asm__(
         "       wsbh    %0, %1                  \n"
@@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
 
         return x;
 }
-#define __arch__swab16(x)       ___arch__swab16(x)
+#define __arch_swab16 __arch_swab16
 
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 {
         __asm__(
         "       wsbh    %0, %1                  \n"
@@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
 
         return x;
 }
-#define __arch__swab32(x)       ___arch__swab32(x)
+#define __arch_swab32 __arch_swab32
 
 #ifdef CONFIG_CPU_MIPS64_R2
-
-static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
 {
         __asm__(
         "       dsbh    %0, %1                  \n"
@@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
 
         return x;
 }
-
-#define __arch__swab64(x)       ___arch__swab64(x)
-
+#define __arch_swab64 __arch_swab64
 #endif /* CONFIG_CPU_MIPS64_R2 */
 
 #endif /* CONFIG_CPU_MIPSR2 */
 
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#endif /* __GNUC__ */
-
-#if defined(__MIPSEB__)
-#  include <linux/byteorder/big_endian.h>
-#elif defined(__MIPSEL__)
-#  include <linux/byteorder/little_endian.h>
-#else
-#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
+#include <linux/byteorder.h>
 
 #endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 5ea701fc342..12d12dfe73c 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -141,6 +141,8 @@
 #define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2)
 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
+#define cpu_has_mips_r  (cpu_has_mips32r1 | cpu_has_mips32r2 | \
+                         cpu_has_mips64r1 | cpu_has_mips64r2)
 
 #ifndef cpu_has_dsp
 #define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h
deleted file mode 100644
index 6983b6ff0af..00000000000
--- a/arch/mips/include/asm/ds1286.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Machine dependent access functions for RTC registers.
- *
- * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef _ASM_DS1286_H
-#define _ASM_DS1286_H
-
-#include <ds1286.h>
-
-#endif /* _ASM_DS1286_H */
diff --git a/arch/mips/include/asm/emma2rh/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 6a1af0af51e..30aea91de62 100644
--- a/arch/mips/include/asm/emma2rh/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -1,5 +1,5 @@
 /*
- *  include/asm-mips/emma2rh/emma2rh.h
+ *  arch/mips/include/asm/emma/emma2rh.h
  *      This file is EMMA2RH common header.
  *
  *  Copyright (C) NEC Electronics Corporation 2005-2006
@@ -21,8 +21,8 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#ifndef __ASM_EMMA2RH_EMMA2RH_H
-#define __ASM_EMMA2RH_EMMA2RH_H
+#ifndef __ASM_EMMA_EMMA2RH_H
+#define __ASM_EMMA_EMMA2RH_H
 
 #include <irq.h>
 
@@ -206,7 +206,6 @@ static inline void emma2rh_out32(u32 offset, u32 val)
 static inline u32 emma2rh_in32(u32 offset)
 {
         u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
-        emma2rh_sync();
         return val;
 }
 
@@ -219,7 +218,6 @@ static inline void emma2rh_out16(u32 offset, u16 val)
 static inline u16 emma2rh_in16(u32 offset)
 {
         u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
-        emma2rh_sync();
         return val;
 }
 
@@ -232,7 +230,6 @@ static inline void emma2rh_out8(u32 offset, u8 val)
 static inline u8 emma2rh_in8(u32 offset)
 {
         u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
-        emma2rh_sync();
         return val;
 }
 
@@ -324,10 +321,10 @@ static inline u8 emma2rh_in8(u32 offset)
 /*
  * include the board dependent part
  */
-#if defined(CONFIG_MARKEINS)
-#include <asm/emma2rh/markeins.h>
+#ifdef CONFIG_NEC_MARKEINS
+#include <asm/emma/markeins.h>
 #else
 #error "Unknown EMMA2RH board!"
 #endif
 
-#endif /* __ASM_EMMA2RH_EMMA2RH_H */
+#endif /* __ASM_EMMA_EMMA2RH_H */
diff --git a/arch/mips/include/asm/emma2rh/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 973b0628490..973b0628490 100644
--- a/arch/mips/include/asm/emma2rh/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index 2731c38bd7a..e5189572956 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -23,6 +23,9 @@
 #ifndef _ASM_FPU_EMULATOR_H
 #define _ASM_FPU_EMULATOR_H
 
+#include <asm/break.h>
+#include <asm/inst.h>
+
 struct mips_fpu_emulator_stats {
         unsigned int emulated;
         unsigned int loads;
@@ -34,4 +37,18 @@ struct mips_fpu_emulator_stats {
 
 extern struct mips_fpu_emulator_stats fpuemustats;
 
+extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
+        unsigned long cpc);
+extern int do_dsemulret(struct pt_regs *xcp);
+
+/*
+ * Instruction inserted following the badinst to further tag the sequence
+ */
+#define BD_COOKIE 0x0000bd36    /* tne $0, $0 with baggage */
+
+/*
+ * Break instruction with special math emu break code set
+ */
+#define BREAK_MATH (0x0000000d | (BRK_MEMU << 16))
+
 #endif /* _ASM_FPU_EMULATOR_H */
diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h
deleted file mode 100644
index f44852e9a96..00000000000
--- a/arch/mips/include/asm/m48t35.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
- */
-#ifndef _ASM_M48T35_H
-#define _ASM_M48T35_H
-
-#include <linux/spinlock.h>
-
-extern spinlock_t rtc_lock;
-
-struct m48t35_rtc {
-        volatile u8     pad[0x7ff8];    /* starts at 0x7ff8 */
-        volatile u8     control;
-        volatile u8     sec;
-        volatile u8     min;
-        volatile u8     hour;
-        volatile u8     day;
-        volatile u8     date;
-        volatile u8     month;
-        volatile u8     year;
-};
-
-#define M48T35_RTC_SET          0x80
-#define M48T35_RTC_STOPPED      0x80
-#define M48T35_RTC_READ         0x40
-
-#endif /* _ASM_M48T35_H */
diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h
new file mode 100644
index 00000000000..ea6aa143b78
--- /dev/null
+++ b/arch/mips/include/asm/mach-lemote/pci.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
+ *
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General
+ * Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be
+ * useful, but WITHOUT ANY WARRANTY; without even the implied
+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ * PURPOSE.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#ifndef _LEMOTE_PCI_H_
+#define _LEMOTE_PCI_H_
+
+#define LOONGSON2E_PCI_MEM_START        0x14000000UL
+#define LOONGSON2E_PCI_MEM_END          0x1fffffffUL
+#define LOONGSON2E_PCI_IO_START         0x00004000UL
+#define LOONGSON2E_IO_PORT_BASE         0x1fd00000UL
+
+#endif /* !_LEMOTE_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h
new file mode 100644
index 00000000000..8de0eb9c98a
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/gpio.h
@@ -0,0 +1,172 @@
+/*
+ *  gpio.h: GPIO Support for PNX833X.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
+#define __ASM_MIPS_MACH_PNX833X_GPIO_H
+
+/* BIG FAT WARNING: races danger!
+   No protections exist here. Current users are only early init code,
+   when locking is not needed because no cuncurency yet exists there,
+   and GPIO IRQ dispatcher, which does locking.
+   However, if many uses will ever happen, proper locking will be needed
+   - including locking between different uses
+*/
+
+#include "pnx833x.h"
+
+#define SET_REG_BIT(reg, bit)           do { (reg |= (1 << (bit))); } while (0)
+#define CLEAR_REG_BIT(reg, bit)         do { (reg &= ~(1 << (bit))); } while (0)
+
+/* Initialize GPIO to a known state */
+static inline void pnx833x_gpio_init(void)
+{
+        PNX833X_PIO_DIR = 0;
+        PNX833X_PIO_DIR2 = 0;
+        PNX833X_PIO_SEL = 0;
+        PNX833X_PIO_SEL2 = 0;
+        PNX833X_PIO_INT_EDGE = 0;
+        PNX833X_PIO_INT_HI = 0;
+        PNX833X_PIO_INT_LO = 0;
+
+        /* clear any GPIO interrupt requests */
+        PNX833X_PIO_INT_CLEAR = 0xffff;
+        PNX833X_PIO_INT_CLEAR = 0;
+        PNX833X_PIO_INT_ENABLE = 0;
+}
+
+/* Select GPIO direction for a pin */
+static inline void pnx833x_gpio_select_input(unsigned int pin)
+{
+        if (pin < 32)
+                CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
+        else
+                CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
+}
+static inline void pnx833x_gpio_select_output(unsigned int pin)
+{
+        if (pin < 32)
+                SET_REG_BIT(PNX833X_PIO_DIR, pin);
+        else
+                SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
+}
+
+/* Select GPIO or alternate function for a pin */
+static inline void pnx833x_gpio_select_function_io(unsigned int pin)
+{
+        if (pin < 32)
+                CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
+        else
+                CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
+}
+static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
+{
+        if (pin < 32)
+                SET_REG_BIT(PNX833X_PIO_SEL, pin);
+        else
+                SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
+}
+
+/* Read GPIO pin */
+static inline int pnx833x_gpio_read(unsigned int pin)
+{
+        if (pin < 32)
+                return (PNX833X_PIO_IN >> pin) & 1;
+        else
+                return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
+}
+
+/* Write GPIO pin */
+static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
+{
+        if (pin < 32) {
+                if (val)
+                        SET_REG_BIT(PNX833X_PIO_OUT, pin);
+                else
+                        CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
+        } else {
+                if (val)
+                        SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
+                else
+                        CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
+        }
+}
+
+/* Configure GPIO interrupt */
+#define GPIO_INT_NONE           0
+#define GPIO_INT_LEVEL_LOW      1
+#define GPIO_INT_LEVEL_HIGH     2
+#define GPIO_INT_EDGE_RISING    3
+#define GPIO_INT_EDGE_FALLING   4
+#define GPIO_INT_EDGE_BOTH      5
+static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
+{
+        switch (when) {
+        case GPIO_INT_LEVEL_LOW:
+                CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
+                CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
+                SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
+                break;
+        case GPIO_INT_LEVEL_HIGH:
+                CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
+                SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
+                CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
+                break;
+        case GPIO_INT_EDGE_RISING:
+                SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
+                SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
+                CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
+                break;
+        case GPIO_INT_EDGE_FALLING:
+                SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
+                CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
+                SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
+                break;
+        case GPIO_INT_EDGE_BOTH:
+                SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
+                SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
+                SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
+                break;
+        default:
+                CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
+                CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
+                CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
+                break;
+        }
+}
+
+/* Enable/disable GPIO interrupt */
+static inline void pnx833x_gpio_enable_irq(unsigned int pin)
+{
+        SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
+}
+static inline void pnx833x_gpio_disable_irq(unsigned int pin)
+{
+        CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
+}
+
+/* Clear GPIO interrupt request */
+static inline void pnx833x_gpio_clear_irq(unsigned int pin)
+{
+        SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
+        CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
+}
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
new file mode 100644
index 00000000000..657f089b172
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
@@ -0,0 +1,126 @@
+
+/*
+ *  irq.h: IRQ mappings for PNX833X.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
+#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
+/*
+ * The "IRQ numbers" are completely virtual.
+ *
+ * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
+ * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
+ * numbers 49..64 for (virtual) GPIO interrupts.
+ *
+ * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
+ * connected to PIC, which uses core hardware interrupt 2, and also
+ * a timer interrupt through hardware interrupt 5.
+ * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
+ * numbers 65..80 for (virtual) GPIO interrupts.
+ *
+ */
+#include <irq.h>
+
+#define PNX833X_TIMER_IRQ                               (MIPS_CPU_IRQ_BASE + 7)
+
+/* Interrupts supported by PIC */
+#define PNX833X_PIC_I2C0_INT                    (PNX833X_PIC_IRQ_BASE +  1)
+#define PNX833X_PIC_I2C1_INT                    (PNX833X_PIC_IRQ_BASE +  2)
+#define PNX833X_PIC_UART0_INT                   (PNX833X_PIC_IRQ_BASE +  3)
+#define PNX833X_PIC_UART1_INT                   (PNX833X_PIC_IRQ_BASE +  4)
+#define PNX833X_PIC_TS_IN0_DV_INT               (PNX833X_PIC_IRQ_BASE +  5)
+#define PNX833X_PIC_TS_IN0_DMA_INT              (PNX833X_PIC_IRQ_BASE +  6)
+#define PNX833X_PIC_GPIO_INT                    (PNX833X_PIC_IRQ_BASE +  7)
+#define PNX833X_PIC_AUDIO_DEC_INT               (PNX833X_PIC_IRQ_BASE +  8)
+#define PNX833X_PIC_VIDEO_DEC_INT               (PNX833X_PIC_IRQ_BASE +  9)
+#define PNX833X_PIC_CONFIG_INT                  (PNX833X_PIC_IRQ_BASE + 10)
+#define PNX833X_PIC_AOI_INT                             (PNX833X_PIC_IRQ_BASE + 11)
+#define PNX833X_PIC_SYNC_INT                    (PNX833X_PIC_IRQ_BASE + 12)
+#define PNX8330_PIC_SPU_INT                             (PNX833X_PIC_IRQ_BASE + 13)
+#define PNX8335_PIC_SATA_INT                    (PNX833X_PIC_IRQ_BASE + 13)
+#define PNX833X_PIC_OSD_INT                             (PNX833X_PIC_IRQ_BASE + 14)
+#define PNX833X_PIC_DISP1_INT                   (PNX833X_PIC_IRQ_BASE + 15)
+#define PNX833X_PIC_DEINTERLACER_INT    (PNX833X_PIC_IRQ_BASE + 16)
+#define PNX833X_PIC_DISPLAY2_INT                (PNX833X_PIC_IRQ_BASE + 17)
+#define PNX833X_PIC_VC_INT                              (PNX833X_PIC_IRQ_BASE + 18)
+#define PNX833X_PIC_SC_INT                              (PNX833X_PIC_IRQ_BASE + 19)
+#define PNX833X_PIC_IDE_INT                             (PNX833X_PIC_IRQ_BASE + 20)
+#define PNX833X_PIC_IDE_DMA_INT                 (PNX833X_PIC_IRQ_BASE + 21)
+#define PNX833X_PIC_TS_IN1_DV_INT               (PNX833X_PIC_IRQ_BASE + 22)
+#define PNX833X_PIC_TS_IN1_DMA_INT              (PNX833X_PIC_IRQ_BASE + 23)
+#define PNX833X_PIC_SGDX_DMA_INT                (PNX833X_PIC_IRQ_BASE + 24)
+#define PNX833X_PIC_TS_OUT_INT                  (PNX833X_PIC_IRQ_BASE + 25)
+#define PNX833X_PIC_IR_INT                              (PNX833X_PIC_IRQ_BASE + 26)
+#define PNX833X_PIC_VMSP1_INT                   (PNX833X_PIC_IRQ_BASE + 27)
+#define PNX833X_PIC_VMSP2_INT                   (PNX833X_PIC_IRQ_BASE + 28)
+#define PNX833X_PIC_PIBC_INT                    (PNX833X_PIC_IRQ_BASE + 29)
+#define PNX833X_PIC_TS_IN0_TRD_INT              (PNX833X_PIC_IRQ_BASE + 30)
+#define PNX833X_PIC_SGDX_TPD_INT                (PNX833X_PIC_IRQ_BASE + 31)
+#define PNX833X_PIC_USB_INT                             (PNX833X_PIC_IRQ_BASE + 32)
+#define PNX833X_PIC_TS_IN1_TRD_INT              (PNX833X_PIC_IRQ_BASE + 33)
+#define PNX833X_PIC_CLOCK_INT                   (PNX833X_PIC_IRQ_BASE + 34)
+#define PNX833X_PIC_SGDX_PARSER_INT             (PNX833X_PIC_IRQ_BASE + 35)
+#define PNX833X_PIC_VMSP_DMA_INT                (PNX833X_PIC_IRQ_BASE + 36)
+
+#if defined(CONFIG_SOC_PNX8335)
+#define PNX8335_PIC_MIU_INT                                     (PNX833X_PIC_IRQ_BASE + 37)
+#define PNX8335_PIC_AVCHIP_IRQ_INT                      (PNX833X_PIC_IRQ_BASE + 38)
+#define PNX8335_PIC_SYNC_HD_INT                         (PNX833X_PIC_IRQ_BASE + 39)
+#define PNX8335_PIC_DISP_HD_INT                         (PNX833X_PIC_IRQ_BASE + 40)
+#define PNX8335_PIC_DISP_SCALER_INT                     (PNX833X_PIC_IRQ_BASE + 41)
+#define PNX8335_PIC_OSD_HD1_INT                         (PNX833X_PIC_IRQ_BASE + 42)
+#define PNX8335_PIC_DTL_WRITER_Y_INT            (PNX833X_PIC_IRQ_BASE + 43)
+#define PNX8335_PIC_DTL_WRITER_C_INT            (PNX833X_PIC_IRQ_BASE + 44)
+#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT       (PNX833X_PIC_IRQ_BASE + 45)
+#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT       (PNX833X_PIC_IRQ_BASE + 46)
+#define PNX8335_PIC_DENC_TTX_INT                        (PNX833X_PIC_IRQ_BASE + 47)
+#define PNX8335_PIC_MMI_SIF0_INT                        (PNX833X_PIC_IRQ_BASE + 48)
+#define PNX8335_PIC_MMI_SIF1_INT                        (PNX833X_PIC_IRQ_BASE + 49)
+#define PNX8335_PIC_MMI_CDMMU_INT                       (PNX833X_PIC_IRQ_BASE + 50)
+#define PNX8335_PIC_PIBCS_INT                           (PNX833X_PIC_IRQ_BASE + 51)
+#define PNX8335_PIC_ETHERNET_INT                        (PNX833X_PIC_IRQ_BASE + 52)
+#define PNX8335_PIC_VMSP1_0_INT                         (PNX833X_PIC_IRQ_BASE + 53)
+#define PNX8335_PIC_VMSP1_1_INT                         (PNX833X_PIC_IRQ_BASE + 54)
+#define PNX8335_PIC_VMSP1_DMA_INT                       (PNX833X_PIC_IRQ_BASE + 55)
+#define PNX8335_PIC_TDGR_DE_INT                         (PNX833X_PIC_IRQ_BASE + 56)
+#define PNX8335_PIC_IR1_IRQ_INT                         (PNX833X_PIC_IRQ_BASE + 57)
+#endif
+
+/* GPIO interrupts */
+#define PNX833X_GPIO_0_INT                      (PNX833X_GPIO_IRQ_BASE +  0)
+#define PNX833X_GPIO_1_INT                      (PNX833X_GPIO_IRQ_BASE +  1)
+#define PNX833X_GPIO_2_INT                      (PNX833X_GPIO_IRQ_BASE +  2)
+#define PNX833X_GPIO_3_INT                      (PNX833X_GPIO_IRQ_BASE +  3)
+#define PNX833X_GPIO_4_INT                      (PNX833X_GPIO_IRQ_BASE +  4)
+#define PNX833X_GPIO_5_INT                      (PNX833X_GPIO_IRQ_BASE +  5)
+#define PNX833X_GPIO_6_INT                      (PNX833X_GPIO_IRQ_BASE +  6)
+#define PNX833X_GPIO_7_INT                      (PNX833X_GPIO_IRQ_BASE +  7)
+#define PNX833X_GPIO_8_INT                      (PNX833X_GPIO_IRQ_BASE +  8)
+#define PNX833X_GPIO_9_INT                      (PNX833X_GPIO_IRQ_BASE +  9)
+#define PNX833X_GPIO_10_INT                     (PNX833X_GPIO_IRQ_BASE + 10)
+#define PNX833X_GPIO_11_INT                     (PNX833X_GPIO_IRQ_BASE + 11)
+#define PNX833X_GPIO_12_INT                     (PNX833X_GPIO_IRQ_BASE + 12)
+#define PNX833X_GPIO_13_INT                     (PNX833X_GPIO_IRQ_BASE + 13)
+#define PNX833X_GPIO_14_INT                     (PNX833X_GPIO_IRQ_BASE + 14)
+#define PNX833X_GPIO_15_INT                     (PNX833X_GPIO_IRQ_BASE + 15)
+
+#endif
+
diff --git a/arch/mips/include/asm/mach-pnx833x/irq.h b/arch/mips/include/asm/mach-pnx833x/irq.h
new file mode 100644
index 00000000000..745114b1d8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/irq.h
@@ -0,0 +1,53 @@
+/*
+ *  irq.h: IRQ mappings for PNX833X.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
+#define __ASM_MIPS_MACH_PNX833X_IRQ_H
+/*
+ * The "IRQ numbers" are completely virtual.
+ *
+ * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
+ * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
+ * numbers 49..64 for (virtual) GPIO interrupts.
+ *
+ * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
+ * connected to PIC, which uses core hardware interrupt 2, and also
+ * a timer interrupt through hardware interrupt 5.
+ * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
+ * numbers 65..80 for (virtual) GPIO interrupts.
+ *
+ */
+#if defined(CONFIG_SOC_PNX8335)
+        #define PNX833X_PIC_NUM_IRQ                     58
+#else
+        #define PNX833X_PIC_NUM_IRQ                     37
+#endif
+
+#define MIPS_CPU_NUM_IRQ                                8
+#define PNX833X_GPIO_NUM_IRQ                    16
+
+#define MIPS_CPU_IRQ_BASE                               0
+#define PNX833X_PIC_IRQ_BASE                    (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
+#define PNX833X_GPIO_IRQ_BASE                   (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
+#define NR_IRQS                                                 (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
new file mode 100644
index 00000000000..100f52870e3
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
@@ -0,0 +1,202 @@
+/*
+ *  pnx833x.h: Register mappings for PNX833X.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
+#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
+
+/* All regs are accessed in KSEG1 */
+#define PNX833X_BASE            (0xa0000000ul + 0x17E00000ul)
+
+#define PNX833X_REG(offs)       (*((volatile unsigned long *)(PNX833X_BASE + offs)))
+
+/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */
+
+/* Read access to multibit fields */
+#define PNX833X_BIT(val, reg, field)    ((val) & PNX833X_##reg##_##field)
+#define PNX833X_REGBIT(reg, field)      PNX833X_BIT(PNX833X_##reg, reg, field)
+
+/* Use PNX833X_FIELD to extract a field from val */
+#define PNX_FIELD(cpu, val, reg, field) \
+                (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
+                        PNX##cpu##_##reg##_##field##_SHIFT)
+#define PNX833X_FIELD(val, reg, field)  PNX_FIELD(833X, val, reg, field)
+#define PNX8330_FIELD(val, reg, field)  PNX_FIELD(8330, val, reg, field)
+#define PNX8335_FIELD(val, reg, field)  PNX_FIELD(8335, val, reg, field)
+
+/* Use PNX833X_REGFIELD to extract a field from a register */
+#define PNX833X_REGFIELD(reg, field)    PNX833X_FIELD(PNX833X_##reg, reg, field)
+#define PNX8330_REGFIELD(reg, field)    PNX8330_FIELD(PNX8330_##reg, reg, field)
+#define PNX8335_REGFIELD(reg, field)    PNX8335_FIELD(PNX8335_##reg, reg, field)
+
+
+#define PNX_WRITEFIELD(cpu, val, reg, field) \
+        (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
+                                                ((val) << PNX##cpu##_##reg##_##field##_SHIFT))
+#define PNX833X_WRITEFIELD(val, reg, field) \
+                                        PNX_WRITEFIELD(833X, val, reg, field)
+#define PNX8330_WRITEFIELD(val, reg, field) \
+                                        PNX_WRITEFIELD(8330, val, reg, field)
+#define PNX8335_WRITEFIELD(val, reg, field) \
+                                        PNX_WRITEFIELD(8335, val, reg, field)
+
+
+/* Macros to detect CPU type */
+
+#define PNX833X_CONFIG_MODULE_ID                PNX833X_REG(0x7FFC)
+#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK    0x0000f000
+#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT   12
+#define PNX8330_CONFIG_MODULE_MAJREV            4
+#define PNX8335_CONFIG_MODULE_MAJREV            5
+#define CPU_IS_PNX8330  (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
+                                        PNX8330_CONFIG_MODULE_MAJREV)
+#define CPU_IS_PNX8335  (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
+                                        PNX8335_CONFIG_MODULE_MAJREV)
+
+
+
+#define PNX833X_RESET_CONTROL           PNX833X_REG(0x8004)
+#define PNX833X_RESET_CONTROL_2         PNX833X_REG(0x8014)
+
+#define PNX833X_PIC_REG(offs)           PNX833X_REG(0x01000 + (offs))
+#define PNX833X_PIC_INT_PRIORITY        PNX833X_PIC_REG(0x0)
+#define PNX833X_PIC_INT_SRC             PNX833X_PIC_REG(0x4)
+#define PNX833X_PIC_INT_SRC_INT_SRC_MASK        0x00000FF8ul    /* bits 11:3 */
+#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT       3
+#define PNX833X_PIC_INT_REG(irq)        PNX833X_PIC_REG(0x10 + 4*(irq))
+
+#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
+#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET      0x00000002ul    /* bit 1 */
+#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK  0x00000018ul    /* bits 4:3 */
+#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
+
+#define PNX8335_CLOCK_PLL_CPU_CTL               PNX833X_REG(0x9020)
+#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK     0x1f
+#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT    0
+
+#define PNX833X_CONFIG_MUX              PNX833X_REG(0x7004)
+#define PNX833X_CONFIG_MUX_IDE_MUX      0x00000080              /* bit 7 */
+
+#define PNX8330_CONFIG_POLYFUSE_7       PNX833X_REG(0x7040)
+#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK        0x00180000
+#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT       19
+
+#define PNX833X_PIO_IN          PNX833X_REG(0xF000)
+#define PNX833X_PIO_OUT         PNX833X_REG(0xF004)
+#define PNX833X_PIO_DIR         PNX833X_REG(0xF008)
+#define PNX833X_PIO_SEL         PNX833X_REG(0xF014)
+#define PNX833X_PIO_INT_EDGE    PNX833X_REG(0xF020)
+#define PNX833X_PIO_INT_HI      PNX833X_REG(0xF024)
+#define PNX833X_PIO_INT_LO      PNX833X_REG(0xF028)
+#define PNX833X_PIO_INT_STATUS  PNX833X_REG(0xFFE0)
+#define PNX833X_PIO_INT_ENABLE  PNX833X_REG(0xFFE4)
+#define PNX833X_PIO_INT_CLEAR   PNX833X_REG(0xFFE8)
+#define PNX833X_PIO_IN2         PNX833X_REG(0xF05C)
+#define PNX833X_PIO_OUT2        PNX833X_REG(0xF060)
+#define PNX833X_PIO_DIR2        PNX833X_REG(0xF064)
+#define PNX833X_PIO_SEL2        PNX833X_REG(0xF068)
+
+#define PNX833X_UART0_PORTS_START       (PNX833X_BASE + 0xB000)
+#define PNX833X_UART0_PORTS_END         (PNX833X_BASE + 0xBFFF)
+#define PNX833X_UART1_PORTS_START       (PNX833X_BASE + 0xC000)
+#define PNX833X_UART1_PORTS_END         (PNX833X_BASE + 0xCFFF)
+
+#define PNX833X_USB_PORTS_START         (PNX833X_BASE + 0x19000)
+#define PNX833X_USB_PORTS_END           (PNX833X_BASE + 0x19FFF)
+
+#define PNX833X_CONFIG_USB              PNX833X_REG(0x7008)
+
+#define PNX833X_I2C0_PORTS_START        (PNX833X_BASE + 0xD000)
+#define PNX833X_I2C0_PORTS_END          (PNX833X_BASE + 0xDFFF)
+#define PNX833X_I2C1_PORTS_START        (PNX833X_BASE + 0xE000)
+#define PNX833X_I2C1_PORTS_END          (PNX833X_BASE + 0xEFFF)
+
+#define PNX833X_IDE_PORTS_START         (PNX833X_BASE + 0x1A000)
+#define PNX833X_IDE_PORTS_END           (PNX833X_BASE + 0x1AFFF)
+#define PNX833X_IDE_MODULE_ID           PNX833X_REG(0x1AFFC)
+
+#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK    0xFFFF0000
+#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT   16
+#define PNX833X_IDE_MODULE_ID_VALUE             0xA009
+
+
+#define PNX833X_MIU_SEL0                        PNX833X_REG(0x2004)
+#define PNX833X_MIU_SEL0_TIMING         PNX833X_REG(0x2008)
+#define PNX833X_MIU_SEL1                        PNX833X_REG(0x200C)
+#define PNX833X_MIU_SEL1_TIMING         PNX833X_REG(0x2010)
+#define PNX833X_MIU_SEL2                        PNX833X_REG(0x2014)
+#define PNX833X_MIU_SEL2_TIMING         PNX833X_REG(0x2018)
+#define PNX833X_MIU_SEL3                        PNX833X_REG(0x201C)
+#define PNX833X_MIU_SEL3_TIMING         PNX833X_REG(0x2020)
+
+#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK   (1 << 14)
+#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT  14
+
+#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
+#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT        7
+
+#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK    (0xF << 9)
+#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT   9
+
+#define PNX833X_MIU_CONFIG_SPI          PNX833X_REG(0x2000)
+
+#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK      (0xFF << 3)
+#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT     3
+
+#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
+#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT        2
+
+#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
+#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT        1
+
+#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK        (1 << 0)
+#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT       0
+
+#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \
+   (PNX833X_MIU_CONFIG_SPI =                                            \
+    ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) |                 \
+    ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) |       \
+    ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) |       \
+    ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT))
+
+#define PNX8335_IP3902_PORTS_START              (PNX833X_BASE + 0x2F000)
+#define PNX8335_IP3902_PORTS_END                (PNX833X_BASE + 0x2FFFF)
+#define PNX8335_IP3902_MODULE_ID                PNX833X_REG(0x2FFFC)
+
+#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK         0xFFFF0000
+#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT        16
+#define PNX8335_IP3902_MODULE_ID_VALUE                  0x3902
+
+ /* I/O location(gets remapped)*/
+#define PNX8335_NAND_BASE           0x18000000
+/* I/O location with CLE high */
+#define PNX8335_NAND_CLE_MASK   0x00100000
+/* I/O location with ALE high */
+#define PNX8335_NAND_ALE_MASK   0x00010000
+
+#define PNX8335_SATA_PORTS_START        (PNX833X_BASE + 0x2E000)
+#define PNX8335_SATA_PORTS_END          (PNX833X_BASE + 0x2EFFF)
+#define PNX8335_SATA_MODULE_ID          PNX833X_REG(0x2EFFC)
+
+#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK   0xFFFF0000
+#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT  16
+#define PNX8335_SATA_MODULE_ID_VALUE            0xA099
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
new file mode 100644
index 00000000000..82cd1e97bc2
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H
+#define __ASM_MIPS_MACH_PNX833X_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
index c8e554eafce..b5cf6457305 100644
--- a/arch/mips/include/asm/mach-rc32434/gpio.h
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned
 extern unsigned get_434_reg(unsigned reg_offs);
 extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
 extern unsigned char get_latch_u5(void);
+extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
+extern void rb532_gpio_set_istat(int bit, unsigned gpio);
 
 #endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index 79e8ef67d0d..f25a8491670 100644
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -40,12 +40,14 @@
 #define BTCS            0x010040
 #define BTCOMPARE       0x010044
 #define GPIOBASE        0x050000
-#define GPIOCFG         0x050004
-#define GPIOD           0x050008
-#define GPIOILEVEL      0x05000C
-#define GPIOISTAT       0x050010
-#define GPIONMIEN       0x050014
-#define IMASK6          0x038038
+/* Offsets relative to GPIOBASE */
+#define GPIOFUNC        0x00
+#define GPIOCFG         0x04
+#define GPIOD           0x08
+#define GPIOILEVEL      0x0C
+#define GPIOISTAT       0x10
+#define GPIONMIEN       0x14
+#define IMASK6          0x38
 #define LO_WPX          (1 << 0)
 #define LO_ALE          (1 << 1)
 #define LO_CLE          (1 << 2)
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
new file mode 100644
index 00000000000..5e6912fdd0e
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_MACH_TX49XX_MANGLE_PORT_H
+#define __ASM_MACH_TX49XX_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  (port)
+#define __swizzle_addr_w(port)  (port)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+#define ioswabb(a, x)           (x)
+#define __mem_ioswabb(a, x)     (x)
+#if defined(CONFIG_TOSHIBA_RBTX4939) && \
+        (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \
+        defined(__BIG_ENDIAN)
+#define NEEDS_TXX9_IOSWABW
+extern u16 (*ioswabw)(volatile u16 *a, u16 x);
+extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x);
+#else
+#define ioswabw(a, x)           le16_to_cpu(x)
+#define __mem_ioswabw(a, x)     (x)
+#endif
+#define ioswabl(a, x)           le32_to_cpu(x)
+#define __mem_ioswabl(a, x)     (x)
+#define ioswabq(a, x)           le64_to_cpu(x)
+#define __mem_ioswabq(a, x)     (x)
+
+#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 979866000da..9316324d070 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -192,6 +192,7 @@
 #define PM_16M          0x01ffe000
 #define PM_64M          0x07ffe000
 #define PM_256M         0x1fffe000
+#define PM_1G           0x7fffe000
 
 #endif
 
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index de6d09ebbd8..e2e09b2cd26 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -98,6 +98,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "R5000 "
 #elif defined CONFIG_CPU_R5432
 #define MODULE_PROC_FAMILY "R5432 "
+#elif defined CONFIG_CPU_R5500
+#define MODULE_PROC_FAMILY "R5500 "
 #elif defined CONFIG_CPU_R6000
 #define MODULE_PROC_FAMILY "R6000 "
 #elif defined CONFIG_CPU_NEVADA
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 9c22571b160..813abd16255 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -80,25 +80,25 @@ enum pt_watch_style {
         pt_watch_style_mips64
 };
 struct mips32_watch_regs {
-        uint32_t watchlo[8];
+        unsigned int watchlo[8];
         /* Lower 16 bits of watchhi. */
-        uint16_t watchhi[8];
+        unsigned short watchhi[8];
         /* Valid mask and I R W bits.
          * bit 0 -- 1 if W bit is usable.
          * bit 1 -- 1 if R bit is usable.
          * bit 2 -- 1 if I bit is usable.
          * bits 3 - 11 -- Valid watchhi mask bits.
          */
-        uint16_t watch_masks[8];
+        unsigned short watch_masks[8];
         /* The number of valid watch register pairs.  */
-        uint32_t num_valid;
+        unsigned int num_valid;
 } __attribute__((aligned(8)));
 
 struct mips64_watch_regs {
-        uint64_t watchlo[8];
-        uint16_t watchhi[8];
-        uint16_t watch_masks[8];
-        uint32_t num_valid;
+        unsigned long long watchlo[8];
+        unsigned short watchhi[8];
+        unsigned short watch_masks[8];
+        unsigned int num_valid;
 } __attribute__((aligned(8)));
 
 struct pt_watch_regs {
@@ -116,6 +116,7 @@ struct pt_watch_regs {
 
 #include <linux/compiler.h>
 #include <linux/linkage.h>
+#include <linux/types.h>
 #include <asm/isadep.h>
 
 struct task_struct;
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index d3bd5c5aa2e..9601ea95054 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void)
 /*
  * Initialize the count register as a clocksource
  */
-#ifdef CONFIG_CEVT_R4K
+#ifdef CONFIG_CSRC_R4K
 extern int init_mips_clocksource(void);
 #else
 static inline int init_mips_clocksource(void)
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 4316a3e5767..9cde0090cbf 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -86,4 +86,9 @@ void txx9_iocled_init(unsigned long baseaddr,
                       int basenum, unsigned int num, int lowactive,
                       const char *color, char **deftriggers);
 
+/* 7SEG LED */
+void txx9_7segled_init(unsigned int num,
+                       void (*putc)(unsigned int pos, unsigned char val));
+int txx9_7segled_putc(unsigned int pos, char c);
+
 #endif /* __ASM_TXX9_GENERIC_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d9da7112aaf..b1372c27f13 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_CPU_R4X00)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R5000)         += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R6000)         += r6000_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R5432)         += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R5500)         += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R8000)         += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_RM7000)        += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_RM9000)        += r4k_fpu.o r4k_switch.o
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0cf15457eca..c9207b5fd92 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -286,11 +286,12 @@ static inline int __cpu_has_fpu(void)
 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
                 | MIPS_CPU_COUNTER)
 
-static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
+static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 {
         switch (c->processor_id & 0xff00) {
         case PRID_IMP_R2000:
                 c->cputype = CPU_R2000;
+                __cpu_name[cpu] = "R2000";
                 c->isa_level = MIPS_CPU_ISA_I;
                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
                              MIPS_CPU_NOFPUEX;
@@ -299,13 +300,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 c->tlbsize = 64;
                 break;
         case PRID_IMP_R3000:
-                if ((c->processor_id & 0xff) == PRID_REV_R3000A)
-                        if (cpu_has_confreg())
+                if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
+                        if (cpu_has_confreg()) {
                                 c->cputype = CPU_R3081E;
-                        else
+                                __cpu_name[cpu] = "R3081";
+                        } else {
                                 c->cputype = CPU_R3000A;
-                else
+                                __cpu_name[cpu] = "R3000A";
+                        }
+                        break;
+                } else {
                         c->cputype = CPU_R3000;
+                        __cpu_name[cpu] = "R3000";
+                }
                 c->isa_level = MIPS_CPU_ISA_I;
                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
                              MIPS_CPU_NOFPUEX;
@@ -315,15 +322,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R4000:
                 if (read_c0_config() & CONF_SC) {
-                        if ((c->processor_id & 0xff) >= PRID_REV_R4400)
+                        if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
                                 c->cputype = CPU_R4400PC;
-                        else
+                                __cpu_name[cpu] = "R4400PC";
+                        } else {
                                 c->cputype = CPU_R4000PC;
+                                __cpu_name[cpu] = "R4000PC";
+                        }
                 } else {
-                        if ((c->processor_id & 0xff) >= PRID_REV_R4400)
+                        if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
                                 c->cputype = CPU_R4400SC;
-                        else
+                                __cpu_name[cpu] = "R4400SC";
+                        } else {
                                 c->cputype = CPU_R4000SC;
+                                __cpu_name[cpu] = "R4000SC";
+                        }
                 }
 
                 c->isa_level = MIPS_CPU_ISA_III;
@@ -336,25 +349,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 switch (c->processor_id & 0xf0) {
                 case PRID_REV_VR4111:
                         c->cputype = CPU_VR4111;
+                        __cpu_name[cpu] = "NEC VR4111";
                         break;
                 case PRID_REV_VR4121:
                         c->cputype = CPU_VR4121;
+                        __cpu_name[cpu] = "NEC VR4121";
                         break;
                 case PRID_REV_VR4122:
-                        if ((c->processor_id & 0xf) < 0x3)
+                        if ((c->processor_id & 0xf) < 0x3) {
                                 c->cputype = CPU_VR4122;
-                        else
+                                __cpu_name[cpu] = "NEC VR4122";
+                        } else {
                                 c->cputype = CPU_VR4181A;
+                                __cpu_name[cpu] = "NEC VR4181A";
+                        }
                         break;
                 case PRID_REV_VR4130:
-                        if ((c->processor_id & 0xf) < 0x4)
+                        if ((c->processor_id & 0xf) < 0x4) {
                                 c->cputype = CPU_VR4131;
-                        else
+                                __cpu_name[cpu] = "NEC VR4131";
+                        } else {
                                 c->cputype = CPU_VR4133;
+                                __cpu_name[cpu] = "NEC VR4133";
+                        }
                         break;
                 default:
                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
                         c->cputype = CPU_VR41XX;
+                        __cpu_name[cpu] = "NEC Vr41xx";
                         break;
                 }
                 c->isa_level = MIPS_CPU_ISA_III;
@@ -363,6 +385,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R4300:
                 c->cputype = CPU_R4300;
+                __cpu_name[cpu] = "R4300";
                 c->isa_level = MIPS_CPU_ISA_III;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_LLSC;
@@ -370,6 +393,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R4600:
                 c->cputype = CPU_R4600;
+                __cpu_name[cpu] = "R4600";
                 c->isa_level = MIPS_CPU_ISA_III;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_LLSC;
@@ -384,6 +408,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                  * it's c0_prid id number with the TX3900.
                  */
                 c->cputype = CPU_R4650;
+                __cpu_name[cpu] = "R4650";
                 c->isa_level = MIPS_CPU_ISA_III;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
                 c->tlbsize = 48;
@@ -395,25 +420,26 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 
                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
                         c->cputype = CPU_TX3927;
+                        __cpu_name[cpu] = "TX3927";
                         c->tlbsize = 64;
                 } else {
                         switch (c->processor_id & 0xff) {
                         case PRID_REV_TX3912:
                                 c->cputype = CPU_TX3912;
+                                __cpu_name[cpu] = "TX3912";
                                 c->tlbsize = 32;
                                 break;
                         case PRID_REV_TX3922:
                                 c->cputype = CPU_TX3922;
+                                __cpu_name[cpu] = "TX3922";
                                 c->tlbsize = 64;
                                 break;
-                        default:
-                                c->cputype = CPU_UNKNOWN;
-                                break;
                         }
                 }
                 break;
         case PRID_IMP_R4700:
                 c->cputype = CPU_R4700;
+                __cpu_name[cpu] = "R4700";
                 c->isa_level = MIPS_CPU_ISA_III;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_LLSC;
@@ -421,6 +447,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_TX49:
                 c->cputype = CPU_TX49XX;
+                __cpu_name[cpu] = "R49XX";
                 c->isa_level = MIPS_CPU_ISA_III;
                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
                 if (!(c->processor_id & 0x08))
@@ -429,6 +456,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R5000:
                 c->cputype = CPU_R5000;
+                __cpu_name[cpu] = "R5000";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_LLSC;
@@ -436,6 +464,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R5432:
                 c->cputype = CPU_R5432;
+                __cpu_name[cpu] = "R5432";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
@@ -443,6 +472,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R5500:
                 c->cputype = CPU_R5500;
+                __cpu_name[cpu] = "R5500";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
@@ -450,6 +480,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_NEVADA:
                 c->cputype = CPU_NEVADA;
+                __cpu_name[cpu] = "Nevada";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
@@ -457,6 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R6000:
                 c->cputype = CPU_R6000;
+                __cpu_name[cpu] = "R6000";
                 c->isa_level = MIPS_CPU_ISA_II;
                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
                              MIPS_CPU_LLSC;
@@ -464,6 +496,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R6000A:
                 c->cputype = CPU_R6000A;
+                __cpu_name[cpu] = "R6000A";
                 c->isa_level = MIPS_CPU_ISA_II;
                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
                              MIPS_CPU_LLSC;
@@ -471,6 +504,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_RM7000:
                 c->cputype = CPU_RM7000;
+                __cpu_name[cpu] = "RM7000";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_LLSC;
@@ -486,6 +520,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_RM9000:
                 c->cputype = CPU_RM9000;
+                __cpu_name[cpu] = "RM9000";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                              MIPS_CPU_LLSC;
@@ -500,6 +535,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R8000:
                 c->cputype = CPU_R8000;
+                __cpu_name[cpu] = "RM8000";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -508,6 +544,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R10000:
                 c->cputype = CPU_R10000;
+                __cpu_name[cpu] = "R10000";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -517,6 +554,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R12000:
                 c->cputype = CPU_R12000;
+                __cpu_name[cpu] = "R12000";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -526,6 +564,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_R14000:
                 c->cputype = CPU_R14000;
+                __cpu_name[cpu] = "R14000";
                 c->isa_level = MIPS_CPU_ISA_IV;
                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -535,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_LOONGSON2:
                 c->cputype = CPU_LOONGSON2;
+                __cpu_name[cpu] = "ICT Loongson-2";
                 c->isa_level = MIPS_CPU_ISA_III;
                 c->options = R4K_OPTS |
                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
@@ -652,21 +692,24 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 
 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 {
+        int ok;
+
         /* MIPS32 or MIPS64 compliant CPU.  */
         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 
         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 
-        /* Read Config registers.  */
-        if (!decode_config0(c))
-                return;                 /* actually worth a panic() */
-        if (!decode_config1(c))
-                return;
-        if (!decode_config2(c))
-                return;
-        if (!decode_config3(c))
-                return;
+        ok = decode_config0(c);                 /* Read Config registers.  */
+        BUG_ON(!ok);                            /* Arch spec violation!  */
+        if (ok)
+                ok = decode_config1(c);
+        if (ok)
+                ok = decode_config2(c);
+        if (ok)
+                ok = decode_config3(c);
+
+        mips_probe_watch_registers(c);
 }
 
 #ifdef CONFIG_CPU_MIPSR2
@@ -675,52 +718,62 @@ extern void spram_config(void);
 static inline void spram_config(void) {}
 #endif
 
-static inline void cpu_probe_mips(struct cpuinfo_mips *c)
+static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
-        mips_probe_watch_registers(c);
         switch (c->processor_id & 0xff00) {
         case PRID_IMP_4KC:
                 c->cputype = CPU_4KC;
+                __cpu_name[cpu] = "MIPS 4Kc";
                 break;
         case PRID_IMP_4KEC:
                 c->cputype = CPU_4KEC;
+                __cpu_name[cpu] = "MIPS 4KEc";
                 break;
         case PRID_IMP_4KECR2:
                 c->cputype = CPU_4KEC;
+                __cpu_name[cpu] = "MIPS 4KEc";
                 break;
         case PRID_IMP_4KSC:
         case PRID_IMP_4KSD:
                 c->cputype = CPU_4KSC;
+                __cpu_name[cpu] = "MIPS 4KSc";
                 break;
         case PRID_IMP_5KC:
                 c->cputype = CPU_5KC;
+                __cpu_name[cpu] = "MIPS 5Kc";
                 break;
         case PRID_IMP_20KC:
                 c->cputype = CPU_20KC;
+                __cpu_name[cpu] = "MIPS 20Kc";
                 break;
         case PRID_IMP_24K:
         case PRID_IMP_24KE:
                 c->cputype = CPU_24K;
+                __cpu_name[cpu] = "MIPS 24Kc";
                 break;
         case PRID_IMP_25KF:
                 c->cputype = CPU_25KF;
+                __cpu_name[cpu] = "MIPS 25Kc";
                 break;
         case PRID_IMP_34K:
                 c->cputype = CPU_34K;
+                __cpu_name[cpu] = "MIPS 34Kc";
                 break;
         case PRID_IMP_74K:
                 c->cputype = CPU_74K;
+                __cpu_name[cpu] = "MIPS 74Kc";
                 break;
         case PRID_IMP_1004K:
                 c->cputype = CPU_1004K;
+                __cpu_name[cpu] = "MIPS 1004Kc";
                 break;
         }
 
         spram_config();
 }
 
-static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
+static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
         switch (c->processor_id & 0xff00) {
@@ -729,23 +782,31 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
                 switch ((c->processor_id >> 24) & 0xff) {
                 case 0:
                         c->cputype = CPU_AU1000;
+                        __cpu_name[cpu] = "Au1000";
                         break;
                 case 1:
                         c->cputype = CPU_AU1500;
+                        __cpu_name[cpu] = "Au1500";
                         break;
                 case 2:
                         c->cputype = CPU_AU1100;
+                        __cpu_name[cpu] = "Au1100";
                         break;
                 case 3:
                         c->cputype = CPU_AU1550;
+                        __cpu_name[cpu] = "Au1550";
                         break;
                 case 4:
                         c->cputype = CPU_AU1200;
-                        if (2 == (c->processor_id & 0xff))
+                        __cpu_name[cpu] = "Au1200";
+                        if ((c->processor_id & 0xff) == 2) {
                                 c->cputype = CPU_AU1250;
+                                __cpu_name[cpu] = "Au1250";
+                        }
                         break;
                 case 5:
                         c->cputype = CPU_AU1210;
+                        __cpu_name[cpu] = "Au1210";
                         break;
                 default:
                         panic("Unknown Au Core!");
@@ -755,154 +816,67 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
         }
 }
 
-static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
+static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
 
         switch (c->processor_id & 0xff00) {
         case PRID_IMP_SB1:
                 c->cputype = CPU_SB1;
+                __cpu_name[cpu] = "SiByte SB1";
                 /* FPU in pass1 is known to have issues. */
                 if ((c->processor_id & 0xff) < 0x02)
                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
                 break;
         case PRID_IMP_SB1A:
                 c->cputype = CPU_SB1A;
+                __cpu_name[cpu] = "SiByte SB1A";
                 break;
         }
 }
 
-static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
+static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
         switch (c->processor_id & 0xff00) {
         case PRID_IMP_SR71000:
                 c->cputype = CPU_SR71000;
+                __cpu_name[cpu] = "Sandcraft SR71000";
                 c->scache.ways = 8;
                 c->tlbsize = 64;
                 break;
         }
 }
 
-static inline void cpu_probe_nxp(struct cpuinfo_mips *c)
+static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
         switch (c->processor_id & 0xff00) {
         case PRID_IMP_PR4450:
                 c->cputype = CPU_PR4450;
+                __cpu_name[cpu] = "Philips PR4450";
                 c->isa_level = MIPS_CPU_ISA_M32R1;
                 break;
-        default:
-                panic("Unknown NXP Core!"); /* REVISIT: die? */
-                break;
         }
 }
 
-
-static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
         switch (c->processor_id & 0xff00) {
         case PRID_IMP_BCM3302:
                 c->cputype = CPU_BCM3302;
+                __cpu_name[cpu] = "Broadcom BCM3302";
                 break;
         case PRID_IMP_BCM4710:
                 c->cputype = CPU_BCM4710;
-                break;
-        default:
-                c->cputype = CPU_UNKNOWN;
+                __cpu_name[cpu] = "Broadcom BCM4710";
                 break;
         }
 }
 
 const char *__cpu_name[NR_CPUS];
 
-/*
- * Name a CPU
- */
-static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
-{
-        const char *name = NULL;
-
-        switch (c->cputype) {
-        case CPU_UNKNOWN:       name = "unknown"; break;
-        case CPU_R2000:         name = "R2000"; break;
-        case CPU_R3000:         name = "R3000"; break;
-        case CPU_R3000A:        name = "R3000A"; break;
-        case CPU_R3041:         name = "R3041"; break;
-        case CPU_R3051:         name = "R3051"; break;
-        case CPU_R3052:         name = "R3052"; break;
-        case CPU_R3081:         name = "R3081"; break;
-        case CPU_R3081E:        name = "R3081E"; break;
-        case CPU_R4000PC:       name = "R4000PC"; break;
-        case CPU_R4000SC:       name = "R4000SC"; break;
-        case CPU_R4000MC:       name = "R4000MC"; break;
-        case CPU_R4200:         name = "R4200"; break;
-        case CPU_R4400PC:       name = "R4400PC"; break;
-        case CPU_R4400SC:       name = "R4400SC"; break;
-        case CPU_R4400MC:       name = "R4400MC"; break;
-        case CPU_R4600:         name = "R4600"; break;
-        case CPU_R6000:         name = "R6000"; break;
-        case CPU_R6000A:        name = "R6000A"; break;
-        case CPU_R8000:         name = "R8000"; break;
-        case CPU_R10000:        name = "R10000"; break;
-        case CPU_R12000:        name = "R12000"; break;
-        case CPU_R14000:        name = "R14000"; break;
-        case CPU_R4300:         name = "R4300"; break;
-        case CPU_R4650:         name = "R4650"; break;
-        case CPU_R4700:         name = "R4700"; break;
-        case CPU_R5000:         name = "R5000"; break;
-        case CPU_R5000A:        name = "R5000A"; break;
-        case CPU_R4640:         name = "R4640"; break;
-        case CPU_NEVADA:        name = "Nevada"; break;
-        case CPU_RM7000:        name = "RM7000"; break;
-        case CPU_RM9000:        name = "RM9000"; break;
-        case CPU_R5432:         name = "R5432"; break;
-        case CPU_4KC:           name = "MIPS 4Kc"; break;
-        case CPU_5KC:           name = "MIPS 5Kc"; break;
-        case CPU_R4310:         name = "R4310"; break;
-        case CPU_SB1:           name = "SiByte SB1"; break;
-        case CPU_SB1A:          name = "SiByte SB1A"; break;
-        case CPU_TX3912:        name = "TX3912"; break;
-        case CPU_TX3922:        name = "TX3922"; break;
-        case CPU_TX3927:        name = "TX3927"; break;
-        case CPU_AU1000:        name = "Au1000"; break;
-        case CPU_AU1500:        name = "Au1500"; break;
-        case CPU_AU1100:        name = "Au1100"; break;
-        case CPU_AU1550:        name = "Au1550"; break;
-        case CPU_AU1200:        name = "Au1200"; break;
-        case CPU_AU1210:        name = "Au1210"; break;
-        case CPU_AU1250:        name = "Au1250"; break;
-        case CPU_4KEC:          name = "MIPS 4KEc"; break;
-        case CPU_4KSC:          name = "MIPS 4KSc"; break;
-        case CPU_VR41XX:        name = "NEC Vr41xx"; break;
-        case CPU_R5500:         name = "R5500"; break;
-        case CPU_TX49XX:        name = "TX49xx"; break;
-        case CPU_20KC:          name = "MIPS 20Kc"; break;
-        case CPU_24K:           name = "MIPS 24K"; break;
-        case CPU_25KF:          name = "MIPS 25Kf"; break;
-        case CPU_34K:           name = "MIPS 34K"; break;
-        case CPU_1004K:         name = "MIPS 1004K"; break;
-        case CPU_74K:           name = "MIPS 74K"; break;
-        case CPU_VR4111:        name = "NEC VR4111"; break;
-        case CPU_VR4121:        name = "NEC VR4121"; break;
-        case CPU_VR4122:        name = "NEC VR4122"; break;
-        case CPU_VR4131:        name = "NEC VR4131"; break;
-        case CPU_VR4133:        name = "NEC VR4133"; break;
-        case CPU_VR4181:        name = "NEC VR4181"; break;
-        case CPU_VR4181A:       name = "NEC VR4181A"; break;
-        case CPU_SR71000:       name = "Sandcraft SR71000"; break;
-        case CPU_BCM3302:       name = "Broadcom BCM3302"; break;
-        case CPU_BCM4710:       name = "Broadcom BCM4710"; break;
-        case CPU_PR4450:        name = "Philips PR4450"; break;
-        case CPU_LOONGSON2:     name = "ICT Loongson-2"; break;
-        default:
-                BUG();
-        }
-
-        return name;
-}
-
 __cpuinit void cpu_probe(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
@@ -915,30 +889,31 @@ __cpuinit void cpu_probe(void)
         c->processor_id = read_c0_prid();
         switch (c->processor_id & 0xff0000) {
         case PRID_COMP_LEGACY:
-                cpu_probe_legacy(c);
+                cpu_probe_legacy(c, cpu);
                 break;
         case PRID_COMP_MIPS:
-                cpu_probe_mips(c);
+                cpu_probe_mips(c, cpu);
                 break;
         case PRID_COMP_ALCHEMY:
-                cpu_probe_alchemy(c);
+                cpu_probe_alchemy(c, cpu);
                 break;
         case PRID_COMP_SIBYTE:
-                cpu_probe_sibyte(c);
+                cpu_probe_sibyte(c, cpu);
                 break;
         case PRID_COMP_BROADCOM:
-                cpu_probe_broadcom(c);
+                cpu_probe_broadcom(c, cpu);
                 break;
         case PRID_COMP_SANDCRAFT:
-                cpu_probe_sandcraft(c);
+                cpu_probe_sandcraft(c, cpu);
                 break;
         case PRID_COMP_NXP:
-                cpu_probe_nxp(c);
+                cpu_probe_nxp(c, cpu);
                 break;
-        default:
-                c->cputype = CPU_UNKNOWN;
         }
 
+        BUG_ON(!__cpu_name[cpu]);
+        BUG_ON(c->cputype == CPU_UNKNOWN);
+
         /*
          * Platform code can force the cpu type to optimize code
          * generation. In that case be sure the cpu type is correctly
@@ -958,8 +933,6 @@ __cpuinit void cpu_probe(void)
                 }
         }
 
-        __cpu_name[cpu] = cpu_to_name(c);
-
         if (cpu_has_mips_r2)
                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
         else
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 86e026f067b..74fb74583b4 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -27,7 +27,7 @@ int __init init_mips_clocksource(void)
         if (!cpu_has_counter || !mips_hpt_frequency)
                 return -ENXIO;
 
-        /* Calclate a somewhat reasonable rating value */
+        /* Calculate a somewhat reasonable rating value */
         clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
 
         clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 5e75a316f6b..759f68066b5 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -180,7 +180,7 @@ bad_stack:
          * The system call does not exist in this kernel
          */
 illegal_syscall:
-        li      v0, -ENOSYS                     # error
+        li      v0, ENOSYS                      # error
         sw      v0, PT_R2(sp)
         li      t0, 1                           # set error flag
         sw      t0, PT_R7(sp)
@@ -293,7 +293,7 @@ bad_alignment:
         jr      t2
         /* Unreached */
 
-einval: li      v0, -EINVAL
+einval: li      v0, -ENOSYS
         jr      ra
         END(sys_syscall)
 
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 3d58204c9d4..a9e17161899 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -117,7 +117,7 @@ syscall_trace_entry:
 
 illegal_syscall:
         /* This also isn't a 64-bit syscall, throw an error.  */
-        li      v0, -ENOSYS                     # error
+        li      v0, ENOSYS                      # error
         sd      v0, PT_R2(sp)
         li      t0, 1                           # set error flag
         sd      t0, PT_R7(sp)
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 16f8edfe5cd..4430a1f8fdf 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -601,8 +601,8 @@ static int __init debugfs_mips(void)
         struct dentry *d;
 
         d = debugfs_create_dir("mips", NULL);
-        if (IS_ERR(d))
-                return PTR_ERR(d);
+        if (!d)
+                return -ENOMEM;
         mips_debugfs_dir = d;
         return 0;
 }
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 7b59cfb7e60..8bf88faf5af 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -163,8 +163,10 @@ static void stop_this_cpu(void *dummy)
          * Remove this CPU:
          */
         cpu_clear(smp_processor_id(), cpu_online_map);
-        local_irq_enable();     /* May need to service _machine_restart IPI */
-        for (;;);               /* Wait if available. */
+        for (;;) {
+                if (cpu_wait)
+                        (*cpu_wait)();          /* Wait if available. */
+        }
 }
 
 void smp_send_stop(void)
@@ -193,12 +195,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 /* preload SMP state for boot cpu */
 void __devinit smp_prepare_boot_cpu(void)
 {
-        /*
-         * This assumes that bootup is always handled by the processor
-         * with the logic and physical number 0.
-         */
-        __cpu_number_map[0] = 0;
-        __cpu_logical_map[0] = 0;
         cpu_set(0, phys_cpu_present_map);
         cpu_set(0, cpu_online_map);
         cpu_set(0, cpu_callin_map);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 80b9e070c20..353056110f2 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -32,6 +32,7 @@
 #include <asm/cpu.h>
 #include <asm/dsp.h>
 #include <asm/fpu.h>
+#include <asm/fpu_emulator.h>
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/module.h>
@@ -722,6 +723,21 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
                 die_if_kernel("Kernel bug detected", regs);
                 force_sig(SIGTRAP, current);
                 break;
+        case BRK_MEMU:
+                /*
+                 * Address errors may be deliberately induced by the FPU
+                 * emulator to retake control of the CPU after executing the
+                 * instruction in the delay slot of an emulated branch.
+                 *
+                 * Terminate if exception was recognized as a delay slot return
+                 * otherwise handle as normal.
+                 */
+                if (do_dsemulret(regs))
+                        return;
+
+                die_if_kernel("Math emu break/trap", regs);
+                force_sig(SIGTRAP, current);
+                break;
         default:
                 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
                 die_if_kernel(b, regs);
@@ -1555,6 +1571,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
 #ifdef CONFIG_64BIT
         unsigned long uncached_ebase = TO_UNCAC(ebase);
 #endif
+        if (cpu_has_mips_r2)
+                ebase += (read_c0_ebase() & 0x3ffff000);
 
         if (!addr)
                 panic(panic_null_cerr);
@@ -1588,8 +1606,11 @@ void __init trap_init(void)
 
         if (cpu_has_veic || cpu_has_vint)
                 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
-        else
+        else {
                 ebase = CAC_BASE;
+                if (cpu_has_mips_r2)
+                        ebase += (read_c0_ebase() & 0x3ffff000);
+        }
 
         per_cpu_trap_init();
 
@@ -1697,11 +1718,11 @@ void __init trap_init(void)
 
         if (cpu_has_vce)
                 /* Special exception: R4[04]00 uses also the divec space. */
-                memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
+                memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
         else if (cpu_has_4kex)
-                memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
+                memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
         else
-                memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
+                memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
 
         signal_init();
 #ifdef CONFIG_MIPS32_COMPAT
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index c327b21bca8..bf4c4a979ab 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -499,22 +499,10 @@ sigill:
 
 asmlinkage void do_ade(struct pt_regs *regs)
 {
-        extern int do_dsemulret(struct pt_regs *);
         unsigned int __user *pc;
         mm_segment_t seg;
 
         /*
-         * Address errors may be deliberately induced by the FPU emulator to
-         * retake control of the CPU after executing the instruction in the
-         * delay slot of an emulated branch.
-         */
-        /* Terminate if exception was recognized as a delay slot return */
-        if (do_dsemulret(regs))
-                return;
-
-        /* Otherwise handle as normal */
-
-        /*
          * Did we catch a fault trying to load an instruction?
          * Or are we running in MIPS16 mode?
          */
@@ -560,12 +548,12 @@ static int __init debugfs_unaligned(void)
                 return -ENODEV;
         d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
                                mips_debugfs_dir, &unaligned_instructions);
-        if (IS_ERR(d))
-                return PTR_ERR(d);
+        if (!d)
+                return -ENOMEM;
         d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
                                mips_debugfs_dir, &unaligned_action);
-        if (IS_ERR(d))
-                return PTR_ERR(d);
+        if (!d)
+                return -ENOMEM;
         return 0;
 }
 __initcall(debugfs_unaligned);
diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c
index c1e41f15cc7..8be03a8e1ad 100644
--- a/arch/mips/lemote/lm2e/pci.c
+++ b/arch/mips/lemote/lm2e/pci.c
@@ -30,19 +30,20 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <asm/mips-boards/bonito64.h>
+#include <asm/mach-lemote/pci.h>
 
 extern struct pci_ops bonito64_pci_ops;
 
 static struct resource loongson2e_pci_mem_resource = {
         .name   = "LOONGSON2E PCI MEM",
-        .start  = 0x14000000UL,
-        .end    = 0x1fffffffUL,
+        .start  = LOONGSON2E_PCI_MEM_START,
+        .end    = LOONGSON2E_PCI_MEM_END,
         .flags  = IORESOURCE_MEM,
 };
 
 static struct resource loongson2e_pci_io_resource = {
         .name   = "LOONGSON2E PCI IO MEM",
-        .start  = 0x00004000UL,
+        .start  = LOONGSON2E_PCI_IO_START,
         .end    = IO_SPACE_LIMIT,
         .flags  = IORESOURCE_IO,
 };
@@ -82,6 +83,12 @@ static void __init ict_pcimap(void)
 static int __init pcibios_init(void)
 {
         ict_pcimap();
+
+        loongson2e_pci_controller.io_map_base =
+            (unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE,
+                                    loongson2e_pci_io_resource.end -
+                                    loongson2e_pci_io_resource.start + 1);
+
         register_pci_controller(&loongson2e_pci_controller);
 
         return 0;
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c
index 2cc6745991a..ebd6ceaef2f 100644
--- a/arch/mips/lemote/lm2e/setup.c
+++ b/arch/mips/lemote/lm2e/setup.c
@@ -34,6 +34,7 @@
 #include <asm/mc146818-time.h>
 #include <asm/time.h>
 #include <asm/wbflush.h>
+#include <asm/mach-lemote/pci.h>
 
 #ifdef CONFIG_VT
 #include <linux/console.h>
@@ -42,12 +43,6 @@
 
 extern void mips_reboot_setup(void);
 
-#ifdef CONFIG_64BIT
-#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p)))
-#else
-#define PTR_PAD(p) (p)
-#endif
-
 unsigned long cpu_clock_freq;
 unsigned long bus_clock;
 unsigned int memsize;
@@ -80,8 +75,8 @@ static void wbflush_loongson2e(void)
 
 void __init plat_mem_setup(void)
 {
-        set_io_port_base(PTR_PAD(0xbfd00000));
-
+        set_io_port_base((unsigned long)ioremap(LOONGSON2E_IO_PORT_BASE,
+                                IO_SPACE_LIMIT - LOONGSON2E_PCI_IO_START + 1));
         mips_reboot_setup();
 
         __wbflush = wbflush_loongson2e;
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 8810dfb915d..dbcf6511b74 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_CPU_R4300)		+= dump_tlb.o
 obj-$(CONFIG_CPU_R4X00)         += dump_tlb.o
 obj-$(CONFIG_CPU_R5000)         += dump_tlb.o
 obj-$(CONFIG_CPU_R5432)         += dump_tlb.o
+obj-$(CONFIG_CPU_R5500)         += dump_tlb.o
 obj-$(CONFIG_CPU_R6000)         +=
 obj-$(CONFIG_CPU_R8000)         +=
 obj-$(CONFIG_CPU_RM7000)        += dump_tlb.o
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 465ff0ec85b..779821cd54a 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -25,6 +25,7 @@ static inline const char *msk2str(unsigned int mask)
         case PM_16M:    return "16Mb";
         case PM_64M:    return "64Mb";
         case PM_256M:   return "256Mb";
+        case PM_1G:     return "1Gb";
 #endif
         }
         return "";
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index b08fc65c13a..890f77927d6 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -48,7 +48,6 @@
 #include <asm/branch.h>
 
 #include "ieee754.h"
-#include "dsemul.h"
 
 /* Strap kernel emulator for full MIPS IV emulation */
 
@@ -346,9 +345,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         /* cop control register rd -> gpr[rt] */
                         u32 value;
 
-                        if (ir == CP1UNDEF) {
-                                return do_dsemulret(xcp);
-                        }
                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
                                 value = ctx->fcr31;
                                 value = (value & ~0x3) | mips_rm[value & 0x3];
@@ -1299,12 +1295,12 @@ static int __init debugfs_fpuemu(void)
         if (!mips_debugfs_dir)
                 return -ENODEV;
         dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
-        if (IS_ERR(dir))
-                return PTR_ERR(dir);
+        if (!dir)
+                return -ENOMEM;
         for (i = 0; i < ARRAY_SIZE(vars); i++) {
                 d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
-                if (IS_ERR(d))
-                        return PTR_ERR(d);
+                if (!d)
+                        return -ENOMEM;
         }
         return 0;
 }
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index 653e325849e..df7b9d928ef 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -18,7 +18,6 @@
 #include <asm/fpu_emulator.h>
 
 #include "ieee754.h"
-#include "dsemul.h"
 
 /* Strap kernel emulator for full MIPS IV emulation */
 
@@ -94,7 +93,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
                 return SIGBUS;
 
         err = __put_user(ir, &fr->emul);
-        err |= __put_user((mips_instruction)BADINST, &fr->badinst);
+        err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst);
         err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
         err |= __put_user(cpc, &fr->epc);
 
@@ -130,13 +129,13 @@ int do_dsemulret(struct pt_regs *xcp)
         /*
          * Do some sanity checking on the stackframe:
          *
-         *  - Is the instruction pointed to by the EPC an BADINST?
+         *  - Is the instruction pointed to by the EPC an BREAK_MATH?
          *  - Is the following memory word the BD_COOKIE?
          */
         err = __get_user(insn, &fr->badinst);
         err |= __get_user(cookie, &fr->cookie);
 
-        if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) {
+        if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
                 fpuemustats.errors++;
                 return 0;
         }
diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h
deleted file mode 100644
index 091f0e76730..00000000000
--- a/arch/mips/math-emu/dsemul.h
+++ /dev/null
@@ -1,17 +0,0 @@
-extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc);
-extern int do_dsemulret(struct pt_regs *xcp);
-
-/* Instruction which will always cause an address error */
-#define AdELOAD 0x8c000001      /* lw $0,1($0) */
-/* Instruction which will plainly cause a CP1 exception when FPU is disabled */
-#define CP1UNDEF 0x44400001    /* cfc1 $0,$0 undef  */
-
-/* Instruction inserted following the badinst to further tag the sequence */
-#define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */
-
-/* Setup which instruction to use for trampoline */
-#ifdef STANDALONE_EMULATOR
-#define BADINST CP1UNDEF
-#else
-#define BADINST AdELOAD
-#endif
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 44e8dd8106b..95ba32b5b72 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CPU_R4300)		+= c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R4X00)         += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R5000)         += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R5432)         += c-r4k.o cex-gen.o tlb-r4k.o
+obj-$(CONFIG_CPU_R5500)         += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R8000)         += c-r4k.o cex-gen.o tlb-r8k.o
 obj-$(CONFIG_CPU_RM7000)        += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_RM9000)        += c-r4k.o cex-gen.o tlb-r4k.o
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 891312f8e5a..5b98d0e731c 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -324,7 +324,6 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
                 if (cpu_is_noncoherent_r10000(dev))
                         __dma_sync((unsigned long)page_address(sg_page(sg)),
                                    sg->length, direction);
-                plat_unmap_dma_mem(sg->dma_address);
         }
 }
 
@@ -342,7 +341,6 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele
                 if (!plat_device_is_coherent(dev))
                         __dma_sync((unsigned long)page_address(sg_page(sg)),
                                    sg->length, direction);
-                plat_unmap_dma_mem(sg->dma_address);
         }
 }
 
diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c
index 1f602a110e1..13adb578211 100644
--- a/arch/mips/mm/sc-ip22.c
+++ b/arch/mips/mm/sc-ip22.c
@@ -161,7 +161,7 @@ static inline int __init indy_sc_probe(void)
 
 /* XXX Check with wje if the Indy caches can differenciate between
    writeback + invalidate and just invalidate.  */
-struct bcache_ops indy_sc_ops = {
+static struct bcache_ops indy_sc_ops = {
         .bc_enable = indy_sc_enable,
         .bc_disable = indy_sc_disable,
         .bc_wback_inv = indy_sc_wback_invalidate,
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index 96236bf3383..df9e526312a 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -22,9 +22,9 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 
-#include <asm-mips/addrspace.h>
-#include <asm-mips/mips-boards/launch.h>
-#include <asm-mips/mipsmtregs.h>
+#include <asm/addrspace.h>
+#include <asm/mips-boards/launch.h>
+#include <asm/mipsmtregs.h>
 
 int amon_cpu_avail(int cpu)
 {
diff --git a/arch/mips/nxp/pnx833x/common/Makefile b/arch/mips/nxp/pnx833x/common/Makefile
new file mode 100644
index 00000000000..4a16f3b503b
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/Makefile
@@ -0,0 +1,3 @@
+obj-y := interrupts.o platform.o prom.o setup.o reset.o
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/nxp/pnx833x/common/interrupts.c
new file mode 100644
index 00000000000..30533ba200e
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/interrupts.c
@@ -0,0 +1,380 @@
+/*
+ *  interrupts.c: Interrupt mappings for PNX833X.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+#include <linux/interrupt.h>
+#include <asm/mipsregs.h>
+#include <asm/irq_cpu.h>
+#include <irq.h>
+#include <irq-mapping.h>
+#include <gpio.h>
+
+static int mips_cpu_timer_irq;
+
+static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
+{
+    0, /* unused */
+    4, /* PNX833X_PIC_I2C0_INT                 1 */
+    4, /* PNX833X_PIC_I2C1_INT                 2 */
+    1, /* PNX833X_PIC_UART0_INT                3 */
+    1, /* PNX833X_PIC_UART1_INT                4 */
+    6, /* PNX833X_PIC_TS_IN0_DV_INT            5 */
+    6, /* PNX833X_PIC_TS_IN0_DMA_INT           6 */
+    7, /* PNX833X_PIC_GPIO_INT                 7 */
+    4, /* PNX833X_PIC_AUDIO_DEC_INT            8 */
+    5, /* PNX833X_PIC_VIDEO_DEC_INT            9 */
+    4, /* PNX833X_PIC_CONFIG_INT              10 */
+    4, /* PNX833X_PIC_AOI_INT                 11 */
+    9, /* PNX833X_PIC_SYNC_INT                12 */
+    9, /* PNX8335_PIC_SATA_INT                13 */
+    4, /* PNX833X_PIC_OSD_INT                 14 */
+    9, /* PNX833X_PIC_DISP1_INT               15 */
+    4, /* PNX833X_PIC_DEINTERLACER_INT        16 */
+    9, /* PNX833X_PIC_DISPLAY2_INT            17 */
+    4, /* PNX833X_PIC_VC_INT                  18 */
+    4, /* PNX833X_PIC_SC_INT                  19 */
+    9, /* PNX833X_PIC_IDE_INT                 20 */
+    9, /* PNX833X_PIC_IDE_DMA_INT             21 */
+    6, /* PNX833X_PIC_TS_IN1_DV_INT           22 */
+    6, /* PNX833X_PIC_TS_IN1_DMA_INT          23 */
+    4, /* PNX833X_PIC_SGDX_DMA_INT            24 */
+    4, /* PNX833X_PIC_TS_OUT_INT              25 */
+    4, /* PNX833X_PIC_IR_INT                  26 */
+    3, /* PNX833X_PIC_VMSP1_INT               27 */
+    3, /* PNX833X_PIC_VMSP2_INT               28 */
+    4, /* PNX833X_PIC_PIBC_INT                29 */
+    4, /* PNX833X_PIC_TS_IN0_TRD_INT          30 */
+    4, /* PNX833X_PIC_SGDX_TPD_INT            31 */
+    5, /* PNX833X_PIC_USB_INT                 32 */
+    4, /* PNX833X_PIC_TS_IN1_TRD_INT          33 */
+    4, /* PNX833X_PIC_CLOCK_INT               34 */
+    4, /* PNX833X_PIC_SGDX_PARSER_INT         35 */
+    4, /* PNX833X_PIC_VMSP_DMA_INT            36 */
+#if defined(CONFIG_SOC_PNX8335)
+    4, /* PNX8335_PIC_MIU_INT                 37 */
+    4, /* PNX8335_PIC_AVCHIP_IRQ_INT          38 */
+    9, /* PNX8335_PIC_SYNC_HD_INT             39 */
+    9, /* PNX8335_PIC_DISP_HD_INT             40 */
+    9, /* PNX8335_PIC_DISP_SCALER_INT         41 */
+    4, /* PNX8335_PIC_OSD_HD1_INT             42 */
+    4, /* PNX8335_PIC_DTL_WRITER_Y_INT        43 */
+    4, /* PNX8335_PIC_DTL_WRITER_C_INT        44 */
+    4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT   45 */
+    4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT   46 */
+    4, /* PNX8335_PIC_DENC_TTX_INT            47 */
+    4, /* PNX8335_PIC_MMI_SIF0_INT            48 */
+    4, /* PNX8335_PIC_MMI_SIF1_INT            49 */
+    4, /* PNX8335_PIC_MMI_CDMMU_INT           50 */
+    4, /* PNX8335_PIC_PIBCS_INT               51 */
+   12, /* PNX8335_PIC_ETHERNET_INT            52 */
+    3, /* PNX8335_PIC_VMSP1_0_INT             53 */
+    3, /* PNX8335_PIC_VMSP1_1_INT             54 */
+    4, /* PNX8335_PIC_VMSP1_DMA_INT           55 */
+    4, /* PNX8335_PIC_TDGR_DE_INT             56 */
+    4, /* PNX8335_PIC_IR1_IRQ_INT             57 */
+#endif
+};
+
+static void pnx833x_timer_dispatch(void)
+{
+        do_IRQ(mips_cpu_timer_irq);
+}
+
+static void pic_dispatch(void)
+{
+        unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
+
+        if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
+                unsigned long priority = PNX833X_PIC_INT_PRIORITY;
+                PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
+
+                if (irq == PNX833X_PIC_GPIO_INT) {
+                        unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
+                        int pin;
+                        while ((pin = ffs(mask & 0xffff))) {
+                                pin -= 1;
+                                do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
+                                mask &= ~(1 << pin);
+                        }
+                } else {
+                        do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
+                }
+
+                PNX833X_PIC_INT_PRIORITY = priority;
+        } else {
+                printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
+        }
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending = read_c0_status() & read_c0_cause();
+
+        if (pending & STATUSF_IP4)
+                pic_dispatch();
+        else if (pending & STATUSF_IP7)
+                do_IRQ(PNX833X_TIMER_IRQ);
+        else
+                spurious_interrupt();
+}
+
+static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
+{
+        /* Currently we do this by setting IRQ priority to 1.
+           If priority support is being implemented, 1 should be repalced
+                by a better value. */
+        PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
+}
+
+static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
+{
+        /* Disable IRQ by writing setting it's priority to 0 */
+        PNX833X_PIC_INT_REG(irq) = 0;
+}
+
+static int irqflags[PNX833X_PIC_NUM_IRQ];       /* initialized by zeroes */
+#define IRQFLAG_STARTED         1
+#define IRQFLAG_DISABLED        2
+
+static DEFINE_SPINLOCK(pnx833x_irq_lock);
+
+static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
+{
+        unsigned long flags;
+        unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
+
+        spin_lock_irqsave(&pnx833x_irq_lock, flags);
+
+        irqflags[pic_irq] = IRQFLAG_STARTED;    /* started, not disabled */
+        pnx833x_hard_enable_pic_irq(pic_irq);
+
+        spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
+        return 0;
+}
+
+static void pnx833x_shutdown_pic_irq(unsigned int irq)
+{
+        unsigned long flags;
+        unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
+
+        spin_lock_irqsave(&pnx833x_irq_lock, flags);
+
+        irqflags[pic_irq] = 0;                  /* not started */
+        pnx833x_hard_disable_pic_irq(pic_irq);
+
+        spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
+}
+
+static void pnx833x_enable_pic_irq(unsigned int irq)
+{
+        unsigned long flags;
+        unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
+
+        spin_lock_irqsave(&pnx833x_irq_lock, flags);
+
+        irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
+        if (irqflags[pic_irq] == IRQFLAG_STARTED)
+                pnx833x_hard_enable_pic_irq(pic_irq);
+
+        spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
+}
+
+static void pnx833x_disable_pic_irq(unsigned int irq)
+{
+        unsigned long flags;
+        unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
+
+        spin_lock_irqsave(&pnx833x_irq_lock, flags);
+
+        irqflags[pic_irq] |= IRQFLAG_DISABLED;
+        pnx833x_hard_disable_pic_irq(pic_irq);
+
+        spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
+}
+
+static void pnx833x_ack_pic_irq(unsigned int irq)
+{
+}
+
+static void pnx833x_end_pic_irq(unsigned int irq)
+{
+}
+
+static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
+
+static unsigned int pnx833x_startup_gpio_irq(unsigned int irq)
+{
+        int pin = irq - PNX833X_GPIO_IRQ_BASE;
+        unsigned long flags;
+        spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        pnx833x_gpio_enable_irq(pin);
+        spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        return 0;
+}
+
+static void pnx833x_enable_gpio_irq(unsigned int irq)
+{
+        int pin = irq - PNX833X_GPIO_IRQ_BASE;
+        unsigned long flags;
+        spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        pnx833x_gpio_enable_irq(pin);
+        spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
+}
+
+static void pnx833x_disable_gpio_irq(unsigned int irq)
+{
+        int pin = irq - PNX833X_GPIO_IRQ_BASE;
+        unsigned long flags;
+        spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        pnx833x_gpio_disable_irq(pin);
+        spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
+}
+
+static void pnx833x_ack_gpio_irq(unsigned int irq)
+{
+}
+
+static void pnx833x_end_gpio_irq(unsigned int irq)
+{
+        int pin = irq - PNX833X_GPIO_IRQ_BASE;
+        unsigned long flags;
+        spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        pnx833x_gpio_clear_irq(pin);
+        spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
+}
+
+static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
+{
+        int pin = irq - PNX833X_GPIO_IRQ_BASE;
+        int gpio_mode;
+
+        switch (flow_type) {
+        case IRQ_TYPE_EDGE_RISING:
+                gpio_mode = GPIO_INT_EDGE_RISING;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                gpio_mode = GPIO_INT_EDGE_FALLING;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                gpio_mode = GPIO_INT_EDGE_BOTH;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                gpio_mode = GPIO_INT_LEVEL_HIGH;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                gpio_mode = GPIO_INT_LEVEL_LOW;
+                break;
+        default:
+                gpio_mode = GPIO_INT_NONE;
+                break;
+        }
+
+        pnx833x_gpio_setup_irq(gpio_mode, pin);
+
+        return 0;
+}
+
+static struct irq_chip pnx833x_pic_irq_type = {
+        .typename = "PNX-PIC",
+        .startup = pnx833x_startup_pic_irq,
+        .shutdown = pnx833x_shutdown_pic_irq,
+        .enable = pnx833x_enable_pic_irq,
+        .disable = pnx833x_disable_pic_irq,
+        .ack = pnx833x_ack_pic_irq,
+        .end = pnx833x_end_pic_irq
+};
+
+static struct irq_chip pnx833x_gpio_irq_type = {
+        .typename = "PNX-GPIO",
+        .startup = pnx833x_startup_gpio_irq,
+        .shutdown = pnx833x_disable_gpio_irq,
+        .enable = pnx833x_enable_gpio_irq,
+        .disable = pnx833x_disable_gpio_irq,
+        .ack = pnx833x_ack_gpio_irq,
+        .end = pnx833x_end_gpio_irq,
+        .set_type = pnx833x_set_type_gpio_irq
+};
+
+void __init arch_init_irq(void)
+{
+        unsigned int irq;
+
+        /* setup standard internal cpu irqs */
+        mips_cpu_irq_init();
+
+        /* Set IRQ information in irq_desc */
+        for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
+                pnx833x_hard_disable_pic_irq(irq);
+                set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
+        }
+
+        for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
+                set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
+
+        /* Set PIC priority limiter register to 0 */
+        PNX833X_PIC_INT_PRIORITY = 0;
+
+        /* Setup GPIO IRQ dispatching */
+        pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
+
+        /* Enable PIC IRQs (HWIRQ2) */
+        if (cpu_has_vint)
+                set_vi_handler(4, pic_dispatch);
+
+        write_c0_status(read_c0_status() | IE_IRQ2);
+}
+
+unsigned int __cpuinit get_c0_compare_int(void)
+{
+        if (cpu_has_vint)
+                set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
+
+        mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+        return mips_cpu_timer_irq;
+}
+
+void __init plat_time_init(void)
+{
+        /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
+
+        extern unsigned long mips_hpt_frequency;
+        unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
+
+        if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
+                /* Functional clock is disabled so use crystal frequency */
+                mips_hpt_frequency = 25;
+        } else {
+#if defined(CONFIG_SOC_PNX8335)
+                /* Functional clock is enabled, so get clock multiplier */
+                mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
+#else
+                static const unsigned long int freq[4] = {240, 160, 120, 80};
+                mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
+#endif
+        }
+
+        printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
+
+        mips_hpt_frequency *= 500000;
+}
+
diff --git a/arch/mips/nxp/pnx833x/common/platform.c b/arch/mips/nxp/pnx833x/common/platform.c
new file mode 100644
index 00000000000..b1ccbcc18f7
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/platform.c
@@ -0,0 +1,319 @@
+/*
+ *  platform.c: platform support for PNX833X.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  Based on software written by:
+ *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+#include <linux/serial.h>
+#include <linux/serial_pnx8xxx.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#ifdef CONFIG_I2C_PNX0105
+/* Until i2c driver available in kernel.*/
+#include <linux/i2c-pnx0105.h>
+#endif
+
+#include <irq.h>
+#include <irq-mapping.h>
+#include <pnx833x.h>
+
+static u64 uart_dmamask     = DMA_32BIT_MASK;
+
+static struct resource pnx833x_uart_resources[] = {
+        [0] = {
+                .start          = PNX833X_UART0_PORTS_START,
+                .end            = PNX833X_UART0_PORTS_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = PNX833X_PIC_UART0_INT,
+                .end            = PNX833X_PIC_UART0_INT,
+                .flags          = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start          = PNX833X_UART1_PORTS_START,
+                .end            = PNX833X_UART1_PORTS_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        [3] = {
+                .start          = PNX833X_PIC_UART1_INT,
+                .end            = PNX833X_PIC_UART1_INT,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+struct pnx8xxx_port pnx8xxx_ports[] = {
+        [0] = {
+                .port   = {
+                        .type           = PORT_PNX8XXX,
+                        .iotype         = UPIO_MEM,
+                        .membase        = (void __iomem *)PNX833X_UART0_PORTS_START,
+                        .mapbase        = PNX833X_UART0_PORTS_START,
+                        .irq            = PNX833X_PIC_UART0_INT,
+                        .uartclk        = 3692300,
+                        .fifosize       = 16,
+                        .flags          = UPF_BOOT_AUTOCONF,
+                        .line           = 0,
+                },
+        },
+        [1] = {
+                .port   = {
+                        .type           = PORT_PNX8XXX,
+                        .iotype         = UPIO_MEM,
+                        .membase        = (void __iomem *)PNX833X_UART1_PORTS_START,
+                        .mapbase        = PNX833X_UART1_PORTS_START,
+                        .irq            = PNX833X_PIC_UART1_INT,
+                        .uartclk        = 3692300,
+                        .fifosize       = 16,
+                        .flags          = UPF_BOOT_AUTOCONF,
+                        .line           = 1,
+                },
+        },
+};
+
+static struct platform_device pnx833x_uart_device = {
+        .name           = "pnx8xxx-uart",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &uart_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .platform_data          = pnx8xxx_ports,
+        },
+        .num_resources  = ARRAY_SIZE(pnx833x_uart_resources),
+        .resource       = pnx833x_uart_resources,
+};
+
+static u64 ehci_dmamask     = DMA_32BIT_MASK;
+
+static struct resource pnx833x_usb_ehci_resources[] = {
+        [0] = {
+                .start          = PNX833X_USB_PORTS_START,
+                .end            = PNX833X_USB_PORTS_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = PNX833X_PIC_USB_INT,
+                .end            = PNX833X_PIC_USB_INT,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device pnx833x_usb_ehci_device = {
+        .name           = "pnx833x-ehci",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+        },
+        .num_resources  = ARRAY_SIZE(pnx833x_usb_ehci_resources),
+        .resource       = pnx833x_usb_ehci_resources,
+};
+
+#ifdef CONFIG_I2C_PNX0105
+static struct resource pnx833x_i2c0_resources[] = {
+        {
+                .start          = PNX833X_I2C0_PORTS_START,
+                .end            = PNX833X_I2C0_PORTS_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = PNX833X_PIC_I2C0_INT,
+                .end            = PNX833X_PIC_I2C0_INT,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource pnx833x_i2c1_resources[] = {
+        {
+                .start          = PNX833X_I2C1_PORTS_START,
+                .end            = PNX833X_I2C1_PORTS_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = PNX833X_PIC_I2C1_INT,
+                .end            = PNX833X_PIC_I2C1_INT,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = {
+        {
+                .base = PNX833X_I2C0_PORTS_START,
+                .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */
+                .clock = 6,     /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */
+                .bus_addr = 0,  /* no slave support */
+        },
+        {
+                .base = PNX833X_I2C1_PORTS_START,
+                .irq = -1,      /* on high freq, polling is faster */
+                /*.irq = PNX833X_PIC_I2C1_INT,*/
+                .clock = 4,     /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe default for now */
+                .bus_addr = 0,  /* no slave support */
+        },
+};
+
+static struct platform_device pnx833x_i2c0_device = {
+        .name           = "i2c-pnx0105",
+        .id             = 0,
+        .dev = {
+                .platform_data = &pnx833x_i2c_dev[0],
+        },
+        .num_resources  = ARRAY_SIZE(pnx833x_i2c0_resources),
+        .resource       = pnx833x_i2c0_resources,
+};
+
+static struct platform_device pnx833x_i2c1_device = {
+        .name           = "i2c-pnx0105",
+        .id             = 1,
+        .dev = {
+                .platform_data = &pnx833x_i2c_dev[1],
+        },
+        .num_resources  = ARRAY_SIZE(pnx833x_i2c1_resources),
+        .resource       = pnx833x_i2c1_resources,
+};
+#endif
+
+static u64 ethernet_dmamask = DMA_32BIT_MASK;
+
+static struct resource pnx833x_ethernet_resources[] = {
+        [0] = {
+                .start = PNX8335_IP3902_PORTS_START,
+                .end   = PNX8335_IP3902_PORTS_END,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = PNX8335_PIC_ETHERNET_INT,
+                .end   = PNX8335_PIC_ETHERNET_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device pnx833x_ethernet_device = {
+        .name = "ip3902-eth",
+        .id   = -1,
+        .dev  = {
+                .dma_mask          = &ethernet_dmamask,
+                .coherent_dma_mask = DMA_32BIT_MASK,
+        },
+        .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),
+        .resource      = pnx833x_ethernet_resources,
+};
+
+static struct resource pnx833x_sata_resources[] = {
+        [0] = {
+                .start = PNX8335_SATA_PORTS_START,
+                .end   = PNX8335_SATA_PORTS_END,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = PNX8335_PIC_SATA_INT,
+                .end   = PNX8335_PIC_SATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device pnx833x_sata_device = {
+        .name          = "pnx833x-sata",
+        .id            = -1,
+        .num_resources = ARRAY_SIZE(pnx833x_sata_resources),
+        .resource      = pnx833x_sata_resources,
+};
+
+static const char *part_probes[] = {
+        "cmdlinepart",
+        NULL
+};
+
+static void
+pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        if (ctrl & NAND_CLE)
+                writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK));
+        else
+                writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_ALE_MASK));
+}
+
+static struct platform_nand_data pnx833x_flash_nand_data = {
+        .chip = {
+                .chip_delay             = 25,
+                .part_probe_types       = part_probes,
+        },
+        .ctrl = {
+                .cmd_ctrl               = pnx833x_flash_nand_cmd_ctrl
+        }
+};
+
+/*
+ * Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!),
+ * 12 bytes more seems to be the standard that allows for NAND access.
+ */
+static struct resource pnx833x_flash_nand_resource = {
+        .start  = PNX8335_NAND_BASE,
+        .end    = PNX8335_NAND_BASE + 12,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device pnx833x_flash_nand = {
+        .name           = "gen_nand",
+        .id                     = -1,
+        .num_resources  = 1,
+        .resource           = &pnx833x_flash_nand_resource,
+        .dev            = {
+                .platform_data = &pnx833x_flash_nand_data,
+        },
+};
+
+static struct platform_device *pnx833x_platform_devices[] __initdata = {
+        &pnx833x_uart_device,
+        &pnx833x_usb_ehci_device,
+#ifdef CONFIG_I2C_PNX0105
+        &pnx833x_i2c0_device,
+        &pnx833x_i2c1_device,
+#endif
+        &pnx833x_ethernet_device,
+        &pnx833x_sata_device,
+        &pnx833x_flash_nand,
+};
+
+static int __init pnx833x_platform_init(void)
+{
+        int res;
+
+        res = platform_add_devices(pnx833x_platform_devices,
+                                   ARRAY_SIZE(pnx833x_platform_devices));
+
+        return res;
+}
+
+arch_initcall(pnx833x_platform_init);
diff --git a/arch/mips/nxp/pnx833x/common/prom.c b/arch/mips/nxp/pnx833x/common/prom.c
new file mode 100644
index 00000000000..2a41e8fec21
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/prom.c
@@ -0,0 +1,70 @@
+/*
+ *  prom.c:
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  Based on software written by:
+ *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <asm/bootinfo.h>
+#include <linux/string.h>
+
+void __init prom_init_cmdline(void)
+{
+        int argc = fw_arg0;
+        char **argv = (char **)fw_arg1;
+        char *c = &(arcs_cmdline[0]);
+        int i;
+
+        for (i = 1; i < argc; i++) {
+                strcpy(c, argv[i]);
+                c += strlen(argv[i]);
+                if (i < argc-1)
+                        *c++ = ' ';
+        }
+        *c = 0;
+}
+
+char __init *prom_getenv(char *envname)
+{
+        extern char **prom_envp;
+        char **env = prom_envp;
+        int i;
+
+        i = strlen(envname);
+
+        while (*env) {
+                if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=')
+                        return *env + i + 1;
+                env++;
+        }
+
+        return 0;
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+char * __init prom_getcmdline(void)
+{
+        return arcs_cmdline;
+}
+
diff --git a/arch/mips/nxp/pnx833x/common/reset.c b/arch/mips/nxp/pnx833x/common/reset.c
new file mode 100644
index 00000000000..a9bc9bacad2
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/reset.c
@@ -0,0 +1,45 @@
+/*
+ *  reset.c: reset support for PNX833X.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  Based on software written by:
+ *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/slab.h>
+#include <linux/reboot.h>
+#include <pnx833x.h>
+
+void pnx833x_machine_restart(char *command)
+{
+        PNX833X_RESET_CONTROL_2 = 0;
+        PNX833X_RESET_CONTROL = 0;
+}
+
+void pnx833x_machine_halt(void)
+{
+        while (1)
+                __asm__ __volatile__ ("wait");
+
+}
+
+void pnx833x_machine_power_off(void)
+{
+        pnx833x_machine_halt();
+}
diff --git a/arch/mips/nxp/pnx833x/common/setup.c b/arch/mips/nxp/pnx833x/common/setup.c
new file mode 100644
index 00000000000..e51fbc4b644
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/setup.c
@@ -0,0 +1,64 @@
+/*
+ *  setup.c: Setup PNX833X Soc.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  Based on software written by:
+ *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <asm/reboot.h>
+#include <pnx833x.h>
+#include <gpio.h>
+
+extern void pnx833x_board_setup(void);
+extern void pnx833x_machine_restart(char *);
+extern void pnx833x_machine_halt(void);
+extern void pnx833x_machine_power_off(void);
+
+int __init plat_mem_setup(void)
+{
+        /* fake pci bus to avoid bounce buffers */
+        PCI_DMA_BUS_IS_PHYS = 1;
+
+        /* set mips clock to 320MHz */
+#if defined(CONFIG_SOC_PNX8335)
+        PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ);
+#endif
+        pnx833x_gpio_init();    /* so it will be ready in board_setup() */
+
+        pnx833x_board_setup();
+
+        _machine_restart = pnx833x_machine_restart;
+        _machine_halt = pnx833x_machine_halt;
+        pm_power_off = pnx833x_machine_power_off;
+
+        /* IO/MEM resources. */
+        set_io_port_base(KSEG1);
+        ioport_resource.start = 0;
+        ioport_resource.end = ~0;
+        iomem_resource.start = 0;
+        iomem_resource.end = ~0;
+
+        return 0;
+}
diff --git a/arch/mips/nxp/pnx833x/stb22x/Makefile b/arch/mips/nxp/pnx833x/stb22x/Makefile
new file mode 100644
index 00000000000..f81c5801f45
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/stb22x/Makefile
@@ -0,0 +1,3 @@
+lib-y := board.o
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx833x/stb22x/board.c b/arch/mips/nxp/pnx833x/stb22x/board.c
new file mode 100644
index 00000000000..90cc604bdad
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/stb22x/board.c
@@ -0,0 +1,133 @@
+/*
+ *  board.c: STB225 board support.
+ *
+ *  Copyright 2008 NXP Semiconductors
+ *        Chris Steel <chris.steel@nxp.com>
+ *    Daniel Laird <daniel.j.laird@nxp.com>
+ *
+ *  Based on software written by:
+ *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <asm/bootinfo.h>
+#include <linux/mm.h>
+#include <pnx833x.h>
+#include <gpio.h>
+
+/* endianess twiddlers */
+#define PNX8335_DEBUG0 0x4400
+#define PNX8335_DEBUG1 0x4404
+#define PNX8335_DEBUG2 0x4408
+#define PNX8335_DEBUG3 0x440c
+#define PNX8335_DEBUG4 0x4410
+#define PNX8335_DEBUG5 0x4414
+#define PNX8335_DEBUG6 0x4418
+#define PNX8335_DEBUG7 0x441c
+
+int prom_argc;
+char **prom_argv = 0, **prom_envp = 0;
+
+extern void prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+
+const char *get_system_type(void)
+{
+        return "NXP STB22x";
+}
+
+static inline unsigned long env_or_default(char *env, unsigned long dfl)
+{
+        char *str = prom_getenv(env);
+        return str ? simple_strtol(str, 0, 0) : dfl;
+}
+
+void __init prom_init(void)
+{
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize = env_or_default("memsize", 0x02000000);
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void __init pnx833x_board_setup(void)
+{
+        pnx833x_gpio_select_function_alt(4);
+        pnx833x_gpio_select_output(4);
+        pnx833x_gpio_select_function_alt(5);
+        pnx833x_gpio_select_input(5);
+        pnx833x_gpio_select_function_alt(6);
+        pnx833x_gpio_select_input(6);
+        pnx833x_gpio_select_function_alt(7);
+        pnx833x_gpio_select_output(7);
+
+        pnx833x_gpio_select_function_alt(25);
+        pnx833x_gpio_select_function_alt(26);
+
+        pnx833x_gpio_select_function_alt(27);
+        pnx833x_gpio_select_function_alt(28);
+        pnx833x_gpio_select_function_alt(29);
+        pnx833x_gpio_select_function_alt(30);
+        pnx833x_gpio_select_function_alt(31);
+        pnx833x_gpio_select_function_alt(32);
+        pnx833x_gpio_select_function_alt(33);
+
+#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+        /* Setup MIU for NAND access on CS0...
+         *
+         * (it seems that we must also configure CS1 for reliable operation,
+         * otherwise the first read ID command will fail if it's read as 4 bytes
+         * but pass if it's read as 1 word.)
+         */
+
+        /* Setup MIU CS0 & CS1 timing */
+        PNX833X_MIU_SEL0 = 0;
+        PNX833X_MIU_SEL1 = 0;
+        PNX833X_MIU_SEL0_TIMING = 0x50003081;
+        PNX833X_MIU_SEL1_TIMING = 0x50003081;
+
+        /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
+        pnx833x_gpio_select_function_alt(0);
+
+        /* Setup GPIO 04 to input NAND read/busy signal */
+        pnx833x_gpio_select_function_io(4);
+        pnx833x_gpio_select_input(4);
+
+        /* Setup GPIO 05 to disable NAND write protect */
+        pnx833x_gpio_select_function_io(5);
+        pnx833x_gpio_select_output(5);
+        pnx833x_gpio_write(1, 5);
+
+#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE)
+
+        /* Set up MIU for 16-bit NOR access on CS0 and CS1... */
+
+        /* Setup MIU CS0 & CS1 timing */
+        PNX833X_MIU_SEL0 = 1;
+        PNX833X_MIU_SEL1 = 1;
+        PNX833X_MIU_SEL0_TIMING = 0x6A08D082;
+        PNX833X_MIU_SEL1_TIMING = 0x6A08D082;
+
+        /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
+        pnx833x_gpio_select_function_alt(0);
+#endif
+}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index b1886244ced..e8a97f59e06 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_MIPS_MSC)		+= ops-msc.o
 obj-$(CONFIG_MIPS_NILE4)        += ops-nile4.o
 obj-$(CONFIG_SOC_TX3927)        += ops-tx3927.o
 obj-$(CONFIG_PCI_VR41XX)        += ops-vr41xx.o pci-vr41xx.o
-obj-$(CONFIG_MARKEINS)          += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
+obj-$(CONFIG_NEC_MARKEINS)      += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
 obj-$(CONFIG_PCI_TX4927)        += ops-tx4927.o
 obj-$(CONFIG_BCM47XX)           += pci-bcm47xx.o
 
diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c
index 846eae9cdd0..fba5aad00d5 100644
--- a/arch/mips/pci/fixup-emma2rh.c
+++ b/arch/mips/pci/fixup-emma2rh.c
@@ -30,7 +30,7 @@
 
 #include <asm/bootinfo.h>
 
-#include <asm/emma2rh/emma2rh.h>
+#include <asm/emma/emma2rh.h>
 
 #define EMMA2RH_PCI_HOST_SLOT 0x09
 #define EMMA2RH_USB_SLOT 0x03
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
index 75b90dcb7a0..3d86823d03a 100644
--- a/arch/mips/pci/fixup-rc32434.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -30,6 +30,7 @@
 #include <linux/init.h>
 
 #include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/irq.h>
 
 static int __devinitdata irq_map[2][12] = {
         {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c
index d31bfc6d415..5947a70b0b7 100644
--- a/arch/mips/pci/ops-emma2rh.c
+++ b/arch/mips/pci/ops-emma2rh.c
@@ -30,7 +30,7 @@
 #include <asm/addrspace.h>
 #include <asm/debug.h>
 
-#include <asm/emma2rh/emma2rh.h>
+#include <asm/emma/emma2rh.h>
 
 #define RTABORT (0x1<<9)
 #define RMABORT (0x1<<10)
diff --git a/arch/mips/pci/pci-emma2rh.c b/arch/mips/pci/pci-emma2rh.c
index 772e283daa6..2df4190232c 100644
--- a/arch/mips/pci/pci-emma2rh.c
+++ b/arch/mips/pci/pci-emma2rh.c
@@ -30,7 +30,7 @@
 
 #include <asm/bootinfo.h>
 
-#include <asm/emma2rh/emma2rh.h>
+#include <asm/emma/emma2rh.h>
 
 static struct resource pci_io_resource = {
         .name = "pci IO space",
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 31619c601b1..c1c29181bd4 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = {
 /* Resources and device for NAND */
 static int rb532_dev_ready(struct mtd_info *mtd)
 {
-        return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
+        return gpio_get_value(GPIO_RDY);
 }
 
 static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
@@ -280,7 +280,7 @@ static int __init plat_setup_devices(void)
 {
         /* Look for the CF card reader */
         if (!readl(IDT434_REG_BASE + DEV1MASK))
-                rb532_devs[1] = NULL;
+                rb532_devs[2] = NULL;   /* disable cf_slot0 at index 2 */
         else {
                 cf_slot0_res[0].start =
                     readl(IDT434_REG_BASE + DEV1BASE);
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 76a7fd96d56..0e84c8ab6a3 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -39,10 +39,6 @@
 struct rb532_gpio_chip {
         struct gpio_chip chip;
         void __iomem     *regbase;
-        void            (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value);
-        int             (*get_int_level)(struct gpio_chip *chip, unsigned offset);
-        void            (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value);
-        int             (*get_int_status)(struct gpio_chip *chip, unsigned offset);
 };
 
 struct mpmc_device dev3;
@@ -111,15 +107,47 @@ unsigned char get_latch_u5(void)
 }
 EXPORT_SYMBOL(get_latch_u5);
 
+/* rb532_set_bit - sanely set a bit
+ *
+ * bitval: new value for the bit
+ * offset: bit index in the 4 byte address range
+ * ioaddr: 4 byte aligned address being altered
+ */
+static inline void rb532_set_bit(unsigned bitval,
+                unsigned offset, void __iomem *ioaddr)
+{
+        unsigned long flags;
+        u32 val;
+
+        bitval = !!bitval;              /* map parameter to {0,1} */
+
+        local_irq_save(flags);
+
+        val = readl(ioaddr);
+        val &= ~( ~bitval << offset );   /* unset bit if bitval == 0 */
+        val |=  (  bitval << offset );   /* set bit if bitval == 1 */
+        writel(val, ioaddr);
+
+        local_irq_restore(flags);
+}
+
+/* rb532_get_bit - read a bit
+ *
+ * returns the boolean state of the bit, which may be > 1
+ */
+static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
+{
+        return (readl(ioaddr) & (1 << offset));
+}
+
 /*
  * Return GPIO level */
 static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        u32                     mask = 1 << offset;
         struct rb532_gpio_chip  *gpch;
 
         gpch = container_of(chip, struct rb532_gpio_chip, chip);
-        return readl(gpch->regbase + GPIOD) & mask;
+        return rb532_get_bit(offset, gpch->regbase + GPIOD);
 }
 
 /*
@@ -128,23 +156,10 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
 static void rb532_gpio_set(struct gpio_chip *chip,
                                 unsigned offset, int value)
 {
-        unsigned long           flags;
-        u32                     mask = 1 << offset;
-        u32                     tmp;
         struct rb532_gpio_chip  *gpch;
-        void __iomem            *gpvr;
 
         gpch = container_of(chip, struct rb532_gpio_chip, chip);
-        gpvr = gpch->regbase + GPIOD;
-
-        local_irq_save(flags);
-        tmp = readl(gpvr);
-        if (value)
-                tmp |= mask;
-        else
-                tmp &= ~mask;
-        writel(tmp, gpvr);
-        local_irq_restore(flags);
+        rb532_set_bit(value, offset, gpch->regbase + GPIOD);
 }
 
 /*
@@ -152,21 +167,14 @@ static void rb532_gpio_set(struct gpio_chip *chip,
  */
 static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
-        unsigned long           flags;
-        u32                     mask = 1 << offset;
-        u32                     value;
         struct rb532_gpio_chip  *gpch;
-        void __iomem            *gpdr;
 
         gpch = container_of(chip, struct rb532_gpio_chip, chip);
-        gpdr = gpch->regbase + GPIOCFG;
 
-        local_irq_save(flags);
-        value = readl(gpdr);
-        value &= ~mask;
-        writel(value, gpdr);
-        local_irq_restore(flags);
+        if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
+                return 1;       /* alternate function, GPIOCFG is ignored */
 
+        rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
         return 0;
 }
 
@@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 static int rb532_gpio_direction_output(struct gpio_chip *chip,
                                         unsigned offset, int value)
 {
-        unsigned long           flags;
-        u32                     mask = 1 << offset;
-        u32                     tmp;
         struct rb532_gpio_chip  *gpch;
-        void __iomem            *gpdr;
 
         gpch = container_of(chip, struct rb532_gpio_chip, chip);
-        writel(mask, gpch->regbase + GPIOD);
-        gpdr = gpch->regbase + GPIOCFG;
 
-        local_irq_save(flags);
-        tmp = readl(gpdr);
-        tmp |= mask;
-        writel(tmp, gpdr);
-        local_irq_restore(flags);
+        if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
+                return 1;       /* alternate function, GPIOCFG is ignored */
+
+        /* set the initial output value */
+        rb532_set_bit(value, offset, gpch->regbase + GPIOD);
 
+        rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
         return 0;
 }
 
-/*
- * Set the GPIO interrupt level
- */
-static void rb532_gpio_set_int_level(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        unsigned long           flags;
-        u32                     mask = 1 << offset;
-        u32                     tmp;
-        struct rb532_gpio_chip  *gpch;
-        void __iomem            *gpil;
-
-        gpch = container_of(chip, struct rb532_gpio_chip, chip);
-        gpil = gpch->regbase + GPIOILEVEL;
-
-        local_irq_save(flags);
-        tmp = readl(gpil);
-        if (value)
-                tmp |= mask;
-        else
-                tmp &= ~mask;
-        writel(tmp, gpil);
-        local_irq_restore(flags);
-}
+static struct rb532_gpio_chip rb532_gpio_chip[] = {
+        [0] = {
+                .chip = {
+                        .label                  = "gpio0",
+                        .direction_input        = rb532_gpio_direction_input,
+                        .direction_output       = rb532_gpio_direction_output,
+                        .get                    = rb532_gpio_get,
+                        .set                    = rb532_gpio_set,
+                        .base                   = 0,
+                        .ngpio                  = 32,
+                },
+        },
+};
 
 /*
- * Get the GPIO interrupt level
+ * Set GPIO interrupt level
  */
-static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset)
+void rb532_gpio_set_ilevel(int bit, unsigned gpio)
 {
-        u32                     mask = 1 << offset;
-        struct rb532_gpio_chip  *gpch;
-
-        gpch = container_of(chip, struct rb532_gpio_chip, chip);
-        return readl(gpch->regbase + GPIOILEVEL) & mask;
+        rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
 }
+EXPORT_SYMBOL(rb532_gpio_set_ilevel);
 
 /*
- * Set the GPIO interrupt status
+ * Set GPIO interrupt status
  */
-static void rb532_gpio_set_int_status(struct gpio_chip *chip,
-                                unsigned offset, int value)
+void rb532_gpio_set_istat(int bit, unsigned gpio)
 {
-        unsigned long           flags;
-        u32                     mask = 1 << offset;
-        u32                     tmp;
-        struct rb532_gpio_chip  *gpch;
-        void __iomem            *gpis;
-
-        gpch = container_of(chip, struct rb532_gpio_chip, chip);
-        gpis = gpch->regbase + GPIOISTAT;
-
-        local_irq_save(flags);
-        tmp = readl(gpis);
-        if (value)
-                tmp |= mask;
-        else
-                tmp &= ~mask;
-        writel(tmp, gpis);
-        local_irq_restore(flags);
+        rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
 }
+EXPORT_SYMBOL(rb532_gpio_set_istat);
 
 /*
- * Get the GPIO interrupt status
+ * Configure GPIO alternate function
  */
-static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset)
+static void rb532_gpio_set_func(int bit, unsigned gpio)
 {
-        u32                     mask = 1 << offset;
-        struct rb532_gpio_chip  *gpch;
-
-        gpch = container_of(chip, struct rb532_gpio_chip, chip);
-        return readl(gpch->regbase + GPIOISTAT) & mask;
+       rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
 }
 
-static struct rb532_gpio_chip rb532_gpio_chip[] = {
-        [0] = {
-                .chip = {
-                        .label                  = "gpio0",
-                        .direction_input        = rb532_gpio_direction_input,
-                        .direction_output       = rb532_gpio_direction_output,
-                        .get                    = rb532_gpio_get,
-                        .set                    = rb532_gpio_set,
-                        .base                   = 0,
-                        .ngpio                  = 32,
-                },
-                .get_int_level          = rb532_gpio_get_int_level,
-                .set_int_level          = rb532_gpio_set_int_level,
-                .get_int_status         = rb532_gpio_get_int_status,
-                .set_int_status         = rb532_gpio_set_int_status,
-        },
-};
-
 int __init rb532_gpio_init(void)
 {
         struct resource *r;
@@ -310,6 +261,12 @@ int __init rb532_gpio_init(void)
                 return -ENXIO;
         }
 
+        /* configure CF_GPIO_NUM as CFRDY IRQ source */
+        rb532_gpio_set_func(0, CF_GPIO_NUM);
+        rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
+        rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
+        rb532_gpio_set_istat(0, CF_GPIO_NUM);
+
         return 0;
 }
 arch_initcall(rb532_gpio_init);
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index f6d9bf4b26e..f8b18af141a 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -12,20 +12,11 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/kernel_stat.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
 #include <asm/irq_cpu.h>
-#include <asm/sgi/ioc.h>
 #include <asm/sgi/hpc3.h>
 #include <asm/sgi/ip22.h>
-#include <asm/time.h>
-
-/* #define DEBUG_SGINT */
 
 /* So far nothing hangs here */
 #undef USE_LIO3_IRQ
@@ -68,7 +59,7 @@ static void enable_local1_irq(unsigned int irq)
                 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
 }
 
-void disable_local1_irq(unsigned int irq)
+static void disable_local1_irq(unsigned int irq)
 {
         sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
 }
@@ -87,7 +78,7 @@ static void enable_local2_irq(unsigned int irq)
         sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
 }
 
-void disable_local2_irq(unsigned int irq)
+static void disable_local2_irq(unsigned int irq)
 {
         sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
         if (!sgint->cmeimask0)
@@ -108,7 +99,7 @@ static void enable_local3_irq(unsigned int irq)
         sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
 }
 
-void disable_local3_irq(unsigned int irq)
+static void disable_local3_irq(unsigned int irq)
 {
         sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
         if (!sgint->cmeimask1)
@@ -344,6 +335,6 @@ void __init arch_init_irq(void)
 
 #ifdef CONFIG_EISA
         if (ip22_is_fullhouse())        /* Only Indigo-2 has EISA stuff */
-                ip22_eisa_init();
+                ip22_eisa_init();
 #endif
 }
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 17052db4161..226e8bb2f0a 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -46,9 +46,10 @@ config TOSHIBA_RBTX4938
           support this machine type
 
 config TOSHIBA_RBTX4939
-        bool "Toshiba RBTX4939 bobard"
+        bool "Toshiba RBTX4939 board"
         depends on MACH_TX49XX
         select SOC_TX4939
+        select TXX9_7SEGLED
         help
           This Toshiba board is based on the TX4939 processor. Say Y here to
           support this machine type
@@ -86,6 +87,9 @@ config SOC_TX4939
         select HW_HAS_PCI
         select PCI_TX4927
 
+config TXX9_7SEGLED
+        bool
+
 config TOSHIBA_FPCIB0
         bool "FPCIB0 Backplane Support"
         depends on PCI && MACH_TXX9
diff --git a/arch/mips/txx9/generic/7segled.c b/arch/mips/txx9/generic/7segled.c
new file mode 100644
index 00000000000..727ab21b661
--- /dev/null
+++ b/arch/mips/txx9/generic/7segled.c
@@ -0,0 +1,112 @@
+/*
+ * 7 Segment LED routines
+ * Based on RBTX49xx patch from CELF patch archive.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright TOSHIBA CORPORATION 2005-2007
+ * All Rights Reserved.
+ */
+#include <linux/sysdev.h>
+#include <linux/slab.h>
+#include <linux/map_to_7segment.h>
+#include <asm/txx9/generic.h>
+
+static unsigned int tx_7segled_num;
+static void (*tx_7segled_putc)(unsigned int pos, unsigned char val);
+
+void __init txx9_7segled_init(unsigned int num,
+                              void (*putc)(unsigned int pos, unsigned char val))
+{
+        tx_7segled_num = num;
+        tx_7segled_putc = putc;
+}
+
+static SEG7_CONVERSION_MAP(txx9_seg7map, MAP_ASCII7SEG_ALPHANUM_LC);
+
+int txx9_7segled_putc(unsigned int pos, char c)
+{
+        if (pos >= tx_7segled_num)
+                return -EINVAL;
+        c = map_to_seg7(&txx9_seg7map, c);
+        if (c < 0)
+                return c;
+        tx_7segled_putc(pos, c);
+        return 0;
+}
+
+static ssize_t ascii_store(struct sys_device *dev,
+                           struct sysdev_attribute *attr,
+                           const char *buf, size_t size)
+{
+        unsigned int ch = dev->id;
+        txx9_7segled_putc(ch, buf[0]);
+        return size;
+}
+
+static ssize_t raw_store(struct sys_device *dev,
+                         struct sysdev_attribute *attr,
+                         const char *buf, size_t size)
+{
+        unsigned int ch = dev->id;
+        tx_7segled_putc(ch, buf[0]);
+        return size;
+}
+
+static SYSDEV_ATTR(ascii, 0200, NULL, ascii_store);
+static SYSDEV_ATTR(raw, 0200, NULL, raw_store);
+
+static ssize_t map_seg7_show(struct sysdev_class *class, char *buf)
+{
+        memcpy(buf, &txx9_seg7map, sizeof(txx9_seg7map));
+        return sizeof(txx9_seg7map);
+}
+
+static ssize_t map_seg7_store(struct sysdev_class *class,
+                              const char *buf, size_t size)
+{
+        if (size != sizeof(txx9_seg7map))
+                return -EINVAL;
+        memcpy(&txx9_seg7map, buf, size);
+        return size;
+}
+
+static SYSDEV_CLASS_ATTR(map_seg7, 0600, map_seg7_show, map_seg7_store);
+
+static struct sysdev_class tx_7segled_sysdev_class = {
+        .name   = "7segled",
+};
+
+static int __init tx_7segled_init_sysfs(void)
+{
+        int error, i;
+        if (!tx_7segled_num)
+                return -ENODEV;
+        error = sysdev_class_register(&tx_7segled_sysdev_class);
+        if (error)
+                return error;
+        error = sysdev_class_create_file(&tx_7segled_sysdev_class,
+                                         &attr_map_seg7);
+        if (error)
+                return error;
+        for (i = 0; i < tx_7segled_num; i++) {
+                struct sys_device *dev;
+                dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+                if (!dev) {
+                        error = -ENODEV;
+                        break;
+                }
+                dev->id = i;
+                dev->cls = &tx_7segled_sysdev_class;
+                error = sysdev_register(dev);
+                if (!error) {
+                        sysdev_create_file(dev, &attr_ascii);
+                        sysdev_create_file(dev, &attr_raw);
+                }
+        }
+        return error;
+}
+
+device_initcall(tx_7segled_init_sysfs);
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 0030d23bef5..f2579ce054a 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_SOC_TX4938)	+= mem_tx4927.o setup_tx4938.o irq_tx4938.o
 obj-$(CONFIG_SOC_TX4939)        += setup_tx4939.o irq_tx4939.o
 obj-$(CONFIG_TOSHIBA_FPCIB0)    += smsc_fdc37m81x.o
 obj-$(CONFIG_SPI)               += spi_eeprom.o
+obj-$(CONFIG_TXX9_7SEGLED)      += 7segled.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 5526375010f..a13a08b8c9e 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -156,11 +156,23 @@ static struct txx9_board_vec *__init find_board_byname(const char *name)
 
 static void __init prom_init_cmdline(void)
 {
-        int argc = (int)fw_arg0;
-        int *argv32 = (int *)fw_arg1;
+        int argc;
+        int *argv32;
         int i;                  /* Always ignore the "-c" at argv[0] */
         char builtin[CL_SIZE];
 
+        if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
+                /*
+                 * argc is not a valid number, or argv32 is not a valid
+                 * pointer
+                 */
+                argc = 0;
+                argv32 = NULL;
+        } else {
+                argc = (int)fw_arg0;
+                argv32 = (int *)fw_arg1;
+        }
+
         /* ignore all built-in args if any f/w args given */
         /*
          * But if built-in strings was started with '+', append them
@@ -414,10 +426,12 @@ char * __init prom_getcmdline(void)
 
 const char *__init prom_getenv(const char *name)
 {
-        const s32 *str = (const s32 *)fw_arg2;
+        const s32 *str;
 
-        if (!str)
+        if (fw_arg2 < CKSEG0)
                 return NULL;
+
+        str = (const s32 *)fw_arg2;
         /* YAMON style ("name", "value" pairs) */
         while (str[0] && str[1]) {
                 if (!strcmp((const char *)(unsigned long)str[0], name))
@@ -622,6 +636,21 @@ unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
 EXPORT_SYMBOL(__swizzle_addr_b);
 #endif
 
+#ifdef NEEDS_TXX9_IOSWABW
+static u16 ioswabw_default(volatile u16 *a, u16 x)
+{
+        return le16_to_cpu(x);
+}
+static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
+{
+        return x;
+}
+u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
+EXPORT_SYMBOL(ioswabw);
+u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
+EXPORT_SYMBOL(__mem_ioswabw);
+#endif
+
 void __init txx9_physmap_flash_init(int no, unsigned long addr,
                                     unsigned long size,
                                     const struct physmap_flash_data *pdata)
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 4a74423b2ba..01129a9d50f 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -49,6 +49,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/leds.h>
 #include <asm/io.h>
 #include <asm/reboot.h>
 #include <asm/txx9/generic.h>
@@ -210,10 +211,6 @@ static void __init rbtx4927_mem_setup(void)
         /* TX4927-SIO DTR on (PIO[15]) */
         gpio_request(15, "sio-dtr");
         gpio_direction_output(15, 1);
-        gpio_request(0, "led");
-        gpio_direction_output(0, 1);
-        gpio_request(1, "led");
-        gpio_direction_output(1, 1);
 
         tx4927_sio_init(0, 0);
 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
@@ -315,6 +312,25 @@ static void __init rbtx4927_mtd_init(void)
                 tx4927_mtd_init(i);
 }
 
+static void __init rbtx4927_gpioled_init(void)
+{
+        static struct gpio_led leds[] = {
+                { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, },
+                { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, },
+        };
+        static struct gpio_led_platform_data pdata = {
+                .num_leds = ARRAY_SIZE(leds),
+                .leds = leds,
+        };
+        struct platform_device *pdev = platform_device_alloc("leds-gpio", 0);
+
+        if (!pdev)
+                return;
+        pdev->dev.platform_data = &pdata;
+        if (platform_device_add(pdev))
+                platform_device_put(pdev);
+}
+
 static void __init rbtx4927_device_init(void)
 {
         toshiba_rbtx4927_rtc_init();
@@ -322,6 +338,7 @@ static void __init rbtx4927_device_init(void)
         tx4927_wdt_init();
         rbtx4927_mtd_init();
         txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
+        rbtx4927_gpioled_init();
 }
 
 struct txx9_board_vec rbtx4927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 9855d7bccc2..98fbd9391bf 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -14,6 +14,8 @@
 #include <linux/types.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
+#include <linux/interrupt.h>
+#include <linux/smc91x.h>
 #include <asm/reboot.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/pci.h>
@@ -33,6 +35,21 @@ static void __init rbtx4939_time_init(void)
         tx4939_time_init(0);
 }
 
+#if defined(__BIG_ENDIAN) && \
+        (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE))
+#define HAVE_RBTX4939_IOSWAB
+#define IS_CE1_ADDR(addr) \
+        ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
+static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x)
+{
+        return IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
+}
+static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x)
+{
+        return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
+}
+#endif /* __BIG_ENDIAN && CONFIG_SMC91X */
+
 static void __init rbtx4939_pci_setup(void)
 {
 #ifdef CONFIG_PCI
@@ -239,6 +256,32 @@ static inline void rbtx4939_led_setup(void)
 }
 #endif
 
+static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
+{
+#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
+        unsigned long flags;
+        local_irq_save(flags);
+        /* bit7: reserved for LED class */
+        led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f);
+        val = led_val[pos];
+        local_irq_restore(flags);
+#endif
+        writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4));
+}
+
+static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
+{
+        /* convert from map_to_seg7() notation */
+        val = (val & 0x88) |
+                ((val & 0x40) >> 6) |
+                ((val & 0x20) >> 4) |
+                ((val & 0x10) >> 2) |
+                ((val & 0x04) << 2) |
+                ((val & 0x02) << 4) |
+                ((val & 0x01) << 6);
+        __rbtx4939_7segled_putc(pos, val);
+}
+
 static void __init rbtx4939_arch_init(void)
 {
         rbtx4939_pci_setup();
@@ -246,22 +289,50 @@ static void __init rbtx4939_arch_init(void)
 
 static void __init rbtx4939_device_init(void)
 {
+        unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
+        struct resource smc_res[] = {
+                {
+                        .start  = smc_addr,
+                        .end    = smc_addr + 0x10 - 1,
+                        .flags  = IORESOURCE_MEM,
+                }, {
+                        .start  = RBTX4939_IRQ_ETHER,
+                        /* override default irq flag defined in smc91x.h */
+                        .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+                },
+        };
+        struct smc91x_platdata smc_pdata = {
+                .flags = SMC91X_USE_16BIT,
+        };
+        struct platform_device *pdev;
 #if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
         int i, j;
         unsigned char ethaddr[2][6];
+        u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
+
         for (i = 0; i < 2; i++) {
                 unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
-                if (readb(rbtx4939_bdipsw_addr) & 8) {
+                if (bdipsw == 0)
+                        memcpy(ethaddr[i], (void *)area, 6);
+                else {
                         u16 buf[3];
-                        area -= 0x03000000;
+                        if (bdipsw & 8)
+                                area -= 0x03000000;
+                        else
+                                area -= 0x01000000;
                         for (j = 0; j < 3; j++)
                                 buf[j] = le16_to_cpup((u16 *)(area + j * 2));
                         memcpy(ethaddr[i], buf, 6);
-                } else
-                        memcpy(ethaddr[i], (void *)area, 6);
+                }
         }
         tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
 #endif
+        pdev = platform_device_alloc("smc91x", -1);
+        if (!pdev ||
+            platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) ||
+            platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) ||
+            platform_device_add(pdev))
+                platform_device_put(pdev);
         rbtx4939_led_setup();
         tx4939_wdt_init();
         tx4939_ata_init();
@@ -269,6 +340,8 @@ static void __init rbtx4939_device_init(void)
 
 static void __init rbtx4939_setup(void)
 {
+        int i;
+
         rbtx4939_ebusc_setup();
         /* always enable ATA0 */
         txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
@@ -276,9 +349,16 @@ static void __init rbtx4939_setup(void)
         if (txx9_master_clock == 0)
                 txx9_master_clock = 20000000;
         tx4939_setup();
+#ifdef HAVE_RBTX4939_IOSWAB
+        ioswabw = rbtx4939_ioswabw;
+        __mem_ioswabw = rbtx4939_mem_ioswabw;
+#endif
 
         _machine_restart = rbtx4939_machine_restart;
 
+        txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc);
+        for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++)
+                txx9_7segled_putc(i, '-');
         pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
                 readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
                 readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));