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-rw-r--r--arch/mips/txx9/generic/Makefile12
-rw-r--r--arch/mips/txx9/generic/dbgio.c48
-rw-r--r--arch/mips/txx9/generic/irq_tx4927.c37
-rw-r--r--arch/mips/txx9/generic/irq_tx4938.c25
-rw-r--r--arch/mips/txx9/generic/mem_tx4927.c77
-rw-r--r--arch/mips/txx9/generic/pci.c388
-rw-r--r--arch/mips/txx9/generic/setup.c246
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c194
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c259
-rw-r--r--arch/mips/txx9/generic/smsc_fdc37m81x.c172
10 files changed, 1458 insertions, 0 deletions
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
new file mode 100644
index 00000000000..9c120771e65
--- /dev/null
+++ b/arch/mips/txx9/generic/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for common code for TXx9 based systems
3#
4
5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
10obj-$(CONFIG_KGDB) += dbgio.o
11
12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/dbgio.c b/arch/mips/txx9/generic/dbgio.c
new file mode 100644
index 00000000000..33b9c672a32
--- /dev/null
+++ b/arch/mips/txx9/generic/dbgio.c
@@ -0,0 +1,48 @@
1/*
2 * linux/arch/mips/tx4938/common/dbgio.c
3 *
4 * kgdb interface for gdb
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2005 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
32 */
33
34#include <linux/types>
35
36extern u8 txx9_sio_kdbg_rd(void);
37extern int txx9_sio_kdbg_wr( u8 ch );
38
39u8 getDebugChar(void)
40{
41 return (txx9_sio_kdbg_rd());
42}
43
44int putDebugChar(u8 byte)
45{
46 return (txx9_sio_kdbg_wr(byte));
47}
48
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
new file mode 100644
index 00000000000..cbea1fdde82
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -0,0 +1,37 @@
1/*
2 * Common tx4927 irq handler
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
14 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
16 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
17 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
18 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
19 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
20 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <asm/irq_cpu.h>
29#include <asm/txx9/tx4927.h>
30
31void __init tx4927_irq_init(void)
32{
33 mips_cpu_irq_init();
34 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
36 handle_simple_irq);
37}
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
new file mode 100644
index 00000000000..6eac684bf19
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -0,0 +1,25 @@
1/*
2 * linux/arch/mips/tx4938/common/irq.c
3 *
4 * Common tx4938 irq handler
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <asm/irq_cpu.h>
17#include <asm/txx9/tx4938.h>
18
19void __init tx4938_irq_init(void)
20{
21 mips_cpu_irq_init();
22 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
24 handle_simple_irq);
25}
diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c
new file mode 100644
index 00000000000..ef6ea6e9787
--- /dev/null
+++ b/arch/mips/txx9/generic/mem_tx4927.c
@@ -0,0 +1,77 @@
1/*
2 * linux/arch/mips/txx9/generic/mem_tx4927.c
3 *
4 * common tx4927 memory interface
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2001-2002 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */
31
32#include <linux/init.h>
33#include <linux/types.h>
34#include <linux/io.h>
35#include <asm/txx9/tx4927.h>
36
37static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr)
38{
39 u64 val;
40 unsigned int sdccr_ce;
41 unsigned int sdccr_bs;
42 unsigned int sdccr_rs;
43 unsigned int sdccr_cs;
44 unsigned int sdccr_mw;
45 unsigned int bs = 0;
46 unsigned int rs = 0;
47 unsigned int cs = 0;
48 unsigned int mw = 0;
49
50 val = __raw_readq(addr);
51
52 /* MVMCP -- need #defs for these bits masks */
53 sdccr_ce = ((val & (1 << 10)) >> 10);
54 sdccr_bs = ((val & (1 << 8)) >> 8);
55 sdccr_rs = ((val & (3 << 5)) >> 5);
56 sdccr_cs = ((val & (7 << 2)) >> 2);
57 sdccr_mw = ((val & (1 << 0)) >> 0);
58
59 if (sdccr_ce) {
60 bs = 2 << sdccr_bs;
61 rs = 2048 << sdccr_rs;
62 cs = 256 << sdccr_cs;
63 mw = 8 >> sdccr_mw;
64 }
65
66 return rs * cs * mw * bs;
67}
68
69unsigned int __init tx4927_get_mem_size(void)
70{
71 unsigned int total = 0;
72 int i;
73
74 for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++)
75 total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]);
76 return total;
77}
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
new file mode 100644
index 00000000000..0b92d8c1320
--- /dev/null
+++ b/arch/mips/txx9/generic/pci.c
@@ -0,0 +1,388 @@
1/*
2 * linux/arch/mips/txx9/pci.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
5 * linux/arch/mips/txx9/rbtx4938/setup.c,
6 * and RBTX49xx patch from CELF patch archive.
7 *
8 * Copyright 2001-2005 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/delay.h>
17#include <linux/jiffies.h>
18#include <linux/io.h>
19#include <asm/txx9/generic.h>
20#include <asm/txx9/pci.h>
21#ifdef CONFIG_TOSHIBA_FPCIB0
22#include <linux/interrupt.h>
23#include <asm/i8259.h>
24#include <asm/txx9/smsc_fdc37m81x.h>
25#endif
26
27static int __init
28early_read_config_word(struct pci_controller *hose,
29 int top_bus, int bus, int devfn, int offset, u16 *value)
30{
31 struct pci_dev fake_dev;
32 struct pci_bus fake_bus;
33
34 fake_dev.bus = &fake_bus;
35 fake_dev.sysdata = hose;
36 fake_dev.devfn = devfn;
37 fake_bus.number = bus;
38 fake_bus.sysdata = hose;
39 fake_bus.ops = hose->pci_ops;
40
41 if (bus != top_bus)
42 /* Fake a parent bus structure. */
43 fake_bus.parent = &fake_bus;
44 else
45 fake_bus.parent = NULL;
46
47 return pci_read_config_word(&fake_dev, offset, value);
48}
49
50int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
51 int current_bus)
52{
53 u32 pci_devfn;
54 unsigned short vid;
55 int cap66 = -1;
56 u16 stat;
57
58 /* It seems SLC90E66 needs some time after PCI reset... */
59 mdelay(80);
60
61 printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
62
63 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
64 if (PCI_FUNC(pci_devfn))
65 continue;
66 if (early_read_config_word(hose, top_bus, current_bus,
67 pci_devfn, PCI_VENDOR_ID, &vid) !=
68 PCIBIOS_SUCCESSFUL)
69 continue;
70 if (vid == 0xffff)
71 continue;
72
73 /* check 66MHz capability */
74 if (cap66 < 0)
75 cap66 = 1;
76 if (cap66) {
77 early_read_config_word(hose, top_bus, current_bus,
78 pci_devfn, PCI_STATUS, &stat);
79 if (!(stat & PCI_STATUS_66MHZ)) {
80 printk(KERN_DEBUG
81 "PCI: %02x:%02x not 66MHz capable.\n",
82 current_bus, pci_devfn);
83 cap66 = 0;
84 break;
85 }
86 }
87 }
88 return cap66 > 0;
89}
90
91static struct resource primary_pci_mem_res[2] = {
92 { .name = "PCI MEM" },
93 { .name = "PCI MMIO" },
94};
95static struct resource primary_pci_io_res = { .name = "PCI IO" };
96struct pci_controller txx9_primary_pcic = {
97 .mem_resource = &primary_pci_mem_res[0],
98 .io_resource = &primary_pci_io_res,
99};
100
101#ifdef CONFIG_64BIT
102int txx9_pci_mem_high __initdata = 1;
103#else
104int txx9_pci_mem_high __initdata;
105#endif
106
107/*
108 * allocate pci_controller and resources.
109 * mem_base, io_base: physical addresss. 0 for auto assignment.
110 * mem_size and io_size means max size on auto assignment.
111 * pcic must be &txx9_primary_pcic or NULL.
112 */
113struct pci_controller *__init
114txx9_alloc_pci_controller(struct pci_controller *pcic,
115 unsigned long mem_base, unsigned long mem_size,
116 unsigned long io_base, unsigned long io_size)
117{
118 struct pcic {
119 struct pci_controller c;
120 struct resource r_mem[2];
121 struct resource r_io;
122 } *new = NULL;
123 int min_size = 0x10000;
124
125 if (!pcic) {
126 new = kzalloc(sizeof(*new), GFP_KERNEL);
127 if (!new)
128 return NULL;
129 new->r_mem[0].name = "PCI mem";
130 new->r_mem[1].name = "PCI mmio";
131 new->r_io.name = "PCI io";
132 new->c.mem_resource = new->r_mem;
133 new->c.io_resource = &new->r_io;
134 pcic = &new->c;
135 } else
136 BUG_ON(pcic != &txx9_primary_pcic);
137 pcic->io_resource->flags = IORESOURCE_IO;
138
139 /*
140 * for auto assignment, first search a (big) region for PCI
141 * MEM, then search a region for PCI IO.
142 */
143 if (mem_base) {
144 pcic->mem_resource[0].start = mem_base;
145 pcic->mem_resource[0].end = mem_base + mem_size - 1;
146 if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
147 goto free_and_exit;
148 } else {
149 unsigned long min = 0, max = 0x20000000; /* low 512MB */
150 if (!mem_size) {
151 /* default size for auto assignment */
152 if (txx9_pci_mem_high)
153 mem_size = 0x20000000; /* mem:512M(max) */
154 else
155 mem_size = 0x08000000; /* mem:128M(max) */
156 }
157 if (txx9_pci_mem_high) {
158 min = 0x20000000;
159 max = 0xe0000000;
160 }
161 /* search free region for PCI MEM */
162 for (; mem_size >= min_size; mem_size /= 2) {
163 if (allocate_resource(&iomem_resource,
164 &pcic->mem_resource[0],
165 mem_size, min, max,
166 mem_size, NULL, NULL) == 0)
167 break;
168 }
169 if (mem_size < min_size)
170 goto free_and_exit;
171 }
172
173 pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
174 if (io_base) {
175 pcic->mem_resource[1].start = io_base;
176 pcic->mem_resource[1].end = io_base + io_size - 1;
177 if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
178 goto release_and_exit;
179 } else {
180 if (!io_size)
181 /* default size for auto assignment */
182 io_size = 0x01000000; /* io:16M(max) */
183 /* search free region for PCI IO in low 512MB */
184 for (; io_size >= min_size; io_size /= 2) {
185 if (allocate_resource(&iomem_resource,
186 &pcic->mem_resource[1],
187 io_size, 0, 0x20000000,
188 io_size, NULL, NULL) == 0)
189 break;
190 }
191 if (io_size < min_size)
192 goto release_and_exit;
193 io_base = pcic->mem_resource[1].start;
194 }
195
196 pcic->mem_resource[0].flags = IORESOURCE_MEM;
197 if (pcic == &txx9_primary_pcic &&
198 mips_io_port_base == (unsigned long)-1) {
199 /* map ioport 0 to PCI I/O space address 0 */
200 set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
201 pcic->io_resource->start = 0;
202 pcic->io_offset = 0; /* busaddr == ioaddr */
203 pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
204 } else {
205 /* physaddr to ioaddr */
206 pcic->io_resource->start =
207 io_base - (mips_io_port_base - IO_BASE);
208 pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
209 pcic->io_map_base = mips_io_port_base;
210 }
211 pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
212
213 pcic->mem_offset = 0; /* busaddr == physaddr */
214
215 printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n",
216 (unsigned long long)pcic->mem_resource[1].start,
217 (unsigned long long)pcic->mem_resource[1].end,
218 (unsigned long long)pcic->mem_resource[0].start,
219 (unsigned long long)pcic->mem_resource[0].end);
220
221 /* register_pci_controller() will request MEM resource */
222 release_resource(&pcic->mem_resource[0]);
223 return pcic;
224 release_and_exit:
225 release_resource(&pcic->mem_resource[0]);
226 free_and_exit:
227 kfree(new);
228 printk(KERN_ERR "PCI: Failed to allocate resources.\n");
229 return NULL;
230}
231
232static int __init
233txx9_arch_pci_init(void)
234{
235 PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */
236 return 0;
237}
238arch_initcall(txx9_arch_pci_init);
239
240/* IRQ/IDSEL mapping */
241int txx9_pci_option =
242#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
243 TXX9_PCI_OPT_PICMG |
244#endif
245 TXX9_PCI_OPT_CLK_AUTO;
246
247enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
248
249#ifdef CONFIG_TOSHIBA_FPCIB0
250static irqreturn_t i8259_interrupt(int irq, void *dev_id)
251{
252 int isairq;
253
254 isairq = i8259_irq();
255 if (unlikely(isairq <= I8259A_IRQ_BASE))
256 return IRQ_NONE;
257 generic_handle_irq(isairq);
258 return IRQ_HANDLED;
259}
260
261static int __init
262txx9_i8259_irq_setup(int irq)
263{
264 int err;
265
266 init_i8259_irqs();
267 err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED,
268 "cascade(i8259)", (void *)(long)irq);
269 if (!err)
270 printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
271 return err;
272}
273
274static void __init quirk_slc90e66_bridge(struct pci_dev *dev)
275{
276 int irq; /* PCI/ISA Bridge interrupt */
277 u8 reg_64;
278 u32 reg_b0;
279 u8 reg_e1;
280 irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
281 if (!irq)
282 return;
283 txx9_i8259_irq_setup(irq);
284 pci_read_config_byte(dev, 0x64, &reg_64);
285 pci_read_config_dword(dev, 0xb0, &reg_b0);
286 pci_read_config_byte(dev, 0xe1, &reg_e1);
287 /* serial irq control */
288 reg_64 = 0xd0;
289 /* serial irq pin */
290 reg_b0 |= 0x00010000;
291 /* ide irq on isa14 */
292 reg_e1 &= 0xf0;
293 reg_e1 |= 0x0d;
294 pci_write_config_byte(dev, 0x64, reg_64);
295 pci_write_config_dword(dev, 0xb0, reg_b0);
296 pci_write_config_byte(dev, 0xe1, reg_e1);
297
298 smsc_fdc37m81x_init(0x3f0);
299 smsc_fdc37m81x_config_beg();
300 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
301 SMSC_FDC37M81X_KBD);
302 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
303 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
304 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
305 1);
306 smsc_fdc37m81x_config_end();
307}
308
309static void quirk_slc90e66_ide(struct pci_dev *dev)
310{
311 unsigned char dat;
312 int regs[2] = {0x41, 0x43};
313 int i;
314
315 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
316 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
317 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
318 printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat);
319 /* enable SMSC SLC90E66 IDE */
320 for (i = 0; i < ARRAY_SIZE(regs); i++) {
321 pci_read_config_byte(dev, regs[i], &dat);
322 pci_write_config_byte(dev, regs[i], dat | 0x80);
323 pci_read_config_byte(dev, regs[i], &dat);
324 printk(KERN_CONT " IDETIM%d %02x", i, dat);
325 }
326 pci_read_config_byte(dev, 0x5c, &dat);
327 /*
328 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
329 *
330 * This line of code is intended to provide the user with a work
331 * around solution to the anomalies cited in SMSC's anomaly sheet
332 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
333 *
334 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
335 */
336 dat |= 0x01;
337 pci_write_config_byte(dev, regs[i], dat);
338 pci_read_config_byte(dev, 0x5c, &dat);
339 printk(KERN_CONT " REG5C %02x", dat);
340 printk(KERN_CONT "\n");
341}
342#endif /* CONFIG_TOSHIBA_FPCIB0 */
343
344static void final_fixup(struct pci_dev *dev)
345{
346 unsigned char bist;
347
348 /* Do build-in self test */
349 if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
350 (bist & PCI_BIST_CAPABLE)) {
351 unsigned long timeout;
352 pci_set_power_state(dev, PCI_D0);
353 printk(KERN_INFO "PCI: %s BIST...", pci_name(dev));
354 pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
355 timeout = jiffies + HZ * 2; /* timeout after 2 sec */
356 do {
357 pci_read_config_byte(dev, PCI_BIST, &bist);
358 if (time_after(jiffies, timeout))
359 break;
360 } while (bist & PCI_BIST_START);
361 if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
362 printk(KERN_CONT "failed. (0x%x)\n", bist);
363 else
364 printk(KERN_CONT "OK.\n");
365 }
366}
367
368#ifdef CONFIG_TOSHIBA_FPCIB0
369#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
370DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
371 quirk_slc90e66_bridge);
372DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
373 quirk_slc90e66_ide);
374DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
375 quirk_slc90e66_ide);
376#endif
377DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
378DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
379
380int pcibios_plat_dev_init(struct pci_dev *dev)
381{
382 return 0;
383}
384
385int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
386{
387 return txx9_board_vec->pci_map_irq(dev, slot, pin);
388}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
new file mode 100644
index 00000000000..8c60c78b9a9
--- /dev/null
+++ b/arch/mips/txx9/generic/setup.c
@@ -0,0 +1,246 @@
1/*
2 * linux/arch/mips/txx9/generic/setup.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
5 * and RBTX49xx patch from CELF patch archive.
6 *
7 * 2003-2005 (c) MontaVista Software, Inc.
8 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/string.h>
19#include <linux/module.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/gpio.h>
23#include <asm/bootinfo.h>
24#include <asm/time.h>
25#include <asm/txx9/generic.h>
26#ifdef CONFIG_CPU_TX49XX
27#include <asm/txx9/tx4938.h>
28#endif
29
30/* EBUSC settings of TX4927, etc. */
31struct resource txx9_ce_res[8];
32static char txx9_ce_res_name[8][4]; /* "CEn" */
33
34/* pcode, internal register */
35unsigned int txx9_pcode;
36char txx9_pcode_str[8];
37static struct resource txx9_reg_res = {
38 .name = txx9_pcode_str,
39 .flags = IORESOURCE_MEM,
40};
41void __init
42txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
43{
44 int i;
45
46 for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
47 sprintf(txx9_ce_res_name[i], "CE%d", i);
48 txx9_ce_res[i].flags = IORESOURCE_MEM;
49 txx9_ce_res[i].name = txx9_ce_res_name[i];
50 }
51
52 sprintf(txx9_pcode_str, "TX%x", pcode);
53 if (base) {
54 txx9_reg_res.start = base & 0xfffffffffULL;
55 txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
56 request_resource(&iomem_resource, &txx9_reg_res);
57 }
58}
59
60/* clocks */
61unsigned int txx9_master_clock;
62unsigned int txx9_cpu_clock;
63unsigned int txx9_gbus_clock;
64
65int txx9_ccfg_toeon __initdata = 1;
66
67/* Minimum CLK support */
68
69struct clk *clk_get(struct device *dev, const char *id)
70{
71 if (!strcmp(id, "spi-baseclk"))
72 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4);
73 if (!strcmp(id, "imbus_clk"))
74 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
75 return ERR_PTR(-ENOENT);
76}
77EXPORT_SYMBOL(clk_get);
78
79int clk_enable(struct clk *clk)
80{
81 return 0;
82}
83EXPORT_SYMBOL(clk_enable);
84
85void clk_disable(struct clk *clk)
86{
87}
88EXPORT_SYMBOL(clk_disable);
89
90unsigned long clk_get_rate(struct clk *clk)
91{
92 return (unsigned long)clk;
93}
94EXPORT_SYMBOL(clk_get_rate);
95
96void clk_put(struct clk *clk)
97{
98}
99EXPORT_SYMBOL(clk_put);
100
101/* GPIO support */
102
103#ifdef CONFIG_GENERIC_GPIO
104int gpio_to_irq(unsigned gpio)
105{
106 return -EINVAL;
107}
108EXPORT_SYMBOL(gpio_to_irq);
109
110int irq_to_gpio(unsigned irq)
111{
112 return -EINVAL;
113}
114EXPORT_SYMBOL(irq_to_gpio);
115#endif
116
117extern struct txx9_board_vec jmr3927_vec;
118extern struct txx9_board_vec rbtx4927_vec;
119extern struct txx9_board_vec rbtx4937_vec;
120extern struct txx9_board_vec rbtx4938_vec;
121
122struct txx9_board_vec *txx9_board_vec __initdata;
123static char txx9_system_type[32];
124
125void __init prom_init_cmdline(void)
126{
127 int argc = (int)fw_arg0;
128 char **argv = (char **)fw_arg1;
129 int i; /* Always ignore the "-c" at argv[0] */
130#ifdef CONFIG_64BIT
131 char *fixed_argv[32];
132 for (i = 0; i < argc; i++)
133 fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i));
134 argv = fixed_argv;
135#endif
136
137 /* ignore all built-in args if any f/w args given */
138 if (argc > 1)
139 *arcs_cmdline = '\0';
140
141 for (i = 1; i < argc; i++) {
142 if (i != 1)
143 strcat(arcs_cmdline, " ");
144 strcat(arcs_cmdline, argv[i]);
145 }
146}
147
148void __init prom_init(void)
149{
150#ifdef CONFIG_CPU_TX39XX
151 txx9_board_vec = &jmr3927_vec;
152#endif
153#ifdef CONFIG_CPU_TX49XX
154 switch (TX4938_REV_PCODE()) {
155#ifdef CONFIG_TOSHIBA_RBTX4927
156 case 0x4927:
157 txx9_board_vec = &rbtx4927_vec;
158 break;
159 case 0x4937:
160 txx9_board_vec = &rbtx4937_vec;
161 break;
162#endif
163#ifdef CONFIG_TOSHIBA_RBTX4938
164 case 0x4938:
165 txx9_board_vec = &rbtx4938_vec;
166 break;
167#endif
168 }
169#endif
170
171 strcpy(txx9_system_type, txx9_board_vec->system);
172
173 txx9_board_vec->prom_init();
174}
175
176void __init prom_free_prom_memory(void)
177{
178}
179
180const char *get_system_type(void)
181{
182 return txx9_system_type;
183}
184
185char * __init prom_getcmdline(void)
186{
187 return &(arcs_cmdline[0]);
188}
189
190/* wrappers */
191void __init plat_mem_setup(void)
192{
193 ioport_resource.start = 0;
194 ioport_resource.end = ~0UL; /* no limit */
195 iomem_resource.start = 0;
196 iomem_resource.end = ~0UL; /* no limit */
197 txx9_board_vec->mem_setup();
198}
199
200void __init arch_init_irq(void)
201{
202 txx9_board_vec->irq_setup();
203}
204
205void __init plat_time_init(void)
206{
207 txx9_board_vec->time_init();
208}
209
210static int __init _txx9_arch_init(void)
211{
212 if (txx9_board_vec->arch_init)
213 txx9_board_vec->arch_init();
214 return 0;
215}
216arch_initcall(_txx9_arch_init);
217
218static int __init _txx9_device_init(void)
219{
220 if (txx9_board_vec->device_init)
221 txx9_board_vec->device_init();
222 return 0;
223}
224device_initcall(_txx9_device_init);
225
226int (*txx9_irq_dispatch)(int pending);
227asmlinkage void plat_irq_dispatch(void)
228{
229 int pending = read_c0_status() & read_c0_cause() & ST0_IM;
230 int irq = txx9_irq_dispatch(pending);
231
232 if (likely(irq >= 0))
233 do_IRQ(irq);
234 else
235 spurious_interrupt();
236}
237
238/* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */
239#ifdef NEEDS_TXX9_SWIZZLE_ADDR_B
240static unsigned long __swizzle_addr_none(unsigned long port)
241{
242 return port;
243}
244unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
245EXPORT_SYMBOL(__swizzle_addr_b);
246#endif
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
new file mode 100644
index 00000000000..89d6e28add9
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -0,0 +1,194 @@
1/*
2 * TX4927 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4927.h>
23
24void __init tx4927_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4927_ccfg_set(TX4927_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4927_ccfg_set(TX4927_CCFG_WR);
30}
31
32static struct resource tx4927_sdram_resource[4];
33
34void __init tx4927_setup(void)
35{
36 int i;
37 __u32 divmode;
38 int cpuclk = 0;
39 u64 ccfg;
40
41 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
42 TX4927_REG_SIZE);
43
44 /* SDRAMC,EBUSC are configured by PROM */
45 for (i = 0; i < 8; i++) {
46 if (!(TX4927_EBUSC_CR(i) & 0x8))
47 continue; /* disabled */
48 txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
49 txx9_ce_res[i].end =
50 txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
51 request_resource(&iomem_resource, &txx9_ce_res[i]);
52 }
53
54 /* clocks */
55 ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
56 if (txx9_master_clock) {
57 /* calculate gbus_clock and cpu_clock from master_clock */
58 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
59 switch (divmode) {
60 case TX4927_CCFG_DIVMODE_8:
61 case TX4927_CCFG_DIVMODE_10:
62 case TX4927_CCFG_DIVMODE_12:
63 case TX4927_CCFG_DIVMODE_16:
64 txx9_gbus_clock = txx9_master_clock * 4; break;
65 default:
66 txx9_gbus_clock = txx9_master_clock;
67 }
68 switch (divmode) {
69 case TX4927_CCFG_DIVMODE_2:
70 case TX4927_CCFG_DIVMODE_8:
71 cpuclk = txx9_gbus_clock * 2; break;
72 case TX4927_CCFG_DIVMODE_2_5:
73 case TX4927_CCFG_DIVMODE_10:
74 cpuclk = txx9_gbus_clock * 5 / 2; break;
75 case TX4927_CCFG_DIVMODE_3:
76 case TX4927_CCFG_DIVMODE_12:
77 cpuclk = txx9_gbus_clock * 3; break;
78 case TX4927_CCFG_DIVMODE_4:
79 case TX4927_CCFG_DIVMODE_16:
80 cpuclk = txx9_gbus_clock * 4; break;
81 }
82 txx9_cpu_clock = cpuclk;
83 } else {
84 if (txx9_cpu_clock == 0)
85 txx9_cpu_clock = 200000000; /* 200MHz */
86 /* calculate gbus_clock and master_clock from cpu_clock */
87 cpuclk = txx9_cpu_clock;
88 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
89 switch (divmode) {
90 case TX4927_CCFG_DIVMODE_2:
91 case TX4927_CCFG_DIVMODE_8:
92 txx9_gbus_clock = cpuclk / 2; break;
93 case TX4927_CCFG_DIVMODE_2_5:
94 case TX4927_CCFG_DIVMODE_10:
95 txx9_gbus_clock = cpuclk * 2 / 5; break;
96 case TX4927_CCFG_DIVMODE_3:
97 case TX4927_CCFG_DIVMODE_12:
98 txx9_gbus_clock = cpuclk / 3; break;
99 case TX4927_CCFG_DIVMODE_4:
100 case TX4927_CCFG_DIVMODE_16:
101 txx9_gbus_clock = cpuclk / 4; break;
102 }
103 switch (divmode) {
104 case TX4927_CCFG_DIVMODE_8:
105 case TX4927_CCFG_DIVMODE_10:
106 case TX4927_CCFG_DIVMODE_12:
107 case TX4927_CCFG_DIVMODE_16:
108 txx9_master_clock = txx9_gbus_clock / 4; break;
109 default:
110 txx9_master_clock = txx9_gbus_clock;
111 }
112 }
113 /* change default value to udelay/mdelay take reasonable time */
114 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
115
116 /* CCFG */
117 tx4927_wdr_init();
118 /* clear BusErrorOnWrite flag (W1C) */
119 tx4927_ccfg_set(TX4927_CCFG_BEOW);
120 /* enable Timeout BusError */
121 if (txx9_ccfg_toeon)
122 tx4927_ccfg_set(TX4927_CCFG_TOE);
123
124 /* DMA selection */
125 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
126
127 /* Use external clock for external arbiter */
128 if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
129 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
130
131 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
132 txx9_pcode_str,
133 (cpuclk + 500000) / 1000000,
134 (txx9_master_clock + 500000) / 1000000,
135 (__u32)____raw_readq(&tx4927_ccfgptr->crir),
136 (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
137 (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
138
139 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
140 for (i = 0; i < 4; i++) {
141 __u64 cr = TX4927_SDRAMC_CR(i);
142 unsigned long base, size;
143 if (!((__u32)cr & 0x00000400))
144 continue; /* disabled */
145 base = (unsigned long)(cr >> 49) << 21;
146 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
147 printk(" CR%d:%016llx", i, (unsigned long long)cr);
148 tx4927_sdram_resource[i].name = "SDRAM";
149 tx4927_sdram_resource[i].start = base;
150 tx4927_sdram_resource[i].end = base + size - 1;
151 tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
152 request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
153 }
154 printk(" TR:%09llx\n",
155 (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
156
157 /* TMR */
158 /* disable all timers */
159 for (i = 0; i < TX4927_NR_TMR; i++)
160 txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
161
162 /* PIO */
163 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
164 __raw_writel(0, &tx4927_pioptr->maskcpu);
165 __raw_writel(0, &tx4927_pioptr->maskext);
166}
167
168void __init tx4927_time_init(unsigned int tmrnr)
169{
170 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
171 txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
172 TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
173 TXX9_IMCLK);
174}
175
176void __init tx4927_setup_serial(void)
177{
178#ifdef CONFIG_SERIAL_TXX9
179 int i;
180 struct uart_port req;
181
182 for (i = 0; i < 2; i++) {
183 memset(&req, 0, sizeof(req));
184 req.line = i;
185 req.iotype = UPIO_MEM;
186 req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);
187 req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;
188 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
189 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
190 req.uartclk = TXX9_IMCLK;
191 early_serial_txx9_setup(&req);
192 }
193#endif /* CONFIG_SERIAL_TXX9 */
194}
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
new file mode 100644
index 00000000000..317378d8579
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -0,0 +1,259 @@
1/*
2 * TX4938/4937 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4938.h>
23
24void __init tx4938_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4938_ccfg_set(TX4938_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4938_ccfg_set(TX4938_CCFG_WR);
30}
31
32static struct resource tx4938_sdram_resource[4];
33static struct resource tx4938_sram_resource;
34
35#define TX4938_SRAM_SIZE 0x800
36
37void __init tx4938_setup(void)
38{
39 int i;
40 __u32 divmode;
41 int cpuclk = 0;
42 u64 ccfg;
43
44 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
45 TX4938_REG_SIZE);
46
47 /* SDRAMC,EBUSC are configured by PROM */
48 for (i = 0; i < 8; i++) {
49 if (!(TX4938_EBUSC_CR(i) & 0x8))
50 continue; /* disabled */
51 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
52 txx9_ce_res[i].end =
53 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
54 request_resource(&iomem_resource, &txx9_ce_res[i]);
55 }
56
57 /* clocks */
58 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
59 if (txx9_master_clock) {
60 /* calculate gbus_clock and cpu_clock from master_clock */
61 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
62 switch (divmode) {
63 case TX4938_CCFG_DIVMODE_8:
64 case TX4938_CCFG_DIVMODE_10:
65 case TX4938_CCFG_DIVMODE_12:
66 case TX4938_CCFG_DIVMODE_16:
67 case TX4938_CCFG_DIVMODE_18:
68 txx9_gbus_clock = txx9_master_clock * 4; break;
69 default:
70 txx9_gbus_clock = txx9_master_clock;
71 }
72 switch (divmode) {
73 case TX4938_CCFG_DIVMODE_2:
74 case TX4938_CCFG_DIVMODE_8:
75 cpuclk = txx9_gbus_clock * 2; break;
76 case TX4938_CCFG_DIVMODE_2_5:
77 case TX4938_CCFG_DIVMODE_10:
78 cpuclk = txx9_gbus_clock * 5 / 2; break;
79 case TX4938_CCFG_DIVMODE_3:
80 case TX4938_CCFG_DIVMODE_12:
81 cpuclk = txx9_gbus_clock * 3; break;
82 case TX4938_CCFG_DIVMODE_4:
83 case TX4938_CCFG_DIVMODE_16:
84 cpuclk = txx9_gbus_clock * 4; break;
85 case TX4938_CCFG_DIVMODE_4_5:
86 case TX4938_CCFG_DIVMODE_18:
87 cpuclk = txx9_gbus_clock * 9 / 2; break;
88 }
89 txx9_cpu_clock = cpuclk;
90 } else {
91 if (txx9_cpu_clock == 0)
92 txx9_cpu_clock = 300000000; /* 300MHz */
93 /* calculate gbus_clock and master_clock from cpu_clock */
94 cpuclk = txx9_cpu_clock;
95 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
96 switch (divmode) {
97 case TX4938_CCFG_DIVMODE_2:
98 case TX4938_CCFG_DIVMODE_8:
99 txx9_gbus_clock = cpuclk / 2; break;
100 case TX4938_CCFG_DIVMODE_2_5:
101 case TX4938_CCFG_DIVMODE_10:
102 txx9_gbus_clock = cpuclk * 2 / 5; break;
103 case TX4938_CCFG_DIVMODE_3:
104 case TX4938_CCFG_DIVMODE_12:
105 txx9_gbus_clock = cpuclk / 3; break;
106 case TX4938_CCFG_DIVMODE_4:
107 case TX4938_CCFG_DIVMODE_16:
108 txx9_gbus_clock = cpuclk / 4; break;
109 case TX4938_CCFG_DIVMODE_4_5:
110 case TX4938_CCFG_DIVMODE_18:
111 txx9_gbus_clock = cpuclk * 2 / 9; break;
112 }
113 switch (divmode) {
114 case TX4938_CCFG_DIVMODE_8:
115 case TX4938_CCFG_DIVMODE_10:
116 case TX4938_CCFG_DIVMODE_12:
117 case TX4938_CCFG_DIVMODE_16:
118 case TX4938_CCFG_DIVMODE_18:
119 txx9_master_clock = txx9_gbus_clock / 4; break;
120 default:
121 txx9_master_clock = txx9_gbus_clock;
122 }
123 }
124 /* change default value to udelay/mdelay take reasonable time */
125 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
126
127 /* CCFG */
128 tx4938_wdr_init();
129 /* clear BusErrorOnWrite flag (W1C) */
130 tx4938_ccfg_set(TX4938_CCFG_BEOW);
131 /* enable Timeout BusError */
132 if (txx9_ccfg_toeon)
133 tx4938_ccfg_set(TX4938_CCFG_TOE);
134
135 /* DMA selection */
136 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
137
138 /* Use external clock for external arbiter */
139 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
140 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
141
142 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
143 txx9_pcode_str,
144 (cpuclk + 500000) / 1000000,
145 (txx9_master_clock + 500000) / 1000000,
146 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
147 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
148 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
149
150 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
151 for (i = 0; i < 4; i++) {
152 __u64 cr = TX4938_SDRAMC_CR(i);
153 unsigned long base, size;
154 if (!((__u32)cr & 0x00000400))
155 continue; /* disabled */
156 base = (unsigned long)(cr >> 49) << 21;
157 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
158 printk(" CR%d:%016llx", i, (unsigned long long)cr);
159 tx4938_sdram_resource[i].name = "SDRAM";
160 tx4938_sdram_resource[i].start = base;
161 tx4938_sdram_resource[i].end = base + size - 1;
162 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
163 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
164 }
165 printk(" TR:%09llx\n",
166 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
167
168 /* SRAM */
169 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
170 unsigned int size = TX4938_SRAM_SIZE;
171 tx4938_sram_resource.name = "SRAM";
172 tx4938_sram_resource.start =
173 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
174 & ~(size - 1);
175 tx4938_sram_resource.end =
176 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
177 tx4938_sram_resource.flags = IORESOURCE_MEM;
178 request_resource(&iomem_resource, &tx4938_sram_resource);
179 }
180
181 /* TMR */
182 /* disable all timers */
183 for (i = 0; i < TX4938_NR_TMR; i++)
184 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
185
186 /* DMA */
187 for (i = 0; i < 2; i++)
188 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
189 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
190
191 /* PIO */
192 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
193 __raw_writel(0, &tx4938_pioptr->maskcpu);
194 __raw_writel(0, &tx4938_pioptr->maskext);
195
196 if (txx9_pcode == 0x4938) {
197 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
198 /* set PCIC1 reset */
199 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
200 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
201 mdelay(1); /* at least 128 cpu clock */
202 /* clear PCIC1 reset */
203 txx9_clear64(&tx4938_ccfgptr->clkctr,
204 TX4938_CLKCTR_PCIC1RST);
205 } else {
206 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
207 /* stop PCIC1 */
208 txx9_set64(&tx4938_ccfgptr->clkctr,
209 TX4938_CLKCTR_PCIC1CKD);
210 }
211 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
212 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
213 txx9_set64(&tx4938_ccfgptr->clkctr,
214 TX4938_CLKCTR_ETH0RST);
215 txx9_set64(&tx4938_ccfgptr->clkctr,
216 TX4938_CLKCTR_ETH0CKD);
217 }
218 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
219 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
220 txx9_set64(&tx4938_ccfgptr->clkctr,
221 TX4938_CLKCTR_ETH1RST);
222 txx9_set64(&tx4938_ccfgptr->clkctr,
223 TX4938_CLKCTR_ETH1CKD);
224 }
225 }
226}
227
228void __init tx4938_time_init(unsigned int tmrnr)
229{
230 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
231 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
232 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
233 TXX9_IMCLK);
234}
235
236void __init tx4938_setup_serial(void)
237{
238#ifdef CONFIG_SERIAL_TXX9
239 int i;
240 struct uart_port req;
241 unsigned int ch_mask = 0;
242
243 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
244 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
245 for (i = 0; i < 2; i++) {
246 if ((1 << i) & ch_mask)
247 continue;
248 memset(&req, 0, sizeof(req));
249 req.line = i;
250 req.iotype = UPIO_MEM;
251 req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i);
252 req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL;
253 req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i);
254 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
255 req.uartclk = TXX9_IMCLK;
256 early_serial_txx9_setup(&req);
257 }
258#endif /* CONFIG_SERIAL_TXX9 */
259}
diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c
new file mode 100644
index 00000000000..69e487467fa
--- /dev/null
+++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c
@@ -0,0 +1,172 @@
1/*
2 * Interface for smsc fdc48m81x Super IO chip
3 *
4 * Author: MontaVista Software, Inc. source@mvista.com
5 *
6 * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Copyright 2004 (c) MontaVista Software, Inc.
12 */
13#include <linux/init.h>
14#include <linux/types.h>
15#include <asm/io.h>
16#include <asm/txx9/smsc_fdc37m81x.h>
17
18#define DEBUG
19
20/* Common Registers */
21#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
22#define SMSC_FDC37M81X_CONFIG_DATA 0x01
23#define SMSC_FDC37M81X_CONF 0x02
24#define SMSC_FDC37M81X_INDEX 0x03
25#define SMSC_FDC37M81X_DNUM 0x07
26#define SMSC_FDC37M81X_DID 0x20
27#define SMSC_FDC37M81X_DREV 0x21
28#define SMSC_FDC37M81X_PCNT 0x22
29#define SMSC_FDC37M81X_PMGT 0x23
30#define SMSC_FDC37M81X_OSC 0x24
31#define SMSC_FDC37M81X_CONFPA0 0x26
32#define SMSC_FDC37M81X_CONFPA1 0x27
33#define SMSC_FDC37M81X_TEST4 0x2B
34#define SMSC_FDC37M81X_TEST5 0x2C
35#define SMSC_FDC37M81X_TEST1 0x2D
36#define SMSC_FDC37M81X_TEST2 0x2E
37#define SMSC_FDC37M81X_TEST3 0x2F
38
39/* Logical device numbers */
40#define SMSC_FDC37M81X_FDD 0x00
41#define SMSC_FDC37M81X_SERIAL1 0x04
42#define SMSC_FDC37M81X_SERIAL2 0x05
43#define SMSC_FDC37M81X_KBD 0x07
44
45/* Logical device Config Registers */
46#define SMSC_FDC37M81X_ACTIVE 0x30
47#define SMSC_FDC37M81X_BASEADDR0 0x60
48#define SMSC_FDC37M81X_BASEADDR1 0x61
49#define SMSC_FDC37M81X_INT 0x70
50#define SMSC_FDC37M81X_INT2 0x72
51#define SMSC_FDC37M81X_MODE 0xF0
52
53/* Chip Config Values */
54#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
55#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
56#define SMSC_FDC37M81X_CHIP_ID 0x4d
57
58static unsigned long g_smsc_fdc37m81x_base = 0;
59
60static inline unsigned char smsc_fdc37m81x_rd(unsigned char index)
61{
62 outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
63
64 return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA);
65}
66
67static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data)
68{
69 outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
70 outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA);
71}
72
73void smsc_fdc37m81x_config_beg(void)
74{
75 if (g_smsc_fdc37m81x_base) {
76 outb(SMSC_FDC37M81X_CONFIG_ENTER,
77 g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
78 }
79}
80
81void smsc_fdc37m81x_config_end(void)
82{
83 if (g_smsc_fdc37m81x_base)
84 outb(SMSC_FDC37M81X_CONFIG_EXIT,
85 g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
86}
87
88u8 smsc_fdc37m81x_config_get(u8 reg)
89{
90 u8 val = 0;
91
92 if (g_smsc_fdc37m81x_base)
93 val = smsc_fdc37m81x_rd(reg);
94
95 return val;
96}
97
98void smsc_fdc37m81x_config_set(u8 reg, u8 val)
99{
100 if (g_smsc_fdc37m81x_base)
101 smsc_dc37m81x_wr(reg, val);
102}
103
104unsigned long __init smsc_fdc37m81x_init(unsigned long port)
105{
106 const int field = sizeof(unsigned long) * 2;
107 u8 chip_id;
108
109 if (g_smsc_fdc37m81x_base)
110 printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n",
111 field, g_smsc_fdc37m81x_base);
112
113 g_smsc_fdc37m81x_base = port;
114
115 smsc_fdc37m81x_config_beg();
116
117 chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID);
118 if (chip_id == SMSC_FDC37M81X_CHIP_ID)
119 smsc_fdc37m81x_config_end();
120 else {
121 printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n",
122 chip_id);
123 g_smsc_fdc37m81x_base = 0;
124 }
125
126 return g_smsc_fdc37m81x_base;
127}
128
129#ifdef DEBUG
130void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg)
131{
132 printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg,
133 smsc_fdc37m81x_rd(reg));
134}
135
136void smsc_fdc37m81x_config_dump(void)
137{
138 u8 orig;
139 char *fname = "smsc_fdc37m81x_config_dump()";
140
141 smsc_fdc37m81x_config_beg();
142
143 orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM);
144
145 printk("%s: common\n", fname);
146 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
147 SMSC_FDC37M81X_DNUM);
148 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
149 SMSC_FDC37M81X_DID);
150 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
151 SMSC_FDC37M81X_DREV);
152 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
153 SMSC_FDC37M81X_PCNT);
154 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
155 SMSC_FDC37M81X_PMGT);
156
157 printk("%s: keyboard\n", fname);
158 smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD);
159 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
160 SMSC_FDC37M81X_ACTIVE);
161 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
162 SMSC_FDC37M81X_INT);
163 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
164 SMSC_FDC37M81X_INT2);
165 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
166 SMSC_FDC37M81X_LDCR_F0);
167
168 smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig);
169
170 smsc_fdc37m81x_config_end();
171}
172#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 10:09:29 -0500