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-rw-r--r--arch/mips/au1000/common/time.c35
1 files changed, 6 insertions, 29 deletions
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index e122bbc6cd8..bdb6d73b26f 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com 3 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
4 * Copied and modified Carsten Langgaard's time.c 4 * Copied and modified Carsten Langgaard's time.c
5 * 5 *
6 * Carsten Langgaard, carstenl@mips.com 6 * Carsten Langgaard, carstenl@mips.com
@@ -34,23 +34,13 @@
34 34
35#include <linux/types.h> 35#include <linux/types.h>
36#include <linux/init.h> 36#include <linux/init.h>
37#include <linux/kernel_stat.h>
38#include <linux/sched.h>
39#include <linux/spinlock.h> 37#include <linux/spinlock.h>
40#include <linux/hardirq.h>
41 38
42#include <asm/compiler.h>
43#include <asm/mipsregs.h> 39#include <asm/mipsregs.h>
44#include <asm/time.h> 40#include <asm/time.h>
45#include <asm/div64.h>
46#include <asm/mach-au1x00/au1000.h> 41#include <asm/mach-au1x00/au1000.h>
47 42
48#include <linux/mc146818rtc.h> 43static int no_au1xxx_32khz;
49#include <linux/timex.h>
50
51static unsigned long r4k_offset; /* Amount to increment compare reg each time */
52static unsigned long r4k_cur; /* What counter should be at next timer irq */
53int no_au1xxx_32khz;
54extern int allow_au1k_wait; /* default off for CP0 Counter */ 44extern int allow_au1k_wait; /* default off for CP0 Counter */
55 45
56#ifdef CONFIG_PM 46#ifdef CONFIG_PM
@@ -184,7 +174,7 @@ wakeup_counter0_set(int ticks)
184 * "wait" is enabled, and we need to detect if the 32KHz isn't present 174 * "wait" is enabled, and we need to detect if the 32KHz isn't present
185 * but requested......got it? :-) -- Dan 175 * but requested......got it? :-) -- Dan
186 */ 176 */
187unsigned long cal_r4koff(void) 177unsigned long calc_clock(void)
188{ 178{
189 unsigned long cpu_speed; 179 unsigned long cpu_speed;
190 unsigned long flags; 180 unsigned long flags;
@@ -229,19 +219,13 @@ unsigned long cal_r4koff(void)
229 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) 219 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
230 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); 220 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
231 spin_unlock_irqrestore(&time_lock, flags); 221 spin_unlock_irqrestore(&time_lock, flags);
232 return (cpu_speed / HZ); 222 return cpu_speed;
233} 223}
234 224
235void __init plat_time_init(void) 225void __init plat_time_init(void)
236{ 226{
237 unsigned int est_freq; 227 unsigned int est_freq = calc_clock();
238
239 printk("calculating r4koff... ");
240 r4k_offset = cal_r4koff();
241 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
242 228
243 //est_freq = 2*r4k_offset*HZ;
244 est_freq = r4k_offset*HZ;
245 est_freq += 5000; /* round */ 229 est_freq += 5000; /* round */
246 est_freq -= est_freq%10000; 230 est_freq -= est_freq%10000;
247 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 231 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
@@ -249,9 +233,6 @@ void __init plat_time_init(void)
249 set_au1x00_speed(est_freq); 233 set_au1x00_speed(est_freq);
250 set_au1x00_lcd_clock(); // program the LCD clock 234 set_au1x00_lcd_clock(); // program the LCD clock
251 235
252 r4k_cur = (read_c0_count() + r4k_offset);
253 write_c0_compare(r4k_cur);
254
255#ifdef CONFIG_PM 236#ifdef CONFIG_PM
256 /* 237 /*
257 * setup counter 0, since it keeps ticking after a 238 * setup counter 0, since it keeps ticking after a
@@ -265,12 +246,8 @@ void __init plat_time_init(void)
265 * Check to ensure we really have a 32KHz oscillator before 246 * Check to ensure we really have a 32KHz oscillator before
266 * we do this. 247 * we do this.
267 */ 248 */
268 if (no_au1xxx_32khz) { 249 if (no_au1xxx_32khz)
269 printk("WARNING: no 32KHz clock found.\n"); 250 printk("WARNING: no 32KHz clock found.\n");
270
271 /* Ensure we get CPO_COUNTER interrupts. */
272 set_c0_status(IE_IRQ5);
273 }
274 else { 251 else {
275 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); 252 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
276 au_writel(0, SYS_TOYWRITE); 253 au_writel(0, SYS_TOYWRITE);