72 files changed, 1856 insertions, 599 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f1d9297b105..d56d21c0573 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1311,7 +1311,7 @@ config HZ
 config THUMB2_KERNEL
        bool "Compile the kernel in Thumb-2 mode"
-        depends on CPU_V7 && EXPERIMENTAL
+        depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
        select AEABI
        select ARM_ASM_UNIFIED
        help
@@ -1759,7 +1759,7 @@ comment "At least one emulation must be selected"
 config FPE_NWFPE
        bool "NWFPE math emulation"
-        depends on !AEABI || OABI_COMPAT
+        depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
        ---help---
          Say Y to include the NWFPE floating point emulator in the kernel.
          This is necessary to run most binaries. Linux does not currently
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 1bec96e8519..42ff90b46df 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -352,3 +352,4 @@ struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
        return pci_scan_bus(nr, &it8152_ops, sys);
 }
+EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index 21fa272301f..b2f95c72287 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -76,6 +76,7 @@ extern unsigned long it8152_base_address;
  IT8152_PD_IRQ(0)  Audio controller (ACR)
 */
 #define IT8152_IRQ(x)   (IRQ_BOARD_START + (x))
+#define IT8152_LAST_IRQ (IRQ_BOARD_START + 40)
 /* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
 #define IT8152_LD_IRQ_COUNT     9
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 1fc684e70ab..7080e2c8fa6 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -25,9 +25,6 @@ extern void *kmap_high(struct page *page);
 extern void *kmap_high_get(struct page *page);
 extern void kunmap_high(struct page *page);
-extern void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte);
-extern void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte);
 /*
 * The following functions are already defined by <linux/highmem.h>
 * when CONFIG_HIGHMEM is not set.
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 4fc1565e4f9..316bb2b2be3 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -13,9 +13,6 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-/* DO NOT EDIT!! - this file automatically generated
- *                 from .s file by awk -f s2h.awk
- */
 /*  Size definitions
 *  Copyright (C) ARM Limited 1998. All rights reserved.
 */
@@ -25,6 +22,9 @@
 /* handy sizes */
 #define SZ_16                           0x00000010
+#define SZ_32                           0x00000020
+#define SZ_64                           0x00000040
+#define SZ_128                          0x00000080
 #define SZ_256                          0x00000100
 #define SZ_512                          0x00000200
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 1120f18a6b1..80025948b8a 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -150,6 +150,7 @@ extern unsigned int user_debug;
 #define rmb()           dmb()
 #define wmb()           mb()
 #else
+#include <asm/memory.h>
 #define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define wmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 8bfa98757cd..80bf8cd88d7 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -29,6 +29,9 @@ ret_fast_syscall:
        ldr     r1, [tsk, #TI_FLAGS]
        tst     r1, #_TIF_WORK_MASK
        bne     fast_work_pending
+#if defined(CONFIG_IRQSOFF_TRACER)
+        asm_trace_hardirqs_on
+#endif
        /* perform architecture specific actions before user return */
        arch_ret_to_user r1, lr
@@ -65,6 +68,9 @@ ret_slow_syscall:
        tst     r1, #_TIF_WORK_MASK
        bne     work_pending
 no_work_pending:
+#if defined(CONFIG_IRQSOFF_TRACER)
+        asm_trace_hardirqs_on
+#endif
        /* perform architecture specific actions before user return */
        arch_ret_to_user r1, lr
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 07a50357492..fdfa4976b0b 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -3034,11 +3034,11 @@ init_hw_perf_events(void)
                pr_info("no hardware support available\n");
        }
-        perf_pmu_register(&pmu);
+        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
        return 0;
 }
-arch_initcall(init_hw_perf_events);
+early_initcall(init_hw_perf_events);
 /*
 * Callchain handling code.
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 8c195959025..9066473c0eb 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -310,7 +310,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         * All kernel threads share the same mm context; grab a
         * reference and switch to it.
         */
-        atomic_inc(&mm->mm_users);
        atomic_inc(&mm->mm_count);
        current->active_mm = mm;
        cpumask_set_cpu(cpu, mm_cpumask(mm));
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 62d686f0b42..d13add71f72 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
 obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
-obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o
+obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index bba5a560e02..feb65787c30 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -31,6 +31,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/stamp9g20.h>
 #include "sam9_smc.h"
 #include "generic.h"
@@ -38,11 +39,7 @@
 static void __init pcontrol_g20_map_io(void)
 {
-        /* Initialize processor: 18.432 MHz crystal */
+        stamp9g20_map_io();
-        at91sam9260_initialize(18432000);
-        /* DGBU on ttyS0. (Rx, Tx) only TTL -> JTAG connector X7 17,19 ) */
-        at91_register_uart(0, 0, 0);
        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback  A2 */
        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
@@ -54,9 +51,6 @@ static void __init pcontrol_g20_map_io(void)
        /* USART2 on ttyS3. (Rx, Tx)  9bit-Bus  Multidrop-mode  X4 */
        at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
@@ -66,38 +60,6 @@ static void __init init_irq(void)
 }
-/*
- * NAND flash 512MiB 1,8V 8-bit, sector size 128 KiB
- */
-static struct atmel_nand_data __initdata nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-};
-/*
- * Bus timings; unit = 7.57ns
- */
-static struct sam9_smc_config __initdata nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 3,
-};
 static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
        .ncs_read_setup         = 16,
        .nrd_setup              = 18,
@@ -138,14 +100,6 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
        .tdf_cycles             = 1,
 } };
-static void __init add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &nand_smc_config);
-        at91_add_device_nand(&nand_data);
-}
 static void __init add_device_pcontrol(void)
 {
        /* configure chip-select 4 (IO compatible to 8051  X4 ) */
@@ -156,23 +110,6 @@ static void __init add_device_pcontrol(void)
 /*
- * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
- */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-static struct mci_platform_data __initdata mmc_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-        },
-};
-#else
-static struct at91_mmc_data __initdata mmc_data = {
-        .wire4          = 1,
-};
-#endif
-/*
 * USB Host port
 */
 static struct at91_usbh_data __initdata usbh_data = {
@@ -265,42 +202,13 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = {
 };
-/*
- * Dallas 1-Wire  DS2431
- */
-static struct w1_gpio_platform_data w1_gpio_pdata = {
-        .pin            = AT91_PIN_PA29,
-        .is_open_drain  = 1,
-};
-static struct platform_device w1_device = {
-        .name                   = "w1-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &w1_gpio_pdata,
-};
-static void add_wire1(void)
-{
-        at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
-        at91_set_multi_drive(w1_gpio_pdata.pin, 1);
-        platform_device_register(&w1_device);
-}
 static void __init pcontrol_g20_board_init(void)
 {
-        at91_add_device_serial();
+        stamp9g20_board_init();
-        add_device_nand();
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-        at91_add_device_mci(0, &mmc_data);
-#else
-        at91_add_device_mmc(0, &mmc_data);
-#endif
        at91_add_device_usbh(&usbh_data);
        at91_add_device_eth(&macb_data);
        at91_add_device_i2c(pcontrol_g20_i2c_devices,
                ARRAY_SIZE(pcontrol_g20_i2c_devices));
-        add_wire1();
        add_device_pcontrol();
        at91_add_device_spi(pcontrol_g20_spi_devices,
                ARRAY_SIZE(pcontrol_g20_spi_devices));
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 5206eef4a67..f8902b11896 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -32,7 +32,7 @@
 #include "generic.h"
-static void __init portuxg20_map_io(void)
+void __init stamp9g20_map_io(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91sam9260_initialize(18432000);
@@ -40,6 +40,24 @@ static void __init portuxg20_map_io(void)
        /* DGBU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+static void __init stamp9g20evb_map_io(void)
+{
+        stamp9g20_map_io();
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
+                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
+}
+static void __init portuxg20_map_io(void)
+{
+        stamp9g20_map_io();
        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
@@ -56,26 +74,6 @@ static void __init portuxg20_map_io(void)
        /* USART5 on ttyS6. (Rx, Tx only) */
        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-static void __init stamp9g20_map_io(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91sam9260_initialize(18432000);
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
-                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static void __init init_irq(void)
@@ -156,7 +154,7 @@ static struct at91_udc_data __initdata portuxg20_udc_data = {
        .pullup_pin     = 0,            /* pull-up driven by UDC */
 };
-static struct at91_udc_data __initdata stamp9g20_udc_data = {
+static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
        .vbus_pin       = AT91_PIN_PA22,
        .pullup_pin     = 0,            /* pull-up driven by UDC */
 };
@@ -190,7 +188,7 @@ static struct gpio_led portuxg20_leds[] = {
        }
 };
-static struct gpio_led stamp9g20_leds[] = {
+static struct gpio_led stamp9g20evb_leds[] = {
        {
                .name                   = "D8",
                .gpio                   = AT91_PIN_PB18,
@@ -250,7 +248,7 @@ void add_w1(void)
 }
-static void __init generic_board_init(void)
+void __init stamp9g20_board_init(void)
 {
        /* Serial */
        at91_add_device_serial();
@@ -262,34 +260,40 @@ static void __init generic_board_init(void)
 #else
        at91_add_device_mmc(0, &mmc_data);
 #endif
-        /* USB Host */
-        at91_add_device_usbh(&usbh_data);
-        /* Ethernet */
-        at91_add_device_eth(&macb_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
        /* W1 */
        add_w1();
 }
 static void __init portuxg20_board_init(void)
 {
-        generic_board_init();
+        stamp9g20_board_init();
-        /* SPI */
+        /* USB Host */
-        at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
+        at91_add_device_usbh(&usbh_data);
        /* USB Device */
        at91_add_device_udc(&portuxg20_udc_data);
+        /* Ethernet */
+        at91_add_device_eth(&macb_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* SPI */
+        at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
        /* LEDs */
        at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds));
 }
-static void __init stamp9g20_board_init(void)
+static void __init stamp9g20evb_board_init(void)
 {
-        generic_board_init();
+        stamp9g20_board_init();
+        /* USB Host */
+        at91_add_device_usbh(&usbh_data);
        /* USB Device */
-        at91_add_device_udc(&stamp9g20_udc_data);
+        at91_add_device_udc(&stamp9g20evb_udc_data);
+        /* Ethernet */
+        at91_add_device_eth(&macb_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
        /* LEDs */
-        at91_gpio_leds(stamp9g20_leds, ARRAY_SIZE(stamp9g20_leds));
+        at91_gpio_leds(stamp9g20evb_leds, ARRAY_SIZE(stamp9g20evb_leds));
 }
 MACHINE_START(PORTUXG20, "taskit PortuxG20")
@@ -305,7 +309,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
        /* Maintainer: taskit GmbH */
        .boot_params    = AT91_SDRAM_BASE + 0x100,
        .timer          = &at91sam926x_timer,
-        .map_io         = stamp9g20_map_io,
+        .map_io         = stamp9g20evb_map_io,
        .init_irq       = init_irq,
-        .init_machine   = stamp9g20_board_init,
+        .init_machine   = stamp9g20evb_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 7525cee3983..9113da6845f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -658,7 +658,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
        /* Now set uhpck values */
        uhpck.parent = &utmi_clk;
        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-        uhpck.rate_hz = utmi_clk.parent->rate_hz;
+        uhpck.rate_hz = utmi_clk.rate_hz;
        uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h
index 57f8ee15494..27ac6f550fe 100644
--- a/arch/arm/mach-at91/include/mach/at91_mci.h
+++ b/arch/arm/mach-at91/include/mach/at91_mci.h
@@ -74,6 +74,8 @@
 #define                 AT91_MCI_TRTYP_BLOCK    (0 << 19)
 #define                 AT91_MCI_TRTYP_MULTIPLE (1 << 19)
 #define                 AT91_MCI_TRTYP_STREAM   (2 << 19)
+#define                 AT91_MCI_TRTYP_SDIO_BYTE        (4 << 19)
+#define                 AT91_MCI_TRTYP_SDIO_BLOCK       (5 << 19)
 #define AT91_MCI_BLKR           0x18            /* Block Register */
 #define         AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0)   /* Block count */
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
new file mode 100644
index 00000000000..6120f9c46d5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_STAMP9G20_H
+#define __MACH_STAMP9G20_H
+void stamp9g20_map_io(void);
+void stamp9g20_board_init(void);
+#endif
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 24498a932ba..a54b3db8036 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -513,4 +513,4 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
 EXPORT_SYMBOL(ixp4xx_pci_read);
 EXPORT_SYMBOL(ixp4xx_pci_write);
+EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index daf3993349f..2e3dd08ccc3 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -126,7 +126,6 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
 static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
 static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
 static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
-static APBC_CLK(rtc, MMP2_RTC, 0, 32768);
 static APMU_CLK(nand, NAND, 0xbf, 100000000);
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index dbbcfeb919d..1a11f1ed216 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -44,6 +44,7 @@ config ARCH_MSM8X60
        select CPU_V7
        select MSM_V2_TLMM
        select MSM_GPIOMUX
+        select IOMMU_API
 endchoice
@@ -122,6 +123,10 @@ config MACH_MSM8X60_FFA
 endmenu
+config IOMMU_PGTABLES_L2
+        def_bool y
+        depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n
 config MSM_DEBUG_UART
        int
        default 1 if MSM_DEBUG_UART1
@@ -162,4 +167,7 @@ config MSM_GPIOMUX
 config MSM_V2_TLMM
        bool
+config IOMMU_API
+        bool
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index b5a7b07a44f..59646bbd619 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
+obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
@@ -28,6 +29,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
-ifndef CONFIG_MSM_V2_TLMM
+ifdef CONFIG_MSM_V2_TLMM
+obj-y   += gpio-v2.o
+else
 obj-y   += gpio.o
 endif
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 05241df3f9b..6f3b9735e97 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
+#include <linux/usb/msm_hsusb.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,11 +40,26 @@
 extern struct sys_timer msm_timer;
+static int hsusb_phy_init_seq[] = {
+        0x30, 0x32,     /* Enable and set Pre-Emphasis Depth to 20% */
+        0x02, 0x36,     /* Disable CDR Auto Reset feature */
+        -1
+};
+static struct msm_otg_platform_data msm_otg_pdata = {
+        .phy_init_seq           = hsusb_phy_init_seq,
+        .mode                   = USB_PERIPHERAL,
+        .otg_control            = OTG_PHY_CONTROL,
+};
 static struct platform_device *devices[] __initdata = {
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
        &msm_device_uart2,
 #endif
        &msm_device_smd,
+        &msm_device_otg,
+        &msm_device_hsusb,
+        &msm_device_hsusb_host,
 };
 static void __init msm7x30_init_irq(void)
@@ -53,6 +69,10 @@ static void __init msm7x30_init_irq(void)
 static void __init msm7x30_init(void)
 {
+        msm_device_otg.dev.platform_data = &msm_otg_pdata;
+        msm_device_hsusb.dev.parent = &msm_device_otg.dev;
+        msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index ed2af4ad97e..2e8391307f5 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -20,6 +20,7 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/usb/msm_hsusb.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -74,9 +75,24 @@ static int __init msm_init_smc91x(void)
 }
 module_init(msm_init_smc91x);
+static int hsusb_phy_init_seq[] = {
+        0x08, 0x31,     /* Increase HS Driver Amplitude */
+        0x20, 0x32,     /* Enable and set Pre-Emphasis Depth to 10% */
+        -1
+};
+static struct msm_otg_platform_data msm_otg_pdata = {
+        .phy_init_seq           = hsusb_phy_init_seq,
+        .mode                   = USB_PERIPHERAL,
+        .otg_control            = OTG_PHY_CONTROL,
+};
 static struct platform_device *devices[] __initdata = {
        &msm_device_uart3,
        &msm_device_smd,
+        &msm_device_otg,
+        &msm_device_hsusb,
+        &msm_device_hsusb_host,
 };
 static void __init qsd8x50_map_io(void)
@@ -93,6 +109,9 @@ static void __init qsd8x50_init_irq(void)
 static void __init qsd8x50_init(void)
 {
+        msm_device_otg.dev.platform_data = &msm_otg_pdata;
+        msm_device_hsusb.dev.parent = &msm_device_otg.dev;
+        msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index c50f3afc313..f8c09ef6666 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -72,6 +72,13 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip,
        return 0;
 }
+static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+        return TROUT_GPIO_TO_INT(offset + chip->base);
+}
 #define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val)           \
        {                                                               \
                .chip = {                                               \
@@ -80,6 +87,7 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip,
                        .direction_output = msm_gpiolib_direction_output, \
                        .get              = msm_gpiolib_get,            \
                        .set              = msm_gpiolib_set,            \
+                        .to_irq           = trout_gpio_to_irq,          \
                        .base             = base_gpio,                  \
                        .ngpio            = 8,                          \
                },                                                      \
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
new file mode 100644
index 00000000000..729bb49a44c
--- /dev/null
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -0,0 +1,297 @@
+/* linux/arch/arm/mach-msm/board-trout-mddi.c
+** Author: Brian Swetland <swetland@google.com>
+*/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/leds.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <mach/msm_fb.h>
+#include <mach/vreg.h>
+#include "board-trout.h"
+#include "proc_comm.h"
+#include "devices.h"
+#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
+#define MDDI_CLIENT_CORE_BASE  0x108000
+#define LCD_CONTROL_BLOCK_BASE 0x110000
+#define SPI_BLOCK_BASE         0x120000
+#define I2C_BLOCK_BASE         0x130000
+#define PWM_BLOCK_BASE         0x140000
+#define GPIO_BLOCK_BASE        0x150000
+#define SYSTEM_BLOCK1_BASE     0x160000
+#define SYSTEM_BLOCK2_BASE     0x170000
+#define DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
+#define SYSCLKENA   (MDDI_CLIENT_CORE_BASE|0x2C)
+#define PWM0OFF       (PWM_BLOCK_BASE|0x1C)
+#define V_VDDE2E_VDD2_GPIO 0
+#define MDDI_RST_N 82
+#define MDDICAP0    (MDDI_CLIENT_CORE_BASE|0x00)
+#define MDDICAP1    (MDDI_CLIENT_CORE_BASE|0x04)
+#define MDDICAP2    (MDDI_CLIENT_CORE_BASE|0x08)
+#define MDDICAP3    (MDDI_CLIENT_CORE_BASE|0x0C)
+#define MDCAPCHG    (MDDI_CLIENT_CORE_BASE|0x10)
+#define MDCRCERC    (MDDI_CLIENT_CORE_BASE|0x14)
+#define TTBUSSEL    (MDDI_CLIENT_CORE_BASE|0x18)
+#define DPSET0      (MDDI_CLIENT_CORE_BASE|0x1C)
+#define DPSET1      (MDDI_CLIENT_CORE_BASE|0x20)
+#define DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
+#define DPRUN       (MDDI_CLIENT_CORE_BASE|0x28)
+#define SYSCKENA    (MDDI_CLIENT_CORE_BASE|0x2C)
+#define TESTMODE    (MDDI_CLIENT_CORE_BASE|0x30)
+#define FIFOMONI    (MDDI_CLIENT_CORE_BASE|0x34)
+#define INTMONI     (MDDI_CLIENT_CORE_BASE|0x38)
+#define MDIOBIST    (MDDI_CLIENT_CORE_BASE|0x3C)
+#define MDIOPSET    (MDDI_CLIENT_CORE_BASE|0x40)
+#define BITMAP0     (MDDI_CLIENT_CORE_BASE|0x44)
+#define BITMAP1     (MDDI_CLIENT_CORE_BASE|0x48)
+#define BITMAP2     (MDDI_CLIENT_CORE_BASE|0x4C)
+#define BITMAP3     (MDDI_CLIENT_CORE_BASE|0x50)
+#define BITMAP4     (MDDI_CLIENT_CORE_BASE|0x54)
+#define SRST        (LCD_CONTROL_BLOCK_BASE|0x00)
+#define PORT_ENB    (LCD_CONTROL_BLOCK_BASE|0x04)
+#define START       (LCD_CONTROL_BLOCK_BASE|0x08)
+#define PORT        (LCD_CONTROL_BLOCK_BASE|0x0C)
+#define CMN         (LCD_CONTROL_BLOCK_BASE|0x10)
+#define GAMMA       (LCD_CONTROL_BLOCK_BASE|0x14)
+#define INTFLG      (LCD_CONTROL_BLOCK_BASE|0x18)
+#define INTMSK      (LCD_CONTROL_BLOCK_BASE|0x1C)
+#define MPLFBUF     (LCD_CONTROL_BLOCK_BASE|0x20)
+#define HDE_LEFT    (LCD_CONTROL_BLOCK_BASE|0x24)
+#define VDE_TOP     (LCD_CONTROL_BLOCK_BASE|0x28)
+#define PXL         (LCD_CONTROL_BLOCK_BASE|0x30)
+#define HCYCLE      (LCD_CONTROL_BLOCK_BASE|0x34)
+#define HSW         (LCD_CONTROL_BLOCK_BASE|0x38)
+#define HDE_START   (LCD_CONTROL_BLOCK_BASE|0x3C)
+#define HDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x40)
+#define VCYCLE      (LCD_CONTROL_BLOCK_BASE|0x44)
+#define VSW         (LCD_CONTROL_BLOCK_BASE|0x48)
+#define VDE_START   (LCD_CONTROL_BLOCK_BASE|0x4C)
+#define VDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x50)
+#define WAKEUP      (LCD_CONTROL_BLOCK_BASE|0x54)
+#define WSYN_DLY    (LCD_CONTROL_BLOCK_BASE|0x58)
+#define REGENB      (LCD_CONTROL_BLOCK_BASE|0x5C)
+#define VSYNIF      (LCD_CONTROL_BLOCK_BASE|0x60)
+#define WRSTB       (LCD_CONTROL_BLOCK_BASE|0x64)
+#define RDSTB       (LCD_CONTROL_BLOCK_BASE|0x68)
+#define ASY_DATA    (LCD_CONTROL_BLOCK_BASE|0x6C)
+#define ASY_DATB    (LCD_CONTROL_BLOCK_BASE|0x70)
+#define ASY_DATC    (LCD_CONTROL_BLOCK_BASE|0x74)
+#define ASY_DATD    (LCD_CONTROL_BLOCK_BASE|0x78)
+#define ASY_DATE    (LCD_CONTROL_BLOCK_BASE|0x7C)
+#define ASY_DATF    (LCD_CONTROL_BLOCK_BASE|0x80)
+#define ASY_DATG    (LCD_CONTROL_BLOCK_BASE|0x84)
+#define ASY_DATH    (LCD_CONTROL_BLOCK_BASE|0x88)
+#define ASY_CMDSET  (LCD_CONTROL_BLOCK_BASE|0x8C)
+#define SSICTL      (SPI_BLOCK_BASE|0x00)
+#define SSITIME     (SPI_BLOCK_BASE|0x04)
+#define SSITX       (SPI_BLOCK_BASE|0x08)
+#define SSIRX       (SPI_BLOCK_BASE|0x0C)
+#define SSIINTC     (SPI_BLOCK_BASE|0x10)
+#define SSIINTS     (SPI_BLOCK_BASE|0x14)
+#define SSIDBG1     (SPI_BLOCK_BASE|0x18)
+#define SSIDBG2     (SPI_BLOCK_BASE|0x1C)
+#define SSIID       (SPI_BLOCK_BASE|0x20)
+#define WKREQ       (SYSTEM_BLOCK1_BASE|0x00)
+#define CLKENB      (SYSTEM_BLOCK1_BASE|0x04)
+#define DRAMPWR     (SYSTEM_BLOCK1_BASE|0x08)
+#define INTMASK     (SYSTEM_BLOCK1_BASE|0x0C)
+#define GPIOSEL     (SYSTEM_BLOCK2_BASE|0x00)
+#define GPIODATA    (GPIO_BLOCK_BASE|0x00)
+#define GPIODIR     (GPIO_BLOCK_BASE|0x04)
+#define GPIOIS      (GPIO_BLOCK_BASE|0x08)
+#define GPIOIBE     (GPIO_BLOCK_BASE|0x0C)
+#define GPIOIEV     (GPIO_BLOCK_BASE|0x10)
+#define GPIOIE      (GPIO_BLOCK_BASE|0x14)
+#define GPIORIS     (GPIO_BLOCK_BASE|0x18)
+#define GPIOMIS     (GPIO_BLOCK_BASE|0x1C)
+#define GPIOIC      (GPIO_BLOCK_BASE|0x20)
+#define GPIOOMS     (GPIO_BLOCK_BASE|0x24)
+#define GPIOPC      (GPIO_BLOCK_BASE|0x28)
+#define GPIOID      (GPIO_BLOCK_BASE|0x30)
+#define SPI_WRITE(reg, val) \
+        { SSITX,        0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
+        { 0, 5 },
+#define SPI_WRITE1(reg) \
+        { SSITX,        (reg) & 0xff }, \
+        { 0, 5 },
+struct mddi_table {
+        uint32_t reg;
+        uint32_t value;
+};
+static struct mddi_table mddi_toshiba_init_table[] = {
+        { DPSET0,       0x09e90046 },
+        { DPSET1,       0x00000118 },
+        { DPSUS,        0x00000000 },
+        { DPRUN,        0x00000001 },
+        { 1,            14         }, /* msleep 14 */
+        { SYSCKENA,     0x00000001 },
+        { CLKENB,       0x0000A1EF },  /*    # SYS.CLKENB  # Enable clocks for each module (without DCLK , i2cCLK) */
+        { GPIODATA,     0x02000200 },  /*   # GPI .GPIODATA  # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
+        { GPIODIR,      0x000030D  },  /* 24D   # GPI .GPIODIR  # Select direction of GPIO port (0,2,3,6,9 output) */
+        { GPIOSEL,      0/*0x00000173*/},  /*   # SYS.GPIOSEL  # GPIO port multiplexing control */
+        { GPIOPC,       0x03C300C0 },  /*   # GPI .GPIOPC  # GPIO2,3 PD cut */
+        { WKREQ,        0x00000000 },  /*   # SYS.WKREQ  # Wake-up request event is VSYNC alignment */
+        { GPIOIBE,      0x000003FF },
+        { GPIOIS,       0x00000000 },
+        { GPIOIC,       0x000003FF },
+        { GPIOIE,       0x00000000 },
+        { GPIODATA,     0x00040004 },  /*   # GPI .GPIODATA  # eDRAM VD supply */
+        { 1,            1          }, /* msleep 1 */
+        { GPIODATA,     0x02040004 },  /*   # GPI .GPIODATA  # eDRAM VD supply */
+        { DRAMPWR,      0x00000001 }, /* eDRAM power */
+};
+#define GPIOSEL_VWAKEINT (1U << 0)
+#define INTMASK_VWAKEOUT (1U << 0)
+static struct clk *gp_clk;
+static int trout_new_backlight = 1;
+static struct vreg *vreg_mddi_1v5;
+static struct vreg *vreg_lcm_2v85;
+static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
+                                     struct mddi_table *table, size_t count)
+{
+        int i;
+        for (i = 0; i < count; i++) {
+                uint32_t reg = table[i].reg;
+                uint32_t value = table[i].value;
+                if (reg == 0)
+                        udelay(value);
+                else if (reg == 1)
+                        msleep(value);
+                else
+                        client_data->remote_write(client_data, value, reg);
+        }
+}
+static int trout_mddi_toshiba_client_init(
+        struct msm_mddi_bridge_platform_data *bridge_data,
+        struct msm_mddi_client_data *client_data)
+{
+        int panel_id;
+        client_data->auto_hibernate(client_data, 0);
+        trout_process_mddi_table(client_data, mddi_toshiba_init_table,
+                                 ARRAY_SIZE(mddi_toshiba_init_table));
+        client_data->auto_hibernate(client_data, 1);
+        panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
+        if (panel_id > 1) {
+                printk(KERN_WARNING "unknown panel id at mddi_enable\n");
+                return -1;
+        }
+        return 0;
+}
+static int trout_mddi_toshiba_client_uninit(
+        struct msm_mddi_bridge_platform_data *bridge_data,
+        struct msm_mddi_client_data *client_data)
+{
+        return 0;
+}
+static struct resource resources_msm_fb[] = {
+        {
+                .start = MSM_FB_BASE,
+                .end = MSM_FB_BASE + MSM_FB_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+};
+struct msm_mddi_bridge_platform_data toshiba_client_data = {
+        .init = trout_mddi_toshiba_client_init,
+        .uninit = trout_mddi_toshiba_client_uninit,
+        .fb_data = {
+                .xres = 320,
+                .yres = 480,
+                .width = 45,
+                .height = 67,
+                .output_format = 0,
+        },
+};
+static struct msm_mddi_platform_data mddi_pdata = {
+        .clk_rate = 122880000,
+        .fb_resource = resources_msm_fb,
+        .num_clients = 1,
+        .client_platform_data = {
+                {
+                        .product_id = (0xd263 << 16 | 0),
+                        .name = "mddi_c_d263_0000",
+                        .id = 0,
+                        .client_data = &toshiba_client_data,
+                        .clk_rate = 0,
+                },
+        },
+};
+int __init trout_init_panel(void)
+{
+        int rc;
+        if (!machine_is_trout())
+                return 0;
+        vreg_mddi_1v5 = vreg_get(0, "gp2");
+        if (IS_ERR(vreg_mddi_1v5))
+                return PTR_ERR(vreg_mddi_1v5);
+        vreg_lcm_2v85 = vreg_get(0, "gp4");
+        if (IS_ERR(vreg_lcm_2v85))
+                return PTR_ERR(vreg_lcm_2v85);
+        trout_new_backlight = system_rev >= 5;
+        if (trout_new_backlight) {
+                uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
+                                                GPIO_NO_PULL, GPIO_8MA);
+                msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
+        } else {
+                uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
+                                                GPIO_NO_PULL, GPIO_8MA);
+                msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
+                gp_clk = clk_get(NULL, "gp_clk");
+                if (IS_ERR(gp_clk)) {
+                        printk(KERN_ERR "trout_init_panel: could not get gp"
+                               "clock\n");
+                        gp_clk = NULL;
+                }
+                rc = clk_set_rate(gp_clk, 19200000);
+                if (rc)
+                        printk(KERN_ERR "trout_init_panel: set clock rate "
+                               "failed\n");
+        }
+        rc = platform_device_register(&msm_device_mdp);
+        if (rc)
+                return rc;
+        msm_device_mddi0.dev.platform_data = &mddi_pdata;
+        return platform_device_register(&msm_device_mddi0);
+}
+device_initcall(trout_init_panel);
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index c57210f4f06..2069bfaa3a2 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -120,6 +120,21 @@ EXPORT_SYMBOL(clk_get_rate);
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
+        int ret;
+        if (clk->flags & CLKFLAG_MAX) {
+                ret = clk->ops->set_max_rate(clk->id, rate);
+                if (ret)
+                        return ret;
+        }
+        if (clk->flags & CLKFLAG_MIN) {
+                ret = clk->ops->set_min_rate(clk->id, rate);
+                if (ret)
+                        return ret;
+        }
+        if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN)
+                return ret;
        return clk->ops->set_rate(clk->id, rate);
 }
 EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 4e8c0bcdc92..fb548a8a21d 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -347,6 +347,73 @@ int __init msm_add_sdcc(unsigned int controller,
        return platform_device_register(pdev);
 }
+static struct resource resources_mddi0[] = {
+        {
+                .start  = MSM_PMDH_PHYS,
+                .end    = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_MDDI_PRI,
+                .end    = INT_MDDI_PRI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct resource resources_mddi1[] = {
+        {
+                .start  = MSM_EMDH_PHYS,
+                .end    = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_MDDI_EXT,
+                .end    = INT_MDDI_EXT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device msm_device_mddi0 = {
+        .name = "msm_mddi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(resources_mddi0),
+        .resource = resources_mddi0,
+        .dev = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+struct platform_device msm_device_mddi1 = {
+        .name = "msm_mddi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(resources_mddi1),
+        .resource = resources_mddi1,
+        .dev = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+static struct resource resources_mdp[] = {
+        {
+                .start  = MSM_MDP_PHYS,
+                .end    = MSM_MDP_PHYS + MSM_MDP_SIZE - 1,
+                .name   = "mdp",
+                .flags  = IORESOURCE_MEM
+        },
+        {
+                .start  = INT_MDP,
+                .end    = INT_MDP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device msm_device_mdp = {
+        .name = "msm_mdp",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(resources_mdp),
+        .resource = resources_mdp,
+};
 struct clk msm_clocks_7x01a[] = {
        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
        CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
@@ -364,7 +431,7 @@ struct clk msm_clocks_7x01a[] = {
        CLK_PCOM("mdp_clk",     MDP_CLK,        NULL, OFF),
        CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, 0),
        CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
-        CLK_PCOM("pmdh_clk",    PMDH_CLK,       NULL, OFF ),
+        CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
        CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
        CLK_PCOM("sdc_clk",     SDC1_CLK,       &msm_device_sdc1.dev, OFF),
        CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     &msm_device_sdc1.dev, OFF),
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 7fcf2e3b769..4e9a0ab3e93 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -56,6 +56,77 @@ struct platform_device msm_device_smd = {
        .id     = -1,
 };
+static struct resource resources_otg[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device msm_device_otg = {
+        .name           = "msm_otg",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_otg),
+        .resource       = resources_otg,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+static struct resource resources_hsusb[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device msm_device_hsusb = {
+        .name           = "msm_hsusb",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_hsusb),
+        .resource       = resources_hsusb,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+static u64 dma_mask = 0xffffffffULL;
+static struct resource resources_hsusb_host[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device msm_device_hsusb_host = {
+        .name           = "msm_hsusb_host",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_hsusb_host),
+        .resource       = resources_hsusb_host,
+        .dev            = {
+                .dma_mask               = &dma_mask,
+                .coherent_dma_mask      = 0xffffffffULL,
+        },
+};
 struct clk msm_clocks_7x30[] = {
        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
        CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
@@ -107,6 +178,7 @@ struct clk msm_clocks_7x30[] = {
        CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
        CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
        CLK_PCOM("uart_clk",    UART2_CLK,      &msm_device_uart2.dev, 0),
+        CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
        CLK_PCOM("usb_hs_clk",          USB_HS_CLK,             NULL, OFF),
        CLK_PCOM("usb_hs_pclk",         USB_HS_P_CLK,           NULL, OFF),
        CLK_PCOM("usb_hs_core_clk",     USB_HS_CORE_CLK,        NULL, OFF),
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c
index 89b9d4437e9..f9e7bd34ec5 100644
--- a/arch/arm/mach-msm/devices-msm8x60-iommu.c
+++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c
@@ -254,60 +254,86 @@ static struct resource msm_iommu_gfx2d0_resources[] = {
        },
 };
+static struct resource msm_iommu_gfx2d1_resources[] = {
+        {
+                .start = MSM_IOMMU_GFX2D1_PHYS,
+                .end   = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
+                .end   = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
 static struct platform_device msm_root_iommu_dev = {
        .name = "msm_iommu",
        .id = -1,
 };
-static struct msm_iommu_dev jpegd_smmu = {
+static struct msm_iommu_dev jpegd_iommu = {
        .name = "jpegd",
        .clk_rate = -1
 };
-static struct msm_iommu_dev vpe_smmu = {
+static struct msm_iommu_dev vpe_iommu = {
        .name = "vpe"
 };
-static struct msm_iommu_dev mdp0_smmu = {
+static struct msm_iommu_dev mdp0_iommu = {
        .name = "mdp0"
 };
-static struct msm_iommu_dev mdp1_smmu = {
+static struct msm_iommu_dev mdp1_iommu = {
        .name = "mdp1"
 };
-static struct msm_iommu_dev rot_smmu = {
+static struct msm_iommu_dev rot_iommu = {
        .name = "rot"
 };
-static struct msm_iommu_dev ijpeg_smmu = {
+static struct msm_iommu_dev ijpeg_iommu = {
        .name = "ijpeg"
 };
-static struct msm_iommu_dev vfe_smmu = {
+static struct msm_iommu_dev vfe_iommu = {
        .name = "vfe",
        .clk_rate = -1
 };
-static struct msm_iommu_dev vcodec_a_smmu = {
+static struct msm_iommu_dev vcodec_a_iommu = {
        .name = "vcodec_a"
 };
-static struct msm_iommu_dev vcodec_b_smmu = {
+static struct msm_iommu_dev vcodec_b_iommu = {
        .name = "vcodec_b"
 };
-static struct msm_iommu_dev gfx3d_smmu = {
+static struct msm_iommu_dev gfx3d_iommu = {
        .name = "gfx3d",
        .clk_rate = 27000000
 };
-static struct msm_iommu_dev gfx2d0_smmu = {
+static struct msm_iommu_dev gfx2d0_iommu = {
        .name = "gfx2d0",
        .clk_rate = 27000000
 };
-static struct platform_device msm_device_smmu_jpegd = {
+static struct msm_iommu_dev gfx2d1_iommu = {
+        .name = "gfx2d1",
+        .clk_rate = 27000000
+};
+static struct platform_device msm_device_iommu_jpegd = {
        .name = "msm_iommu",
        .id = 0,
        .dev = {
@@ -317,7 +343,7 @@ static struct platform_device msm_device_smmu_jpegd = {
        .resource = msm_iommu_jpegd_resources,
 };
-static struct platform_device msm_device_smmu_vpe = {
+static struct platform_device msm_device_iommu_vpe = {
        .name = "msm_iommu",
        .id = 1,
        .dev = {
@@ -327,7 +353,7 @@ static struct platform_device msm_device_smmu_vpe = {
        .resource = msm_iommu_vpe_resources,
 };
-static struct platform_device msm_device_smmu_mdp0 = {
+static struct platform_device msm_device_iommu_mdp0 = {
        .name = "msm_iommu",
        .id = 2,
        .dev = {
@@ -337,7 +363,7 @@ static struct platform_device msm_device_smmu_mdp0 = {
        .resource = msm_iommu_mdp0_resources,
 };
-static struct platform_device msm_device_smmu_mdp1 = {
+static struct platform_device msm_device_iommu_mdp1 = {
        .name = "msm_iommu",
        .id = 3,
        .dev = {
@@ -347,7 +373,7 @@ static struct platform_device msm_device_smmu_mdp1 = {
        .resource = msm_iommu_mdp1_resources,
 };
-static struct platform_device msm_device_smmu_rot = {
+static struct platform_device msm_device_iommu_rot = {
        .name = "msm_iommu",
        .id = 4,
        .dev = {
@@ -357,7 +383,7 @@ static struct platform_device msm_device_smmu_rot = {
        .resource = msm_iommu_rot_resources,
 };
-static struct platform_device msm_device_smmu_ijpeg = {
+static struct platform_device msm_device_iommu_ijpeg = {
        .name = "msm_iommu",
        .id = 5,
        .dev = {
@@ -367,7 +393,7 @@ static struct platform_device msm_device_smmu_ijpeg = {
        .resource = msm_iommu_ijpeg_resources,
 };
-static struct platform_device msm_device_smmu_vfe = {
+static struct platform_device msm_device_iommu_vfe = {
        .name = "msm_iommu",
        .id = 6,
        .dev = {
@@ -377,7 +403,7 @@ static struct platform_device msm_device_smmu_vfe = {
        .resource = msm_iommu_vfe_resources,
 };
-static struct platform_device msm_device_smmu_vcodec_a = {
+static struct platform_device msm_device_iommu_vcodec_a = {
        .name = "msm_iommu",
        .id = 7,
        .dev = {
@@ -387,7 +413,7 @@ static struct platform_device msm_device_smmu_vcodec_a = {
        .resource = msm_iommu_vcodec_a_resources,
 };
-static struct platform_device msm_device_smmu_vcodec_b = {
+static struct platform_device msm_device_iommu_vcodec_b = {
        .name = "msm_iommu",
        .id = 8,
        .dev = {
@@ -397,7 +423,7 @@ static struct platform_device msm_device_smmu_vcodec_b = {
        .resource = msm_iommu_vcodec_b_resources,
 };
-static struct platform_device msm_device_smmu_gfx3d = {
+static struct platform_device msm_device_iommu_gfx3d = {
        .name = "msm_iommu",
        .id = 9,
        .dev = {
@@ -407,7 +433,7 @@ static struct platform_device msm_device_smmu_gfx3d = {
        .resource = msm_iommu_gfx3d_resources,
 };
-static struct platform_device msm_device_smmu_gfx2d0 = {
+static struct platform_device msm_device_iommu_gfx2d0 = {
        .name = "msm_iommu",
        .id = 10,
        .dev = {
@@ -417,6 +443,16 @@ static struct platform_device msm_device_smmu_gfx2d0 = {
        .resource = msm_iommu_gfx2d0_resources,
 };
+struct platform_device msm_device_iommu_gfx2d1 = {
+        .name = "msm_iommu",
+        .id = 11,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
+        .resource = msm_iommu_gfx2d1_resources,
+};
 static struct msm_iommu_ctx_dev jpegd_src_ctx = {
        .name = "jpegd_src",
        .num = 0,
@@ -519,41 +555,36 @@ static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
        .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
 };
-static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
+static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
-        .name = "gfx3d_rbpa",
+        .name = "gfx3d_user",
        .num = 0,
-        .mids = {-1}
+        .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
 };
-static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
+static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
-        .name = "gfx3d_cpvgttc",
+        .name = "gfx3d_priv",
        .num = 1,
-        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
+        .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
-};
+                 31, -1}
-static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
-        .name = "gfx3d_smmu",
-        .num = 2,
-        .mids = {8, 9, 10, 11, 12, -1}
 };
-static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
+static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
-        .name = "gfx2d0_pixv1_smmu",
+        .name = "gfx2d0_2d0",
        .num = 0,
-        .mids = {0, 3, 4, -1}
+        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
 };
-static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
+static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
-        .name = "gfx2d0_texv3_smmu",
+        .name = "gfx2d1_2d1",
-        .num = 1,
+        .num = 0,
-        .mids = {1, 6, 7, -1}
+        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
 };
 static struct platform_device msm_device_jpegd_src_ctx = {
        .name = "msm_iommu_ctx",
        .id = 0,
        .dev = {
-                .parent = &msm_device_smmu_jpegd.dev,
+                .parent = &msm_device_iommu_jpegd.dev,
        },
 };
@@ -561,7 +592,7 @@ static struct platform_device msm_device_jpegd_dst_ctx = {
        .name = "msm_iommu_ctx",
        .id = 1,
        .dev = {
-                .parent = &msm_device_smmu_jpegd.dev,
+                .parent = &msm_device_iommu_jpegd.dev,
        },
 };
@@ -569,7 +600,7 @@ static struct platform_device msm_device_vpe_src_ctx = {
        .name = "msm_iommu_ctx",
        .id = 2,
        .dev = {
-                .parent = &msm_device_smmu_vpe.dev,
+                .parent = &msm_device_iommu_vpe.dev,
        },
 };
@@ -577,7 +608,7 @@ static struct platform_device msm_device_vpe_dst_ctx = {
        .name = "msm_iommu_ctx",
        .id = 3,
        .dev = {
-                .parent = &msm_device_smmu_vpe.dev,
+                .parent = &msm_device_iommu_vpe.dev,
        },
 };
@@ -585,7 +616,7 @@ static struct platform_device msm_device_mdp_vg1_ctx = {
        .name = "msm_iommu_ctx",
        .id = 4,
        .dev = {
-                .parent = &msm_device_smmu_mdp0.dev,
+                .parent = &msm_device_iommu_mdp0.dev,
        },
 };
@@ -593,7 +624,7 @@ static struct platform_device msm_device_mdp_rgb1_ctx = {
        .name = "msm_iommu_ctx",
        .id = 5,
        .dev = {
-                .parent = &msm_device_smmu_mdp0.dev,
+                .parent = &msm_device_iommu_mdp0.dev,
        },
 };
@@ -601,7 +632,7 @@ static struct platform_device msm_device_mdp_vg2_ctx = {
        .name = "msm_iommu_ctx",
        .id = 6,
        .dev = {
-                .parent = &msm_device_smmu_mdp1.dev,
+                .parent = &msm_device_iommu_mdp1.dev,
        },
 };
@@ -609,7 +640,7 @@ static struct platform_device msm_device_mdp_rgb2_ctx = {
        .name = "msm_iommu_ctx",
        .id = 7,
        .dev = {
-                .parent = &msm_device_smmu_mdp1.dev,
+                .parent = &msm_device_iommu_mdp1.dev,
        },
 };
@@ -617,7 +648,7 @@ static struct platform_device msm_device_rot_src_ctx = {
        .name = "msm_iommu_ctx",
        .id = 8,
        .dev = {
-                .parent = &msm_device_smmu_rot.dev,
+                .parent = &msm_device_iommu_rot.dev,
        },
 };
@@ -625,7 +656,7 @@ static struct platform_device msm_device_rot_dst_ctx = {
        .name = "msm_iommu_ctx",
        .id = 9,
        .dev = {
-                .parent = &msm_device_smmu_rot.dev,
+                .parent = &msm_device_iommu_rot.dev,
        },
 };
@@ -633,7 +664,7 @@ static struct platform_device msm_device_ijpeg_src_ctx = {
        .name = "msm_iommu_ctx",
        .id = 10,
        .dev = {
-                .parent = &msm_device_smmu_ijpeg.dev,
+                .parent = &msm_device_iommu_ijpeg.dev,
        },
 };
@@ -641,7 +672,7 @@ static struct platform_device msm_device_ijpeg_dst_ctx = {
        .name = "msm_iommu_ctx",
        .id = 11,
        .dev = {
-                .parent = &msm_device_smmu_ijpeg.dev,
+                .parent = &msm_device_iommu_ijpeg.dev,
        },
 };
@@ -649,7 +680,7 @@ static struct platform_device msm_device_vfe_imgwr_ctx = {
        .name = "msm_iommu_ctx",
        .id = 12,
        .dev = {
-                .parent = &msm_device_smmu_vfe.dev,
+                .parent = &msm_device_iommu_vfe.dev,
        },
 };
@@ -657,7 +688,7 @@ static struct platform_device msm_device_vfe_misc_ctx = {
        .name = "msm_iommu_ctx",
        .id = 13,
        .dev = {
-                .parent = &msm_device_smmu_vfe.dev,
+                .parent = &msm_device_iommu_vfe.dev,
        },
 };
@@ -665,7 +696,7 @@ static struct platform_device msm_device_vcodec_a_stream_ctx = {
        .name = "msm_iommu_ctx",
        .id = 14,
        .dev = {
-                .parent = &msm_device_smmu_vcodec_a.dev,
+                .parent = &msm_device_iommu_vcodec_a.dev,
        },
 };
@@ -673,7 +704,7 @@ static struct platform_device msm_device_vcodec_a_mm1_ctx = {
        .name = "msm_iommu_ctx",
        .id = 15,
        .dev = {
-                .parent = &msm_device_smmu_vcodec_a.dev,
+                .parent = &msm_device_iommu_vcodec_a.dev,
        },
 };
@@ -681,76 +712,70 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = {
        .name = "msm_iommu_ctx",
        .id = 16,
        .dev = {
-                .parent = &msm_device_smmu_vcodec_b.dev,
+                .parent = &msm_device_iommu_vcodec_b.dev,
        },
 };
-static struct platform_device msm_device_gfx3d_rbpa_ctx = {
+static struct platform_device msm_device_gfx3d_user_ctx = {
        .name = "msm_iommu_ctx",
        .id = 17,
        .dev = {
-                .parent = &msm_device_smmu_gfx3d.dev,
+                .parent = &msm_device_iommu_gfx3d.dev,
        },
 };
-static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
+static struct platform_device msm_device_gfx3d_priv_ctx = {
        .name = "msm_iommu_ctx",
        .id = 18,
        .dev = {
-                .parent = &msm_device_smmu_gfx3d.dev,
+                .parent = &msm_device_iommu_gfx3d.dev,
        },
 };
-static struct platform_device msm_device_gfx3d_smmu_ctx = {
+static struct platform_device msm_device_gfx2d0_2d0_ctx = {
        .name = "msm_iommu_ctx",
        .id = 19,
        .dev = {
-                .parent = &msm_device_smmu_gfx3d.dev,
+                .parent = &msm_device_iommu_gfx2d0.dev,
        },
 };
-static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
+static struct platform_device msm_device_gfx2d1_2d1_ctx = {
        .name = "msm_iommu_ctx",
        .id = 20,
        .dev = {
-                .parent = &msm_device_smmu_gfx2d0.dev,
+                .parent = &msm_device_iommu_gfx2d1.dev,
-        },
-};
-static struct platform_device msm_device_gfx2d0_texv3_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 21,
-        .dev = {
-                .parent = &msm_device_smmu_gfx2d0.dev,
        },
 };
 static struct platform_device *msm_iommu_devs[] = {
-        &msm_device_smmu_jpegd,
+        &msm_device_iommu_jpegd,
-        &msm_device_smmu_vpe,
+        &msm_device_iommu_vpe,
-        &msm_device_smmu_mdp0,
+        &msm_device_iommu_mdp0,
-        &msm_device_smmu_mdp1,
+        &msm_device_iommu_mdp1,
-        &msm_device_smmu_rot,
+        &msm_device_iommu_rot,
-        &msm_device_smmu_ijpeg,
+        &msm_device_iommu_ijpeg,
-        &msm_device_smmu_vfe,
+        &msm_device_iommu_vfe,
-        &msm_device_smmu_vcodec_a,
+        &msm_device_iommu_vcodec_a,
-        &msm_device_smmu_vcodec_b,
+        &msm_device_iommu_vcodec_b,
-        &msm_device_smmu_gfx3d,
+        &msm_device_iommu_gfx3d,
-        &msm_device_smmu_gfx2d0,
+        &msm_device_iommu_gfx2d0,
+        &msm_device_iommu_gfx2d1,
 };
 static struct msm_iommu_dev *msm_iommu_data[] = {
-        &jpegd_smmu,
+        &jpegd_iommu,
-        &vpe_smmu,
+        &vpe_iommu,
-        &mdp0_smmu,
+        &mdp0_iommu,
-        &mdp1_smmu,
+        &mdp1_iommu,
-        &rot_smmu,
+        &rot_iommu,
-        &ijpeg_smmu,
+        &ijpeg_iommu,
-        &vfe_smmu,
+        &vfe_iommu,
-        &vcodec_a_smmu,
+        &vcodec_a_iommu,
-        &vcodec_b_smmu,
+        &vcodec_b_iommu,
-        &gfx3d_smmu,
+        &gfx3d_iommu,
-        &gfx2d0_smmu,
+        &gfx2d0_iommu,
+        &gfx2d1_iommu,
 };
 static struct platform_device *msm_iommu_ctx_devs[] = {
@@ -771,11 +796,10 @@ static struct platform_device *msm_iommu_ctx_devs[] = {
        &msm_device_vcodec_a_stream_ctx,
        &msm_device_vcodec_a_mm1_ctx,
        &msm_device_vcodec_b_mm2_ctx,
-        &msm_device_gfx3d_rbpa_ctx,
+        &msm_device_gfx3d_user_ctx,
-        &msm_device_gfx3d_cpvgttc_ctx,
+        &msm_device_gfx3d_priv_ctx,
-        &msm_device_gfx3d_smmu_ctx,
+        &msm_device_gfx2d0_2d0_ctx,
-        &msm_device_gfx2d0_pixv1_ctx,
+        &msm_device_gfx2d1_2d1_ctx,
-        &msm_device_gfx2d0_texv3_ctx,
 };
 static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
@@ -796,14 +820,13 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
        &vcodec_a_stream_ctx,
        &vcodec_a_mm1_ctx,
        &vcodec_b_mm2_ctx,
-        &gfx3d_rbpa_ctx,
+        &gfx3d_user_ctx,
-        &gfx3d_cpvgttc_ctx,
+        &gfx3d_priv_ctx,
-        &gfx3d_smmu_ctx,
+        &gfx2d0_2d0_ctx,
-        &gfx2d0_pixv1_ctx,
+        &gfx2d1_2d1_ctx,
-        &gfx2d0_texv3_ctx,
 };
-static int msm8x60_iommu_init(void)
+static int __init msm8x60_iommu_init(void)
 {
        int ret, i;
@@ -826,7 +849,7 @@ static int msm8x60_iommu_init(void)
                ret = platform_device_register(msm_iommu_devs[i]);
                if (ret != 0) {
-                        pr_err("platform_device_register smmu failed, "
+                        pr_err("platform_device_register iommu failed, "
                               "i = %d\n", i);
                        goto failure_unwind;
                }
@@ -837,7 +860,7 @@ static int msm8x60_iommu_init(void)
                                               msm_iommu_ctx_data[i],
                                               sizeof(*msm_iommu_ctx_devs[i]));
                if (ret != 0) {
-                        pr_err("platform_device_add_data smmu failed, "
+                        pr_err("platform_device_add_data iommu failed, "
                               "i = %d\n", i);
                        goto failure_unwind2;
                }
@@ -863,7 +886,7 @@ failure:
        return ret;
 }
-static void msm8x60_iommu_exit(void)
+static void __exit msm8x60_iommu_exit(void)
 {
        int i;
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 6fe67c5d1ae..a4b798f20cc 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -53,6 +53,77 @@ struct platform_device msm_device_smd = {
        .id     = -1,
 };
+static struct resource resources_otg[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device msm_device_otg = {
+        .name           = "msm_otg",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_otg),
+        .resource       = resources_otg,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+static struct resource resources_hsusb[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device msm_device_hsusb = {
+        .name           = "msm_hsusb",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_hsusb),
+        .resource       = resources_hsusb,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+static u64 dma_mask = 0xffffffffULL;
+static struct resource resources_hsusb_host[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device msm_device_hsusb_host = {
+        .name           = "msm_hsusb_host",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_hsusb_host),
+        .resource       = resources_hsusb_host,
+        .dev            = {
+                .dma_mask               = &dma_mask,
+                .coherent_dma_mask      = 0xffffffffULL,
+        },
+};
 struct clk msm_clocks_8x50[] = {
        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
        CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 568443e7642..87c70bfce2b 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -28,6 +28,8 @@ extern struct platform_device msm_device_sdc3;
 extern struct platform_device msm_device_sdc4;
 extern struct platform_device msm_device_hsusb;
+extern struct platform_device msm_device_otg;
+extern struct platform_device msm_device_hsusb_host;
 extern struct platform_device msm_device_i2c;
@@ -35,6 +37,10 @@ extern struct platform_device msm_device_smd;
 extern struct platform_device msm_device_nand;
+extern struct platform_device msm_device_mddi0;
+extern struct platform_device msm_device_mddi1;
+extern struct platform_device msm_device_mdp;
 extern struct clk msm_clocks_7x01a[];
 extern unsigned msm_num_clocks_7x01a;
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
new file mode 100644
index 00000000000..0de19ec74e3
--- /dev/null
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -0,0 +1,426 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <mach/msm_iomap.h>
+#include "gpiomux.h"
+/* Bits of interest in the GPIO_IN_OUT register.
+ */
+enum {
+        GPIO_IN  = 0,
+        GPIO_OUT = 1
+};
+/* Bits of interest in the GPIO_INTR_STATUS register.
+ */
+enum {
+        INTR_STATUS = 0,
+};
+/* Bits of interest in the GPIO_CFG register.
+ */
+enum {
+        GPIO_OE = 9,
+};
+/* Bits of interest in the GPIO_INTR_CFG register.
+ * When a GPIO triggers, two separate decisions are made, controlled
+ * by two separate flags.
+ *
+ * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
+ * register for that GPIO will be updated to reflect the triggering of that
+ * gpio.  If this bit is 0, this register will not be updated.
+ * - Second, INTR_ENABLE controls whether an interrupt is triggered.
+ *
+ * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
+ * can be triggered but the status register will not reflect it.
+ */
+enum {
+        INTR_ENABLE        = 0,
+        INTR_POL_CTL       = 1,
+        INTR_DECT_CTL      = 2,
+        INTR_RAW_STATUS_EN = 3,
+};
+/* Codes of interest in GPIO_INTR_CFG_SU.
+ */
+enum {
+        TARGET_PROC_SCORPION = 4,
+        TARGET_PROC_NONE     = 7,
+};
+#define GPIO_INTR_CFG_SU(gpio)    (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
+#define GPIO_CONFIG(gpio)         (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
+#define GPIO_IN_OUT(gpio)         (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
+#define GPIO_INTR_CFG(gpio)       (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
+#define GPIO_INTR_STATUS(gpio)    (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
+/**
+ * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
+ *
+ * @enabled_irqs: a bitmap used to optimize the summary-irq handler.  By
+ * keeping track of which gpios are unmasked as irq sources, we avoid
+ * having to do readl calls on hundreds of iomapped registers each time
+ * the summary interrupt fires in order to locate the active interrupts.
+ *
+ * @wake_irqs: a bitmap for tracking which interrupt lines are enabled
+ * as wakeup sources.  When the device is suspended, interrupts which are
+ * not wakeup sources are disabled.
+ *
+ * @dual_edge_irqs: a bitmap used to track which irqs are configured
+ * as dual-edge, as this is not supported by the hardware and requires
+ * some special handling in the driver.
+ */
+struct msm_gpio_dev {
+        struct gpio_chip gpio_chip;
+        DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
+        DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
+        DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
+};
+static DEFINE_SPINLOCK(tlmm_lock);
+static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
+{
+        return container_of(chip, struct msm_gpio_dev, gpio_chip);
+}
+static inline void set_gpio_bits(unsigned n, void __iomem *reg)
+{
+        writel(readl(reg) | n, reg);
+}
+static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
+{
+        writel(readl(reg) & ~n, reg);
+}
+static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
+}
+static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
+}
+static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        unsigned long irq_flags;
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+        return 0;
+}
+static int msm_gpio_direction_output(struct gpio_chip *chip,
+                                unsigned offset,
+                                int val)
+{
+        unsigned long irq_flags;
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        msm_gpio_set(chip, offset, val);
+        set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+        return 0;
+}
+static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return msm_gpiomux_get(chip->base + offset);
+}
+static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        msm_gpiomux_put(chip->base + offset);
+}
+static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        return MSM_GPIO_TO_INT(chip->base + offset);
+}
+static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
+{
+        return irq - MSM_GPIO_TO_INT(chip->base);
+}
+static struct msm_gpio_dev msm_gpio = {
+        .gpio_chip = {
+                .base             = 0,
+                .ngpio            = NR_GPIO_IRQS,
+                .direction_input  = msm_gpio_direction_input,
+                .direction_output = msm_gpio_direction_output,
+                .get              = msm_gpio_get,
+                .set              = msm_gpio_set,
+                .to_irq           = msm_gpio_to_irq,
+                .request          = msm_gpio_request,
+                .free             = msm_gpio_free,
+        },
+};
+/* For dual-edge interrupts in software, since the hardware has no
+ * such support:
+ *
+ * At appropriate moments, this function may be called to flip the polarity
+ * settings of both-edge irq lines to try and catch the next edge.
+ *
+ * The attempt is considered successful if:
+ * - the status bit goes high, indicating that an edge was caught, or
+ * - the input value of the gpio doesn't change during the attempt.
+ * If the value changes twice during the process, that would cause the first
+ * test to fail but would force the second, as two opposite
+ * transitions would cause a detection no matter the polarity setting.
+ *
+ * The do-loop tries to sledge-hammer closed the timing hole between
+ * the initial value-read and the polarity-write - if the line value changes
+ * during that window, an interrupt is lost, the new polarity setting is
+ * incorrect, and the first success test will fail, causing a retry.
+ *
+ * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
+ */
+static void msm_gpio_update_dual_edge_pos(unsigned gpio)
+{
+        int loop_limit = 100;
+        unsigned val, val2, intstat;
+        do {
+                val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
+                if (val)
+                        clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
+                else
+                        set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
+                val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
+                intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
+                if (intstat || val == val2)
+                        return;
+        } while (loop_limit-- > 0);
+        pr_err("dual-edge irq failed to stabilize, "
+               "interrupts dropped. %#08x != %#08x\n",
+               val, val2);
+}
+static void msm_gpio_irq_ack(unsigned int irq)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
+        if (test_bit(gpio, msm_gpio.dual_edge_irqs))
+                msm_gpio_update_dual_edge_pos(gpio);
+}
+static void msm_gpio_irq_mask(unsigned int irq)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        unsigned long irq_flags;
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
+        clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
+        __clear_bit(gpio, msm_gpio.enabled_irqs);
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+}
+static void msm_gpio_irq_unmask(unsigned int irq)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        unsigned long irq_flags;
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        __set_bit(gpio, msm_gpio.enabled_irqs);
+        set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
+        writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+}
+static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        unsigned long irq_flags;
+        uint32_t bits;
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        bits = readl(GPIO_INTR_CFG(gpio));
+        if (flow_type & IRQ_TYPE_EDGE_BOTH) {
+                bits |= BIT(INTR_DECT_CTL);
+                irq_desc[irq].handle_irq = handle_edge_irq;
+                if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
+                        __set_bit(gpio, msm_gpio.dual_edge_irqs);
+                else
+                        __clear_bit(gpio, msm_gpio.dual_edge_irqs);
+        } else {
+                bits &= ~BIT(INTR_DECT_CTL);
+                irq_desc[irq].handle_irq = handle_level_irq;
+                __clear_bit(gpio, msm_gpio.dual_edge_irqs);
+        }
+        if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
+                bits |= BIT(INTR_POL_CTL);
+        else
+                bits &= ~BIT(INTR_POL_CTL);
+        writel(bits, GPIO_INTR_CFG(gpio));
+        if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
+                msm_gpio_update_dual_edge_pos(gpio);
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+        return 0;
+}
+/*
+ * When the summary IRQ is raised, any number of GPIO lines may be high.
+ * It is the job of the summary handler to find all those GPIO lines
+ * which have been set as summary IRQ lines and which are triggered,
+ * and to call their interrupt handlers.
+ */
+static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long i;
+        for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
+             i < NR_GPIO_IRQS;
+             i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) {
+                if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
+                        generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
+                                                           i));
+        }
+        desc->chip->ack(irq);
+}
+static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        if (on) {
+                if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
+                        set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
+                set_bit(gpio, msm_gpio.wake_irqs);
+        } else {
+                clear_bit(gpio, msm_gpio.wake_irqs);
+                if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
+                        set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
+        }
+        return 0;
+}
+static struct irq_chip msm_gpio_irq_chip = {
+        .name           = "msmgpio",
+        .mask           = msm_gpio_irq_mask,
+        .unmask         = msm_gpio_irq_unmask,
+        .ack            = msm_gpio_irq_ack,
+        .set_type       = msm_gpio_irq_set_type,
+        .set_wake       = msm_gpio_irq_set_wake,
+};
+static int __devinit msm_gpio_probe(struct platform_device *dev)
+{
+        int i, irq, ret;
+        bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
+        bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
+        bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
+        msm_gpio.gpio_chip.label = dev->name;
+        ret = gpiochip_add(&msm_gpio.gpio_chip);
+        if (ret < 0)
+                return ret;
+        for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
+                irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
+                set_irq_chip(irq, &msm_gpio_irq_chip);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
+                                msm_summary_irq_handler);
+        return 0;
+}
+static int __devexit msm_gpio_remove(struct platform_device *dev)
+{
+        int ret = gpiochip_remove(&msm_gpio.gpio_chip);
+        if (ret < 0)
+                return ret;
+        set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
+        return 0;
+}
+static struct platform_driver msm_gpio_driver = {
+        .probe = msm_gpio_probe,
+        .remove = __devexit_p(msm_gpio_remove),
+        .driver = {
+                .name = "msmgpio",
+                .owner = THIS_MODULE,
+        },
+};
+static struct platform_device msm_device_gpio = {
+        .name = "msmgpio",
+        .id   = -1,
+};
+static int __init msm_gpio_init(void)
+{
+        int rc;
+        rc = platform_driver_register(&msm_gpio_driver);
+        if (!rc) {
+                rc = platform_device_register(&msm_device_gpio);
+                if (rc)
+                        platform_driver_unregister(&msm_gpio_driver);
+        }
+        return rc;
+}
+static void __exit msm_gpio_exit(void)
+{
+        platform_device_unregister(&msm_device_gpio);
+        platform_driver_unregister(&msm_gpio_driver);
+}
+postcore_initcall(msm_gpio_init);
+module_exit(msm_gpio_exit);
+MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
+MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:msmgpio");
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 218ef5732a2..296c0f10f23 100644
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -20,13 +20,26 @@
 #include <linux/interrupt.h>
+/* Sharability attributes of MSM IOMMU mappings */
+#define MSM_IOMMU_ATTR_NON_SH           0x0
+#define MSM_IOMMU_ATTR_SH               0x4
+/* Cacheability attributes of MSM IOMMU mappings */
+#define MSM_IOMMU_ATTR_NONCACHED        0x0
+#define MSM_IOMMU_ATTR_CACHED_WB_WA     0x1
+#define MSM_IOMMU_ATTR_CACHED_WB_NWA    0x2
+#define MSM_IOMMU_ATTR_CACHED_WT        0x3
+/* Mask for the cache policy attribute */
+#define MSM_IOMMU_CP_MASK               0x03
 /* Maximum number of Machine IDs that we are allowing to be mapped to the same
 * context bank. The number of MIDs mapped to the same CB does not affect
 * performance, but there is a practical limit on how many distinct MIDs may
 * be present. These mappings are typically determined at design time and are
 * not expected to change at run time.
 */
-#define MAX_NUM_MIDS    16
+#define MAX_NUM_MIDS    32
 /**
 * struct msm_iommu_dev - a single IOMMU hardware instance
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
index f9386d3a2f7..c2c3da9444f 100644
--- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -54,6 +54,7 @@ do { \
 #define NUM_FL_PTE      4096
 #define NUM_SL_PTE      256
+#define NUM_TEX_CLASS   8
 /* First-level page table bits */
 #define FL_BASE_MASK            0xFFFFFC00
@@ -63,6 +64,9 @@ do { \
 #define FL_AP_WRITE             (1 << 10)
 #define FL_AP_READ              (1 << 11)
 #define FL_SHARED               (1 << 16)
+#define FL_BUFFERABLE           (1 << 2)
+#define FL_CACHEABLE            (1 << 3)
+#define FL_TEX0                 (1 << 12)
 #define FL_OFFSET(va)           (((va) & 0xFFF00000) >> 20)
 /* Second-level page table bits */
@@ -73,8 +77,20 @@ do { \
 #define SL_AP0                  (1 << 4)
 #define SL_AP1                  (2 << 4)
 #define SL_SHARED               (1 << 10)
+#define SL_BUFFERABLE           (1 << 2)
+#define SL_CACHEABLE            (1 << 3)
+#define SL_TEX0                 (1 << 6)
 #define SL_OFFSET(va)           (((va) & 0xFF000) >> 12)
+/* Memory type and cache policy attributes */
+#define MT_SO                   0
+#define MT_DEV                  1
+#define MT_NORMAL               2
+#define CP_NONCACHED            0
+#define CP_WB_WA                1
+#define CP_WT                   2
+#define CP_WB_NWA               3
 /* Global register setters / getters */
 #define SET_M2VCBR_N(b, N, v)    SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
 #define SET_CBACR_N(b, N, v)     SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
@@ -706,7 +722,9 @@ do { \
 #define GET_OCPC5(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
 #define GET_OCPC6(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
 #define GET_OCPC7(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
+#define NMRR_ICP(nmrr, n)       (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2))
+#define NMRR_OCP(nmrr, n)       (((nmrr) & (3 << ((n) * 2 + 16))) >> \
+                                                                ((n) * 2 + 16))
 /* PAR */
 #define GET_FAULT(b, c)         GET_CONTEXT_FIELD(b, c, PAR, FAULT)
@@ -750,6 +768,8 @@ do { \
 #define GET_NOS5(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
 #define GET_NOS6(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
 #define GET_NOS7(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
+#define PRRR_NOS(prrr, n)        ((prrr) & (1 << ((n) + 24)) ? 1 : 0)
+#define PRRR_MT(prrr, n)         ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2)))
 /* RESUME */
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
index 36074cfc9ad..f65841c74c0 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8x60.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -237,7 +237,12 @@
 #define GSBI11_QUP_IRQ                          (GIC_SPI_START + 194)
 #define INT_UART12DM_IRQ                        (GIC_SPI_START + 195)
 #define GSBI12_QUP_IRQ                          (GIC_SPI_START + 196)
-/*SPI 197 to 216 arent used in 8x60*/
+/*SPI 197 to 209 arent used in 8x60*/
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ            (GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 211)
+/*SPI 212 to 216 arent used in 8x60*/
 #define SMPSS_SPARE_1                           (GIC_SPI_START + 217)
 #define SMPSS_SPARE_2                           (GIC_SPI_START + 218)
 #define SMPSS_SPARE_3                           (GIC_SPI_START + 219)
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 8a00c2defbc..0fd7b68ca11 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -119,4 +119,7 @@
 #define MSM_AD5_PHYS          0xA7000000
 #define MSM_AD5_SIZE          (SZ_1M*13)
+#define MSM_HSUSB_PHYS        0xA3600000
+#define MSM_HSUSB_SIZE        SZ_1K
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 45bab50e3ee..7c43a9bff1a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -98,4 +98,7 @@
 #define MSM_IOMMU_GFX2D0_PHYS   0x07D00000
 #define MSM_IOMMU_GFX2D0_SIZE   SZ_1M
+#define MSM_IOMMU_GFX2D1_PHYS   0x07E00000
+#define MSM_IOMMU_GFX2D1_SIZE   SZ_1M
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index d36b6107414..f912d7bf188 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -163,3 +163,4 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
        return __arm_ioremap_caller(phys_addr, size, mtype,
                __builtin_return_address(0));
 }
+EXPORT_SYMBOL(__msm_ioremap);
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index f71747db3be..e2d58e4cb0d 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -33,6 +33,16 @@
 #include <mach/iommu_hw-8xxx.h>
 #include <mach/iommu.h>
+#define MRC(reg, processor, op1, crn, crm, op2)                         \
+__asm__ __volatile__ (                                                  \
+"   mrc   "   #processor "," #op1 ", %0,"  #crn "," #crm "," #op2 "\n"  \
+: "=r" (reg))
+#define RCP15_PRRR(reg)         MRC(reg, p15, 0, c10, c2, 0)
+#define RCP15_NMRR(reg)         MRC(reg, p15, 0, c10, c2, 1)
+static int msm_iommu_tex_class[4];
 DEFINE_SPINLOCK(msm_iommu_lock);
 struct msm_priv {
@@ -40,23 +50,26 @@ struct msm_priv {
        struct list_head list_attached;
 };
-static void __flush_iotlb(struct iommu_domain *domain)
+static int __flush_iotlb(struct iommu_domain *domain)
 {
        struct msm_priv *priv = domain->priv;
        struct msm_iommu_drvdata *iommu_drvdata;
        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+        int ret = 0;
 #ifndef CONFIG_IOMMU_PGTABLES_L2
        unsigned long *fl_table = priv->pgtable;
        int i;
-        dmac_flush_range(fl_table, fl_table + SZ_16K);
+        if (!list_empty(&priv->list_attached)) {
+                dmac_flush_range(fl_table, fl_table + SZ_16K);
-        for (i = 0; i < NUM_FL_PTE; i++)
+                for (i = 0; i < NUM_FL_PTE; i++)
-                if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
+                        if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
-                        void *sl_table = __va(fl_table[i] & FL_BASE_MASK);
+                                void *sl_table = __va(fl_table[i] &
-                        dmac_flush_range(sl_table, sl_table + SZ_4K);
+                                                                FL_BASE_MASK);
-                }
+                                dmac_flush_range(sl_table, sl_table + SZ_4K);
+                        }
+        }
 #endif
        list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
@@ -66,6 +79,8 @@ static void __flush_iotlb(struct iommu_domain *domain)
                iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
                SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
        }
+        return ret;
 }
 static void __reset_context(void __iomem *base, int ctx)
@@ -95,6 +110,7 @@ static void __reset_context(void __iomem *base, int ctx)
 static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
 {
+        unsigned int prrr, nmrr;
        __reset_context(base, ctx);
        /* Set up HTW mode */
@@ -127,11 +143,11 @@ static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
        /* Turn on TEX Remap */
        SET_TRE(base, ctx, 1);
-        /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
+        /* Set TEX remap attributes */
-         * TEX class 0 for everything until attributes are properly worked out
+        RCP15_PRRR(prrr);
-         */
+        RCP15_NMRR(nmrr);
-        SET_PRRR(base, ctx, 0);
+        SET_PRRR(base, ctx, prrr);
-        SET_NMRR(base, ctx, 0);
+        SET_NMRR(base, ctx, nmrr);
        /* Turn on BFB prefetch */
        SET_BFBDFE(base, ctx, 1);
@@ -238,6 +254,11 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
                goto fail;
        }
+        if (!list_empty(&ctx_drvdata->attached_elm)) {
+                ret = -EBUSY;
+                goto fail;
+        }
        list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
                if (tmp_drvdata == ctx_drvdata) {
                        ret = -EBUSY;
@@ -248,7 +269,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
                          __pa(priv->pgtable));
        list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
-        __flush_iotlb(domain);
+        ret = __flush_iotlb(domain);
 fail:
        spin_unlock_irqrestore(&msm_iommu_lock, flags);
@@ -263,6 +284,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain,
        struct msm_iommu_drvdata *iommu_drvdata;
        struct msm_iommu_ctx_drvdata *ctx_drvdata;
        unsigned long flags;
+        int ret;
        spin_lock_irqsave(&msm_iommu_lock, flags);
        priv = domain->priv;
@@ -277,7 +299,10 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain,
        if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
                goto fail;
-        __flush_iotlb(domain);
+        ret = __flush_iotlb(domain);
+        if (ret)
+                goto fail;
        __reset_context(iommu_drvdata->base, ctx_dev->num);
        list_del_init(&ctx_drvdata->attached_elm);
@@ -296,12 +321,21 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
        unsigned long *sl_table;
        unsigned long *sl_pte;
        unsigned long sl_offset;
+        unsigned int pgprot;
        size_t len = 0x1000UL << order;
-        int ret = 0;
+        int ret = 0, tex, sh;
        spin_lock_irqsave(&msm_iommu_lock, flags);
-        priv = domain->priv;
+        sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0;
+        tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK];
+        if (tex < 0 || tex > NUM_TEX_CLASS - 1) {
+                ret = -EINVAL;
+                goto fail;
+        }
+        priv = domain->priv;
        if (!priv) {
                ret = -EINVAL;
                goto fail;
@@ -322,6 +356,18 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
                goto fail;
        }
+        if (len == SZ_16M || len == SZ_1M) {
+                pgprot = sh ? FL_SHARED : 0;
+                pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0;
+                pgprot |= tex & 0x02 ? FL_CACHEABLE : 0;
+                pgprot |= tex & 0x04 ? FL_TEX0 : 0;
+        } else  {
+                pgprot = sh ? SL_SHARED : 0;
+                pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0;
+                pgprot |= tex & 0x02 ? SL_CACHEABLE : 0;
+                pgprot |= tex & 0x04 ? SL_TEX0 : 0;
+        }
        fl_offset = FL_OFFSET(va);      /* Upper 12 bits */
        fl_pte = fl_table + fl_offset;  /* int pointers, 4 bytes */
@@ -330,17 +376,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
                for (i = 0; i < 16; i++)
                        *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
                                  FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
-                                  FL_SHARED;
+                                  FL_SHARED | pgprot;
        }
        if (len == SZ_1M)
                *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
-                                                FL_TYPE_SECT | FL_SHARED;
+                                            FL_TYPE_SECT | FL_SHARED | pgprot;
        /* Need a 2nd level table */
        if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
                unsigned long *sl;
-                sl = (unsigned long *) __get_free_pages(GFP_KERNEL,
+                sl = (unsigned long *) __get_free_pages(GFP_ATOMIC,
                                                        get_order(SZ_4K));
                if (!sl) {
@@ -360,17 +406,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
        if (len == SZ_4K)
                *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
-                                          SL_SHARED | SL_TYPE_SMALL;
+                                          SL_SHARED | SL_TYPE_SMALL | pgprot;
        if (len == SZ_64K) {
                int i;
                for (i = 0; i < 16; i++)
                        *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
-                                            SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
+                                SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
        }
-        __flush_iotlb(domain);
+        ret = __flush_iotlb(domain);
 fail:
        spin_unlock_irqrestore(&msm_iommu_lock, flags);
        return ret;
@@ -455,7 +501,7 @@ static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
                }
        }
-        __flush_iotlb(domain);
+        ret = __flush_iotlb(domain);
 fail:
        spin_unlock_irqrestore(&msm_iommu_lock, flags);
        return ret;
@@ -490,9 +536,6 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
        SET_CTX_TLBIALL(base, ctx, 0);
        SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
-        if (GET_FAULT(base, ctx))
-                goto fail;
        par = GET_PAR(base, ctx);
        /* We are dealing with a supersection */
@@ -501,6 +544,9 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
        else    /* Upper 20 bits from PAR, lower 12 from VA */
                ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
+        if (GET_FAULT(base, ctx))
+                ret = 0;
 fail:
        spin_unlock_irqrestore(&msm_iommu_lock, flags);
        return ret;
@@ -543,8 +589,8 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
 {
        struct msm_iommu_drvdata *drvdata = dev_id;
        void __iomem *base;
-        unsigned int fsr = 0;
+        unsigned int fsr;
-        int ncb = 0, i = 0;
+        int ncb, i;
        spin_lock(&msm_iommu_lock);
@@ -555,7 +601,6 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
        base = drvdata->base;
-        pr_err("===== WOAH! =====\n");
        pr_err("Unexpected IOMMU page fault!\n");
        pr_err("base = %08x\n", (unsigned int) base);
@@ -585,8 +630,47 @@ static struct iommu_ops msm_iommu_ops = {
        .domain_has_cap = msm_iommu_domain_has_cap
 };
-static int msm_iommu_init(void)
+static int __init get_tex_class(int icp, int ocp, int mt, int nos)
+{
+        int i = 0;
+        unsigned int prrr = 0;
+        unsigned int nmrr = 0;
+        int c_icp, c_ocp, c_mt, c_nos;
+        RCP15_PRRR(prrr);
+        RCP15_NMRR(nmrr);
+        for (i = 0; i < NUM_TEX_CLASS; i++) {
+                c_nos = PRRR_NOS(prrr, i);
+                c_mt = PRRR_MT(prrr, i);
+                c_icp = NMRR_ICP(nmrr, i);
+                c_ocp = NMRR_OCP(nmrr, i);
+                if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos)
+                        return i;
+        }
+        return -ENODEV;
+}
+static void __init setup_iommu_tex_classes(void)
+{
+        msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] =
+                        get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1);
+        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] =
+                        get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1);
+        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] =
+                        get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1);
+        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] =
+                        get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1);
+}
+static int __init msm_iommu_init(void)
 {
+        setup_iommu_tex_classes();
        register_iommu(&msm_iommu_ops);
        return 0;
 }
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
index 9019cee2907..b83c73b41fd 100644
--- a/arch/arm/mach-msm/iommu_dev.c
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -346,7 +346,7 @@ static struct platform_driver msm_iommu_ctx_driver = {
        .remove         = msm_iommu_ctx_remove,
 };
-static int msm_iommu_driver_init(void)
+static int __init msm_iommu_driver_init(void)
 {
        int ret;
        ret = platform_driver_register(&msm_iommu_driver);
@@ -365,7 +365,7 @@ error:
        return ret;
 }
-static void msm_iommu_driver_exit(void)
+static void __exit msm_iommu_driver_exit(void)
 {
        platform_driver_unregister(&msm_iommu_ctx_driver);
        platform_driver_unregister(&msm_iommu_driver);
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index b0794524ba6..152eefda3ce 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -40,9 +40,6 @@ static struct sirc_cascade_regs sirc_reg_table[] = {
        }
 };
-static unsigned int save_type;
-static unsigned int save_polarity;
 /* Mask off the given interrupt. Keep the int_enable mask in sync with
   the enable reg, so it can be restored after power collapse. */
 static void sirc_irq_mask(unsigned int irq)
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index f07dc7c738f..657be73297d 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -14,6 +14,8 @@
 *
 */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/fs.h>
@@ -89,7 +91,7 @@ static void smd_diag(void)
        x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG);
        if (x != 0) {
                x[SZ_DIAG_ERR_MSG - 1] = 0;
-                pr_info("smem: DIAG '%s'\n", x);
+                pr_debug("DIAG '%s'\n", x);
        }
 }
@@ -312,7 +314,7 @@ static void smd_state_change(struct smd_channel *ch,
 {
        ch->last_state = next;
-        pr_info("SMD: ch %d %d -> %d\n", ch->n, last, next);
+        pr_debug("ch %d %d -> %d\n", ch->n, last, next);
        switch (next) {
        case SMD_SS_OPENING:
@@ -601,7 +603,7 @@ static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type)
        ch->pdev.name = ch->name;
        ch->pdev.id = -1;
-        pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
+        pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
                ch->n, ch->fifo_size, ch->name);
        mutex_lock(&smd_creation_mutex);
@@ -621,7 +623,7 @@ static void smd_channel_probe_worker(struct work_struct *work)
        shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
        if (!shared) {
-                pr_err("smd: cannot find allocation table\n");
+                pr_err("cannot find allocation table\n");
                return;
        }
        for (n = 0; n < 64; n++) {
@@ -725,8 +727,6 @@ int smd_close(smd_channel_t *ch)
 {
        unsigned long flags;
-        pr_info("smd_close(%p)\n", ch);
        if (ch == 0)
                return -1;
@@ -939,7 +939,6 @@ int smsm_set_sleep_duration(uint32_t delay)
 int smd_core_init(void)
 {
        int r;
-        pr_info("smd_core_init()\n");
        /* wait for essential items to be initialized */
        for (;;) {
@@ -992,15 +991,11 @@ int smd_core_init(void)
        smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0);
 #endif
-        pr_info("smd_core_init() done\n");
        return 0;
 }
 static int __devinit msm_smd_probe(struct platform_device *pdev)
 {
-        pr_info("smd_init()\n");
        /*
         * If we haven't waited for the ARM9 to boot up till now,
         * then we need to wait here. Otherwise this should just
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
index f91c3b7bc65..8736afff82f 100644
--- a/arch/arm/mach-msm/smd_debug.c
+++ b/arch/arm/mach-msm/smd_debug.c
@@ -270,8 +270,10 @@ void smsm_print_sleep_info(void)
 {
        unsigned long flags;
        uint32_t *ptr;
+#ifndef CONFIG_ARCH_MSM_SCORPION
        struct tramp_gpio_smem *gpio;
        struct smsm_interrupt_info *int_info;
+#endif
        spin_lock_irqsave(&smem_lock, flags);
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 89ed1be2d62..8be26150605 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -642,31 +642,13 @@ static void __init omap3pandora_init_irq(void)
        omap_gpio_init();
 }
-static void pandora_wl1251_set_power(bool enable)
+static void __init pandora_wl1251_init(void)
-{
-        /*
-         * Keep power always on until wl1251_sdio driver learns to re-init
-         * the chip after powering it down and back up.
-         */
-}
-static struct wl12xx_platform_data pandora_wl1251_pdata = {
-        .set_power      = pandora_wl1251_set_power,
-        .use_eeprom     = true,
-};
-static struct platform_device pandora_wl1251_data = {
-        .name           = "wl1251_data",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &pandora_wl1251_pdata,
-        },
-};
-static void pandora_wl1251_init(void)
 {
+        struct wl12xx_platform_data pandora_wl1251_pdata;
        int ret;
+        memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata));
        ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq");
        if (ret < 0)
                goto fail;
@@ -679,6 +661,11 @@ static void pandora_wl1251_init(void)
        if (pandora_wl1251_pdata.irq < 0)
                goto fail_irq;
+        pandora_wl1251_pdata.use_eeprom = true;
+        ret = wl12xx_set_platform_data(&pandora_wl1251_pdata);
+        if (ret < 0)
+                goto fail_irq;
        return;
 fail_irq:
@@ -691,7 +678,6 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
        &pandora_leds_gpio,
        &pandora_keys_gpio,
        &pandora_dss_device,
-        &pandora_wl1251_data,
        &pandora_vwlan_device,
 };
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 86c9b210295..9db9203667d 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -216,7 +216,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
        {
                .name           = "wl1271",
                .mmc            = 3,
-                .caps           = MMC_CAP_4_BIT_DATA,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
                .gpio_wp        = -EINVAL,
                .gpio_cd        = -EINVAL,
                .nonremovable   = true,
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 40562ddd3ee..a1939b1e6f8 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -297,7 +297,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
                return 0;
        dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
-        if (!dpll3_m2_ck)
+        if (IS_ERR(dpll3_m2_ck))
                return -EINVAL;
        rate = clk_get_rate(dpll3_m2_ck);
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 5e81517a7af..a8afb610c7d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -161,6 +161,23 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
                printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 }
+void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
+{
+        u32 tick_rate, cycles;
+        if (!seconds && !milliseconds)
+                return;
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
+        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
+        omap_dm_timer_stop(gptimer_wakeup);
+        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
+        pr_info("PM: Resume timer in %u.%03u secs"
+                " (%d ticks at %d ticks/sec.)\n",
+                seconds, milliseconds, cycles, tick_rate);
+}
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
@@ -354,23 +371,6 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
        pwrdm->timer = t;
 }
-void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
-{
-        u32 tick_rate, cycles;
-        if (!seconds && !milliseconds)
-                return;
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
-        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
-        omap_dm_timer_stop(gptimer_wakeup);
-        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
-        pr_info("PM: Resume timer in %u.%03u secs"
-                " (%d ticks at %d ticks/sec.)\n",
-                seconds, milliseconds, cycles, tick_rate);
-}
 static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
 {
        struct seq_file *s = (struct seq_file *)user;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index c85923e56b8..aaeea49b9bd 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,6 +53,19 @@
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state = PM_SUSPEND_ON;
+static inline bool is_suspending(void)
+{
+        return (suspend_state != PM_SUSPEND_ON);
+}
+#else
+static inline bool is_suspending(void)
+{
+        return false;
+}
+#endif
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
                                  void __iomem *sdrc_power);
@@ -120,8 +133,9 @@ static void omap2_enter_full_retention(void)
                goto no_sleep;
        /* Block console output in case it is on one of the OMAP UARTs */
-        if (try_acquire_console_sem())
+        if (!is_suspending())
-                goto no_sleep;
+                if (try_acquire_console_sem())
+                        goto no_sleep;
        omap_uart_prepare_idle(0);
        omap_uart_prepare_idle(1);
@@ -136,7 +150,8 @@ static void omap2_enter_full_retention(void)
        omap_uart_resume_idle(1);
        omap_uart_resume_idle(0);
-        release_console_sem();
+        if (!is_suspending())
+                release_console_sem();
 no_sleep:
        if (omap2_pm_debug) {
@@ -284,6 +299,12 @@ out:
        local_irq_enable();
 }
+static int omap2_pm_begin(suspend_state_t state)
+{
+        suspend_state = state;
+        return 0;
+}
 static int omap2_pm_prepare(void)
 {
        /* We cannot sleep in idle until we have resumed */
@@ -333,10 +354,17 @@ static void omap2_pm_finish(void)
        enable_hlt();
 }
+static void omap2_pm_end(void)
+{
+        suspend_state = PM_SUSPEND_ON;
+}
 static struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap2_pm_begin,
        .prepare        = omap2_pm_prepare,
        .enter          = omap2_pm_enter,
        .finish         = omap2_pm_finish,
+        .end            = omap2_pm_end,
        .valid          = suspend_valid_only_mem,
 };
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 0ec8a04b747..648b8c50d02 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -50,6 +50,19 @@
 #include "sdrc.h"
 #include "control.h"
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state = PM_SUSPEND_ON;
+static inline bool is_suspending(void)
+{
+        return (suspend_state != PM_SUSPEND_ON);
+}
+#else
+static inline bool is_suspending(void)
+{
+        return false;
+}
+#endif
 /* Scratchpad offsets */
 #define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
@@ -387,10 +400,11 @@ void omap_sram_idle(void)
        }
        /* Block console output in case it is on one of the OMAP UARTs */
-        if (per_next_state < PWRDM_POWER_ON ||
+        if (!is_suspending())
-            core_next_state < PWRDM_POWER_ON)
+                if (per_next_state < PWRDM_POWER_ON ||
-                if (try_acquire_console_sem())
+                    core_next_state < PWRDM_POWER_ON)
-                        goto console_still_active;
+                        if (try_acquire_console_sem())
+                                goto console_still_active;
        /* PER */
        if (per_next_state < PWRDM_POWER_ON) {
@@ -470,7 +484,8 @@ void omap_sram_idle(void)
                omap_uart_resume_idle(3);
        }
-        release_console_sem();
+        if (!is_suspending())
+                release_console_sem();
 console_still_active:
        /* Disable IO-PAD and IO-CHAIN wakeup */
@@ -514,8 +529,6 @@ out:
 }
 #ifdef CONFIG_SUSPEND
-static suspend_state_t suspend_state;
 static int omap3_pm_prepare(void)
 {
        disable_hlt();
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 298a22a754e..f81acee4738 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -243,13 +243,14 @@
 #define OMAP24XX_EN_GPT1_MASK                           (1 << 0)
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS_SHIFT                         (1 << 2)
+#define OMAP24XX_ST_GPIOS_SHIFT                         2
-#define OMAP24XX_ST_GPIOS_MASK                          2
+#define OMAP24XX_ST_GPIOS_MASK                          (1 << 2)
-#define OMAP24XX_ST_GPT1_SHIFT                          (1 << 0)
+#define OMAP24XX_ST_GPT1_SHIFT                          0
-#define OMAP24XX_ST_GPT1_MASK                           0
+#define OMAP24XX_ST_GPT1_MASK                           (1 << 0)
 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM_SHIFT                           (1 << 0)
+#define OMAP2430_ST_MDM_SHIFT                           0
+#define OMAP2430_ST_MDM_MASK                            (1 << 0)
 /* 3430 register bits shared between CM & PRM registers */
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index dd235ecc9d6..c93e73d54dd 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -540,6 +540,7 @@ config MACH_ICONTROL
 config ARCH_PXA_ESERIES
        bool "PXA based Toshiba e-series PDAs"
        select PXA25x
+        select FB_W100
 config MACH_E330
        bool "Toshiba e330"
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index d2060a1d1d6..e5c9932b758 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -241,7 +241,8 @@ static inline void palmtx_keys_init(void) {}
 /******************************************************************************
 * NAND Flash
 ******************************************************************************/
-#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
+#if defined(CONFIG_MTD_NAND_PLATFORM) || \
+        defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 static void palmtx_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
                                 unsigned int ctrl)
 {
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 52c30b01a67..ae008110db4 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -353,8 +353,8 @@ resume_turn_on_mmu:
        @ Let us ensure we jump to resume_after_mmu only when the mcr above
        @ actually took effect.  They call it the "cpwait" operation.
-        mrc     p15, 0, r1, c2, c0, 0           @ queue a dependency on CP15
+        mrc     p15, 0, r0, c2, c0, 0           @ queue a dependency on CP15
-        sub     pc, r2, r1, lsr #32             @ jump to virtual addr
+        sub     pc, r2, r0, lsr #32             @ jump to virtual addr
        nop
        nop
        nop
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index fa2e5bffbb8..6983cb4d4ca 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -28,9 +28,16 @@ config S3C2412_DMA
 config S3C2412_PM
        bool
+        select S3C2412_PM_SLEEP
        help
          Internal config node to apply S3C2412 power management
+config S3C2412_PM_SLEEP
+        bool
+        help
+          Internal config node to apply sleep for S3C2412 power management.
+          Can be selected by another SoCs with similar sleep procedure.
 # Note, the S3C2412 IOtiming support is in plat-s3c24xx
 config S3C2412_CPUFREQ
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 530ec46cbae..6c48a91ea39 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -14,7 +14,8 @@ obj-$(CONFIG_CPU_S3C2412)	+= irq.o
 obj-$(CONFIG_CPU_S3C2412)       += clock.o
 obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
-obj-$(CONFIG_S3C2412_PM)        += pm.o sleep.o
+obj-$(CONFIG_S3C2412_PM)        += pm.o
+obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
 # Machine support
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 27b3e7c9d61..df8d14974c9 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -27,6 +27,7 @@ config S3C2416_DMA
 config S3C2416_PM
        bool
+        select S3C2412_PM_SLEEP
        help
          Internal config node to apply S3C2416 power management
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 28677caf361..461aa035afc 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -378,6 +378,12 @@ static struct max8998_regulator_data aquila_regulators[] = {
 static struct max8998_platform_data aquila_max8998_pdata = {
        .num_regulators = ARRAY_SIZE(aquila_regulators),
        .regulators     = aquila_regulators,
+        .buck1_set1     = S5PV210_GPH0(3),
+        .buck1_set2     = S5PV210_GPH0(4),
+        .buck2_set3     = S5PV210_GPH0(5),
+        .buck1_max_voltage1 = 1200000,
+        .buck1_max_voltage2 = 1200000,
+        .buck2_max_voltage = 1200000,
 };
 #endif
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index b1dcf964a76..e22d5112fd4 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -518,6 +518,12 @@ static struct max8998_regulator_data goni_regulators[] = {
 static struct max8998_platform_data goni_max8998_pdata = {
        .num_regulators = ARRAY_SIZE(goni_regulators),
        .regulators     = goni_regulators,
+        .buck1_set1     = S5PV210_GPH0(3),
+        .buck1_set2     = S5PV210_GPH0(4),
+        .buck2_set3     = S5PV210_GPH0(5),
+        .buck1_max_voltage1 = 1200000,
+        .buck1_max_voltage2 = 1200000,
+        .buck2_max_voltage = 1200000,
 };
 #endif
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index d440e5f456a..b1222dc4338 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -501,7 +501,12 @@ static struct platform_device keysc_device = {
 static struct resource mipidsi0_resources[] = {
        [0] = {
                .start  = 0xffc60000,
-                .end    = 0xffc68fff,
+                .end    = 0xffc63073,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffc68000,
+                .end    = 0xffc680ef,
                .flags  = IORESOURCE_MEM,
        },
 };
@@ -509,6 +514,7 @@ static struct resource mipidsi0_resources[] = {
 static struct sh_mipi_dsi_info mipidsi0_info = {
        .data_format    = MIPI_RGB888,
        .lcd_chan       = &lcdc_info.ch[0],
+        .vsynw_offset   = 17,
 };
 static struct platform_device mipidsi0_device = {
@@ -521,44 +527,6 @@ static struct platform_device mipidsi0_device = {
        },
 };
-/* This function will disappear when we switch to (runtime) PM */
-static int __init ap4evb_init_display_clk(void)
-{
-        struct clk *lcdc_clk;
-        struct clk *dsitx_clk;
-        int ret;
-        lcdc_clk = clk_get(&lcdc_device.dev, "sh_mobile_lcdc_fb.0");
-        if (IS_ERR(lcdc_clk))
-                return PTR_ERR(lcdc_clk);
-        dsitx_clk = clk_get(&mipidsi0_device.dev, "sh-mipi-dsi.0");
-        if (IS_ERR(dsitx_clk)) {
-                ret = PTR_ERR(dsitx_clk);
-                goto eclkdsitxget;
-        }
-        ret = clk_enable(lcdc_clk);
-        if (ret < 0)
-                goto eclklcdcon;
-        ret = clk_enable(dsitx_clk);
-        if (ret < 0)
-                goto eclkdsitxon;
-        return 0;
-eclkdsitxon:
-        clk_disable(lcdc_clk);
-eclklcdcon:
-        clk_put(dsitx_clk);
-eclkdsitxget:
-        clk_put(lcdc_clk);
-        return ret;
-}
-device_initcall(ap4evb_init_display_clk);
 static struct platform_device *qhd_devices[] __initdata = {
        &mipidsi0_device,
        &keysc_device,
@@ -764,10 +732,15 @@ static struct platform_device lcdc1_device = {
        },
 };
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+                                unsigned long *parent_freq);
 static struct sh_mobile_hdmi_info hdmi_info = {
        .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
        .lcd_dev = &lcdc1_device.dev,
        .flags = HDMI_SND_SRC_SPDIF,
+        .clk_optimize_parent = ap4evb_clk_optimize,
 };
 static struct resource hdmi_resources[] = {
@@ -794,6 +767,25 @@ static struct platform_device hdmi_device = {
        },
 };
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+                                unsigned long *parent_freq)
+{
+        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+        long error;
+        if (IS_ERR(hdmi_ick)) {
+                int ret = PTR_ERR(hdmi_ick);
+                pr_err("Cannot get HDMI ICK: %d\n", ret);
+                return ret;
+        }
+        error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
+        clk_put(hdmi_ick);
+        return error;
+}
 static struct gpio_led ap4evb_leds[] = {
        {
                .name                   = "led4",
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 3aa02606943..66663adb21f 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -507,7 +507,7 @@ enum { MSTP001,
       MSTP223,
       MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
       MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
-       MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
+       MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
       MSTP_NR };
 #define MSTP(_parent, _reg, _bit, _flags) \
@@ -543,6 +543,7 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
        [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
        [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
+        [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
        [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
        [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
        [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
@@ -596,9 +597,10 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
        CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
        CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
-        CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
-        CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
-        CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
+        CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
@@ -610,7 +612,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
-        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
+        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
@@ -633,6 +635,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
+        CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
        CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index a285d13c741..f428c4db2b6 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2010 Magnus Damm
 * Copyright (C) 2008 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or modify
@@ -14,24 +15,45 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-#include <mach/hardware.h>
 #include <mach/irqs.h>
+#define INTCA_BASE      0xe6980000
+#define INTFLGA_OFFS    0x00000018 /* accept pending interrupt */
+#define INTEVTA_OFFS    0x00000020 /* vector number of accepted interrupt */
+#define INTLVLA_OFFS    0x00000030 /* priority level of accepted interrupt */
+#define INTLVLB_OFFS    0x00000034 /* previous priority level */
        .macro  disable_fiq
        .endm
        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =INTFLGA
+        ldr     \base, =INTCA_BASE
        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base]
+        /* The single INTFLGA read access below results in the following:
+         *
+         * 1. INTLVLB is updated with old priority value from INTLVLA
+         * 2. Highest priority interrupt is accepted
+         * 3. INTLVLA is updated to contain priority of accepted interrupt
+         * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
+         */
+        ldr     \irqnr, [\base, #INTFLGA_OFFS]
+        /* Restore INTLVLA with the value saved in INTLVLB.
+         * This is required to support interrupt priorities properly.
+         */
+        ldrb    \tmp, [\base, #INTLVLB_OFFS]
+        strb    \tmp, [\base, #INTLVLA_OFFS]
+        /* Handle invalid vector number case */
        cmp     \irqnr, #0
        beq     1000f
-        /* intevt to irq number */
+        /* Convert vector to irq number, same as the evt2irq() macro */
        lsr     \irqnr, \irqnr, #0x5
        subs    \irqnr, \irqnr, #16
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
index 4aecf6e3a85..2b8fd8b942f 100644
--- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
+++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h
@@ -2,6 +2,6 @@
 #define __ASM_MACH_VMALLOC_H
 /* Vmalloc at ... - 0xe5ffffff */
-#define VMALLOC_END 0xe6000000
+#define VMALLOC_END 0xe6000000UL
 #endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 6e77c042d8e..e0b0e7a4ec6 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -13,13 +13,9 @@
 */
 #include <linux/init.h>
+#include <linux/highmem.h>
 #include <asm/cacheflush.h>
-#include <asm/kmap_types.h>
-#include <asm/fixmap.h>
-#include <asm/pgtable.h>
-#include <asm/tlbflush.h>
 #include <plat/cache-feroceon-l2.h>
-#include "mm.h"
 /*
 * Low-level cache maintenance operations.
@@ -39,27 +35,30 @@
 * between which we don't want to be preempted.
 */
-static inline unsigned long l2_start_va(unsigned long paddr)
+static inline unsigned long l2_get_va(unsigned long paddr)
 {
 #ifdef CONFIG_HIGHMEM
        /*
-         * Let's do our own fixmap stuff in a minimal way here.
         * Because range ops can't be done on physical addresses,
         * we simply install a virtual mapping for it only for the
         * TLB lookup to occur, hence no need to flush the untouched
-         * memory mapping.  This is protected with the disabling of
+         * memory mapping afterwards (note: a cache flush may happen
-         * interrupts by the caller.
+         * in some circumstances depending on the path taken in kunmap_atomic).
         */
-        unsigned long idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id();
+        void *vaddr = kmap_atomic_pfn(paddr >> PAGE_SHIFT);
-        unsigned long vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+        return (unsigned long)vaddr + (paddr & ~PAGE_MASK);
-        set_pte_ext(TOP_PTE(vaddr), pfn_pte(paddr >> PAGE_SHIFT, PAGE_KERNEL), 0);
-        local_flush_tlb_kernel_page(vaddr);
-        return vaddr + (paddr & ~PAGE_MASK);
 #else
        return __phys_to_virt(paddr);
 #endif
 }
+static inline void l2_put_va(unsigned long vaddr)
+{
+#ifdef CONFIG_HIGHMEM
+        kunmap_atomic((void *)vaddr);
+#endif
+}
 static inline void l2_clean_pa(unsigned long addr)
 {
        __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
@@ -76,13 +75,14 @@ static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
         */
        BUG_ON((start ^ end) >> PAGE_SHIFT);
-        raw_local_irq_save(flags);
+        va_start = l2_get_va(start);
-        va_start = l2_start_va(start);
        va_end = va_start + (end - start);
+        raw_local_irq_save(flags);
        __asm__("mcr p15, 1, %0, c15, c9, 4\n\t"
                "mcr p15, 1, %1, c15, c9, 5"
                : : "r" (va_start), "r" (va_end));
        raw_local_irq_restore(flags);
+        l2_put_va(va_start);
 }
 static inline void l2_clean_inv_pa(unsigned long addr)
@@ -106,13 +106,14 @@ static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
         */
        BUG_ON((start ^ end) >> PAGE_SHIFT);
-        raw_local_irq_save(flags);
+        va_start = l2_get_va(start);
-        va_start = l2_start_va(start);
        va_end = va_start + (end - start);
+        raw_local_irq_save(flags);
        __asm__("mcr p15, 1, %0, c15, c11, 4\n\t"
                "mcr p15, 1, %1, c15, c11, 5"
                : : "r" (va_start), "r" (va_end));
        raw_local_irq_restore(flags);
+        l2_put_va(va_start);
 }
 static inline void l2_inv_all(void)
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 99fa688dfad..c96fa1b3f49 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -203,6 +203,10 @@ ENTRY(v6_flush_kern_dcache_area)
 *      - end     - virtual end address of region
 */
 v6_dma_inv_range:
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrb    r2, [r0]                        @ read for ownership
+        strb    r2, [r0]                        @ write for ownership
+#endif
        tst     r0, #D_CACHE_LINE_SIZE - 1
        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
@@ -211,6 +215,10 @@ v6_dma_inv_range:
        mcrne   p15, 0, r0, c7, c11, 1          @ clean unified line
 #endif
        tst     r1, #D_CACHE_LINE_SIZE - 1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrneb  r2, [r1, #-1]                   @ read for ownership
+        strneb  r2, [r1, #-1]                   @ write for ownership
+#endif
        bic     r1, r1, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
        mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D line
@@ -218,10 +226,6 @@ v6_dma_inv_range:
        mcrne   p15, 0, r1, c7, c15, 1          @ clean & invalidate unified line
 #endif
 1:
-#ifdef CONFIG_DMA_CACHE_RWFO
-        ldr     r2, [r0]                        @ read for ownership
-        str     r2, [r0]                        @ write for ownership
-#endif
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D line
 #else
@@ -229,6 +233,10 @@ v6_dma_inv_range:
 #endif
        add     r0, r0, #D_CACHE_LINE_SIZE
        cmp     r0, r1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrlo   r2, [r0]                        @ read for ownership
+        strlo   r2, [r0]                        @ write for ownership
+#endif
        blo     1b
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
@@ -263,12 +271,12 @@ v6_dma_clean_range:
 *      - end     - virtual end address of region
 */
 ENTRY(v6_dma_flush_range)
-        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
-1:
 #ifdef CONFIG_DMA_CACHE_RWFO
-        ldr     r2, [r0]                        @ read for ownership
+        ldrb    r2, [r0]                @ read for ownership
-        str     r2, [r0]                        @ write for ownership
+        strb    r2, [r0]                @ write for ownership
 #endif
+        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
+1:
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
 #else
@@ -276,6 +284,10 @@ ENTRY(v6_dma_flush_range)
 #endif
        add     r0, r0, #D_CACHE_LINE_SIZE
        cmp     r0, r1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrlob  r2, [r0]                        @ read for ownership
+        strlob  r2, [r0]                        @ write for ownership
+#endif
        blo     1b
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a3ebf7a4f49..6136e68ce95 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -173,15 +173,22 @@ ENTRY(v7_coherent_user_range)
 UNWIND(.fnstart                )
        dcache_line_size r2, r3
        sub     r3, r2, #1
-        bic     r0, r0, r3
+        bic     r12, r0, r3
 1:
- USER(  mcr     p15, 0, r0, c7, c11, 1  )       @ clean D line to the point of unification
+ USER(  mcr     p15, 0, r12, c7, c11, 1 )       @ clean D line to the point of unification
+        add     r12, r12, r2
+        cmp     r12, r1
+        blo     1b
        dsb
- USER(  mcr     p15, 0, r0, c7, c5, 1   )       @ invalidate I line
+        icache_line_size r2, r3
-        add     r0, r0, r2
+        sub     r3, r2, #1
+        bic     r12, r0, r3
 2:
-        cmp     r0, r1
+ USER(  mcr     p15, 0, r12, c7, c5, 1  )       @ invalidate I line
-        blo     1b
+        add     r12, r12, r2
+        cmp     r12, r1
+        blo     2b
+3:
        mov     r0, #0
        ALT_SMP(mcr     p15, 0, r0, c7, c1, 6)  @ invalidate BTB Inner Shareable
        ALT_UP(mcr      p15, 0, r0, c7, c5, 6)  @ invalidate BTB
@@ -194,10 +201,10 @@ ENTRY(v7_coherent_user_range)
 * isn't mapped, just try the next page.
 */
 9001:
-        mov     r0, r0, lsr #12
+        mov     r12, r12, lsr #12
-        mov     r0, r0, lsl #12
+        mov     r12, r12, lsl #12
-        add     r0, r0, #4096
+        add     r12, r12, #4096
-        b       2b
+        b       3b
 UNWIND(.fnend          )
 ENDPROC(v7_coherent_kern_range)
 ENDPROC(v7_coherent_user_range)
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index c3154928bcc..5a32020471e 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -17,14 +17,10 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
 #include <linux/init.h>
+#include <linux/highmem.h>
 #include <asm/system.h>
 #include <asm/cputype.h>
 #include <asm/cacheflush.h>
-#include <asm/kmap_types.h>
-#include <asm/fixmap.h>
-#include <asm/pgtable.h>
-#include <asm/tlbflush.h>
-#include "mm.h"
 #define CR_L2   (1 << 26)
@@ -71,16 +67,15 @@ static inline void xsc3_l2_inv_all(void)
        dsb();
 }
+static inline void l2_unmap_va(unsigned long va)
+{
 #ifdef CONFIG_HIGHMEM
-#define l2_map_save_flags(x)            raw_local_save_flags(x)
+        if (va != -1)
-#define l2_map_restore_flags(x)         raw_local_irq_restore(x)
+                kunmap_atomic((void *)va);
-#else
-#define l2_map_save_flags(x)            ((x) = 0)
-#define l2_map_restore_flags(x)         ((void)(x))
 #endif
+}
-static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va,
+static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va)
-                                      unsigned long flags)
 {
 #ifdef CONFIG_HIGHMEM
        unsigned long va = prev_va & PAGE_MASK;
@@ -89,17 +84,10 @@ static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va,
                /*
                 * Switching to a new page.  Because cache ops are
                 * using virtual addresses only, we must put a mapping
-                 * in place for it.  We also enable interrupts for a
+                 * in place for it.
-                 * short while and disable them again to protect this
-                 * mapping.
                 */
-                unsigned long idx;
+                l2_unmap_va(prev_va);
-                raw_local_irq_restore(flags);
+                va = (unsigned long)kmap_atomic_pfn(pa >> PAGE_SHIFT);
-                idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id();
-                va = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-                raw_local_irq_restore(flags | PSR_I_BIT);
-                set_pte_ext(TOP_PTE(va), pfn_pte(pa >> PAGE_SHIFT, PAGE_KERNEL), 0);
-                local_flush_tlb_kernel_page(va);
        }
        return va + (pa_offset >> (32 - PAGE_SHIFT));
 #else
@@ -109,7 +97,7 @@ static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va,
 static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
 {
-        unsigned long vaddr, flags;
+        unsigned long vaddr;
        if (start == 0 && end == -1ul) {
                xsc3_l2_inv_all();
@@ -117,13 +105,12 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
        }
        vaddr = -1;  /* to force the first mapping */
-        l2_map_save_flags(flags);
        /*
         * Clean and invalidate partial first cache line.
         */
        if (start & (CACHE_LINE_SIZE - 1)) {
-                vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr, flags);
+                vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr);
                xsc3_l2_clean_mva(vaddr);
                xsc3_l2_inv_mva(vaddr);
                start = (start | (CACHE_LINE_SIZE - 1)) + 1;
@@ -133,7 +120,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
         * Invalidate all full cache lines between 'start' and 'end'.
         */
        while (start < (end & ~(CACHE_LINE_SIZE - 1))) {
-                vaddr = l2_map_va(start, vaddr, flags);
+                vaddr = l2_map_va(start, vaddr);
                xsc3_l2_inv_mva(vaddr);
                start += CACHE_LINE_SIZE;
        }
@@ -142,31 +129,30 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
         * Clean and invalidate partial last cache line.
         */
        if (start < end) {
-                vaddr = l2_map_va(start, vaddr, flags);
+                vaddr = l2_map_va(start, vaddr);
                xsc3_l2_clean_mva(vaddr);
                xsc3_l2_inv_mva(vaddr);
        }
-        l2_map_restore_flags(flags);
+        l2_unmap_va(vaddr);
        dsb();
 }
 static void xsc3_l2_clean_range(unsigned long start, unsigned long end)
 {
-        unsigned long vaddr, flags;
+        unsigned long vaddr;
        vaddr = -1;  /* to force the first mapping */
-        l2_map_save_flags(flags);
        start &= ~(CACHE_LINE_SIZE - 1);
        while (start < end) {
-                vaddr = l2_map_va(start, vaddr, flags);
+                vaddr = l2_map_va(start, vaddr);
                xsc3_l2_clean_mva(vaddr);
                start += CACHE_LINE_SIZE;
        }
-        l2_map_restore_flags(flags);
+        l2_unmap_va(vaddr);
        dsb();
 }
@@ -193,7 +179,7 @@ static inline void xsc3_l2_flush_all(void)
 static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
 {
-        unsigned long vaddr, flags;
+        unsigned long vaddr;
        if (start == 0 && end == -1ul) {
                xsc3_l2_flush_all();
@@ -201,17 +187,16 @@ static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
        }
        vaddr = -1;  /* to force the first mapping */
-        l2_map_save_flags(flags);
        start &= ~(CACHE_LINE_SIZE - 1);
        while (start < end) {
-                vaddr = l2_map_va(start, vaddr, flags);
+                vaddr = l2_map_va(start, vaddr);
                xsc3_l2_clean_mva(vaddr);
                xsc3_l2_inv_mva(vaddr);
                start += CACHE_LINE_SIZE;
        }
-        l2_map_restore_flags(flags);
+        l2_unmap_va(vaddr);
        dsb();
 }
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index ac6a36142fc..809f1bf9fa2 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <linux/highmem.h>
 #include <asm/memory.h>
 #include <asm/highmem.h>
@@ -480,10 +481,10 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
                                op(vaddr, len, dir);
                                kunmap_high(page);
                        } else if (cache_is_vipt()) {
-                                pte_t saved_pte;
+                                /* unmapped pages might still be cached */
-                                vaddr = kmap_high_l1_vipt(page, &saved_pte);
+                                vaddr = kmap_atomic(page);
                                op(vaddr + offset, len, dir);
-                                kunmap_high_l1_vipt(page, saved_pte);
+                                kunmap_atomic(vaddr);
                        }
                } else {
                        vaddr = page_address(page) + offset;
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 391ffae7509..c29f2839f1d 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -10,6 +10,7 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/pagemap.h>
+#include <linux/highmem.h>
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
@@ -180,10 +181,10 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
                        kunmap_high(page);
                } else if (cache_is_vipt()) {
-                        pte_t saved_pte;
+                        /* unmapped pages might still be cached */
-                        addr = kmap_high_l1_vipt(page, &saved_pte);
+                        addr = kmap_atomic(page);
                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
-                        kunmap_high_l1_vipt(page, saved_pte);
+                        kunmap_atomic(addr);
                }
        }
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index c435fd9e1da..807c0573abb 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -140,90 +140,3 @@ struct page *kmap_atomic_to_page(const void *ptr)
        pte = TOP_PTE(vaddr);
        return pte_page(*pte);
 }
-#ifdef CONFIG_CPU_CACHE_VIPT
-#include <linux/percpu.h>
-/*
- * The VIVT cache of a highmem page is always flushed before the page
- * is unmapped. Hence unmapped highmem pages need no cache maintenance
- * in that case.
- *
- * However unmapped pages may still be cached with a VIPT cache, and
- * it is not possible to perform cache maintenance on them using physical
- * addresses unfortunately.  So we have no choice but to set up a temporary
- * virtual mapping for that purpose.
- *
- * Yet this VIPT cache maintenance may be triggered from DMA support
- * functions which are possibly called from interrupt context. As we don't
- * want to keep interrupt disabled all the time when such maintenance is
- * taking place, we therefore allow for some reentrancy by preserving and
- * restoring the previous fixmap entry before the interrupted context is
- * resumed.  If the reentrancy depth is 0 then there is no need to restore
- * the previous fixmap, and leaving the current one in place allow it to
- * be reused the next time without a TLB flush (common with DMA).
- */
-static DEFINE_PER_CPU(int, kmap_high_l1_vipt_depth);
-void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte)
-{
-        unsigned int idx, cpu;
-        int *depth;
-        unsigned long vaddr, flags;
-        pte_t pte, *ptep;
-        if (!in_interrupt())
-                preempt_disable();
-        cpu = smp_processor_id();
-        depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
-        idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
-        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-        ptep = TOP_PTE(vaddr);
-        pte = mk_pte(page, kmap_prot);
-        raw_local_irq_save(flags);
-        (*depth)++;
-        if (pte_val(*ptep) == pte_val(pte)) {
-                *saved_pte = pte;
-        } else {
-                *saved_pte = *ptep;
-                set_pte_ext(ptep, pte, 0);
-                local_flush_tlb_kernel_page(vaddr);
-        }
-        raw_local_irq_restore(flags);
-        return (void *)vaddr;
-}
-void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte)
-{
-        unsigned int idx, cpu = smp_processor_id();
-        int *depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
-        unsigned long vaddr, flags;
-        pte_t pte, *ptep;
-        idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
-        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-        ptep = TOP_PTE(vaddr);
-        pte = mk_pte(page, kmap_prot);
-        BUG_ON(pte_val(*ptep) != pte_val(pte));
-        BUG_ON(*depth <= 0);
-        raw_local_irq_save(flags);
-        (*depth)--;
-        if (*depth != 0 && pte_val(pte) != pte_val(saved_pte)) {
-                set_pte_ext(ptep, saved_pte, 0);
-                local_flush_tlb_kernel_page(vaddr);
-        }
-        raw_local_irq_restore(flags);
-        if (!in_interrupt())
-                preempt_enable();
-}
-#endif  /* CONFIG_CPU_CACHE_VIPT */
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7d63beaf974..b795afd0a2c 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -61,17 +61,27 @@
        .endm
 /*
- * cache_line_size - get the cache line size from the CSIDR register
+ * dcache_line_size - get the minimum D-cache line size from the CTR register
- * (available on ARMv7+). It assumes that the CSSR register was configured
+ * on ARMv7.
- * to access the L1 data cache CSIDR.
 */
        .macro  dcache_line_size, reg, tmp
-        mrc     p15, 1, \tmp, c0, c0, 0         @ read CSIDR
+        mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
-        and     \tmp, \tmp, #7                  @ cache line size encoding
+        lsr     \tmp, \tmp, #16
-        mov     \reg, #16                       @ size offset
+        and     \tmp, \tmp, #0xf                @ cache line size encoding
+        mov     \reg, #4                        @ bytes per word
        mov     \reg, \reg, lsl \tmp            @ actual cache line size
        .endm
+/*
+ * icache_line_size - get the minimum I-cache line size from the CTR register
+ * on ARMv7.
+ */
+        .macro  icache_line_size, reg, tmp
+        mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
+        and     \tmp, \tmp, #0xf                @ cache line size encoding
+        mov     \reg, #4                        @ bytes per word
+        mov     \reg, \reg, lsl \tmp            @ actual cache line size
+        .endm
 /*
 * Sanity check the PTE configuration for the code below - which makes
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 155fe43a672..8722a136f3a 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/err.h>
 #include <plat/common.h>
 #include <plat/board.h>
@@ -164,7 +165,7 @@ static int __init omap_init_clocksource_32k(void)
                        return -ENODEV;
                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
-                if (sync_32k_ick)
+                if (!IS_ERR(sync_32k_ick))
                        clk_enable(sync_32k_ick);
                clocksource_32k.mult = clocksource_hz2mult(32768,
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e2c8eebe6b3..74dac419d32 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -166,7 +166,7 @@ static void __init omap_detect_sram(void)
                     cpu_is_omap1710())
                        omap_sram_size = 0x4000;        /* 16K */
                else if (cpu_is_omap1611())
-                        omap_sram_size = 0x3e800;       /* 250K */
+                        omap_sram_size = SZ_256K;
                else {
                        printk(KERN_ERR "Could not detect SRAM size\n");
                        omap_sram_size = 0x4000;
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 5a27b1b538f..eb105e61c74 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C24XX
        default y
        select NO_IOPORT
        select ARCH_REQUIRE_GPIOLIB
-        select S3C_DEVICE_NAND
+        select S3C_DEV_NAND
        select S3C_GPIO_CFG_S3C24XX
        help
          Base platform code for any Samsung S3C24XX device
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 55590a4d87c..2fea897ebeb 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Thu Sep 9 22:43:01 2010
+# Last update: Sun Dec 12 23:24:27 2010
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -2321,7 +2321,7 @@ mx31txtr		MACH_MX31TXTR		MX31TXTR		2332
 u380                    MACH_U380               U380                    2333
 oamp3_hualu             MACH_HUALU_BOARD        HUALU_BOARD             2334
 npcmx50                 MACH_NPCMX50            NPCMX50                 2335
-mx51_lange51            MACH_MX51_LANGE51       MX51_LANGE51            2336
+mx51_efikamx            MACH_MX51_EFIKAMX       MX51_EFIKAMX            2336
 mx51_lange52            MACH_MX51_LANGE52       MX51_LANGE52            2337
 riom                    MACH_RIOM               RIOM                    2338
 comcas                  MACH_COMCAS             COMCAS                  2339
@@ -2355,7 +2355,7 @@ at91sam9263cs		MACH_AT91SAM9263CS	AT91SAM9263CS		2366
 csb732                  MACH_CSB732             CSB732                  2367
 u8500                   MACH_U8500              U8500                   2368
 huqiu                   MACH_HUQIU              HUQIU                   2369
-mx51_kunlun             MACH_MX51_KUNLUN        MX51_KUNLUN             2370
+mx51_efikasb            MACH_MX51_EFIKASB       MX51_EFIKASB            2370
 pmt1g                   MACH_PMT1G              PMT1G                   2371
 htcelf                  MACH_HTCELF             HTCELF                  2372
 armadillo420            MACH_ARMADILLO420       ARMADILLO420            2373
@@ -2971,7 +2971,7 @@ premierwave_en		MACH_PREMIERWAVE_EN	PREMIERWAVE_EN		2985
 wasabi                  MACH_WASABI             WASABI                  2986
 vivow                   MACH_VIVOW              VIVOW                   2987
 mx50_rdp                MACH_MX50_RDP           MX50_RDP                2988
-universal               MACH_UNIVERSAL          UNIVERSAL               2989
+universal_c210          MACH_UNIVERSAL_C210     UNIVERSAL_C210          2989
 real6410                MACH_REAL6410           REAL6410                2990
 spx_sakura              MACH_SPX_SAKURA         SPX_SAKURA              2991
 ij3k_2440               MACH_IJ3K_2440          IJ3K_2440               2992
@@ -3044,3 +3044,178 @@ harvest_desoto		MACH_HARVEST_DESOTO	HARVEST_DESOTO		3059
 msm8x60_qrdc            MACH_MSM8X60_QRDC       MSM8X60_QRDC            3060
 spear900                MACH_SPEAR900           SPEAR900                3061
 pcontrol_g20            MACH_PCONTROL_G20       PCONTROL_G20            3062
+rdstor                  MACH_RDSTOR             RDSTOR                  3063
+usdloader               MACH_USDLOADER          USDLOADER               3064
+tsoploader              MACH_TSOPLOADER         TSOPLOADER              3065
+kronos                  MACH_KRONOS             KRONOS                  3066
+ffcore                  MACH_FFCORE             FFCORE                  3067
+mone                    MACH_MONE               MONE                    3068
+unit2s                  MACH_UNIT2S             UNIT2S                  3069
+acer_a5                 MACH_ACER_A5            ACER_A5                 3070
+etherpro_isp            MACH_ETHERPRO_ISP       ETHERPRO_ISP            3071
+stretchs7000            MACH_STRETCHS7000       STRETCHS7000            3072
+p87_smartsim            MACH_P87_SMARTSIM       P87_SMARTSIM            3073
+tulip                   MACH_TULIP              TULIP                   3074
+sunflower               MACH_SUNFLOWER          SUNFLOWER               3075
+rib                     MACH_RIB                RIB                     3076
+clod                    MACH_CLOD               CLOD                    3077
+rump                    MACH_RUMP               RUMP                    3078
+tenderloin              MACH_TENDERLOIN         TENDERLOIN              3079
+shortloin               MACH_SHORTLOIN          SHORTLOIN               3080
+crespo                  MACH_CRESPO             CRESPO                  3081
+antares                 MACH_ANTARES            ANTARES                 3082
+wb40n                   MACH_WB40N              WB40N                   3083
+herring                 MACH_HERRING            HERRING                 3084
+naxy400                 MACH_NAXY400            NAXY400                 3085
+naxy1200                MACH_NAXY1200           NAXY1200                3086
+vpr200                  MACH_VPR200             VPR200                  3087
+bug20                   MACH_BUG20              BUG20                   3088
+goflexnet               MACH_GOFLEXNET          GOFLEXNET               3089
+torbreck                MACH_TORBRECK           TORBRECK                3090
+saarb_mg1               MACH_SAARB_MG1          SAARB_MG1               3091
+callisto                MACH_CALLISTO           CALLISTO                3092
+multhsu                 MACH_MULTHSU            MULTHSU                 3093
+saluda                  MACH_SALUDA             SALUDA                  3094
+pemp_omap3_apollo       MACH_PEMP_OMAP3_APOLLO  PEMP_OMAP3_APOLLO       3095
+vc0718                  MACH_VC0718             VC0718                  3096
+mvblx                   MACH_MVBLX              MVBLX                   3097
+inhand_apeiron          MACH_INHAND_APEIRON     INHAND_APEIRON          3098
+inhand_fury             MACH_INHAND_FURY        INHAND_FURY             3099
+inhand_siren            MACH_INHAND_SIREN       INHAND_SIREN            3100
+hdnvp                   MACH_HDNVP              HDNVP                   3101
+softwinner              MACH_SOFTWINNER         SOFTWINNER              3102
+prima2_evb              MACH_PRIMA2_EVB         PRIMA2_EVB              3103
+nas6210                 MACH_NAS6210            NAS6210                 3104
+unisdev                 MACH_UNISDEV            UNISDEV                 3105
+sbca11                  MACH_SBCA11             SBCA11                  3106
+saga                    MACH_SAGA               SAGA                    3107
+ns_k330                 MACH_NS_K330            NS_K330                 3108
+tanna                   MACH_TANNA              TANNA                   3109
+imate8502               MACH_IMATE8502          IMATE8502               3110
+aspen                   MACH_ASPEN              ASPEN                   3111
+daintree_cwac           MACH_DAINTREE_CWAC      DAINTREE_CWAC           3112
+zmx25                   MACH_ZMX25              ZMX25                   3113
+maple1                  MACH_MAPLE1             MAPLE1                  3114
+qsd8x72_surf            MACH_QSD8X72_SURF       QSD8X72_SURF            3115
+qsd8x72_ffa             MACH_QSD8X72_FFA        QSD8X72_FFA             3116
+abilene                 MACH_ABILENE            ABILENE                 3117
+eigen_ttr               MACH_EIGEN_TTR          EIGEN_TTR               3118
+iomega_ix2_200          MACH_IOMEGA_IX2_200     IOMEGA_IX2_200          3119
+coretec_vcx7400         MACH_CORETEC_VCX7400    CORETEC_VCX7400         3120
+santiago                MACH_SANTIAGO           SANTIAGO                3121
+mx257sol                MACH_MX257SOL           MX257SOL                3122
+strasbourg              MACH_STRASBOURG         STRASBOURG              3123
+msm8x60_fluid           MACH_MSM8X60_FLUID      MSM8X60_FLUID           3124
+smartqv5                MACH_SMARTQV5           SMARTQV5                3125
+smartqv3                MACH_SMARTQV3           SMARTQV3                3126
+smartqv7                MACH_SMARTQV7           SMARTQV7                3127
+paz00                   MACH_PAZ00              PAZ00                   3128
+acmenetusfoxg20         MACH_ACMENETUSFOXG20    ACMENETUSFOXG20         3129
+htcwillow               MACH_HTCWILLOW          HTCWILLOW               3130
+fwbd_0404               MACH_FWBD_0404          FWBD_0404               3131
+hdgu                    MACH_HDGU               HDGU                    3132
+pyramid                 MACH_PYRAMID            PYRAMID                 3133
+epiphan                 MACH_EPIPHAN            EPIPHAN                 3134
+omap_bender             MACH_OMAP_BENDER        OMAP_BENDER             3135
+gurnard                 MACH_GURNARD            GURNARD                 3136
+gtl_it5100              MACH_GTL_IT5100         GTL_IT5100              3137
+bcm2708                 MACH_BCM2708            BCM2708                 3138
+mx51_ggc                MACH_MX51_GGC           MX51_GGC                3139
+sharespace              MACH_SHARESPACE         SHARESPACE              3140
+haba_knx_explorer       MACH_HABA_KNX_EXPLORER  HABA_KNX_EXPLORER       3141
+simtec_kirkmod          MACH_SIMTEC_KIRKMOD     SIMTEC_KIRKMOD          3142
+crux                    MACH_CRUX               CRUX                    3143
+mx51_bravo              MACH_MX51_BRAVO         MX51_BRAVO              3144
+charon                  MACH_CHARON             CHARON                  3145
+picocom3                MACH_PICOCOM3           PICOCOM3                3146
+picocom4                MACH_PICOCOM4           PICOCOM4                3147
+serrano                 MACH_SERRANO            SERRANO                 3148
+doubleshot              MACH_DOUBLESHOT         DOUBLESHOT              3149
+evsy                    MACH_EVSY               EVSY                    3150
+huashan                 MACH_HUASHAN            HUASHAN                 3151
+lausanne                MACH_LAUSANNE           LAUSANNE                3152
+emerald                 MACH_EMERALD            EMERALD                 3153
+tqma35                  MACH_TQMA35             TQMA35                  3154
+marvel                  MACH_MARVEL             MARVEL                  3155
+manuae                  MACH_MANUAE             MANUAE                  3156
+chacha                  MACH_CHACHA             CHACHA                  3157
+lemon                   MACH_LEMON              LEMON                   3158
+csc                     MACH_CSC                CSC                     3159
+gira_knxip_router       MACH_GIRA_KNXIP_ROUTER  GIRA_KNXIP_ROUTER       3160
+t20                     MACH_T20                T20                     3161
+hdmini                  MACH_HDMINI             HDMINI                  3162
+sciphone_g2             MACH_SCIPHONE_G2        SCIPHONE_G2             3163
+express                 MACH_EXPRESS            EXPRESS                 3164
+express_kt              MACH_EXPRESS_KT         EXPRESS_KT              3165
+maximasp                MACH_MAXIMASP           MAXIMASP                3166
+nitrogen_imx51          MACH_NITROGEN_IMX51     NITROGEN_IMX51          3167
+nitrogen_imx53          MACH_NITROGEN_IMX53     NITROGEN_IMX53          3168
+sunfire                 MACH_SUNFIRE            SUNFIRE                 3169
+arowana                 MACH_AROWANA            AROWANA                 3170
+tegra_daytona           MACH_TEGRA_DAYTONA      TEGRA_DAYTONA           3171
+tegra_swordfish         MACH_TEGRA_SWORDFISH    TEGRA_SWORDFISH         3172
+edison                  MACH_EDISON             EDISON                  3173
+svp8500v1               MACH_SVP8500V1          SVP8500V1               3174
+svp8500v2               MACH_SVP8500V2          SVP8500V2               3175
+svp5500                 MACH_SVP5500            SVP5500                 3176
+b5500                   MACH_B5500              B5500                   3177
+s5500                   MACH_S5500              S5500                   3178
+icon                    MACH_ICON               ICON                    3179
+elephant                MACH_ELEPHANT           ELEPHANT                3180
+msm8x60_fusion          MACH_MSM8X60_FUSION     MSM8X60_FUSION          3181
+shooter                 MACH_SHOOTER            SHOOTER                 3182
+spade_lte               MACH_SPADE_LTE          SPADE_LTE               3183
+philhwani               MACH_PHILHWANI          PHILHWANI               3184
+gsncomm                 MACH_GSNCOMM            GSNCOMM                 3185
+strasbourg_a2           MACH_STRASBOURG_A2      STRASBOURG_A2           3186
+mmm                     MACH_MMM                MMM                     3187
+davinci_dm365_bv        MACH_DAVINCI_DM365_BV   DAVINCI_DM365_BV        3188
+ag5evm                  MACH_AG5EVM             AG5EVM                  3189
+sc575plc                MACH_SC575PLC           SC575PLC                3190
+sc575hmi                MACH_SC575IPC           SC575IPC                3191
+omap3_tdm3730           MACH_OMAP3_TDM3730      OMAP3_TDM3730           3192
+g7                      MACH_G7                 G7                      3193
+top9000_eval            MACH_TOP9000_EVAL       TOP9000_EVAL            3194
+top9000_su              MACH_TOP9000_SU         TOP9000_SU              3195
+utm300                  MACH_UTM300             UTM300                  3196
+tsunagi                 MACH_TSUNAGI            TSUNAGI                 3197
+ts75xx                  MACH_TS75XX             TS75XX                  3198
+msm8x60_fusn_ffa        MACH_MSM8X60_FUSN_FFA   MSM8X60_FUSN_FFA        3199
+ts47xx                  MACH_TS47XX             TS47XX                  3200
+da850_k5                MACH_DA850_K5           DA850_K5                3201
+ax502                   MACH_AX502              AX502                   3202
+igep0032                MACH_IGEP0032           IGEP0032                3203
+antero                  MACH_ANTERO             ANTERO                  3204
+synergy                 MACH_SYNERGY            SYNERGY                 3205
+ics_if_voip             MACH_ICS_IF_VOIP        ICS_IF_VOIP             3206
+wlf_cragg_6410          MACH_WLF_CRAGG_6410     WLF_CRAGG_6410          3207
+punica                  MACH_PUNICA             PUNICA                  3208
+sbc_nt250               MACH_SBC_NT250          SBC_NT250               3209
+mx27_wmultra            MACH_MX27_WMULTRA       MX27_WMULTRA            3210
+mackerel                MACH_MACKEREL           MACKEREL                3211
+fa9x27                  MACH_FA9X27             FA9X27                  3213
+ns2816tb                MACH_NS2816TB           NS2816TB                3214
+ns2816_ntpad            MACH_NS2816_NTPAD       NS2816_NTPAD            3215
+ns2816_ntnb             MACH_NS2816_NTNB        NS2816_NTNB             3216
+kaen                    MACH_KAEN               KAEN                    3217
+nv1000                  MACH_NV1000             NV1000                  3218
+nuc950ts                MACH_NUC950TS           NUC950TS                3219
+nokia_rm680             MACH_NOKIA_RM680        NOKIA_RM680             3220
+ast2200                 MACH_AST2200            AST2200                 3221
+lead                    MACH_LEAD               LEAD                    3222
+unino1                  MACH_UNINO1             UNINO1                  3223
+greeco                  MACH_GREECO             GREECO                  3224
+verdi                   MACH_VERDI              VERDI                   3225
+dm6446_adbox            MACH_DM6446_ADBOX       DM6446_ADBOX            3226
+quad_salsa              MACH_QUAD_SALSA         QUAD_SALSA              3227
+abb_gma_1_1             MACH_ABB_GMA_1_1        ABB_GMA_1_1             3228
+svcid                   MACH_SVCID              SVCID                   3229
+msm8960_sim             MACH_MSM8960_SIM        MSM8960_SIM             3230
+msm8960_rumi3           MACH_MSM8960_RUMI3      MSM8960_RUMI3           3231
+icon_g                  MACH_ICON_G             ICON_G                  3232
+mb3                     MACH_MB3                MB3                     3233
+gsia18s                 MACH_GSIA18S            GSIA18S                 3234
+pivicc                  MACH_PIVICC             PIVICC                  3235
+pcm048                  MACH_PCM048             PCM048                  3236
+dds                     MACH_DDS                DDS                     3237
+chalten_xa1             MACH_CHALTEN_XA1        CHALTEN_XA1             3238