diff options
Diffstat (limited to 'arch/arm/plat-samsung/include/plat/regs-fb.h')
-rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-fb.h | 366 |
1 files changed, 366 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h new file mode 100644 index 00000000000..0ef806e5034 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h | |||
@@ -0,0 +1,366 @@ | |||
1 | /* arch/arm/plat-samsung/include/plat/regs-fb.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C Platform - new-style framebuffer register definitions | ||
9 | * | ||
10 | * This is the register set for the new style framebuffer interface | ||
11 | * found from the S3C2443 onwards into the S3C2416, S3C2450 and the | ||
12 | * S3C64XX series such as the S3C6400 and S3C6410. | ||
13 | * | ||
14 | * The file does not contain the cpu specific items which are based on | ||
15 | * whichever architecture is selected, it only contains the core of the | ||
16 | * register set. See <mach/regs-fb.h> to get the specifics. | ||
17 | * | ||
18 | * Note, we changed to using regs-fb.h as it avoids any clashes with | ||
19 | * the original regs-lcd.h so out of the way of regs-lcd.h as well as | ||
20 | * indicating the newer block is much more than just an LCD interface. | ||
21 | * | ||
22 | * This program is free software; you can redistribute it and/or modify | ||
23 | * it under the terms of the GNU General Public License version 2 as | ||
24 | * published by the Free Software Foundation. | ||
25 | */ | ||
26 | |||
27 | /* Please do not include this file directly, use <mach/regs-fb.h> to | ||
28 | * ensure all the localised SoC support is included as necessary. | ||
29 | */ | ||
30 | |||
31 | /* VIDCON0 */ | ||
32 | |||
33 | #define VIDCON0 (0x00) | ||
34 | #define VIDCON0_INTERLACE (1 << 29) | ||
35 | #define VIDCON0_VIDOUT_MASK (0x3 << 26) | ||
36 | #define VIDCON0_VIDOUT_SHIFT (26) | ||
37 | #define VIDCON0_VIDOUT_RGB (0x0 << 26) | ||
38 | #define VIDCON0_VIDOUT_TV (0x1 << 26) | ||
39 | #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) | ||
40 | #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) | ||
41 | |||
42 | #define VIDCON0_L1_DATA_MASK (0x7 << 23) | ||
43 | #define VIDCON0_L1_DATA_SHIFT (23) | ||
44 | #define VIDCON0_L1_DATA_16BPP (0x0 << 23) | ||
45 | #define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) | ||
46 | #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) | ||
47 | #define VIDCON0_L1_DATA_24BPP (0x3 << 23) | ||
48 | #define VIDCON0_L1_DATA_18BPP (0x4 << 23) | ||
49 | #define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) | ||
50 | |||
51 | #define VIDCON0_L0_DATA_MASK (0x7 << 20) | ||
52 | #define VIDCON0_L0_DATA_SHIFT (20) | ||
53 | #define VIDCON0_L0_DATA_16BPP (0x0 << 20) | ||
54 | #define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) | ||
55 | #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) | ||
56 | #define VIDCON0_L0_DATA_24BPP (0x3 << 20) | ||
57 | #define VIDCON0_L0_DATA_18BPP (0x4 << 20) | ||
58 | #define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) | ||
59 | |||
60 | #define VIDCON0_PNRMODE_MASK (0x3 << 17) | ||
61 | #define VIDCON0_PNRMODE_SHIFT (17) | ||
62 | #define VIDCON0_PNRMODE_RGB (0x0 << 17) | ||
63 | #define VIDCON0_PNRMODE_BGR (0x1 << 17) | ||
64 | #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) | ||
65 | #define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17) | ||
66 | |||
67 | #define VIDCON0_CLKVALUP (1 << 16) | ||
68 | #define VIDCON0_CLKVAL_F_MASK (0xff << 6) | ||
69 | #define VIDCON0_CLKVAL_F_SHIFT (6) | ||
70 | #define VIDCON0_CLKVAL_F_LIMIT (0xff) | ||
71 | #define VIDCON0_CLKVAL_F(_x) ((_x) << 6) | ||
72 | #define VIDCON0_VLCKFREE (1 << 5) | ||
73 | #define VIDCON0_CLKDIR (1 << 4) | ||
74 | |||
75 | #define VIDCON0_CLKSEL_MASK (0x3 << 2) | ||
76 | #define VIDCON0_CLKSEL_SHIFT (2) | ||
77 | #define VIDCON0_CLKSEL_HCLK (0x0 << 2) | ||
78 | #define VIDCON0_CLKSEL_LCD (0x1 << 2) | ||
79 | #define VIDCON0_CLKSEL_27M (0x3 << 2) | ||
80 | |||
81 | #define VIDCON0_ENVID (1 << 1) | ||
82 | #define VIDCON0_ENVID_F (1 << 0) | ||
83 | |||
84 | #define VIDCON1 (0x04) | ||
85 | #define VIDCON1_LINECNT_MASK (0x7ff << 16) | ||
86 | #define VIDCON1_LINECNT_SHIFT (16) | ||
87 | #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) | ||
88 | #define VIDCON1_VSTATUS_MASK (0x3 << 13) | ||
89 | #define VIDCON1_VSTATUS_SHIFT (13) | ||
90 | #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) | ||
91 | #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) | ||
92 | #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) | ||
93 | #define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) | ||
94 | |||
95 | #define VIDCON1_INV_VCLK (1 << 7) | ||
96 | #define VIDCON1_INV_HSYNC (1 << 6) | ||
97 | #define VIDCON1_INV_VSYNC (1 << 5) | ||
98 | #define VIDCON1_INV_VDEN (1 << 4) | ||
99 | |||
100 | /* VIDCON2 */ | ||
101 | |||
102 | #define VIDCON2 (0x08) | ||
103 | #define VIDCON2_EN601 (1 << 23) | ||
104 | #define VIDCON2_TVFMTSEL_SW (1 << 14) | ||
105 | |||
106 | #define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) | ||
107 | #define VIDCON2_TVFMTSEL1_SHIFT (12) | ||
108 | #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) | ||
109 | #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) | ||
110 | #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) | ||
111 | |||
112 | #define VIDCON2_ORGYCbCr (1 << 8) | ||
113 | #define VIDCON2_YUVORDCrCb (1 << 7) | ||
114 | |||
115 | /* VIDTCON0 */ | ||
116 | |||
117 | #define VIDTCON0_VBPDE_MASK (0xff << 24) | ||
118 | #define VIDTCON0_VBPDE_SHIFT (24) | ||
119 | #define VIDTCON0_VBPDE_LIMIT (0xff) | ||
120 | #define VIDTCON0_VBPDE(_x) ((_x) << 24) | ||
121 | |||
122 | #define VIDTCON0_VBPD_MASK (0xff << 16) | ||
123 | #define VIDTCON0_VBPD_SHIFT (16) | ||
124 | #define VIDTCON0_VBPD_LIMIT (0xff) | ||
125 | #define VIDTCON0_VBPD(_x) ((_x) << 16) | ||
126 | |||
127 | #define VIDTCON0_VFPD_MASK (0xff << 8) | ||
128 | #define VIDTCON0_VFPD_SHIFT (8) | ||
129 | #define VIDTCON0_VFPD_LIMIT (0xff) | ||
130 | #define VIDTCON0_VFPD(_x) ((_x) << 8) | ||
131 | |||
132 | #define VIDTCON0_VSPW_MASK (0xff << 0) | ||
133 | #define VIDTCON0_VSPW_SHIFT (0) | ||
134 | #define VIDTCON0_VSPW_LIMIT (0xff) | ||
135 | #define VIDTCON0_VSPW(_x) ((_x) << 0) | ||
136 | |||
137 | /* VIDTCON1 */ | ||
138 | |||
139 | #define VIDTCON1_VFPDE_MASK (0xff << 24) | ||
140 | #define VIDTCON1_VFPDE_SHIFT (24) | ||
141 | #define VIDTCON1_VFPDE_LIMIT (0xff) | ||
142 | #define VIDTCON1_VFPDE(_x) ((_x) << 24) | ||
143 | |||
144 | #define VIDTCON1_HBPD_MASK (0xff << 16) | ||
145 | #define VIDTCON1_HBPD_SHIFT (16) | ||
146 | #define VIDTCON1_HBPD_LIMIT (0xff) | ||
147 | #define VIDTCON1_HBPD(_x) ((_x) << 16) | ||
148 | |||
149 | #define VIDTCON1_HFPD_MASK (0xff << 8) | ||
150 | #define VIDTCON1_HFPD_SHIFT (8) | ||
151 | #define VIDTCON1_HFPD_LIMIT (0xff) | ||
152 | #define VIDTCON1_HFPD(_x) ((_x) << 8) | ||
153 | |||
154 | #define VIDTCON1_HSPW_MASK (0xff << 0) | ||
155 | #define VIDTCON1_HSPW_SHIFT (0) | ||
156 | #define VIDTCON1_HSPW_LIMIT (0xff) | ||
157 | #define VIDTCON1_HSPW(_x) ((_x) << 0) | ||
158 | |||
159 | #define VIDTCON2 (0x18) | ||
160 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) | ||
161 | #define VIDTCON2_LINEVAL_SHIFT (11) | ||
162 | #define VIDTCON2_LINEVAL_LIMIT (0x7ff) | ||
163 | #define VIDTCON2_LINEVAL(_x) ((_x) << 11) | ||
164 | |||
165 | #define VIDTCON2_HOZVAL_MASK (0x7ff << 0) | ||
166 | #define VIDTCON2_HOZVAL_SHIFT (0) | ||
167 | #define VIDTCON2_HOZVAL_LIMIT (0x7ff) | ||
168 | #define VIDTCON2_HOZVAL(_x) ((_x) << 0) | ||
169 | |||
170 | /* WINCONx */ | ||
171 | |||
172 | |||
173 | #define WINCONx_BITSWP (1 << 18) | ||
174 | #define WINCONx_BYTSWP (1 << 17) | ||
175 | #define WINCONx_HAWSWP (1 << 16) | ||
176 | #define WINCONx_BURSTLEN_MASK (0x3 << 9) | ||
177 | #define WINCONx_BURSTLEN_SHIFT (9) | ||
178 | #define WINCONx_BURSTLEN_16WORD (0x0 << 9) | ||
179 | #define WINCONx_BURSTLEN_8WORD (0x1 << 9) | ||
180 | #define WINCONx_BURSTLEN_4WORD (0x2 << 9) | ||
181 | |||
182 | #define WINCONx_ENWIN (1 << 0) | ||
183 | #define WINCON0_BPPMODE_MASK (0xf << 2) | ||
184 | #define WINCON0_BPPMODE_SHIFT (2) | ||
185 | #define WINCON0_BPPMODE_1BPP (0x0 << 2) | ||
186 | #define WINCON0_BPPMODE_2BPP (0x1 << 2) | ||
187 | #define WINCON0_BPPMODE_4BPP (0x2 << 2) | ||
188 | #define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2) | ||
189 | #define WINCON0_BPPMODE_16BPP_565 (0x5 << 2) | ||
190 | #define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2) | ||
191 | #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) | ||
192 | #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) | ||
193 | |||
194 | #define WINCON1_BLD_PIX (1 << 6) | ||
195 | |||
196 | #define WINCON1_ALPHA_SEL (1 << 1) | ||
197 | #define WINCON1_BPPMODE_MASK (0xf << 2) | ||
198 | #define WINCON1_BPPMODE_SHIFT (2) | ||
199 | #define WINCON1_BPPMODE_1BPP (0x0 << 2) | ||
200 | #define WINCON1_BPPMODE_2BPP (0x1 << 2) | ||
201 | #define WINCON1_BPPMODE_4BPP (0x2 << 2) | ||
202 | #define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2) | ||
203 | #define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2) | ||
204 | #define WINCON1_BPPMODE_16BPP_565 (0x5 << 2) | ||
205 | #define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
206 | #define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
207 | #define WINCON1_BPPMODE_18BPP_666 (0x8 << 2) | ||
208 | #define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
209 | #define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2) | ||
210 | #define WINCON1_BPPMODE_24BPP_888 (0xb << 2) | ||
211 | #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) | ||
212 | #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) | ||
213 | #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) | ||
214 | |||
215 | |||
216 | #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) | ||
217 | #define VIDOSDxA_TOPLEFT_X_SHIFT (11) | ||
218 | #define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) | ||
219 | #define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) | ||
220 | |||
221 | #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) | ||
222 | #define VIDOSDxA_TOPLEFT_Y_SHIFT (0) | ||
223 | #define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) | ||
224 | #define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) | ||
225 | |||
226 | #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) | ||
227 | #define VIDOSDxB_BOTRIGHT_X_SHIFT (11) | ||
228 | #define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) | ||
229 | #define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) | ||
230 | |||
231 | #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) | ||
232 | #define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) | ||
233 | #define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) | ||
234 | #define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) | ||
235 | |||
236 | /* For VIDOSD[1..4]C */ | ||
237 | #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) | ||
238 | #define VIDISD14C_ALPHA0_G_MASK (0xf << 16) | ||
239 | #define VIDISD14C_ALPHA0_G_SHIFT (16) | ||
240 | #define VIDISD14C_ALPHA0_G_LIMIT (0xf) | ||
241 | #define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) | ||
242 | #define VIDISD14C_ALPHA0_B_MASK (0xf << 12) | ||
243 | #define VIDISD14C_ALPHA0_B_SHIFT (12) | ||
244 | #define VIDISD14C_ALPHA0_B_LIMIT (0xf) | ||
245 | #define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) | ||
246 | #define VIDISD14C_ALPHA1_R_MASK (0xf << 8) | ||
247 | #define VIDISD14C_ALPHA1_R_SHIFT (8) | ||
248 | #define VIDISD14C_ALPHA1_R_LIMIT (0xf) | ||
249 | #define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) | ||
250 | #define VIDISD14C_ALPHA1_G_MASK (0xf << 4) | ||
251 | #define VIDISD14C_ALPHA1_G_SHIFT (4) | ||
252 | #define VIDISD14C_ALPHA1_G_LIMIT (0xf) | ||
253 | #define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) | ||
254 | #define VIDISD14C_ALPHA1_B_MASK (0xf << 0) | ||
255 | #define VIDISD14C_ALPHA1_B_SHIFT (0) | ||
256 | #define VIDISD14C_ALPHA1_B_LIMIT (0xf) | ||
257 | #define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) | ||
258 | |||
259 | /* Video buffer addresses */ | ||
260 | #define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) | ||
261 | #define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) | ||
262 | #define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) | ||
263 | #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) | ||
264 | #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) | ||
265 | |||
266 | #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) | ||
267 | #define VIDW_BUF_SIZE_OFFSET_SHIFT (13) | ||
268 | #define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) | ||
269 | #define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) | ||
270 | |||
271 | #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) | ||
272 | #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) | ||
273 | #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) | ||
274 | #define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) | ||
275 | |||
276 | /* Interrupt controls and status */ | ||
277 | |||
278 | #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) | ||
279 | #define VIDINTCON0_FIFOINTERVAL_SHIFT (20) | ||
280 | #define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) | ||
281 | #define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) | ||
282 | |||
283 | #define VIDINTCON0_INT_SYSMAINCON (1 << 19) | ||
284 | #define VIDINTCON0_INT_SYSSUBCON (1 << 18) | ||
285 | #define VIDINTCON0_INT_I80IFDONE (1 << 17) | ||
286 | |||
287 | #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) | ||
288 | #define VIDINTCON0_FRAMESEL0_SHIFT (15) | ||
289 | #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) | ||
290 | #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) | ||
291 | #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) | ||
292 | #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) | ||
293 | |||
294 | #define VIDINTCON0_FRAMESEL1 (1 << 14) | ||
295 | #define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14) | ||
296 | #define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14) | ||
297 | #define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14) | ||
298 | #define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14) | ||
299 | |||
300 | #define VIDINTCON0_INT_FRAME (1 << 12) | ||
301 | #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) | ||
302 | #define VIDINTCON0_FIFIOSEL_SHIFT (5) | ||
303 | #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) | ||
304 | #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) | ||
305 | |||
306 | #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) | ||
307 | #define VIDINTCON0_FIFOLEVEL_SHIFT (2) | ||
308 | #define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) | ||
309 | #define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) | ||
310 | #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) | ||
311 | #define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2) | ||
312 | #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) | ||
313 | |||
314 | #define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) | ||
315 | #define VIDINTCON0_INT_FIFO_SHIFT (0) | ||
316 | #define VIDINTCON0_INT_ENABLE (1 << 0) | ||
317 | |||
318 | #define VIDINTCON1 (0x134) | ||
319 | #define VIDINTCON1_INT_I180 (1 << 2) | ||
320 | #define VIDINTCON1_INT_FRAME (1 << 1) | ||
321 | #define VIDINTCON1_INT_FIFO (1 << 0) | ||
322 | |||
323 | /* Window colour-key control registers */ | ||
324 | |||
325 | #define WxKEYCON0_KEYBL_EN (1 << 26) | ||
326 | #define WxKEYCON0_KEYEN_F (1 << 25) | ||
327 | #define WxKEYCON0_DIRCON (1 << 24) | ||
328 | #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) | ||
329 | #define WxKEYCON0_COMPKEY_SHIFT (0) | ||
330 | #define WxKEYCON0_COMPKEY_LIMIT (0xffffff) | ||
331 | #define WxKEYCON0_COMPKEY(_x) ((_x) << 0) | ||
332 | #define WxKEYCON1_COLVAL_MASK (0xffffff << 0) | ||
333 | #define WxKEYCON1_COLVAL_SHIFT (0) | ||
334 | #define WxKEYCON1_COLVAL_LIMIT (0xffffff) | ||
335 | #define WxKEYCON1_COLVAL(_x) ((_x) << 0) | ||
336 | |||
337 | |||
338 | /* Window blanking (MAP) */ | ||
339 | |||
340 | #define WINxMAP_MAP (1 << 24) | ||
341 | #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) | ||
342 | #define WINxMAP_MAP_COLOUR_SHIFT (0) | ||
343 | #define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) | ||
344 | #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) | ||
345 | |||
346 | #define WPALCON_PAL_UPDATE (1 << 9) | ||
347 | #define WPALCON_W1PAL_MASK (0x7 << 3) | ||
348 | #define WPALCON_W1PAL_SHIFT (3) | ||
349 | #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) | ||
350 | #define WPALCON_W1PAL_24BPP (0x1 << 3) | ||
351 | #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) | ||
352 | #define WPALCON_W1PAL_18BPP_A665 (0x3 << 3) | ||
353 | #define WPALCON_W1PAL_18BPP (0x4 << 3) | ||
354 | #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) | ||
355 | #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) | ||
356 | |||
357 | #define WPALCON_W0PAL_MASK (0x7 << 0) | ||
358 | #define WPALCON_W0PAL_SHIFT (0) | ||
359 | #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) | ||
360 | #define WPALCON_W0PAL_24BPP (0x1 << 0) | ||
361 | #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) | ||
362 | #define WPALCON_W0PAL_18BPP_A665 (0x3 << 0) | ||
363 | #define WPALCON_W0PAL_18BPP (0x4 << 0) | ||
364 | #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) | ||
365 | #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) | ||
366 | |||